diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 52c8c5cd5e19958c99e7f45e2fce23baee1ee6a6..e619ec2ef2c9d915839f7a714ccd5ac1fd82bc88 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -56,7 +56,7 @@ end mms_unb2_fpga_sens;
architecture str of mms_unb2_fpga_sens is
- constant c_sens_nof_result : natural := 1; --
+ constant c_sens_nof_result : natural := 1; --
constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
signal sens_err : std_logic;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 52c8c5cd5e19958c99e7f45e2fce23baee1ee6a6..e619ec2ef2c9d915839f7a714ccd5ac1fd82bc88 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -56,7 +56,7 @@ end mms_unb2_fpga_sens;
architecture str of mms_unb2_fpga_sens is
- constant c_sens_nof_result : natural := 1; --
+ constant c_sens_nof_result : natural := 1; --
constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
signal sens_err : std_logic;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 5da601d9e674d612bdffb900bbfa9d251b2c545d..9469fd2656c232a4d88c0eaa1403bedeaf1e0a2e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -1373,7 +1373,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :INTEGER; nof, width : natural) return std_logic_vector is
+ function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index fb5616eea9369da323eebec1e61c5796366634b4..40128fea21ea799361fb11525746787d64202e63 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -571,7 +571,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :NATURAL) return std_logic_vector is
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 5da601d9e674d612bdffb900bbfa9d251b2c545d..9469fd2656c232a4d88c0eaa1403bedeaf1e0a2e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -1373,7 +1373,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :INTEGER; nof, width : natural) return std_logic_vector is
+ function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index fb5616eea9369da323eebec1e61c5796366634b4..40128fea21ea799361fb11525746787d64202e63 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -571,7 +571,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :NATURAL) return std_logic_vector is
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 5da601d9e674d612bdffb900bbfa9d251b2c545d..9469fd2656c232a4d88c0eaa1403bedeaf1e0a2e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -1373,7 +1373,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :INTEGER; nof, width : natural) return std_logic_vector is
+ function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index fb5616eea9369da323eebec1e61c5796366634b4..40128fea21ea799361fb11525746787d64202e63 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -571,7 +571,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :NATURAL) return std_logic_vector is
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 5da601d9e674d612bdffb900bbfa9d251b2c545d..9469fd2656c232a4d88c0eaa1403bedeaf1e0a2e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -1373,7 +1373,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :INTEGER; nof, width : natural) return std_logic_vector is
+ function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index fb5616eea9369da323eebec1e61c5796366634b4..40128fea21ea799361fb11525746787d64202e63 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -571,7 +571,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :NATURAL) return std_logic_vector is
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
diff --git a/libraries/base/common/src/vhdl/common_field_pkg.vhd b/libraries/base/common/src/vhdl/common_field_pkg.vhd
index 1f47015ec5623b6412ac25249b054b23dbc4eea1..bdf62486d904f06895e177df6a224a5059318d45 100644
--- a/libraries/base/common/src/vhdl/common_field_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_field_pkg.vhd
@@ -331,7 +331,7 @@ package body common_field_pkg is
return v_field_arr;
end field_arr_set_mode;
- function sel_a_b(sel :BOOLEAN; a, b : t_common_field_arr) return t_common_field_arr is
+ function sel_a_b(sel :boolean; a, b : t_common_field_arr) return t_common_field_arr is
begin
if sel = true then
return a;
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 1c54724dc40c79d37f4e862f42386b829c0eef26..6a03dd4febeac90b23ead718456473be75f5d8d0 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -1679,7 +1679,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :INTEGER; nof, width : natural) return std_logic_vector is
+ function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1978,7 +1978,7 @@ package body common_pkg is
if udec >= 0.0 then
return TO_SINT(udec, w + 1, resolution_w); -- w + 1, because unsigned has no sign bit
else
- report "Negative real clipped to integer 0 : " & real'image(c_ureal) & " -- > 0" SEVERITY WARNING;
+ report "Negative real clipped to integer 0 : " & real'image(c_ureal) & " -- > 0" severity WARNING;
return 0;
end if;
end;
@@ -1994,11 +1994,11 @@ package body common_pkg is
if c_sreal <= c_max then
return c_sint;
else
- report "REAL clipped to integer max : " & real'image(c_sreal) & " -- > " & INTEGER'IMAGE(INTEGER(c_max)) SEVERITY WARNING;
+ report "REAL clipped to integer max : " & real'image(c_sreal) & " -- > " & integer'image(integer(c_max)) severity WARNING;
return integer(c_max); -- clip to max
end if;
else
- report "REAL clipped to integer min : " & real'image(c_sreal) & " -- > " & INTEGER'IMAGE(INTEGER(c_min)) SEVERITY WARNING;
+ report "REAL clipped to integer min : " & real'image(c_sreal) & " -- > " & integer'image(integer(c_min)) severity WARNING;
return integer(c_min); -- clip to min
end if;
end;
@@ -2039,11 +2039,11 @@ package body common_pkg is
assert v_floor = 0.0 report "Unexpected TO_UVEC real remainder : " & real'image(v_floor) & " /= 0.0" severity FAILURE;
return v_uvec;
else
- report "Positive real clipped to UVEC max : " & real'image(v_ureal) & " -- > " & REAL'IMAGE(c_max) SEVERITY WARNING;
+ report "Positive real clipped to UVEC max : " & real'image(v_ureal) & " -- > " & real'image(c_max) severity WARNING;
return c_uvec_max;
end if;
else
- report "Negative real clipped to UVEC 0 : " & real'image(v_ureal) & " -- > 0" SEVERITY WARNING;
+ report "Negative real clipped to UVEC 0 : " & real'image(v_ureal) & " -- > 0" severity WARNING;
return TO_UVEC(0, w);
end if;
end;
@@ -2069,11 +2069,11 @@ package body common_pkg is
if c_sreal <= c_max then
return c_svec(w - 1 downto 0);
else
- report "REAL clipped to SVEC max : " & real'image(c_sreal) & " -- > " & REAL'IMAGE(c_max) SEVERITY WARNING;
+ report "REAL clipped to SVEC max : " & real'image(c_sreal) & " -- > " & real'image(c_max) severity WARNING;
return c_svec_max; -- clip to max
end if;
else
- report "REAL clipped to SVEC min : " & real'image(c_sreal) & " -- > " & REAL'IMAGE(c_min) SEVERITY WARNING;
+ report "REAL clipped to SVEC min : " & real'image(c_sreal) & " -- > " & real'image(c_min) severity WARNING;
return c_svec_min; -- clip to min
end if;
end;
diff --git a/libraries/base/common/src/vhdl/common_str_pkg.vhd b/libraries/base/common/src/vhdl/common_str_pkg.vhd
index 68e5b65e7df3a090a345bc318ad13563e7cabf63..af8f915c7b5c3f24fbdefeb1ff28d4b0eb7bf5bd 100644
--- a/libraries/base/common/src/vhdl/common_str_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_str_pkg.vhd
@@ -178,7 +178,7 @@ package body common_str_pkg is
return v_hex;
end;
- function slv_to_hex(slv :STD_LOGIC_VECTOR) return string is
+ function slv_to_hex(slv :std_logic_vector) return string is
begin
return str_to_hex(slv_to_str(slv));
end;
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index d06e7c6f21f1145dabf6d1f655e1e471e36b6800..e466a0ad0457ab9536a42f72296b20cc5b6873ba 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -608,7 +608,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :NATURAL) return std_logic_vector is
+ function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
index 8255454db3ae872913e7bbbd25ac857c8cb4b179..69c2a55e5be3fc9d565a7d7b07f35b2e64ae2105 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
@@ -230,7 +230,7 @@ begin
v_ssn := ref_grid.ssn + 1; -- +1 to prepare start in next PPS interval
v_bsn_init := ceil_div(v_SSN * g_pps_interval, g_block_size); -- Equation 3.6 in [1]
v_bsn_time_offset := v_bsn_init * g_block_size - v_SSN * g_pps_interval; -- Equation 3.7 in [1]
- bsn_init <= TO_UVEC(v_bsn_init, c_bsn_w); --
+ bsn_init <= TO_UVEC(v_bsn_init, c_bsn_w); --
bsn_time_offset <= TO_UVEC(v_bsn_time_offset, c_bsn_time_offset_w);
-- Start synchronously by making dp_on and dp_on_pps high
tb_state <= s_dp_on_pps;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
index 88398d7ff1a6775eea604b5ffb6bd11bffe399ff..ef9aff6ee3a0f84ab6fc66133d45c902f394689b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
@@ -297,7 +297,7 @@ begin
v_ssn := ref_grid_bs.ssn + 1; -- +1 to prepare start in next PPS interval
v_bsn_init := ceil_div(v_SSN * g_pps_interval, g_bs_block_size); -- Equation 3.6 in [1]
v_bsn_time_offset := v_bsn_init * g_bs_block_size - v_SSN * g_pps_interval; -- Equation 3.7 in [1]
- bsn_init <= TO_UVEC(v_bsn_init, c_bsn_w); --
+ bsn_init <= TO_UVEC(v_bsn_init, c_bsn_w); --
bsn_time_offset <= TO_UVEC(v_bsn_time_offset, c_bsn_time_offset_w);
-- Start synchronously by making dp_on and dp_on_pps high
tb_state <= s_dp_on_pps;
diff --git a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
index b213e940b282579a8aa635740666e424d640a20f..6eec8d96eee02515ec831af1581cf917ebea0d4f 100644
--- a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
@@ -269,7 +269,7 @@ begin
v.count_up := 0;
v.count_down := g_nof_points;
v.count_chan := 0;
- elsif(r.count_up = g_nof_points / 2 and r.count_chan < c_nof_channels - 1) then --
+ elsif(r.count_up = g_nof_points / 2 and r.count_chan < c_nof_channels - 1) then --
v.count_up := 0;
v.count_down := g_nof_points;
v.count_chan := r.count_chan + 1;
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
index 6a330a4e684b6640a505459312286780eb5595a3..c114651ec5c5665697630ffd3c6880f6d7ad2f74 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
@@ -104,7 +104,7 @@ end unb1_eth_10g;
architecture str of unb1_eth_10g is
-- Firmware version x.y
- constant c_fw_version : t_unb1_board_fw_version := (1, 0); --
+ constant c_fw_version : t_unb1_board_fw_version := (1, 0); --
-- CONSTANT c_eth_packet_size --FIXME
diff --git a/libraries/io/mdio/src/vhdl/mdio_phy.vhd b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
index d23532a6585dcb45ab5e1cdb58d1d8270a26d30d..594d6d69306bc6af10be351132c873aebf7e212d 100644
--- a/libraries/io/mdio/src/vhdl/mdio_phy.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
@@ -220,7 +220,7 @@ begin
end if;
when s_add_mdc =>
- bit_cnt_rst <= '1'; --
+ bit_cnt_rst <= '1'; --
if tx_en = '1' then
nxt_state <= s_done;
end if;