From efb07bad329bb3f687e3208afe1b80871792e8c2 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 5 Oct 2022 10:09:58 +0200
Subject: [PATCH] Use external ref_sync to start and hold counter values.
---
.../base/dp/src/vhdl/dp_block_validate_err.vhd | 18 +++++++++++++++---
.../dp/tb/vhdl/tb_dp_block_validate_err.vhd | 7 +++++--
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
index f5404195ff..91d0c9b6ee 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
@@ -49,6 +49,11 @@
-- . g_fifo_size can be set to g_max_block_size if there is no backpressure.
-- If there is back pressure on the src_in, the fifo_fill_eop can be used to
-- to account for this backpressure by using an g_fifo_size > g_max_block_size.
+-- . Typically externally connect snk_in.sync to ref_sync or use another reference
+-- pulse. If ref_sync is kept '1', then the MM counts show the current values.
+-- Use a ref_sync pulse to let the MM counts show the values at that specific
+-- instant, independent of when they are read.
+--
-------------------------------------------------------------------------------
-- REGMAP
-------------------------------------------------------------------------------
@@ -95,6 +100,9 @@ ENTITY dp_block_validate_err IS
PORT (
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
+
+ ref_sync : IN STD_LOGIC := '1';
+
-- ST sink
snk_out : OUT t_dp_siso := c_dp_siso_rdy;
snk_in : IN t_dp_sosi;
@@ -126,6 +134,7 @@ ARCHITECTURE rtl OF dp_block_validate_err IS
init_sl => '0');
-- Registers in st_clk domain
+ SIGNAL ref_sync_reg : STD_LOGIC := '0';
SIGNAL count_reg : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL nxt_cnt_en : STD_LOGIC;
@@ -169,10 +178,13 @@ BEGIN
out_pulse => cnt_clr
);
+ -- . register snk_in.sync to ease timing closure for ref_sync fanout
+ ref_sync_reg <= ref_sync WHEN rising_edge(dp_clk);
+
-- . clear block counters immediately at cnt_clr
-- . start block counters after sync, e.g. to align block counters in different nodes in
-- case the snk_in was (already) active during the cnt_clr
- nxt_cnt_en <= '0' WHEN cnt_clr = '1' ELSE '1' WHEN snk_in.sync = '1' ELSE cnt_en;
+ nxt_cnt_en <= '0' WHEN cnt_clr = '1' ELSE '1' WHEN ref_sync_reg = '1' ELSE cnt_en;
cnt_en <= nxt_cnt_en WHEN rising_edge(dp_clk);
cnt_this_eop <= cnt_en AND snk_in.eop;
@@ -226,7 +238,7 @@ BEGIN
);
END GENERATE;
- -- Hold counter values at snk_in.sync to have stable values for MM read for comparision between nodes
+ -- Hold counter values at ref_sync_reg to have stable values for MM read for comparision between nodes
p_hold_counters : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
@@ -234,7 +246,7 @@ BEGIN
hold_cnt_blk <= (OTHERS=>'0');
hold_cnt_discarded <= (OTHERS=>'0');
hold_cnt_err_arr <= (OTHERS=>(OTHERS=>'0'));
- ELSIF snk_in.sync = '1' THEN
+ ELSIF ref_sync_reg = '1' THEN
hold_cnt_blk <= cnt_blk;
hold_cnt_discarded <= cnt_discarded;
hold_cnt_err_arr <= cnt_err_arr;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
index 156f92bed2..fe42dfd3e3 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
@@ -160,8 +160,8 @@ BEGIN
dp_rst => rst,
dp_clk => dp_clk,
- mm_rst => rst,
- mm_clk => mm_clk,
+ ref_sync => stimuli_sosi.sync,
+
-- ST sink
snk_out => stimuli_siso,
snk_in => stimuli_sosi,
@@ -169,6 +169,9 @@ BEGIN
src_in => verify_siso,
src_out => verify_sosi,
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
reg_mosi => reg_mosi,
reg_miso => reg_miso
);
--
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