From ef8778947c0fc03d8bb26e732316e5d934ee4b08 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Tue, 13 Jan 2015 16:01:58 +0000
Subject: [PATCH] 'minimal' -> 'test'
---
.../unb2_test/src/vhdl/mmm_unb2_test.vhd | 10 +++++-----
.../unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd | 8 ++++----
.../designs/unb2_test/src/vhdl/unb2_test.vhd | 10 +++++-----
.../unb2_test/tb/python/tc_unb2_test.py | 2 +-
.../designs/unb2_test/tb/vhdl/tb_unb2_test.vhd | 18 +++++++++---------
5 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index b8bfba4b2a..a9144a14fa 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -28,10 +28,10 @@ USE unb2_board_lib.unb2_board_pkg.ALL;
USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
-USE work.qsys_unb2_minimal_pkg.ALL;
+USE work.qsys_unb2_test_pkg.ALL;
-ENTITY mmm_unb2_minimal IS
+ENTITY mmm_unb2_test IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
@@ -89,9 +89,9 @@ ENTITY mmm_unb2_minimal IS
reg_remu_mosi : OUT t_mem_mosi;
reg_remu_miso : IN t_mem_miso
);
-END mmm_unb2_minimal;
+END mmm_unb2_test;
-ARCHITECTURE str OF mmm_unb2_minimal IS
+ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr;
CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
@@ -151,7 +151,7 @@ BEGIN
-- QSYS for synthesis
----------------------------------------------------------------------------
gen_qsys : IF g_sim = FALSE GENERATE
- u_qsys : qsys_unb2_minimal
+ u_qsys : qsys_unb2_test
PORT MAP (
clk_clk => mm_clk,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 6bb3c81b00..5d3d9d57e6 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -22,13 +22,13 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-PACKAGE qsys_unb2_minimal_pkg IS
+PACKAGE qsys_unb2_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v14 QSYS builder
-----------------------------------------------------------------------------
- COMPONENT qsys_unb2_minimal is
+ COMPONENT qsys_unb2_test is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
@@ -131,6 +131,6 @@ PACKAGE qsys_unb2_minimal_pkg IS
reg_dpmm_data_clk_export : out std_logic; -- export
reg_dpmm_data_reset_export : out std_logic -- export
);
- END COMPONENT qsys_unb2_minimal;
+ END COMPONENT qsys_unb2_test;
-END qsys_unb2_minimal_pkg;
+END qsys_unb2_test_pkg;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 2745a6d31f..9f9eb71e82 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -27,9 +27,9 @@ USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb2_board_lib.unb2_board_pkg.ALL;
-ENTITY unb2_minimal IS
+ENTITY unb2_test IS
GENERIC (
- g_design_name : STRING := "unb2_minimal";
+ g_design_name : STRING := "unb2_test";
g_design_note : STRING := "UNUSED";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
@@ -60,10 +60,10 @@ ENTITY unb2_minimal IS
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
);
-END unb2_minimal;
+END unb2_test;
-ARCHITECTURE str OF unb2_minimal IS
+ARCHITECTURE str OF unb2_test IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
@@ -237,7 +237,7 @@ BEGIN
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
- u_mmm : ENTITY work.mmm_unb2_minimal
+ u_mmm : ENTITY work.mmm_unb2_test
GENERIC MAP (
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
diff --git a/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py b/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
index 350f67779e..72dbbba706 100644
--- a/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
+++ b/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
@@ -20,7 +20,7 @@
#
###############################################################################
-"""Test case for unb1_minimal
+"""Test case for unb2_test
Usage:
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index cf2e781b4c..9e4f7de441 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Test bench for unb2_minimal.
+-- Purpose: Test bench for unb2_test.
-- Description:
-- The DUT can be targeted at unb 0, node 3 with the same Python scripts
-- that are used on hardware.
@@ -29,10 +29,10 @@
-- > run_modelsim & (to start Modeslim)
--
-- In Modelsim do:
--- > lp unb2_minimal
+-- > lp unb2_test
-- > mk clean all (only first time to clean all libraries)
--- > mk all (to compile all libraries that are needed for unb2_minimal)
--- . load tb_unb1_minimal simulation by double clicking the tb_unb2_minimal icon
+-- > mk all (to compile all libraries that are needed for unb2_test)
+-- . load tb_unb1_test simulation by double clicking the tb_unb2_test icon
-- > as 10 (to view signals in Wave Window)
-- > run 100 us (or run -all)
--
@@ -49,15 +49,15 @@ USE common_lib.common_pkg.ALL;
USE unb2_board_lib.unb2_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
-ENTITY tb_unb2_minimal IS
+ENTITY tb_unb2_test IS
GENERIC (
- g_design_name : STRING := "unb2_minimal";
+ g_design_name : STRING := "unb2_test";
g_sim_unb_nr : NATURAL := 0; -- UniBoard 0
g_sim_node_nr : NATURAL := 3 -- Node 3
);
-END tb_unb2_minimal;
+END tb_unb2_test;
-ARCHITECTURE tb OF tb_unb2_minimal IS
+ARCHITECTURE tb OF tb_unb2_test IS
CONSTANT c_sim : BOOLEAN := TRUE;
@@ -132,7 +132,7 @@ BEGIN
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- u_unb2_minimal : ENTITY work.unb2_minimal
+ u_unb2_test : ENTITY work.unb2_test
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
--
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