From ef389af004148d3d35b11b89d5f5f4a598d8b607 Mon Sep 17 00:00:00 2001 From: Eric Kooistra <kooistra@astron.nl> Date: Wed, 13 Sep 2023 10:39:25 +0200 Subject: [PATCH] Correct c_sdp_N_clk_sync_timeout_xsub --- applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd index f77bab6fcf..ebd79dc6d4 100644 --- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd +++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd @@ -435,7 +435,7 @@ architecture str of sdp_station is constant c_validate_channel : boolean := true; constant c_validate_channel_mode : string := "="; constant c_sync_timeout : natural := sel_a_b(g_sim, g_sim_sync_timeout, c_sdp_N_clk_sync_timeout); - constant c_sync_timeout_xst : natural := sel_a_b(g_sim, g_sim_sync_timeout, c_sdp_N_clk_sync_timeout_xst); + constant c_sync_timeout_xst : natural := sel_a_b(g_sim, g_sim_sync_timeout, c_sdp_N_clk_sync_timeout_xsub); -- Use same Tx FIFO size for all lanes in the ring to ease the code, no need to optimize Tx FIFO RAM usage per lane. -- The tr_10GbE uses dp_fifo_fill_eop, so rely on releasing packets (beamlets, crosslets) at eop instead -- GitLab