diff --git a/boards/uniboard2a/designs/unb2a_minimal/build/unb2a_minimal.jic b/boards/uniboard2a/designs/unb2a_minimal/build/unb2a_minimal.jic
new file mode 100644
index 0000000000000000000000000000000000000000..738840a8428ec654196e85cf02c934b6da682921
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diff --git a/boards/uniboard2a/designs/unb2a_minimal/build/unb2a_minimal.sof b/boards/uniboard2a/designs/unb2a_minimal/build/unb2a_minimal.sof
new file mode 100644
index 0000000000000000000000000000000000000000..3776084da402a1f81a0f62c21c09e2ae3fff1623
Binary files /dev/null and b/boards/uniboard2a/designs/unb2a_minimal/build/unb2a_minimal.sof differ
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README b/boards/uniboard2a/designs/unb2a_minimal/doc/README
new file mode 100644
index 0000000000000000000000000000000000000000..e1f88cd968980457a9d2a5297f927d41ae5ec21c
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README
@@ -0,0 +1,111 @@
+Quick steps to compile and use design [unb2a_minimal] in RadionHDL
+------------------------------------------------------------------
+
+-> In case of a new installation, the IP's have to be generated for Arria10.
+ In the: $RADIOHDL/libraries/technology/ip_arria10
+ directory; run the bash script: ./generate-all-ip.sh
+
+-> For compilation it might be necessary to check the .vhd file:
+ $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+
+
+
+1. Start with the Oneclick Commands:
+ python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2a
+ python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2a
+
+
+2. Generate MMM for QSYS:
+ run_qsys unb2a unb2a_minimal
+
+
+
+3. -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
+
+Simulation
+----------
+Modelsim instructions:
+ # in bash do:
+ rm $UNB/Software/python/sim/* # (optional)
+ run_modelsim unb2a
+
+ # in Modelsim do:
+ lp unb2a_minimal
+ mk all
+ # now double click on testbench file
+ as 10
+ run 500us
+
+ # while the simulation runs... in another bash session do:
+ cd unb2a_minimal/tb/python
+ python tc_unb2a_minimal.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS
+
+ # (sensor results only show up after 1000us of simulation runtime)
+
+ # to end simulation in Modelsim do:
+ quit -sim
+
+
+Synthesis
+---------
+Quartus instructions:
+ run_qcomp unb2a unb2a_minimal
+
+
+In case of needing the Quartus GUI for inspection:
+ run_quartus unb2a
+
+
+
+4. Load firmware
+----------------
+Using JTAG: Start the Quartus GUI and open: tools->programmer.
+ Then click auto-detect;
+ Use 'change file' to select the correct .sof file for each FPGA
+ Select the FPGA(s) which has to be programmed
+ Click 'start'
+Using EPCS: See step 6 below.
+
+
+
+
+5. Testing on hardware
+----------------------
+Assuming the firmware is loaded and running already in the FPGA, the firmware can be tested from the connected
+LCU computer.
+
+# (assume that the Uniboard is --unb 1)
+
+# To read out the design_name, ppsh and sensors; do:
+
+python tc_unb2_minimal.py --unb 1 --fn 0:3 --seq REGMAP,INFO,PPSH,SENSORS -v5
+
+
+
+6.
+Programming the EPCS flash.
+when the EPCS module works an RBF file can be generated to program the flash,
+then the .sof file file can be converted to .rbf with the 'run_rbf' script.
+
+But for now the only way to program the EPCS flash is via JTAG.
+Firstly a JIC file has to be generated from the SOF file.
+In Quartus GUI; open current project; File -> Convert Programming Files.
+Then setup:
+- Output programming file: JIC
+- Configuration device: EPCQL1024
+- Mode: Active Serial x4
+- Flash Loader: Add/Select Device Arria10/10AX115U4ES
+- SOF Data: add file (the generated .sof file)
+ - click the .sof file; Set property 'Compression' to ON
+- Press 'Generate'
+Then program the .JIC file (output_file.jic) to EPCS flash:
+- Make sure that the JTAG (on server connected to board) runs at 16MHz:
+ c:\altera\15.0\quartus\bin64\jtagconfig USB-BlasterII JtagClock 16M
+- open tools->programmer
+- make sure the 4 fpga icons have the device 10AX115U4F45ES
+- right-click each fpga icon and attach flash device EPCQL1024
+- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
+ (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+- right-click each EPCQL1024 and change file from <none> to output_file.jic
+- select click each Program/Configure radiobutton
+- click start and wait for 'Successful'
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..add9726620d4e01da3dfd0cb42d1e4e50c64100f
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -0,0 +1,35 @@
+hdl_lib_name = unb2a_minimal
+hdl_library_clause_name = unb2a_minimal_lib
+hdl_lib_uses_synth = common technology mm unb2a_board
+hdl_lib_uses_sim =
+hdl_lib_excludes = ip_arria10_e3sge3_mac_10g
+
+hdl_lib_technology = ip_arria10_e3sge3
+
+synth_files =
+ src/vhdl/qsys_unb2a_minimal_pkg.vhd
+ src/vhdl/mmm_unb2a_minimal.vhd
+ src/vhdl/unb2a_minimal.vhd
+
+test_bench_files =
+ tb/vhdl/tb_unb2a_minimal.vhd
+
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/qsys_unb2a_minimal.qsys .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+
+quartus_tcl_files =
+ quartus/unb2a_minimal_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
+
diff --git a/boards/uniboard2a/designs/unb2a_minimal/quartus/qsys_unb2a_minimal.qsys b/boards/uniboard2a/designs/unb2a_minimal/quartus/qsys_unb2a_minimal.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..4421237bcda179f164f30147b870764d27d943c9
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/quartus/qsys_unb2a_minimal.qsys
@@ -0,0 +1,1857 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "String";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "String";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ }
+ element cpu_0.debug_mem_slave
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "String";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "440";
+ type = "String";
+ }
+ }
+ element jtag_uart_0.irq
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "String";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "432";
+ type = "String";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "384";
+ type = "String";
+ }
+ }
+ element reg_dpmm_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dpmm_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "424";
+ type = "String";
+ }
+ }
+ element reg_dpmm_data
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dpmm_data.mem
+ {
+ datum baseAddress
+ {
+ value = "416";
+ type = "String";
+ }
+ }
+ element reg_epcs
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_epcs.mem
+ {
+ datum baseAddress
+ {
+ value = "288";
+ type = "String";
+ }
+ }
+ element reg_fpga_temp_sens
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element reg_fpga_temp_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "224";
+ type = "String";
+ }
+ }
+ element reg_fpga_voltage_sens
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element reg_fpga_voltage_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "String";
+ }
+ }
+ element reg_mmdp_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mmdp_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "408";
+ type = "String";
+ }
+ }
+ element reg_mmdp_data
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mmdp_data.mem
+ {
+ datum baseAddress
+ {
+ value = "400";
+ type = "String";
+ }
+ }
+ element reg_remu
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_remu.mem
+ {
+ datum baseAddress
+ {
+ value = "320";
+ type = "String";
+ }
+ }
+ element reg_unb_pmbus
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+ element reg_unb_pmbus.mem
+ {
+ datum baseAddress
+ {
+ value = "192";
+ type = "String";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "352";
+ type = "String";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "String";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "String";
+ }
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="avs_eth_0_clk"
+ internal="avs_eth_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_irq"
+ internal="avs_eth_0.irq"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_address"
+ internal="avs_eth_0.ram_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_read"
+ internal="avs_eth_0.ram_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_readdata"
+ internal="avs_eth_0.ram_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_write"
+ internal="avs_eth_0.ram_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_writedata"
+ internal="avs_eth_0.ram_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_address"
+ internal="avs_eth_0.reg_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_read"
+ internal="avs_eth_0.reg_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_readdata"
+ internal="avs_eth_0.reg_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_write"
+ internal="avs_eth_0.reg_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_writedata"
+ internal="avs_eth_0.reg_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reset"
+ internal="avs_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_address"
+ internal="avs_eth_0.tse_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_read"
+ internal="avs_eth_0.tse_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_readdata"
+ internal="avs_eth_0.tse_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_waitrequest"
+ internal="avs_eth_0.tse_waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_write"
+ internal="avs_eth_0.tse_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_writedata"
+ internal="avs_eth_0.tse_writedata"
+ type="conduit"
+ dir="end" />
+ <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
+ <interface
+ name="pio_pps_address"
+ internal="pio_pps.address"
+ type="conduit"
+ dir="end" />
+ <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" />
+ <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" />
+ <interface
+ name="pio_pps_readdata"
+ internal="pio_pps.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_reset"
+ internal="pio_pps.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_write"
+ internal="pio_pps.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_writedata"
+ internal="pio_pps.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_address"
+ internal="pio_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_clk"
+ internal="pio_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_read"
+ internal="pio_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_readdata"
+ internal="pio_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_reset"
+ internal="pio_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_write"
+ internal="pio_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_writedata"
+ internal="pio_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_wdi_external_connection"
+ internal="pio_wdi.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_address"
+ internal="reg_dpmm_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_clk"
+ internal="reg_dpmm_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_read"
+ internal="reg_dpmm_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_readdata"
+ internal="reg_dpmm_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_reset"
+ internal="reg_dpmm_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_write"
+ internal="reg_dpmm_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_writedata"
+ internal="reg_dpmm_ctrl.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_address"
+ internal="reg_dpmm_data.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_clk"
+ internal="reg_dpmm_data.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_read"
+ internal="reg_dpmm_data.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_readdata"
+ internal="reg_dpmm_data.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_reset"
+ internal="reg_dpmm_data.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_write"
+ internal="reg_dpmm_data.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_writedata"
+ internal="reg_dpmm_data.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_address"
+ internal="reg_epcs.address"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end" />
+ <interface
+ name="reg_epcs_read"
+ internal="reg_epcs.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_readdata"
+ internal="reg_epcs.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_reset"
+ internal="reg_epcs.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_write"
+ internal="reg_epcs.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_writedata"
+ internal="reg_epcs.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_temp_sens_address"
+ internal="reg_fpga_temp_sens.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_temp_sens_clk"
+ internal="reg_fpga_temp_sens.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_temp_sens_read"
+ internal="reg_fpga_temp_sens.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_temp_sens_readdata"
+ internal="reg_fpga_temp_sens.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_temp_sens_reset"
+ internal="reg_fpga_temp_sens.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_temp_sens_write"
+ internal="reg_fpga_temp_sens.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_temp_sens_writedata"
+ internal="reg_fpga_temp_sens.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_voltage_sens_address"
+ internal="reg_fpga_voltage_sens.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_voltage_sens_clk"
+ internal="reg_fpga_voltage_sens.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_voltage_sens_read"
+ internal="reg_fpga_voltage_sens.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_voltage_sens_readdata"
+ internal="reg_fpga_voltage_sens.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_voltage_sens_reset"
+ internal="reg_fpga_voltage_sens.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_voltage_sens_write"
+ internal="reg_fpga_voltage_sens.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_fpga_voltage_sens_writedata"
+ internal="reg_fpga_voltage_sens.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_address"
+ internal="reg_mmdp_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_clk"
+ internal="reg_mmdp_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_read"
+ internal="reg_mmdp_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_readdata"
+ internal="reg_mmdp_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_reset"
+ internal="reg_mmdp_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_write"
+ internal="reg_mmdp_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_writedata"
+ internal="reg_mmdp_ctrl.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_address"
+ internal="reg_mmdp_data.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_clk"
+ internal="reg_mmdp_data.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_read"
+ internal="reg_mmdp_data.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_readdata"
+ internal="reg_mmdp_data.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_reset"
+ internal="reg_mmdp_data.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_write"
+ internal="reg_mmdp_data.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_writedata"
+ internal="reg_mmdp_data.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_address"
+ internal="reg_remu.address"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
+ <interface
+ name="reg_remu_read"
+ internal="reg_remu.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_readdata"
+ internal="reg_remu.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_reset"
+ internal="reg_remu.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_write"
+ internal="reg_remu.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_writedata"
+ internal="reg_remu.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_pmbus_address"
+ internal="reg_unb_pmbus.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_pmbus_clk"
+ internal="reg_unb_pmbus.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_pmbus_read"
+ internal="reg_unb_pmbus.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_pmbus_readdata"
+ internal="reg_unb_pmbus.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_pmbus_reset"
+ internal="reg_unb_pmbus.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_pmbus_write"
+ internal="reg_unb_pmbus.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_pmbus_writedata"
+ internal="reg_unb_pmbus.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_address"
+ internal="reg_unb_sens.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_clk"
+ internal="reg_unb_sens.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_read"
+ internal="reg_unb_sens.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_readdata"
+ internal="reg_unb_sens.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_reset"
+ internal="reg_unb_sens.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_write"
+ internal="reg_unb_sens.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_writedata"
+ internal="reg_unb_sens.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_address"
+ internal="reg_wdi.address"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" />
+ <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" />
+ <interface
+ name="reg_wdi_readdata"
+ internal="reg_wdi.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_reset"
+ internal="reg_wdi.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_write"
+ internal="reg_wdi.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_writedata"
+ internal="reg_wdi.writedata"
+ type="conduit"
+ dir="end" />
+ <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
+ <interface
+ name="rom_system_info_address"
+ internal="rom_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_clk"
+ internal="rom_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_read"
+ internal="rom_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_readdata"
+ internal="rom_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_reset"
+ internal="rom_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_write"
+ internal="rom_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_writedata"
+ internal="rom_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <module name="avs_eth_0" kind="avs2_eth_coe" version="1.0" enabled="1" />
+ <module name="clk_0" kind="clock_source" version="15.0" enabled="1">
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module name="cpu_0" kind="altera_nios2_gen2" version="15.0" enabled="1">
+ <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
+ <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
+ <parameter name="bht_ramBlockType" value="Automatic" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="breakSlave" value="None" />
+ <parameter name="cdx_enabled" value="false" />
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="cpuArchRev" value="1" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
+ <parameter name="dataAddrWidth" value="18" />
+ <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+ <parameter name="dataMasterHighPerformanceMapParam" value="" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='reg_unb_pmbus.mem' start='0xC0' end='0xE0' /><slave name='reg_fpga_temp_sens.mem' start='0xE0' end='0x100' /><slave name='timer_0.s1' start='0x100' end='0x120' /><slave name='reg_epcs.mem' start='0x120' end='0x140' /><slave name='reg_remu.mem' start='0x140' end='0x160' /><slave name='reg_unb_sens.mem' start='0x160' end='0x180' /><slave name='pio_wdi.s1' start='0x180' end='0x190' /><slave name='reg_mmdp_data.mem' start='0x190' end='0x198' /><slave name='reg_mmdp_ctrl.mem' start='0x198' end='0x1A0' /><slave name='reg_dpmm_data.mem' start='0x1A0' end='0x1A8' /><slave name='reg_dpmm_ctrl.mem' start='0x1A8' end='0x1B0' /><slave name='pio_pps.mem' start='0x1B0' end='0x1B8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B8' end='0x1C0' /><slave name='reg_fpga_voltage_sens.mem' start='0x200' end='0x240' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="data_master_high_performance_paddr_base" value="0" />
+ <parameter name="data_master_high_performance_paddr_size" value="0" />
+ <parameter name="data_master_paddr_base" value="0" />
+ <parameter name="data_master_paddr_size" value="0" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_tagramBlockType" value="Automatic" />
+ <parameter name="dcache_victim_buf_impl" value="ram" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_datatrigger" value="0" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_enabled" value="true" />
+ <parameter name="debug_hwbreakpoint" value="0" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_traceStorage" value="onchip_trace" />
+ <parameter name="debug_traceType" value="none" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+ <parameter name="dividerType" value="no_div" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="faAddrWidth" value="1" />
+ <parameter name="faSlaveMapParam" value="" />
+ <parameter name="fa_cache_line" value="2" />
+ <parameter name="fa_cache_linesize" value="0" />
+ <parameter name="flash_instruction_master_paddr_base" value="0" />
+ <parameter name="flash_instruction_master_paddr_size" value="0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_size" value="4096" />
+ <parameter name="icache_tagramBlockType" value="Automatic" />
+ <parameter name="impl" value="Tiny" />
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+ <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+ <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+ <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+ <parameter name="instruction_master_paddr_base" value="0" />
+ <parameter name="instruction_master_paddr_size" value="0" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="io_regionbase" value="0" />
+ <parameter name="io_regionsize" value="0" />
+ <parameter name="master_addr_map" value="false" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="mmu_TLBMissExcSlave" value="None" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="mmu_ramBlockType" value="Automatic" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpx_enabled" value="false" />
+ <parameter name="mul_32_impl" value="2" />
+ <parameter name="mul_64_impl" value="0" />
+ <parameter name="mul_shift_choice" value="0" />
+ <parameter name="ocimem_ramBlockType" value="Automatic" />
+ <parameter name="ocimem_ramInit" value="false" />
+ <parameter name="regfile_ramBlockType" value="Automatic" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateTrace" value="false" />
+ <parameter name="setting_allow_break_inst" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_asic_add_scan_mode_input" value="false" />
+ <parameter name="setting_asic_enabled" value="false" />
+ <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+ <parameter name="setting_asic_third_party_synthesis" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_branchpredictiontype" value="Dynamic" />
+ <parameter name="setting_breakslaveoveride" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_dc_ecc_present" value="true" />
+ <parameter name="setting_disable_tmr_inj" value="false" />
+ <parameter name="setting_disableocitrace" value="false" />
+ <parameter name="setting_dtcm_ecc_present" value="true" />
+ <parameter name="setting_ecc_present" value="false" />
+ <parameter name="setting_ecc_sim_test_ports" value="false" />
+ <parameter name="setting_exportHostDebugPort" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_export_large_RAMs" value="false" />
+ <parameter name="setting_exportdebuginfo" value="false" />
+ <parameter name="setting_exportvectors" value="false" />
+ <parameter name="setting_fast_register_read" value="false" />
+ <parameter name="setting_ic_ecc_present" value="true" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_itcm_ecc_present" value="true" />
+ <parameter name="setting_mmu_ecc_present" value="true" />
+ <parameter name="setting_oci_export_jtag_signals" value="false" />
+ <parameter name="setting_oci_version" value="1" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_removeRAMinit" value="false" />
+ <parameter name="setting_rf_ecc_present" value="true" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_support31bitdcachebypass" value="true" />
+ <parameter name="setting_usedesignware" value="false" />
+ <parameter name="shift_rot_impl" value="1" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+ <parameter name="tmr_enabled" value="false" />
+ <parameter name="tracefilename" value="" />
+ <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+ name="jtag_uart_0"
+ kind="altera_avalon_jtag_uart"
+ version="15.0"
+ enabled="1">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="avalonSpec" value="2.0" />
+ <parameter name="clkFreq" value="50000000" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream" value="" />
+ <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module
+ name="onchip_memory2_0"
+ kind="altera_avalon_onchip_memory2"
+ version="15.0"
+ enabled="1">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
+ <parameter name="blockType" value="AUTO" />
+ <parameter name="copyInitFile" value="false" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+ <parameter name="dualPort" value="false" />
+ <parameter name="ecc_enabled" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName">onchip_memory2_0.hex</parameter>
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="true" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module name="pio_pps" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="pio_system_info" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="pio_wdi" kind="altera_avalon_pio" version="15.0" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module name="reg_dpmm_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_dpmm_data" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_epcs" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_fpga_temp_sens"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_fpga_voltage_sens"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_mmdp_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_mmdp_data" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_remu" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_unb_pmbus" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_unb_sens" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_wdi" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="rom_system_info" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="timer_0" kind="altera_avalon_timer" version="15.0" enabled="1">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="50000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="watchdogPulse" value="2" />
+ </module>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01b8" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="cpu_0.debug_mem_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0160" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01b0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_remu.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0140" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_epcs.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0120" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_dpmm_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01a8" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_dpmm_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x01a0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_mmdp_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0198" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_mmdp_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0190" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_fpga_temp_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00e0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_unb_pmbus.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00c0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="reg_fpga_voltage_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0180" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.instruction_master"
+ end="cpu_0.debug_mem_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="15.0"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="jtag_uart_0.clk" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="pio_wdi.clk" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="timer_0.clk" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="avs_eth_0.mm" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="rom_system_info.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="pio_system_info.system" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="pio_pps.system" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="reg_wdi.system" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="reg_remu.system" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="reg_epcs.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_dpmm_ctrl.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_mmdp_data.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_dpmm_data.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_mmdp_ctrl.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_fpga_temp_sens.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_unb_pmbus.system" />
+ <connection
+ kind="clock"
+ version="15.0"
+ start="clk_0.clk"
+ end="reg_fpga_voltage_sens.system" />
+ <connection
+ kind="interrupt"
+ version="15.0"
+ start="cpu_0.irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="15.0"
+ start="cpu_0.irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection kind="interrupt" version="15.0" start="cpu_0.irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="timer_0.reset" />
+ <connection kind="reset" version="15.0" start="clk_0.clk_reset" end="cpu_0.reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_remu.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_epcs.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_dpmm_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_mmdp_data.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_mmdp_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_dpmm_data.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_fpga_temp_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="clk_0.clk_reset"
+ end="reg_unb_pmbus.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="timer_0.reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="cpu_0.reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_remu.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_epcs.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_dpmm_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_mmdp_data.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_dpmm_data.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_mmdp_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_fpga_temp_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_unb_pmbus.system_reset" />
+ <connection
+ kind="reset"
+ version="15.0"
+ start="cpu_0.debug_reset_request"
+ end="reg_fpga_voltage_sens.system_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9437c56ae86a4a803878c98e96a95090aab15246
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
@@ -0,0 +1,22 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2a_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2369223fb833489a6934a063855bdc34e8739306
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -0,0 +1,320 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE work.qsys_unb2_minimal_pkg.ALL;
+
+
+ENTITY mmm_unb2_minimal IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ pout_wdi : OUT STD_LOGIC;
+
+ -- Manual WDI override
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso;
+
+ -- system_info
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso;
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso;
+
+ reg_fpga_temp_sens_mosi : OUT t_mem_mosi;
+ reg_fpga_temp_sens_miso : IN t_mem_miso;
+ reg_fpga_voltage_sens_mosi: OUT t_mem_mosi;
+ reg_fpga_voltage_sens_miso: IN t_mem_miso;
+
+ reg_unb_pmbus_mosi : OUT t_mem_mosi;
+ reg_unb_pmbus_miso : IN t_mem_miso;
+
+ -- PPSH
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso;
+
+ -- eth1g
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso;
+
+ -- EPCS read
+ reg_dpmm_data_mosi : OUT t_mem_mosi;
+ reg_dpmm_data_miso : IN t_mem_miso;
+ reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
+ reg_dpmm_ctrl_miso : IN t_mem_miso;
+
+ -- EPCS write
+ reg_mmdp_data_mosi : OUT t_mem_mosi;
+ reg_mmdp_data_miso : IN t_mem_miso;
+ reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
+ reg_mmdp_ctrl_miso : IN t_mem_miso;
+
+ -- EPCS status/control
+ reg_epcs_mosi : OUT t_mem_mosi;
+ reg_epcs_miso : IN t_mem_miso;
+
+ -- Remote Update
+ reg_remu_mosi : OUT t_mem_mosi;
+ reg_remu_miso : IN t_mem_miso
+ );
+END mmm_unb2_minimal;
+
+ARCHITECTURE str OF mmm_unb2_minimal IS
+
+ CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr;
+ CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
+
+ SIGNAL i_reset_n : STD_LOGIC;
+
+ ----------------------------------------------------------------------------
+ -- mm_file component
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_update_on_change : BOOLEAN := FALSE;
+ g_mm_rd_latency : NATURAL := 1
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ ----------------------------------------------------------------------------
+ gen_mm_file_io : IF g_sim = TRUE GENERATE
+
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_unb_pmbus : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+
+ u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+
+ u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
+ u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ END GENERATE;
+
+ i_reset_n <= NOT mm_rst;
+
+ ----------------------------------------------------------------------------
+ -- QSYS for synthesis
+ ----------------------------------------------------------------------------
+ gen_qsys : IF g_sim = FALSE GENERATE
+ u_qsys : qsys_unb2_minimal
+ PORT MAP (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 DOWNTO 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 DOWNTO 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 DOWNTO 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 DOWNTO 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 DOWNTO 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+END str;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0c1cd8ba6d162512032ed19af47170c117615983
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
@@ -0,0 +1,156 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE qsys_unb2_minimal_pkg IS
+
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
+
+ component qsys_unb2_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2_minimal;
+
+END qsys_unb2_minimal_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ea4cf89b162146551fd48e0d1c8c80394acf4c5c
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
@@ -0,0 +1,379 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+
+ENTITY unb2_minimal IS
+ GENERIC (
+ g_design_name : STRING := "unb2_minimal";
+ g_design_note : STRING := "UNUSED";
+ g_technology : NATURAL := c_tech_arria10;
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
+ g_factory_image : BOOLEAN := TRUE
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2_minimal;
+
+
+ARCHITECTURE str OF unb2_minimal IS
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_50M;
+
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_ethclk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL st_rst : STD_LOGIC;
+ SIGNAL st_clk : STD_LOGIC;
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+
+ -- PPSH
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- pm bus
+ SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
+ SIGNAL reg_unb_pmbus_miso : t_mem_miso;
+
+ -- FPGA sensors
+ SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
+ SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- EPCS read
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+
+ -- EPCS write
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+
+ -- EPCS status/control
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+
+ -- Remote Update
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+
+ -- QSFP leds
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_tse_clk_buf => TRUE,
+ g_factory_image => g_factory_image
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_mmm : ENTITY work.mmm_unb2_minimal
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
+
+ u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
+
+ u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
+ GENERIC MAP (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ PORT MAP (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
+
+END str;
+
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/python/tc_unb2_minimal.py b/boards/uniboard2a/designs/unb2a_minimal/tb/python/tc_unb2_minimal.py
new file mode 100644
index 0000000000000000000000000000000000000000..2f28d76d12e9c5d336ad80348d0edefd520265d8
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/python/tc_unb2_minimal.py
@@ -0,0 +1,363 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for unb1_minimal
+
+Usage:
+
+ --rep = number of intervals that diagnostics results are verified
+ --sim targets a running simulation.
+
+Description:
+ This test case tests:
+ - system info
+ - read sensors
+ - read ppsh
+ - write to wdi to force reload from bank 0
+ - flash access: write image to bank 1
+ - remote update: start image in bank 1
+
+"""
+
+###############################################################################
+# System imports
+import sys
+import signal
+import test_case
+import node_io
+import pi_system_info
+import pi_unb_sens
+import pi_unb_fpga_sens
+import pi_unb_fpga_voltage_sens
+import pi_ppsh
+import pi_wdi
+import pi_epcs
+import pi_remu
+import pi_eth
+import pi_debug_wave
+
+from tools import *
+from common import *
+from pi_common import *
+
+
+def test_info(tc,io,cmd):
+ tc.set_section_id('Read System Info - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ info = pi_system_info.PiSystemInfo(tc, io)
+ info.read_system_info()
+ tc.append_log(3, '')
+ info.read_use_phy()
+ tc.append_log(3, '')
+ design_name = info.read_design_name()
+ tc.append_log(1, '>>> design_name=%s' % design_name)
+ tc.append_log(3, '')
+ info.read_stamps()
+ tc.append_log(3, '')
+ info.read_design_note()
+
+ expected_design_name = tc.gpString
+ if expected_design_name != '':
+ tc.set_section_id('Verify System Info - ')
+ compared=True
+ for name in design_name:
+ if (name != expected_design_name):
+ tc.set_result('FAILED')
+ compared=False
+ tc.append_log(2, '>>> design_name mismatch!! (%s != %s)' % (name,expected_design_name))
+ tc.append_log(1, '>>> Verify design_name == %s: %s' % (expected_design_name,compared))
+
+
+
+def read_regmap(tc,io,cmd):
+ tc.set_section_id('Update REGMAP - ')
+ info = pi_system_info.PiSystemInfo(tc, io)
+ tc.append_log(1, '>>> reading REGMAPs')
+ info.make_register_info()
+ tc.append_log(1, '>>> reload NodeIO class')
+ return node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+
+
+def test_sensors(tc,io,cmd):
+ tc.set_section_id('Read sensors - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ sens = pi_unb_sens.PiUnbSens(tc, io)
+
+ sens.read_unb_sensors()
+ tc.append_log(3, '')
+ #sens.read_fpga_temperature()
+ tc.append_log(3, '')
+ sens.read_eth_temperature()
+ tc.append_log(3, '')
+ sens.read_unb_current()
+ sens.read_unb_voltage()
+ sens.read_unb_power()
+
+ # Read internal FPGA temp sensor:
+ tc.set_section_id('Read internal fpga sensors - ')
+ sens = pi_unb_fpga_sens.PiUnbFpgaSens(tc, io)
+ sens.read_fpga_temperature()
+ sens = pi_unb_fpga_voltage_sens.PiUnbFpgaVoltageSens(tc, io)
+ sens.read_fpga_voltage()
+
+
+def test_ppsh(tc,io,cmd):
+ tc.set_section_id('Read PPSH capture count - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ Ppsh = pi_ppsh.PiPpsh(tc, io)
+ Ppsh.read_ppsh_capture_cnt()
+ tc.append_log(3, '')
+
+
+
+def test_wdi(tc,io,cmd):
+ tc.set_section_id('Reset to image in bank 0 using WDI - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ Wdi = pi_wdi.PiWdi(tc, io)
+ Wdi.write_wdi_override()
+ tc.append_log(3, '')
+ tc.append_log(3, '>>> Booting...')
+ tc.sleep(5.0)
+
+
+
+def test_remu(tc,io,cmd):
+ tc.set_section_id('REMU start image in bank 1 - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ dummy_tc = test_case.Testcase('Dummy TB - ', '',logfilename='REMU-log')
+ dummy_tc.set_result('PASSED')
+
+ Remu = pi_remu.PiRemu(dummy_tc, io)
+ try:
+ Remu.write_user_reconfigure()
+ except:
+ pass # ignoring FAILED
+
+ if dummy_tc.get_result() == 'FAILED':
+ tc.append_log(1, 'Result=%s but ignoring this' % dummy_tc.get_result())
+
+ tc.append_log(3, '>>> Booting...')
+ tc.sleep(5.0)
+ tc.append_log(3, '')
+
+
+
+def test_eth(tc,io,cmd):
+ tc.set_section_id('ETH status - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ eth = pi_eth.PiEth(tc, io)
+ hdr=eth.read_hdr(0)
+ eth.disassemble_hdr(hdr)
+ tc.append_log(3, '')
+
+
+
+def test_flash(tc,io,cmd):
+ tc.set_section_id('Flash write to bank 1 - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ Epcs = pi_epcs.PiEpcs(tc, io)
+ path_to_rbf = instanceName = tc.gpString
+ Epcs.write_raw_binary_file("user", path_to_rbf)
+ tc.append_log(3, '')
+
+ tc.set_section_id('Flash read/verify bank 1 - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> Read from flash (pi_epcs.py)')
+ tc.append_log(3, '>>>')
+
+ path_to_rbf = instanceName = tc.gpString
+ Epcs.read_and_verify_raw_binary_file("user", path_to_rbf)
+ tc.append_log(3, '')
+
+
+def set_led(tc,dw,led,text):
+ tc.append_log(3, text)
+ dw.set_led(led)
+ tc.sleep(1.0)
+
+def test_leds(tc,io,cmd):
+ tc.set_section_id('LED test - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+ dw = pi_debug_wave.PiDebugWave(tc, io)
+ set_led(tc,dw,'off', '')
+ set_led(tc,dw,'red', 'RED on')
+ set_led(tc,dw,'off', 'RED off')
+ set_led(tc,dw,'green','GREEN on')
+ set_led(tc,dw,'off', 'GREEN off')
+ set_led(tc,dw,'both', 'ORANGE (RED+GREEN) on')
+ set_led(tc,dw,'off', 'ORANGE (RED+GREEN) off')
+ tc.append_log(3, '')
+
+
+def sleep(tc,io,cmd):
+ tc.set_section_id('%s - ' % cmd)
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ if cmd == 'sleep1':
+ tc.sleep(1.0)
+ elif cmd == 'sleep5':
+ tc.sleep(5.0)
+
+def show_help(tc,io,cmd):
+ tc.set_section_id('%s - ' % cmd)
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+
+
+# Avaliable commands
+Cmd = dict()
+Cmd['REGMAP'] = (read_regmap, 'using pi_system_info to read register info (access PIO_SYSTEM_INFO) and store REGMAPs','')
+Cmd['INFO'] = (test_info, 'using pi_system_info to read system info (access PIO_SYSTEM_INFO)','(-s for expected design_name)')
+Cmd['FLASH'] = (test_flash, 'using pi_epcs to program/verify flash','(-s for .rbf file)')
+Cmd['SENSORS'] = (test_sensors, 'using pi_unb_sens to readout sensors (access REG_UNB_SENS)','')
+Cmd['LED'] = (test_leds, 'using pi_debug_wave to set LEDs (access PIO_DEBUG_WAVE)','')
+Cmd['PPSH'] = (test_ppsh, 'using pi_ppsh to read PPSH capture count (access PIO_PPS)','')
+Cmd['ETH'] = (test_eth, 'using pi_eth to read eth status','')
+Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_REMU)','')
+Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','')
+Cmd['sleep1'] = (sleep, 'Sleep 1 second','')
+Cmd['sleep5'] = (sleep, 'Sleep 5 seconds','')
+Cmd['example'] = (show_help, 'show several example commands','')
+Cmd['help'] = (show_help, 'show help on commands','')
+
+
+def help_text(tc,io,cmd):
+ str=''
+ if cmd == 'help':
+ tc.append_log(0, '\n')
+ tc.append_log(0, '>>> Help:')
+ tc.append_log(0, 'Usage: %s <nodes> <command sequence> [-v..] [--rep ...]' % sys.argv[0])
+ tc.append_log(0, '')
+ tc.append_log(0, ' <nodes>: use: --unb N --fn N --bn N (N is a number or vector) or:')
+ tc.append_log(0, ' <nodes>: use: --gn N (N is a number or vector)')
+ tc.append_log(0, ' <command sequence>: use: --seq <command(s) separated by ",">:')
+ tc.append_log(0, '')
+ for cmd in sorted(Cmd):
+ tc.append_log(0, ' . %s\t%s %s' % (cmd,Cmd[cmd][1],Cmd[cmd][2]))
+ tc.append_log(0, '')
+ tc.append_log(0, ' [-vN]: verbose level N (default=5): %s' % tc.verbose_levels())
+ tc.append_log(0, ' [--rep N]: N=number of repeats, where -1 is forever, non-stop')
+ help_text(tc,io,'example')
+ elif cmd == 'example':
+ tc.append_log(0, '')
+ tc.append_log(0, '>>> Examples:')
+ tc.append_log(0, '')
+ tc.append_log(0, 'Getting INFO from all nodes on 1 Uniboard: %s --gn 0:7 --seq INFO' % sys.argv[0])
+ tc.append_log(0, '')
+ tc.append_log(0, '[reset, load user img] sequence: --seq REGMAP,WDI,REGMAP,REMU,REGMAP,INFO')
+ tc.append_log(0, '[flash+start user img] sequence: --seq FLASH,WDI,REGMAP,REMU,REGMAP,INFO -s file.rbf')
+ tc.append_log(0, '[re-read info,sensors] sequence: --seq INFO,PPSH,SENSORS --rep -1 -s expected_design_name')
+ tc.append_log(0, '[reset to factory] sequence: --seq WDI,REGMAP')
+ tc.append_log(0, '[program user image] sequence: --seq FLASH -s file.rbf')
+ tc.append_log(0, '[load user image] sequence: --seq REMU,REGMAP')
+ tc.append_log(0, '[modelsim BG-DB test] arguments: --unb 0 --fn 0 --seq BGDB --sim -r 0:2')
+ tc.append_log(0, '\n')
+ else:
+ str = Cmd[cmd][1]
+ return str
+
+
+def signal_handler(signal, frame):
+ print('You pressed Ctrl+C!')
+ tc.repeat=0
+
+
+##################################################################################################################
+# Main
+#
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+tc.set_result('PASSED')
+dgnName = tc.gpString
+tc.append_log(3, '>>>')
+tc.append_log(0, '>>> Title : Test bench (%s) on nodes %s, %s' % (sys.argv[0],tc.unb_nodes_string(''),dgnName))
+tc.append_log(0, '>>> Commandline : %s' % " ".join(sys.argv))
+tc.append_log(3, '>>>')
+
+
+# Create access object for nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+signal.signal(signal.SIGINT, signal_handler)
+
+##################################################################################################################
+# Run tests
+while tc.repeat != 0: # -1 for non-stop
+ tc.repeat -= 1
+ tc.next_run()
+ tc.append_log(3, '')
+
+ try:
+ for cmd in tc.sequence:
+ tc.set_section_id('Next command: %s ' % cmd)
+ tc.append_log(1, '>>> Testrun %d (@%.02fs) - ' % (tc.get_nof_runs(),tc.get_run_time()))
+
+ if cmd == 'REGMAP': # reload node_io:
+ io = Cmd[cmd][0](tc,io,cmd)
+ else:
+ Cmd[cmd][0](tc,io,cmd)
+
+
+ except KeyError:
+ print 'Unknown command:',cmd
+ cmd='help'
+ Cmd[cmd][0](tc,io,cmd)
+# except:
+# print 'Catched error:',sys.exc_info()[0]
+
+
+
+##################################################################################################################
+# End
+tc.set_section_id('')
+tc.append_log(3, '')
+tc.append_log(3, '>>>')
+tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+tc.append_log(0, '>>> Number of runs=%d' % tc.get_nof_runs())
+tc.append_log(0, '>>> Number of errors=%d' % tc.get_nof_errors())
+tc.append_log(0, '>>> Runtime=%f seconds (%f hours)' % (tc.get_run_time(),tc.get_run_time()/3600))
+tc.append_log(3, '>>>')
+
+sys.exit(tc.get_result())
+
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8bc8b42190fa6b3653504a57ec4533f1df9ea37a
--- /dev/null
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -0,0 +1,220 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb2_minimal.
+-- Description:
+-- The DUT can be targeted at unb 0, node 3 with the same Python scripts
+-- that are used on hardware.
+-- Usage:
+-- On command line do:
+-- > run_modelsim & (to start Modeslim)
+--
+-- In Modelsim do:
+-- > lp unb2_minimal
+-- > mk clean all (only first time to clean all libraries)
+-- > mk all (to compile all libraries that are needed for unb2_minimal)
+-- . load tb_unb1_minimal simulation by double clicking the tb_unb2_minimal icon
+-- > as 10 (to view signals in Wave Window)
+-- > run 100 us (or run -all)
+--
+-- On command line do:
+-- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--
+
+LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_unb2_minimal IS
+ GENERIC (
+ g_design_name : STRING := "unb2_minimal";
+ g_sim_unb_nr : NATURAL := 0; -- UniBoard 0
+ g_sim_node_nr : NATURAL := 3 -- Node 3
+ );
+END tb_unb2_minimal;
+
+ARCHITECTURE tb OF tb_unb2_minimal IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 3; -- Node 3
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
+
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 0);
+
+ CONSTANT c_cable_delay : TIME := 12 ns;
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ -- DUT
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+
+ SIGNAL PMBUS_SC : STD_LOGIC;
+ SIGNAL PMBUS_SD : STD_LOGIC;
+ SIGNAL PMBUS_ALERT : STD_LOGIC := '0';
+
+ SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- Model I2C sensor slaves as on the UniBoard
+ CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
+ CONSTANT c_fpga_temp : INTEGER := 60;
+ CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW
+ CONSTANT c_eth_temp : INTEGER := 40;
+ CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L
+ CONSTANT c_hot_swap_R_sense : REAL := 0.01; -- = 10 mOhm on UniBoard
+
+ CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard
+ CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard
+ CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+
+ PMBUS_SC <= 'H'; -- pull up
+ PMBUS_SD <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+ ------------------------------------------------------------------------------
+ -- 1GbE Loopback model
+ ------------------------------------------------------------------------------
+ eth_rxp(0) <= TRANSPORT eth_txp(0) AFTER c_cable_delay;
+
+ eth_rxp(1) <= '0';
+ eth_txp(1) <= '0';
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_unb2_minimal : ENTITY work.unb2_minimal
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_design_name => g_design_name
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ QSFP_LED => qsfp_led
+ );
+
+ ------------------------------------------------------------------------------
+ -- UniBoard sensors
+ ------------------------------------------------------------------------------
+ -- I2C slaves that are available for each FPGA
+ u_fpga_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_fpga_temp_address
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
+
+ -- I2C slaves that are available only via FPGA back node 3
+ u_eth_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_eth_temp_address
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
+
+ u_power : ENTITY i2c_lib.dev_ltc4260
+ GENERIC MAP (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
+
+END tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..68389f080ce4cf76f20db809c089e9a61518d4fb
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
@@ -0,0 +1,39 @@
+hdl_lib_name = unb2_board
+hdl_library_clause_name = unb2_board_lib
+hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs fpga_sense
+hdl_lib_uses_sim =
+
+hdl_lib_technology = ip_arria10
+
+synth_files =
+ src/vhdl/unb2_board_pkg.vhd
+ src/vhdl/unb2_board_system_info.vhd
+ src/vhdl/unb2_board_system_info_reg.vhd
+ src/vhdl/mms_unb2_board_system_info.vhd
+ src/vhdl/unb2_board_clk200_pll.vhd
+ src/vhdl/unb2_board_clk25_pll.vhd
+ src/vhdl/unb2_board_clk125_pll.vhd
+# src/vhdl/unb2_board_clk200mm_pll.vhd
+ src/vhdl/unb2_board_wdi_extend.vhd
+ src/vhdl/unb2_board_node_ctrl.vhd
+ src/vhdl/unb2_board_sens_ctrl.vhd
+ src/vhdl/unb2_board_sens.vhd
+ src/vhdl/unb2_board_sens_reg.vhd
+ src/vhdl/unb2_fpga_sens_reg.vhd
+ src/vhdl/mms_unb2_board_sens.vhd
+ src/vhdl/mms_unb2_fpga_sens.vhd
+ src/vhdl/unb2_board_wdi_reg.vhd
+ src/vhdl/unb2_board_qsfp_leds.vhd
+ src/vhdl/ctrl_unb2_board.vhd
+ src/vhdl/unb2_board_front_io.vhd
+ src/vhdl/unb2_board_back_io.vhd
+ src/vhdl/unb2_board_ring_io.vhd
+ src/vhdl/unb2_board_peripherals_pkg.vhd
+
+test_bench_files =
+ tb/vhdl/tb_mms_unb2_board_sens.vhd
+ tb/vhdl/tb_unb2_board_clk200_pll.vhd
+ tb/vhdl/tb_unb2_board_clk25_pll.vhd
+ tb/vhdl/tb_unb2_board_node_ctrl.vhd
+ tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/README b/boards/uniboard2a/libraries/unb2a_board/quartus/README
new file mode 100644
index 0000000000000000000000000000000000000000..2053e16965d1767ad0313b33e0d29f31f31ee3e9
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/README
@@ -0,0 +1,5 @@
+The file:
+
+ sfl_enhanced_01_02e360dd.sof
+
+needs to be loaded in the FPGA when a JIC file is programmed to the EPCS flash
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl b/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3473f5172e5273b0c9dd68518e0a58ea6b87fc26
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
@@ -0,0 +1,672 @@
+
+set_location_assignment PIN_AL32 -to CLKUSR
+
+
+set_location_assignment PIN_Y36 -to SA_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
+# internal termination should be enabled.
+set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK
+
+
+set_location_assignment PIN_AH9 -to SB_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK
+# internal termination should be enabled.
+set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SB_CLK
+
+
+set_location_assignment PIN_V9 -to BCK_REF_CLK
+set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
+
+
+
+# QSFP_0_RX
+set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
+set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
+set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
+set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3]
+
+# QSFP_0_TX
+set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
+set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
+set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
+set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
+
+# QSFP_1_RX
+set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
+set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
+set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
+set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_1_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[3]
+
+
+#
+# QSFP_1_TX
+set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
+set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
+set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
+set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[3]
+
+# QSFP_2_RX
+set_location_assignment PIN_AL38 -to QSFP_2_RX[0]
+set_location_assignment PIN_AH40 -to QSFP_2_RX[1]
+set_location_assignment PIN_AE38 -to QSFP_2_RX[2]
+set_location_assignment PIN_AB40 -to QSFP_2_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_2_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_2_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_2_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_2_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_RX[3]
+
+
+# QSFP_2_TX
+set_location_assignment PIN_AL42 -to QSFP_2_TX[0]
+set_location_assignment PIN_AH44 -to QSFP_2_TX[1]
+set_location_assignment PIN_AE42 -to QSFP_2_TX[2]
+set_location_assignment PIN_AB44 -to QSFP_2_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_2_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_2_TX[3]
+
+# QSFP_3_RX
+set_location_assignment PIN_W38 -to QSFP_3_RX[0]
+set_location_assignment PIN_T40 -to QSFP_3_RX[1]
+set_location_assignment PIN_N38 -to QSFP_3_RX[2]
+set_location_assignment PIN_K40 -to QSFP_3_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_3_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_3_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_3_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_3_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_RX[3]
+
+
+# QSFP_3_TX
+set_location_assignment PIN_W42 -to QSFP_3_TX[0]
+set_location_assignment PIN_T44 -to QSFP_3_TX[1]
+set_location_assignment PIN_N42 -to QSFP_3_TX[2]
+set_location_assignment PIN_K44 -to QSFP_3_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_3_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_3_TX[3]
+
+# QSFP_4_RX
+set_location_assignment PIN_AA38 -to QSFP_4_RX[0]
+set_location_assignment PIN_Y40 -to QSFP_4_RX[1]
+set_location_assignment PIN_V40 -to QSFP_4_RX[2]
+set_location_assignment PIN_U38 -to QSFP_4_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_4_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_4_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_4_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_4_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_RX[3]
+
+
+# QSFP_4_TX
+set_location_assignment PIN_AA42 -to QSFP_4_TX[0]
+set_location_assignment PIN_Y44 -to QSFP_4_TX[1]
+set_location_assignment PIN_V44 -to QSFP_4_TX[2]
+set_location_assignment PIN_U42 -to QSFP_4_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_4_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_4_TX[3]
+
+# QSFP_5_RX
+set_location_assignment PIN_L38 -to QSFP_5_RX[0]
+set_location_assignment PIN_M40 -to QSFP_5_RX[1]
+set_location_assignment PIN_P40 -to QSFP_5_RX[2]
+set_location_assignment PIN_R38 -to QSFP_5_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_5_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_5_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_5_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFP_5_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_RX[3]
+
+
+# QSFP_5_TX
+set_location_assignment PIN_L42 -to QSFP_5_TX[0]
+set_location_assignment PIN_M44 -to QSFP_5_TX[1]
+set_location_assignment PIN_P44 -to QSFP_5_TX[2]
+set_location_assignment PIN_R42 -to QSFP_5_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_5_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_5_TX[3]
+
+
+
+set_location_assignment PIN_B9 -to BCK_RX[0]
+set_location_assignment PIN_D9 -to BCK_RX[1]
+set_location_assignment PIN_C11 -to BCK_RX[2]
+set_location_assignment PIN_F9 -to BCK_RX[3]
+set_location_assignment PIN_C7 -to BCK_RX[4]
+set_location_assignment PIN_E11 -to BCK_RX[5]
+set_location_assignment PIN_E7 -to BCK_RX[6]
+set_location_assignment PIN_D5 -to BCK_RX[7]
+set_location_assignment PIN_G7 -to BCK_RX[8]
+set_location_assignment PIN_F5 -to BCK_RX[9]
+set_location_assignment PIN_J7 -to BCK_RX[10]
+set_location_assignment PIN_H5 -to BCK_RX[11]
+set_location_assignment PIN_L7 -to BCK_RX[12]
+set_location_assignment PIN_K5 -to BCK_RX[13]
+set_location_assignment PIN_N7 -to BCK_RX[14]
+set_location_assignment PIN_M5 -to BCK_RX[15]
+set_location_assignment PIN_R7 -to BCK_RX[16]
+set_location_assignment PIN_P5 -to BCK_RX[17]
+set_location_assignment PIN_U7 -to BCK_RX[18]
+set_location_assignment PIN_T5 -to BCK_RX[19]
+set_location_assignment PIN_W7 -to BCK_RX[20]
+set_location_assignment PIN_V5 -to BCK_RX[21]
+set_location_assignment PIN_AA7 -to BCK_RX[22]
+set_location_assignment PIN_Y5 -to BCK_RX[23]
+set_location_assignment PIN_AC7 -to BCK_RX[24]
+set_location_assignment PIN_AB5 -to BCK_RX[25]
+set_location_assignment PIN_AE7 -to BCK_RX[26]
+set_location_assignment PIN_AD5 -to BCK_RX[27]
+set_location_assignment PIN_AG7 -to BCK_RX[28]
+set_location_assignment PIN_AF5 -to BCK_RX[29]
+set_location_assignment PIN_AJ7 -to BCK_RX[30]
+set_location_assignment PIN_AH5 -to BCK_RX[31]
+set_location_assignment PIN_AL7 -to BCK_RX[32]
+set_location_assignment PIN_AK5 -to BCK_RX[33]
+set_location_assignment PIN_AN7 -to BCK_RX[34]
+set_location_assignment PIN_AM5 -to BCK_RX[35]
+set_location_assignment PIN_AR7 -to BCK_RX[36]
+set_location_assignment PIN_AP5 -to BCK_RX[37]
+set_location_assignment PIN_AU7 -to BCK_RX[38]
+set_location_assignment PIN_AT5 -to BCK_RX[39]
+set_location_assignment PIN_AW7 -to BCK_RX[40]
+set_location_assignment PIN_AV5 -to BCK_RX[41]
+set_location_assignment PIN_BA7 -to BCK_RX[42]
+set_location_assignment PIN_AY5 -to BCK_RX[43]
+set_location_assignment PIN_BC7 -to BCK_RX[44]
+set_location_assignment PIN_BB5 -to BCK_RX[45]
+set_location_assignment PIN_AY9 -to BCK_RX[46]
+set_location_assignment PIN_BB9 -to BCK_RX[47]
+
+set_location_assignment PIN_B5 -to BCK_TX[0]
+set_location_assignment PIN_A3 -to BCK_TX[1]
+set_location_assignment PIN_A11 -to BCK_TX[2]
+set_location_assignment PIN_B1 -to BCK_TX[3]
+set_location_assignment PIN_C3 -to BCK_TX[4]
+set_location_assignment PIN_A7 -to BCK_TX[5]
+set_location_assignment PIN_D1 -to BCK_TX[6]
+set_location_assignment PIN_E3 -to BCK_TX[7]
+set_location_assignment PIN_F1 -to BCK_TX[8]
+set_location_assignment PIN_G3 -to BCK_TX[9]
+set_location_assignment PIN_J3 -to BCK_TX[10]
+set_location_assignment PIN_H1 -to BCK_TX[11]
+set_location_assignment PIN_L3 -to BCK_TX[12]
+set_location_assignment PIN_K1 -to BCK_TX[13]
+set_location_assignment PIN_N3 -to BCK_TX[14]
+set_location_assignment PIN_M1 -to BCK_TX[15]
+set_location_assignment PIN_R3 -to BCK_TX[16]
+set_location_assignment PIN_P1 -to BCK_TX[17]
+set_location_assignment PIN_U3 -to BCK_TX[18]
+set_location_assignment PIN_T1 -to BCK_TX[19]
+set_location_assignment PIN_W3 -to BCK_TX[20]
+set_location_assignment PIN_V1 -to BCK_TX[21]
+set_location_assignment PIN_AA3 -to BCK_TX[22]
+set_location_assignment PIN_Y1 -to BCK_TX[23]
+set_location_assignment PIN_AC3 -to BCK_TX[24]
+set_location_assignment PIN_AB1 -to BCK_TX[25]
+set_location_assignment PIN_AE3 -to BCK_TX[26]
+set_location_assignment PIN_AD1 -to BCK_TX[27]
+set_location_assignment PIN_AG3 -to BCK_TX[28]
+set_location_assignment PIN_AF1 -to BCK_TX[29]
+set_location_assignment PIN_AJ3 -to BCK_TX[30]
+set_location_assignment PIN_AH1 -to BCK_TX[31]
+set_location_assignment PIN_AL3 -to BCK_TX[32]
+set_location_assignment PIN_AK1 -to BCK_TX[33]
+set_location_assignment PIN_AN3 -to BCK_TX[34]
+set_location_assignment PIN_AM1 -to BCK_TX[35]
+set_location_assignment PIN_AR3 -to BCK_TX[36]
+set_location_assignment PIN_AP1 -to BCK_TX[37]
+set_location_assignment PIN_AU3 -to BCK_TX[38]
+set_location_assignment PIN_AT1 -to BCK_TX[39]
+set_location_assignment PIN_AW3 -to BCK_TX[40]
+set_location_assignment PIN_AV1 -to BCK_TX[41]
+set_location_assignment PIN_BB1 -to BCK_TX[42]
+set_location_assignment PIN_AY1 -to BCK_TX[43]
+set_location_assignment PIN_BD5 -to BCK_TX[44]
+set_location_assignment PIN_BA3 -to BCK_TX[45]
+set_location_assignment PIN_BC3 -to BCK_TX[46]
+set_location_assignment PIN_BD9 -to BCK_TX[47]
+
+set_location_assignment PIN_AP40 -to RING_0_RX[0]
+set_location_assignment PIN_AR38 -to RING_0_RX[1]
+set_location_assignment PIN_AT40 -to RING_0_RX[2]
+set_location_assignment PIN_AU38 -to RING_0_RX[3]
+set_location_assignment PIN_AP44 -to RING_0_TX[0]
+set_location_assignment PIN_AR42 -to RING_0_TX[1]
+set_location_assignment PIN_AT44 -to RING_0_TX[2]
+set_location_assignment PIN_AU42 -to RING_0_TX[3]
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_F44 -to RING_1_TX[3]
+
+set_location_assignment PIN_AV40 -to RING_0_RX[4]
+set_location_assignment PIN_AW38 -to RING_0_RX[5]
+set_location_assignment PIN_AY40 -to RING_0_RX[6]
+set_location_assignment PIN_BA38 -to RING_0_RX[7]
+set_location_assignment PIN_BB40 -to RING_0_RX[8]
+set_location_assignment PIN_BC38 -to RING_0_RX[9]
+set_location_assignment PIN_AY36 -to RING_0_RX[10]
+set_location_assignment PIN_BB36 -to RING_0_RX[11]
+set_location_assignment PIN_AV44 -to RING_0_TX[4]
+set_location_assignment PIN_AW42 -to RING_0_TX[5]
+set_location_assignment PIN_AY44 -to RING_0_TX[6]
+set_location_assignment PIN_BB44 -to RING_0_TX[7]
+set_location_assignment PIN_BA42 -to RING_0_TX[8]
+set_location_assignment PIN_BD40 -to RING_0_TX[9]
+set_location_assignment PIN_BC42 -to RING_0_TX[10]
+set_location_assignment PIN_BD36 -to RING_0_TX[11]
+set_location_assignment PIN_D40 -to RING_1_RX[4]
+set_location_assignment PIN_E38 -to RING_1_RX[5]
+set_location_assignment PIN_F36 -to RING_1_RX[6]
+set_location_assignment PIN_C38 -to RING_1_RX[7]
+set_location_assignment PIN_B36 -to RING_1_RX[8]
+set_location_assignment PIN_D36 -to RING_1_RX[9]
+set_location_assignment PIN_E34 -to RING_1_RX[10]
+set_location_assignment PIN_C34 -to RING_1_RX[11]
+set_location_assignment PIN_E42 -to RING_1_TX[4]
+set_location_assignment PIN_D44 -to RING_1_TX[5]
+set_location_assignment PIN_B44 -to RING_1_TX[6]
+set_location_assignment PIN_C42 -to RING_1_TX[7]
+set_location_assignment PIN_B40 -to RING_1_TX[8]
+set_location_assignment PIN_A42 -to RING_1_TX[9]
+set_location_assignment PIN_A38 -to RING_1_TX[10]
+set_location_assignment PIN_A34 -to RING_1_TX[11]
+
+
+
+
+#set_location_assignment PIN_BA25 -to PMBUS_SC
+#set_location_assignment PIN_BD25 -to PMBUS_SD
+#set_location_assignment PIN_BD26 -to PMBUS_ALERT
+#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
+#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
+#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
+
+
+
+
+set_location_assignment PIN_R14 -to BCK_SCL[0]
+set_location_assignment PIN_Y13 -to BCK_SCL[1]
+set_location_assignment PIN_U14 -to BCK_SCL[2]
+set_location_assignment PIN_P14 -to BCK_SDA[0]
+set_location_assignment PIN_T12 -to BCK_SDA[1]
+set_location_assignment PIN_V12 -to BCK_SDA[2]
+
+set_location_assignment PIN_AT31 -to QSFP_RST
+
+set_location_assignment PIN_AY33 -to QSFP_SCL[0]
+set_location_assignment PIN_AY32 -to QSFP_SCL[1]
+set_location_assignment PIN_AY30 -to QSFP_SCL[2]
+set_location_assignment PIN_AN33 -to QSFP_SCL[3]
+set_location_assignment PIN_AN31 -to QSFP_SCL[4]
+set_location_assignment PIN_AJ33 -to QSFP_SCL[5]
+set_location_assignment PIN_BA32 -to QSFP_SDA[0]
+set_location_assignment PIN_BA31 -to QSFP_SDA[1]
+set_location_assignment PIN_AP33 -to QSFP_SDA[2]
+set_location_assignment PIN_AM33 -to QSFP_SDA[3]
+set_location_assignment PIN_AK33 -to QSFP_SDA[4]
+set_location_assignment PIN_AH32 -to QSFP_SDA[5]
+set_location_assignment PIN_M13 -to BCK_ERR[0]
+set_location_assignment PIN_R13 -to BCK_ERR[1]
+set_location_assignment PIN_U12 -to BCK_ERR[2]
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[2]
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl b/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cef7b7858770b1a9604b77770737eb1b4bfa2e08
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
@@ -0,0 +1,561 @@
+# module I:
+set_location_assignment PIN_AP20 -to MB_I_OU.a[0]
+set_location_assignment PIN_AR20 -to MB_I_OU.a[1]
+set_location_assignment PIN_AP19 -to MB_I_OU.a[2]
+set_location_assignment PIN_AR19 -to MB_I_OU.a[3]
+set_location_assignment PIN_AR18 -to MB_I_OU.a[4]
+set_location_assignment PIN_AT17 -to MB_I_OU.a[5]
+set_location_assignment PIN_AU19 -to MB_I_OU.a[6]
+set_location_assignment PIN_AT18 -to MB_I_OU.a[7]
+set_location_assignment PIN_AL17 -to MB_I_OU.a[8]
+set_location_assignment PIN_AM18 -to MB_I_OU.a[9]
+set_location_assignment PIN_AM19 -to MB_I_OU.a[10]
+set_location_assignment PIN_AN19 -to MB_I_OU.a[11]
+set_location_assignment PIN_BA17 -to MB_I_OU.a[12]
+set_location_assignment PIN_BD17 -to MB_I_OU.a[13]
+set_location_assignment PIN_AY18 -to MB_I_OU.act_n
+set_location_assignment PIN_AV29 -to MB_I_IN.alert_n
+set_location_assignment PIN_BB16 -to MB_I_OU.ba[0]
+set_location_assignment PIN_BD16 -to MB_I_OU.ba[1]
+set_location_assignment PIN_BC16 -to MB_I_OU.bg[0]
+set_location_assignment PIN_AW19 -to MB_I_OU.bg[1]
+set_location_assignment PIN_BA15 -to MB_I_OU.a[15]
+set_location_assignment PIN_BC21 -to MB_I_IO.dq[64]
+set_location_assignment PIN_BA22 -to MB_I_IO.dq[65]
+set_location_assignment PIN_BD21 -to MB_I_IO.dq[66]
+set_location_assignment PIN_BB20 -to MB_I_IO.dq[67]
+set_location_assignment PIN_BA20 -to MB_I_IO.dq[68]
+set_location_assignment PIN_BD20 -to MB_I_IO.dq[69]
+set_location_assignment PIN_AY20 -to MB_I_IO.dq[70]
+set_location_assignment PIN_AY22 -to MB_I_IO.dq[71]
+set_location_assignment PIN_AU18 -to MB_I_OU.ck[0]
+#set_location_assignment PIN_AV18 -to MB_I_OU.ck_n[0]
+set_location_assignment PIN_AT16 -to MB_I_OU.ck[1]
+#set_location_assignment PIN_AU16 -to MB_I_OU.ck_n[1]
+set_location_assignment PIN_BB19 -to MB_I_OU.cke[0]
+set_location_assignment PIN_AP16 -to MB_I_OU.cke[1]
+set_location_assignment PIN_AY19 -to MB_I_OU.cs_n[0]
+set_location_assignment PIN_AN16 -to MB_I_OU.cs_n[1]
+set_location_assignment PIN_BC29 -to MB_I_IO.dbi_n[0]
+set_location_assignment PIN_AR27 -to MB_I_IO.dbi_n[1]
+set_location_assignment PIN_BD24 -to MB_I_IO.dbi_n[2]
+set_location_assignment PIN_AM23 -to MB_I_IO.dbi_n[3]
+set_location_assignment PIN_AU12 -to MB_I_IO.dbi_n[4]
+set_location_assignment PIN_AU13 -to MB_I_IO.dbi_n[5]
+set_location_assignment PIN_AM14 -to MB_I_IO.dbi_n[6]
+set_location_assignment PIN_AM16 -to MB_I_IO.dbi_n[7]
+set_location_assignment PIN_BA21 -to MB_I_IO.dbi_n[8]
+set_location_assignment PIN_BA28 -to MB_I_IO.dqs[0]
+set_location_assignment PIN_AM28 -to MB_I_IO.dqs[1]
+set_location_assignment PIN_AV24 -to MB_I_IO.dqs[2]
+set_location_assignment PIN_AN24 -to MB_I_IO.dqs[3]
+set_location_assignment PIN_BC14 -to MB_I_IO.dqs[4]
+set_location_assignment PIN_AW14 -to MB_I_IO.dqs[5]
+set_location_assignment PIN_AN12 -to MB_I_IO.dqs[6]
+set_location_assignment PIN_AK15 -to MB_I_IO.dqs[7]
+set_location_assignment PIN_BC22 -to MB_I_IO.dqs[8]
+
+set_location_assignment PIN_BD19 -to MB_I_OU.odt[0]
+set_location_assignment PIN_AR17 -to MB_I_OU.odt[1]
+set_location_assignment PIN_BC18 -to MB_I_OU.par
+set_location_assignment PIN_BB15 -to MB_I_OU.a[16]
+
+set_location_assignment PIN_AW17 -to MB_I_REF_CLK
+
+set_location_assignment PIN_AV19 -to MB_I_OU.reset_n
+set_location_assignment PIN_AY17 -to MB_I_IN.oct_rzqin
+set_location_assignment PIN_BC17 -to MB_I_OU.a[14]
+
+
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cke[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cs_n[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.odt[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_REF_CLK
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IN.oct_rzqin
+
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[2]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[3]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[4]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[5]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[6]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[7]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[8]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[9]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[10]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[11]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[12]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[13]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.act_n
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.ba[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.ba[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.bg[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.bg[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[15]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_I_OU.ck[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cke[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.cs_n[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.par
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[16]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_I_OU.reset_n
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.a[14]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_I_OU.odt[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IN.alert_n
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[64]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[65]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[66]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[67]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[68]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[69]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[70]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[71]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dbi_n[8]
+
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[5]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[6]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[7]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_I_IO.dqs[8]
+
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[9]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[10]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[11]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[12]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[13]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[14]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[15]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[16]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[17]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[18]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[19]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[20]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[21]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[22]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[23]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[24]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[25]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[26]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[27]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[28]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[29]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[30]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[31]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[32]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[33]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[34]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[35]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[36]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[37]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[38]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[39]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[40]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[41]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[42]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[43]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[44]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[45]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[46]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[47]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[48]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[49]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[50]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[51]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[52]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[53]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[54]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[55]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[56]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[57]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[58]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[59]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[60]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[61]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[62]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_I_IO.dq[63]
+
+# locations changed 30 sept
+set_location_assignment PIN_Y12 -to MB_SCL
+set_location_assignment PIN_AA12 -to MB_SDA
+set_location_assignment PIN_M16 -to MB_I_IN.evt
+
+
+set_location_assignment PIN_AU29 -to MB_I_IO.dq[0]
+set_location_assignment PIN_BC28 -to MB_I_IO.dq[1]
+set_location_assignment PIN_AY29 -to MB_I_IO.dq[2]
+set_location_assignment PIN_BB28 -to MB_I_IO.dq[3]
+set_location_assignment PIN_BB29 -to MB_I_IO.dq[4]
+set_location_assignment PIN_AW29 -to MB_I_IO.dq[5]
+set_location_assignment PIN_BC27 -to MB_I_IO.dq[6]
+set_location_assignment PIN_BD29 -to MB_I_IO.dq[7]
+set_location_assignment PIN_AR28 -to MB_I_IO.dq[8]
+set_location_assignment PIN_AR29 -to MB_I_IO.dq[9]
+set_location_assignment PIN_AV27 -to MB_I_IO.dq[10]
+set_location_assignment PIN_AU28 -to MB_I_IO.dq[11]
+set_location_assignment PIN_AW27 -to MB_I_IO.dq[12]
+set_location_assignment PIN_AT28 -to MB_I_IO.dq[13]
+set_location_assignment PIN_AV28 -to MB_I_IO.dq[14]
+set_location_assignment PIN_AP27 -to MB_I_IO.dq[15]
+set_location_assignment PIN_BC24 -to MB_I_IO.dq[16]
+set_location_assignment PIN_BB24 -to MB_I_IO.dq[17]
+set_location_assignment PIN_BB23 -to MB_I_IO.dq[18]
+set_location_assignment PIN_AW22 -to MB_I_IO.dq[19]
+set_location_assignment PIN_BA23 -to MB_I_IO.dq[20]
+set_location_assignment PIN_BC23 -to MB_I_IO.dq[21]
+set_location_assignment PIN_AY23 -to MB_I_IO.dq[22]
+set_location_assignment PIN_AY24 -to MB_I_IO.dq[23]
+set_location_assignment PIN_AP22 -to MB_I_IO.dq[24]
+set_location_assignment PIN_AN23 -to MB_I_IO.dq[25]
+set_location_assignment PIN_AR23 -to MB_I_IO.dq[26]
+set_location_assignment PIN_AT23 -to MB_I_IO.dq[27]
+set_location_assignment PIN_AU23 -to MB_I_IO.dq[28]
+set_location_assignment PIN_AV23 -to MB_I_IO.dq[29]
+set_location_assignment PIN_AR24 -to MB_I_IO.dq[30]
+set_location_assignment PIN_AP24 -to MB_I_IO.dq[31]
+set_location_assignment PIN_AV12 -to MB_I_IO.dq[32]
+set_location_assignment PIN_AY13 -to MB_I_IO.dq[33]
+set_location_assignment PIN_BD14 -to MB_I_IO.dq[34]
+set_location_assignment PIN_AY12 -to MB_I_IO.dq[35]
+set_location_assignment PIN_BA13 -to MB_I_IO.dq[36]
+set_location_assignment PIN_BA12 -to MB_I_IO.dq[37]
+set_location_assignment PIN_AW12 -to MB_I_IO.dq[38]
+set_location_assignment PIN_BB13 -to MB_I_IO.dq[39]
+set_location_assignment PIN_AV13 -to MB_I_IO.dq[40]
+set_location_assignment PIN_AR13 -to MB_I_IO.dq[41]
+set_location_assignment PIN_AR15 -to MB_I_IO.dq[42]
+set_location_assignment PIN_AP15 -to MB_I_IO.dq[43]
+set_location_assignment PIN_AT15 -to MB_I_IO.dq[44]
+set_location_assignment PIN_AU14 -to MB_I_IO.dq[45]
+set_location_assignment PIN_AU15 -to MB_I_IO.dq[46]
+set_location_assignment PIN_AV14 -to MB_I_IO.dq[47]
+set_location_assignment PIN_AM13 -to MB_I_IO.dq[48]
+set_location_assignment PIN_AT13 -to MB_I_IO.dq[49]
+set_location_assignment PIN_AT12 -to MB_I_IO.dq[50]
+set_location_assignment PIN_AP14 -to MB_I_IO.dq[51]
+set_location_assignment PIN_AN13 -to MB_I_IO.dq[52]
+set_location_assignment PIN_AK13 -to MB_I_IO.dq[53]
+set_location_assignment PIN_AM12 -to MB_I_IO.dq[54]
+set_location_assignment PIN_AL13 -to MB_I_IO.dq[55]
+set_location_assignment PIN_AH13 -to MB_I_IO.dq[56]
+set_location_assignment PIN_AL15 -to MB_I_IO.dq[57]
+set_location_assignment PIN_AM15 -to MB_I_IO.dq[58]
+set_location_assignment PIN_AJ14 -to MB_I_IO.dq[59]
+set_location_assignment PIN_AJ12 -to MB_I_IO.dq[60]
+set_location_assignment PIN_AL16 -to MB_I_IO.dq[61]
+set_location_assignment PIN_AK12 -to MB_I_IO.dq[62]
+set_location_assignment PIN_AH14 -to MB_I_IO.dq[63]
+set_location_assignment PIN_AY28 -to MB_I_IO.dqs_n[0]
+set_location_assignment PIN_AN28 -to MB_I_IO.dqs_n[1]
+set_location_assignment PIN_AU24 -to MB_I_IO.dqs_n[2]
+set_location_assignment PIN_AM24 -to MB_I_IO.dqs_n[3]
+set_location_assignment PIN_BB14 -to MB_I_IO.dqs_n[4]
+set_location_assignment PIN_AY14 -to MB_I_IO.dqs_n[5]
+set_location_assignment PIN_AP12 -to MB_I_IO.dqs_n[6]
+set_location_assignment PIN_AK14 -to MB_I_IO.dqs_n[7]
+set_location_assignment PIN_BD22 -to MB_I_IO.dqs_n[8]
+
+
+
+
+
+# module II:
+set_location_assignment PIN_A29 -to MB_II_OU.a[0]
+set_location_assignment PIN_B29 -to MB_II_OU.a[1]
+set_location_assignment PIN_H29 -to MB_II_OU.a[2]
+set_location_assignment PIN_G29 -to MB_II_OU.a[3]
+set_location_assignment PIN_D29 -to MB_II_OU.a[4]
+set_location_assignment PIN_E29 -to MB_II_OU.a[5]
+set_location_assignment PIN_C29 -to MB_II_OU.a[6]
+set_location_assignment PIN_C28 -to MB_II_OU.a[7]
+set_location_assignment PIN_E30 -to MB_II_OU.a[8]
+set_location_assignment PIN_D30 -to MB_II_OU.a[9]
+set_location_assignment PIN_B28 -to MB_II_OU.a[10]
+set_location_assignment PIN_A28 -to MB_II_OU.a[11]
+set_location_assignment PIN_H27 -to MB_II_OU.a[12]
+set_location_assignment PIN_E28 -to MB_II_OU.a[13]
+set_location_assignment PIN_K28 -to MB_II_OU.act_n
+set_location_assignment PIN_C16 -to MB_II_IN.alert_n
+set_location_assignment PIN_C27 -to MB_II_OU.ba[0]
+set_location_assignment PIN_A27 -to MB_II_OU.ba[1]
+set_location_assignment PIN_B26 -to MB_II_OU.bg[0]
+set_location_assignment PIN_L27 -to MB_II_OU.bg[1]
+set_location_assignment PIN_F28 -to MB_II_OU.a[15]
+set_location_assignment PIN_E24 -to MB_II_IO.dq[64]
+set_location_assignment PIN_J25 -to MB_II_IO.dq[65]
+set_location_assignment PIN_A25 -to MB_II_IO.dq[66]
+set_location_assignment PIN_G25 -to MB_II_IO.dq[67]
+set_location_assignment PIN_D25 -to MB_II_IO.dq[68]
+set_location_assignment PIN_K25 -to MB_II_IO.dq[69]
+set_location_assignment PIN_D24 -to MB_II_IO.dq[70]
+set_location_assignment PIN_F25 -to MB_II_IO.dq[71]
+set_location_assignment PIN_N27 -to MB_II_OU.ck[0]
+#set_location_assignment PIN_M28 -to MB_II_OU.ck_n[0] ;#
+set_location_assignment PIN_K27 -to MB_II_OU.ck[1]
+#set_location_assignment PIN_J26 -to MB_II_OU.ck_n[1] ;#
+set_location_assignment PIN_N28 -to MB_II_OU.cke[0]
+set_location_assignment PIN_P26 -to MB_II_OU.cke[1]
+set_location_assignment PIN_K29 -to MB_II_OU.cs_n[0]
+set_location_assignment PIN_H26 -to MB_II_OU.cs_n[1]
+set_location_assignment PIN_A16 -to MB_II_IO.dbi_n[0]
+set_location_assignment PIN_M21 -to MB_II_IO.dbi_n[1]
+set_location_assignment PIN_K22 -to MB_II_IO.dbi_n[2]
+set_location_assignment PIN_D19 -to MB_II_IO.dbi_n[3]
+set_location_assignment PIN_G30 -to MB_II_IO.dbi_n[4]
+set_location_assignment PIN_R32 -to MB_II_IO.dbi_n[5]
+set_location_assignment PIN_G32 -to MB_II_IO.dbi_n[6]
+set_location_assignment PIN_AC32 -to MB_II_IO.dbi_n[7]
+set_location_assignment PIN_E25 -to MB_II_IO.dbi_n[8]
+set_location_assignment PIN_F17 -to MB_II_IO.dqs[0]
+set_location_assignment PIN_L20 -to MB_II_IO.dqs[1]
+set_location_assignment PIN_J22 -to MB_II_IO.dqs[2]
+set_location_assignment PIN_B19 -to MB_II_IO.dqs[3]
+set_location_assignment PIN_L31 -to MB_II_IO.dqs[4]
+set_location_assignment PIN_P31 -to MB_II_IO.dqs[5]
+set_location_assignment PIN_N33 -to MB_II_IO.dqs[6]
+set_location_assignment PIN_T33 -to MB_II_IO.dqs[7]
+set_location_assignment PIN_A26 -to MB_II_IO.dqs[8]
+
+set_location_assignment PIN_K30 -to MB_II_OU.odt[0]
+set_location_assignment PIN_R27 -to MB_II_OU.odt[1]
+set_location_assignment PIN_R28 -to MB_II_OU.par
+set_location_assignment PIN_G28 -to MB_II_OU.a[16]
+
+set_location_assignment PIN_J29 -to MB_II_REF_CLK
+
+set_location_assignment PIN_L28 -to MB_II_OU.reset_n
+set_location_assignment PIN_J27 -to MB_II_IN.oct_rzqin
+set_location_assignment PIN_F27 -to MB_II_OU.a[14]
+
+
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.cke[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.cs_n[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.odt[1]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_REF_CLK ;#
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IN.oct_rzqin ;#
+
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[2]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[3]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[4]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[5]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[6]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[7]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[8]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[9]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[10]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[11]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[12]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[13]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.act_n
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.ba[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.ba[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.bg[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.bg[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[15]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_OU.ck[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V SSTL" -to MB_II_OU.ck[1]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.cke[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.cs_n[0]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.par
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[16]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to MB_II_OU.reset_n ;#
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.a[14]
+set_instance_assignment -name IO_STANDARD "SSTL-12" -to MB_II_OU.odt[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IN.alert_n ;#
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[64]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[65]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[66]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[67]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[68]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[69]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[70]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[71]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dbi_n[8]
+
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[5]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[6]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[7]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to MB_II_IO.dqs[8]
+
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[0]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[1]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[2]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[3]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[4]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[5]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[6]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[7]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[8]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[9]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[10]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[11]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[12]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[13]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[14]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[15]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[16]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[17]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[18]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[19]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[20]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[21]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[22]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[23]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[24]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[25]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[26]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[27]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[28]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[29]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[30]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[31]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[32]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[33]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[34]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[35]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[36]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[37]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[38]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[39]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[40]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[41]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[42]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[43]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[44]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[45]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[46]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[47]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[48]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[49]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[50]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[51]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[52]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[53]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[54]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[55]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[56]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[57]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[58]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[59]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[60]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[61]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[62]
+set_instance_assignment -name IO_STANDARD "1.2-V POD" -to MB_II_IO.dq[63]
+
+
+
+
+set_location_assignment PIN_A17 -to MB_II_IO.dq[0]
+set_location_assignment PIN_B16 -to MB_II_IO.dq[1]
+set_location_assignment PIN_D16 -to MB_II_IO.dq[2]
+set_location_assignment PIN_A18 -to MB_II_IO.dq[3]
+set_location_assignment PIN_B18 -to MB_II_IO.dq[4]
+set_location_assignment PIN_C17 -to MB_II_IO.dq[5]
+set_location_assignment PIN_E18 -to MB_II_IO.dq[6]
+set_location_assignment PIN_F18 -to MB_II_IO.dq[7]
+set_location_assignment PIN_R22 -to MB_II_IO.dq[8]
+set_location_assignment PIN_J20 -to MB_II_IO.dq[9]
+set_location_assignment PIN_L21 -to MB_II_IO.dq[10]
+set_location_assignment PIN_M20 -to MB_II_IO.dq[11]
+set_location_assignment PIN_J21 -to MB_II_IO.dq[12]
+set_location_assignment PIN_P21 -to MB_II_IO.dq[13]
+set_location_assignment PIN_R20 -to MB_II_IO.dq[14]
+set_location_assignment PIN_N21 -to MB_II_IO.dq[15]
+set_location_assignment PIN_L22 -to MB_II_IO.dq[16]
+set_location_assignment PIN_G20 -to MB_II_IO.dq[17]
+set_location_assignment PIN_H21 -to MB_II_IO.dq[18]
+set_location_assignment PIN_N22 -to MB_II_IO.dq[19]
+set_location_assignment PIN_P22 -to MB_II_IO.dq[20]
+set_location_assignment PIN_F20 -to MB_II_IO.dq[21]
+set_location_assignment PIN_G21 -to MB_II_IO.dq[22]
+set_location_assignment PIN_F21 -to MB_II_IO.dq[23]
+set_location_assignment PIN_E19 -to MB_II_IO.dq[24]
+set_location_assignment PIN_B20 -to MB_II_IO.dq[25]
+set_location_assignment PIN_A20 -to MB_II_IO.dq[26]
+set_location_assignment PIN_G19 -to MB_II_IO.dq[27]
+set_location_assignment PIN_D20 -to MB_II_IO.dq[28]
+set_location_assignment PIN_E20 -to MB_II_IO.dq[29]
+set_location_assignment PIN_D17 -to MB_II_IO.dq[30]
+set_location_assignment PIN_C18 -to MB_II_IO.dq[31]
+set_location_assignment PIN_F30 -to MB_II_IO.dq[32]
+set_location_assignment PIN_L30 -to MB_II_IO.dq[33]
+set_location_assignment PIN_M30 -to MB_II_IO.dq[34]
+set_location_assignment PIN_C31 -to MB_II_IO.dq[35]
+set_location_assignment PIN_D31 -to MB_II_IO.dq[36]
+set_location_assignment PIN_H31 -to MB_II_IO.dq[37]
+set_location_assignment PIN_J31 -to MB_II_IO.dq[38]
+set_location_assignment PIN_F31 -to MB_II_IO.dq[39]
+set_location_assignment PIN_P32 -to MB_II_IO.dq[40]
+set_location_assignment PIN_R30 -to MB_II_IO.dq[41]
+set_location_assignment PIN_U31 -to MB_II_IO.dq[42]
+set_location_assignment PIN_W31 -to MB_II_IO.dq[43]
+set_location_assignment PIN_P29 -to MB_II_IO.dq[44]
+set_location_assignment PIN_P30 -to MB_II_IO.dq[45]
+set_location_assignment PIN_V31 -to MB_II_IO.dq[46]
+set_location_assignment PIN_R29 -to MB_II_IO.dq[47]
+set_location_assignment PIN_M33 -to MB_II_IO.dq[48]
+set_location_assignment PIN_J33 -to MB_II_IO.dq[49]
+set_location_assignment PIN_H33 -to MB_II_IO.dq[50]
+set_location_assignment PIN_H32 -to MB_II_IO.dq[51]
+set_location_assignment PIN_J32 -to MB_II_IO.dq[52]
+set_location_assignment PIN_K33 -to MB_II_IO.dq[53]
+set_location_assignment PIN_K32 -to MB_II_IO.dq[54]
+set_location_assignment PIN_L32 -to MB_II_IO.dq[55]
+set_location_assignment PIN_AB33 -to MB_II_IO.dq[56]
+set_location_assignment PIN_AA32 -to MB_II_IO.dq[57]
+set_location_assignment PIN_W32 -to MB_II_IO.dq[58]
+set_location_assignment PIN_U33 -to MB_II_IO.dq[59]
+set_location_assignment PIN_Y33 -to MB_II_IO.dq[60]
+set_location_assignment PIN_AA33 -to MB_II_IO.dq[61]
+set_location_assignment PIN_V33 -to MB_II_IO.dq[62]
+set_location_assignment PIN_Y32 -to MB_II_IO.dq[63]
+set_location_assignment PIN_E17 -to MB_II_IO.dqs_n[0]
+set_location_assignment PIN_K20 -to MB_II_IO.dqs_n[1]
+set_location_assignment PIN_H22 -to MB_II_IO.dqs_n[2]
+set_location_assignment PIN_C19 -to MB_II_IO.dqs_n[3]
+set_location_assignment PIN_M31 -to MB_II_IO.dqs_n[4]
+set_location_assignment PIN_N31 -to MB_II_IO.dqs_n[5]
+set_location_assignment PIN_P33 -to MB_II_IO.dqs_n[6]
+set_location_assignment PIN_T32 -to MB_II_IO.dqs_n[7]
+set_location_assignment PIN_B25 -to MB_II_IO.dqs_n[8]
+
+
+
+
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl b/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2f6669160deb6400b7aac25904c4ea07415e7aba
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
@@ -0,0 +1,129 @@
+
+set_location_assignment PIN_K15 -to CLK
+set_location_assignment PIN_J15 -to "CLK(n)"
+set_location_assignment PIN_N12 -to ETH_CLK
+set_location_assignment PIN_K14 -to PPS
+set_location_assignment PIN_J14 -to "PPS(n)"
+
+# enable 100 ohm termination:
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to CLK
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to PPS
+
+#set_location_assignment PIN_AT33 -to CFG_DATA[0]
+#set_location_assignment PIN_AT32 -to CFG_DATA[1]
+#set_location_assignment PIN_BB33 -to CFG_DATA[2]
+#set_location_assignment PIN_BA33 -to CFG_DATA[3]
+
+
+
+
+# IO Standard Assignments from Gijs (excluding memory)
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[1](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[0]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGOUT[1]
+set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[1](n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ID[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to INTA
+set_instance_assignment -name IO_STANDARD "1.8 V" -to INTB
+set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SC
+set_instance_assignment -name IO_STANDARD "1.8 V" -to SENS_SD
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to TESTIO[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to WDI
+
+# locations changed 30 sept
+set_location_assignment PIN_P16 -to ID[0]
+set_location_assignment PIN_P15 -to ID[1]
+set_location_assignment PIN_K13 -to ID[2]
+set_location_assignment PIN_L13 -to ID[3]
+set_location_assignment PIN_N16 -to ID[4]
+set_location_assignment PIN_N14 -to ID[5]
+set_location_assignment PIN_U13 -to ID[6]
+
+set_location_assignment PIN_T13 -to ID[7]
+set_location_assignment PIN_AU31 -to INTA
+set_location_assignment PIN_AR30 -to INTB
+
+set_location_assignment PIN_BC31 -to SENS_SC
+set_location_assignment PIN_BB31 -to SENS_SD
+
+set_location_assignment PIN_BA25 -to PMBUS_SC
+set_location_assignment PIN_BD25 -to PMBUS_SD
+set_location_assignment PIN_BD26 -to PMBUS_ALERT
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
+set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
+
+
+set_location_assignment PIN_AN32 -to TESTIO[0]
+set_location_assignment PIN_AP32 -to TESTIO[1]
+set_location_assignment PIN_AT30 -to TESTIO[2]
+set_location_assignment PIN_BD31 -to TESTIO[3]
+set_location_assignment PIN_AU30 -to TESTIO[4]
+set_location_assignment PIN_BD30 -to TESTIO[5]
+
+set_location_assignment PIN_AB12 -to VERSION[0]
+set_location_assignment PIN_AB13 -to VERSION[1]
+set_location_assignment PIN_BB30 -to WDI
+
+set_location_assignment PIN_K12 -to ETH_SGIN[0]
+set_location_assignment PIN_J12 -to "ETH_SGIN[0](n)"
+set_location_assignment PIN_AF33 -to ETH_SGIN[1]
+set_location_assignment PIN_AE33 -to "ETH_SGIN[1](n)"
+set_location_assignment PIN_H13 -to ETH_SGOUT[0]
+set_location_assignment PIN_H12 -to "ETH_SGOUT[0](n)"
+set_location_assignment PIN_AW31 -to ETH_SGOUT[1]
+set_location_assignment PIN_AV31 -to "ETH_SGOUT[1](n)"
+
+set_instance_assignment -name IO_STANDARD LVDS -to PPS
+set_instance_assignment -name IO_STANDARD LVDS -to "PPS(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "CLK(n)"
+
+# Enable internal termination for LVDS inputs
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PPS
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CLK
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ETH_SGIN[0]
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ETH_SGIN[1]
+
+set_location_assignment PIN_AG31 -to altera_reserved_tms
+set_location_assignment PIN_AJ31 -to altera_reserved_tck
+set_location_assignment PIN_AK18 -to altera_reserved_tdi
+set_location_assignment PIN_AH31 -to altera_reserved_ntrst
+set_location_assignment PIN_AM29 -to altera_reserved_tdo
+#set_location_assignment PIN_AV33 -to ~ALTERA_DATA0~
+
+
+set_location_assignment PIN_BA33 -to QSFP_LED[0]
+set_location_assignment PIN_BA30 -to QSFP_LED[1]
+set_location_assignment PIN_BB33 -to QSFP_LED[2]
+set_location_assignment PIN_AU33 -to QSFP_LED[3]
+set_location_assignment PIN_AV32 -to QSFP_LED[4]
+set_location_assignment PIN_AW30 -to QSFP_LED[5]
+set_location_assignment PIN_AP31 -to QSFP_LED[6]
+set_location_assignment PIN_AP30 -to QSFP_LED[7]
+set_location_assignment PIN_AT33 -to QSFP_LED[8]
+set_location_assignment PIN_AG32 -to QSFP_LED[9]
+set_location_assignment PIN_AF32 -to QSFP_LED[10]
+set_location_assignment PIN_AE32 -to QSFP_LED[11]
+
+
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/sfl_enhanced_01_02e360dd.sof b/boards/uniboard2a/libraries/unb2a_board/quartus/sfl_enhanced_01_02e360dd.sof
new file mode 100644
index 0000000000000000000000000000000000000000..a044a591af588213211d3da3002523f5ccdfa399
Binary files /dev/null and b/boards/uniboard2a/libraries/unb2a_board/quartus/sfl_enhanced_01_02e360dd.sof differ
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.qsf b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..577051cd04ca496483104ac833348cdca94c10c4
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.qsf
@@ -0,0 +1,113 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# This QSF is sourced by other design QSF files.
+# ==============================================
+# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+
+# Device:
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115U4F45I3SGES
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+#set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
+#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQL1024
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
+#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_12_5MHZ
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_25MHZ
+#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
+
+set_global_assignment -name USER_START_UP_CLOCK OFF
+
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
+
+set_global_assignment -name HEX_FILE pm_uc_ES1_ww05p1.hex
+set_global_assignment -name SOURCE_FILE quartus.ini
+
+#set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
+#set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
+#set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5P0 -section_id eda_board_design_signal_integrity
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+
+# Optimize for performance:
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+
+# To set a location assignment for a PLL, do the following:
+# - after compilation, open the chip planner
+# - hover over the ATX PLL block (left side or right side)
+# - Right click and click "Copy tooltip"
+# - Paste text in here and edit
+#set_location_assignment HSSIPMALCPLL_X0_Y33_N29 -to "unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:\gen_phy_24:u_ip_arria10_transceiver_pll_10g_0|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"
+
+
+
+#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0"
+#set_parameter -name dbg_user_identifier 0 -to "\\Generate_XCVR_LANE_INSTANCES:0:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
+#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
+
+set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
+set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
+
+set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
+set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
+
+
+# Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
+if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
+ set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
+ set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
+ post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+}
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.sdc b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..c6d9c5a0ee5cfa0b8c12bddce73ad21b1b9b4398
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board.sdc
@@ -0,0 +1,74 @@
+###############################################################################
+#
+# Copyright (C) 2013
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+set_time_format -unit ns -decimal_places 3
+
+create_clock -period 125Mhz [get_ports {ETH_CLK}]
+create_clock -period 200Mhz [get_ports {CLK}]
+create_clock -period 100Mhz [get_ports {CLKUSR}]
+create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
+create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
+create_clock -period 1.552 -name {BCK_REF_CLK} { BCK_REF_CLK }
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group {CLK}
+set_clock_groups -asynchronous -group {ETH_CLK}
+set_clock_groups -asynchronous -group {BCK_REF_CLK}
+set_clock_groups -asynchronous -group {CLK_USR}
+set_clock_groups -asynchronous -group {CLKUSR}
+set_clock_groups -asynchronous -group {SA_CLK}
+set_clock_groups -asynchronous -group {SB_CLK}
+
+# IOPLL outputs (which have global names defined in the IP qsys settings)
+set_clock_groups -asynchronous -group [get_clocks pll_clk20]
+set_clock_groups -asynchronous -group [get_clocks pll_clk50]
+set_clock_groups -asynchronous -group [get_clocks pll_clk100]
+set_clock_groups -asynchronous -group [get_clocks pll_clk125]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
+set_clock_groups -asynchronous -group [get_clocks pll_clk400]
+
+
+# FPLL outputs
+set_clock_groups -asynchronous -group [get_clocks {*u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {*u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk3}]
+set_clock_groups -asynchronous -group [get_clocks {*u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
+
+
+set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_tr_10GbE_0|u_tech_eth_10g|\gen_ip_arria10:u0|u_tech_10gbase_r|\gen_ip_arria10:u0|\gen_phy_12:u_ip_arria10_phy_10gbase_r_12|xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
+set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
+set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
+
+
+#set_clock_groups -asynchronous \
+#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
+#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
+
+
+#JTAG Signal Constraints
+#constrain the TDI TMS and TDO ports -- (modified from timequest SDC cookbook)
+#set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi]
+#set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms]
+#set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo]
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v0_fpga_device_family.JPG b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v0_fpga_device_family.JPG
new file mode 100644
index 0000000000000000000000000000000000000000..f50d11684f4abad160db1a44556541c969d49e6e
Binary files /dev/null and b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v0_fpga_device_family.JPG differ
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v1_fpga_device_family.jpg b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v1_fpga_device_family.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..cbe907cf5705a8d93e7725dc5bbc6ba8cf66e27f
Binary files /dev/null and b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2_board_v1_fpga_device_family.jpg differ
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..bfee21d190540c1387812aaf8cdca87941c1a60c
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
@@ -0,0 +1,115 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# This QSF is sourced by other design QSF files.
+# ==============================================
+# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
+# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL)" do not work.
+
+set_parameter -name g_technology c_tech_arria10_e3sge3
+
+# Device:
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115U4F45E3SGE3
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+#set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
+#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQL1024
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
+#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_12_5MHZ
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_25MHZ
+#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
+
+set_global_assignment -name USER_START_UP_CLOCK OFF
+
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
+
+set_global_assignment -name HEX_FILE pm_uc_ES1_ww05p1.hex
+set_global_assignment -name SOURCE_FILE quartus.ini
+
+#set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
+#set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
+#set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5P0 -section_id eda_board_design_signal_integrity
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+
+# Optimize for performance:
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+
+# To set a location assignment for a PLL, do the following:
+# - after compilation, open the chip planner
+# - hover over the ATX PLL block (left side or right side)
+# - Right click and click "Copy tooltip"
+# - Paste text in here and edit
+#set_location_assignment HSSIPMALCPLL_X0_Y33_N29 -to "unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:\gen_phy_24:u_ip_arria10_transceiver_pll_10g_0|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst"
+
+
+
+#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0"
+#set_parameter -name dbg_user_identifier 0 -to "\\Generate_XCVR_LANE_INSTANCES:0:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
+#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
+
+set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
+set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
+
+set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
+set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
+
+
+# Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
+if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
+ set_parameter -name g_stamp_date [clock format [clock seconds] -format {%Y%m%d}]
+ set_parameter -name g_stamp_time [clock format [clock seconds] -format {%H%M%S}]
+ post_message -type info "RADIOHDL: using SVN $::env(RADIOHDL_SVN_REVISION)"
+ set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""]
+}
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9f19b28b1cfe24596f469a61e81a4b9fa0fe870f
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
@@ -0,0 +1,804 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Provide general control infrastructure
+-- Usage: In a design <design_name>.vhd that consists of:
+-- . mmm_<design_name>.vhd with a Nios2 and the MM bus and the peripherals
+-- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
+
+LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
+USE i2c_lib.i2c_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
+ENTITY ctrl_unb2_board IS
+ GENERIC (
+ ----------------------------------------------------------------------------
+ -- General
+ ----------------------------------------------------------------------------
+ g_technology : NATURAL := c_tech_arria10;
+ g_sim : BOOLEAN := FALSE;
+ g_design_name : STRING := "UNUSED";
+ g_fw_version : t_unb2_board_fw_version := (0, 0); -- firmware version x.y
+ g_stamp_date : NATURAL := 0;
+ g_stamp_time : NATURAL := 0;
+ g_stamp_svn : NATURAL := 0;
+ g_design_note : STRING := "UNUSED";
+ g_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
+ g_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_125M;
+ g_eth_clk_freq : NATURAL := c_unb2_board_eth_clk_freq_125M;
+ g_tse_clk_buf : BOOLEAN := FALSE;
+
+ ----------------------------------------------------------------------------
+ -- External CLK
+ ----------------------------------------------------------------------------
+ g_dp_clk_freq : NATURAL := c_unb2_board_ext_clk_freq_200M;
+ g_dp_clk_use_pll : BOOLEAN := TRUE;
+ -- PLL phase clk shift with respect to CLK
+ -- STRING := "0" = 0
+ -- STRING := "156" = 011.25
+ -- STRING := "313" = 022.5
+ -- STRING := "469" = 033.75
+ -- STRING := "625" = 045
+ -- STRING := "781" = 056.25
+ -- STRING := "938" = 067.5
+ -- STRING := "1094" = 078.75
+ -- STRING := "1250" = 090
+ -- STRING := "1406" = 1250+ 156 = 101.25
+ -- STRING := "1563" = 1250+ 313 = 112.5
+ -- STRING := "1719" = 1250+ 469 = 123.75
+ -- STRING := "1875" = 1250+ 625 = 135
+ -- STRING := "2031" = 1250+ 781 = 146.25
+ -- STRING := "2188" = 1250+ 938 = 157.5
+ -- STRING := "2344" = 1250+1094 = 168.75
+ -- STRING := "2500" = 1250+1250 = 180
+ -- STRING := "2656" = 2500+ 156 = 191.25
+ -- STRING := "2813" = 2500+ 313 = 202.5
+ -- STRING := "2969" = 2500+ 469 = 213.75
+ -- STRING := "3125" = 2500+ 625 = 225
+ -- STRING := "3281" = 2500+ 781 = 236.25
+ -- STRING := "3438" = 2500+ 938 = 247.5
+ -- STRING := "3594" = 2500+1094 = 258.75
+ -- STRING := "3750" = 2500+1250 = 270
+ -- STRING := "3906" = 3750+ 156 = 281.25
+ -- STRING := "4063" = 3750+ 313 = 292.5
+ -- STRING := "4219" = 3750+ 469 = 303.75
+ -- STRING := "4375" = 3750+ 625 = 315
+ -- STRING := "4531" = 3750+ 781 = 326.25
+ -- STRING := "4688" = 3750+ 938 = 337.5
+ -- STRING := "4844" = 3750+1094 = 348.75
+ -- STRING := "5000" = 3750+1250 = 360
+ g_dp_clk_phase : STRING := "0"; -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+
+ ----------------------------------------------------------------------------
+ -- 1GbE UDP offload
+ ----------------------------------------------------------------------------
+ g_udp_offload : BOOLEAN := FALSE;
+ g_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
+
+ ----------------------------------------------------------------------------
+ -- Auxiliary Interface
+ ----------------------------------------------------------------------------
+ g_fpga_temp_high : NATURAL := 85;
+ g_app_led_red : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_red
+ g_app_led_green : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_green
+
+ g_aux : t_c_unb2_board_aux := c_unb2_board_aux;
+ g_factory_image : BOOLEAN := FALSE
+ );
+ PORT (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim : OUT STD_LOGIC;
+
+ xo_ethclk : OUT STD_LOGIC; -- 125 MHz ETH_CLK
+ xo_rst : OUT STD_LOGIC; -- reset in ETH_CLK domain released after few cycles
+ xo_rst_n : OUT STD_LOGIC;
+
+ ext_clk200 : OUT STD_LOGIC; -- 200 MHz CLK
+ ext_rst200 : OUT STD_LOGIC; -- reset in CLK clock domain released after mm_rst
+
+ mm_clk : OUT STD_LOGIC; -- MM clock from xo_ethclk PLL
+ mm_rst : OUT STD_LOGIC; -- reset in MM clock domain released after xo_ethclk PLL locked
+
+ dp_rst : OUT STD_LOGIC; -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
+ dp_clk : OUT STD_LOGIC; -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
+ dp_pps : OUT STD_LOGIC; -- PPS in dp_clk domain
+ dp_rst_in : IN STD_LOGIC; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_clk_in : IN STD_LOGIC; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
+
+ mb_I_ref_rst : OUT STD_LOGIC; -- reset in MB_I_REF_CLK domain released after mm_rst
+ mb_II_ref_rst : OUT STD_LOGIC; -- reset in MB_II_REF_CLK domain released after mm_rst
+
+ this_chip_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0); -- [1:0], so range 0-3 for PN
+ this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+
+ app_led_red : IN STD_LOGIC := '0';
+ app_led_green : IN STD_LOGIC := '1';
+
+ -- PIOs
+ pout_wdi : IN STD_LOGIC; -- Toggled by unb_osy; can be overriden by reg_wdi.
+
+ -- Manual WDI override
+ reg_wdi_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_wdi_miso : OUT t_mem_miso;
+
+ -- REMU
+ reg_remu_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_remu_miso : OUT t_mem_miso;
+
+ -- EPCS read
+ reg_dpmm_data_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dpmm_data_miso : OUT t_mem_miso;
+ reg_dpmm_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dpmm_ctrl_miso : OUT t_mem_miso;
+
+ -- EPCS write
+ reg_mmdp_data_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_mmdp_data_miso : OUT t_mem_miso;
+ reg_mmdp_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_mmdp_ctrl_miso : OUT t_mem_miso;
+
+ -- EPCS status/control
+ reg_epcs_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_epcs_miso : OUT t_mem_miso;
+
+ -- MM buses to/from mms_unb2_board_system_info
+ reg_unb_system_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_unb_system_info_miso : OUT t_mem_miso;
+
+ rom_unb_system_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ rom_unb_system_info_miso : OUT t_mem_miso;
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_unb_sens_miso : OUT t_mem_miso;
+
+ reg_unb_pmbus_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_unb_pmbus_miso : OUT t_mem_miso;
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_fpga_temp_sens_miso : OUT t_mem_miso;
+ reg_fpga_voltage_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_fpga_voltage_sens_miso : OUT t_mem_miso;
+
+ -- PPSH
+ reg_ppsh_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_ppsh_miso : OUT t_mem_miso;
+
+ -- eth1g control&monitoring
+ eth1g_mm_rst : IN STD_LOGIC;
+ eth1g_tse_mosi : IN t_mem_mosi; -- ETH TSE MAC registers
+ eth1g_tse_miso : OUT t_mem_miso;
+ eth1g_reg_mosi : IN t_mem_mosi; -- ETH control and status registers
+ eth1g_reg_miso : OUT t_mem_miso;
+ eth1g_reg_interrupt : OUT STD_LOGIC; -- Interrupt
+ eth1g_ram_mosi : IN t_mem_mosi; -- ETH rx frame and tx frame memory
+ eth1g_ram_miso : OUT t_mem_miso;
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr : IN t_dp_sosi_arr(g_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ udp_tx_siso_arr : OUT t_dp_siso_arr(g_udp_offload_nof_streams-1 DOWNTO 0);
+ udp_rx_sosi_arr : OUT t_dp_sosi_arr(g_udp_offload_nof_streams-1 DOWNTO 0);
+ udp_rx_siso_arr : IN t_dp_siso_arr(g_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+
+ --
+ -- >>> Ctrl FPGA pins
+ --
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC := 'H';
+ SENS_SD : INOUT STD_LOGIC := 'H';
+
+ -- pmbus
+ PMBUS_SC : INOUT STD_LOGIC := 'H';
+ PMBUS_SD : INOUT STD_LOGIC := 'H';
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- DDR reference clock domains reset creation
+ MB_I_REF_CLK : IN STD_LOGIC := '0'; -- 25 MHz
+ MB_II_REF_CLK : IN STD_LOGIC := '0'; -- 25 MHz
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC; -- 125 MHz
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
+ );
+END ctrl_unb2_board;
+
+
+ARCHITECTURE str OF ctrl_unb2_board IS
+
+ CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
+
+ -- Clock and reset
+ SIGNAL i_ext_clk200 : STD_LOGIC;
+ SIGNAL ext_pps : STD_LOGIC;
+
+ SIGNAL i_xo_ethclk : STD_LOGIC;
+ SIGNAL i_xo_rst : STD_LOGIC;
+ SIGNAL i_mm_rst : STD_LOGIC;
+ SIGNAL i_mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_sim_clk : STD_LOGIC := '1';
+ SIGNAL epcs_clk : STD_LOGIC := '1';
+ SIGNAL clk125 : STD_LOGIC := '1';
+ SIGNAL clk100 : STD_LOGIC := '1';
+ SIGNAL clk50 : STD_LOGIC := '1';
+
+ SIGNAL mm_wdi : STD_LOGIC;
+
+ SIGNAL mm_pulse_ms : STD_LOGIC;
+ SIGNAL mm_pulse_s : STD_LOGIC;
+ SIGNAL mm_board_sens_start : STD_LOGIC;
+
+ SIGNAL led_toggle : STD_LOGIC;
+ SIGNAL led_toggle_red : STD_LOGIC;
+ SIGNAL led_toggle_green : STD_LOGIC;
+
+ -- eth1g
+ SIGNAL i_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_led : t_tech_tse_led;
+
+ -- Manual WDI override
+ SIGNAL wdi_override : STD_LOGIC;
+
+ -- Temperature alarm (temp > g_fpga_temp_high)
+ SIGNAL temp_alarm : STD_LOGIC;
+
+ -- UDP offload I/O
+ SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+
+BEGIN
+
+ ext_clk200 <= i_ext_clk200;
+ xo_ethclk <= i_xo_ethclk;
+ xo_rst <= i_xo_rst;
+ xo_rst_n <= NOT i_xo_rst;
+ mm_clk <= i_mm_clk;
+ mm_rst <= i_mm_rst;
+
+ -- Default leave unused INOUT tri-state
+ INTA <= 'Z';
+ INTB <= 'Z';
+
+ TESTIO <= (OTHERS=>'Z'); -- Leave unused INOUT tri-state
+
+ ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+
+ -----------------------------------------------------------------------------
+ -- ext_clk200 = CLK
+ -----------------------------------------------------------------------------
+ i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+
+ u_common_areset_ext : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
+
+ -----------------------------------------------------------------------------
+ -- xo_ethclk = ETH_CLK
+ -----------------------------------------------------------------------------
+
+ i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+
+ u_common_areset_xo : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- MB_I_REF_CLK --> mb_I_ref_rst
+ -- MB_II_REF_CLK --> mb_II_ref_rst
+ -----------------------------------------------------------------------------
+
+ u_common_areset_mb_I : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
+
+ u_common_areset_mb_II : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
+
+ -----------------------------------------------------------------------------
+ -- dp_clk
+ -- . release dp_rst some clock cycles after mm_rst went low
+ -----------------------------------------------------------------------------
+
+ gen_dp_clk_sim: IF g_sim = TRUE GENERATE
+ dp_clk <= i_ext_clk200;
+
+ u_common_areset_st : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
+ END GENERATE;
+
+ gen_dp_clk_hardware: IF g_sim = FALSE GENERATE
+ gen_pll: IF g_dp_clk_use_pll = TRUE GENERATE
+ u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_use_fpll => TRUE,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ PORT MAP (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => dp_rst
+ );
+ END GENERATE;
+
+ no_pll: IF g_dp_clk_use_pll = FALSE GENERATE
+ dp_clk <= i_ext_clk200;
+
+ u_common_areset_st : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
+ END GENERATE;
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- mm_clk
+ -- . use mm_sim_clk in sim
+ -- . derived from ETH_CLK via PLL on hardware
+ -----------------------------------------------------------------------------
+
+ i_mm_clk <= mm_sim_clk WHEN g_sim = TRUE ELSE
+ clk125 WHEN g_mm_clk_freq = c_unb2_board_mm_clk_freq_125M ELSE
+ clk100 WHEN g_mm_clk_freq = c_unb2_board_mm_clk_freq_100M ELSE
+ clk50 WHEN g_mm_clk_freq = c_unb2_board_mm_clk_freq_50M ELSE
+ clk50; -- default
+
+ gen_mm_clk_sim: IF g_sim = TRUE GENERATE
+ epcs_clk <= NOT epcs_clk AFTER 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= NOT clk50 AFTER 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= NOT clk100 AFTER 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= NOT clk125 AFTER 4 ns; -- 125 MHz, 8ns/2
+ mm_sim_clk <= NOT mm_sim_clk AFTER 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_locked <= '0', '1' AFTER 70 ns;
+ END GENERATE;
+
+ gen_mm_clk_hardware: IF g_sim = FALSE GENERATE
+ u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
+ GENERIC MAP (
+ g_use_fpll => TRUE,
+ g_technology => g_technology
+ )
+ PORT MAP (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ END GENERATE;
+
+ u_unb2_board_node_ctrl : ENTITY work.unb2_board_node_ctrl
+ GENERIC MAP (
+ g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ PORT MAP (
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- System info
+ -----------------------------------------------------------------------------
+ cs_sim <= is_true(g_sim);
+
+ u_mms_unb2_board_system_info : ENTITY work.mms_unb2_board_system_info
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ PORT MAP (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Red LED control
+ -----------------------------------------------------------------------------
+
+ gen_app_led_red: IF g_app_led_red = TRUE GENERATE
+ -- Let external app control the LED via the app_led_red input
+ TESTIO(c_unb2_board_testio_led_red) <= app_led_red;
+ END GENERATE;
+
+ no_app_led_red: IF g_app_led_red = FALSE GENERATE
+ TESTIO(c_unb2_board_testio_led_red) <= led_toggle_red;
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- Green LED control
+ -----------------------------------------------------------------------------
+
+ gen_app_led_green: IF g_app_led_green = TRUE GENERATE
+ -- Let external app control the LED via the app_led_green input
+ TESTIO(c_unb2_board_testio_led_green) <= app_led_green;
+ END GENERATE;
+
+ no_app_led_green: IF g_app_led_green = FALSE GENERATE
+ TESTIO(c_unb2_board_testio_led_green) <= led_toggle_green;
+ END GENERATE;
+
+
+ ------------------------------------------------------------------------------
+ -- Toggle red LED when unb2_minimal is running, green LED for other designs.
+ ------------------------------------------------------------------------------
+ led_toggle_red <= sel_a_b(g_factory_image=TRUE, led_toggle, '0');
+ led_toggle_green <= sel_a_b(g_factory_image=FALSE, led_toggle, '0');
+
+ u_toggle : ENTITY common_lib.common_toggle
+ PORT MAP (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- WDI override
+ ------------------------------------------------------------------------------
+ -- Actively reset watchdog from software when used, else disable watchdog by leaving the WDI at tri-state level.
+ -- A high temp_alarm will keep WDI asserted, causing the watch dog to reset the FPGA.
+ -- A third option is to override the WDI manually using the output of a dedicated reg_wdi.
+ WDI <= mm_wdi OR temp_alarm OR wdi_override;
+
+ u_unb2_board_wdi_reg : ENTITY work.unb2_board_wdi_reg
+ PORT MAP (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
+
+ wdi_override => wdi_override
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- Remote upgrade
+ ------------------------------------------------------------------------------
+ -- Every design instantiates an mms_remu instance + MM status & control ports.
+ -- So there is full control over the memory mapped registers to set start address of the flash
+ -- and reconfigure from that address.
+ u_mms_remu: ENTITY remu_lib.mms_remu
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ epcs_clk => epcs_clk,
+
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
+
+ -------------------------------------------------------------------------------
+ ---- EPCS
+ -------------------------------------------------------------------------------
+ u_mms_epcs: ENTITY epcs_lib.mms_epcs
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ epcs_clk => epcs_clk,
+
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
+
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
+
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
+
+ ------------------------------------------------------------------------------
+ -- PPS input
+ ------------------------------------------------------------------------------
+
+ u_mms_ppsh : ENTITY ppsh_lib.mms_ppsh
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- I2C control for UniBoard sensors
+ ------------------------------------------------------------------------------
+
+ mm_board_sens_start <= mm_pulse_s WHEN g_sim=FALSE ELSE mm_pulse_ms; -- speed up in simulation
+
+ u_mms_unb2_board_sens : ENTITY work.mms_unb2_board_sens
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_clk_freq => g_mm_clk_freq
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
+
+ u_mms_unb2_board_pmbus : ENTITY work.mms_unb2_board_sens
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_clk_freq => 20 * 10**6 -- (to be checked) this (re)calculation lets the I2C bus run at ~300kHz
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
+
+ u_mms_unb2_fpga_sens : ENTITY work.mms_unb2_fpga_sens
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- Ethernet 1GbE
+ ------------------------------------------------------------------------------
+
+ gen_tse_clk_buf: IF g_tse_clk_buf=TRUE GENERATE
+ -- Separate clkbuf for the 1GbE tse_clk:
+ u_tse_clk_buf : ENTITY tech_clkbuf_lib.tech_clkbuf
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ PORT MAP (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
+ END GENERATE;
+
+ gen_tse_no_clk_buf: IF g_tse_clk_buf=FALSE GENERATE
+ i_tse_clk <= i_xo_ethclk;
+ END GENERATE;
+
+
+ wire_udp_offload: FOR i IN 0 TO g_udp_offload_nof_streams-1 GENERATE
+ eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
+ udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
+
+ udp_rx_sosi_arr(i) <= eth1g_udp_rx_sosi_arr(i);
+ eth1g_udp_rx_siso_arr(i) <= udp_rx_siso_arr(i);
+ END GENERATE;
+
+ -- In simulation use file IO for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
+ no_eth1g : IF g_sim=TRUE AND g_udp_offload=FALSE GENERATE
+ eth1g_reg_interrupt <= '0';
+ eth1g_tse_miso <= c_mem_miso_rst;
+ eth1g_reg_miso <= c_mem_miso_rst;
+ eth1g_ram_miso <= c_mem_miso_rst;
+ END GENERATE;
+
+ --On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
+ gen_eth: IF g_sim=FALSE OR g_udp_offload=TRUE GENERATE
+ u_eth : ENTITY eth_lib.eth
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
+ END GENERATE;
+
+END str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..434fd9359f9f6cf5f7ce72ccffa9ac626a290b73
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -0,0 +1,118 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose : MMS for unb2_board_sens
+-- Description: See unb2_board_sens.vhd
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+
+ENTITY mms_unb2_board_sens IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_clk_freq : NATURAL := 100*10**6; -- clk frequency in Hz
+ g_temp_high : NATURAL := 85
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
+ mm_start : IN STD_LOGIC;
+
+ -- Memory-mapped clock domain
+ reg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
+ reg_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+
+ -- i2c bus
+ scl : INOUT STD_LOGIC := '0';
+ sda : INOUT STD_LOGIC := '0';
+
+ -- Temperature alarm output
+ temp_alarm : OUT STD_LOGIC
+ );
+END mms_unb2_board_sens;
+
+
+ARCHITECTURE str OF mms_unb2_board_sens IS
+
+ CONSTANT c_sens_nof_result : NATURAL := 4; -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ CONSTANT c_temp_high_w : NATURAL := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+
+ SIGNAL sens_err : STD_LOGIC;
+ SIGNAL sens_data : t_slv_8_arr(0 TO c_sens_nof_result-1);
+
+ SIGNAL temp_high : STD_LOGIC_VECTOR(c_temp_high_w-1 DOWNTO 0);
+
+BEGIN
+
+ u_unb2_board_sens_reg : ENTITY work.unb2_board_sens_reg
+ GENERIC MAP (
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
+
+ -- Max temp threshold
+ temp_high => temp_high
+ );
+
+ u_unb2_board_sens : ENTITY work.unb2_board_sens
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => c_sens_nof_result
+ )
+ PORT MAP (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
+
+ -- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
+ -- would produce -1 degrees so does not trigger a temperature alarm.
+ -- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
+ temp_alarm <= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
+
+END str;
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7e70d05b559657793da91a2be966549d49b55ed6
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -0,0 +1,138 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+ENTITY mms_unb2_board_system_info IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_technology : NATURAL := c_tech_arria10;
+ g_design_name : STRING;
+ g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y
+ g_stamp_date : NATURAL := 0;
+ g_stamp_time : NATURAL := 0;
+ g_stamp_svn : NATURAL := 0;
+ g_design_note : STRING := "";
+ g_aux : t_c_unb2_board_aux := c_unb2_board_aux -- aux contains the hardware version
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ -- MM registers
+ reg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_miso : OUT t_mem_miso;
+
+ rom_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ rom_miso : OUT t_mem_miso;
+
+ hw_version : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
+ id : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
+
+ chip_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0);
+ bck_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0);
+
+ -- Info output still supported for older designs
+ info : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
+ );
+END mms_unb2_board_system_info;
+
+
+ARCHITECTURE str OF mms_unb2_board_system_info IS
+
+ -- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
+ -- Required because the work paths of ModelSim and Quartus are different.
+ CONSTANT c_quartus_path_prefix : STRING := "";
+ CONSTANT c_modelsim_path_prefix : STRING := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
+ CONSTANT c_path_prefix : STRING := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
+
+-- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ CONSTANT c_mif_name : STRING := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
+
+ CONSTANT c_rom_addr_w : NATURAL := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
+
+ CONSTANT c_mm_rom : t_c_mem := (latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
+
+ SIGNAL i_info : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+BEGIN
+
+ info <= i_info;
+
+ u_unb2_board_system_info: ENTITY work.unb2_board_system_info
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version
+ )
+ PORT MAP (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
+
+ u_unb2_board_system_info_reg: ENTITY work.unb2_board_system_info_reg
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
+
+ u_common_rom : ENTITY common_lib.common_rom
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w-1 DOWNTO 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w-1 DOWNTO 0),
+ rd_val => rom_miso.rdval
+ );
+
+END str;
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..96ae8dc74dd007749a9ceafa6f9b081e45e2085e
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -0,0 +1,122 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose : MMS for unb2_fpga_sens
+-- Description: See unb2_fpga_sens.vhd
+
+LIBRARY IEEE, technology_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY mms_unb2_fpga_sens IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_technology : NATURAL := c_tech_arria10;
+ g_temp_high : NATURAL := 85
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
+ mm_start : IN STD_LOGIC;
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
+ reg_temp_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+ reg_voltage_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
+ reg_voltage_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+
+ -- Temperature alarm output
+ temp_alarm : OUT STD_LOGIC
+ );
+END mms_unb2_fpga_sens;
+
+
+ARCHITECTURE str OF mms_unb2_fpga_sens IS
+
+ CONSTANT c_sens_nof_result : NATURAL := 1; --
+ CONSTANT c_temp_high_w : NATURAL := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
+
+ SIGNAL sens_err : STD_LOGIC;
+ SIGNAL sens_data : t_slv_8_arr(0 TO c_sens_nof_result-1);
+
+ SIGNAL temp_high : STD_LOGIC_VECTOR(c_temp_high_w-1 DOWNTO 0);
+
+BEGIN
+
+ u_unb2_fpga_sens_reg : ENTITY work.unb2_fpga_sens_reg
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start => mm_start,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_temp_in => reg_temp_mosi,
+ sla_temp_out => reg_temp_miso,
+ sla_voltage_in => reg_voltage_mosi,
+ sla_voltage_out => reg_voltage_miso,
+
+ -- MM registers
+ --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ --sens_data => sens_data,
+
+ -- Max temp threshold
+ temp_high => temp_high
+ );
+
+-- u_unb2_board_sens : ENTITY work.unb2_board_sens
+-- GENERIC MAP (
+-- g_sim => g_sim,
+-- g_clk_freq => g_clk_freq,
+-- g_temp_high => g_temp_high,
+-- g_sens_nof_result => c_sens_nof_result
+-- )
+-- PORT MAP (
+-- clk => mm_clk,
+-- rst => mm_rst,
+-- start => mm_start,
+-- -- i2c bus
+-- scl => scl,
+-- sda => sda,
+-- -- read results
+-- sens_evt => OPEN,
+-- sens_err => sens_err,
+-- sens_data => sens_data
+-- );
+
+ -- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
+ -- would produce -1 degrees so does not trigger a temperature alarm.
+ -- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
+ temp_alarm <= '0';--<= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
+
+END str;
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8142ed4527a9840b4b19c806788f9fb1da0b1737
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
@@ -0,0 +1,68 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_back_io IS
+ GENERIC (
+ g_nof_back_bus : NATURAL := c_unb2_board_tr_back.nof_bus
+ );
+ PORT (
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_back_bus * c_unb2_board_tr_back.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_back_bus * c_unb2_board_tr_back.bus_w-1 DOWNTO 0);
+
+ -- back transceivers
+ BCK_RX : IN t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ BCK_TX : OUT t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
+
+ BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0);
+ BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0);
+ BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 DOWNTO 0)
+ );
+END unb2_board_back_io;
+
+ARCHITECTURE str OF unb2_board_back_io IS
+
+ -- help signals so we can iterate through buses
+ SIGNAL si_tx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
+
+BEGIN
+
+ gen_buses : FOR i IN 0 TO g_nof_back_bus-1 GENERATE
+ BCK_TX(i) <= si_tx_2arr(i);
+ si_rx_2arr(i) <= BCK_RX(i);
+ END GENERATE;
+
+
+ gen_wire_bus : FOR i IN 0 TO g_nof_back_bus-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_back.bus_w-1 GENERATE
+
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_back.bus_w + j);
+ serial_rx_arr(i*c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
+
+ END GENERATE;
+ END GENERATE;
+
+END;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..858cc68b92013637641691b30cdb7eb3bf206202
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -0,0 +1,110 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
+-- Description:
+-- c0 = 20 MHz
+-- c1 = 50 MHz
+-- c2 = 100 MHz
+-- c3 = 125 MHz
+--
+
+ENTITY unb2_board_clk125_pll IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_arria10;
+ g_use_clkbuf : BOOLEAN := TRUE;
+ g_use_fpll : BOOLEAN := FALSE
+ );
+ PORT (
+ arst : IN STD_LOGIC := '0';
+ clk125 : IN STD_LOGIC := '0'; -- connect to UniBoard ETH_clk pin (125 MHz)
+
+ c0_clk20 : OUT STD_LOGIC; -- PLL c0
+ c1_clk50 : OUT STD_LOGIC; -- PLL c1
+ c2_clk100 : OUT STD_LOGIC; -- PLL c2
+ c3_clk125 : OUT STD_LOGIC; -- PLL c3
+ pll_locked : OUT STD_LOGIC
+ );
+END unb2_board_clk125_pll;
+
+
+ARCHITECTURE arria10 OF unb2_board_clk125_pll IS
+
+ SIGNAL clk125buf : STD_LOGIC;
+
+BEGIN
+
+ no_clkbuf : IF g_use_clkbuf=FALSE GENERATE
+ clk125buf <= clk125;
+ END GENERATE;
+
+ gen_clkbuf : IF g_use_clkbuf=TRUE GENERATE
+ u_clkbuf : ENTITY tech_clkbuf_lib.tech_clkbuf
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ PORT MAP (
+ inclk => clk125,
+ outclk => clk125buf
+ );
+ END GENERATE;
+
+
+ gen_pll : IF g_use_fpll=FALSE GENERATE
+ u_pll : ENTITY tech_pll_lib.tech_pll_clk125
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
+ END GENERATE;
+
+ gen_fractional_pll : IF g_use_fpll=TRUE GENERATE
+ u_pll : ENTITY tech_fractional_pll_lib.tech_fractional_pll_clk125
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
+ END GENERATE;
+
+END arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..63e575d26d41b00f75fa42ee937f963b5cf02aac
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -0,0 +1,222 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
+-- Description:
+-- . The PLL runs in normal mode using c0 to compensate for the internal clock
+-- network delay, so that c0 = st_clk200 is aligned to the input clk200.
+-- . The assumption is that default the streaming DSP will run on the 200 MHz
+-- clock from the CLK input via c1 = st_clk200p.
+-- . The PLL normal mode operation compensates for internal clock network
+-- delays of c0. This compensations aligns c0 to inclk0. With
+-- tb_unb2_board_clk200_pll.vhd it appears that the phase setting for c0 does
+-- not influence the compensation. Therefore it is llso possible to use
+-- g_clk200_phase_shift /= 0 and touse c0 as processing clock instead of c1.
+-- . The phase offset of c0 and c1 in the clk200_pll MegaWizard component
+-- can be set in steps of 11.25 degrees (and even finer):
+-- g_clk200_phase_shift (for c0)
+-- phase [degrees] g_clk200p_phase_shift (for c1)
+-- 0 "0"
+-- 11.25 "156"
+-- 22.5 "313"
+-- 33.75 "469"
+-- 45 "625"
+-- 56.25 "781"
+-- 67.5 "938"
+-- 78.75 "1094"
+-- 90 "1250"
+-- 101.25 "1406" = 1250+ 156
+-- 112.5 "1563" = 1250+ 313
+-- 123.75 "1719" = 1250+ 469
+-- 135 "1875" = 1250+ 625
+-- 146.25 "2031" = 1250+ 781
+-- 157.5 "2188" = 1250+ 938
+-- 168.75 "2344" = 1250+1094
+-- 180 "2500" = 1250+1250
+-- 191.25 "2656" = 2500+ 156
+-- 202.5 "2813" = 2500+ 313
+-- 213.75 "2969" = 2500+ 469
+-- 225 "3125" = 2500+ 625
+-- 236.25 "3281" = 2500+ 781
+-- 247.5 "3438" = 2500+ 938
+-- 258.75 "3594" = 2500+1094
+-- 270 "3750" = 2500+1250
+-- 281.25 "3906" = 3750+ 156
+-- 292.5 "4063" = 3750+ 313
+-- 303.75 "4219" = 3750+ 469
+-- 315 "4375" = 3750+ 625
+-- 326.25 "4531" = 3750+ 781
+-- 337.5 "4688" = 3750+ 938
+-- 348.75 "4844" = 3750+1094
+-- 360 "5000" = 3750+1250
+-- . With a phase offset of 22.5 degrees the c1 = clk200p is offset by a 1/16
+-- period of 200 MHz, so 1/8 period of the 400 MHz DCLK from ADU and 1/4
+-- period of the 800 MHz sample SCLK of ADU. This phase offset can be used
+-- to achieve stable timing between the DCLK and the clk200p domain.
+-- . Some DSP may also be possible at 400 MHz via st_clk400. Note that this
+-- 400 MHz can also be used at places where only a little more than 200 MHz
+-- would be needed, e.g. to create packets at full data rate.
+-- Therefore it is not necessary to create yet another st clock frequency.
+-- This to also avoid the EMI or RFI that a non integer factor of 200 MHz
+-- like e.g. 250 MHz would cause.
+-- . At 400 MHz ADC samples can be clocked in at 800 MSps using DDIO. At 800
+-- MSps the sample period is 1250 ns. Input timing can be tuned via fixed
+-- pad input delays and/or by using another phase of the PLL output clock.
+-- Remarks:
+-- . If necessary more 400 M clock phase could be made available, via g_sel.
+--
+
+ENTITY unb2_board_clk200_pll IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_arria10;
+ g_use_clkbuf : BOOLEAN := TRUE;
+ g_use_fpll : BOOLEAN := FALSE;
+ g_operation_mode : STRING := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
+ g_clk200_phase_shift : STRING := "0"; -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ g_clk200p_phase_shift : STRING := "0" -- default use 0 degrees, see clk200_pll.vhd for other phase values
+ );
+ PORT (
+ -- It depends on g_sel which outputs are actually available
+ -- . common
+ arst : IN STD_LOGIC := '0';
+ clk200 : IN STD_LOGIC := '0'; -- connect to UniBoard CLK pin
+ st_clk200 : OUT STD_LOGIC; -- PLL c0 = g_clk200_phase_shift degrees phase offset to input clk200
+ st_rst200 : OUT STD_LOGIC;
+ st_clk200p : OUT STD_LOGIC; -- PLL c1 = g_clk200p_phase_shift degrees phase offset to input clk200 (see clk200_pll.vhd from MegaWizard)
+ st_rst200p : OUT STD_LOGIC;
+ st_clk400 : OUT STD_LOGIC; -- PLL c2 = 0 degrees phase offset to input clk200
+ st_rst400 : OUT STD_LOGIC
+ );
+END unb2_board_clk200_pll;
+
+
+ARCHITECTURE arria10 OF unb2_board_clk200_pll IS
+
+ CONSTANT c_reset_len : NATURAL := c_meta_delay_len;
+
+ SIGNAL clk200buf : STD_LOGIC;
+ SIGNAL i_st_rst200 : STD_LOGIC;
+ SIGNAL i_st_clk200 : STD_LOGIC;
+ SIGNAL i_st_clk200p : STD_LOGIC;
+ SIGNAL i_st_clk400 : STD_LOGIC;
+
+ SIGNAL st_locked : STD_LOGIC;
+ SIGNAL st_locked_n : STD_LOGIC;
+
+BEGIN
+
+ st_rst200 <= i_st_rst200;
+ st_clk200 <= i_st_clk200;
+ st_clk200p <= i_st_clk200p;
+ st_clk400 <= i_st_clk400;
+
+ no_clkbuf : IF g_use_clkbuf=FALSE GENERATE
+ clk200buf <= clk200;
+ END GENERATE;
+
+ gen_clkbuf : IF g_use_clkbuf=TRUE GENERATE
+ u_clkbuf : ENTITY tech_clkbuf_lib.tech_clkbuf
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ PORT MAP (
+ inclk => clk200,
+ outclk => clk200buf
+ );
+ END GENERATE;
+
+ gen_st_pll : IF g_use_fpll=FALSE GENERATE
+ u_st_pll : ENTITY tech_pll_lib.tech_pll_clk200
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ PORT MAP (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
+ END GENERATE;
+
+ gen_st_fractional_pll : IF g_use_fpll=TRUE GENERATE
+ u_st_fractional_pll : ENTITY tech_fractional_pll_lib.tech_fractional_pll_clk200
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
+ END GENERATE;
+
+ -- Release clock domain resets after some clock cycles when the PLL has locked
+ st_locked_n <= NOT st_locked;
+
+ u_rst200 : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
+
+ u_rst200p : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
+
+ u_rst400 : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
+
+END arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a4f7612305993083e11746a92216ab1586e1126c
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -0,0 +1,69 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib, tech_pll_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
+-- Description:
+-- c0 = 20 MHz
+-- c1 = 50 MHz
+-- c2 = 100 MHz
+-- c3 = 125 MHz
+--
+
+ENTITY unb2_board_clk25_pll IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_arria10
+ );
+ PORT (
+ arst : IN STD_LOGIC := '0';
+ clk25 : IN STD_LOGIC := '0'; -- connect to UniBoard ETH_clk pin (25 MHz)
+
+ c0_clk20 : OUT STD_LOGIC; -- PLL c0
+ c1_clk50 : OUT STD_LOGIC; -- PLL c1
+ c2_clk100 : OUT STD_LOGIC; -- PLL c2
+ c3_clk125 : OUT STD_LOGIC; -- PLL c3
+ pll_locked : OUT STD_LOGIC
+ );
+END unb2_board_clk25_pll;
+
+
+ARCHITECTURE arria10 OF unb2_board_clk25_pll IS
+BEGIN
+
+ u_pll : ENTITY tech_pll_lib.tech_pll_clk25
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
+END arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..561075cf83b12b408cda4871c1272434f693beeb
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -0,0 +1,86 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Purpose:
+-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
+-- reset_n).
+-- 2) sys_rst released when the sys_clk PLL from the SOPC system has locked,
+-- can be used as a system reset for the sys_clk domain.
+
+ENTITY unb2_board_clk_rst IS
+ PORT (
+ -- Reference clock and reset to SOPC system PLL
+ xo_clk : IN STD_LOGIC; -- reference XO clock (e.g. 25 MHz also use by PLL in SOPC)
+ xo_rst_n : OUT STD_LOGIC; -- NOT xo_rst (e.g. to reset the SOPC with NIOS2 uP)
+ -- System clock and locked from SOPC system PLL
+ sys_clk : IN STD_LOGIC; -- system clock derived from the reference XO clock (e.g. 125 MHz by a PLL from SOPC with NIOS2 uP)
+ sys_locked : IN STD_LOGIC; -- system clock PLL locked
+ sys_rst : OUT STD_LOGIC -- system reset released some cycles after the system clock PLL has in locked
+ );
+END unb2_board_clk_rst;
+
+
+ARCHITECTURE str OF unb2_board_clk_rst IS
+
+ CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
+
+ -- XO clock domain
+ SIGNAL xo_rst : STD_LOGIC; -- initial reset released after some XO clock cycles
+
+ -- SYS clock domain
+ SIGNAL sys_locked_n : STD_LOGIC;
+
+BEGIN
+
+ -- Reference clock and reset to SOPC system PLL
+ xo_rst_n <= NOT xo_rst;
+
+ u_common_areset_xo : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
+
+ -- System clock from SOPC system PLL and system reset
+ sys_locked_n <= NOT sys_locked;
+
+ u_common_areset_sys : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
+
+END str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..73927379317d0a4639fbd006f8af9da384338e59
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
@@ -0,0 +1,78 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_front_io IS
+ GENERIC (
+ g_nof_qsfp_bus : NATURAL := c_unb2_board_tr_qsfp.nof_bus
+ );
+ PORT (
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp_bus * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+ green_led_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>'0');
+ red_led_arr : IN STD_LOGIC_VECTOR(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>'0');
+
+ QSFP_RX : IN t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ QSFP_TX : OUT t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
+
+ --QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ --QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ --QSFP_RST : INOUT STD_LOGIC;
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2_board_front_io;
+
+ARCHITECTURE str OF unb2_board_front_io IS
+
+ -- help signals so we can iterate through buses
+ SIGNAL si_tx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
+
+BEGIN
+
+ gen_leds : FOR i IN 0 TO g_nof_qsfp_bus-1 GENERATE
+ QSFP_LED(i*2) <= green_led_arr(i);
+ QSFP_LED(i*2+1) <= red_led_arr(i);
+ END GENERATE;
+
+
+ gen_buses : FOR i IN 0 TO g_nof_qsfp_bus-1 GENERATE
+ QSFP_TX(i) <= si_tx_2arr(i);
+ si_rx_2arr(i) <= QSFP_RX(i);
+ END GENERATE;
+
+
+ gen_wire_bus : FOR i IN 0 TO g_nof_qsfp_bus-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_qsfp.bus_w-1 GENERATE
+
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i*c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+
+ END GENERATE;
+ END GENERATE;
+
+END;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..afe1feab4e4d7fc402bc8adc4a0519c823ab754c
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -0,0 +1,114 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
+-- Description:
+-- . Create mm_rst for mm_clk:
+-- . Extend WDI to avoid watchdog reset during software reload
+-- . Pulse every 1 us, 1 ms and 1 s
+
+ENTITY unb2_board_node_ctrl IS
+ GENERIC (
+ g_pulse_us : NATURAL := 125; -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ g_pulse_ms : NATURAL := 1000; -- nof pulse_us pulses to get ms period (fixed, use less to speed up simulation)
+ g_pulse_s : NATURAL := 1000; -- nof pulse_ms pulses to get s period (fixed, use less to speed up simulation)
+ g_wdi_extend_w : NATURAL := 14 -- extend the mm_wdi_in by toggling the mm_wdi_out for about 2**(14-1)= 8 s more
+ );
+ PORT (
+ -- MM clock domain reset
+ mm_clk : IN STD_LOGIC; -- MM clock
+ mm_locked : IN STD_LOGIC := '1'; -- MM clock PLL locked (or use default '1')
+ mm_rst : OUT STD_LOGIC; -- MM reset released after MM clock PLL has locked
+
+ -- WDI extend
+ mm_wdi_in : IN STD_LOGIC; -- from software running on the NIOS2 in the SOPC design
+ mm_wdi_out : OUT STD_LOGIC; -- to FPGA pin
+
+ -- Pulses
+ mm_pulse_us : OUT STD_LOGIC; -- pulses every us
+ mm_pulse_ms : OUT STD_LOGIC; -- pulses every ms
+ mm_pulse_s : OUT STD_LOGIC -- pulses every s
+ );
+END unb2_board_node_ctrl;
+
+
+ARCHITECTURE str OF unb2_board_node_ctrl IS
+
+ CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
+
+ SIGNAL mm_locked_n : STD_LOGIC;
+ SIGNAL i_mm_rst : STD_LOGIC;
+ SIGNAL i_mm_pulse_ms : STD_LOGIC;
+
+BEGIN
+
+ -- Create mm_rst reset in mm_clk domain based on mm_locked
+ mm_rst <= i_mm_rst;
+
+ mm_locked_n <= NOT mm_locked;
+
+ u_common_areset_mm : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
+
+ -- Create 1 pulse per us, per ms and per s
+ mm_pulse_ms <= i_mm_pulse_ms;
+
+ u_common_pulser_us_ms_s : ENTITY common_lib.common_pulser_us_ms_s
+ GENERIC MAP (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ PORT MAP (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
+
+ -- Toggle the WDI every 1 ms
+ u_unb2_board_wdi_extend : ENTITY work.unb2_board_wdi_extend
+ GENERIC MAP (
+ g_extend_w => g_wdi_extend_w
+ )
+ PORT MAP (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
+
+END str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..179be05dab124343bbccaaed2cd35aded8dde543
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -0,0 +1,173 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009-2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Central location for collecting the peripheral MM register widths
+-- Description:
+-- The MM register width can be fixed or application dependent. When the MM
+-- register width is fixed it can be defined as a local constant in the
+-- module *_reg.vhd file or it may be defined in a module package.
+-- When modules are used in a design the MM register widths are needed to
+-- connect the 'node' part of the design to the 'sopc' part. Most designs do
+-- use the same widths also for the variable width MM registers. Therefore
+-- rather then obtaining the variable MM register widths from local design
+-- constants and the fixed widths from module packages, it seems easier to
+-- collect them here in t_c_unb2_board_peripherals_mm_reg.
+-- Remarks:
+-- . The c_unb2_board_peripherals_mm_reg_default suits most designs, if
+-- necessary design specific t_c_unb2_board_peripherals_mm_reg constants
+-- can be defined here as well.
+-- . If some design would need different widths for multiple instances, then
+-- these widths need to be defined locally in that design.
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE unb2_board_peripherals_pkg IS
+
+
+ -- *_adr_w : Actual MM address widths
+ -- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
+ TYPE t_c_unb2_board_peripherals_mm_reg IS RECORD
+ cross_clock_domain : BOOLEAN; -- = TRUE -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
+
+ -- 1GbE
+ reg_tse_adr_w : NATURAL; -- = 10 -- = c_tse_byte_addr_w from tse_pkg.vhd
+ reg_eth_adr_w : NATURAL; -- = 4 -- = c_eth_reg_addr_w from eth_pkg.vhd
+ ram_eth_adr_w : NATURAL; -- = 10 -- = c_eth_ram_addr_w from eth_pkg.vhd
+
+ -- pi_system_info (first word of reg_unb_system_info_adr_w is backwards compatible with the original single word PIO system info)
+ reg_unb_system_info_adr_w : NATURAL; -- = 5 -- fixed, from c_mm_reg in unb_system_info_reg
+ rom_unb_system_info_adr_w : NATURAL; -- = 10 -- fixed, from c_mm_rom in mms_unb_system_info
+ -- pi_reg_common
+ reg_common_adr_w : NATURAL; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
+
+ -- pi_ppsh
+ reg_ppsh_adr_w : NATURAL; -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+
+ -- pi_unb_sens
+ reg_unb_sens_adr_w : NATURAL; -- = 3 -- fixed, from c_mm_reg in unb_sens_reg
+
+ -- pi_dpmm
+ reg_dpmm_data_adr_w : NATURAL; -- = 1 -- fixed, see dp_fifo_to_mm.vhd
+ reg_dpmm_ctrl_adr_w : NATURAL; -- = 1 -- fixed, from c_mm_reg in dp_fifo_to_mm_reg.vhd
+
+ -- pi_mmdp
+ reg_mmdp_data_adr_w : NATURAL; -- = 1 -- fixed, see dp_fifo_from_mm.vhd
+ reg_mmdp_ctrl_adr_w : NATURAL; -- = 1 -- fixed, from c_mm_reg in dp_fifo_from_mm_reg.vhd
+
+ -- pi_dp_ram_from_mm
+ reg_dp_ram_from_mm_adr_w : NATURAL; -- = 1 -- fixed, see dp_ram_from_mm.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+
+ -- pi_dp_ram_to_mm
+-- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+
+ -- pi_epcs (uses DP-MM read and write FIFOs for data access)
+ reg_epcs_adr_w : NATURAL; -- = 3 -- fixed, from c_mm_reg in epcs_reg
+
+ -- pi_remu
+ reg_remu_adr_w : NATURAL; -- = 3 -- fixed, from c_mm_reg in remu_reg
+
+ -- pi_ddr
+ -- pi_ddr_capture (uses DP-MM read FIFO for data access)
+ reg_ddr_adr_w : NATURAL; -- = 3 -- fixed, from c_mm_reg in ddr_reg
+
+ -- pi_io_ddr
+ reg_io_ddr_adr_w : NATURAL; -- = 16 -- fixed, from c_mm_reg in io_ddr (3) and in io_ddr_reg (8) that get multiplexed in on addresses 0..2, 8..15
+
+ -- pi_tr_nonbonded
+ reg_tr_nonbonded_adr_w : NATURAL; -- = 4 -- fixed, from c_mm_reg in tr_nonbonded_reg
+
+ -- pi_diagnostics
+ reg_diagnostics_adr_w : NATURAL; -- = 6 -- fixed, from c_mm_reg in diagnostics_reg
+
+ -- pi_dp_throttle
+ reg_dp_throttle_adr_w : NATURAL; -- = 2 -- fixed, from c_mm_reg in dp_throttle_reg
+
+ -- pi_bsn_source
+ reg_bsn_source_adr_w : NATURAL; -- = 2 -- fixed, from c_mm_reg in dp_bsn_source_reg.vhd
+
+ -- pi_bsn_schedurer
+ reg_bsn_scheduler_adr_w : NATURAL; -- = 1 -- fixed, from c_mm_reg in dp_bsn_scheduler_reg.vhd
+
+ -- pi_bsn_monitor
+ reg_bsn_monitor_adr_w : NATURAL; -- = 4 -- fixed, from c_mm_reg in dp_bsn_monitor_reg.vhd
+
+ -- pi_aduh_quad (defaults for ADU)
+ reg_adc_quad_adr_w : NATURAL; -- = 3 -- fixed, from c_mm_reg in aduh_quad_reg.vhd
+
+ -- pi_aduh_i2c_commander (defaults for ADU)
+ reg_i2c_commander_adr_w : NATURAL; -- = 6 -- = c_i2c_cmdr_aduh_i2c_mm.control_adr_w, from i2c_commander_aduh_pkg, used to pass on commander_adr_w
+ ram_i2c_protocol_adr_w : NATURAL; -- = 13 -- = c_i2c_cmdr_aduh_i2c_mm.protocol_adr_w, from i2c_commander_aduh_pkg
+ ram_i2c_result_adr_w : NATURAL; -- = 12 -- = c_i2c_cmdr_aduh_i2c_mm.result_adr_w, from i2c_commander_aduh_pkg
+
+ -- pi_aduh_monitor (defaults for ADU or WG used in bn_capture)
+ reg_aduh_mon_adr_w : NATURAL; -- = 2 -- fixed, from c_mm_reg in aduh_monitor_reg.vhd
+ ram_aduh_mon_dat_w : NATURAL; -- = 32 -- = c_sp_data_w, see node_bn_capture.vhd
+ ram_aduh_mon_adr_w : NATURAL; -- = 8 -- = ceil_log2(c_bn_capture.sp.monitor_buffer_nof_samples/c_wideband_factor), see node_bn_capture.vhd
+
+ -- pi_diag_wg_wideband.py (defaults for WG used in bn_capture)
+ reg_diag_wg_adr_w : NATURAL; -- = 2 -- fixed, from c_mm_reg in diag_wg_wideband_reg
+ ram_diag_wg_dat_w : NATURAL; -- = 8 -- defined here, see bn_capture_input.vhd
+ ram_diag_wg_adr_w : NATURAL; -- = 10 -- defined here, see bn_capture_input.vhd
+
+ -- pi_diag_data_buffer.py
+ ram_diag_db_nof_buf : NATURAL; -- = 16
+ ram_diag_db_buf_size : NATURAL; -- = 1024
+ ram_diag_db_adr_w : NATURAL; -- = 14 -- = ram_diag_db_nof_buf*ceil_log2(ram_diag_db_buf_size)
+ reg_diag_db_adr_w : NATURAL; -- = 5 -- 32 words for 16 streams max
+
+ -- pi_diag_block_gen (defaults when used with the BF for Apertif)
+ reg_diag_bg_adr_w : NATURAL; -- = 3
+ ram_diag_bg_adr_w : NATURAL; -- = 11 -- = ceil_log2(c_bf.nof_subbands*c_bf.nof_signal_paths/c_bf.nof_input_streams = 24*64/16 = 96) + ceil_log2(c_bf.nof_input_streams = 16)
+
+ -- pi_diag_tx_seq.py
+ reg_diag_tx_seq_w : NATURAL; -- = 2
+
+ -- pi_diag_tx_seq.py
+ reg_diag_rx_seq_w : NATURAL; -- = 3
+
+ -- pi_bf_bf (defaults for the BF for Apertif)
+ reg_bf_offsets_adr_w : NATURAL; -- = 5 -- = ceil_log2(c_bf.nof_offsets = 6) + ceil_log2(c_bf.nof_bf_units = 4)
+ ram_bf_weights_adr_w : NATURAL; -- = 16 -- = ceil_log2(c_bf.nof_bf_units*c_bf.nof_signal_paths*c_bf.nof_weights = 4 * 64 * 256 = 65536)
+ ram_st_sst_bf_adr_w : NATURAL; -- = 11 -- = ceil_log2(c_bf.nof_bf_units*c_bf.stat_data_sz*c_bf.nof_weights = 4 * 2 * 256 = 2048)
+
+ -- pi_mdio
+ reg_mdio_adr_w : NATURAL; -- = 3
+
+ -- dp_offload
+ reg_dp_offload_tx_adr_w : NATURAL; -- = 1
+
+ -- pi_unb_fpga_sensors
+ reg_fpga_temp_sens_adr_w : NATURAL; -- = 3
+ reg_fpga_voltage_sens_adr_w : NATURAL; -- = 4
+
+ -- pi_unb_pmbus
+ reg_unb_pmbus_adr_w : NATURAL; -- = 3
+ END RECORD;
+
+ CONSTANT c_unb2_board_peripherals_mm_reg_default : t_c_unb2_board_peripherals_mm_reg := (TRUE, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 3);
+
+END unb2_board_peripherals_pkg;
+
+PACKAGE BODY unb2_board_peripherals_pkg IS
+END unb2_board_peripherals_pkg;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..33484bcbe6d0dcfa8148a7732579b56af7d353a4
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
@@ -0,0 +1,170 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009-2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+PACKAGE unb2_board_pkg IS
+
+ -- UniBoard
+ CONSTANT c_unb2_board_nof_node : NATURAL := 4; -- number of nodes on UniBoard
+ CONSTANT c_unb2_board_nof_node_w : NATURAL := 2; -- = ceil_log2(c_unb2_board_nof_node)
+ CONSTANT c_unb2_board_nof_chip : NATURAL := c_unb2_board_nof_node; -- = 4
+ CONSTANT c_unb2_board_nof_chip_w : NATURAL := 2; -- = ceil_log2(c_unb2_board_nof_chip)
+ CONSTANT c_unb2_board_nof_ddr : NATURAL := 2; -- each node has 2 DDR modules
+
+ -- Subrack
+ CONSTANT c_unb2_board_nof_uniboard : NATURAL := 4; -- nof UniBoard in a subrack
+ CONSTANT c_unb2_board_nof_uniboard_w : NATURAL := 6; -- Only 2 required for 4 boards; full width is 6.
+
+ -- Clock frequencies
+ CONSTANT c_unb2_board_ext_clk_freq_200M : NATURAL := 200 * 10**6; -- external clock, SMA clock
+ CONSTANT c_unb2_board_eth_clk_freq_25M : NATURAL := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ CONSTANT c_unb2_board_eth_clk_freq_125M : NATURAL := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ CONSTANT c_unb2_board_tse_clk_freq : NATURAL := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_cal_clk_freq : NATURAL := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_mm_clk_freq_25M : NATURAL := 25 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_mm_clk_freq_50M : NATURAL := 50 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_mm_clk_freq_100M : NATURAL := 100 * 10**6; -- clock derived from ETH_clk by PLL
+ CONSTANT c_unb2_board_mm_clk_freq_125M : NATURAL := 125 * 10**6; -- clock derived from ETH_clk by PLL
+
+ -- I2C
+ CONSTANT c_unb2_board_reg_sens_adr_w : NATURAL := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd
+
+ -- ETH
+ CONSTANT c_unb2_board_nof_eth : NATURAL := 2; -- number of ETH channels per node
+
+ -- CONSTANT RECORD DECLARATIONS ---------------------------------------------
+
+ -- c_unb2_board_signature_* : random signature words used for unused status bits to ensure that the software reads the correct interface address
+ CONSTANT c_unb2_board_signature_eth1g_slv : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"46e46cbc";
+ CONSTANT c_unb2_board_signature_eth10g_slv : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"2bd2e40a";
+
+ CONSTANT c_unb2_board_signature_eth1g : INTEGER := TO_SINT(c_unb2_board_signature_eth1g_slv );
+ CONSTANT c_unb2_board_signature_eth10g : INTEGER := TO_SINT(c_unb2_board_signature_eth10g_slv );
+
+ -- Transceivers
+ TYPE t_c_unb2_board_tr IS RECORD
+ nof_bus : NATURAL;
+ bus_w : NATURAL;
+ i2c_w : NATURAL;
+ END RECORD;
+
+ --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 24, 3); -- per node: 2 buses with 24 channels
+ CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 24, 3); -- per node: 1 buses with 24 channels (testing)
+ --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 12, 3); -- per node: 2 buses with 24 channels (testing)
+ --CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (2, 4, 3); -- per node: 2 buses with 24 channels (testing)
+
+ CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
+ --CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 4, 0); -- per node: 2 buses with 12 channels (testing)
+
+ CONSTANT c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
+ CONSTANT c_unb2_board_tr_qsfp_nof_leds : NATURAL := c_unb2_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
+
+
+ TYPE t_unb2_board_qsfp_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ TYPE t_unb2_board_ring_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
+ TYPE t_unb2_board_back_bus_2arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 DOWNTO 0);
+
+
+ -- Auxiliary
+
+ -- Test IO Interface
+ TYPE t_c_unb2_board_testio IS RECORD
+ tst_w : NATURAL; -- = nof tst = 2; [tst_w-1 +tst_lo : tst_lo] = [5:4],
+ led_w : NATURAL; -- = nof led = 2; [led_w-1 +led_lo : led_lo] = [3:2],
+ jmp_w : NATURAL; -- = nof jmp = 2; [jmp_w-1 +jmp_lo : jmp_lo] = [1:0],
+ tst_lo : NATURAL; -- = 2;
+ led_lo : NATURAL; -- = 2;
+ jmp_lo : NATURAL; -- = 0;
+ END RECORD;
+
+ CONSTANT c_unb2_board_testio : t_c_unb2_board_testio := (2, 2, 2, 2, 2, 0);
+ CONSTANT c_unb2_board_testio_led_green : NATURAL := c_unb2_board_testio.led_lo;
+ CONSTANT c_unb2_board_testio_led_red : NATURAL := c_unb2_board_testio.led_lo+1;
+
+ TYPE t_c_unb2_board_aux IS RECORD
+ version_w : NATURAL; -- = 2;
+ id_w : NATURAL; -- = 8; -- 6+2 bits wide = total node ID for up to 64 UniBoards in a system and 4 nodes per board
+ chip_id_w : NATURAL; -- = 2; -- board node ID for the 4 FPGA nodes on a UniBoard
+ testio_w : NATURAL; -- = 6;
+ testio : t_c_unb2_board_testio;
+ END RECORD;
+
+ CONSTANT c_unb2_board_aux : t_c_unb2_board_aux := (2, 8, c_unb2_board_nof_chip_w, 6, c_unb2_board_testio);
+
+ TYPE t_e_unb2_board_node IS (e_any);
+
+ TYPE t_unb2_board_fw_version IS RECORD
+ hi : NATURAL; -- = 0..15
+ lo : NATURAL; -- = 0..15, firmware version is: hi.lo
+ END RECORD;
+
+ CONSTANT c_unb2_board_fw_version : t_unb2_board_fw_version := (0, 0);
+
+ -- SIGNAL RECORD DECLARATIONS -----------------------------------------------
+
+
+ -- I2C, MDIO
+ -- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
+ -- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
+ TYPE t_unb2_board_i2c_inout IS RECORD
+ scl : STD_LOGIC; -- serial clock
+ sda : STD_LOGIC; -- serial data
+ END RECORD;
+
+ -- System info
+ TYPE t_c_unb2_board_system_info IS RECORD
+ version : NATURAL; -- UniBoard board HW version (2 bit value)
+ id : NATURAL; -- UniBoard FPGA node id (8 bit value)
+ -- Derived ID info:
+ bck_id : NATURAL; -- = id[7:2], ID part from back plane
+ chip_id : NATURAL; -- = id[1:0], ID part from UniBoard
+ node_id : NATURAL; -- = id[1:0], node ID: 0, 1, 2 or 3
+ is_node2 : NATURAL; -- 1 for Node 2, else 0.
+ END RECORD;
+
+ FUNCTION func_unb2_board_system_info(VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0)) RETURN t_c_unb2_board_system_info;
+
+END unb2_board_pkg;
+
+
+PACKAGE BODY unb2_board_pkg IS
+
+ FUNCTION func_unb2_board_system_info(VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0)) RETURN t_c_unb2_board_system_info IS
+ VARIABLE v_system_info : t_c_unb2_board_system_info;
+ BEGIN
+ v_system_info.version := TO_INTEGER(UNSIGNED(VERSION));
+ v_system_info.id := TO_INTEGER(UNSIGNED(ID));
+ v_system_info.bck_id := TO_INTEGER(UNSIGNED(ID(7 DOWNTO 2)));
+ v_system_info.chip_id := TO_INTEGER(UNSIGNED(ID(1 DOWNTO 0)));
+ v_system_info.node_id := TO_INTEGER(UNSIGNED(ID(1 DOWNTO 0)));
+ IF UNSIGNED(ID(1 DOWNTO 0))=2 THEN v_system_info.is_node2 := 1; ELSE v_system_info.is_node2 := 0; END IF;
+ RETURN v_system_info;
+ END;
+
+END unb2_board_pkg;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f90d2dc68961b44125a049a8e170d394778f678e
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -0,0 +1,186 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
+-- Description:
+-- The testio LED on UniBoard2 is not visible via the front panel. The
+-- front panel does have a dual colour LED for each QSFP lane. Therefore
+-- these QSFP LEDs are used to signal some application information and lane
+-- status/activity information.
+--
+-- LED lights:
+--
+-- 1) Default behaviour for all QSFP leds:
+-- . off = no FPGA image is running
+--
+-- 2) For factory image:
+-- . green off
+-- . red toggling every 1 s = factory image is running (g_factory_image=TRUE)
+--
+-- 3) For a user image without Gbps lane functionality:
+-- . red off
+-- . green toggling every 1 s = user image is running (g_factory_image=FALSE and green_on_arr(I)='0' default)
+--
+-- 4) For a user image with Gbps lane functionality:
+-- . red off
+-- . green toggling every 1 s when the lane status is not OK (green_on_arr(I)=xon='0')
+-- . green on continously when the lane status is OK (green_on_arr(I)=xon='1')
+-- . green led goes off briefly off when there is an Tx or Rx packet (green_evt_arr(I).sop='1')
+--
+-- The combined colour amber (= red + green) is not used. The factory image
+-- only uses the red led and the user image only uses the green led.
+--
+-- Each QSFP carries c_quad = 4 lanes, therefore the green led LED can only
+-- signal a combined status of the lanes. The combined status eg. be:
+--
+-- 'and-status' = combined status is on when all lanes are on
+-- 'or-status' = combined status is on when at least 1 lane is on
+--
+-- Choose using 'or-status', because then the LED can give lane status
+-- information when less than all 4 lane are connected.
+--
+
+ENTITY unb2_board_qsfp_leds IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE; -- when true speed up led toggling in simulation
+ g_factory_image : BOOLEAN := FALSE; -- distinguish factory image and user images
+ g_nof_qsfp : NATURAL := 6; -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us : NATURAL := 200 -- nof clk cycles to get us period
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ -- internal pulser outputs
+ pulse_us : OUT STD_LOGIC;
+ pulse_ms : OUT STD_LOGIC;
+ pulse_s : OUT STD_LOGIC;
+ -- lane status
+ tx_siso_arr : IN t_dp_siso_arr(g_nof_qsfp*c_quad-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rst);
+ tx_sosi_arr : IN t_dp_sosi_arr(g_nof_qsfp*c_quad-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ rx_sosi_arr : IN t_dp_sosi_arr(g_nof_qsfp*c_quad-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ -- leds
+ green_led_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp-1 DOWNTO 0);
+ red_led_arr : OUT STD_LOGIC_VECTOR(g_nof_qsfp-1 DOWNTO 0)
+ );
+END unb2_board_qsfp_leds;
+
+
+ARCHITECTURE str OF unb2_board_qsfp_leds IS
+
+ CONSTANT c_nof_ms : NATURAL := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
+ CONSTANT c_nof_lanes : NATURAL := g_nof_qsfp*c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
+
+ SIGNAL i_pulse_ms : STD_LOGIC;
+ SIGNAL i_pulse_s : STD_LOGIC;
+ SIGNAL toggle_s : STD_LOGIC;
+
+ SIGNAL green_on_arr : STD_LOGIC_VECTOR(g_nof_qsfp*c_quad-1 DOWNTO 0);
+ SIGNAL green_evt_arr : STD_LOGIC_VECTOR(g_nof_qsfp*c_quad-1 DOWNTO 0);
+
+ SIGNAL qsfp_on_arr : STD_LOGIC_VECTOR(g_nof_qsfp-1 DOWNTO 0);
+ SIGNAL qsfp_evt_arr : STD_LOGIC_VECTOR(g_nof_qsfp-1 DOWNTO 0);
+
+BEGIN
+
+ pulse_ms <= i_pulse_ms;
+ pulse_s <= i_pulse_s;
+
+ -- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
+ u_common_pulser_us_ms_s : ENTITY common_lib.common_pulser_us_ms_s
+ GENERIC MAP (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
+
+ u_common_toggle_s : ENTITY common_lib.common_toggle
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
+
+ gen_factory_image : IF g_factory_image=TRUE GENERATE
+ green_led_arr <= (OTHERS=>'0');
+
+ gen_red_led_arr : FOR I IN g_nof_qsfp-1 DOWNTO 0 GENERATE
+ u_red_led_controller : ENTITY common_lib.common_led_controller
+ GENERIC MAP (
+ g_nof_ms => c_nof_ms
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
+ END GENERATE;
+ END GENERATE;
+
+ gen_user_image : IF g_factory_image=FALSE GENERATE
+
+ red_led_arr <= (OTHERS=>'0');
+
+ gen_green_ctrl_arr : FOR I IN c_nof_lanes-1 DOWNTO 0 GENERATE
+ green_on_arr(I) <= tx_siso_arr(I).xon WHEN rising_edge(clk);
+ green_evt_arr(I) <= tx_sosi_arr(I).sop OR rx_sosi_arr(I).sop WHEN rising_edge(clk);
+ END GENERATE;
+
+ gen_green_led_arr : FOR I IN g_nof_qsfp-1 DOWNTO 0 GENERATE
+
+ qsfp_on_arr(I) <= orv(green_on_arr( (I+1)*c_quad-1 DOWNTO + I*c_quad));
+ qsfp_evt_arr(I) <= orv(green_evt_arr((I+1)*c_quad-1 DOWNTO + I*c_quad));
+
+ u_green_led_controller : ENTITY common_lib.common_led_controller
+ GENERIC MAP (
+ g_nof_ms => c_nof_ms
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
+ END GENERATE;
+ END GENERATE;
+
+END str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2c924997a546d3de8092e6107b80f868482b3617
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
@@ -0,0 +1,63 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_ring_io IS
+ GENERIC (
+ g_nof_ring_bus : NATURAL := c_unb2_board_tr_ring.nof_bus
+ );
+ PORT (
+ serial_tx_arr : IN STD_LOGIC_VECTOR(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w-1 DOWNTO 0);
+
+ RING_RX : IN t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ RING_TX : OUT t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0)
+ );
+END unb2_board_ring_io;
+
+ARCHITECTURE str OF unb2_board_ring_io IS
+
+ -- help signals so we can iterate through buses
+ SIGNAL si_tx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL si_rx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus-1 DOWNTO 0);
+
+BEGIN
+
+ gen_buses : FOR i IN 0 TO g_nof_ring_bus-1 GENERATE
+ RING_TX(i) <= si_tx_2arr(i);
+ si_rx_2arr(i) <= RING_RX(i);
+ END GENERATE;
+
+
+ gen_wire_bus : FOR i IN 0 TO g_nof_ring_bus-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_unb2_board_tr_ring.bus_w-1 GENERATE
+
+ si_tx_2arr(i)(j) <= serial_tx_arr(i*c_unb2_board_tr_ring.bus_w + j);
+ serial_rx_arr(i*c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
+
+ END GENERATE;
+ END GENERATE;
+
+END;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d56e6802fb445b0c34f6344566a72cdbd1406560
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
@@ -0,0 +1,110 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE i2c_lib.i2c_pkg.ALL;
+
+
+ENTITY unb2_board_sens is
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_clk_freq : NATURAL := 100*10**6; -- clk frequency in Hz
+ g_temp_high : NATURAL := 85;
+ g_sens_nof_result : NATURAL := 4 -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ start : IN STD_LOGIC;
+ -- i2c bus
+ scl : INOUT STD_LOGIC;
+ sda : INOUT STD_LOGIC;
+ -- read results
+ sens_evt : OUT STD_LOGIC;
+ sens_err : OUT STD_LOGIC;
+ sens_data : OUT t_slv_8_arr(0 TO g_sens_nof_result-1)
+ );
+END ENTITY;
+
+
+ARCHITECTURE str OF unb2_board_sens IS
+
+ -- I2C clock rate settings
+ CONSTANT c_sens_clk_cnt : NATURAL := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq/10**6)); -- define I2C clock rate
+ CONSTANT c_sens_comma_w : NATURAL := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
+ -- 0 = no comma time
+
+ CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
+
+ SIGNAL smbus_in_dat : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ SIGNAL smbus_in_val : STD_LOGIC;
+ SIGNAL smbus_out_dat : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ SIGNAL smbus_out_val : STD_LOGIC;
+ SIGNAL smbus_out_err : STD_LOGIC;
+ SIGNAL smbus_out_ack : STD_LOGIC;
+ SIGNAL smbus_out_end : STD_LOGIC;
+
+BEGIN
+
+ u_unb2_board_sens_ctrl : ENTITY work.unb2_board_sens_ctrl
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ PORT MAP (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+
+ u_i2c_smbus : ENTITY i2c_lib.i2c_smbus
+ GENERIC MAP (
+ g_i2c_phy => c_sens_phy
+ )
+ PORT MAP (
+ gs_sim => g_sim,
+ clk => clk,
+ rst => rst,
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
+ );
+
+END ARCHITECTURE;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c4f99d23048de7cfa7c53213f799833ec0532c45
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -0,0 +1,191 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE i2c_lib.i2c_smbus_pkg.ALL;
+USE i2c_lib.i2c_dev_max1617_pkg.ALL;
+USE i2c_lib.i2c_dev_ltc4260_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY unb2_board_sens_ctrl IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_nof_result : NATURAL := 4;
+ g_temp_high : NATURAL := 85
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ start : IN STD_LOGIC; -- pulse to start the I2C sequence to read out the sensors
+ out_dat : OUT STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ out_val : OUT STD_LOGIC;
+ in_dat : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ in_val : IN STD_LOGIC;
+ in_err : IN STD_LOGIC;
+ in_ack : IN STD_LOGIC;
+ in_end : IN STD_LOGIC;
+ result_val : OUT STD_LOGIC;
+ result_err : OUT STD_LOGIC;
+ result_dat : OUT t_slv_8_arr(0 TO g_nof_result-1)
+ );
+END ENTITY;
+
+
+ARCHITECTURE rtl OF unb2_board_sens_ctrl IS
+
+ -- I2C slave addresses of the devices on the I2C bus on UniBoard
+ CONSTANT FPGA_MAX1617_ADR : NATURAL := MAX1617_ADR_LOW_LOW; -- FPGA temperature sensor, slave address is "0011000"
+ CONSTANT ETH_MAX1617_ADR : NATURAL := MAX1617_ADR_MID_LOW; -- ETH temperature sensor, slave address is "0101001"
+ CONSTANT HOTSWAP_LTC4260_ADR : NATURAL := LTC4260_ADR_LOW_LOW_LOW; -- Hot swap controller, slave address is "1000100";
+
+
+ -- Experimental constants for the PMBUS, power module readouts (to be checked FIXME)
+ CONSTANT LOC_POWER_TR_R : NATURAL := 16#1C#; -- 0x0E
+ CONSTANT LOC_POWER_TR_R1 : NATURAL := 16#0E#;
+ CONSTANT LOC_POWER_TR_R2 : NATURAL := 16#0F#; -- 0x0E
+ CONSTANT LP_VOUT_MODE : NATURAL := 16#20#;
+ CONSTANT LP_VOUT : NATURAL := 16#8B#;
+ CONSTANT LP_IOUT : NATURAL := 16#8C#;
+ CONSTANT LP_TEMP : NATURAL := 16#8D#;
+
+
+ TYPE t_SEQUENCE IS ARRAY (NATURAL RANGE <>) OF NATURAL;
+
+ -- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
+ -- Assume clk <= 200 MHz, so 5 ns period. Hence timeout of 4000 is enough.
+ CONSTANT c_timeout_sda : NATURAL := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
+
+ CONSTANT c_SEQ : t_SEQUENCE := (
+ SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_TEMP,--LP_VOUT_MODE,
+ SMBUS_READ_BYTE , LOC_POWER_TR_R1, LP_TEMP,--LP_VOUT, -- SMBUS_READ_WORD
+ SMBUS_READ_BYTE , LOC_POWER_TR_R2, LP_TEMP,--LP_IOUT, -- SMBUS_READ_WORD
+ SMBUS_READ_BYTE , LOC_POWER_TR_R1, LP_VOUT_MODE, -- SMBUS_READ_WORD
+
+ --SMBUS_READ_BYTE , FPGA_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ --SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ --SMBUS_READ_BYTE , HOTSWAP_LTC4260_ADR, LTC4260_CMD_SENSE,
+ --SMBUS_READ_BYTE , HOTSWAP_LTC4260_ADR, LTC4260_CMD_SOURCE,
+ SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_C_END,
+ SMBUS_C_NOP
+ ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+
+ CONSTANT c_seq_len : NATURAL := c_SEQ'LENGTH-1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
+
+ -- The protocol list c_SEQ yields a list of g_nof_result=14 result bytes:
+ -- . expected SMBUS_READ_BYTE -> rdbyte, ok=0
+ -- . expected SMBUS_WRITE_BYTE -> ok=0
+ -- . expected SMBUS_C_END -> ok=0
+ -- ==> so expected result_dat[0:4] = [rdbyte, rdbyte, rdbyte, rdbyte, rdbyte]
+
+ SIGNAL start_reg : STD_LOGIC;
+
+ SIGNAL seq_cnt : NATURAL RANGE 0 TO c_seq_len := c_seq_len;
+ SIGNAL nxt_seq_cnt : NATURAL;
+
+ SIGNAL rx_cnt : NATURAL RANGE 0 TO g_nof_result;
+ SIGNAL nxt_rx_cnt : NATURAL;
+
+ SIGNAL rx_val : STD_LOGIC;
+ SIGNAL nxt_rx_val : STD_LOGIC;
+ SIGNAL rx_err : STD_LOGIC;
+ SIGNAL nxt_rx_err : STD_LOGIC;
+ SIGNAL rx_dat : t_slv_8_arr(result_dat'RANGE);
+ SIGNAL nxt_rx_dat : t_slv_8_arr(result_dat'RANGE);
+ SIGNAL nxt_result_val : STD_LOGIC;
+ SIGNAL nxt_result_err : STD_LOGIC;
+ SIGNAL i_result_dat : t_slv_8_arr(result_dat'RANGE);
+ SIGNAL nxt_result_dat : t_slv_8_arr(result_dat'RANGE);
+
+BEGIN
+
+ result_dat <= i_result_dat;
+
+ regs: PROCESS(rst, clk)
+ BEGIN
+ IF rst='1' THEN
+ start_reg <= '0';
+ seq_cnt <= c_seq_len;
+ rx_cnt <= 0;
+ rx_val <= '0';
+ rx_err <= '0';
+ rx_dat <= (OTHERS=>(OTHERS=>'0'));
+ result_val <= '0';
+ result_err <= '0';
+ i_result_dat <= (OTHERS=>(OTHERS=>'0'));
+ ELSIF rising_edge(clk) THEN
+ start_reg <= start;
+ seq_cnt <= nxt_seq_cnt;
+ rx_cnt <= nxt_rx_cnt;
+ rx_val <= nxt_rx_val;
+ rx_err <= nxt_rx_err;
+ rx_dat <= nxt_rx_dat;
+ result_val <= nxt_result_val;
+ result_err <= nxt_result_err;
+ i_result_dat <= nxt_result_dat;
+ END IF;
+ END PROCESS;
+
+ -- Issue the protocol list
+ p_seq_cnt : PROCESS(seq_cnt, start_reg, in_ack)
+ BEGIN
+ nxt_seq_cnt <= seq_cnt;
+ IF start_reg = '1' THEN
+ nxt_seq_cnt <= 0;
+ ELSIF seq_cnt<c_seq_len AND in_ack='1' THEN
+ nxt_seq_cnt <= seq_cnt + 1;
+ END IF;
+ END PROCESS;
+
+ out_dat <= STD_LOGIC_VECTOR(TO_UVEC(c_SEQ(seq_cnt), c_byte_w));
+ out_val <= '1' WHEN seq_cnt<c_seq_len ELSE '0';
+
+ -- Fill the rx_dat byte array
+ p_rx_dat : PROCESS(start_reg, rx_err, in_err, rx_dat, rx_cnt, in_dat, in_val)
+ BEGIN
+ nxt_rx_err <= rx_err;
+ IF start_reg = '1' THEN
+ nxt_rx_err <= '0';
+ ELSIF in_err='1' THEN
+ nxt_rx_err <= '1';
+ END IF;
+
+ nxt_rx_dat <= rx_dat;
+ nxt_rx_cnt <= rx_cnt;
+ IF start_reg = '1' THEN
+ nxt_rx_dat <= (OTHERS=>(OTHERS=>'0'));
+ nxt_rx_cnt <= 0;
+ ELSIF in_val='1' THEN
+ nxt_rx_dat(rx_cnt) <= in_dat;
+ nxt_rx_cnt <= rx_cnt + 1;
+ END IF;
+ END PROCESS;
+
+ nxt_rx_val <= in_end;
+
+ -- Capture the complete rx_dat byte array
+ nxt_result_val <= rx_val;
+ nxt_result_err <= rx_err;
+ nxt_result_dat <= rx_dat WHEN rx_val='1' ELSE i_result_dat;
+
+END rtl;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e38265c892ebbcc6bf09e1ba56aaa5eeef87cdb0
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Provide MM slave register for unb2_board_sens
+-- Description:
+--
+-- 31 24 23 16 15 8 7 0 wi
+-- |-----------------|-----------------|-----------------|-----------------|
+-- | xxx fpga_temp = sens_data[0][7:0]| 0
+-- |-----------------------------------------------------------------------|
+-- | xxx eth_temp = sens_data[1][7:0]| 1
+-- |-----------------------------------------------------------------------|
+-- | xxx hot_swap_v_sense = sens_data[2][7:0]| 2
+-- |-----------------------------------------------------------------------|
+-- | xxx hot_swap_v_source = sens_data[3][7:0]| 3
+-- |-----------------------------------------------------------------------|
+-- | xxx sens_err[0]| 4
+-- |-----------------------------------------------------------------------|
+-- | xxx temp_high[6:0]| 5
+-- |-----------------------------------------------------------------------|
+--
+-- * The fpga_temp and eth_temp are in degrees (two's complement)
+-- * The hot swap voltages depend on:
+-- . From i2c_dev_ltc4260_pkg:
+-- LTC4260_V_UNIT_SENSE = 0.0003 -- 0.3 mV over Rs for current sense
+-- LTC4260_V_UNIT_SOURCE = 0.4 -- 400 mV supply voltage (e.g +48 V)
+-- LTC4260_V_UNIT_ADIN = 0.01 -- 10 mV ADC
+--
+-- . From UniBoard unb_sensors.h:
+-- SENS_HOT_SWAP_R_SENSE = 0.005 -- R sense on UniBoard is 5 mOhm (~= 10 mOhm // 10 mOhm)
+-- SENS_HOT_SWAP_I_UNIT_SENSE = LTC4260_V_UNIT_SENSE / SENS_HOT_SWAP_R_SENSE
+-- SENS_HOT_SWAP_V_UNIT_SOURCE = LTC4260_V_UNIT_SOURCE
+--
+-- ==>
+-- Via all nodes:
+-- 0 = FPGA temperature = TInt8(fpga_temp)
+-- Only via node2:
+-- 1 = UniBoard ETH PHY temperature = TInt8(eth_temp)
+-- 2 = UniBoard hot swap supply current = hot_swap_v_sense * SENS_HOT_SWAP_I_UNIT_SENSE
+-- 3 = UniBoard hot swap supply voltage = hot_swap_v_source * SENS_HOT_SWAP_V_UNIT_SOURCE
+-- 4 = I2C error status for node2 sensors access only, 0 = ok
+--
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY unb2_board_sens_reg IS
+ GENERIC (
+ g_sens_nof_result : NATURAL := 4;
+ g_temp_high : NATURAL := 85
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
+ sla_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+
+ -- MM registers
+ sens_err : IN STD_LOGIC := '0';
+ sens_data : IN t_slv_8_arr(0 TO g_sens_nof_result-1);
+
+ -- Max temp output
+ temp_high : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+
+ );
+END unb2_board_sens_reg;
+
+
+ARCHITECTURE rtl OF unb2_board_sens_reg IS
+
+ -- Define the actual size of the MM slave register
+ CONSTANT c_mm_nof_dat : NATURAL := g_sens_nof_result+1+1; -- +1 to fit user set temp_high one additional address
+ -- +1 to fit sens_err in the last address
+
+ CONSTANT c_mm_reg : t_c_mem := (latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
+
+ SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+BEGIN
+
+ temp_high <= i_temp_high;
+
+ ------------------------------------------------------------------------------
+ -- MM register access in the mm_clk domain
+ -- . Hardcode the shared MM slave register directly in RTL instead of using
+ -- the common_reg_r_w instance. Directly using RTL is easier when the large
+ -- MM register has multiple different fields and with different read and
+ -- write options per field in one MM register.
+ ------------------------------------------------------------------------------
+
+ p_mm_reg : PROCESS (mm_rst, mm_clk)
+ VARIABLE vA : NATURAL := 0;
+ BEGIN
+ IF mm_rst = '1' THEN
+ -- Read access
+ sla_out <= c_mem_miso_rst;
+ -- Write access, register values
+ i_temp_high <= TO_UVEC(g_temp_high, 7);
+
+ ELSIF rising_edge(mm_clk) THEN
+ vA := TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0));
+
+ -- Read access defaults
+ sla_out.rdval <= '0';
+
+ -- Write access: set register value
+ IF sla_in.wr = '1' THEN
+ IF vA = g_sens_nof_result+1 THEN
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ IF UNSIGNED(sla_in.wrdata(c_word_w-1 DOWNTO 7)) = 0 THEN
+ i_temp_high <= sla_in.wrdata(6 DOWNTO 0);
+ END IF;
+ END IF;
+
+ -- Read access: get register value
+ ELSIF sla_in.rd = '1' THEN
+ sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
+ sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+
+ -- no need to capture sens_data, it is not critical if the sens_data happens to be read just before and after an I2C access occurred
+ IF vA < g_sens_nof_result THEN
+ sla_out.rddata <= RESIZE_MEM_DATA(sens_data(vA)(c_byte_w-1 DOWNTO 0));
+ ELSIF vA = g_sens_nof_result THEN
+ sla_out.rddata(0) <= sens_err; -- only valid for node2
+ ELSE
+ sla_out.rddata(6 DOWNTO 0) <= i_temp_high;
+ END IF;
+ -- else unused addresses read zero
+ END IF;
+ END IF;
+ END PROCESS;
+
+END rtl;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7bf92453fe036c0192e885c2c931e0e541be2f3b
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
@@ -0,0 +1,98 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
+
+-- Keep the UniBoard system info knowledge in this HDL entity and in the
+-- corresponding software functions in unb_common.c,h. This avoids having to
+-- define named constants for indexing the fields in the info word.
+
+ENTITY unb2_board_system_info IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y (4b.4b)
+ g_aux : t_c_unb2_board_aux := c_unb2_board_aux -- aux contains the hardware version
+ );
+ PORT (
+ clk : IN STD_LOGIC;
+ hw_version : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
+ id : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
+ info : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ bck_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0); -- ID[7:2]
+ chip_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0); -- ID[1:0]
+ node_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_node_w-1 DOWNTO 0); -- ID[1:0]
+ is_node2 : OUT STD_LOGIC -- '1' for Node 2, else '0'.
+ );
+END unb2_board_system_info;
+
+
+ARCHITECTURE str OF unb2_board_system_info IS
+
+ SIGNAL cs_sim : STD_LOGIC;
+
+ SIGNAL hw_version_reg : STD_LOGIC_VECTOR(hw_version'RANGE);
+ SIGNAL id_reg : STD_LOGIC_VECTOR(id'RANGE);
+ SIGNAL nxt_info : STD_LOGIC_VECTOR(info'RANGE);
+
+ SIGNAL nxt_bck_id : STD_LOGIC_VECTOR(bck_id'RANGE);
+ SIGNAL nxt_chip_id : STD_LOGIC_VECTOR(chip_id'RANGE);
+ SIGNAL nxt_node_id : STD_LOGIC_VECTOR(node_id'RANGE);
+ SIGNAL nxt_is_node2 : STD_LOGIC;
+
+BEGIN
+
+ p_reg : PROCESS(clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ -- inputs
+ hw_version_reg <= hw_version;
+ id_reg <= id;
+ -- output
+ info <= nxt_info;
+ bck_id <= nxt_bck_id;
+ chip_id <= nxt_chip_id;
+ node_id <= nxt_node_id;
+ is_node2 <= nxt_is_node2;
+ END IF;
+ END PROCESS;
+
+ cs_sim <= is_true(g_sim);
+
+ p_info : PROCESS(cs_sim, hw_version_reg, id_reg)
+ BEGIN
+ nxt_info <= (OTHERS=>'0');
+ nxt_info(23 DOWNTO 20) <= TO_UVEC(g_fw_version.hi, 4);
+ nxt_info(19 DOWNTO 16) <= TO_UVEC(g_fw_version.lo, 4);
+ nxt_info(10) <= cs_sim;
+ nxt_info(9 DOWNTO 8) <= hw_version_reg;
+ nxt_info(7 DOWNTO 0) <= id_reg;
+ END PROCESS;
+
+ nxt_bck_id <= id_reg(7 DOWNTO 2);
+ nxt_chip_id <= id_reg(1 DOWNTO 0);
+ nxt_node_id <= id_reg(1 DOWNTO 0);
+ nxt_is_node2 <= '1' WHEN TO_UINT(id_reg(1 DOWNTO 0)) = 2 ELSE '0';
+
+END str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d528a8d4b5c44a9b1e77aa52d6609d9c5d17da66
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -0,0 +1,144 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RO read only (no VHDL present to access HW in write mode)
+-- WO write only (no VHDL present to access HW in read mode)
+-- WE write event (=WO)
+-- WR write control, read control
+-- RW read status, write control
+-- RC read, clear on read
+-- FR FIFO read
+-- FW FIFO write
+--
+-- wi Bits R/W Name Default Description |REG_UNB2_BOARD_SYSTEM_INFO|
+-- =============================================================================
+-- 0 [23..0] RO info
+-- 1 [7..0] RO 0
+-- 2 [31..0] RO design_name
+-- . .. . ..
+-- 9 [31..0] RO design name
+-- 10 [31..0] RO date stamp (YYYYMMDD)
+-- 11 [31..0] RO time stamp (HHMMSS)
+-- 12 [31..0] RO SVN stamp
+-- 13 [31..0] RO note
+-- . . . ..
+-- 20 [31..0] RO note
+-- =============================================================================
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
+
+ENTITY unb2_board_system_info_reg IS
+ GENERIC (
+ g_design_name : STRING;
+ g_stamp_date : NATURAL := 0;
+ g_stamp_time : NATURAL := 0;
+ g_stamp_svn : NATURAL := 0;
+ g_design_note : STRING
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ -- Memory Mapped Slave
+ sla_in : IN t_mem_mosi;
+ sla_out : OUT t_mem_miso;
+
+ info : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
+ );
+END unb2_board_system_info_reg;
+
+
+ARCHITECTURE rtl OF unb2_board_system_info_reg IS
+
+ CONSTANT c_nof_fixed_regs : NATURAL := 2; -- info
+ CONSTANT c_nof_design_name_regs : NATURAL := 8; -- design_name
+ CONSTANT c_nof_stamp_regs : NATURAL := 3; -- date, time, svn rev
+ CONSTANT c_nof_design_note_regs : NATURAL := 8; -- note
+
+ CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
+
+ CONSTANT c_mm_reg : t_c_mem := (latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
+
+ CONSTANT c_use_phy_w : NATURAL := 8; -- FIXME: to be removed
+ CONSTANT c_use_phy : STD_LOGIC_VECTOR(c_use_phy_w-1 DOWNTO 0) := (OTHERS=> '0'); -- FIXME: to be removed
+
+ CONSTANT c_design_name : t_slv_32_arr(0 TO c_nof_design_name_regs-1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
+ CONSTANT c_design_note : t_slv_32_arr(0 TO c_nof_design_note_regs-1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
+
+BEGIN
+
+ p_mm_reg : PROCESS (mm_rst, mm_clk)
+ VARIABLE vA : NATURAL := 0;
+ BEGIN
+ IF mm_rst = '1' THEN
+ -- Read access
+ sla_out <= c_mem_miso_rst;
+ ELSIF rising_edge(mm_clk) THEN
+ -- Read access defaults
+ sla_out.rdval <= '0';
+
+ -- Read access: get register value
+ IF sla_in.rd = '1' THEN
+ sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
+ sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
+
+ vA := TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0));
+ IF vA = 0 THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= info;
+ -- Use bit 11 to indicate that we're using the MM bus (not the info SLV).
+ -- Using the MM bus enables user to also read use_phy, design_name etc.
+ sla_out.rddata(11) <= '1';
+ ELSIF vA = 1 THEN
+ sla_out.rddata(c_use_phy_w-1 DOWNTO 0) <= c_use_phy;
+ ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_name(vA-c_nof_fixed_regs);
+
+ ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_date, c_word_w);
+
+ ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs+1 THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_time, c_word_w);
+
+ ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs+2 THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_svn, c_word_w);
+
+ ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs+c_nof_stamp_regs+c_nof_design_note_regs THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_note(vA-c_nof_fixed_regs-c_nof_design_name_regs-c_nof_stamp_regs);
+
+ END IF;
+
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+END rtl;
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ffc5345b51204581561602c2e42a2cf28f7bece8
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -0,0 +1,98 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Purpose:
+-- Extend the input WDI that is controlled in SW (as it should be) to avoid
+-- that the watchdog reset will occur when new SW is loaded, while keeping
+-- the HDL image. This component extends the last input WDI by toggling the
+-- output WDI for about 2**(g_extend_w-1) ms more.
+
+ENTITY unb2_board_wdi_extend IS
+ GENERIC (
+ g_extend_w : NATURAL := 14
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ pulse_ms : IN STD_LOGIC; -- pulses every 1 ms
+ wdi_in : IN STD_LOGIC;
+ wdi_out : OUT STD_LOGIC
+ );
+END unb2_board_wdi_extend;
+
+
+ARCHITECTURE str OF unb2_board_wdi_extend IS
+
+ SIGNAL wdi_evt : STD_LOGIC;
+
+ SIGNAL wdi_cnt : STD_LOGIC_VECTOR(g_extend_w-1 DOWNTO 0);
+ SIGNAL wdi_cnt_en : STD_LOGIC;
+
+ SIGNAL i_wdi_out : STD_LOGIC;
+ SIGNAL nxt_wdi_out : STD_LOGIC;
+
+BEGIN
+
+ wdi_out <= i_wdi_out;
+
+ p_clk : PROCESS(rst, clk)
+ BEGIN
+ IF rst='1' THEN
+ i_wdi_out <= '0';
+ ELSIF rising_edge(clk) THEN
+ i_wdi_out <= nxt_wdi_out;
+ END IF;
+ END PROCESS;
+
+ wdi_cnt_en <= '1' WHEN pulse_ms='1' AND wdi_cnt(wdi_cnt'HIGH)='0' ELSE '0';
+
+ nxt_wdi_out <= NOT i_wdi_out WHEN wdi_cnt_en='1' ELSE i_wdi_out;
+
+ u_common_evt : ENTITY common_lib.common_evt
+ GENERIC MAP (
+ g_evt_type => "BOTH",
+ g_out_reg => TRUE
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
+
+ u_common_counter : ENTITY common_lib.common_counter
+ GENERIC MAP (
+ g_width => g_extend_w
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
+
+END str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..42a42742a54008100adefd7cc0b25a5df68ba5fa
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -0,0 +1,90 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Manually override WDI to initiate reconfiguratioon of the FPGA.
+-- Write 0xB007FAC7 to address 0x0.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY unb2_board_wdi_reg IS
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
+ sla_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+
+ -- MM registers in st_clk domain
+ wdi_override : OUT STD_LOGIC
+ );
+END unb2_board_wdi_reg;
+
+
+ARCHITECTURE rtl OF unb2_board_wdi_reg IS
+
+ -- Define the actual size of the MM slave register
+ CONSTANT c_mm_reg : t_c_mem := (latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
+
+ -- For safety, WDI override requires the following word to be written:
+ CONSTANT c_cmd_reconfigure : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0 ) := x"B007FAC7"; -- "Boot factory"
+
+BEGIN
+
+ p_mm_reg : PROCESS (mm_rst, mm_clk)
+ BEGIN
+ IF mm_rst = '1' THEN
+ -- Read access
+ sla_out <= c_mem_miso_rst;
+ -- Write access, register values
+ wdi_override <= '0';
+ ELSIF rising_edge(mm_clk) THEN
+ -- Read access defaults: unused
+ sla_out <= c_mem_miso_rst;
+
+ -- Write access: set register value
+ IF sla_in.wr = '1' THEN
+ CASE TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
+ -- Write Block Sync
+ WHEN 0 =>
+ IF sla_in.wrdata(c_word_w-1 DOWNTO 0) = c_cmd_reconfigure THEN
+ wdi_override <= '1';
+ ELSE
+ wdi_override <= '0';
+ END IF;
+ WHEN OTHERS => NULL; -- unused MM addresses
+ END CASE;
+ END IF;
+
+ END IF;
+ END PROCESS;
+
+END rtl;
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..eb233b1ac5546e80db457f343112f05d94548181
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -0,0 +1,89 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Provide MM slave register for unb2_fpga_sens
+--
+
+LIBRARY IEEE, common_lib, technology_lib, fpga_sense_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2_fpga_sens_reg IS
+ GENERIC (
+ g_sim : BOOLEAN;
+ g_technology : NATURAL := c_tech_arria10;
+ g_sens_nof_result : NATURAL := 1;
+ g_temp_high : NATURAL := 85
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
+ start : IN STD_LOGIC;
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_temp_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
+ sla_temp_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+
+ sla_voltage_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
+ sla_voltage_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+
+ -- MM registers
+ --sens_err : IN STD_LOGIC := '0';
+ --sens_data : IN t_slv_8_arr(0 TO g_sens_nof_result-1); -- FIXME should be OUT
+
+ -- Max temp output
+ temp_high : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+ );
+END unb2_fpga_sens_reg;
+
+
+ARCHITECTURE str OF unb2_fpga_sens_reg IS
+
+ --SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+BEGIN
+
+ temp_high <= (others => '0'); --i_temp_high;
+
+ u_fpga_sense: ENTITY fpga_sense_lib.fpga_sense
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ start_sense => start,
+
+ reg_temp_mosi => sla_temp_in,
+ reg_temp_miso => sla_temp_out,
+
+ reg_voltage_store_mosi => sla_voltage_in,
+ reg_voltage_store_miso => sla_voltage_out
+ );
+
+END str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..71e2198b7759daae9b141f583275581770a3f8f8
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -0,0 +1,212 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for mms_unb2_board_sens
+--
+-- Features:
+-- . Verify that the UniBoard sensors are read.
+--
+-- Usage:
+-- . > as 10
+-- . > run -all
+
+ENTITY tb_mms_unb2_board_sens IS
+END tb_mms_unb2_board_sens;
+
+LIBRARY IEEE, common_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+
+
+ARCHITECTURE tb OF tb_mms_unb2_board_sens IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE; --FALSE;
+ CONSTANT c_repeat : NATURAL := 2;
+ CONSTANT c_clk_freq : NATURAL := 100*10**6;
+ CONSTANT c_clk_period : TIME := (10**9/c_clk_freq) * 1 ns;
+ CONSTANT c_rst_period : TIME := 4 * c_clk_period;
+
+ -- Model I2C sensor slaves as on the UniBoard
+ CONSTANT c_temp_high : NATURAL := 85;
+ CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
+ CONSTANT c_fpga_temp : INTEGER := 60;
+ CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW
+ CONSTANT c_eth_temp : INTEGER := 40;
+ CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L
+ CONSTANT c_hot_swap_R_sense : REAL := 0.01; -- = 10 mOhm on UniBoard
+
+ CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
+ CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
+ CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
+
+ CONSTANT c_sens_nof_result : NATURAL := 4 + 1;
+ CONSTANT c_sens_expected : t_natural_arr(0 TO c_sens_nof_result-1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb2_board_sens_ctrl + sens_err
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL start : STD_LOGIC;
+
+ SIGNAL reg_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_miso : t_mem_miso;
+
+ SIGNAL sens_val : STD_LOGIC;
+ SIGNAL sens_dat : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+
+ SIGNAL scl_stretch : STD_LOGIC := 'Z';
+ SIGNAL scl : STD_LOGIC;
+ SIGNAL sda : STD_LOGIC;
+
+BEGIN
+
+ rst <= '0' AFTER 4*c_clk_period;
+ clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+
+ -- I2C bus
+ scl <= 'H'; -- model I2C pull up
+ sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify sens_err
+
+ scl <= scl_stretch;
+
+ sens_clk_stretch : PROCESS (scl)
+ BEGIN
+ IF falling_edge(scl) THEN
+ scl_stretch <= '0', 'Z' AFTER 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ END IF;
+ END PROCESS;
+
+ p_mm_reg_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE vI : NATURAL;
+ VARIABLE vJ : NATURAL;
+ BEGIN
+ start <= '0';
+ reg_mosi <= c_mem_mosi_rst;
+
+ proc_common_wait_until_low(clk, rst);
+ proc_common_wait_some_cycles(clk, 10);
+
+ FOR I IN 0 TO c_repeat-1 LOOP
+ -- start I2C access
+ start <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ start <= '0';
+
+ -- wait for I2C access to have finished
+ proc_common_wait_some_cycles(clk, sel_a_b(c_sim, 5000, 500000));
+
+ -- read I2C result data
+ FOR I IN 0 TO c_sens_nof_result-1 LOOP
+ proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi); -- read sens_data
+ END LOOP;
+
+ proc_common_wait_some_cycles(clk, 1000);
+ END LOOP;
+
+ proc_common_wait_some_cycles(clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ sens_val <= reg_miso.rdval;
+ sens_dat <= reg_miso.rddata(c_byte_w-1 DOWNTO 0);
+
+ -- Verify sensor data
+ p_verify : PROCESS
+ BEGIN
+ WAIT UNTIL rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+
+ proc_common_wait_until_high(clk, sens_val);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(0) REPORT "Wrong FPGA temperature value" SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(1) REPORT "Wrong ETH temperature value" SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(2) REPORT "Wrong hot swap V sense value" SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(3) REPORT "Wrong hot swap V source value" SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(4) REPORT "An I2C error occurred" SEVERITY ERROR;
+
+ END PROCESS;
+
+
+ -- I2C sensors master
+ u_mms_unb2_board_sens : ENTITY work.mms_unb2_board_sens
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
+
+ -- I2C slaves that are available for each FPGA
+ u_fpga_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_fpga_temp_address
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
+
+ -- I2C slaves that are available only via FPGA node 3
+ u_eth_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_eth_temp_address
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
+
+ u_power : ENTITY i2c_lib.dev_ltc4260
+ GENERIC MAP (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
+
+END tb;
+
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..13f29d91913a0a613615e253ad05da073e3e694c
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -0,0 +1,71 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+-- Purpose: Simulate phase behaviour of PLL in normal mode
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_unb2_board_clk125_pll IS
+END tb_unb2_board_clk125_pll;
+
+
+ARCHITECTURE tb OF tb_unb2_board_clk125_pll IS
+
+ CONSTANT c_ext_clk_period : TIME := 8 ns; -- 125 MHz
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL ext_rst : STD_LOGIC;
+ SIGNAL c0_clk20 : STD_LOGIC;
+ SIGNAL c1_clk50 : STD_LOGIC;
+ SIGNAL c2_clk100 : STD_LOGIC;
+ SIGNAL c3_clk125 : STD_LOGIC;
+ SIGNAL pll_locked : STD_LOGIC;
+
+BEGIN
+
+ tb_end <= '0', '1' AFTER c_ext_clk_period*5000;
+
+ ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
+ ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
+
+ dut_0 : ENTITY work.unb2_board_clk125_pll
+ PORT MAP (
+ arst => ext_rst,
+ clk125 => ext_clk,
+
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
+
+ pll_locked => pll_locked
+ );
+END tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a2e442c17a96dc1432cee7897a8e1f79917bea4d
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -0,0 +1,116 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+-- Purpose: Simulate phase behaviour of PLL in normal mode
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_unb2_board_clk200_pll IS
+END tb_unb2_board_clk200_pll;
+
+
+ARCHITECTURE tb OF tb_unb2_board_clk200_pll IS
+
+ CONSTANT c_ext_clk_period : TIME := 5 ns; -- 200 MHz
+ CONSTANT c_clk_vec_w : NATURAL := 6;
+ CONSTANT c_clk_div : NATURAL := 32;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL ext_rst : STD_LOGIC;
+
+ SIGNAL st_clk200_0 : STD_LOGIC;
+ SIGNAL st_rst200_0 : STD_LOGIC;
+
+ SIGNAL st_clk200p0 : STD_LOGIC;
+ SIGNAL st_rst200p0 : STD_LOGIC;
+
+ SIGNAL st_clk200_45 : STD_LOGIC;
+ SIGNAL st_rst200_45 : STD_LOGIC;
+
+ SIGNAL st_clk200p45 : STD_LOGIC;
+ SIGNAL st_rst200p45 : STD_LOGIC;
+
+ SIGNAL st_clk400 : STD_LOGIC;
+ SIGNAL st_rst400 : STD_LOGIC;
+
+ SIGNAL dp_clk200 : STD_LOGIC;
+ SIGNAL dp_rst200 : STD_LOGIC;
+
+BEGIN
+
+ tb_end <= '0', '1' AFTER c_ext_clk_period*5000;
+
+ ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
+ ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
+
+ dut_0 : ENTITY work.unb2_board_clk200_pll
+ GENERIC MAP (
+ g_clk200_phase_shift => "0"
+ )
+ PORT MAP (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
+
+ dut_45 : ENTITY work.unb2_board_clk200_pll
+ GENERIC MAP (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ PORT MAP (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => OPEN
+ );
+
+ dut_p6 : ENTITY work.unb2_board_clk200_pll
+ GENERIC MAP (
+ g_clk200_phase_shift => "0"
+ )
+ PORT MAP (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
+
+END tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cbd3d0290147c376a450c5b718e38c57f8d652db
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -0,0 +1,71 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+-- Purpose: Simulate phase behaviour of PLL in normal mode
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_unb2_board_clk25_pll IS
+END tb_unb2_board_clk25_pll;
+
+
+ARCHITECTURE tb OF tb_unb2_board_clk25_pll IS
+
+ CONSTANT c_ext_clk_period : TIME := 40 ns; -- 25 MHz
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL ext_rst : STD_LOGIC;
+ SIGNAL c0_clk20 : STD_LOGIC;
+ SIGNAL c1_clk50 : STD_LOGIC;
+ SIGNAL c2_clk100 : STD_LOGIC;
+ SIGNAL c3_clk125 : STD_LOGIC;
+ SIGNAL pll_locked : STD_LOGIC;
+
+BEGIN
+
+ tb_end <= '0', '1' AFTER c_ext_clk_period*5000;
+
+ ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
+ ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
+
+ dut_0 : ENTITY work.unb2_board_clk25_pll
+ PORT MAP (
+ arst => ext_rst,
+ clk25 => ext_clk,
+
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
+
+ pll_locked => pll_locked
+ );
+END tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a5dbd064dc9a2edc29f28336cfbba3bc4270b09c
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_unb2_board_node_ctrl IS
+END tb_unb2_board_node_ctrl;
+
+
+ARCHITECTURE tb OF tb_unb2_board_node_ctrl IS
+
+ CONSTANT c_scale : NATURAL := 100; -- scale to speed up simulation
+
+ CONSTANT c_xo_clk_period : TIME := 1 us; -- 1 MHz XO, slow XO to speed up simulation
+ CONSTANT c_mm_clk_period : TIME := c_xo_clk_period/5; -- 5 MHz PLL output from XO reference
+ CONSTANT c_mm_locked_time : TIME := 10 us;
+
+ CONSTANT c_pulse_us : NATURAL := 5; -- nof 5 MHz clk cycles to get us period
+ CONSTANT c_pulse_ms : NATURAL := 1000/c_scale; -- nof pulse_us pulses to get ms period
+ CONSTANT c_pulse_s : NATURAL := 1000; -- nof pulse_ms pulses to get s period
+
+ CONSTANT c_wdi_extend_w : NATURAL := 14; -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
+ CONSTANT c_wdi_period : TIME := 1000 ms; -- wdi toggle after c_wdi_period
+
+ -- Use c_sw_period=40000 ms to show that the c_wdi_extend_w=5 is not enough, the WD will kick in when the sw is off during reload
+ CONSTANT c_sw_period : TIME := 40000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ -- Use c_sw_period=10000 ms to show that the c_wdi_extend_w=5 is enough, the WD will not kick in when the sw is off during reload
+ --CONSTANT c_sw_period : TIME := 6000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+
+ SIGNAL mm_clk : STD_LOGIC := '0';
+ SIGNAL mm_locked : STD_LOGIC := '0';
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL wdi : STD_LOGIC := '0';
+ SIGNAL wdi_in : STD_LOGIC;
+ SIGNAL wdi_out : STD_LOGIC;
+
+ SIGNAL sw : STD_LOGIC := '0';
+
+ SIGNAL pulse_us : STD_LOGIC;
+ SIGNAL pulse_ms : STD_LOGIC;
+ SIGNAL pulse_s : STD_LOGIC;
+
+BEGIN
+
+ -- run 2000 ms
+
+ mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
+ mm_locked <= '0', '1' AFTER c_mm_locked_time;
+
+ wdi <= NOT wdi AFTER c_wdi_period/c_scale; -- wd interrupt
+ sw <= NOT sw AFTER c_sw_period/c_scale; -- sw active / reload
+
+ wdi_in <= wdi AND sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+
+ dut : ENTITY work.unb2_board_node_ctrl
+ GENERIC MAP (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ PORT MAP (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
+
+END tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..06f7e52d03b4c4be727e5f18049b20f9778e2ebd
--- /dev/null
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -0,0 +1,190 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb2_board_qsfp_leds
+-- Description:
+-- The test bench is self-stopping but not self-checking. Manually obeserve
+-- in the wave window that:
+-- 1) factory image:
+-- - green led is off
+-- - red led toggles
+-- 2) user image
+-- - red led is off
+-- - green led toggles when any xon='0'
+-- - green led is on continously when any xon='1'
+-- - green led goes briefly off when any sop='1'
+-- Usage:
+-- > as 3
+-- > run -a
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY tb_unb2_board_qsfp_leds IS
+END tb_unb2_board_qsfp_leds;
+
+ARCHITECTURE tb OF tb_unb2_board_qsfp_leds IS
+
+ CONSTANT c_clk_freq_hz : NATURAL := 200 * 10**6;
+ CONSTANT c_clk_period_ns : NATURAL := 10**9 / c_clk_freq_hz;
+ CONSTANT c_nof_clk_per_us : NATURAL := 1000 / c_clk_period_ns;
+
+ CONSTANT clk_period : TIME := c_clk_period_ns * 1 ns;
+
+ CONSTANT c_nof_qsfp : NATURAL := 2;
+ CONSTANT c_nof_lanes : NATURAL := c_nof_qsfp*c_quad;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC;
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pulse_us : STD_LOGIC;
+ SIGNAL pulse_ms : STD_LOGIC;
+ SIGNAL pulse_s : STD_LOGIC;
+
+ SIGNAL tx_siso_arr : t_dp_siso_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rst);
+ SIGNAL tx_sosi_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+
+ SIGNAL dbg_xon_arr : STD_LOGIC_VECTOR(c_nof_lanes-1 DOWNTO 0);
+ SIGNAL dbg_tx_sop_arr : STD_LOGIC_VECTOR(c_nof_lanes-1 DOWNTO 0);
+ SIGNAL dbg_rx_sop_arr : STD_LOGIC_VECTOR(c_nof_lanes-1 DOWNTO 0);
+
+ SIGNAL factory_green_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp-1 DOWNTO 0);
+ SIGNAL factory_red_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp-1 DOWNTO 0);
+
+ SIGNAL user_green_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp-1 DOWNTO 0);
+ SIGNAL user_red_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp-1 DOWNTO 0);
+
+ -- Cannot use proc_common_gen_pulse() to create sop in array.
+ -- proc_common_gen_pulse() works for dbg_sop, dbg_sosi.sop but not for dbg_sop_slv(I) or for tx_sosi_arr(I).sop.
+ -- The compiler then gives Error: "(vcom-1450) Actual (indexed name) for formal "pulse" is not a static signal name"
+ -- It does work if the array index is from a GENERATE statement, but it does not work when it is from a LOOP statement.
+ SIGNAL dbg_sop : STD_LOGIC;
+ SIGNAL dbg_sop_slv : STD_LOGIC_VECTOR(c_nof_lanes-1 DOWNTO 0);
+ SIGNAL dbg_sosi : t_dp_sosi;
+
+BEGIN
+
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
+ rst <= '1', '0' AFTER clk_period*7;
+
+ -- Ease observation of record fields in Wave window, by mapping them to a SLV
+ dbg_xon_arr <= func_dp_stream_arr_get(tx_siso_arr, "XON");
+ dbg_tx_sop_arr <= func_dp_stream_arr_get(tx_sosi_arr, "SOP");
+ dbg_rx_sop_arr <= func_dp_stream_arr_get(rx_sosi_arr, "SOP");
+
+ p_stimuli : PROCESS
+ BEGIN
+ tx_siso_arr <= (OTHERS=>c_dp_siso_rst);
+ tx_sosi_arr <= (OTHERS=>c_dp_sosi_rst);
+ rx_sosi_arr <= (OTHERS=>c_dp_sosi_rst);
+ proc_common_wait_some_pulses(clk, pulse_ms, 50);
+
+ -- Switch on each lane
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ tx_siso_arr(I).xon <= '1';
+ proc_common_wait_some_pulses(clk, pulse_ms, 10);
+ END LOOP;
+ proc_common_wait_some_pulses(clk, pulse_ms, 50);
+
+ -- Issue the sop of a Tx packet on each lane
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ -- Cannot use proc_common_gen_pulse(), because index I in a LOOP is not static
+ tx_sosi_arr(I).sop <= '1';
+ WAIT UNTIL rising_edge(clk);
+ tx_sosi_arr(I).sop <= '0';
+ proc_common_wait_some_pulses(clk, pulse_ms, 10);
+ END LOOP;
+ proc_common_wait_some_pulses(clk, pulse_ms, 50);
+
+ -- Issue the sop of an Rx packet on each lane
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ -- Cannot use proc_common_gen_pulse(), because index I in a LOOP is not static
+ rx_sosi_arr(I).sop <= '1';
+ WAIT UNTIL rising_edge(clk);
+ rx_sosi_arr(I).sop <= '0';
+ proc_common_wait_some_pulses(clk, pulse_ms, 10);
+ END LOOP;
+ proc_common_wait_some_pulses(clk, pulse_ms, 50);
+
+ -- Switch off each lane
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ tx_siso_arr(I).xon <= '0';
+ proc_common_wait_some_pulses(clk, pulse_ms, 10);
+ END LOOP;
+ proc_common_wait_some_pulses(clk, pulse_ms, 50);
+
+ tb_end <= '1';
+ proc_common_wait_some_pulses(clk, pulse_ms, 10);
+ WAIT;
+ END PROCESS;
+
+ u_unb2_factory_qsfp_leds : ENTITY work.unb2_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => TRUE, -- when true speed up led toggling in simulation
+ g_factory_image => TRUE, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
+
+ u_unb2_user_qsfp_leds : ENTITY work.unb2_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => TRUE, -- when true speed up led toggling in simulation
+ g_factory_image => FALSE, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
+
+END tb;