From 848a1d38852a4ba2bb685eb55cd67b2081f2f59c Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Wed, 16 Aug 2023 10:12:43 +0200
Subject: [PATCH] RTSD-82: add indent fix from vsg
---
.../lofar1/RSP/pfb2/src/vhdl/pfb2.vhd | 92 +-
.../lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd | 108 +-
.../lofar1/RSP/pfs/src/vhdl/pfs(str).vhd | 178 +-
applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd | 182 +-
.../RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd | 38 +-
.../pfs/src/vhdl/pfs_coefsbuf(stratix).vhd | 86 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd | 38 +-
.../RSP/pfs/src/vhdl/pfs_combine(rtl).vhd | 4 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd | 2 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd | 4 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd | 4 +-
.../RSP/pfs/src/vhdl/pfs_filter(rtl).vhd | 38 +-
.../RSP/pfs/src/vhdl/pfs_filter(stratix).vhd | 204 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd | 38 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd | 232 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd | 10 +-
.../src/vhdl/pfs_fir_coefsbuf(stratix).vhd | 78 +-
.../RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd | 4 +-
.../RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd | 14 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd | 2 +-
.../RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd | 154 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd | 4 +-
.../pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd | 114 +-
.../RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd | 4 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd | 4 +-
.../RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd | 4 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd | 4 +-
.../RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd | 34 +-
.../RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd | 114 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd | 6 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd | 42 +-
.../lofar1/RSP/pfs/src/vhdl/pfs_top.vhd | 2 +-
.../lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd | 48 +-
.../lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd | 4 +-
.../lofar1/RSP/pft2/src/vhdl/pft(str).vhd | 182 +-
applications/lofar1/RSP/pft2/src/vhdl/pft.vhd | 182 +-
.../lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd | 220 +-
.../lofar1/RSP/pft2/src/vhdl/pft_bf.vhd | 218 +-
.../RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd | 148 +-
.../lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd | 146 +-
.../RSP/pft2/src/vhdl/pft_buffer(rtl).vhd | 86 +-
.../lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd | 84 +-
.../RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd | 2 +-
.../lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd | 2 +-
.../lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd | 4 +-
.../RSP/pft2/src/vhdl/pft_reverse(rtl).vhd | 8 +-
.../lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd | 8 +-
.../RSP/pft2/src/vhdl/pft_separate(rtl).vhd | 132 +-
.../lofar1/RSP/pft2/src/vhdl/pft_separate.vhd | 126 +-
.../RSP/pft2/src/vhdl/pft_stage(str).vhd | 212 +-
.../lofar1/RSP/pft2/src/vhdl/pft_stage.vhd | 214 +-
.../RSP/pft2/src/vhdl/pft_switch(rtl).vhd | 38 +-
.../lofar1/RSP/pft2/src/vhdl/pft_switch.vhd | 36 +-
.../RSP/pft2/src/vhdl/pft_tmult(rtl).vhd | 148 +-
.../lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd | 150 +-
.../lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd | 42 +-
.../lofar1/RSP/pft2/src/vhdl/pft_top.vhd | 6 +-
.../RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd | 42 +-
.../lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd | 40 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd | 108 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd | 264 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd | 102 +-
.../lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd | 6 +-
.../lofar2_unb2b_adc_6ch_200MHz.vhd | 112 +-
.../tb_lofar2_unb2b_adc_6ch_200MHz.vhd | 94 +-
.../lofar2_unb2b_adc_full.vhd | 110 +-
.../tb_lofar2_unb2b_adc_full.vhd | 94 +-
.../lofar2_unb2b_adc_one_node.vhd | 108 +-
.../tb_lofar2_unb2b_adc_one_node.vhd | 94 +-
.../src/vhdl/lofar2_unb2b_adc.vhd | 556 +-
.../src/vhdl/lofar2_unb2b_adc_pkg.vhd | 12 +-
.../src/vhdl/mmm_lofar2_unb2b_adc.vhd | 546 +-
.../src/vhdl/node_adc_input_and_timing.vhd | 438 +-
.../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd | 418 +-
.../tb/vhdl/tb_lofar2_unb2b_adc.vhd | 98 +-
.../vhdl/tb_lofar2_unb2b_adc_multichannel.vhd | 254 +-
.../tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd | 110 +-
.../lofar2_unb2b_beamformer_one_node.vhd | 124 +-
...ofar2_unb2b_beamformer_one_node_256MHz.vhd | 124 +-
.../src/vhdl/lofar2_unb2b_beamformer.vhd | 950 +--
.../src/vhdl/lofar2_unb2b_beamformer_pkg.vhd | 14 +-
.../src/vhdl/mmm_lofar2_unb2b_beamformer.vhd | 884 +-
.../vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd | 642 +-
.../tb/vhdl/tb_lofar2_unb2b_beamformer.vhd | 152 +-
.../lofar2_unb2b_filterbank_full.vhd | 110 +-
.../lofar2_unb2b_filterbank_full_256MHz.vhd | 110 +-
.../src/vhdl/lofar2_unb2b_filterbank.vhd | 710 +-
.../src/vhdl/lofar2_unb2b_filterbank_pkg.vhd | 14 +-
.../src/vhdl/mmm_lofar2_unb2b_filterbank.vhd | 722 +-
.../vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd | 572 +-
.../tb/vhdl/tb_lofar2_unb2b_filterbank.vhd | 124 +-
.../lofar2_unb2b_ring_full.vhd | 118 +-
.../tb_lofar2_unb2b_ring_full.vhd | 106 +-
.../lofar2_unb2b_ring_one.vhd | 118 +-
.../tb_lofar2_unb2b_ring_one.vhd | 106 +-
.../src/vhdl/lofar2_unb2b_ring.vhd | 1024 +--
.../src/vhdl/lofar2_unb2b_ring_pkg.vhd | 14 +-
.../src/vhdl/mmc_lofar2_unb2b_ring.vhd | 554 +-
.../src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd | 432 +-
.../tb/vhdl/tb_lofar2_unb2b_ring.vhd | 134 +-
.../tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd | 20 +-
.../disturb2_unb2b_sdp_station_full.vhd | 142 +-
.../disturb2_unb2b_sdp_station_full_wg.vhd | 132 +-
.../tb_disturb2_unb2b_sdp_station_full_wg.vhd | 126 +-
.../lofar2_unb2b_sdp_station_adc.vhd | 110 +-
.../tb_lofar2_unb2b_sdp_station_adc.vhd | 118 +-
.../lofar2_unb2b_sdp_station_bf.vhd | 124 +-
.../tb_lofar2_unb2b_sdp_station_bf.vhd | 286 +-
...ofar2_unb2b_sdp_station_bf_bst_offload.vhd | 128 +-
.../lofar2_unb2b_sdp_station_fsub.vhd | 110 +-
.../tb_lofar2_unb2b_sdp_station_fsub.vhd | 120 +-
...ar2_unb2b_sdp_station_fsub_sst_offload.vhd | 128 +-
.../lofar2_unb2b_sdp_station_full.vhd | 142 +-
.../lofar2_unb2b_sdp_station_full_wg.vhd | 124 +-
.../lofar2_unb2b_sdp_station_xsub_one.vhd | 110 +-
.../tb_lofar2_unb2b_sdp_station_xsub_one.vhd | 120 +-
...unb2b_sdp_station_xsub_one_xst_offload.vhd | 128 +-
.../lofar2_unb2b_sdp_station_xsub_ring.vhd | 142 +-
.../tb_lofar2_unb2b_sdp_station_xsub_ring.vhd | 158 +-
.../src/vhdl/lofar2_unb2b_sdp_station.vhd | 1084 +--
.../src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd | 14 +-
.../src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd | 1770 ++--
.../qsys_lofar2_unb2b_sdp_station_pkg.vhd | 1104 +--
.../tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd | 138 +-
.../src/vhdl/lofar2_unb2c_ddrctrl.vhd | 908 +--
.../src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd | 468 +-
.../vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd | 368 +-
.../tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd | 58 +-
.../lofar2_unb2c_filterbank_full.vhd | 110 +-
.../lofar2_unb2c_filterbank_full_256MHz.vhd | 110 +-
.../src/vhdl/lofar2_unb2c_filterbank.vhd | 598 +-
.../src/vhdl/lofar2_unb2c_filterbank_pkg.vhd | 14 +-
.../src/vhdl/mmm_lofar2_unb2c_filterbank.vhd | 668 +-
.../vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd | 516 +-
.../tb/vhdl/tb_lofar2_unb2c_filterbank.vhd | 124 +-
.../lofar2_unb2c_ring_full.vhd | 102 +-
.../tb_lofar2_unb2c_ring_full.vhd | 90 +-
.../lofar2_unb2c_ring_one.vhd | 102 +-
.../tb_lofar2_unb2c_ring_one.vhd | 90 +-
.../src/vhdl/lofar2_unb2c_ring.vhd | 988 +--
.../src/vhdl/lofar2_unb2c_ring_pkg.vhd | 14 +-
.../src/vhdl/mmc_lofar2_unb2c_ring.vhd | 518 +-
.../src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd | 404 +-
.../tb/vhdl/tb_lofar2_unb2c_ring.vhd | 120 +-
.../tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd | 20 +-
.../disturb2_unb2c_sdp_station_full.vhd | 126 +-
.../disturb2_unb2c_sdp_station_full_wg.vhd | 108 +-
.../lofar2_unb2c_sdp_station_adc.vhd | 94 +-
.../tb_lofar2_unb2c_sdp_station_adc.vhd | 102 +-
.../tb_lofar2_unb2c_sdp_station_adc_jesd.vhd | 302 +-
.../lofar2_unb2c_sdp_station_bf.vhd | 108 +-
.../tb_lofar2_unb2c_sdp_station_bf.vhd | 282 +-
...ofar2_unb2c_sdp_station_bf_bst_offload.vhd | 182 +-
.../tb_tb_lofar2_unb2c_sdp_station_bf.vhd | 44 +-
.../lofar2_unb2c_sdp_station_bf_ring.vhd | 126 +-
.../tb_lofar2_unb2c_sdp_station_bf_ring.vhd | 302 +-
.../lofar2_unb2c_sdp_station_fsub.vhd | 94 +-
.../tb_lofar2_unb2c_sdp_station_fsub.vhd | 112 +-
...ar2_unb2c_sdp_station_fsub_sst_offload.vhd | 156 +-
.../tb_tb_lofar2_unb2c_sdp_station_fsub.vhd | 60 +-
.../lofar2_unb2c_sdp_station_full.vhd | 126 +-
.../lofar2_unb2c_sdp_station_full_wg.vhd | 108 +-
.../lofar2_unb2c_sdp_station_xsub_one.vhd | 94 +-
.../tb_lofar2_unb2c_sdp_station_xsub_one.vhd | 104 +-
...unb2c_sdp_station_xsub_one_xst_offload.vhd | 160 +-
.../lofar2_unb2c_sdp_station_xsub_ring.vhd | 126 +-
.../src/vhdl/lofar2_unb2c_sdp_station.vhd | 1046 +--
.../src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd | 14 +-
.../src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd | 1734 ++--
.../qsys_lofar2_unb2c_sdp_station_pkg.vhd | 1076 +--
.../tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd | 120 +-
.../src/vhdl/Prototype_ddrctrl_controller.vhd | 508 +-
.../libraries/ddrctrl/src/vhdl/ddrctrl.vhd | 310 +-
.../ddrctrl/src/vhdl/ddrctrl_controller.vhd | 586 +-
.../ddrctrl/src/vhdl/ddrctrl_input.vhd | 88 +-
.../vhdl/ddrctrl_input_address_counter.vhd | 72 +-
.../ddrctrl/src/vhdl/ddrctrl_input_pack.vhd | 4 +-
.../ddrctrl/src/vhdl/ddrctrl_input_repack.vhd | 158 +-
.../ddrctrl/src/vhdl/ddrctrl_output.vhd | 132 +-
.../src/vhdl/ddrctrl_output_repack.vhd | 6 +-
.../src/vhdl/ddrctrl_output_unpack.vhd | 198 +-
.../libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd | 80 +-
.../vhdl/node_sdp_adc_input_and_timing.vhd | 472 +-
.../sdp/src/vhdl/node_sdp_beamformer.vhd | 350 +-
.../sdp/src/vhdl/node_sdp_correlator.vhd | 506 +-
.../sdp/src/vhdl/node_sdp_filterbank.vhd | 222 +-
.../vhdl/node_sdp_oversampled_filterbank.vhd | 500 +-
.../sdp/src/vhdl/sdp_beamformer_local.vhd | 156 +-
.../sdp/src/vhdl/sdp_beamformer_output.vhd | 298 +-
.../sdp/src/vhdl/sdp_beamformer_remote.vhd | 182 +-
.../libraries/sdp/src/vhdl/sdp_bf_weights.vhd | 64 +-
.../src/vhdl/sdp_crosslets_subband_select.vhd | 254 +-
.../libraries/sdp/src/vhdl/sdp_info.vhd | 32 +-
.../libraries/sdp/src/vhdl/sdp_info_reg.vhd | 58 +-
.../lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd | 386 +-
.../libraries/sdp/src/vhdl/sdp_scope.vhd | 56 +-
.../libraries/sdp/src/vhdl/sdp_station.vhd | 1294 +--
.../sdp/src/vhdl/sdp_statistics_offload.vhd | 206 +-
.../sdp/src/vhdl/sdp_subband_equalizer.vhd | 212 +-
.../sdp/src/vhdl/sdp_subband_weights.vhd | 118 +-
.../vhdl/tb_sdp_crosslets_subband_select.vhd | 66 +-
.../libraries/sdp/tb/vhdl/tb_sdp_info.vhd | 12 +-
.../libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd | 168 +-
.../sdp/tb/vhdl/tb_sdp_statistics_offload.vhd | 252 +-
.../tb/vhdl/tb_tb_sdp_statistics_offload.vhd | 34 +-
.../src/vhdl/rdma_demo_eth_tester_wrapper.vhd | 182 +-
.../rdma_demo/src/vhdl/rdma_demo_pkg.vhd | 92 +-
.../vhdl/rdma_demo_roce_tester_wrapper.vhd | 188 +-
.../lofar2_unb2b_ring_bsp/ring_pkg.vhd | 14 +-
.../tb_lofar2_unb2b_ring_bsp.vhd | 126 +-
.../hardware/lofar2_unb2b_ring_bsp/top.vhd | 1830 ++---
.../top_components_pkg.vhd | 410 +-
.../ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd | 750 +-
.../ta2_unb2b_bsp/top_components_pkg.vhd | 384 +-
.../ta2_channel_cross/ta2_channel_cross.vhd | 164 +-
.../ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd | 296 +-
.../ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd | 94 +-
.../ta2_unb2b_1GbE_ip_wrapper.vhd | 66 +-
.../ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd | 654 +-
.../ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd | 570 +-
.../ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd | 132 +-
.../ta2_unb2b_jesd204b_ip_wrapper.vhd | 2 +-
.../ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd | 124 +-
.../ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd | 62 +-
.../src/vhdl/node_unb1_bn_capture.vhd | 376 +-
.../src/vhdl/unb1_bn_capture.vhd | 1080 +--
.../src/vhdl/unb1_bn_capture_input.vhd | 356 +-
.../src/vhdl/unb1_bn_capture_mux.vhd | 104 +-
.../src/vhdl/unb1_bn_capture_pkg.vhd | 16 +-
.../src/vhdl/unb1_bn_capture_storage.vhd | 194 +-
.../src/vhdl/unb1_bn_capture_storage_reg.vhd | 114 +-
.../tb/vhdl/tb_node_unb1_bn_capture.vhd | 350 +-
.../tb/vhdl/tb_unb1_bn_capture.vhd | 234 +-
.../tb/vhdl/tb_unb1_bn_capture_input.vhd | 200 +-
.../src/vhdl/node_unb1_bn_terminal_bg.vhd | 270 +-
.../src/vhdl/unb1_bn_terminal_bg.vhd | 678 +-
.../tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd | 202 +-
.../vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd | 66 +-
.../unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd | 344 +-
.../unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd | 164 +-
.../designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd | 512 +-
.../unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd | 116 +-
.../tb_unb1_ddr3_reorder_dual_rank.vhd | 26 +-
.../unb1_ddr3_reorder_dual_rank.vhd | 72 +-
.../tb_unb1_ddr3_reorder_single_rank.vhd | 26 +-
.../unb1_ddr3_reorder_single_rank.vhd | 72 +-
.../src/vhdl/mmm_unb1_ddr3_reorder.vhd | 402 +-
.../src/vhdl/node_unb1_ddr3_reorder.vhd | 386 +-
.../src/vhdl/unb1_ddr3_reorder.vhd | 544 +-
.../tb/vhdl/tb_unb1_ddr3_reorder.vhd | 114 +-
.../src/vhdl/mmm_unb1_ddr3_transpose.vhd | 378 +-
.../src/vhdl/unb1_ddr3_transpose.vhd | 634 +-
.../tb/vhdl/tb_unb1_ddr3_transpose.vhd | 86 +-
.../src/vhdl/mmm_unb1_fn_terminal_db.vhd | 328 +-
.../src/vhdl/node_unb1_fn_terminal_db.vhd | 266 +-
.../src/vhdl/unb1_fn_terminal_db.vhd | 434 +-
.../tb/vhdl/tb_unb1_fn_terminal_db.vhd | 272 +-
.../unb1_heater/src/vhdl/mmm_unb1_heater.vhd | 324 +-
.../src/vhdl/qsys_unb1_heater_pkg.vhd | 242 +-
.../unb1_heater/src/vhdl/unb1_heater.vhd | 394 +-
.../unb1_heater/tb/vhdl/tb_unb1_heater.vhd | 74 +-
.../tb_unb1_minimal_mm_arbiter.vhd | 10 +-
.../unb1_minimal_mm_arbiter.vhd | 62 +-
.../tb_unb1_minimal_qsys.vhd | 10 +-
.../tb_unb1_minimal_qsys_stimuli.vhd | 68 +-
.../unb1_minimal_qsys/unb1_minimal_qsys.vhd | 62 +-
.../mmm_unb1_minimal_qsys_wo_pll.vhd | 306 +-
.../qsys_wo_pll_unb1_minimal_pkg.vhd | 214 +-
.../tb_unb1_minimal_qsys_wo_pll.vhd | 74 +-
.../unb1_minimal_qsys_wo_pll.vhd | 370 +-
.../tb_unb1_minimal_sopc.vhd | 10 +-
.../unb1_minimal_sopc/unb1_minimal_sopc.vhd | 60 +-
.../src/vhdl/mmm_unb1_minimal.vhd | 706 +-
.../src/vhdl/qsys_unb1_minimal_pkg.vhd | 322 +-
.../unb1_minimal/src/vhdl/unb1_minimal.vhd | 370 +-
.../unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd | 74 +-
.../src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd | 296 +-
.../vhdl/node_unb1_terminal_bg_mesh_db.vhd | 344 +-
.../src/vhdl/unb1_terminal_bg_mesh_db.vhd | 504 +-
.../tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd | 272 +-
.../unb1_test_10GbE/tb_unb1_test_10GbE.vhd | 12 +-
.../unb1_test_10GbE/unb1_test_10GbE.vhd | 128 +-
.../tb_unb1_test_10GbE_tx_only.vhd | 12 +-
.../unb1_test_10GbE_tx_only.vhd | 110 +-
.../unb1_test_1GbE/tb_unb1_test_1GbE.vhd | 12 +-
.../unb1_test_1GbE/unb1_test_1GbE.vhd | 66 +-
.../unb1_test_all/tb_unb1_test_all.vhd | 12 +-
.../revisions/unb1_test_all/unb1_test_all.vhd | 146 +-
.../unb1_test_ddr/tb_unb1_test_ddr.vhd | 12 +-
.../revisions/unb1_test_ddr/unb1_test_ddr.vhd | 90 +-
.../tb_unb1_test_ddr_16g_MB_I.vhd | 12 +-
.../unb1_test_ddr_16g_MB_I.vhd | 84 +-
.../tb_unb1_test_ddr_16g_MB_II.vhd | 12 +-
.../unb1_test_ddr_16g_MB_II.vhd | 84 +-
.../tb_unb1_test_ddr_16g_MB_I_II.vhd | 12 +-
.../unb1_test_ddr_16g_MB_I_II.vhd | 94 +-
.../tb_unb1_test_ddr_MB_I.vhd | 12 +-
.../tb_unb1_test_ddr_MB_II.vhd | 12 +-
.../tb_unb1_test_ddr_MB_I_II.vhd | 12 +-
.../unb1_test_ddr_MB_I_II.vhd | 94 +-
.../unb1_test/src/vhdl/mmm_unb1_test.vhd | 924 +--
.../unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd | 666 +-
.../designs/unb1_test/src/vhdl/udp_stream.vhd | 338 +-
.../designs/unb1_test/src/vhdl/unb1_test.vhd | 1220 +--
.../unb1_test/src/vhdl/unb1_test_pkg.vhd | 70 +-
.../unb1_test/tb/vhdl/tb_unb1_test.vhd | 112 +-
.../src/vhdl/mmm_unb1_tr_10GbE.vhd | 296 +-
.../unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd | 633 +-
.../tb/vhdl/tb_unb1_tr_10GbE.vhd | 10 +-
.../unb1_board/src/vhdl/ctrl_unb1_board.vhd | 456 +-
.../src/vhdl/mms_unb1_board_sens.vhd | 84 +-
.../src/vhdl/mms_unb1_board_system_info.vhd | 116 +-
.../src/vhdl/node_unb1_fn_terminal_db.vhd | 266 +-
.../src/vhdl/unb1_board_back_io.vhd | 4 +-
.../src/vhdl/unb1_board_back_reorder.vhd | 130 +-
.../src/vhdl/unb1_board_back_select.vhd | 10 +-
.../unb1_board_back_uth_terminals_bidir.vhd | 104 +-
.../src/vhdl/unb1_board_clk200_pll.vhd | 162 +-
.../src/vhdl/unb1_board_clk25_pll.vhd | 32 +-
.../src/vhdl/unb1_board_clk_rst.vhd | 40 +-
.../src/vhdl/unb1_board_front_io.vhd | 52 +-
.../src/vhdl/unb1_board_mesh_io.vhd | 4 +-
.../vhdl/unb1_board_mesh_reorder_bidir.vhd | 58 +-
.../src/vhdl/unb1_board_mesh_reorder_rx.vhd | 12 +-
.../src/vhdl/unb1_board_mesh_reorder_tx.vhd | 38 +-
.../unb1_board_mesh_uth_terminals_bidir.vhd | 110 +-
.../src/vhdl/unb1_board_node_ctrl.vhd | 98 +-
.../src/vhdl/unb1_board_peripherals_pkg.vhd | 6 +-
.../unb1_board/src/vhdl/unb1_board_pkg.vhd | 82 +-
.../unb1_board/src/vhdl/unb1_board_sens.vhd | 82 +-
.../src/vhdl/unb1_board_sens_ctrl.vhd | 32 +-
.../src/vhdl/unb1_board_sens_reg.vhd | 36 +-
.../src/vhdl/unb1_board_system_info.vhd | 8 +-
.../src/vhdl/unb1_board_system_info_reg.vhd | 38 +-
.../src/vhdl/unb1_board_terminals_back.vhd | 228 +-
.../src/vhdl/unb1_board_terminals_mesh.vhd | 312 +-
.../src/vhdl/unb1_board_wdi_extend.vhd | 44 +-
.../src/vhdl/unb1_board_wdi_reg.vhd | 22 +-
.../tb/vhdl/tb_mms_unb1_board_sens.vhd | 102 +-
.../vhdl/tb_tb_tb_unb1_board_regression.vhd | 2 +-
.../tb/vhdl/tb_unb1_board_clk200_pll.vhd | 124 +-
.../vhdl/tb_unb1_board_mesh_reorder_bidir.vhd | 224 +-
.../tb/vhdl/tb_unb1_board_node_ctrl.vhd | 40 +-
.../unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd | 10 +-
.../tb/vhdl/unb1_board_back_model_sl.vhd | 22 +-
.../tb/vhdl/unb1_board_back_model_sosi.vhd | 22 +-
.../tb/vhdl/unb1_board_mesh_model_siso.vhd | 14 +-
.../tb/vhdl/unb1_board_mesh_model_sl.vhd | 16 +-
.../tb/vhdl/unb1_board_mesh_model_sosi.vhd | 14 +-
.../designs/unb2_led/src/vhdl/unb2_led.vhd | 152 +-
.../designs/unb2_led/tb/vhdl/tb_unb2_led.vhd | 18 +-
.../src/vhdl/mmm_unb2_minimal.vhd | 314 +-
.../src/vhdl/qsys_unb2_minimal_pkg.vhd | 256 +-
.../unb2_minimal/src/vhdl/unb2_minimal.vhd | 384 +-
.../unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd | 74 +-
.../unb2_pinning/src/vhdl/unb2_pinning.vhd | 1556 ++--
.../src/vhdl/unb2_singlemac.vhd | 508 +-
.../unb2_test_10GbE/tb_unb2_test_10GbE.vhd | 8 +-
.../unb2_test_10GbE/unb2_test_10GbE.vhd | 174 +-
.../unb2_test_1GbE/tb_unb2_test_1GbE.vhd | 8 +-
.../unb2_test_1GbE/unb2_test_1GbE.vhd | 86 +-
.../unb2_test_all/tb_unb2_test_all.vhd | 10 +-
.../revisions/unb2_test_all/unb2_test_all.vhd | 198 +-
.../tb_unb2_test_ddr_MB_I.vhd | 10 +-
.../unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd | 104 +-
.../tb_unb2_test_ddr_MB_II.vhd | 10 +-
.../unb2_test_ddr_MB_II.vhd | 104 +-
.../tb_unb2_test_ddr_MB_I_II.vhd | 10 +-
.../unb2_test_ddr_MB_I_II.vhd | 116 +-
.../unb2_test/src/vhdl/mmm_unb2_test.vhd | 942 +--
.../unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd | 700 +-
.../designs/unb2_test/src/vhdl/udp_stream.vhd | 348 +-
.../designs/unb2_test/src/vhdl/unb2_test.vhd | 1504 ++--
.../unb2_test/src/vhdl/unb2_test_pkg.vhd | 50 +-
.../unb2_test/tb/vhdl/tb_unb2_test.vhd | 254 +-
.../unb2_board/src/vhdl/ctrl_unb2_board.vhd | 604 +-
.../src/vhdl/mms_unb2_board_sens.vhd | 86 +-
.../src/vhdl/mms_unb2_board_system_info.vhd | 116 +-
.../src/vhdl/mms_unb2_fpga_sens.vhd | 100 +-
.../src/vhdl/unb2_board_back_io.vhd | 4 +-
.../src/vhdl/unb2_board_clk125_pll.vhd | 70 +-
.../src/vhdl/unb2_board_clk200_pll.vhd | 126 +-
.../src/vhdl/unb2_board_clk25_pll.vhd | 30 +-
.../src/vhdl/unb2_board_clk_rst.vhd | 40 +-
.../src/vhdl/unb2_board_front_io.vhd | 8 +-
.../src/vhdl/unb2_board_node_ctrl.vhd | 66 +-
.../src/vhdl/unb2_board_peripherals_pkg.vhd | 6 +-
.../unb2_board/src/vhdl/unb2_board_pkg.vhd | 20 +-
.../src/vhdl/unb2_board_pmbus_ctrl.vhd | 80 +-
.../src/vhdl/unb2_board_qsfp_leds.vhd | 92 +-
.../src/vhdl/unb2_board_ring_io.vhd | 4 +-
.../unb2_board/src/vhdl/unb2_board_sens.vhd | 118 +-
.../src/vhdl/unb2_board_sens_ctrl.vhd | 34 +-
.../src/vhdl/unb2_board_sens_reg.vhd | 36 +-
.../src/vhdl/unb2_board_system_info.vhd | 8 +-
.../src/vhdl/unb2_board_system_info_reg.vhd | 24 +-
.../src/vhdl/unb2_board_wdi_extend.vhd | 44 +-
.../src/vhdl/unb2_board_wdi_reg.vhd | 22 +-
.../src/vhdl/unb2_fpga_sens_reg.vhd | 44 +-
.../tb/vhdl/tb_mms_unb2_board_sens.vhd | 102 +-
.../tb/vhdl/tb_unb2_board_clk125_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2_board_clk200_pll.vhd | 76 +-
.../tb/vhdl/tb_unb2_board_clk25_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2_board_node_ctrl.vhd | 42 +-
.../tb/vhdl/tb_unb2_board_qsfp_leds.vhd | 92 +-
.../src/vhdl/unb2_board_10gbe.vhd | 36 +-
.../ddr4_micron46_mbIIskew_inst.vhd | 2 +-
.../ddr4_micron46_mbIskew_inst.vhd | 2 +-
.../src/vhdl/mmm_unb2a_heater.vhd | 332 +-
.../src/vhdl/qsys_unb2a_heater_pkg.vhd | 270 +-
.../unb2a_heater/src/vhdl/unb2a_heater.vhd | 464 +-
.../unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd | 74 +-
.../designs/unb2a_led/src/vhdl/unb2a_led.vhd | 152 +-
.../unb2a_led/tb/vhdl/tb_unb2a_led.vhd | 20 +-
.../src/vhdl/mmm_unb2a_minimal.vhd | 314 +-
.../src/vhdl/qsys_unb2a_minimal_pkg.vhd | 256 +-
.../unb2a_minimal/src/vhdl/unb2a_minimal.vhd | 420 +-
.../tb/vhdl/tb_unb2a_minimal.vhd | 104 +-
.../unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd | 8 +-
.../unb2a_test_10GbE/unb2a_test_10GbE.vhd | 174 +-
.../unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd | 8 +-
.../unb2a_test_1GbE/unb2a_test_1GbE.vhd | 86 +-
.../unb2a_test_all/tb_unb2a_test_all.vhd | 10 +-
.../unb2a_test_all/unb2a_test_all.vhd | 198 +-
.../tb_unb2a_test_ddr_MB_I.vhd | 10 +-
.../unb2a_test_ddr_MB_I.vhd | 104 +-
.../tb_unb2a_test_ddr_MB_II.vhd | 10 +-
.../unb2a_test_ddr_MB_II.vhd | 104 +-
.../tb_unb2a_test_ddr_MB_I_II.vhd | 10 +-
.../unb2a_test_ddr_MB_I_II.vhd | 116 +-
.../unb2a_test/src/vhdl/mmm_unb2a_test.vhd | 982 +--
.../src/vhdl/qsys_unb2a_test_pkg.vhd | 730 +-
.../unb2a_test/src/vhdl/udp_stream.vhd | 350 +-
.../unb2a_test/src/vhdl/unb2a_test.vhd | 1528 ++--
.../unb2a_test/src/vhdl/unb2a_test_pkg.vhd | 50 +-
.../unb2a_test/tb/vhdl/tb_unb2a_test.vhd | 254 +-
.../unb2a_board/src/vhdl/ctrl_unb2_board.vhd | 598 +-
.../src/vhdl/mms_unb2_board_sens.vhd | 88 +-
.../src/vhdl/mms_unb2_board_system_info.vhd | 116 +-
.../src/vhdl/mms_unb2_fpga_sens.vhd | 100 +-
.../src/vhdl/unb2_board_back_io.vhd | 4 +-
.../src/vhdl/unb2_board_clk125_pll.vhd | 70 +-
.../src/vhdl/unb2_board_clk200_pll.vhd | 126 +-
.../src/vhdl/unb2_board_clk25_pll.vhd | 30 +-
.../src/vhdl/unb2_board_clk_rst.vhd | 40 +-
.../src/vhdl/unb2_board_front_io.vhd | 8 +-
.../src/vhdl/unb2_board_hmc_ctrl.vhd | 122 +-
.../src/vhdl/unb2_board_node_ctrl.vhd | 66 +-
.../src/vhdl/unb2_board_peripherals_pkg.vhd | 6 +-
.../unb2a_board/src/vhdl/unb2_board_pkg.vhd | 20 +-
.../src/vhdl/unb2_board_pmbus_ctrl.vhd | 122 +-
.../src/vhdl/unb2_board_qsfp_leds.vhd | 92 +-
.../src/vhdl/unb2_board_ring_io.vhd | 4 +-
.../unb2a_board/src/vhdl/unb2_board_sens.vhd | 180 +-
.../src/vhdl/unb2_board_sens_ctrl.vhd | 132 +-
.../src/vhdl/unb2_board_sens_reg.vhd | 36 +-
.../src/vhdl/unb2_board_system_info.vhd | 8 +-
.../src/vhdl/unb2_board_system_info_reg.vhd | 24 +-
.../src/vhdl/unb2_board_wdi_extend.vhd | 44 +-
.../src/vhdl/unb2_board_wdi_reg.vhd | 22 +-
.../src/vhdl/unb2_fpga_sens_reg.vhd | 44 +-
.../tb/vhdl/tb_mms_unb2_board_sens.vhd | 110 +-
.../tb/vhdl/tb_unb2_board_clk125_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2_board_clk200_pll.vhd | 76 +-
.../tb/vhdl/tb_unb2_board_clk25_pll.vhd | 22 +-
.../tb/vhdl/tb_unb2_board_node_ctrl.vhd | 42 +-
.../tb/vhdl/tb_unb2_board_qsfp_leds.vhd | 92 +-
.../src/vhdl/unb2_board_10gbe.vhd | 34 +-
.../src/vhdl/unb2b_arp_ping.vhd | 344 +-
.../unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd | 358 +-
.../unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd | 40 +-
.../tb/vhdl/tb_unb2b_arp_ping.vhd | 370 +-
.../src/vhdl/mmm_unb2b_heater.vhd | 336 +-
.../src/vhdl/qsys_unb2b_heater_pkg.vhd | 270 +-
.../unb2b_heater/src/vhdl/unb2b_heater.vhd | 484 +-
.../unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd | 74 +-
.../altjesd_ss_RX_corepll_inst.vhd | 2 +-
.../altjesd_ss_RX_frame_reset_inst.vhd | 2 +-
.../altjesd_ss_RX_link_reset_inst.vhd | 2 +-
.../altjesd_ss_RX_reset_seq_inst.vhd | 2 +-
.../altjesd_ss_RX_xcvr_reset_control_inst.vhd | 2 +-
.../device_clk/device_clk_inst.vhd | 2 +-
.../frame_clk/frame_clk_inst.vhd | 2 +-
.../ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd | 2 +-
.../link_clk/link_clk_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_avs_common_mm_0_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_avs_common_mm_1_inst.vhd | 2 +-
.../avs2_eth_coe_10/sim/avs2_eth_coe.vhd | 8 +-
.../sim/common_network_layers_pkg.vhd | 77 +-
.../avs2_eth_coe_10/sim/common_pkg.vhd | 960 +--
.../avs2_eth_coe_10/sim/dp_stream_pkg.vhd | 536 +-
.../avs2_eth_coe_10/sim/eth_pkg.vhd | 72 +-
.../avs2_eth_coe_10/sim/tech_tse_pkg.vhd | 4 +-
.../avs2_eth_coe_10/synth/avs2_eth_coe.vhd | 8 +-
.../synth/common_network_layers_pkg.vhd | 77 +-
.../avs2_eth_coe_10/synth/common_pkg.vhd | 960 +--
.../avs2_eth_coe_10/synth/dp_stream_pkg.vhd | 536 +-
.../avs2_eth_coe_10/synth/eth_pkg.vhd | 72 +-
.../avs2_eth_coe_10/synth/tech_tse_pkg.vhd | 4 +-
.../qsys_unb2b_minimal_avs_eth_0_inst.vhd | 2 +-
.../qsys_unb2b_minimal_clk_0_inst.vhd | 2 +-
.../qsys_unb2b_minimal_cpu_0_inst.vhd | 2 +-
.../qsys_unb2b_minimal_jesd204_inst.vhd | 2 +-
..._0_altera_avalon_jtag_uart_180_tj65noi.vhd | 754 +-
.../qsys_unb2b_minimal_jtag_uart_0_inst.vhd | 2 +-
...tera_avalon_onchip_memory2_180_lo46q2y.vhd | 110 +-
...ys_unb2b_minimal_onchip_memory2_0_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_pio_pps_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_pio_system_info_inst.vhd | 2 +-
..._pio_wdi_altera_avalon_pio_180_2botkdq.vhd | 40 +-
.../qsys_unb2b_minimal_pio_wdi_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_dpmm_data_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_epcs_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
..._unb2b_minimal_reg_fpga_temp_sens_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...b2b_minimal_reg_fpga_voltage_sens_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_mmdp_data_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_remu_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_unb_sens_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
.../qsys_unb2b_minimal_reg_wdi_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_rom_system_info_inst.vhd | 2 +-
...imer_0_altera_avalon_timer_180_5qqtsby.vhd | 72 +-
.../qsys_unb2b_minimal_timer_0_inst.vhd | 2 +-
.../unb2b_jesd_node0/unb2b_jesd_node0.vhd | 108 +-
.../altjesd_ss_RX_corepll_inst.vhd | 2 +-
.../altjesd_ss_RX_frame_reset_inst.vhd | 2 +-
.../altjesd_ss_RX_link_reset_inst.vhd | 2 +-
.../altjesd_ss_RX_reset_seq_inst.vhd | 2 +-
.../altjesd_ss_RX_xcvr_reset_control_inst.vhd | 2 +-
.../device_clk/device_clk_inst.vhd | 2 +-
.../frame_clk/frame_clk_inst.vhd | 2 +-
.../ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd | 2 +-
.../link_clk/link_clk_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
...sys_unb2b_minimal_avs_common_mm_0_inst.vhd | 2 +-
.../avs_common_mm_10/sim/avs_common_mm.vhd | 2 +-
.../avs_common_mm_10/synth/avs_common_mm.vhd | 2 +-
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.../avs2_eth_coe_10/sim/avs2_eth_coe.vhd | 8 +-
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.../common/src/vhdl/common_add_symbol.vhd | 80 +-
.../common/src/vhdl/common_adder_staged.vhd | 158 +-
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.../base/common/src/vhdl/common_ddreg.vhd | 150 +-
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libraries/base/common/src/vhdl/common_evt.vhd | 4 +-
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.../src/vhdl/common_fifo_dc_mixed_widths.vhd | 80 +-
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.../src/vhdl/common_lfsr_sequences_pkg.vhd | 626 +-
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.../base/common/src/vhdl/common_mem_pkg.vhd | 138 +-
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.../src/vhdl/common_network_layers_pkg.vhd | 93 +-
.../vhdl/common_network_total_header_pkg.vhd | 300 +-
.../base/common/src/vhdl/common_operation.vhd | 34 +-
.../common/src/vhdl/common_operation_tree.vhd | 84 +-
.../src/vhdl/common_paged_ram_crw_crw.vhd | 202 +-
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.../common/src/vhdl/common_paged_ram_w_rr.vhd | 64 +-
.../src/vhdl/common_paged_ram_ww_rr.vhd | 66 +-
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.../src/vhdl/common_pipeline_integer.vhd | 36 +-
.../src/vhdl/common_pipeline_natural.vhd | 36 +-
.../common/src/vhdl/common_pipeline_sl.vhd | 38 +-
.../src/vhdl/common_pipeline_symbol.vhd | 80 +-
libraries/base/common/src/vhdl/common_pkg.vhd | 1238 +--
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.../common/src/vhdl/common_pulser_us_ms_s.vhd | 76 +-
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.../src/vhdl/common_ram_cr_cw_ratio.vhd | 58 +-
.../common/src/vhdl/common_ram_crw_cr.vhd | 56 +-
.../common/src/vhdl/common_ram_crw_crw.vhd | 178 +-
.../src/vhdl/common_ram_crw_crw_ratio.vhd | 146 +-
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.../src/vhdl/common_reg_cross_domain.vhd | 26 +-
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.../common/src/vhdl/common_reg_r_w_dc.vhd | 162 +-
.../common/src/vhdl/common_reinterleave.vhd | 80 +-
.../common/src/vhdl/common_reorder_symbol.vhd | 162 +-
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.../common/src/vhdl/common_reverse_n_data.vhd | 132 +-
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.../common/src/vhdl/common_rl_increase.vhd | 2 +-
.../common/src/vhdl/common_rl_register.vhd | 68 +-
libraries/base/common/src/vhdl/common_rom.vhd | 40 +-
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.../src/vhdl/common_select_m_symbols.vhd | 58 +-
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.../base/common/src/vhdl/common_shiftram.vhd | 87 +-
.../base/common/src/vhdl/common_shiftreg.vhd | 136 +-
.../src/vhdl/common_shiftreg_symbol.vhd | 44 +-
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.../src/vhdl/common_transpose_symbol.vhd | 80 +-
.../common/src/vhdl/common_variable_delay.vhd | 4 +-
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libraries/base/common/src/vhdl/common_zip.vhd | 4 +-
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libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd | 78 +-
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libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd | 78 +-
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libraries/base/dp/src/vhdl/dp_stream_pkg.vhd | 572 +-
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libraries/base/dp/src/vhdl/dp_unfolder.vhd | 122 +-
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libraries/base/dp/src/vhdl/dp_xonoff.vhd | 4 +-
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.../src/vhdl/mms_dp_force_data_serial_arr.vhd | 68 +-
libraries/base/dp/src/vhdl/mms_dp_gain.vhd | 92 +-
.../base/dp/src/vhdl/mms_dp_gain_arr.vhd | 228 +-
.../base/dp/src/vhdl/mms_dp_gain_serial.vhd | 90 +-
.../dp/src/vhdl/mms_dp_gain_serial_arr.vhd | 240 +-
.../base/dp/src/vhdl/mms_dp_packet_merge.vhd | 80 +-
.../base/dp/src/vhdl/mms_dp_ram_from_mm.vhd | 68 +-
libraries/base/dp/src/vhdl/mms_dp_scale.vhd | 98 +-
libraries/base/dp/src/vhdl/mms_dp_split.vhd | 94 +-
.../base/dp/src/vhdl/mms_dp_sync_checker.vhd | 102 +-
.../dp/src/vhdl/mms_dp_sync_checker_arr.vhd | 74 +-
.../base/dp/src/vhdl/mms_dp_throttle.vhd | 64 +-
libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd | 130 +-
libraries/base/dp/tb/vhdl/dp_phy_link.vhd | 2 +-
.../base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd | 14 +-
.../base/dp/tb/vhdl/dp_sosi_recorder.vhd | 14 +-
libraries/base/dp/tb/vhdl/dp_statistics.vhd | 16 +-
.../base/dp/tb/vhdl/dp_stream_player.vhd | 14 +-
.../base/dp/tb/vhdl/dp_stream_rec_play.vhd | 42 +-
.../base/dp/tb/vhdl/dp_stream_stimuli.vhd | 14 +-
.../base/dp/tb/vhdl/dp_stream_verify.vhd | 14 +-
libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd | 104 +-
libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd | 136 +-
libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd | 52 +-
libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd | 58 +-
.../base/dp/tb/vhdl/tb_dp_block_from_mm.vhd | 128 +-
libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd | 58 +-
.../dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd | 132 +-
.../base/dp/tb/vhdl/tb_dp_block_reshape.vhd | 144 +-
.../dp/tb/vhdl/tb_dp_block_reshape_sync.vhd | 170 +-
.../base/dp/tb/vhdl/tb_dp_block_select.vhd | 114 +-
.../vhdl/tb_dp_block_validate_bsn_at_sync.vhd | 160 +-
.../tb/vhdl/tb_dp_block_validate_channel.vhd | 110 +-
.../dp/tb/vhdl/tb_dp_block_validate_err.vhd | 154 +-
.../tb/vhdl/tb_dp_block_validate_length.vhd | 112 +-
libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd | 62 +-
.../base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd | 236 +-
.../base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd | 74 +-
.../base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd | 68 +-
.../base/dp/tb/vhdl/tb_dp_bsn_source.vhd | 44 +-
.../base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd | 60 +-
.../dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd | 149 +-
.../base/dp/tb/vhdl/tb_dp_calculate_crc.vhd | 82 +-
libraries/base/dp/tb/vhdl/tb_dp_concat.vhd | 36 +-
.../dp/tb/vhdl/tb_dp_concat_field_blk.vhd | 320 +-
libraries/base/dp/tb/vhdl/tb_dp_counter.vhd | 58 +-
.../base/dp/tb/vhdl/tb_dp_counter_func.vhd | 50 +-
.../base/dp/tb/vhdl/tb_dp_counter_offset.vhd | 60 +-
.../base/dp/tb/vhdl/tb_dp_deinterleave.vhd | 42 +-
.../tb_dp_deinterleave_interleave_to_one.vhd | 260 +-
.../tb_dp_deinterleave_one_to_n_to_one.vhd | 256 +-
libraries/base/dp/tb/vhdl/tb_dp_demux.vhd | 88 +-
.../base/dp/tb/vhdl/tb_dp_distribute.vhd | 142 +-
.../base/dp/tb/vhdl/tb_dp_example_dut.vhd | 158 +-
.../base/dp/tb/vhdl/tb_dp_example_no_dut.vhd | 14 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd | 64 +-
.../base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd | 74 +-
.../dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd | 134 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd | 58 +-
.../base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd | 72 +-
.../base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd | 64 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd | 94 +-
libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd | 62 +-
.../base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd | 126 +-
.../base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd | 190 +-
libraries/base/dp/tb/vhdl/tb_dp_flush.vhd | 48 +-
libraries/base/dp/tb/vhdl/tb_dp_folder.vhd | 62 +-
libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd | 133 +-
.../base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd | 127 +-
libraries/base/dp/tb/vhdl/tb_dp_gap.vhd | 44 +-
.../dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd | 118 +-
.../base/dp/tb/vhdl/tb_dp_latency_adapter.vhd | 38 +-
.../base/dp/tb/vhdl/tb_dp_latency_fifo.vhd | 56 +-
libraries/base/dp/tb/vhdl/tb_dp_mux.vhd | 66 +-
.../dp/tb/vhdl/tb_dp_offload_rx_filter.vhd | 156 +-
.../base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd | 536 +-
libraries/base/dp/tb/vhdl/tb_dp_packet.vhd | 70 +-
.../base/dp/tb/vhdl/tb_dp_packet_merge.vhd | 72 +-
.../base/dp/tb/vhdl/tb_dp_packetizing.vhd | 444 +-
.../dp/tb/vhdl/tb_dp_pad_insert_remove.vhd | 68 +-
libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd | 32 +-
.../base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd | 72 +-
libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd | 1754 ++--
.../base/dp/tb/vhdl/tb_dp_reinterleave.vhd | 46 +-
libraries/base/dp/tb/vhdl/tb_dp_repack.vhd | 102 +-
.../base/dp/tb/vhdl/tb_dp_repack_data.vhd | 230 +-
.../base/dp/tb/vhdl/tb_dp_repack_legacy.vhd | 244 +-
.../base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd | 244 +-
.../dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd | 208 +-
.../base/dp/tb/vhdl/tb_dp_rsn_source.vhd | 96 +-
.../base/dp/tb/vhdl/tb_dp_selector_arr.vhd | 116 +-
libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd | 68 +-
libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd | 48 +-
libraries/base/dp/tb/vhdl/tb_dp_split.vhd | 46 +-
.../dp/tb/vhdl/tb_dp_strobe_total_count.vhd | 88 +-
libraries/base/dp/tb/vhdl/tb_dp_switch.vhd | 58 +-
.../base/dp/tb/vhdl/tb_dp_sync_checker.vhd | 40 +-
.../base/dp/tb/vhdl/tb_dp_sync_insert.vhd | 38 +-
.../base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd | 54 +-
.../base/dp/tb/vhdl/tb_dp_sync_recover.vhd | 46 +-
.../base/dp/tb/vhdl/tb_dp_tail_remove.vhd | 86 +-
.../base/dp/tb/vhdl/tb_dp_throttle_sop.vhd | 64 +-
.../base/dp/tb/vhdl/tb_dp_throttle_xon.vhd | 50 +-
libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd | 34 +-
.../dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd | 40 +-
.../dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd | 104 +-
.../tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd | 102 +-
.../base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd | 86 +-
.../base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd | 196 +-
.../dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd | 234 +-
.../base/dp/tb/vhdl/tb_mms_dp_fields.vhd | 94 +-
.../base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd | 98 +-
.../tb_mms_dp_force_data_parallel_arr.vhd | 168 +-
.../vhdl/tb_mms_dp_force_data_serial_arr.vhd | 128 +-
.../base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd | 148 +-
.../dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd | 174 +-
libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd | 40 +-
.../dp/tb/vhdl/tb_mms_dp_sync_checker.vhd | 50 +-
.../base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd | 106 +-
libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd | 4 +-
.../dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd | 4 +-
.../tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd | 4 +-
.../dp/tb/vhdl/tb_tb_dp_block_reshape.vhd | 6 +-
.../tb/vhdl/tb_tb_dp_block_reshape_sync.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_block_select.vhd | 10 +-
.../tb_tb_dp_block_validate_bsn_at_sync.vhd | 8 +-
.../vhdl/tb_tb_dp_block_validate_channel.vhd | 12 +-
.../tb/vhdl/tb_tb_dp_block_validate_err.vhd | 14 +-
.../vhdl/tb_tb_dp_block_validate_length.vhd | 10 +-
.../base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd | 4 +-
.../dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd | 4 +-
.../tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd | 4 +-
.../dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd | 16 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd | 2 +-
.../dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd | 20 +-
.../base/dp/tb/vhdl/tb_tb_dp_counter.vhd | 6 +-
...b_tb_dp_deinterleave_interleave_to_one.vhd | 28 +-
.../tb_tb_dp_deinterleave_one_to_n_to_one.vhd | 36 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd | 6 +-
.../base/dp/tb/vhdl/tb_tb_dp_distribute.vhd | 6 +-
.../base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd | 6 +-
.../dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd | 2 +-
.../tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd | 2 +-
.../dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd | 2 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd | 4 +-
.../dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd | 6 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd | 6 +-
.../dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd | 2 +-
.../dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd | 6 +-
.../base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd | 2 +-
.../dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd | 4 +-
.../base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd | 6 +-
.../dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd | 20 +-
.../dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd | 28 +-
.../base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd | 4 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd | 2 +-
.../tb/vhdl/tb_tb_dp_strobe_total_count.vhd | 2 +-
.../base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd | 28 +-
.../base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd | 16 +-
.../dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd | 18 +-
.../base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd | 18 +-
.../base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd | 22 +-
libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd | 24 +-
.../dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd | 4 +-
.../tb_tb_mms_dp_force_data_parallel_arr.vhd | 32 +-
.../tb_tb_mms_dp_force_data_serial_arr.vhd | 28 +-
.../base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd | 6 +-
.../tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd | 6 +-
.../dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd | 6 +-
libraries/base/mm/src/vhdl/mm_arbiter.vhd | 212 +-
libraries/base/mm/src/vhdl/mm_bus.vhd | 72 +-
libraries/base/mm/src/vhdl/mm_bus_comb.vhd | 12 +-
libraries/base/mm/src/vhdl/mm_bus_pipe.vhd | 84 +-
libraries/base/mm/src/vhdl/mm_fields.vhd | 58 +-
.../base/mm/src/vhdl/mm_latency_adapter.vhd | 38 +-
libraries/base/mm/src/vhdl/mm_master_mux.vhd | 12 +-
libraries/base/mm/src/vhdl/mm_pipeline.vhd | 6 +-
.../base/mm/src/vhdl/mm_slave_enable.vhd | 24 +-
libraries/base/mm/src/vhdl/mm_slave_mux.vhd | 32 +-
libraries/base/mm/tb/vhdl/mm_file.vhd | 20 +-
libraries/base/mm/tb/vhdl/mm_file_pkg.vhd | 337 +-
libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd | 28 +-
.../base/mm/tb/vhdl/mm_waitrequest_model.vhd | 8 +-
libraries/base/mm/tb/vhdl/tb_mm_bus.vhd | 118 +-
libraries/base/mm/tb/vhdl/tb_mm_file.vhd | 90 +-
.../base/mm/tb/vhdl/tb_mm_master_mux.vhd | 134 +-
libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd | 10 +-
libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd | 2 +-
.../base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd | 8 +-
.../reorder/src/vhdl/mms_reorder_rewire.vhd | 86 +-
.../base/reorder/src/vhdl/reorder_col.vhd | 284 +-
.../reorder/src/vhdl/reorder_col_select.vhd | 156 +-
.../reorder/src/vhdl/reorder_col_wide.vhd | 78 +-
.../src/vhdl/reorder_col_wide_select.vhd | 54 +-
.../base/reorder/src/vhdl/reorder_matrix.vhd | 168 +-
.../base/reorder/src/vhdl/reorder_pkg.vhd | 1113 ++-
.../reorder/src/vhdl/reorder_retreive.vhd | 42 +-
.../base/reorder/src/vhdl/reorder_rewire.vhd | 12 +-
.../reorder/src/vhdl/reorder_rewire_reg.vhd | 70 +-
.../base/reorder/src/vhdl/reorder_row.vhd | 144 +-
.../reorder/src/vhdl/reorder_row_select.vhd | 46 +-
.../reorder/src/vhdl/reorder_sequencer.vhd | 12 +-
.../base/reorder/src/vhdl/reorder_store.vhd | 10 +-
.../reorder/src/vhdl/reorder_transpose.vhd | 318 +-
.../reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd | 226 +-
.../reorder/tb/vhdl/tb_mmf_reorder_row.vhd | 230 +-
.../reorder/tb/vhdl/tb_mms_reorder_rewire.vhd | 1297 ++-
.../base/reorder/tb/vhdl/tb_reorder_col.vhd | 96 +-
.../tb/vhdl/tb_reorder_col_select_all.vhd | 208 +-
.../reorder/tb/vhdl/tb_reorder_col_wide.vhd | 62 +-
.../vhdl/tb_reorder_col_wide_row_select.vhd | 134 +-
.../reorder/tb/vhdl/tb_reorder_transpose.vhd | 416 +-
.../reorder/tb/vhdl/tb_tb_reorder_col.vhd | 2 +-
.../tb/vhdl/tb_tb_reorder_col_select_all.vhd | 20 +-
.../tb_tb_reorder_col_wide_row_select.vhd | 2 +-
libraries/base/ring/src/vhdl/ring_info.vhd | 38 +-
libraries/base/ring/src/vhdl/ring_lane.vhd | 158 +-
.../base/ring/src/vhdl/ring_lane_info.vhd | 30 +-
.../base/ring/src/vhdl/ring_lane_info_reg.vhd | 40 +-
libraries/base/ring/src/vhdl/ring_mux.vhd | 64 +-
libraries/base/ring/src/vhdl/ring_pkg.vhd | 68 +-
libraries/base/ring/src/vhdl/ring_rx.vhd | 196 +-
libraries/base/ring/src/vhdl/ring_tx.vhd | 154 +-
.../base/ring/tb/vhdl/tb_ring_lane_info.vhd | 12 +-
libraries/base/sens/src/vhdl/sens.vhd | 76 +-
libraries/base/sens/src/vhdl/sens_ctrl.vhd | 111 +-
libraries/base/sens/tb/vhdl/tb_sens.vhd | 136 +-
libraries/base/ss/src/vhdl/ss.vhd | 288 +-
libraries/base/ss/src/vhdl/ss_parallel.vhd | 176 +-
libraries/base/ss/src/vhdl/ss_reorder.vhd | 144 +-
libraries/base/ss/src/vhdl/ss_retrieve.vhd | 36 +-
libraries/base/ss/src/vhdl/ss_store.vhd | 10 +-
libraries/base/ss/src/vhdl/ss_wide.vhd | 82 +-
.../base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd | 226 +-
.../base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd | 230 +-
libraries/base/ss/tb/vhdl/tb_ss.vhd | 96 +-
libraries/base/ss/tb/vhdl/tb_ss_wide.vhd | 62 +-
libraries/base/ss/tb/vhdl/tb_tb_ss.vhd | 2 +-
libraries/base/tst/src/vhdl/tst_input.vhd | 10 +-
libraries/base/tst/src/vhdl/tst_output.vhd | 8 +-
libraries/base/uth/src/vhdl/uth_pkg.vhd | 24 +-
libraries/base/uth/src/vhdl/uth_rx.vhd | 160 +-
libraries/base/uth/src/vhdl/uth_rx_tlen.vhd | 10 +-
.../base/uth/src/vhdl/uth_terminal_bidir.vhd | 28 +-
.../base/uth/src/vhdl/uth_terminal_rx.vhd | 212 +-
.../base/uth/src/vhdl/uth_terminal_tx.vhd | 202 +-
libraries/base/uth/src/vhdl/uth_tx.vhd | 88 +-
libraries/base/uth/src/vhdl/uth_tx_tlen.vhd | 10 +-
.../uth/tb/vhdl/tb_tb_tb_uth_regression.vhd | 2 +-
libraries/base/uth/tb/vhdl/tb_tb_uth.vhd | 4 +-
.../base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd | 4 +-
.../base/uth/tb/vhdl/tb_tb_uth_terminals.vhd | 4 +-
libraries/base/uth/tb/vhdl/tb_uth.vhd | 152 +-
.../base/uth/tb/vhdl/tb_uth_dp_packet.vhd | 250 +-
.../base/uth/tb/vhdl/tb_uth_terminals.vhd | 212 +-
libraries/base/util/src/vhdl/util_heater.vhd | 304 +-
.../base/util/src/vhdl/util_heater_pkg.vhd | 4 +-
libraries/base/util/src/vhdl/util_logic.vhd | 2 +-
.../base/util/tb/vhdl/tb_util_heater.vhd | 42 +-
.../dsp/beamformer/src/vhdl/beamformer.vhd | 204 +-
.../dsp/beamformer/tb/vhdl/tb_beamformer.vhd | 72 +-
.../beamformer/tb/vhdl/tb_tb_beamformer.vhd | 46 +-
.../unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd | 390 +-
.../unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd | 228 +-
.../unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd | 436 +-
.../unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd | 50 +-
libraries/dsp/bf/src/vhdl/bf.vhd | 152 +-
libraries/dsp/bf/src/vhdl/bf_pkg.vhd | 6 +-
libraries/dsp/bf/src/vhdl/bf_unit.vhd | 432 +-
libraries/dsp/bf/tb/vhdl/tb_bf.vhd | 256 +-
libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd | 256 +-
.../src/vhdl/mmm_unb1_correlator.vhd | 414 +-
.../src/vhdl/unb1_correlator.vhd | 490 +-
.../tb/vhdl/tb_unb1_correlator.vhd | 10 +-
.../correlator/src/vhdl/corr_accumulator.vhd | 68 +-
.../dsp/correlator/src/vhdl/corr_adder.vhd | 78 +-
.../dsp/correlator/src/vhdl/corr_carousel.vhd | 8 +-
.../dsp/correlator/src/vhdl/corr_folder.vhd | 30 +-
.../src/vhdl/corr_folder_2arr_2.vhd | 72 +-
.../correlator/src/vhdl/corr_multiplier.vhd | 84 +-
.../src/vhdl/corr_output_framer.vhd | 58 +-
.../correlator/src/vhdl/corr_permutator.vhd | 10 +-
.../dsp/correlator/src/vhdl/corr_permutor.vhd | 98 +-
.../correlator/src/vhdl/corr_permutor_pkg.vhd | 10 +-
.../dsp/correlator/src/vhdl/corr_unfolder.vhd | 54 +-
.../src/vhdl/corr_visibility_buffer.vhd | 80 +-
.../dsp/correlator/src/vhdl/correlator.vhd | 186 +-
.../correlator/src/vhdl/correlator_dev.vhd | 88 +-
.../tb/vhdl/tb_corr_accumulator.vhd | 54 +-
.../correlator/tb/vhdl/tb_corr_carousel.vhd | 34 +-
.../dsp/correlator/tb/vhdl/tb_corr_folder.vhd | 10 +-
.../correlator/tb/vhdl/tb_corr_multiplier.vhd | 10 +-
.../correlator/tb/vhdl/tb_corr_permutator.vhd | 30 +-
.../correlator/tb/vhdl/tb_corr_permutor.vhd | 34 +-
.../dsp/correlator/tb/vhdl/tb_correlator.vhd | 306 +-
.../correlator/tb/vhdl/tb_correlator_dev.vhd | 112 +-
.../tb/vhdl/tb_tb_corr_accumulator.vhd | 22 +-
libraries/dsp/fft/src/vhdl/fft_lfsr.vhd | 4 +-
libraries/dsp/fft/src/vhdl/fft_pkg.vhd | 52 +-
libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd | 362 +-
libraries/dsp/fft/src/vhdl/fft_r2_par.vhd | 312 +-
libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd | 306 +-
libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd | 260 +-
.../fft/src/vhdl/fft_reorder_sepa_pipe.vhd | 122 +-
libraries/dsp/fft/src/vhdl/fft_sepa.vhd | 62 +-
libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd | 166 +-
libraries/dsp/fft/src/vhdl/fft_switch.vhd | 56 +-
libraries/dsp/fft/src/vhdl/fft_unswitch.vhd | 56 +-
libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd | 158 +-
.../fft/src/vhdl/fft_wide_unit_control.vhd | 178 +-
.../dsp/fft/tb/vhdl/tb_fft_functions.vhd | 8 +-
libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd | 50 +-
libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd | 184 +-
.../dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd | 178 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd | 54 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd | 50 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd | 202 +-
.../fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd | 86 +-
libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd | 72 +-
libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd | 132 +-
.../dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd | 142 +-
libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd | 342 +-
.../dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd | 240 +-
.../dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd | 240 +-
.../dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd | 242 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd | 72 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd | 72 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd | 134 +-
libraries/dsp/filter/src/vhdl/fil_pkg.vhd | 4 +-
.../dsp/filter/src/vhdl/fil_ppf_ctrl.vhd | 8 +-
.../dsp/filter/src/vhdl/fil_ppf_filter.vhd | 116 +-
.../dsp/filter/src/vhdl/fil_ppf_single.vhd | 190 +-
.../dsp/filter/src/vhdl/fil_ppf_wide.vhd | 74 +-
.../dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd | 112 +-
.../dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd | 114 +-
.../tb/vhdl/tb_fil_ppf_wide_file_data.vhd | 222 +-
.../filter/tb/vhdl/tb_tb_fil_ppf_single.vhd | 64 +-
.../dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd | 68 +-
.../tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd | 74 +-
.../fringe_stop/src/vhdl/fringe_stop_unit.vhd | 434 +-
.../tb/vhdl/tb_fringe_stop_unit.vhd | 160 +-
.../tb/vhdl/tb_mmf_fringe_stop_unit.vhd | 80 +-
.../tb/vhdl/tb_tb_fringe_stop_unit.vhd | 28 +-
.../tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd | 10 +-
libraries/dsp/iquv/src/vhdl/iquv.vhd | 574 +-
libraries/dsp/iquv/src/vhdl/iquv_accum.vhd | 126 +-
libraries/dsp/iquv/src/vhdl/iquv_iab.vhd | 626 +-
libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd | 176 +-
.../dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd | 60 +-
libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd | 64 +-
.../iquv/tb/vhdl/tb_iquv_iab_file_data.vhd | 72 +-
.../dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd | 4 +-
.../iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd | 4 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd | 44 +-
.../dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd | 172 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd | 96 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd | 150 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd | 2 +-
.../dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd | 268 +-
libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd | 256 +-
.../dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd | 6 +-
.../dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd | 38 +-
libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd | 58 +-
.../dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd | 32 +-
libraries/dsp/si/src/vhdl/si.vhd | 24 +-
libraries/dsp/si/src/vhdl/si_arr.vhd | 56 +-
libraries/dsp/si/tb/vhdl/tb_si.vhd | 34 +-
.../dsp/st/src/vhdl/mmp_st_histogram.vhd | 132 +-
libraries/dsp/st/src/vhdl/st_acc.vhd | 62 +-
libraries/dsp/st/src/vhdl/st_calc.vhd | 208 +-
libraries/dsp/st/src/vhdl/st_ctrl.vhd | 48 +-
libraries/dsp/st/src/vhdl/st_histogram.vhd | 78 +-
libraries/dsp/st/src/vhdl/st_sst.vhd | 262 +-
libraries/dsp/st/src/vhdl/st_xsq.vhd | 244 +-
libraries/dsp/st/src/vhdl/st_xsq_arr.vhd | 68 +-
libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd | 72 +-
libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd | 10 +-
libraries/dsp/st/src/vhdl/st_xst.vhd | 84 +-
libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd | 162 +-
.../dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd | 66 +-
libraries/dsp/st/tb/vhdl/tb_st_acc.vhd | 81 +-
libraries/dsp/st/tb/vhdl/tb_st_calc.vhd | 54 +-
libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd | 54 +-
libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd | 10 +-
libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd | 72 +-
libraries/dsp/st/tb/vhdl/tb_st_xst.vhd | 126 +-
.../dsp/st/tb/vhdl/tb_tb_st_histogram.vhd | 76 +-
libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd | 20 +-
libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd | 22 +-
.../dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd | 1338 +--
.../dsp/verify_pfb/tb_verify_pfb_response.vhd | 162 +-
libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd | 336 +-
libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd | 344 +-
libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd | 244 +-
libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd | 248 +-
.../dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd | 400 +-
.../dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd | 994 ++-
libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd | 146 +-
.../dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd | 394 +-
.../dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd | 374 +-
libraries/io/aduh/src/vhdl/aduh_dd.vhd | 232 +-
libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd | 10 +-
libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd | 70 +-
libraries/io/aduh/src/vhdl/aduh_monitor.vhd | 130 +-
.../io/aduh/src/vhdl/aduh_monitor_reg.vhd | 78 +-
libraries/io/aduh/src/vhdl/aduh_pll.vhd | 70 +-
libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd | 24 +-
libraries/io/aduh/src/vhdl/aduh_power_sum.vhd | 124 +-
libraries/io/aduh/src/vhdl/aduh_quad.vhd | 120 +-
libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd | 422 +-
.../io/aduh/src/vhdl/aduh_quad_scope.vhd | 36 +-
libraries/io/aduh/src/vhdl/aduh_verify.vhd | 56 +-
.../io/aduh/src/vhdl/aduh_verify_bit.vhd | 8 +-
libraries/io/aduh/src/vhdl/lvdsh_dd.vhd | 256 +-
libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd | 380 +-
.../io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd | 180 +-
libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd | 308 +-
libraries/io/aduh/src/vhdl/lvdsh_pll.vhd | 216 +-
.../io/aduh/src/vhdl/mms_aduh_monitor.vhd | 96 +-
.../io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd | 96 +-
libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd | 192 +-
libraries/io/aduh/tb/vhdl/adc08d1020.vhd | 6 +-
libraries/io/aduh/tb/vhdl/adu_half.vhd | 82 +-
libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd | 201 +-
.../io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd | 60 +-
libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd | 184 +-
.../io/aduh/tb/vhdl/tb_aduh_power_sum.vhd | 60 +-
libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd | 142 +-
libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd | 94 +-
.../io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd | 110 +-
libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd | 104 +-
.../io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd | 148 +-
.../io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd | 2 +-
.../io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd | 2 +-
libraries/io/ddr/src/vhdl/io_ddr.vhd | 432 +-
.../io/ddr/src/vhdl/io_ddr_cross_domain.vhd | 78 +-
libraries/io/ddr/src/vhdl/io_ddr_driver.vhd | 28 +-
.../ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd | 12 +-
libraries/io/ddr/src/vhdl/io_ddr_reg.vhd | 20 +-
libraries/io/ddr/src/vhdl/mms_io_ddr.vhd | 196 +-
libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd | 256 +-
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd | 222 +-
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd | 10 +-
libraries/io/ddr3/src/vhdl/ddr3.vhd | 344 +-
libraries/io/ddr3/src/vhdl/ddr3_driver.vhd | 46 +-
.../io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd | 26 +-
libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd | 286 +-
libraries/io/ddr3/src/vhdl/ddr3_reg.vhd | 116 +-
libraries/io/ddr3/src/vhdl/ddr3_seq.vhd | 14 +-
libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd | 378 +-
libraries/io/ddr3/src/vhdl/mms_ddr3.vhd | 172 +-
.../io/ddr3/src/vhdl/mms_ddr3_capture.vhd | 136 +-
libraries/io/ddr3/src/vhdl/seq_ddr3.vhd | 166 +-
libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd | 240 +-
.../io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd | 378 +-
libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd | 324 +-
libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd | 288 +-
libraries/io/epcs/src/vhdl/epcs_reg.vhd | 74 +-
libraries/io/epcs/src/vhdl/mms_epcs.vhd | 246 +-
libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd | 42 +-
.../src/vhdl/mmm_unb1_eth_10g.vhd | 432 +-
.../unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd | 816 +-
.../unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd | 130 +-
libraries/io/eth/src/vhdl/avs2_eth.vhd | 74 +-
libraries/io/eth/src/vhdl/avs2_eth_coe.vhd | 8 +-
libraries/io/eth/src/vhdl/eth.vhd | 662 +-
libraries/io/eth/src/vhdl/eth_buffer.vhd | 116 +-
libraries/io/eth/src/vhdl/eth_checksum.vhd | 14 +-
libraries/io/eth/src/vhdl/eth_control.vhd | 42 +-
libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd | 70 +-
libraries/io/eth/src/vhdl/eth_crc_word.vhd | 10 +-
libraries/io/eth/src/vhdl/eth_frm_discard.vhd | 6 +-
libraries/io/eth/src/vhdl/eth_hdr.vhd | 112 +-
libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd | 38 +-
libraries/io/eth/src/vhdl/eth_hdr_status.vhd | 28 +-
libraries/io/eth/src/vhdl/eth_hdr_store.vhd | 10 +-
libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd | 84 +-
.../eth/src/vhdl/eth_ip_header_checksum.vhd | 90 +-
.../io/eth/src/vhdl/eth_mm_reg_frame.vhd | 10 +-
.../io/eth/src/vhdl/eth_mm_registers.vhd | 196 +-
libraries/io/eth/src/vhdl/eth_pkg.vhd | 72 +-
libraries/io/eth/src/vhdl/eth_statistics.vhd | 68 +-
libraries/io/eth/src/vhdl/eth_stream.vhd | 146 +-
libraries/io/eth/src/vhdl/eth_stream_udp.vhd | 120 +-
libraries/io/eth/src/vhdl/eth_tester.vhd | 304 +-
libraries/io/eth/src/vhdl/eth_tester_pkg.vhd | 92 +-
libraries/io/eth/src/vhdl/eth_tester_rx.vhd | 210 +-
libraries/io/eth/src/vhdl/eth_tester_tx.vhd | 358 +-
libraries/io/eth/src/vhdl/eth_udp_channel.vhd | 8 +-
libraries/io/eth/tb/vhdl/tb_eth.vhd | 374 +-
libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd | 32 +-
libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd | 40 +-
libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd | 36 +-
libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd | 66 +-
.../eth/tb/vhdl/tb_eth_ip_header_checksum.vhd | 568 +-
.../io/eth/tb/vhdl/tb_eth_stream_udp.vhd | 158 +-
libraries/io/eth/tb/vhdl/tb_eth_tester.vhd | 198 +-
.../io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd | 134 +-
.../io/eth/tb/vhdl/tb_eth_tester_pkg.vhd | 20 +-
.../io/eth/tb/vhdl/tb_eth_udp_offload.vhd | 326 +-
libraries/io/eth/tb/vhdl/tb_tb_eth.vhd | 34 +-
.../tb/vhdl/tb_tb_eth_ip_header_checksum.vhd | 6 +-
.../io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd | 34 +-
libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd | 76 +-
.../eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd | 50 +-
.../eth/tb/vhdl/tb_tb_tb_eth_regression.vhd | 2 +-
libraries/io/eth1g/src/vhdl/eth1g.vhd | 654 +-
libraries/io/eth1g/src/vhdl/eth1g_master.vhd | 75 +-
libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd | 206 +-
libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd | 372 +-
libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd | 30 +-
.../io/fpga_sense/src/vhdl/fpga_sense.vhd | 122 +-
libraries/io/i2c/src/vhdl/avs_i2c_master.vhd | 92 +-
libraries/io/i2c/src/vhdl/i2c_bit.vhd | 520 +-
.../io/i2c/src/vhdl/i2c_bit_scl_sense.vhd | 516 +-
libraries/io/i2c/src/vhdl/i2c_byte.vhd | 468 +-
libraries/io/i2c/src/vhdl/i2c_commander.vhd | 322 +-
.../i2c/src/vhdl/i2c_commander_aduh_pkg.vhd | 140 +-
.../io/i2c/src/vhdl/i2c_commander_ctrl.vhd | 10 +-
.../io/i2c/src/vhdl/i2c_commander_pkg.vhd | 34 +-
.../io/i2c/src/vhdl/i2c_commander_reg.vhd | 22 +-
.../src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd | 106 +-
.../src/vhdl/i2c_commander_unb2_sens_pkg.vhd | 106 +-
.../i2c/src/vhdl/i2c_commander_unbh_pkg.vhd | 130 +-
libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd | 6082 +++++++++++---
.../io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd | 12 +-
.../io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd | 190 +-
libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd | 51 +-
libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd | 6 +-
libraries/io/i2c/src/vhdl/i2c_master.vhd | 190 +-
libraries/io/i2c/src/vhdl/i2c_mm.vhd | 202 +-
libraries/io/i2c/src/vhdl/i2c_pkg.vhd | 28 +-
libraries/io/i2c/src/vhdl/i2c_smbus.vhd | 134 +-
libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd | 239 +-
libraries/io/i2c/src/vhdl/i2cslave.vhd | 32 +-
libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd | 34 +-
libraries/io/i2c/tb/vhdl/dev_max1618.vhd | 32 +-
libraries/io/i2c/tb/vhdl/dev_max6652.vhd | 30 +-
libraries/io/i2c/tb/vhdl/dev_pca9555.vhd | 30 +-
libraries/io/i2c/tb/vhdl/dev_pmbus.vhd | 32 +-
libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd | 22 +-
.../io/i2c/tb/vhdl/tb_avs_i2c_master.vhd | 182 +-
libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd | 230 +-
.../tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd | 264 +-
.../tb/vhdl/tb_i2c_commander_unb2_sens.vhd | 304 +-
libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd | 407 +-
libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd | 56 +-
.../io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd | 2 +-
libraries/io/mac_10g/io_mac_10g.vhd | 74 +-
libraries/io/mdio/src/vhdl/avs_mdio.vhd | 68 +-
libraries/io/mdio/src/vhdl/mdio.vhd | 96 +-
libraries/io/mdio/src/vhdl/mdio_ctlr.vhd | 96 +-
libraries/io/mdio/src/vhdl/mdio_mm.vhd | 118 +-
libraries/io/mdio/src/vhdl/mdio_phy.vhd | 50 +-
libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd | 80 +-
libraries/io/mdio/src/vhdl/mdio_pkg.vhd | 14 +-
.../src/vhdl/mdio_vitesse_vsc8486_pkg.vhd | 8 +-
libraries/io/mdio/tb/vhdl/mmd_slave.vhd | 4 +-
libraries/io/mdio/tb/vhdl/tb_mdio.vhd | 90 +-
libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd | 76 +-
.../io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd | 108 +-
libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd | 112 +-
libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd | 214 +-
.../io/nw_10GbE/src/vhdl/nw_arp_request.vhd | 84 +-
.../io/nw_10GbE/src/vhdl/nw_ping_response.vhd | 118 +-
libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd | 378 +-
.../io/nw_10GbE/tb/vhdl/tb_nw_arp_request.vhd | 48 +-
.../nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd | 96 +-
.../io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd | 34 +-
libraries/io/ppsh/src/vhdl/mm_ppsh.vhd | 54 +-
libraries/io/ppsh/src/vhdl/mms_ppsh.vhd | 112 +-
libraries/io/ppsh/src/vhdl/ppsh.vhd | 136 +-
libraries/io/ppsh/src/vhdl/ppsh_reg.vhd | 152 +-
libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd | 50 +-
libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd | 42 +-
libraries/io/remu/src/vhdl/mms_remu.vhd | 94 +-
libraries/io/remu/src/vhdl/remu_reg.vhd | 152 +-
libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd | 394 +-
.../src/vhdl/tr_10GbE_ip_checksum.vhd | 96 +-
.../tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd | 154 +-
.../io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd | 34 +-
libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd | 340 +-
.../src/vhdl/mms_tr_nonbonded.vhd | 242 +-
.../io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd | 198 +-
.../src/vhdl/tr_nonbonded_reg.vhd | 62 +-
.../tb/vhdl/tb_tb_tr_nonbonded.vhd | 6 +-
.../tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd | 260 +-
libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd | 232 +-
libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd | 152 +-
.../io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd | 102 +-
.../io/tr_xaui/src/vhdl/tr_xaui_framer.vhd | 96 +-
.../io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd | 152 +-
.../io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd | 10 +-
libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd | 130 +-
.../tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd | 78 +-
.../io/tr_xaui/tb/vhdl/tb_tr_xaui_framer.vhd | 64 +-
.../technology/10gbase_r/sim_10gbase_r.vhd | 92 +-
.../10gbase_r/tb_tech_10gbase_r.vhd | 84 +-
.../technology/10gbase_r/tech_10gbase_r.vhd | 32 +-
.../10gbase_r/tech_10gbase_r_arria10.vhd | 394 +-
.../10gbase_r/tech_10gbase_r_arria10_e1sg.vhd | 494 +-
.../10gbase_r/tech_10gbase_r_arria10_e2sg.vhd | 494 +-
.../tech_10gbase_r_arria10_e3sge3.vhd | 422 +-
.../tech_10gbase_r_component_pkg.vhd | 2996 +++----
libraries/technology/clkbuf/tech_clkbuf.vhd | 40 +-
.../clkbuf/tech_clkbuf_component_pkg.vhd | 34 +-
libraries/technology/ddr/sim_ddr.vhd | 12 +-
libraries/technology/ddr/tech_ddr.vhd | 66 +-
libraries/technology/ddr/tech_ddr_arria10.vhd | 148 +-
.../technology/ddr/tech_ddr_arria10_e1sg.vhd | 284 +-
.../technology/ddr/tech_ddr_arria10_e2sg.vhd | 284 +-
.../ddr/tech_ddr_arria10_e3sge3.vhd | 216 +-
.../technology/ddr/tech_ddr_component_pkg.vhd | 1358 ++--
.../technology/ddr/tech_ddr_mem_model.vhd | 132 +-
.../ddr/tech_ddr_mem_model_component_pkg.vhd | 126 +-
libraries/technology/ddr/tech_ddr_pkg.vhd | 52 +-
.../technology/ddr/tech_ddr_stratixiv.vhd | 516 +-
.../technology/eth_10g/tb_tb_tech_eth_10g.vhd | 30 +-
.../technology/eth_10g/tb_tech_eth_10g.vhd | 382 +-
.../eth_10g/tb_tech_eth_10g_ppm.vhd | 70 +-
libraries/technology/eth_10g/tech_eth_10g.vhd | 420 +-
.../eth_10g/tech_eth_10g_arria10.vhd | 90 +-
.../eth_10g/tech_eth_10g_arria10_e1sg.vhd | 98 +-
.../eth_10g/tech_eth_10g_arria10_e2sg.vhd | 98 +-
.../eth_10g/tech_eth_10g_arria10_e3sge3.vhd | 96 +-
.../eth_10g/tech_eth_10g_clocks.vhd | 6 +-
.../eth_10g/tech_eth_10g_component_pkg.vhd | 416 +-
.../eth_10g/tech_eth_10g_stratixiv.vhd | 102 +-
.../fifo/tech_fifo_component_pkg.vhd | 622 +-
libraries/technology/fifo/tech_fifo_dc.vhd | 32 +-
.../fifo/tech_fifo_dc_mixed_widths.vhd | 32 +-
libraries/technology/fifo/tech_fifo_sc.vhd | 32 +-
.../flash/tech_flash_asmi_parallel.vhd | 20 +-
.../flash/tech_flash_component_pkg.vhd | 334 +-
.../flash/tech_flash_remote_update.vhd | 18 +-
.../fpga_temp_sens/tech_fpga_temp_sens.vhd | 80 +-
.../tech_fpga_temp_sens_component_pkg.vhd | 50 +-
.../tech_fpga_voltage_sens.vhd | 10 +-
.../tech_fpga_voltage_sens_component_pkg.vhd | 122 +-
.../tech_fractional_pll_clk125.vhd | 88 +-
.../tech_fractional_pll_clk200.vhd | 80 +-
.../tech_fractional_pll_component_pkg.vhd | 154 +-
.../iobuf/tech_iobuf_component_pkg.vhd | 226 +-
.../technology/iobuf/tech_iobuf_ddio_in.vhd | 28 +-
.../technology/iobuf/tech_iobuf_ddio_out.vhd | 28 +-
.../ip_arria10_complex_mult_rtl.vhd | 10 +-
.../ip_arria10_complex_mult_rtl_canonical.vhd | 10 +-
.../ip_arria10/ddio/ip_arria10_ddio_in.vhd | 30 +-
.../ip_arria10/ddio/ip_arria10_ddio_out.vhd | 30 +-
.../ddio/sim/ip_arria10_ddio_in_1.vhd | 16 +-
.../ddio/sim/ip_arria10_ddio_out_1.vhd | 16 +-
.../ddio/sim/tb_ip_arria10_ddio_1.vhd | 54 +-
.../ip_arria10/eth_10g/ip_arria10_eth_10g.vhd | 210 +-
.../ip_arria10/fifo/ip_arria10_fifo_dc.vhd | 114 +-
.../fifo/ip_arria10_fifo_dc_mixed_widths.vhd | 126 +-
.../ip_arria10/fifo/ip_arria10_fifo_sc.vhd | 60 +-
.../ip_arria10/mult/ip_arria10_mult.vhd | 60 +-
.../ip_arria10/mult/ip_arria10_mult_rtl.vhd | 14 +-
.../ip_arria10/ram/ip_arria10_ram_cr_cw.vhd | 126 +-
.../ip_arria10/ram/ip_arria10_ram_crw_crw.vhd | 156 +-
.../ram/ip_arria10_ram_crwk_crw.vhd | 126 +-
.../ip_arria10/ram/ip_arria10_ram_r_w.vhd | 124 +-
...rria10_simple_dual_port_ram_dual_clock.vhd | 16 +-
...ia10_simple_dual_port_ram_single_clock.vhd | 18 +-
..._arria10_true_dual_port_ram_dual_clock.vhd | 22 +-
.../tb_ip_arria10_tse_sgmii_gx.vhd | 377 +-
.../tb_ip_arria10_tse_sgmii_lvds.vhd | 351 +-
.../ddio/ip_arria10_e1sg_ddio_in.vhd | 30 +-
.../ddio/ip_arria10_e1sg_ddio_out.vhd | 30 +-
.../ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd | 16 +-
.../ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd | 16 +-
.../ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd | 54 +-
...tera_avalon_onchip_memory2_170_yroldmy.vhd | 112 +-
...tera_avalon_onchip_memory2_180_xymx6za.vhd | 112 +-
...g_2400_altera_emif_arch_nf_180_e37lt4i.vhd | 7182 ++++++++---------
.../ip_arria10_e1sg_ddr4_8g_2400_inst.vhd | 2 +-
.../eth_10g/ip_arria10_e1sg_eth_10g.vhd | 214 +-
.../fifo/ip_arria10_e1sg_fifo_dc.vhd | 114 +-
.../ip_arria10_e1sg_fifo_dc_mixed_widths.vhd | 126 +-
.../fifo/ip_arria10_e1sg_fifo_sc.vhd | 60 +-
.../jesd204b/ip_arria10_e1sg_jesd204b.vhd | 272 +-
...ip_arria10_e1sg_jesd204b_component_pkg.vhd | 14 +-
.../ip_arria10_e1sg_mult_add2_rtl.vhd | 6 +-
.../ip_arria10_e1sg_mult_add4_rtl.vhd | 6 +-
.../ram/ip_arria10_e1sg_ram_cr_cw.vhd | 126 +-
.../ram/ip_arria10_e1sg_ram_crw_crw.vhd | 156 +-
.../ram/ip_arria10_e1sg_ram_crwk_crw.vhd | 126 +-
.../ip_arria10_e1sg_ram_crwk_crw_inst.vhd | 2 +-
...1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd | 122 +-
.../ram/ip_arria10_e1sg_ram_r_w.vhd | 124 +-
...0_e1sg_simple_dual_port_ram_dual_clock.vhd | 16 +-
...e1sg_simple_dual_port_ram_single_clock.vhd | 18 +-
...a10_e1sg_true_dual_port_ram_dual_clock.vhd | 22 +-
...sg_transceiver_reset_controller_3_inst.vhd | 2 +-
.../tb_ip_arria10_e1sg_tse_sgmii_gx.vhd | 377 +-
.../tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd | 351 +-
.../ddio/ip_arria10_e2sg_ddio_in.vhd | 30 +-
.../ddio/ip_arria10_e2sg_ddio_out.vhd | 30 +-
.../ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd | 16 +-
.../ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd | 16 +-
.../ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd | 54 +-
.../ip_arria10_e2sg_ddr4_8g_1600_inst.vhd | 2 +-
.../eth_10g/ip_arria10_e2sg_eth_10g.vhd | 214 +-
.../fifo/ip_arria10_e2sg_fifo_dc.vhd | 114 +-
.../ip_arria10_e2sg_fifo_dc_mixed_widths.vhd | 126 +-
.../fifo/ip_arria10_e2sg_fifo_sc.vhd | 60 +-
.../jesd204b/ip_arria10_e2sg_jesd204b.vhd | 272 +-
...ip_arria10_e2sg_jesd204b_component_pkg.vhd | 14 +-
.../ip_arria10_e2sg_mult_add2_rtl.vhd | 6 +-
.../ip_arria10_e2sg_mult_add4_rtl.vhd | 6 +-
.../ram/ip_arria10_e2sg_ram_cr_cw.vhd | 130 +-
.../ram/ip_arria10_e2sg_ram_crw_crw.vhd | 160 +-
.../ip_arria10_e2sg_ram_crw_crw_inst.vhd | 2 +-
...2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd | 112 +-
.../ram/ip_arria10_e2sg_ram_crwk_crw.vhd | 126 +-
.../ram/ip_arria10_e2sg_ram_r_w.vhd | 124 +-
...0_e2sg_simple_dual_port_ram_dual_clock.vhd | 16 +-
...e2sg_simple_dual_port_ram_single_clock.vhd | 18 +-
...a10_e2sg_true_dual_port_ram_dual_clock.vhd | 22 +-
.../tb_ip_arria10_e2sg_tse_sgmii_gx.vhd | 377 +-
.../tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd | 351 +-
.../ddio/ip_arria10_e3sge3_ddio_in.vhd | 30 +-
.../ddio/ip_arria10_e3sge3_ddio_out.vhd | 30 +-
.../ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd | 16 +-
.../ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd | 16 +-
.../ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd | 54 +-
.../eth_10g/ip_arria10_e3sge3_eth_10g.vhd | 214 +-
.../fifo/ip_arria10_e3sge3_fifo_dc.vhd | 114 +-
...ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd | 126 +-
.../fifo/ip_arria10_e3sge3_fifo_sc.vhd | 60 +-
.../ip_arria10_e3sge3_mult_add4_rtl.vhd | 6 +-
.../ram/ip_arria10_e3sge3_ram_cr_cw.vhd | 126 +-
.../ram/ip_arria10_e3sge3_ram_crw_crw.vhd | 156 +-
.../ram/ip_arria10_e3sge3_ram_crwk_crw.vhd | 126 +-
.../ram/ip_arria10_e3sge3_ram_r_w.vhd | 124 +-
...e3sge3_simple_dual_port_ram_dual_clock.vhd | 16 +-
...sge3_simple_dual_port_ram_single_clock.vhd | 18 +-
...0_e3sge3_true_dual_port_ram_dual_clock.vhd | 22 +-
.../tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd | 377 +-
.../tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd | 351 +-
.../ddio/ip_stratixiv_ddio_in.vhd | 36 +-
.../ddio/ip_stratixiv_ddio_out.vhd | 42 +-
.../eth_10g/ip_stratixiv_eth_10g.vhd | 150 +-
.../mult/ip_stratixiv_complex_mult_rtl.vhd | 10 +-
.../ip_stratixiv/mult/ip_stratixiv_mult.vhd | 48 +-
.../mult/ip_stratixiv_mult_add2_rtl.vhd | 6 +-
.../mult/ip_stratixiv_mult_add4_rtl.vhd | 6 +-
.../mult/ip_stratixiv_mult_rtl.vhd | 14 +-
.../phy_xaui/tb_ip_stratixiv_phy_xaui.vhd | 54 +-
.../phy_xaui/tb_ip_stratixiv_phy_xaui_ppm.vhd | 46 +-
.../ip_stratixiv_gxb_reconfig_v101.vhd | 40 +-
.../ip_stratixiv_gxb_reconfig_v111.vhd | 28 +-
.../ip_stratixiv_gxb_reconfig_v91.vhd | 50 +-
.../tb_ip_stratixiv_tse_sgmii_lvds.vhd | 343 +-
.../fifo/ip_ultrascale_fifo_dc.vhd | 102 +-
.../ip_ultrascale_fifo_dc_mixed_widths.vhd | 102 +-
.../fifo/ip_ultrascale_fifo_sc.vhd | 100 +-
.../ram/ip_ultrascale_ram_cr_cw.vhd | 64 +-
.../ram/ip_ultrascale_ram_crw_crw.vhd | 92 +-
.../technology/jesd204b/tb_tech_jesd204b.vhd | 328 +-
.../technology/jesd204b/tech_jesd204b.vhd | 134 +-
.../jesd204b/tech_jesd204b_arria10_e1sg.vhd | 72 +-
.../jesd204b/tech_jesd204b_arria10_e2sg.vhd | 72 +-
.../jesd204b/tech_jesd204b_component_pkg.vhd | 334 +-
.../technology/jesd204b/tech_jesd204b_pkg.vhd | 2 +-
.../technology/jesd204b/tech_jesd204b_tx.vhd | 204 +-
.../technology/mac_10g/tb_tb_tech_mac_10g.vhd | 18 +-
.../technology/mac_10g/tb_tech_mac_10g.vhd | 240 +-
.../mac_10g/tb_tech_mac_10g_link_connect.vhd | 6 +-
.../mac_10g/tb_tech_mac_10g_pkg.vhd | 242 +-
.../mac_10g/tb_tech_mac_10g_receiver.vhd | 12 +-
.../mac_10g/tb_tech_mac_10g_setup.vhd | 18 +-
.../tb_tech_mac_10g_simulation_end.vhd | 6 +-
.../mac_10g/tb_tech_mac_10g_transmitter.vhd | 16 +-
.../tb_tech_mac_10g_verify_rx_at_eop.vhd | 12 +-
.../tb_tech_mac_10g_verify_rx_pkt_cnt.vhd | 4 +-
libraries/technology/mac_10g/tech_mac_10g.vhd | 154 +-
.../mac_10g/tech_mac_10g_arria10.vhd | 120 +-
.../mac_10g/tech_mac_10g_arria10_e1sg.vhd | 120 +-
.../mac_10g/tech_mac_10g_arria10_e2sg.vhd | 120 +-
.../mac_10g/tech_mac_10g_arria10_e3sge3.vhd | 120 +-
.../mac_10g/tech_mac_10g_component_pkg.vhd | 424 +-
.../mac_10g/tech_mac_10g_stratixiv.vhd | 110 +-
.../memory/tech_memory_component_pkg.vhd | 864 +-
.../memory/tech_memory_ram_cr_cw.vhd | 32 +-
.../memory/tech_memory_ram_crw_crw.vhd | 32 +-
.../memory/tech_memory_ram_crwk_crw.vhd | 28 +-
.../technology/memory/tech_memory_ram_r_w.vhd | 28 +-
.../technology/memory/tech_memory_rom_r.vhd | 84 +-
.../technology/mult/tech_complex_mult.vhd | 266 +-
libraries/technology/mult/tech_mult.vhd | 154 +-
libraries/technology/mult/tech_mult_add2.vhd | 130 +-
libraries/technology/mult/tech_mult_add4.vhd | 186 +-
.../mult/tech_mult_component_pkg.vhd | 696 +-
libraries/technology/mult/tech_mult_pkg.vhd | 4 +-
libraries/technology/pll/tech_pll_clk125.vhd | 80 +-
libraries/technology/pll/tech_pll_clk200.vhd | 76 +-
.../technology/pll/tech_pll_clk200_p6.vhd | 16 +-
libraries/technology/pll/tech_pll_clk25.vhd | 100 +-
.../technology/pll/tech_pll_component_pkg.vhd | 418 +-
.../pll/tech_pll_xgmii_mac_clocks.vhd | 110 +-
libraries/technology/technology_pkg.vhd | 42 +-
.../technology/technology_select_pkg.vhd | 4 +-
.../technology/technology_select_pkg_unb1.vhd | 4 +-
.../technology_select_pkg_unb2b.vhd | 4 +-
.../technology_select_pkg_unb2c.vhd | 4 +-
.../sim_transceiver_deserializer.vhd | 4 +-
.../transceiver/sim_transceiver_gx.vhd | 92 +-
.../sim_transceiver_serializer.vhd | 4 +-
.../transceiver/tb_sim_transceiver_serdes.vhd | 60 +-
.../tech_transceiver_arria10_1.vhd | 40 +-
.../tech_transceiver_arria10_48.vhd | 42 +-
.../tech_transceiver_component_pkg.vhd | 302 +-
.../transceiver/tech_transceiver_gx.vhd | 16 +-
.../tech_transceiver_gx_stratixiv.vhd | 530 +-
.../transceiver/tech_transceiver_rx_align.vhd | 30 +-
.../transceiver/tech_transceiver_rx_order.vhd | 4 +-
.../transceiver/tech_transceiver_rx_rst.vhd | 28 +-
.../transceiver/tech_transceiver_tx_align.vhd | 12 +-
.../transceiver/tech_transceiver_tx_rst.vhd | 28 +-
libraries/technology/tse/sim_tse.vhd | 164 +-
libraries/technology/tse/tb_tb_tech_tse.vhd | 22 +-
libraries/technology/tse/tb_tech_tse.vhd | 100 +-
libraries/technology/tse/tb_tech_tse_pkg.vhd | 276 +-
.../technology/tse/tb_tech_tse_with_setup.vhd | 104 +-
libraries/technology/tse/tech_tse.vhd | 114 +-
libraries/technology/tse/tech_tse_arria10.vhd | 284 +-
.../technology/tse/tech_tse_arria10_e1sg.vhd | 284 +-
.../technology/tse/tech_tse_arria10_e2sg.vhd | 284 +-
.../tse/tech_tse_arria10_e3sge3.vhd | 284 +-
.../technology/tse/tech_tse_component_pkg.vhd | 1044 +--
libraries/technology/tse/tech_tse_pkg.vhd | 14 +-
libraries/technology/tse/tech_tse_setup.vhd | 18 +-
.../technology/tse/tech_tse_stratixiv.vhd | 286 +-
.../technology/tse/tech_tse_with_setup.vhd | 144 +-
libraries/technology/xaui/sim_xaui.vhd | 110 +-
libraries/technology/xaui/tech_xaui.vhd | 20 +-
.../technology/xaui/tech_xaui_align_dly.vhd | 30 +-
.../xaui/tech_xaui_component_pkg.vhd | 380 +-
.../technology/xaui/tech_xaui_stratixiv.vhd | 372 +-
2038 files changed, 143701 insertions(+), 134265 deletions(-)
diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
index 38d1546d52..3bc1172d1d 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
@@ -30,11 +30,11 @@
-- that occurs due to shared complex FFT and seperate in PFT_MODE_REAL2.
library IEEE, common_lib, dp_lib, pfs_lib, pft2_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use pfs_lib.pfs_pkg.all;
-use pft2_lib.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use pfs_lib.pfs_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pfb2 is
generic (
@@ -91,27 +91,27 @@ begin
gen_pfs : if g_pfs_bypass = false generate
u_pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => g_nof_points,
- g_nof_taps => c_nof_coeffs,
- g_in_dat_w => g_pfs_in_dat_w,
- g_out_dat_w => g_pfs_out_dat_w,
- g_coef_dat_w => g_pfs_coef_dat_w,
- g_coefs_file => g_pfs_coefs_file
- )
- port map (
- in_dat_x => pfs_in_dat_x,
- in_dat_y => pfs_in_dat_y,
- in_val => pfs_in_val,
- in_sync => pfs_in_sync,
- out_dat_x => fil_out_dat_x,
- out_dat_y => fil_out_dat_y,
- out_val => fil_out_val,
- out_sync => fil_out_sync,
- clk => dp_clk,
- rst => dp_rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => g_nof_points,
+ g_nof_taps => c_nof_coeffs,
+ g_in_dat_w => g_pfs_in_dat_w,
+ g_out_dat_w => g_pfs_out_dat_w,
+ g_coef_dat_w => g_pfs_coef_dat_w,
+ g_coefs_file => g_pfs_coefs_file
+ )
+ port map (
+ in_dat_x => pfs_in_dat_x,
+ in_dat_y => pfs_in_dat_y,
+ in_val => pfs_in_val,
+ in_sync => pfs_in_sync,
+ out_dat_x => fil_out_dat_x,
+ out_dat_y => fil_out_dat_y,
+ out_val => fil_out_val,
+ out_sync => fil_out_sync,
+ clk => dp_clk,
+ rst => dp_rst,
+ restart => '0'
+ );
end generate;
no_pfs : if g_pfs_bypass = true generate
@@ -127,26 +127,26 @@ begin
fil_sosi.sync <= fil_out_sync;
u_pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => ceil_log2(g_nof_points),
- g_in_dat_w => g_pfs_out_dat_w,
- g_out_dat_w => g_pft_out_dat_w,
- g_stage_dat_w => g_pft_stage_dat_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => fil_out_dat_x,
- in_im => fil_out_dat_y,
- in_val => fil_out_val,
- in_sync => fil_out_sync,
- switch_en => g_pft_switch_en,
- out_re => pft_out_dat_re,
- out_im => pft_out_dat_im,
- out_val => pft_out_val,
- out_sync => pft_out_sync,
- clk => dp_clk,
- rst => dp_rst
- );
+ generic map (
+ g_fft_size_w => ceil_log2(g_nof_points),
+ g_in_dat_w => g_pfs_out_dat_w,
+ g_out_dat_w => g_pft_out_dat_w,
+ g_stage_dat_w => g_pft_stage_dat_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => fil_out_dat_x,
+ in_im => fil_out_dat_y,
+ in_val => fil_out_val,
+ in_sync => fil_out_sync,
+ switch_en => g_pft_switch_en,
+ out_re => pft_out_dat_re,
+ out_im => pft_out_dat_im,
+ out_val => pft_out_val,
+ out_sync => pft_out_sync,
+ clk => dp_clk,
+ rst => dp_rst
+ );
-- Delay pft sync with respect pft data to fit DP sync timing
out_sosi.re <= RESIZE_DP_DSP_DATA(pft_out_dat_re);
diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
index 776304c928..6402e68bd7 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
@@ -29,12 +29,12 @@
-- Remark:
library IEEE, common_lib, dp_lib, pfs_lib, pft2_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use pfs_lib.pfs_pkg.all;
-use pft2_lib.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use pfs_lib.pfs_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pfb2_unit is
generic (
@@ -88,30 +88,30 @@ begin
---------------------------------------------------------------
gen_pfb2: for I in 0 to g_nof_streams - 1 generate
u_pfb2 : entity work.pfb2
- generic map (
- g_nof_points => g_nof_points,
-
- -- pfs
- g_pfs_bypass => g_pfs_bypass,
- g_pfs_nof_taps => g_pfs_nof_taps,
- g_pfs_in_dat_w => g_pfs_in_dat_w,
- g_pfs_out_dat_w => g_pfs_out_dat_w,
- g_pfs_coef_dat_w => g_pfs_coef_dat_w,
- g_pfs_coefs_file => g_pfs_coefs_file,
-
- -- pft2
- g_pft_mode => g_pft_mode,
- g_pft_switch_en => g_pft_switch_en,
- g_pft_stage_dat_w => g_pft_stage_dat_w,
- g_pft_out_dat_w => g_pft_out_dat_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_sosi => in_sosi_arr(I),
- fil_sosi => fil_sosi_arr(I),
- out_sosi => pft_sosi_arr(I)
- );
+ generic map (
+ g_nof_points => g_nof_points,
+
+ -- pfs
+ g_pfs_bypass => g_pfs_bypass,
+ g_pfs_nof_taps => g_pfs_nof_taps,
+ g_pfs_in_dat_w => g_pfs_in_dat_w,
+ g_pfs_out_dat_w => g_pfs_out_dat_w,
+ g_pfs_coef_dat_w => g_pfs_coef_dat_w,
+ g_pfs_coefs_file => g_pfs_coefs_file,
+
+ -- pft2
+ g_pft_mode => g_pft_mode,
+ g_pft_switch_en => g_pft_switch_en,
+ g_pft_stage_dat_w => g_pft_stage_dat_w,
+ g_pft_out_dat_w => g_pft_out_dat_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi => in_sosi_arr(I),
+ fil_sosi => fil_sosi_arr(I),
+ out_sosi => pft_sosi_arr(I)
+ );
end generate;
---------------------------------------------------------------
@@ -119,34 +119,34 @@ begin
---------------------------------------------------------------
-- MM mux for SST
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(g_sst_data_sz * c_nof_stats)
- )
- port map (
- mosi => ram_st_sst_mosi,
- miso => ram_st_sst_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
-
- gen_sst: for I in 0 to g_nof_streams - 1 generate
- u_sst : entity st_lib.st_sst
generic map (
- g_nof_stat => c_nof_stats,
- g_in_data_w => g_pft_out_dat_w,
- g_stat_data_w => g_sst_data_w,
- g_stat_data_sz => g_sst_data_sz
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(g_sst_data_sz * c_nof_stats)
)
port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_complex => pft_sosi_arr(I),
- ram_st_sst_mosi => ram_st_sst_mosi_arr(I),
- ram_st_sst_miso => ram_st_sst_miso_arr(I)
+ mosi => ram_st_sst_mosi,
+ miso => ram_st_sst_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
);
+
+ gen_sst: for I in 0 to g_nof_streams - 1 generate
+ u_sst : entity st_lib.st_sst
+ generic map (
+ g_nof_stat => c_nof_stats,
+ g_in_data_w => g_pft_out_dat_w,
+ g_stat_data_w => g_sst_data_w,
+ g_stat_data_sz => g_sst_data_sz
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_complex => pft_sosi_arr(I),
+ ram_st_sst_mosi => ram_st_sst_mosi_arr(I),
+ ram_st_sst_miso => ram_st_sst_miso_arr(I)
+ );
end generate;
out_sosi_arr <= pft_sosi_arr;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
index 30b483a481..c831d67522 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
@@ -1,7 +1,7 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
library common_lib;
-use common_lib.common_pkg.all;
+ use common_lib.common_pkg.all;
architecture str of pfs is
@@ -21,108 +21,108 @@ architecture str of pfs is
begin
ctrl : entity pfs_lib.pfs_ctrl
- generic map (
- g_nof_bands_w => c_nof_bands_w,
- g_nof_taps => c_nof_fir_taps,
- g_nof_taps_w => c_nof_fir_taps_w,
- g_taps_w => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- restart => restart,
- in_x => in_dat_x,
- in_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- taps_rdaddr => taps_rdaddr,
- taps_wraddr => taps_wraddr,
- taps_wren => taps_wren,
- taps_in_x => taps_in_x,
- taps_in_y => taps_in_y,
- taps_out_x => taps_out_x,
- taps_out_y => taps_out_y,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_bands_w => c_nof_bands_w,
+ g_nof_taps => c_nof_fir_taps,
+ g_nof_taps_w => c_nof_fir_taps_w,
+ g_taps_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ restart => restart,
+ in_x => in_dat_x,
+ in_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ taps_rdaddr => taps_rdaddr,
+ taps_wraddr => taps_wraddr,
+ taps_wren => taps_wren,
+ taps_in_x => taps_in_x,
+ taps_in_y => taps_in_y,
+ taps_out_x => taps_out_x,
+ taps_out_y => taps_out_y,
+ out_val => out_val,
+ out_sync => out_sync
+ );
firx : entity pfs_lib.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map(
- clk => clk,
- taps => taps_out_x,
- coefs => coefs,
- result => out_dat_x
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map(
+ clk => clk,
+ taps => taps_out_x,
+ coefs => coefs,
+ result => out_dat_x
+ );
firy : entity pfs_lib.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map (
- clk => clk,
- taps => taps_out_y,
- coefs => coefs,
- result => out_dat_y
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map (
+ clk => clk,
+ taps => taps_out_y,
+ coefs => coefs,
+ result => out_dat_y
+ );
tapsbufx : entity pfs_lib.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_x,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_x,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_x,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_x,
+ clk => clk,
+ rst => rst
+ );
tapsbufy : entity pfs_lib.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_y,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_y,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_y,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_y,
+ clk => clk,
+ rst => rst
+ );
coefsbuf : entity pfs_lib.pfs_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w * c_nof_fir_taps,
- g_nof_coefs => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- addr => taps_rdaddr,
- data => coefs,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_coef_dat_w * c_nof_fir_taps,
+ g_nof_coefs => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ addr => taps_rdaddr,
+ data => coefs,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
index 3a59bc5033..ce092e6949 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.pfs_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.pfs_pkg.all;
entity pfs is
generic (
@@ -71,109 +71,109 @@ architecture str of pfs is
begin
ctrl : entity work.pfs_ctrl
- generic map (
- g_nof_bands_w => c_nof_bands_w,
- g_nof_taps => c_nof_fir_taps,
- g_nof_taps_w => c_nof_fir_taps_w,
- g_taps_w => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- restart => restart,
- in_x => in_dat_x,
- in_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- taps_rdaddr => taps_rdaddr,
- taps_wraddr => taps_wraddr,
- taps_wren => taps_wren,
- taps_in_x => taps_in_x,
- taps_in_y => taps_in_y,
- taps_out_x => taps_out_x,
- taps_out_y => taps_out_y,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_bands_w => c_nof_bands_w,
+ g_nof_taps => c_nof_fir_taps,
+ g_nof_taps_w => c_nof_fir_taps_w,
+ g_taps_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ restart => restart,
+ in_x => in_dat_x,
+ in_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ taps_rdaddr => taps_rdaddr,
+ taps_wraddr => taps_wraddr,
+ taps_wren => taps_wren,
+ taps_in_x => taps_in_x,
+ taps_in_y => taps_in_y,
+ taps_out_x => taps_out_x,
+ taps_out_y => taps_out_y,
+ out_val => out_val,
+ out_sync => out_sync
+ );
firx : entity work.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map(
- clk => clk,
- taps => taps_out_x,
- coefs => coefs,
- result => out_dat_x
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map(
+ clk => clk,
+ taps => taps_out_x,
+ coefs => coefs,
+ result => out_dat_x
+ );
firy : entity work.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map (
- clk => clk,
- taps => taps_out_y,
- coefs => coefs,
- result => out_dat_y
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map (
+ clk => clk,
+ taps => taps_out_y,
+ coefs => coefs,
+ result => out_dat_y
+ );
tapsbufx : entity work.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_x,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_x,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_x,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_x,
+ clk => clk,
+ rst => rst
+ );
tapsbufy : entity work.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_y,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_y,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_y,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_y,
+ clk => clk,
+ rst => rst
+ );
coefsbuf : entity work.pfs_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w * c_nof_fir_taps,
- g_coefs_file => g_coefs_file,
- g_nof_coefs => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- addr => taps_rdaddr,
- data => coefs,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_coef_dat_w * c_nof_fir_taps,
+ g_coefs_file => g_coefs_file,
+ g_nof_coefs => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ addr => taps_rdaddr,
+ data => coefs,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
index 461af4d42a..e77f4b6cf4 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
@@ -1,31 +1,33 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_mem_pkg.all;
architecture str of pfs_coefsbuf is
- constant c_coefs_rom : t_c_mem := (latency => 2,
- adr_w => g_addr_w,
- dat_w => g_data_w,
- nof_dat => g_nof_coefs, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_coefs_rom : t_c_mem := (
+ latency => 2,
+ adr_w => g_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ init_sl => '0'
+ );
begin
rom : entity common_lib.common_rom
- generic map (
- g_ram => c_coefs_rom,
- g_init_file => "data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ generic map (
+ g_ram => c_coefs_rom,
+ g_init_file => "data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
--g_init_file => "data/pfs_coefsbuf_1024.bin" -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => addr,
- rd_dat => data
- );
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => addr,
+ rd_dat => data
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
index 9d7c70a8a7..1f22cb809b 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
@@ -1,57 +1,57 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_coefsbuf is
component altsyncram
- generic (
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_a : string;
- outdata_aclr_a : string;
- read_during_write_mode_mixed_ports : string;
- ram_block_type : string;
- init_file : string;
- intended_device_family : string
- );
- port (
- aclr0 : in std_logic ;
- clock0 : in std_logic ;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- q_a : out std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_a : string;
+ outdata_aclr_a : string;
+ read_during_write_mode_mixed_ports : string;
+ ram_block_type : string;
+ init_file : string;
+ intended_device_family : string
+ );
+ port (
+ aclr0 : in std_logic ;
+ clock0 : in std_logic ;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_a : out std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
rom : altsyncram
- generic map (
- operation_mode => "ROM",
- width_a => g_data_w,
- widthad_a => g_addr_w,
- numwords_a => g_nof_coefs,
- lpm_type => "altsyncram",
- width_byteena_a => 1,
- outdata_reg_a => "CLOCK0",
- outdata_aclr_a => "CLEAR0",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- ram_block_type => "AUTO",
- init_file => "../../../../pfs/src/data/pfs_coefsbuf_1024.hex",
- intended_device_family => c_rsp_device_family
- )
- port map (
- aclr0 => rst,
- clock0 => clk,
- address_a => addr,
- q_a => data
- );
+ generic map (
+ operation_mode => "ROM",
+ width_a => g_data_w,
+ widthad_a => g_addr_w,
+ numwords_a => g_nof_coefs,
+ lpm_type => "altsyncram",
+ width_byteena_a => 1,
+ outdata_reg_a => "CLOCK0",
+ outdata_aclr_a => "CLEAR0",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ ram_block_type => "AUTO",
+ init_file => "../../../../pfs/src/data/pfs_coefsbuf_1024.hex",
+ intended_device_family => c_rsp_device_family
+ )
+ port map (
+ aclr0 => rst,
+ clock0 => clk,
+ address_a => addr,
+ q_a => data
+ );
end stratix;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
index f68e6c99e3..3d3e172e20 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_mem_pkg.all;
entity pfs_coefsbuf is
@@ -48,24 +48,26 @@ end pfs_coefsbuf;
architecture str of pfs_coefsbuf is
- constant c_coefs_rom : t_c_mem := (latency => 2,
- adr_w => g_addr_w,
- dat_w => g_data_w,
- nof_dat => g_nof_coefs, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_coefs_rom : t_c_mem := (
+ latency => 2,
+ adr_w => g_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ init_sl => '0'
+ );
begin
rom : entity common_lib.common_rom
- generic map (
- g_ram => c_coefs_rom,
- g_init_file => g_coefs_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => addr,
- rd_dat => data
- );
+ generic map (
+ g_ram => c_coefs_rom,
+ g_init_file => g_coefs_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => addr,
+ rd_dat => data
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
index 2f4d1cce6b..b079e3dcb5 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_combine is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
index 58d73db25d..c81bef3ffd 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
@@ -1,5 +1,5 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pfs_combine is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
index 111e9267bf..10a8e3ca01 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_ctrl is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
index 703f337882..56d5a542e6 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_ctrl is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
index 2b024f2256..11e412873a 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
@@ -1,7 +1,7 @@
library IEEE, common_lib, common_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture rtl of pfs_filter is
@@ -30,27 +30,27 @@ begin
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
gen : for i in 0 to 7 generate
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
--MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
MULT_ADD : entity common_mult_lib.common_mult_add -- rtl
- generic map (
- g_in_a_w => g_taps_w,
- g_in_b_w => g_coef_w,
- g_out_dat_w => g_coef_w + g_taps_w + 1,
- g_add_sub => "ADD",
- g_pipeline => 3
- )
- port map (
- clk => clk,
- in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
- in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
- in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
- in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
- out_dat => res(i)
- );
+ generic map (
+ g_in_a_w => g_taps_w,
+ g_in_b_w => g_coef_w,
+ g_out_dat_w => g_coef_w + g_taps_w + 1,
+ g_add_sub => "ADD",
+ g_pipeline => 3
+ )
+ port map (
+ clk => clk,
+ in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
+ in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
+ in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
+ in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
+ out_dat => res(i)
+ );
end generate;
pipe : process (clk)
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
index 9cde479324..f73c25654d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
@@ -1,82 +1,82 @@
library IEEE, lpm, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_filter is
component altmult_add
- generic (
- input_register_b2 : string := "CLOCK0" ;
- input_register_a1 : string := "CLOCK0" ;
- multiplier_register0 : string := "CLOCK0" ;
- signed_pipeline_aclr_b : string := "ACLR3" ;
- input_register_b3 : string := "CLOCK0" ;
- input_register_a2 : string := "CLOCK0" ;
- multiplier_register1 : string := "CLOCK0" ;
- addnsub_multiplier_pipeline_aclr1 : string := "ACLR3" ;
- input_register_a3 : string := "CLOCK0" ;
- multiplier_register2 : string := "CLOCK0" ;
- signed_aclr_a : string := "ACLR3" ;
- signed_register_a : string := "CLOCK0" ;
- number_of_multipliers : natural := 4 ;
- multiplier_register3 : string := "CLOCK0" ;
- multiplier_aclr0 : string := "ACLR3" ;
- addnsub_multiplier_pipeline_aclr3 : string := "ACLR3" ;
- signed_aclr_b : string := "ACLR3" ;
- signed_register_b : string := "CLOCK0" ;
- lpm_type : string := "altmult_add";
- multiplier_aclr1 : string := "ACLR3" ;
- input_aclr_b0 : string := "ACLR3" ;
- output_register : string := "CLOCK0" ;
- width_result : natural := g_taps_w + g_coef_w + 2;
- representation_a : string := "SIGNED" ;
- signed_pipeline_register_a : string := "CLOCK0" ;
- input_source_b0 : string := "DATAB" ;
- multiplier_aclr2 : string := "ACLR3" ;
- input_aclr_b1 : string := "ACLR3" ;
- input_aclr_a0 : string := "ACLR3" ;
- multiplier3_direction : string := "ADD" ;
- addnsub_multiplier_register1 : string := "CLOCK0" ;
- representation_b : string := "SIGNED" ;
- signed_pipeline_register_b : string := "CLOCK0" ;
- input_source_b1 : string := "DATAB" ;
- input_source_a0 : string := "DATAA" ;
- multiplier_aclr3 : string := "ACLR3" ;
- input_aclr_b2 : string := "ACLR3" ;
- input_aclr_a1 : string := "ACLR3" ;
- dedicated_multiplier_circuitry : string := "YES" ;
- input_source_b2 : string := "DATAB" ;
- input_source_a1 : string := "DATAA" ;
- input_aclr_b3 : string := "ACLR3" ;
- input_aclr_a2 : string := "ACLR3" ;
- addnsub_multiplier_register3 : string := "CLOCK0" ;
- addnsub_multiplier_aclr1 : string := "ACLR3" ;
- output_aclr : string := "ACLR3" ;
- input_source_b3 : string := "DATAB" ;
- input_source_a2 : string := "DATAA" ;
- input_aclr_a3 : string := "ACLR3" ;
- input_source_a3 : string := "DATAA" ;
- addnsub_multiplier_aclr3 : string := "ACLR3" ;
- intended_device_family : string := "Stratix II" ;
- addnsub_multiplier_pipeline_register1 : string := "CLOCK0" ;
- width_a : natural := g_taps_w ;
- input_register_b0 : string := "CLOCK0" ;
- width_b : natural := g_coef_w ;
- input_register_b1 : string := "CLOCK0" ;
- input_register_a0 : string := "CLOCK0" ;
- addnsub_multiplier_pipeline_register3 : string := "CLOCK0" ;
- multiplier1_direction : string := "ADD" ;
- signed_pipeline_aclr_a : string := "ACLR3"
- );
- port (
- dataa : in std_logic_vector(g_taps_w * 4 - 1 downto 0);
- datab : in std_logic_vector(g_coef_w * 4 - 1 downto 0);
- clock0 : in std_logic ;
- aclr3 : in std_logic ;
- result : out std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0)
- );
+ generic (
+ input_register_b2 : string := "CLOCK0" ;
+ input_register_a1 : string := "CLOCK0" ;
+ multiplier_register0 : string := "CLOCK0" ;
+ signed_pipeline_aclr_b : string := "ACLR3" ;
+ input_register_b3 : string := "CLOCK0" ;
+ input_register_a2 : string := "CLOCK0" ;
+ multiplier_register1 : string := "CLOCK0" ;
+ addnsub_multiplier_pipeline_aclr1 : string := "ACLR3" ;
+ input_register_a3 : string := "CLOCK0" ;
+ multiplier_register2 : string := "CLOCK0" ;
+ signed_aclr_a : string := "ACLR3" ;
+ signed_register_a : string := "CLOCK0" ;
+ number_of_multipliers : natural := 4 ;
+ multiplier_register3 : string := "CLOCK0" ;
+ multiplier_aclr0 : string := "ACLR3" ;
+ addnsub_multiplier_pipeline_aclr3 : string := "ACLR3" ;
+ signed_aclr_b : string := "ACLR3" ;
+ signed_register_b : string := "CLOCK0" ;
+ lpm_type : string := "altmult_add";
+ multiplier_aclr1 : string := "ACLR3" ;
+ input_aclr_b0 : string := "ACLR3" ;
+ output_register : string := "CLOCK0" ;
+ width_result : natural := g_taps_w + g_coef_w + 2;
+ representation_a : string := "SIGNED" ;
+ signed_pipeline_register_a : string := "CLOCK0" ;
+ input_source_b0 : string := "DATAB" ;
+ multiplier_aclr2 : string := "ACLR3" ;
+ input_aclr_b1 : string := "ACLR3" ;
+ input_aclr_a0 : string := "ACLR3" ;
+ multiplier3_direction : string := "ADD" ;
+ addnsub_multiplier_register1 : string := "CLOCK0" ;
+ representation_b : string := "SIGNED" ;
+ signed_pipeline_register_b : string := "CLOCK0" ;
+ input_source_b1 : string := "DATAB" ;
+ input_source_a0 : string := "DATAA" ;
+ multiplier_aclr3 : string := "ACLR3" ;
+ input_aclr_b2 : string := "ACLR3" ;
+ input_aclr_a1 : string := "ACLR3" ;
+ dedicated_multiplier_circuitry : string := "YES" ;
+ input_source_b2 : string := "DATAB" ;
+ input_source_a1 : string := "DATAA" ;
+ input_aclr_b3 : string := "ACLR3" ;
+ input_aclr_a2 : string := "ACLR3" ;
+ addnsub_multiplier_register3 : string := "CLOCK0" ;
+ addnsub_multiplier_aclr1 : string := "ACLR3" ;
+ output_aclr : string := "ACLR3" ;
+ input_source_b3 : string := "DATAB" ;
+ input_source_a2 : string := "DATAA" ;
+ input_aclr_a3 : string := "ACLR3" ;
+ input_source_a3 : string := "DATAA" ;
+ addnsub_multiplier_aclr3 : string := "ACLR3" ;
+ intended_device_family : string := "Stratix II" ;
+ addnsub_multiplier_pipeline_register1 : string := "CLOCK0" ;
+ width_a : natural := g_taps_w ;
+ input_register_b0 : string := "CLOCK0" ;
+ width_b : natural := g_coef_w ;
+ input_register_b1 : string := "CLOCK0" ;
+ input_register_a0 : string := "CLOCK0" ;
+ addnsub_multiplier_pipeline_register3 : string := "CLOCK0" ;
+ multiplier1_direction : string := "ADD" ;
+ signed_pipeline_aclr_a : string := "ACLR3"
+ );
+ port (
+ dataa : in std_logic_vector(g_taps_w * 4 - 1 downto 0);
+ datab : in std_logic_vector(g_coef_w * 4 - 1 downto 0);
+ clock0 : in std_logic ;
+ aclr3 : in std_logic ;
+ result : out std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0)
+ );
end component;
@@ -105,46 +105,46 @@ begin
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
ALTMULT_ADD_0 : altmult_add
- port map (
- dataa => taps(47 downto 0),
- datab => coefs(63 downto 0),
- clock0 => clk,
- aclr3 => rst,
- result => res_0
- );
+ port map (
+ dataa => taps(47 downto 0),
+ datab => coefs(63 downto 0),
+ clock0 => clk,
+ aclr3 => rst,
+ result => res_0
+ );
ALTMULT_ADD_1 : altmult_add
- port map (
- dataa => taps(95 downto 48),
- datab => coefs(127 downto 64),
- clock0 => clk,
- aclr3 => rst,
- result => res_1
- );
+ port map (
+ dataa => taps(95 downto 48),
+ datab => coefs(127 downto 64),
+ clock0 => clk,
+ aclr3 => rst,
+ result => res_1
+ );
ALTMULT_ADD_2 : altmult_add
- port map (
- dataa => taps(143 downto 96),
- datab => coefs(191 downto 128),
- clock0 => clk,
- aclr3 => rst,
- result => res_2
- );
+ port map (
+ dataa => taps(143 downto 96),
+ datab => coefs(191 downto 128),
+ clock0 => clk,
+ aclr3 => rst,
+ result => res_2
+ );
ALTMULT_ADD_3 : altmult_add
- port map (
- dataa => taps(191 downto 144),
- datab => coefs(255 downto 192),
- clock0 => clk,
- aclr3 => rst,
- result => res_3
- );
+ port map (
+ dataa => taps(191 downto 144),
+ datab => coefs(255 downto 192),
+ clock0 => clk,
+ aclr3 => rst,
+ result => res_3
+ );
end stratix;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
index de51085899..4973924a05 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib, common_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity pfs_filter is
@@ -71,27 +71,27 @@ begin
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
gen : for i in 0 to 7 generate
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
--MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
MULT_ADD : entity common_mult_lib.common_mult_add -- rtl
- generic map (
- g_in_a_w => g_taps_w,
- g_in_b_w => g_coef_w,
- g_out_dat_w => g_coef_w + g_taps_w + 1,
- g_add_sub => "ADD",
- g_pipeline => 3
- )
- port map (
- clk => clk,
- in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
- in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
- in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
- in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
- out_dat => res(i)
- );
+ generic map (
+ g_in_a_w => g_taps_w,
+ g_in_b_w => g_coef_w,
+ g_out_dat_w => g_coef_w + g_taps_w + 1,
+ g_add_sub => "ADD",
+ g_pipeline => 3
+ )
+ port map (
+ clk => clk,
+ in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
+ in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
+ in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
+ in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
+ out_dat => res(i)
+ );
end generate;
pipe : process (clk)
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
index 86711a87f5..03530d7f9e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
@@ -1,7 +1,7 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
library common_lib;
-use common_lib.common_pkg.all;
+ use common_lib.common_pkg.all;
architecture str of pfs_fir is
@@ -30,144 +30,144 @@ architecture str of pfs_fir is
begin
ctrl : entity pfs_lib.pfs_fir_ctrl
- generic map (
- g_nof_prefilter => g_nof_prefilter,
- g_nof_prefilter_w => c_nof_prefilter_w,
- g_nof_taps => g_nof_taps,
- g_nof_taps_w => c_nof_taps_w,
- g_sample_width => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- input_hor => in_hor,
- input_ver => in_ver,
- input_val => in_val,
- input_sync => in_sync,
- coefs_addr => coefs_addr,
- coefs_rden => coefs_rden,
- sample_addr => sample_addr,
- sample_data_hor => sample_data_hor,
- sample_data_ver => sample_data_ver,
- sample_wren => sample_wren,
- taps_addr => taps_addr,
- taps_rden => taps_rden,
- res_clr => res_clr,
- result_val => i_res_val,
- result_sync => res_sync
- );
+ generic map (
+ g_nof_prefilter => g_nof_prefilter,
+ g_nof_prefilter_w => c_nof_prefilter_w,
+ g_nof_taps => g_nof_taps,
+ g_nof_taps_w => c_nof_taps_w,
+ g_sample_width => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ input_hor => in_hor,
+ input_ver => in_ver,
+ input_val => in_val,
+ input_sync => in_sync,
+ coefs_addr => coefs_addr,
+ coefs_rden => coefs_rden,
+ sample_addr => sample_addr,
+ sample_data_hor => sample_data_hor,
+ sample_data_ver => sample_data_ver,
+ sample_wren => sample_wren,
+ taps_addr => taps_addr,
+ taps_rden => taps_rden,
+ res_clr => res_clr,
+ result_val => i_res_val,
+ result_sync => res_sync
+ );
mac_hor : entity pfs_lib.pfs_fir_mac
- generic map (
- g_a_in_w => g_in_dat_w,
- g_b_in_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => c_nof_taps_w,
- g_mult_pipeline => c_mult_latency
- )
- port map (
- data_a => taps_data_hor,
- data_b => coefs_data,
- res_clr => res_clr,
- res_val => i_res_val,
- clk => clk,
- rst => rst,
- result => res_hor
- );
+ generic map (
+ g_a_in_w => g_in_dat_w,
+ g_b_in_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => c_nof_taps_w,
+ g_mult_pipeline => c_mult_latency
+ )
+ port map (
+ data_a => taps_data_hor,
+ data_b => coefs_data,
+ res_clr => res_clr,
+ res_val => i_res_val,
+ clk => clk,
+ rst => rst,
+ result => res_hor
+ );
mac_ver : entity pfs_lib.pfs_fir_mac
- generic map (
- g_a_in_w => g_in_dat_w,
- g_b_in_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => c_nof_taps_w,
- g_mult_pipeline => c_mult_latency
- )
- port map (
- data_a => taps_data_ver,
- data_b => coefs_data,
- res_clr => res_clr,
- res_val => i_res_val,
- clk => clk,
- rst => rst,
- result => res_ver
- );
+ generic map (
+ g_a_in_w => g_in_dat_w,
+ g_b_in_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => c_nof_taps_w,
+ g_mult_pipeline => c_mult_latency
+ )
+ port map (
+ data_a => taps_data_ver,
+ data_b => coefs_data,
+ res_clr => res_clr,
+ res_val => i_res_val,
+ clk => clk,
+ rst => rst,
+ result => res_ver
+ );
coefsbuf_0 : if g_fir_nr = 0 generate
coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w,
- g_coefs_w => c_addr_w,
- g_nof_coefs => c_nof_coefs,
- g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_0_"
+ generic map (
+ g_data_w => g_coef_dat_w,
+ g_coefs_w => c_addr_w,
+ g_nof_coefs => c_nof_coefs,
+ g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_0_"
& natural'image(g_nof_prefilter * g_nof_taps) & "pts.hex"
- )
- port map (
- addr => coefs_addr,
- rden => coefs_rden,
- data => coefs_data,
- clk => clk,
- rst => rst
- );
+ )
+ port map (
+ addr => coefs_addr,
+ rden => coefs_rden,
+ data => coefs_data,
+ clk => clk,
+ rst => rst
+ );
end generate;
coefsbuf_N : if g_fir_nr > 0 generate
coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w,
- g_coefs_w => c_addr_w,
- g_nof_coefs => c_nof_coefs,
- g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_"
+ generic map (
+ g_data_w => g_coef_dat_w,
+ g_coefs_w => c_addr_w,
+ g_nof_coefs => c_nof_coefs,
+ g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_"
& natural'image(g_fir_nr) & "_" & natural'image(g_nof_prefilter * g_nof_taps) & "pts.hex"
- )
- port map (
- addr => coefs_addr,
- rden => coefs_rden,
- data => coefs_data,
- clk => clk,
- rst => rst
- );
+ )
+ port map (
+ addr => coefs_addr,
+ rden => coefs_rden,
+ data => coefs_data,
+ clk => clk,
+ rst => rst
+ );
end generate;
tapsbuf_hor : entity pfs_lib.pfs_fir_tapsbuf
- generic map (
- g_data_w => g_in_dat_w,
- g_nof_words => c_nof_coefs,
- g_addr_w => c_addr_w
- )
- port map (
- data_a => sample_data_hor,
- wren_a => sample_wren,
- addr_a => sample_addr,
- addr_b => taps_addr,
- rden_b => taps_rden,
- data_b => taps_data_hor,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w,
+ g_nof_words => c_nof_coefs,
+ g_addr_w => c_addr_w
+ )
+ port map (
+ data_a => sample_data_hor,
+ wren_a => sample_wren,
+ addr_a => sample_addr,
+ addr_b => taps_addr,
+ rden_b => taps_rden,
+ data_b => taps_data_hor,
+ clk => clk,
+ rst => rst
+ );
tapsbuf_ver : entity pfs_lib.pfs_fir_tapsbuf
- generic map (
- g_data_w => g_in_dat_w,
- g_nof_words => c_nof_coefs,
- g_addr_w => c_addr_w
- )
- port map (
- data_a => sample_data_ver,
- wren_a => sample_wren,
- addr_a => sample_addr,
- addr_b => taps_addr,
- rden_b => taps_rden,
- data_b => taps_data_ver,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w,
+ g_nof_words => c_nof_coefs,
+ g_addr_w => c_addr_w
+ )
+ port map (
+ data_a => sample_data_ver,
+ wren_a => sample_wren,
+ addr_a => sample_addr,
+ addr_b => taps_addr,
+ rden_b => taps_rden,
+ data_b => taps_data_ver,
+ clk => clk,
+ rst => rst
+ );
res_val <= i_res_val;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
index 1d5f3219c1..e678b8f1cd 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir is
@@ -8,10 +8,10 @@ entity pfs_fir is
g_in_dat_w : natural;
g_out_dat_w : natural;
g_coef_dat_w : natural;
--- g_nof_fir : NATURAL;
--- g_nof_subbands : NATURAL;
+ -- g_nof_fir : NATURAL;
+ -- g_nof_subbands : NATURAL;
g_nof_prefilter : natural;
--- g_nof_polarizations : NATURAL;
+ -- g_nof_polarizations : NATURAL;
g_nof_taps : natural;
g_fir_nr : natural
);
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
index 9569e84d0b..aca98096b3 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
@@ -1,57 +1,57 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_coefsbuf is
component altsyncram
- generic (
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_a : string;
- outdata_aclr_a : string;
- read_during_write_mode_mixed_ports : string;
- ram_block_type : string;
- init_file : string;
- intended_device_family : string
- );
- port (
+ generic (
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_a : string;
+ outdata_aclr_a : string;
+ read_during_write_mode_mixed_ports : string;
+ ram_block_type : string;
+ init_file : string;
+ intended_device_family : string
+ );
+ port (
aclr0 : in std_logic ;
clock0 : in std_logic ;
address_a : in std_logic_vector(g_coefs_w - 1 downto 0);
q_a : out std_logic_vector(g_data_w - 1 downto 0)
- );
+ );
end component;
begin
rom : altsyncram
- generic map (
- operation_mode => "ROM",
- width_a => g_data_w,
- widthad_a => g_coefs_w,
- numwords_a => g_nof_coefs,
- lpm_type => "altsyncram",
- width_byteena_a => 1,
- outdata_reg_a => "CLOCK0",
- outdata_aclr_a => "CLEAR0",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- ram_block_type => "AUTO",
- init_file => g_init_file,
- intended_device_family => c_rsp_device_family
- )
- port map (
- aclr0 => rst,
- clock0 => clk,
- address_a => addr,
- q_a => data
- );
+ generic map (
+ operation_mode => "ROM",
+ width_a => g_data_w,
+ widthad_a => g_coefs_w,
+ numwords_a => g_nof_coefs,
+ lpm_type => "altsyncram",
+ width_byteena_a => 1,
+ outdata_reg_a => "CLOCK0",
+ outdata_aclr_a => "CLEAR0",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ ram_block_type => "AUTO",
+ init_file => g_init_file,
+ intended_device_family => c_rsp_device_family
+ )
+ port map (
+ aclr0 => rst,
+ clock0 => clk,
+ address_a => addr,
+ q_a => data
+ );
end stratix;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
index 7eecba0059..981f4b55d2 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_coefsbuf is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
index 0a33653b35..48b4751b33 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
architecture rtl of pfs_fir_ctrl is
@@ -52,7 +52,7 @@ begin
-- Output signals.
result_val <= mac_res_delay(mac_res_delay'high);
result_sync <= sync_delay(sync_delay'high);
--- res_clr <= mac_res_delay(c_mac_clr_delay - 1);
+ -- res_clr <= mac_res_delay(c_mac_clr_delay - 1);
taps_addr <= i_taps_addr;
sample_data_hor <= i_sample_data_hor;
sample_data_ver <= i_sample_data_ver;
@@ -188,9 +188,9 @@ begin
if input_val = '1' then
nxt_sample_data_hor <= std_logic_vector(to_signed(
- to_integer(signed(input_hor)), i_sample_data_hor'length));
+ to_integer(signed(input_hor)), i_sample_data_hor'length));
nxt_sample_data_ver <= std_logic_vector(to_signed(
- to_integer(signed(input_ver)), i_sample_data_ver'length));
+ to_integer(signed(input_ver)), i_sample_data_ver'length));
end if;
end process;
@@ -212,13 +212,13 @@ begin
if unsigned(prefilter_cnt) = (g_nof_prefilter - 1) and last_tap = '1' then
nxt_taps_addr_base <=
- std_logic_vector(unsigned(taps_addr_base) + 1);
+ std_logic_vector(unsigned(taps_addr_base) + 1);
end if;
end process;
taps_addr_offset <= std_logic_vector(unsigned(taps_addr_base)
- + unsigned(taps_cnt));
+ + unsigned(taps_cnt));
-- The MAC delay register is used to generate a valid pulse for the MAC output
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
index 3554e9b5d8..927894e69d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
@@ -1,5 +1,5 @@
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
entity pfs_fir_ctrl is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
index 845d6a4ea4..fdfef91bb2 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
@@ -1,49 +1,49 @@
library IEEE, lpm, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_mac is
component altmult_accum
- generic (
- intended_device_family : string;
- width_a : natural;
- width_b : natural;
- representation_a : string;
- representation_b : string;
- lpm_type : string;
- width_result : natural;
- input_source_a : string;
- input_source_b : string;
- multiplier_rounding : string;
- multiplier_saturation : string;
- port_mult_is_saturated : string;
- accumulator_rounding : string;
- accumulator_saturation : string;
- port_accum_is_saturated : string;
- accum_direction : string;
- input_reg_a : string;
- input_aclr_a : string;
- input_reg_b : string;
- input_aclr_b : string;
- multiplier_reg : string;
- multiplier_aclr : string;
- accum_sload_reg : string;
- accum_sload_pipeline_reg : string;
- output_reg : string;
- output_aclr : string;
- dedicated_multiplier_circuitry : string
- );
- port (
- dataa : in std_logic_vector(width_a - 1 downto 0);
- datab : in std_logic_vector(width_b - 1 downto 0);
- accum_sload : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- result : out std_logic_vector(width_result - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ width_a : natural;
+ width_b : natural;
+ representation_a : string;
+ representation_b : string;
+ lpm_type : string;
+ width_result : natural;
+ input_source_a : string;
+ input_source_b : string;
+ multiplier_rounding : string;
+ multiplier_saturation : string;
+ port_mult_is_saturated : string;
+ accumulator_rounding : string;
+ accumulator_saturation : string;
+ port_accum_is_saturated : string;
+ accum_direction : string;
+ input_reg_a : string;
+ input_aclr_a : string;
+ input_reg_b : string;
+ input_aclr_b : string;
+ multiplier_reg : string;
+ multiplier_aclr : string;
+ accum_sload_reg : string;
+ accum_sload_pipeline_reg : string;
+ output_reg : string;
+ output_aclr : string;
+ dedicated_multiplier_circuitry : string
+ );
+ port (
+ dataa : in std_logic_vector(width_a - 1 downto 0);
+ datab : in std_logic_vector(width_b - 1 downto 0);
+ accum_sload : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ result : out std_logic_vector(width_result - 1 downto 0)
+ );
end component;
@@ -63,43 +63,43 @@ begin
mac : altmult_accum
- generic map (
- intended_device_family => c_rsp_device_family,
- width_a => g_a_in_w,
- width_b => g_b_in_w,
- representation_a => "SIGNED",
- representation_b => "SIGNED",
- lpm_type => "altmult_accum",
- width_result => g_a_in_w + g_b_in_w,
- input_source_a => "DATAA",
- input_source_b => "DATAB",
- multiplier_rounding => "NO",
- multiplier_saturation => "NO",
- port_mult_is_saturated => "UNUSED",
- accumulator_rounding => "NO",
- accumulator_saturation => "NO",
- port_accum_is_saturated => "UNUSED",
- accum_direction => "ADD",
- input_reg_a => "CLOCK0",
- input_aclr_a => "ACLR0",
- input_reg_b => "CLOCK0",
- input_aclr_b => "ACLR0",
- multiplier_reg => "CLOCK0",
- multiplier_aclr => "ACLR0",
- accum_sload_reg => "CLOCK0",
- accum_sload_pipeline_reg => "CLOCK0",
- output_reg => "CLOCK0",
- output_aclr => "ACLR0",
- dedicated_multiplier_circuitry => "YES"
- )
- port map (
- dataa => data_a,
- datab => data_b,
- accum_sload => res_clr,
- aclr0 => rst,
- clock0 => clk,
- result => acc_out
- );
+ generic map (
+ intended_device_family => c_rsp_device_family,
+ width_a => g_a_in_w,
+ width_b => g_b_in_w,
+ representation_a => "SIGNED",
+ representation_b => "SIGNED",
+ lpm_type => "altmult_accum",
+ width_result => g_a_in_w + g_b_in_w,
+ input_source_a => "DATAA",
+ input_source_b => "DATAB",
+ multiplier_rounding => "NO",
+ multiplier_saturation => "NO",
+ port_mult_is_saturated => "UNUSED",
+ accumulator_rounding => "NO",
+ accumulator_saturation => "NO",
+ port_accum_is_saturated => "UNUSED",
+ accum_direction => "ADD",
+ input_reg_a => "CLOCK0",
+ input_aclr_a => "ACLR0",
+ input_reg_b => "CLOCK0",
+ input_aclr_b => "ACLR0",
+ multiplier_reg => "CLOCK0",
+ multiplier_aclr => "ACLR0",
+ accum_sload_reg => "CLOCK0",
+ accum_sload_pipeline_reg => "CLOCK0",
+ output_reg => "CLOCK0",
+ output_aclr => "ACLR0",
+ dedicated_multiplier_circuitry => "YES"
+ )
+ port map (
+ dataa => data_a,
+ datab => data_b,
+ accum_sload => res_clr,
+ aclr0 => rst,
+ clock0 => clk,
+ result => acc_out
+ );
end stratix;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
index 91a4949441..8b76144f2a 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_mac is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
index fe27455ccf..839081c4bb 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
@@ -1,72 +1,72 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_tapsbuf is
component altsyncram
- generic (
- intended_device_family : string;
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- width_b : natural;
- widthad_b : natural;
- numwords_b : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_b : string;
- address_reg_b : string;
- outdata_aclr_b : string;
- read_during_write_mode_mixed_ports : string;
- init_file : string;
- ram_block_type : string
- );
- port (
- wren_a : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- address_b : in std_logic_vector(g_addr_w - 1 downto 0);
- q_b : out std_logic_vector(g_data_w - 1 downto 0);
- data_a : in std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ width_b : natural;
+ widthad_b : natural;
+ numwords_b : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_b : string;
+ address_reg_b : string;
+ outdata_aclr_b : string;
+ read_during_write_mode_mixed_ports : string;
+ init_file : string;
+ ram_block_type : string
+ );
+ port (
+ wren_a : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_b : out std_logic_vector(g_data_w - 1 downto 0);
+ data_a : in std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
altsyncram_component : altsyncram
- generic map (
- intended_device_family => c_rsp_device_family,
- operation_mode => "DUAL_PORT",
- width_a => g_data_w,
- widthad_a => g_addr_w,
- numwords_a => g_nof_words,
- width_b => g_data_w,
- widthad_b => g_addr_w,
- numwords_b => g_nof_words,
- lpm_type => "altsyncram",
- width_byteena_a => 1,
- outdata_reg_b => "CLOCK0",
- address_reg_b => "CLOCK0",
- outdata_aclr_b => "CLEAR0",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- init_file => "../../../../../EPA/pfs/src/data/pfs_fir_taps_"
+ generic map (
+ intended_device_family => c_rsp_device_family,
+ operation_mode => "DUAL_PORT",
+ width_a => g_data_w,
+ widthad_a => g_addr_w,
+ numwords_a => g_nof_words,
+ width_b => g_data_w,
+ widthad_b => g_addr_w,
+ numwords_b => g_nof_words,
+ lpm_type => "altsyncram",
+ width_byteena_a => 1,
+ outdata_reg_b => "CLOCK0",
+ address_reg_b => "CLOCK0",
+ outdata_aclr_b => "CLEAR0",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ init_file => "../../../../../EPA/pfs/src/data/pfs_fir_taps_"
& natural'image(g_nof_words) & "pts.hex",
- ram_block_type => "AUTO"
- )
- port map (
- wren_a => wren_a,
- aclr0 => rst,
- clock0 => clk,
- address_a => addr_a,
- address_b => addr_b,
- data_a => data_a,
- q_b => data_b
- );
+ ram_block_type => "AUTO"
+ )
+ port map (
+ wren_a => wren_a,
+ aclr0 => rst,
+ clock0 => clk,
+ address_a => addr_a,
+ address_b => addr_b,
+ data_a => data_a,
+ q_b => data_b
+ );
end stratix;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
index e147c4872d..a04d8ea533 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_tapsbuf is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
index 08444d204e..f8af83592d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
@@ -24,8 +24,8 @@
-- Remark: Use package to keep default pfs constants
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pfs_pkg is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
index b33201039c..4932586b3d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_rotate is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
index d9fc8e59bc..99deb4d419 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_rotate is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
index 07d942d7cb..82a34427c3 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
@@ -1,31 +1,31 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
+ use common_lib.common_pkg.all;
architecture rtl of pfs_tapsbuf is
-type RamType is array(0 to 2**g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
+ type RamType is array(0 to 2**g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
--- pfs_tapsbuf_1024.hex is empty (all zeros)
-signal RAM : RamType := (others => (others => '0'));
+ -- pfs_tapsbuf_1024.hex is empty (all zeros)
+ signal RAM : RamType := (others => (others => '0'));
-signal read_addrb : std_logic_vector(g_addr_w - 1 downto 0);
+ signal read_addrb : std_logic_vector(g_addr_w - 1 downto 0);
begin
----------------------------------------------------------------
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (wren = '1') then
- RAM (conv_integer(wraddr)) <= wrdata;
- end if;
- read_addrb <= rdaddr;
+ ---------------------------------------------------------------
+ process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ if (wren = '1') then
+ RAM (conv_integer(wraddr)) <= wrdata;
+ end if;
+ read_addrb <= rdaddr;
rddata <= RAM(conv_integer(read_addrb));
- end if;
-end process;
+ end if;
+ end process;
---------------------------------------------------------------
---------------------------------------------------------------
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
index 416c141731..35a3c9c68f 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
@@ -1,71 +1,71 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_tapsbuf is
component altsyncram
- generic (
- intended_device_family : string;
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- width_b : natural;
- widthad_b : natural;
- numwords_b : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_b : string;
- address_reg_b : string;
- outdata_aclr_b : string;
- read_during_write_mode_mixed_ports : string;
- init_file : string;
- ram_block_type : string
- );
- port (
- wren_a : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- address_b : in std_logic_vector(g_addr_w - 1 downto 0);
- q_b : out std_logic_vector(g_data_w - 1 downto 0);
- data_a : in std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ width_b : natural;
+ widthad_b : natural;
+ numwords_b : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_b : string;
+ address_reg_b : string;
+ outdata_aclr_b : string;
+ read_during_write_mode_mixed_ports : string;
+ init_file : string;
+ ram_block_type : string
+ );
+ port (
+ wren_a : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_b : out std_logic_vector(g_data_w - 1 downto 0);
+ data_a : in std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
altsyncram_component : altsyncram
- generic map (
- intended_device_family => c_rsp_device_family,
- operation_mode => "DUAL_PORT",
- width_a => g_data_w,
- widthad_a => g_addr_w,
- numwords_a => g_nof_words,
- width_b => g_data_w,
- widthad_b => g_addr_w,
- numwords_b => g_nof_words,
- lpm_type => "altsyncram",
- width_byteena_a => 1,
- outdata_reg_b => "CLOCK0",
- address_reg_b => "CLOCK0",
- outdata_aclr_b => "CLEAR0",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- init_file => "../../../../pfs/src/data/pfs_tapsbuf_1024.hex",
- ram_block_type => "AUTO"
- )
- port map (
- wren_a => wren,
- aclr0 => rst,
- clock0 => clk,
- address_a => wraddr,
- address_b => rdaddr,
- data_a => wrdata,
- q_b => rddata
- );
+ generic map (
+ intended_device_family => c_rsp_device_family,
+ operation_mode => "DUAL_PORT",
+ width_a => g_data_w,
+ widthad_a => g_addr_w,
+ numwords_a => g_nof_words,
+ width_b => g_data_w,
+ widthad_b => g_addr_w,
+ numwords_b => g_nof_words,
+ lpm_type => "altsyncram",
+ width_byteena_a => 1,
+ outdata_reg_b => "CLOCK0",
+ address_reg_b => "CLOCK0",
+ outdata_aclr_b => "CLEAR0",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ init_file => "../../../../pfs/src/data/pfs_tapsbuf_1024.hex",
+ ram_block_type => "AUTO"
+ )
+ port map (
+ wren_a => wren,
+ aclr0 => rst,
+ clock0 => clk,
+ address_a => wraddr,
+ address_b => rdaddr,
+ data_a => wrdata,
+ q_b => rddata
+ );
end stratix;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
index 36a6e09163..89f543657e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_unsigned.all;
entity pfs_tapsbuf is
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
index 663a119396..a88bceba29 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
@@ -1,5 +1,5 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
architecture str of pfs_top is
@@ -30,25 +30,25 @@ begin
end process;
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => g_nof_bands,
- g_nof_taps => g_nof_taps,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_coef_dat_w => g_coef_dat_w
- )
- port map (
- in_dat_x => reg_in_dat_x,
- in_dat_y => reg_in_dat_y,
- in_val => reg_in_val,
- in_sync => reg_in_sync,
- out_dat_x => d_out_dat_x,
- out_dat_y => d_out_dat_y,
- out_val => d_out_val,
- out_sync => d_out_sync,
- clk => clk,
- rst => rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => g_nof_bands,
+ g_nof_taps => g_nof_taps,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_coef_dat_w => g_coef_dat_w
+ )
+ port map (
+ in_dat_x => reg_in_dat_x,
+ in_dat_y => reg_in_dat_y,
+ in_val => reg_in_val,
+ in_sync => reg_in_sync,
+ out_dat_x => d_out_dat_x,
+ out_dat_y => d_out_dat_y,
+ out_val => d_out_val,
+ out_sync => d_out_sync,
+ clk => clk,
+ rst => rst,
+ restart => '0'
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
index 7b318f2069..99ea3b24b2 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
@@ -1,5 +1,5 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pfs_top is
diff --git a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
index 14758276d5..72779e39e4 100644
--- a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
+++ b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
@@ -30,10 +30,10 @@
-- . View pfs_dat_x in decimal radix and analog format (right click)
library IEEE, pfs_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_pfs is
@@ -61,26 +61,26 @@ begin
rst <= '0' after 3 * clk_period;
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => 1024,
- g_nof_taps => 16 * 1024,
- g_in_dat_w => 12,
- g_out_dat_w => 18,
- g_coef_dat_w => 16
- )
- port map (
- in_dat_x => in_dat_x,
- in_dat_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- out_dat_x => pfs_dat_x,
- out_dat_y => pfs_dat_y,
- out_val => pfs_val,
- out_sync => pfs_sync,
- restart => '0',
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_nof_bands => 1024,
+ g_nof_taps => 16 * 1024,
+ g_in_dat_w => 12,
+ g_out_dat_w => 18,
+ g_coef_dat_w => 16
+ )
+ port map (
+ in_dat_x => in_dat_x,
+ in_dat_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_dat_x => pfs_dat_x,
+ out_dat_y => pfs_dat_y,
+ out_val => pfs_val,
+ out_sync => pfs_sync,
+ restart => '0',
+ clk => clk,
+ rst => rst
+ );
-- Keep in_dat_x high for one slice to get the filter impules response. Using amplitude 1024
-- yields the FIR coefficients, this amplitude compensates the PFS scaling of 2^4/2^14. The
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
index 979b3a80a1..41e9bd0f49 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pft_pkg is
constant c_pft_stage_dat_w : natural := 20;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
index 794c5bf7b4..c26b783999 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.pft_pkg.all;
+ use pft2_lib.pft_pkg.all;
architecture str of pft is
@@ -72,7 +72,7 @@ architecture str of pft is
signal power : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
signal power_x : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
signal power_y : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
- -- synthesis translate_on
+-- synthesis translate_on
begin
@@ -82,23 +82,23 @@ begin
switch: entity pft2_lib.pft_switch
- generic map (
- g_dat_w => g_in_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_sync => in_sync,
- in_re => in_re,
- in_im => in_im,
- switch_en => switch_en,
- out_re => switch_re,
- out_im => switch_im,
- out_val => switch_val,
- out_sync => switch_sync
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_sync => in_sync,
+ in_re => in_re,
+ in_im => in_im,
+ switch_en => switch_en,
+ out_re => switch_re,
+ out_im => switch_im,
+ out_val => switch_val,
+ out_sync => switch_sync
+ );
first_gen : if (c_nof_stages > 1) generate
first_stage : entity pft2_lib.pft_stage
@@ -166,23 +166,23 @@ begin
only_gen : if c_nof_stages = 1 generate
only_stage : entity pft2_lib.pft_stage
- generic map (
- g_index => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_pft_dat_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => pft_re,
- out_im => pft_im,
- out_val => pft_val,
- out_sync => pft_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_pft_dat_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => pft_re,
+ out_im => pft_im,
+ out_val => pft_val,
+ out_sync => pft_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
-- In "BITREV" mode, fft output is in bit reversed order.
@@ -218,7 +218,7 @@ begin
end generate;
- reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
+ reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
reverse : entity pft2_lib.pft_reverse
generic map (
g_fft_sz => 2**g_fft_size_w,
@@ -270,66 +270,66 @@ begin
end generate;
unswitch: entity pft2_lib.pft_unswitch
- generic map (
- g_dat_w => g_out_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => sep_val,
- in_sync => sep_sync,
- in_re => sep_re,
- in_im => sep_im,
- switch_en => switch_en,
- out_re => unswitch_re,
- out_im => unswitch_im,
- out_val => unswitch_val,
- out_sync => unswitch_sync
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => sep_val,
+ in_sync => sep_sync,
+ in_re => sep_re,
+ in_im => sep_im,
+ switch_en => switch_en,
+ out_re => unswitch_re,
+ out_im => unswitch_im,
+ out_val => unswitch_val,
+ out_sync => unswitch_sync
+ );
-- calculate the power. This is intended to be used in simulations only.
-- synthesis translate_off
- determine_bin : process (clk)
- begin
- if rising_edge(clk) then
- if unswitch_val = '1' then
- bin <= std_logic_vector(unsigned(bin) + 1);
- end if;
+ determine_bin : process (clk)
+ begin
+ if rising_edge(clk) then
+ if unswitch_val = '1' then
+ bin <= std_logic_vector(unsigned(bin) + 1);
end if;
- end process;
-
- band <= bin(bin'high downto 1);
-
- power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
- + signed(unswitch_im) * signed(unswitch_im)
- ) when unswitch_val = '1' else (others => '0');
-
- -- Wave window: View fft_re, fft_im in analogue format
- -- Wave window: View power in binary format to get a spectrum diagram
-
- -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
- -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
-
- -- Use clk to avoid limit cycle pulses in power_x and power_y
- demux_power : process(clk)
- begin
- if falling_edge(clk) then
- if unswitch_val = '1' then
- if bin(0) = '0' then
- fft_x_re <= unswitch_re;
- fft_x_im <= unswitch_im;
- power_x <= power;
- else
- fft_y_re <= unswitch_re;
- fft_y_im <= unswitch_im;
- power_y <= power;
- end if;
+ end if;
+ end process;
+
+ band <= bin(bin'high downto 1);
+
+ power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
+ + signed(unswitch_im) * signed(unswitch_im)
+ ) when unswitch_val = '1' else (others => '0');
+
+ -- Wave window: View fft_re, fft_im in analogue format
+ -- Wave window: View power in binary format to get a spectrum diagram
+
+ -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
+ -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
+
+ -- Use clk to avoid limit cycle pulses in power_x and power_y
+ demux_power : process(clk)
+ begin
+ if falling_edge(clk) then
+ if unswitch_val = '1' then
+ if bin(0) = '0' then
+ fft_x_re <= unswitch_re;
+ fft_x_im <= unswitch_im;
+ power_x <= power;
+ else
+ fft_y_re <= unswitch_re;
+ fft_y_im <= unswitch_im;
+ power_y <= power;
end if;
end if;
- end process;
+ end if;
+ end process;
-- synthesis translate_on
out_re <= unswitch_re;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
index ea022d0a49..e624233134 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.pft_pkg.all;
entity pft is
@@ -119,7 +119,7 @@ architecture str of pft is
signal power : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
signal power_x : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
signal power_y : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
- -- synthesis translate_on
+-- synthesis translate_on
begin
@@ -129,23 +129,23 @@ begin
switch: entity work.pft_switch
- generic map (
- g_dat_w => g_in_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_sync => in_sync,
- in_re => in_re,
- in_im => in_im,
- switch_en => switch_en,
- out_re => switch_re,
- out_im => switch_im,
- out_val => switch_val,
- out_sync => switch_sync
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_sync => in_sync,
+ in_re => in_re,
+ in_im => in_im,
+ switch_en => switch_en,
+ out_re => switch_re,
+ out_im => switch_im,
+ out_val => switch_val,
+ out_sync => switch_sync
+ );
first_gen : if (c_nof_stages > 1) generate
first_stage : entity work.pft_stage
@@ -213,23 +213,23 @@ begin
only_gen : if c_nof_stages = 1 generate
only_stage : entity work.pft_stage
- generic map (
- g_index => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_pft_dat_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => pft_re,
- out_im => pft_im,
- out_val => pft_val,
- out_sync => pft_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_pft_dat_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => pft_re,
+ out_im => pft_im,
+ out_val => pft_val,
+ out_sync => pft_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
-- In "BITREV" mode, fft output is in bit reversed order.
@@ -265,7 +265,7 @@ begin
end generate;
- reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
+ reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
reverse : entity work.pft_reverse
generic map (
g_fft_sz => 2**g_fft_size_w,
@@ -317,66 +317,66 @@ begin
end generate;
unswitch: entity work.pft_unswitch
- generic map (
- g_dat_w => g_out_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => sep_val,
- in_sync => sep_sync,
- in_re => sep_re,
- in_im => sep_im,
- switch_en => switch_en,
- out_re => unswitch_re,
- out_im => unswitch_im,
- out_val => unswitch_val,
- out_sync => unswitch_sync
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => sep_val,
+ in_sync => sep_sync,
+ in_re => sep_re,
+ in_im => sep_im,
+ switch_en => switch_en,
+ out_re => unswitch_re,
+ out_im => unswitch_im,
+ out_val => unswitch_val,
+ out_sync => unswitch_sync
+ );
-- calculate the power. This is intended to be used in simulations only.
-- synthesis translate_off
- determine_bin : process (clk)
- begin
- if rising_edge(clk) then
- if unswitch_val = '1' then
- bin <= std_logic_vector(unsigned(bin) + 1);
- end if;
+ determine_bin : process (clk)
+ begin
+ if rising_edge(clk) then
+ if unswitch_val = '1' then
+ bin <= std_logic_vector(unsigned(bin) + 1);
end if;
- end process;
-
- band <= bin(bin'high downto 1);
-
- power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
- + signed(unswitch_im) * signed(unswitch_im)
- ) when unswitch_val = '1' else (others => '0');
-
- -- Wave window: View fft_re, fft_im in analogue format
- -- Wave window: View power in binary format to get a spectrum diagram
-
- -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
- -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
-
- -- Use clk to avoid limit cycle pulses in power_x and power_y
- demux_power : process(clk)
- begin
- if falling_edge(clk) then
- if unswitch_val = '1' then
- if bin(0) = '0' then
- fft_x_re <= unswitch_re;
- fft_x_im <= unswitch_im;
- power_x <= power;
- else
- fft_y_re <= unswitch_re;
- fft_y_im <= unswitch_im;
- power_y <= power;
- end if;
+ end if;
+ end process;
+
+ band <= bin(bin'high downto 1);
+
+ power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
+ + signed(unswitch_im) * signed(unswitch_im)
+ ) when unswitch_val = '1' else (others => '0');
+
+ -- Wave window: View fft_re, fft_im in analogue format
+ -- Wave window: View power in binary format to get a spectrum diagram
+
+ -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
+ -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
+
+ -- Use clk to avoid limit cycle pulses in power_x and power_y
+ demux_power : process(clk)
+ begin
+ if falling_edge(clk) then
+ if unswitch_val = '1' then
+ if bin(0) = '0' then
+ fft_x_re <= unswitch_re;
+ fft_x_im <= unswitch_im;
+ power_x <= power;
+ else
+ fft_y_re <= unswitch_re;
+ fft_y_im <= unswitch_im;
+ power_y <= power;
end if;
end if;
- end process;
+ end if;
+ end process;
-- synthesis translate_on
out_re <= unswitch_re;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
index 5cd8e02ac4..ad244eff3a 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_bf is
@@ -157,7 +157,7 @@ begin
rd_re <= (others => '0');
rd_im <= (others => '0');
end if;
- --synthesis translate on
+ --synthesis translate on
end process;
rd_req <= in_val and init;
@@ -214,11 +214,11 @@ begin
end process;
--- Adds/ Subs ------------------------------------------------------------------
+ -- Adds/ Subs ------------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--cadd : ENTITY common_lib.common_caddsub
--GENERIC MAP (
@@ -242,120 +242,120 @@ begin
--);
cadd : entity common_complex_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => add_ar,
- in_ai => add_ai,
- in_br => add_br,
- in_bi => add_bi,
- out_re => add_cr,
- out_im => add_ci
- );
-
--- csub : ENTITY common_lib.common_caddsub
--- GENERIC MAP (
--- g_in_a_w => c_dat_w,
--- g_in_b_w => c_dat_w,
--- g_out_c_w => c_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_ar => sub_ar,
--- in_ai => sub_ai,
--- in_br => sub_br,
--- in_bi => sub_bi,
--- in_cr => '1',
--- in_ci => '1',
--- out_cr => sub_cr,
--- out_ci => sub_ci,
--- clk => clk,
--- rst => rst
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => add_ar,
+ in_ai => add_ai,
+ in_br => add_br,
+ in_bi => add_bi,
+ out_re => add_cr,
+ out_im => add_ci
+ );
+
+ -- csub : ENTITY common_lib.common_caddsub
+ -- GENERIC MAP (
+ -- g_in_a_w => c_dat_w,
+ -- g_in_b_w => c_dat_w,
+ -- g_out_c_w => c_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_ar => sub_ar,
+ -- in_ai => sub_ai,
+ -- in_br => sub_br,
+ -- in_bi => sub_bi,
+ -- in_cr => '1',
+ -- in_ci => '1',
+ -- out_cr => sub_cr,
+ -- out_ci => sub_ci,
+ -- clk => clk,
+ -- rst => rst
+ -- );
csub : entity common_complex_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => sub_ar,
- in_ai => sub_ai,
- in_br => sub_br,
- in_bi => sub_bi,
- out_re => sub_cr,
- out_im => sub_ci
- );
-
--- regbank --------------------------------------------------------------------------
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => sub_ar,
+ in_ai => sub_ai,
+ in_br => sub_br,
+ in_bi => sub_bi,
+ out_re => sub_cr,
+ out_im => sub_ci
+ );
+
+ -- regbank --------------------------------------------------------------------------
fifo_gen: if c_regbank_size > 8 generate
- fifo : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => wr_dat'LENGTH,
- g_nof_words => c_regbank_size
- )
- port map (
- wr_dat => wr_dat,
- wr_req => wr_req,
- rd_dat => rd_dat,
- rd_req => rd_req,
- clk => clk,
- rst => rst
- );
+ fifo : entity common_lib.common_fifo_sc
+ generic map (
+ g_dat_w => wr_dat'LENGTH,
+ g_nof_words => c_regbank_size
+ )
+ port map (
+ wr_dat => wr_dat,
+ wr_req => wr_req,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ clk => clk,
+ rst => rst
+ );
end generate fifo_gen;
fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
- fifo2_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
+ fifo2_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
- fifo2_proc : process(fifo_dat,wr_req,wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo2_proc : process(fifo_dat,wr_req,wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
fifo3_gen : if c_regbank_size = c_pipeline generate
- fifo3_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
+ fifo3_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
- fifo3_proc : process(fifo_dat, wr_req, wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat(0) <= wr_dat;
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo3_proc : process(fifo_dat, wr_req, wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat(0) <= wr_dat;
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
assert c_regbank_size >= c_pipeline severity FAILURE;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index edbaf8f12a..72d5e5acf5 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
@@ -206,7 +206,7 @@ begin
rd_re <= (others => '0');
rd_im <= (others => '0');
end if;
- --synthesis translate on
+ --synthesis translate on
end process;
rd_req <= in_val and init;
@@ -263,11 +263,11 @@ begin
end process;
--- Adds/ Subs ------------------------------------------------------------------
+ -- Adds/ Subs ------------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--cadd : ENTITY common_lib.common_caddsub
--GENERIC MAP (
@@ -291,120 +291,120 @@ begin
--);
cadd : entity common_lib.common_complex_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => add_ar,
- in_ai => add_ai,
- in_br => add_br,
- in_bi => add_bi,
- out_re => add_cr,
- out_im => add_ci
- );
-
--- csub : ENTITY common_lib.common_caddsub
--- GENERIC MAP (
--- g_in_a_w => c_dat_w,
--- g_in_b_w => c_dat_w,
--- g_out_c_w => c_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_ar => sub_ar,
--- in_ai => sub_ai,
--- in_br => sub_br,
--- in_bi => sub_bi,
--- in_cr => '1',
--- in_ci => '1',
--- out_cr => sub_cr,
--- out_ci => sub_ci,
--- clk => clk,
--- rst => rst
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => add_ar,
+ in_ai => add_ai,
+ in_br => add_br,
+ in_bi => add_bi,
+ out_re => add_cr,
+ out_im => add_ci
+ );
+
+ -- csub : ENTITY common_lib.common_caddsub
+ -- GENERIC MAP (
+ -- g_in_a_w => c_dat_w,
+ -- g_in_b_w => c_dat_w,
+ -- g_out_c_w => c_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_ar => sub_ar,
+ -- in_ai => sub_ai,
+ -- in_br => sub_br,
+ -- in_bi => sub_bi,
+ -- in_cr => '1',
+ -- in_ci => '1',
+ -- out_cr => sub_cr,
+ -- out_ci => sub_ci,
+ -- clk => clk,
+ -- rst => rst
+ -- );
csub : entity common_lib.common_complex_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => sub_ar,
- in_ai => sub_ai,
- in_br => sub_br,
- in_bi => sub_bi,
- out_re => sub_cr,
- out_im => sub_ci
- );
-
--- regbank --------------------------------------------------------------------------
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => sub_ar,
+ in_ai => sub_ai,
+ in_br => sub_br,
+ in_bi => sub_bi,
+ out_re => sub_cr,
+ out_im => sub_ci
+ );
+
+ -- regbank --------------------------------------------------------------------------
fifo_gen: if c_regbank_size > 8 generate
- fifo : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => wr_dat'LENGTH,
- g_nof_words => c_regbank_size
- )
- port map (
- wr_dat => wr_dat,
- wr_req => wr_req,
- rd_dat => rd_dat,
- rd_req => rd_req,
- clk => clk,
- rst => rst
- );
+ fifo : entity common_lib.common_fifo_sc
+ generic map (
+ g_dat_w => wr_dat'LENGTH,
+ g_nof_words => c_regbank_size
+ )
+ port map (
+ wr_dat => wr_dat,
+ wr_req => wr_req,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ clk => clk,
+ rst => rst
+ );
end generate fifo_gen;
fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
- fifo2_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
+ fifo2_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
- fifo2_proc : process(fifo_dat,wr_req,wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo2_proc : process(fifo_dat,wr_req,wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
fifo3_gen : if c_regbank_size = c_pipeline generate
- fifo3_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
+ fifo3_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
- fifo3_proc : process(fifo_dat, wr_req, wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat(0) <= wr_dat;
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo3_proc : process(fifo_dat, wr_req, wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat(0) <= wr_dat;
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
assert c_regbank_size >= c_pipeline severity FAILURE;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
index b0a1c3b417..a1ff150573 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_bf_fw is
@@ -163,81 +163,81 @@ begin
-- Adds/ Subs ----------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- yr_cry <= NOT yr_add;
-
--- yr : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yr_a,
--- in_b => yr_b,
--- in_cry => yr_cry,
--- add_sub => yr_add,
--- clk => clk,
--- out_c => out_re
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- yr_cry <= NOT yr_add;
+
+ -- yr : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yr_a,
+ -- in_b => yr_b,
+ -- in_cry => yr_cry,
+ -- add_sub => yr_add,
+ -- clk => clk,
+ -- out_c => out_re
+ -- );
yr : entity common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yr_add,
- in_a => yr_a,
- in_b => yr_b,
- result => out_re
- );
-
--- yi_cry <= NOT yi_add;
---
--- yi : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yi_a,
--- in_b => yi_b,
--- in_cry => yi_cry,
--- add_sub => yi_add,
--- clk => clk,
--- out_c => out_im
--- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yr_add,
+ in_a => yr_a,
+ in_b => yr_b,
+ result => out_re
+ );
+
+ -- yi_cry <= NOT yi_add;
+ --
+ -- yi : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yi_a,
+ -- in_b => yi_b,
+ -- in_cry => yi_cry,
+ -- add_sub => yi_add,
+ -- clk => clk,
+ -- out_c => out_im
+ -- );
yi : entity common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yi_add,
- in_a => yi_a,
- in_b => yi_b,
- result => out_im
- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yi_add,
+ in_a => yi_a,
+ in_b => yi_b,
+ result => out_im
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
index 77530984b9..81960d0c89 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
@@ -212,80 +212,80 @@ begin
-- Adds/ Subs ----------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- yr_cry <= NOT yr_add;
-
--- yr : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yr_a,
--- in_b => yr_b,
--- in_cry => yr_cry,
--- add_sub => yr_add,
--- clk => clk,
--- out_c => out_re
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- yr_cry <= NOT yr_add;
+
+ -- yr : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yr_a,
+ -- in_b => yr_b,
+ -- in_cry => yr_cry,
+ -- add_sub => yr_add,
+ -- clk => clk,
+ -- out_c => out_re
+ -- );
yr : entity common_lib.common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yr_add,
- in_a => yr_a,
- in_b => yr_b,
- result => out_re
- );
-
--- yi_cry <= NOT yi_add;
---
--- yi : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yi_a,
--- in_b => yi_b,
--- in_cry => yi_cry,
--- add_sub => yi_add,
--- clk => clk,
--- out_c => out_im
--- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yr_add,
+ in_a => yr_a,
+ in_b => yr_b,
+ result => out_re
+ );
+
+ -- yi_cry <= NOT yi_add;
+ --
+ -- yi : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yi_a,
+ -- in_b => yi_b,
+ -- in_cry => yi_cry,
+ -- add_sub => yi_add,
+ -- clk => clk,
+ -- out_c => out_im
+ -- );
yi : entity common_lib.common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yi_add,
- in_a => yi_a,
- in_b => yi_b,
- result => out_im
- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yi_add,
+ in_a => yi_a,
+ in_b => yi_b,
+ result => out_im
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
index f6fa171496..6aa47b367b 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
@@ -1,11 +1,11 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
architecture rtl of pft_buffer is
@@ -13,11 +13,13 @@ architecture rtl of pft_buffer is
constant c_adr_w : natural := g_fft_size_w + 1;
constant c_nof_words : natural := 2**c_adr_w;
- constant c_ram : t_c_mem := (latency => c_latency,
- adr_w => c_adr_w,
- dat_w => 2 * g_dat_w,
- nof_dat => c_nof_words, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_ram : t_c_mem := (
+ latency => c_latency,
+ adr_w => c_adr_w,
+ dat_w => 2 * g_dat_w,
+ nof_dat => c_nof_words, -- <= 2**g_addr_w
+ init_sl => '0'
+ );
signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
signal wr_dat : std_logic_vector(rd_dat'range);
@@ -35,7 +37,7 @@ architecture rtl of pft_buffer is
signal pipe_val : std_logic_vector(c_latency - 1 downto 0);
signal nxt_pipe_val : std_logic_vector(pipe_val'range);
- function bit_rev(adr : in std_logic_vector) return std_logic_vector is
+ function bit_rev (adr : in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(adr'range);
begin
for i in adr'high downto 0 loop
@@ -99,44 +101,44 @@ begin
rd_re <= (others => '0');
rd_im <= (others => '0');
end if;
- --synthesis translate on
+ --synthesis translate on
end process;
wr_dat <= wr_re & wr_im;
wr_en <= wr_val;
--- -- ram module
--- ram : ENTITY common_lib.common_dpram
--- GENERIC MAP (
--- g_dat_w => 2*g_dat_w,
--- g_adr_w => c_adr_w,
--- g_nof_words => c_nof_words
--- )
--- PORT MAP (
--- rd_dat => rd_dat,
--- rd_adr => rd_adr_paged,
--- rd_en => rd_en,
--- wr_dat => wr_dat,
--- wr_adr => wr_adr_paged,
--- wr_en => wr_en,
--- clk => clk,
--- rst => rst
--- );
+ -- -- ram module
+ -- ram : ENTITY common_lib.common_dpram
+ -- GENERIC MAP (
+ -- g_dat_w => 2*g_dat_w,
+ -- g_adr_w => c_adr_w,
+ -- g_nof_words => c_nof_words
+ -- )
+ -- PORT MAP (
+ -- rd_dat => rd_dat,
+ -- rd_adr => rd_adr_paged,
+ -- rd_en => rd_en,
+ -- wr_dat => wr_dat,
+ -- wr_adr => wr_adr_paged,
+ -- wr_en => wr_en,
+ -- clk => clk,
+ -- rst => rst
+ -- );
ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_en,
- wr_adr => wr_adr_paged,
- wr_dat => wr_dat,
- rd_en => rd_en,
- rd_adr => rd_adr_paged,
- rd_dat => rd_dat
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_en,
+ wr_adr => wr_adr_paged,
+ wr_dat => wr_dat,
+ rd_en => rd_en,
+ rd_adr => rd_adr_paged,
+ rd_dat => rd_dat
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
index 422d4c850a..a528050755 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
@@ -24,12 +24,12 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity pft_buffer is
generic (
@@ -60,11 +60,13 @@ architecture rtl of pft_buffer is
constant c_adr_w : natural := g_fft_size_w + 1;
constant c_nof_words : natural := 2**c_adr_w;
- constant c_ram : t_c_mem := (latency => c_latency,
- adr_w => c_adr_w,
- dat_w => 2 * g_dat_w,
- nof_dat => c_nof_words, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_ram : t_c_mem := (
+ latency => c_latency,
+ adr_w => c_adr_w,
+ dat_w => 2 * g_dat_w,
+ nof_dat => c_nof_words, -- <= 2**g_addr_w
+ init_sl => '0'
+ );
signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
signal wr_dat : std_logic_vector(rd_dat'range);
@@ -82,7 +84,7 @@ architecture rtl of pft_buffer is
signal pipe_val : std_logic_vector(c_latency - 1 downto 0);
signal nxt_pipe_val : std_logic_vector(pipe_val'range);
- function bit_rev(adr : in std_logic_vector) return std_logic_vector is
+ function bit_rev (adr : in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(adr'range);
begin
for i in adr'high downto 0 loop
@@ -146,43 +148,43 @@ begin
rd_re <= (others => '0');
rd_im <= (others => '0');
end if;
- --synthesis translate on
+ --synthesis translate on
end process;
wr_dat <= wr_re & wr_im;
wr_en <= wr_val;
--- -- ram module
--- ram : ENTITY common_lib.common_dpram
--- GENERIC MAP (
--- g_dat_w => 2*g_dat_w,
--- g_adr_w => c_adr_w,
--- g_nof_words => c_nof_words
--- )
--- PORT MAP (
--- rd_dat => rd_dat,
--- rd_adr => rd_adr_paged,
--- rd_en => rd_en,
--- wr_dat => wr_dat,
--- wr_adr => wr_adr_paged,
--- wr_en => wr_en,
--- clk => clk,
--- rst => rst
--- );
+ -- -- ram module
+ -- ram : ENTITY common_lib.common_dpram
+ -- GENERIC MAP (
+ -- g_dat_w => 2*g_dat_w,
+ -- g_adr_w => c_adr_w,
+ -- g_nof_words => c_nof_words
+ -- )
+ -- PORT MAP (
+ -- rd_dat => rd_dat,
+ -- rd_adr => rd_adr_paged,
+ -- rd_en => rd_en,
+ -- wr_dat => wr_dat,
+ -- wr_adr => wr_adr_paged,
+ -- wr_en => wr_en,
+ -- clk => clk,
+ -- rst => rst
+ -- );
ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_en,
- wr_adr => wr_adr_paged,
- wr_dat => wr_dat,
- rd_en => rd_en,
- rd_adr => rd_adr_paged,
- rd_dat => rd_dat
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_en,
+ wr_adr => wr_adr_paged,
+ wr_dat => wr_dat,
+ rd_en => rd_en,
+ rd_adr => rd_adr_paged,
+ rd_dat => rd_dat
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
index 10175d1095..4541b92d9c 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
architecture rtl of pft_lfsr is
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
index f873710685..8b723b4043 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
@@ -24,7 +24,7 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pft_lfsr is
port (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
index b1feb26ef2..a8ed2084c3 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
@@ -24,8 +24,8 @@
-- Remark: Copy of pft(pkg).vhd to avoid () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pft_pkg is
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
index 38d53ce352..06f9dd877c 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pft_reverse is
@@ -24,12 +24,12 @@ begin
-- Output signals.
i_rdaddr <= (others => '0');
i_rden <= '0';
- -- Internal signals.
+ -- Internal signals.
elsif rising_edge(clk) then
-- Output signals.
i_rdaddr <= nxt_rdaddr;
i_rden <= nxt_rden;
- -- Internal signals.
+ -- Internal signals.
end if;
end process;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
index c74f2d8e29..6cae2b1697 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_reverse is
generic (
@@ -74,12 +74,12 @@ begin
-- Output signals.
i_rdaddr <= (others => '0');
i_rden <= '0';
- -- Internal signals.
+ -- Internal signals.
elsif rising_edge(clk) then
-- Output signals.
i_rdaddr <= nxt_rdaddr;
i_rden <= nxt_rden;
- -- Internal signals.
+ -- Internal signals.
end if;
end process;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
index b5b97ee960..bc89044a83 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_separate is
@@ -170,73 +170,73 @@ begin
nxt_out_val <= rdval_dly(rdval_dly'high);
nxt_out_sync <= rdsync_dly(rdsync_dly'high);
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- add : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => add0'LENGTH,
--- g_in_b_w => add1'LENGTH,
--- g_out_c_w => add_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "ADD"
--- )
--- PORT MAP (
--- in_a => add0,
--- in_b => add1,
--- in_cry => '0',
--- out_c => add_out,
--- clk => clk
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- add : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => add0'LENGTH,
+ -- g_in_b_w => add1'LENGTH,
+ -- g_out_c_w => add_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "ADD"
+ -- )
+ -- PORT MAP (
+ -- in_a => add0,
+ -- in_b => add1,
+ -- in_cry => '0',
+ -- out_c => add_out,
+ -- clk => clk
+ -- );
add : entity common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => add0,
- in_b => add1,
- result => add_out
- );
-
--- sub : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => sub0'LENGTH,
--- g_in_b_w => sub1'LENGTH,
--- g_out_c_w => sub_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_a => sub0,
--- in_b => sub1,
--- in_cry => '1',
--- out_c => sub_out,
--- clk => clk
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => add0,
+ in_b => add1,
+ result => add_out
+ );
+
+ -- sub : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => sub0'LENGTH,
+ -- g_in_b_w => sub1'LENGTH,
+ -- g_out_c_w => sub_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_a => sub0,
+ -- in_b => sub1,
+ -- in_cry => '1',
+ -- out_c => sub_out,
+ -- clk => clk
+ -- );
sub : entity common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => sub0,
- in_b => sub1,
- result => sub_out
- );
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => sub0,
+ in_b => sub1,
+ result => sub_out
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
index 41325aa1fa..658060c9d4 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_separate is
generic (
@@ -218,72 +218,72 @@ begin
nxt_out_val <= rdval_dly(rdval_dly'high);
nxt_out_sync <= rdsync_dly(rdsync_dly'high);
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--- add : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => add0'LENGTH,
--- g_in_b_w => add1'LENGTH,
--- g_out_c_w => add_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "ADD"
--- )
--- PORT MAP (
--- in_a => add0,
--- in_b => add1,
--- in_cry => '0',
--- out_c => add_out,
--- clk => clk
--- );
+ -- add : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => add0'LENGTH,
+ -- g_in_b_w => add1'LENGTH,
+ -- g_out_c_w => add_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "ADD"
+ -- )
+ -- PORT MAP (
+ -- in_a => add0,
+ -- in_b => add1,
+ -- in_cry => '0',
+ -- out_c => add_out,
+ -- clk => clk
+ -- );
add : entity common_lib.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => add0,
- in_b => add1,
- result => add_out
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => add0,
+ in_b => add1,
+ result => add_out
+ );
--- sub : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => sub0'LENGTH,
--- g_in_b_w => sub1'LENGTH,
--- g_out_c_w => sub_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_a => sub0,
--- in_b => sub1,
--- in_cry => '1',
--- out_c => sub_out,
--- clk => clk
--- );
+ -- sub : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => sub0'LENGTH,
+ -- g_in_b_w => sub1'LENGTH,
+ -- g_out_c_w => sub_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_a => sub0,
+ -- in_b => sub1,
+ -- in_cry => '1',
+ -- out_c => sub_out,
+ -- clk => clk
+ -- );
sub : entity common_lib.common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => sub0,
- in_b => sub1,
- result => sub_out
- );
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => sub0,
+ in_b => sub1,
+ result => sub_out
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
index 6a4eb2c67a..d0c1d3ec7f 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library common_lib, pft2_lib;
-use common_lib.all;
+ use common_lib.all;
architecture str of pft_stage is
@@ -46,63 +46,63 @@ begin
gen_middle: if g_index > 0 generate
bf1 : entity pft2_lib.pft_bf
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2 : entity pft2_lib.pft_bf
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
tmult : entity pft2_lib.pft_tmult
- generic map (
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w,
- g_index => g_index
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- in_val => bf2_val,
- in_sync => bf2_sync,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w,
+ g_index => g_index
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ in_val => bf2_val,
+ in_sync => bf2_sync,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
gen_last: if g_index = 0 generate
@@ -113,62 +113,62 @@ begin
begin
bf1_fw : entity pft2_lib.pft_bf_fw
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2_fw : entity pft2_lib.pft_bf_fw
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
u_rnd : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
p_regs: process(clk,rst)
begin
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
index 80b92de2b0..1eadab6c6e 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
@@ -24,7 +24,7 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pft_stage is
@@ -44,7 +44,7 @@ entity pft_stage is
out_sync : out std_logic;
clk : in std_logic;
rst : in std_logic
- );
+ );
end pft_stage;
@@ -72,63 +72,63 @@ begin
gen_middle: if g_index > 0 generate
bf1 : entity work.pft_bf
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2 : entity work.pft_bf
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
tmult : entity work.pft_tmult
- generic map (
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w,
- g_index => g_index
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- in_val => bf2_val,
- in_sync => bf2_sync,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w,
+ g_index => g_index
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ in_val => bf2_val,
+ in_sync => bf2_sync,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
gen_last: if g_index = 0 generate
@@ -139,62 +139,62 @@ begin
begin
bf1_fw : entity work.pft_bf_fw
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2_fw : entity work.pft_bf_fw
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
u_rnd : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
p_regs: process(clk,rst)
begin
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
index e7243c4796..82c0d319fc 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
@@ -1,23 +1,23 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.all;
+ use pft2_lib.all;
architecture rtl of pft_switch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
@@ -76,13 +76,13 @@ begin
end process;
lfsr: entity pft2_lib.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
index 2932e0745d..cb0f186bf8 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
@@ -25,8 +25,8 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_switch is
generic (
@@ -52,17 +52,17 @@ end pft_switch;
architecture rtl of pft_switch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
@@ -121,13 +121,13 @@ begin
end process;
lfsr: entity work.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
index d77f34405f..8043cffcfb 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_mult_lib;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
architecture rtl of pft_tmult is
@@ -37,15 +37,17 @@ architecture rtl of pft_tmult is
constant c_coeff_w : natural := 16;
constant c_mult_out_w : natural := c_mult_in_w + c_coeff_w - 1;
- constant c_twid_rom : t_c_mem := (latency => 2,
- adr_w => c_adr_w,
- dat_w => 2 * c_coeff_w, -- complex
- nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_twid_rom : t_c_mem := (
+ latency => 2,
+ adr_w => c_adr_w,
+ dat_w => 2 * c_coeff_w, -- complex
+ nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
+ init_sl => '0'
+ );
constant c_twid_file : string :=
- "data/twiddle_" & natural'image(c_coeff_w)
- & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ "data/twiddle_" & natural'image(c_coeff_w)
+ & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
--CONSTANT c_twid_file : STRING :=
-- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
-- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
@@ -130,73 +132,73 @@ begin
out_sync <= reg_sync(0);
u_coeff : entity common_lib.common_rom
- generic map (
- g_ram => c_twid_rom,
- g_init_file => c_twid_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => adr,
- rd_dat => coeff_dat
- );
+ generic map (
+ g_ram => c_twid_rom,
+ g_init_file => c_twid_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => adr,
+ rd_dat => coeff_dat
+ );
u_rnd1 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_mult_in_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- out_re => mult_in_re,
- out_im => mult_in_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_mult_in_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ out_re => mult_in_re,
+ out_im => mult_in_im,
+ clk => clk
+ );
u_cmult : entity common_mult_lib.common_complex_mult
- generic map (
- g_variant => "IP",
- g_in_a_w => c_mult_in_w,
- g_in_b_w => c_coeff_w,
- g_out_p_w => c_mult_out_w,
- g_conjugate_b => false,
- g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
- g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
- g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
- g_pipeline_output => c_mult_pipeline_output -- >= 0
- )
- port map (
- in_ar => mult_in_re,
- in_ai => mult_in_im,
- in_br => coeff_re,
- in_bi => coeff_im,
- out_pr => mult_out_re,
- out_pi => mult_out_im,
- clk => clk
- );
+ generic map (
+ g_variant => "IP",
+ g_in_a_w => c_mult_in_w,
+ g_in_b_w => c_coeff_w,
+ g_out_p_w => c_mult_out_w,
+ g_conjugate_b => false,
+ g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
+ g_pipeline_output => c_mult_pipeline_output -- >= 0
+ )
+ port map (
+ in_ar => mult_in_re,
+ in_ai => mult_in_im,
+ in_br => coeff_re,
+ in_bi => coeff_im,
+ out_pr => mult_out_re,
+ out_pi => mult_out_im,
+ clk => clk
+ );
u_rnd2 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_mult_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => mult_out_re,
- in_im => mult_out_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_mult_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => mult_out_re,
+ in_im => mult_out_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
index fbe5a2b8f3..1a4a93fdc1 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
@@ -24,14 +24,14 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_mult_lib;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.pft_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.pft_pkg.all;
entity pft_tmult is
@@ -64,15 +64,17 @@ architecture rtl of pft_tmult is
constant c_coeff_w : natural := c_pft_twiddle_w;
constant c_mult_out_w : natural := c_mult_in_w + c_coeff_w - 1;
- constant c_twid_rom : t_c_mem := (latency => 2,
- adr_w => c_adr_w,
- dat_w => 2 * c_coeff_w, -- complex
- nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_twid_rom : t_c_mem := (
+ latency => 2,
+ adr_w => c_adr_w,
+ dat_w => 2 * c_coeff_w, -- complex
+ nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
+ init_sl => '0'
+ );
constant c_twid_file : string :=
- "data/twiddle_" & natural'image(c_coeff_w)
- & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ "data/twiddle_" & natural'image(c_coeff_w)
+ & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
--CONSTANT c_twid_file : STRING :=
-- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
-- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
@@ -157,73 +159,73 @@ begin
out_sync <= reg_sync(0);
u_coeff : entity common_lib.common_rom
- generic map (
- g_ram => c_twid_rom,
- g_init_file => c_twid_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => adr,
- rd_dat => coeff_dat
- );
+ generic map (
+ g_ram => c_twid_rom,
+ g_init_file => c_twid_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => adr,
+ rd_dat => coeff_dat
+ );
u_rnd1 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_mult_in_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- out_re => mult_in_re,
- out_im => mult_in_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_mult_in_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ out_re => mult_in_re,
+ out_im => mult_in_im,
+ clk => clk
+ );
u_cmult : entity common_mult_lib.common_complex_mult
- generic map (
- g_variant => "IP",
- g_in_a_w => c_mult_in_w,
- g_in_b_w => c_coeff_w,
- g_out_p_w => c_mult_out_w,
- g_conjugate_b => false,
- g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
- g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
- g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
- g_pipeline_output => c_mult_pipeline_output -- >= 0
- )
- port map (
- in_ar => mult_in_re,
- in_ai => mult_in_im,
- in_br => coeff_re,
- in_bi => coeff_im,
- out_pr => mult_out_re,
- out_pi => mult_out_im,
- clk => clk
- );
+ generic map (
+ g_variant => "IP",
+ g_in_a_w => c_mult_in_w,
+ g_in_b_w => c_coeff_w,
+ g_out_p_w => c_mult_out_w,
+ g_conjugate_b => false,
+ g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
+ g_pipeline_output => c_mult_pipeline_output -- >= 0
+ )
+ port map (
+ in_ar => mult_in_re,
+ in_ai => mult_in_im,
+ in_br => coeff_re,
+ in_bi => coeff_im,
+ out_pr => mult_out_re,
+ out_pi => mult_out_im,
+ clk => clk
+ );
u_rnd2 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_mult_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => mult_out_re,
- in_im => mult_out_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_mult_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => mult_out_re,
+ in_im => mult_out_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
index 7eb587edd0..8281741685 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
@@ -1,6 +1,6 @@
library IEEE, common_lib, pft2_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
architecture str of pft_top is
@@ -37,24 +37,24 @@ begin
end process;
u_pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_mode => g_mode
- )
- port map (
- in_re => reg_in_re,
- in_im => reg_in_im,
- in_val => reg_in_val,
- in_sync => reg_in_sync,
- switch_en => switch_en,
- out_re => d_out_re,
- out_im => d_out_im,
- out_val => d_out_val,
- out_sync => d_out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_mode => g_mode
+ )
+ port map (
+ in_re => reg_in_re,
+ in_im => reg_in_im,
+ in_val => reg_in_val,
+ in_sync => reg_in_sync,
+ switch_en => switch_en,
+ out_re => d_out_re,
+ out_im => d_out_im,
+ out_val => d_out_val,
+ out_sync => d_out_sync,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
index cf7f913ddb..01e61cd346 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.pft_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pft_top is
generic (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
index 896495e46a..cd507cdea1 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
@@ -1,24 +1,24 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.all;
+ use pft2_lib.all;
architecture rtl of pft_unswitch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
@@ -66,19 +66,19 @@ begin
nxt_out_im <= in_im;
if ((cnt(0) = '0' and cnt(cnt'high) = lfsr_bit1)
or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
- nxt_out_re <= std_logic_vector(-signed(in_re));
- nxt_out_im <= std_logic_vector(-signed(in_im));
+ nxt_out_re <= std_logic_vector(-signed(in_re));
+ nxt_out_im <= std_logic_vector(-signed(in_im));
end if;
end process;
lfsr: entity pft2_lib.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
index 81add2c981..33749dd011 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_unswitch is
@@ -52,18 +52,18 @@ end pft_unswitch;
architecture rtl of pft_unswitch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
@@ -111,19 +111,19 @@ begin
nxt_out_im <= in_im;
if ((cnt(0) = '0' and cnt(cnt'high) = lfsr_bit1)
or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
- nxt_out_re <= std_logic_vector(-signed(in_re));
- nxt_out_im <= std_logic_vector(-signed(in_im));
+ nxt_out_re <= std_logic_vector(-signed(in_re));
+ nxt_out_im <= std_logic_vector(-signed(in_im));
end if;
end process;
lfsr: entity work.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
index 3f6757eda4..72b7516383 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
@@ -1,7 +1,7 @@
library ieee, pfs_lib, pft2_lib, tst_lib;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use pft2_lib.pft_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use pft2_lib.pft_pkg.all;
entity tb_pft is
generic (
@@ -54,65 +54,65 @@ begin
in_dat: entity tst_lib.tst_input
- generic map (
- g_file_name => c_pft_in_file,
- g_data_width => g_in_w
- )
- port map (
- clk => clk,
- rst => rst,
- en => '1',
- out_dat1 => in_x,
- out_dat2 => in_y,
- out_val => open -- in_val
- );
+ generic map (
+ g_file_name => c_pft_in_file,
+ g_data_width => g_in_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => '1',
+ out_dat1 => in_x,
+ out_dat2 => in_y,
+ out_val => open -- in_val
+ );
in_val <= val;
in_sync <= '0';
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => 2**g_fft_size_w, -- 2*g_nof_subbands,
- g_nof_taps => 2**g_fft_size_w * 16, -- 2*16*g_nof_subbands,
- g_in_dat_w => g_in_w,
- g_out_dat_w => g_pfs_w,
- g_coef_dat_w => g_pfs_coef_w
- )
- port map (
- in_dat_x => in_x,
- in_dat_y => in_y,
- in_val => in_val,
- in_sync => in_sync,
- out_dat_x => pfs_x,
- out_dat_y => pfs_y,
- out_val => pfs_val,
- out_sync => pfs_sync,
- clk => clk,
- rst => rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => 2**g_fft_size_w, -- 2*g_nof_subbands,
+ g_nof_taps => 2**g_fft_size_w * 16, -- 2*16*g_nof_subbands,
+ g_in_dat_w => g_in_w,
+ g_out_dat_w => g_pfs_w,
+ g_coef_dat_w => g_pfs_coef_w
+ )
+ port map (
+ in_dat_x => in_x,
+ in_dat_y => in_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_dat_x => pfs_x,
+ out_dat_y => pfs_y,
+ out_val => pfs_val,
+ out_sync => pfs_sync,
+ clk => clk,
+ rst => rst,
+ restart => '0'
+ );
pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_pfs_w,
- g_out_dat_w => g_out_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => pfs_x,
- in_im => pfs_y,
- in_val => pfs_val,
- in_sync => pfs_sync,
- switch_en => '1',
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_pfs_w,
+ g_out_dat_w => g_out_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => pfs_x,
+ in_im => pfs_y,
+ in_val => pfs_val,
+ in_sync => pfs_sync,
+ switch_en => '1',
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
-- out_dat: ENTITY tst_lib.tst_output
-- GENERIC MAP (
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
index 3fbd80e15a..7830122bf9 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
@@ -32,11 +32,11 @@
-- - The tb works OK for all three PFT modes.
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.pft_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.pft_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_pft2 is
generic (
@@ -87,7 +87,7 @@ entity tb_pft2 is
--g_name_y : STRING := "u_noise";
g_repeat : natural := 2 -- minimal 2 due to PFT latency
- --g_repeat : NATURAL := 10 -- > c_nof_block_per_sync to view multiple in_sync and out_sync intervals
+ --g_repeat : NATURAL := 10 -- > c_nof_block_per_sync to view multiple in_sync and out_sync intervals
);
end tb_pft2;
@@ -226,7 +226,7 @@ architecture tb of tb_pft2 is
-----------------------------------------------------------------------------
-- PFT_MODE_BITREV
- function func_bitrev(n, w : in natural) return natural is
+ function func_bitrev (n, w : in natural) return natural is
variable un : unsigned(w - 1 downto 0);
variable ur : unsigned(w - 1 downto 0);
begin
@@ -237,9 +237,10 @@ architecture tb of tb_pft2 is
return to_integer(ur);
end func_bitrev;
- procedure proc_fft_bitrev(en : in std_logic;
- ref : in t_ref_dat;
- signal sr : out t_ref_fft_dat) is
+ procedure proc_fft_bitrev (
+ en : in std_logic;
+ ref : in t_ref_dat;
+ signal sr : out t_ref_fft_dat) is
constant N : natural := c_fft_size;
constant w : natural := c_fft_size_w;
variable r : natural;
@@ -253,9 +254,10 @@ architecture tb of tb_pft2 is
end proc_fft_bitrev;
-- PFT_MODE_COMPLEX
- procedure proc_fft_complex(en : in std_logic;
- ref : in t_ref_dat;
- signal sr : out t_ref_fft_dat) is
+ procedure proc_fft_complex (
+ en : in std_logic;
+ ref : in t_ref_dat;
+ signal sr : out t_ref_fft_dat) is
constant N : natural := c_fft_size;
begin
if en = '1' then
@@ -271,10 +273,11 @@ architecture tb of tb_pft2 is
-- . PFT seperate does not divide by 2 in Xa(m) = [X*(N-m) + X(m)]/2, Xb(m)=j[X*(N-m) - X(m)]/2
-- . PFT seperate result for m=N is same as for m=0
-- . PFT seperate puts real result for m=N/2 in imag of m=0
- procedure proc_fft_real2_im(en : in std_logic;
- re : in t_ref_dat;
- im : in t_ref_dat;
- signal sr : out t_ref_real2_dat) is
+ procedure proc_fft_real2_im (
+ en : in std_logic;
+ re : in t_ref_dat;
+ im : in t_ref_dat;
+ signal sr : out t_ref_real2_dat) is
constant N : natural := c_fft_size;
variable lo : integer;
variable hi : integer;
@@ -289,9 +292,10 @@ architecture tb of tb_pft2 is
end if;
end proc_fft_real2_im;
- procedure proc_fft_real2_re(en : in std_logic;
- re : in t_ref_dat;
- signal sr : out t_ref_real2_dat) is
+ procedure proc_fft_real2_re (
+ en : in std_logic;
+ re : in t_ref_dat;
+ signal sr : out t_ref_real2_dat) is
constant N : natural := c_fft_size;
variable lo : integer;
variable hi : integer;
@@ -332,36 +336,36 @@ begin
-----------------------------------------------------------------------------
u_in_x: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_in_x,
- g_file_repeat => g_repeat,
- g_nof_data => 1,
- g_data_width => c_in_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_en,
- out_dat => in_dat_x,
- out_val => in_val_x
- );
+ generic map (
+ g_file_name => c_file_pft_in_x,
+ g_file_repeat => g_repeat,
+ g_nof_data => 1,
+ g_data_width => c_in_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_en,
+ out_dat => in_dat_x,
+ out_val => in_val_x
+ );
u_in_y: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_in_y,
- g_file_repeat => g_repeat,
- g_nof_data => 1,
- g_data_width => c_in_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_en,
- out_dat => in_dat_y,
- out_val => in_val_y
- );
+ generic map (
+ g_file_name => c_file_pft_in_y,
+ g_file_repeat => g_repeat,
+ g_nof_data => 1,
+ g_data_width => c_in_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_en,
+ out_dat => in_dat_y,
+ out_val => in_val_y
+ );
-----------------------------------------------------------------------------
@@ -369,68 +373,68 @@ begin
-----------------------------------------------------------------------------
u_ref_x_re: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_x_re,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_x_re,
- out_val => ref_val_x_re
- );
+ generic map (
+ g_file_name => c_file_pft_ref_x_re,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_x_re,
+ out_val => ref_val_x_re
+ );
u_ref_x_im: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_x_im,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_x_im,
- out_val => ref_val_x_im
- );
+ generic map (
+ g_file_name => c_file_pft_ref_x_im,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_x_im,
+ out_val => ref_val_x_im
+ );
u_ref_y_re: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_y_re,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_y_re,
- out_val => ref_val_y_re
- );
+ generic map (
+ g_file_name => c_file_pft_ref_y_re,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_y_re,
+ out_val => ref_val_y_re
+ );
u_ref_y_im: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_y_im,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_y_im,
- out_val => ref_val_y_im
- );
+ generic map (
+ g_file_name => c_file_pft_ref_y_im,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_y_im,
+ out_val => ref_val_y_im
+ );
p_ref_reg : process(clk)
begin
@@ -506,9 +510,9 @@ begin
begin
if diff_rdy = '1' then
if diff_max_fft_re <= c_diff_max then report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is OK" severity NOTE;
- else report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
+ else report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
if diff_max_fft_im <= c_diff_max then report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is OK" severity NOTE;
- else report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
+ else report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
end if;
end process;
end generate;
@@ -538,13 +542,13 @@ begin
begin
if diff_rdy = '1' then
if diff_max_x_re <= c_diff_max then report "FFT X real output for " & g_name_x & " is OK" severity NOTE;
- else report "FFT X real output for " & g_name_x & " is wrong" severity ERROR; end if;
+ else report "FFT X real output for " & g_name_x & " is wrong" severity ERROR; end if;
if diff_max_x_im <= c_diff_max then report "FFT X imag output for " & g_name_x & " is OK" severity NOTE;
- else report "FFT X imag output for " & g_name_x & " is wrong" severity ERROR; end if;
+ else report "FFT X imag output for " & g_name_x & " is wrong" severity ERROR; end if;
if diff_max_y_re <= c_diff_max then report "FFT Y real output for " & g_name_y & " is OK" severity NOTE;
- else report "FFT Y real output for " & g_name_y & " is wrong" severity ERROR; end if;
+ else report "FFT Y real output for " & g_name_y & " is wrong" severity ERROR; end if;
if diff_max_y_im <= c_diff_max then report "FFT Y imag output for " & g_name_y & " is OK" severity NOTE;
- else report "FFT Y imag output for " & g_name_y & " is wrong" severity ERROR; end if;
+ else report "FFT Y imag output for " & g_name_y & " is wrong" severity ERROR; end if;
end if;
end process;
end generate;
@@ -557,26 +561,26 @@ begin
-----------------------------------------------------------------------------
u_pft : entity work.pft
- generic map (
- g_fft_size_w => c_fft_size_w,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w,
- g_stage_dat_w => g_stage_dat_w,
- g_mode => g_pft_mode
- )
- port map (
- in_re => in_dat_x,
- in_im => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- switch_en => g_switch_en,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => c_fft_size_w,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w,
+ g_stage_dat_w => g_stage_dat_w,
+ g_mode => g_pft_mode
+ )
+ port map (
+ in_re => in_dat_x,
+ in_im => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ switch_en => g_switch_en,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
p_pft_reg : process(clk)
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
index 7e4f250ff4..737f113e99 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
@@ -1,10 +1,10 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib,common_lib;
-use pft2_lib.pft_pkg.all;
-use common_lib.common_pkg.all;
+ use pft2_lib.pft_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_pft is
@@ -50,39 +50,39 @@ begin
cnt <= (others => '0');
elsif rising_edge(clk) then
cnt <= nxt_cnt;
- end if;
+ end if;
end process;
nxt_cnt <= std_logic_vector(unsigned(cnt) + 1) when in_sync = '0' else (others => '0');
pft : entity work.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => in_x,
- in_im => in_y,
- in_val => in_val,
- in_sync => in_sync,
- switch_en => switch_en,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => in_x,
+ in_im => in_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ switch_en => switch_en,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
clk <= not(clk) after clk_period / 2;
rst <= '0' after rst_period;
switch_en <= '0';
--- in_sync <= '1' WHEN UNSIGNED(cnt)=g_pps_ps-1 ELSE '0';
--- in_val <= '1' WHEN UNSIGNED(cnt)=732;
+ -- in_sync <= '1' WHEN UNSIGNED(cnt)=g_pps_ps-1 ELSE '0';
+ -- in_val <= '1' WHEN UNSIGNED(cnt)=732;
input_ctrl : process
begin
@@ -97,7 +97,7 @@ begin
-- val
wait until unsigned(cnt) = 1024;
--- WAIT UNTIL UNSIGNED(cnt)=731;
+ -- WAIT UNTIL UNSIGNED(cnt)=731;
in_val <= '1';
for J in 1 to 10 loop
@@ -116,28 +116,28 @@ begin
end process;
--- -----------------------------------------------------------------------------
--- --
--- -- X = Y is sliding impulse
--- --
--- -----------------------------------------------------------------------------
--- in_gen: PROCESS
--- BEGIN
--- FOR I IN 0 TO g_fft_size-1 LOOP -- Slide impulse
--- FOR J IN 1 TO 1 LOOP -- Repeat impulse
--- IF in_val='1' THEN
--- WAIT UNTIL UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=I;
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w));
--- WAIT FOR clk_period;
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
--- WAIT FOR clk_period;
--- ELSE
--- WAIT UNTIL in_val='1';
--- END IF;
--- END LOOP;
--- END LOOP;
--- END PROCESS;
--- in_y <= in_x;
+ -- -----------------------------------------------------------------------------
+ -- --
+ -- -- X = Y is sliding impulse
+ -- --
+ -- -----------------------------------------------------------------------------
+ -- in_gen: PROCESS
+ -- BEGIN
+ -- FOR I IN 0 TO g_fft_size-1 LOOP -- Slide impulse
+ -- FOR J IN 1 TO 1 LOOP -- Repeat impulse
+ -- IF in_val='1' THEN
+ -- WAIT UNTIL UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=I;
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w));
+ -- WAIT FOR clk_period;
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
+ -- WAIT FOR clk_period;
+ -- ELSE
+ -- WAIT UNTIL in_val='1';
+ -- END IF;
+ -- END LOOP;
+ -- END LOOP;
+ -- END PROCESS;
+ -- in_y <= in_x;
-----------------------------------------------------------------------------
@@ -153,8 +153,8 @@ begin
elsif rising_edge(clk) then
if cnt(0) = '1' then
if in_val = '1' then
- in_x <= std_logic_vector(-signed(in_x));
- in_y <= std_logic_vector(signed(in_y));
+ in_x <= std_logic_vector(-signed(in_x));
+ in_y <= std_logic_vector(signed(in_y));
end if;
end if;
end if;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
index 541de50963..b1b85e9359 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
@@ -25,11 +25,11 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_pft2 is
end tb_tb_pft2;
-use work.pft_pkg.all;
+ use work.pft_pkg.all;
architecture tb of tb_tb_pft2 is
constant c_sw : std_logic := '1'; -- default for g_switch_en
@@ -127,6 +127,6 @@ begin
u_17_block_117_u_noise : entity work.tb_pft2 generic map(c_sw, 17, PFT_MODE_REAL2, "block_117", "u_noise", 2);
u_18_block_117_u_noise : entity work.tb_pft2 generic map(c_sw, 18, PFT_MODE_REAL2, "block_117", "u_noise", 2);
u_19_block_117_u_noise : entity work.tb_pft2 generic map(c_sw, 19, PFT_MODE_REAL2, "block_117", "u_noise", 2);
- -- . for g_stage_dat_w > 20 tb result is still OK, but diff_max_* does not reduce further
+-- . for g_stage_dat_w > 20 tb result is still OK, but diff_max_* does not reduce further
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
index 824dd0c1b3..12e7f6cd56 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_6ch_200MHz is
generic (
@@ -76,7 +76,7 @@ entity lofar2_unb2b_adc_6ch_200MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -113,52 +113,52 @@ begin
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_jesd_freq => g_jesd_freq,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_jesd_freq => g_jesd_freq,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
index 9a73f68341..f240dc05dd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -29,11 +29,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_6ch_200MHz is
end tb_lofar2_unb2b_adc_6ch_200MHz;
@@ -111,48 +111,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_6ch_200MHz : entity work.lofar2_unb2b_adc_6ch_200MHz
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index bb69c74548..89139da32f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_full is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2b_adc_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -112,51 +112,51 @@ begin
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
index 09e5939db9..75eac2a6bb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
@@ -30,11 +30,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_full is
end tb_lofar2_unb2b_adc_full;
@@ -112,48 +112,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_full : entity work.lofar2_unb2b_adc_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 8c022088a3..cb1cf5d5a5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -27,13 +27,13 @@
-- Contains complete AIT input stage with 1 ADC stream
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_one_node is
generic (
@@ -111,51 +111,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
index 4986bce1d0..5075022f26 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
@@ -29,11 +29,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_one_node is
end tb_lofar2_unb2b_adc_one_node;
@@ -111,48 +111,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_one_node : entity work.lofar2_unb2b_adc_one_node
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index 81e7907992..0e4ffee1c2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -27,15 +27,15 @@
-- Use revisions to select one_node or full versions
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.lofar2_unb2b_adc_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.lofar2_unb2b_adc_pkg.all;
entity lofar2_unb2b_adc is
generic (
@@ -82,9 +82,9 @@ entity lofar2_unb2b_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -234,209 +234,209 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => c_mem_mosi_rst,
- ram_scrap_miso => open,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => c_mem_mosi_rst,
+ ram_scrap_miso => open,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_adc
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso
+ );
-----------------------------------------------------------------------------
@@ -445,77 +445,77 @@ begin
-----------------------------------------------------------------------------
u_ait: entity work.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_nof_streams,
- g_jesd_freq => g_jesd_freq,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => alt_sosi_arr
- );
-
- u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_jesd_freq => g_jesd_freq,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => alt_sosi_arr
+ );
+
+ u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
index 00c4a2d426..571f68e6e2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package lofar2_unb2b_adc_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -41,7 +41,7 @@ package lofar2_unb2b_adc_pkg is
constant c_full : t_lofar2_unb2b_adc_config := ( 12, 2, 12 );
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_adc_config;
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_adc_config;
end lofar2_unb2b_adc_pkg;
@@ -49,7 +49,7 @@ end lofar2_unb2b_adc_pkg;
package body lofar2_unb2b_adc_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_adc_config is
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_adc_config is
begin
if g_design_name = "lofar2_unb2b_adc_one_node" then return c_one_node;
elsif g_design_name = "lofar2_unb2b_adc_full" then return c_full;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index 3e138949c3..f57baed52e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_adc_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_adc_pkg.all;
entity mmm_lofar2_unb2b_adc is
@@ -158,62 +158,62 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -229,249 +229,249 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2b_adc
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- jesd204b_reset_export => OPEN,
- jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(11 downto 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
-
- pio_jesd_ctrl_reset_export => OPEN,
- pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(0 downto 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(7 downto 0),
- reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- waveform generators (multiplexed)
- reg_wg_clk_export => OPEN,
- reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_mosi.address(5 downto 0),
- reg_wg_read_export => reg_wg_mosi.rd,
- reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w - 1 downto 0),
- reg_wg_write_export => reg_wg_mosi.wr,
- reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_wg_clk_export => OPEN,
- ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_mosi.address(13 downto 0),
- ram_wg_read_export => ram_wg_mosi.rd,
- ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w - 1 downto 0),
- ram_wg_write_export => ram_wg_mosi.wr,
- ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_dp_shiftram_clk_export => OPEN,
- reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(2 downto 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_source_clk_export => OPEN,
- reg_bsn_source_reset_export => OPEN,
- reg_bsn_source_address_export => reg_bsn_source_mosi.address(1 downto 0),
- reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
- reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
- reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_scheduler_clk_export => OPEN,
- reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(0 downto 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- ram_diag_data_buffer_bsn_clk_export => OPEN,
- ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0), -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
- ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_bsn_reset_export => OPEN,
- reg_diag_data_buffer_bsn_clk_export => OPEN,
- reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(12 - 1 downto 0),
- reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- ram_aduh_monitor_clk_export => OPEN,
- ram_aduh_monitor_reset_export => OPEN,
- ram_aduh_monitor_address_export => ram_aduh_monitor_mosi.address(12 - 1 downto 0),
- ram_aduh_monitor_write_export => ram_aduh_monitor_mosi.wr,
- ram_aduh_monitor_writedata_export => ram_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
- ram_aduh_monitor_read_export => ram_aduh_monitor_mosi.rd,
- ram_aduh_monitor_readdata_export => ram_aduh_monitor_miso.rddata(c_word_w - 1 downto 0),
-
- reg_aduh_monitor_reset_export => OPEN,
- reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(6 - 1 downto 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w - 1 downto 0)
-
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ jesd204b_reset_export => OPEN,
+ jesd204b_clk_export => OPEN,
+ jesd204b_address_export => jesd204b_mosi.address(11 downto 0),
+ jesd204b_write_export => jesd204b_mosi.wr,
+ jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
+ jesd204b_read_export => jesd204b_mosi.rd,
+ jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_jesd_ctrl_reset_export => OPEN,
+ pio_jesd_ctrl_clk_export => OPEN,
+ pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(0 downto 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(7 downto 0),
+ reg_bsn_monitor_input_clk_export => OPEN,
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_input_reset_export => OPEN,
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- waveform generators (multiplexed)
+ reg_wg_clk_export => OPEN,
+ reg_wg_reset_export => OPEN,
+ reg_wg_address_export => reg_wg_mosi.address(5 downto 0),
+ reg_wg_read_export => reg_wg_mosi.rd,
+ reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w - 1 downto 0),
+ reg_wg_write_export => reg_wg_mosi.wr,
+ reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_wg_clk_export => OPEN,
+ ram_wg_reset_export => OPEN,
+ ram_wg_address_export => ram_wg_mosi.address(13 downto 0),
+ ram_wg_read_export => ram_wg_mosi.rd,
+ ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w - 1 downto 0),
+ ram_wg_write_export => ram_wg_mosi.wr,
+ ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_dp_shiftram_clk_export => OPEN,
+ reg_dp_shiftram_reset_export => OPEN,
+ reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(2 downto 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_source_clk_export => OPEN,
+ reg_bsn_source_reset_export => OPEN,
+ reg_bsn_source_address_export => reg_bsn_source_mosi.address(1 downto 0),
+ reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
+ reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
+ reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_scheduler_clk_export => OPEN,
+ reg_bsn_scheduler_reset_export => OPEN,
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(0 downto 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ ram_diag_data_buffer_bsn_clk_export => OPEN,
+ ram_diag_data_buffer_bsn_reset_export => OPEN,
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0), -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_bsn_reset_export => OPEN,
+ reg_diag_data_buffer_bsn_clk_export => OPEN,
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(12 - 1 downto 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_aduh_monitor_clk_export => OPEN,
+ ram_aduh_monitor_reset_export => OPEN,
+ ram_aduh_monitor_address_export => ram_aduh_monitor_mosi.address(12 - 1 downto 0),
+ ram_aduh_monitor_write_export => ram_aduh_monitor_mosi.wr,
+ ram_aduh_monitor_writedata_export => ram_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_aduh_monitor_read_export => ram_aduh_monitor_mosi.rd,
+ ram_aduh_monitor_readdata_export => ram_aduh_monitor_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_aduh_monitor_reset_export => OPEN,
+ reg_aduh_monitor_clk_export => OPEN,
+ reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(6 - 1 downto 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w - 1 downto 0)
+
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 594eb65cf5..3b5a8a4226 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -27,16 +27,16 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, unb2b_board_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.lofar2_unb2b_adc_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.lofar2_unb2b_adc_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity node_adc_input_and_timing is
generic (
@@ -122,11 +122,13 @@ architecture str of node_adc_input_and_timing is
constant c_nof_streams_jesd204b : natural := 12; -- IP is set up for 12 streams
- constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0'
+ );
-- Waveform Generator
constant c_wg_buf_directory : string := "data/";
@@ -191,35 +193,35 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_jesd204b,
- g_nof_sync_n => g_nof_sync_n,
- g_jesd_freq => g_jesd_freq
- )
- port map(
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_internal,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b - 1 downto 0)
- );
+ generic map(
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_nof_sync_n => g_nof_sync_n,
+ g_jesd_freq => g_jesd_freq
+ )
+ port map(
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b - 1 downto 0)
+ );
-----------------------------------------------------------------------------
@@ -239,75 +241,75 @@ begin
u_dp_shiftram : entity dp_lib.dp_shiftram
- generic map (
- g_nof_streams => c_nof_streams_jesd204b,
- g_nof_words => c_dp_shiftram_nof_samples,
- g_data_w => c_data_w,
- g_use_sync_in => true
- )
- port map (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
+ generic map (
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_nof_words => c_dp_shiftram_nof_samples,
+ g_data_w => c_data_w,
+ g_use_sync_in => true
+ )
+ port map (
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
- sync_in => bs_sosi.sync,
+ sync_in => bs_sosi.sync,
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => dp_shiftram_snk_in_arr,
+ snk_in_arr => dp_shiftram_snk_in_arr,
- src_out_arr => ant_sosi_arr
- );
+ src_out_arr => ant_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source : entity dp_lib.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_mosi,
+ reg_miso => reg_bsn_source_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
-----------------------------------------------------------------------------
@@ -315,39 +317,39 @@ begin
-----------------------------------------------------------------------------
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi,
- reg_miso => reg_wg_miso,
-
- buf_mosi => ram_wg_mosi,
- buf_miso => ram_wg_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_mosi,
+ reg_miso => reg_wg_miso,
+
+ buf_mosi => ram_wg_mosi,
+ buf_miso => ram_wg_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
-----------------------------------------------------------------------------
@@ -393,82 +395,82 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => g_bsn_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => g_bsn_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-----------------------------------------------------------------------------
u_aduh_monitor : entity aduh_lib.mms_aduh_monitor_arr
- generic map (
- g_cross_clock_domain => true,
- g_nof_streams => g_nof_streams,
- g_symbol_w => c_data_w, -- TBD 16?
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
- g_buffer_nof_symbols => g_aduh_buffer_nof_symbols, -- default 512, larger for full design
- g_buffer_use_sync => true -- True to capture all streams synchronously
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_aduh_monitor_miso,
- buf_mosi => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
- buf_miso => ram_aduh_monitor_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
-
- in_sosi_arr => st_sosi_arr
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_nof_streams => g_nof_streams,
+ g_symbol_w => c_data_w, -- TBD 16?
+ g_nof_symbols_per_data => 1, -- Wideband factor is 1
+ g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
+ g_buffer_nof_symbols => g_aduh_buffer_nof_symbols, -- default 512, larger for full design
+ g_buffer_use_sync => true -- True to capture all streams synchronously
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+ reg_miso => reg_aduh_monitor_miso,
+ buf_mosi => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
+ buf_miso => ram_aduh_monitor_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+
+ in_sosi_arr => st_sosi_arr
+ );
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
+ -----------------------------------------------------------------------------
+ -- Diagnostic Data Buffer
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
@@ -500,24 +502,24 @@ begin
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg,
- in_reg => mm_jesd_ctrl_reg
- );
+ generic map (
+ g_reg => c_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg,
+ in_reg => mm_jesd_ctrl_reg
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index 8bc5901363..7e468bac45 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -21,7 +21,7 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_adc_pkg is
@@ -30,213 +30,213 @@ package qsys_lofar2_unb2b_adc_pkg is
-- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_adc is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_adc;
+ component qsys_lofar2_unb2b_adc is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_adc;
end qsys_lofar2_unb2b_adc_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
index 1e1167a1cd..e1bceff11c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
@@ -31,11 +31,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc is
end tb_lofar2_unb2b_adc;
@@ -113,50 +113,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : entity work.lofar2_unb2b_adc
- generic map (
- g_design_name => "lofar2_unb2b_adc_one_node",
- g_design_note => "Lofar2 adc with one node",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 061f75cf7b..7240c9949f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -31,12 +31,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, ip_arria10_e1sg_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.all;
entity tb_lofar2_unb2b_adc_multichannel is
end tb_lofar2_unb2b_adc_multichannel;
@@ -60,30 +60,34 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
-- Transport delays
type t_time_arr is array (0 to 11) of time;
constant c_nof_jesd204b_tx : natural := 3; -- number of jesd204b input sources to instantiate
- constant c_delay_data_arr : t_time_arr := (4000 ps,
- 5000 ps,
- 6000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps) ; -- transport delays tx to rx data
- constant c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
- 5000 ps,
- 6000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps) ; -- transport delays clock source to adc(tx)
+ constant c_delay_data_arr : t_time_arr := (
+ 4000 ps,
+ 5000 ps,
+ 6000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps
+ ) ; -- transport delays tx to rx data
+ constant c_delay_sysreftoadc_arr : t_time_arr := (
+ 4000 ps,
+ 5000 ps,
+ 6000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps
+ ) ; -- transport delays clock source to adc(tx)
constant c_delay_sysreftofpga : time := 10200 ps;
@@ -187,50 +191,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : entity work.lofar2_unb2b_adc
- generic map (
- g_design_name => "lofar2_unb2b_adc_one_node",
- g_design_note => "Lofar2 adc with one node",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => bck_rx,
- JESD204B_REFCLK => jesd204b_sampclk_fpga,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref_fpga,
- JESD204B_SYNC_N => jesd204b_sync_n_fpga
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => bck_rx,
+ JESD204B_REFCLK => jesd204b_sampclk_fpga,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref_fpga,
+ JESD204B_SYNC_N => jesd204b_sync_n_fpga
+ );
-----------------------------------------------------------------------------
@@ -240,7 +244,7 @@ begin
gen_transport : for i in 0 to c_nof_jesd204b_tx - 1 generate
jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i);
jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
--- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
+ -- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
jesd204b_sync_n_adc(i) <= transport jesd204b_sync_n_fpga(i) after c_delay_data_arr(i);
end generate;
@@ -312,40 +316,40 @@ begin
variable even_sample : boolean := true;
begin
if mm_rst = '1' then
- jesd204b_tx_link_data_arr(i) <= (others => '0');
- jesd204b_tx_link_valid(i) <= '0';
- txlink_clk(i) <= '0';
- data := 0;
- even_sample := true;
- else
- if rising_edge(jesd204b_sampclk_adc(i)) then
- txlink_clk(i) <= not txlink_clk(i);
- jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
- jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
- if (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') then
- data := 1000;
- elsif (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') then
- data := -1000;
- else
- data := 0;
- end if;
-
- -- Frame the data to 32 bits at half the rate
- if(jesd204b_tx_link_ready(i) = '0') then
- even_sample := true;
- else
- even_sample := not even_sample;
- end if;
- if (even_sample = true) then
- jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '0';
- else
- jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '1';
- end if;
-
- end if;
- end if;
+ jesd204b_tx_link_data_arr(i) <= (others => '0');
+ jesd204b_tx_link_valid(i) <= '0';
+ txlink_clk(i) <= '0';
+ data := 0;
+ even_sample := true;
+ else
+ if rising_edge(jesd204b_sampclk_adc(i)) then
+ txlink_clk(i) <= not txlink_clk(i);
+ jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+ jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+ if (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') then
+ data := 1000;
+ elsif (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') then
+ data := -1000;
+ else
+ data := 0;
+ end if;
+
+ -- Frame the data to 32 bits at half the rate
+ if(jesd204b_tx_link_ready(i) = '0') then
+ even_sample := true;
+ else
+ even_sample := not even_sample;
+ end if;
+ if (even_sample = true) then
+ jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
+ jesd204b_tx_link_valid(i) <= '0';
+ else
+ jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
+ jesd204b_tx_link_valid(i) <= '1';
+ end if;
+
+ end if;
+ end if;
end process;
@@ -396,23 +400,23 @@ begin
variable count : natural := 0;
begin
if mm_rst = '1' then
- jesd204b_sysref <= '0';
- count := 0;
- else
- if rising_edge(jesd204b_sampclk) then
+ jesd204b_sysref <= '0';
+ count := 0;
+ else
+ if rising_edge(jesd204b_sampclk) then
if (count = c_sysref_period - 1) then
- count := 0;
- else
- count := count + 1;
- end if;
-
- if count > c_sysref_period - 8 then
- jesd204b_sysref <= '1';
- else
- jesd204b_sysref <= '0';
- end if;
- end if;
- end if;
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+
+ if count > c_sysref_period - 8 then
+ jesd204b_sysref <= '1';
+ else
+ jesd204b_sysref <= '0';
+ end if;
+ end if;
+ end if;
end process;
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
index f3791a4aef..e8978913cf 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
@@ -47,16 +47,16 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_lofar2_unb2b_adc_wg is
end tb_lofar2_unb2b_adc_wg;
@@ -77,7 +77,7 @@ architecture tb of tb_lofar2_unb2b_adc_wg is
constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
constant c_cable_delay : time := 12 ns
-;
+ ;
constant c_sample_freq : natural := c_unb2b_board_ext_clk_freq_200M / 10**6; -- 200 MSps
constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps;
@@ -183,50 +183,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : entity work.lofar2_unb2b_adc
- generic map (
- g_design_name => "lofar2_unb2b_adc_one_node",
- g_design_note => "Lofar2 adc with one node",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index cd8df535cd..e3881aa9ee 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_beamformer_one_node is
generic (
@@ -82,7 +82,7 @@ entity lofar2_unb2b_beamformer_one_node is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -119,58 +119,58 @@ begin
u_revision : entity lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index 1fd5cbce8c..eb4083666a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_beamformer_one_node_256MHz is
generic (
@@ -82,7 +82,7 @@ entity lofar2_unb2b_beamformer_one_node_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -119,58 +119,58 @@ begin
u_revision : entity lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 45b42b43b0..ac4852f4de 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -27,19 +27,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_beamformer_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_beamformer_pkg.all;
entity lofar2_unb2b_beamformer is
generic (
@@ -91,9 +91,9 @@ entity lofar2_unb2b_beamformer is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -400,267 +400,267 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_dp_clk_freq,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_dp_clk_freq,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_beamformer
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ reg_bf_scale_mosi => reg_bf_scale_mosi,
+ reg_bf_scale_miso => reg_bf_scale_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso,
+ ram_st_bst_mosi => ram_st_bst_mosi,
+ ram_st_bst_miso => ram_st_bst_miso,
+ reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
+ reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
+ reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
+ reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
-----------------------------------------------------------------------------
-- SDP Info register
-----------------------------------------------------------------------------
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- nof beamsets node_sdp_beamformers (BF)
@@ -681,215 +681,215 @@ begin
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
-----------------------------------------------------------------------------
u_ait: entity lofar2_unb2b_adc_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_V_si_db,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd_ctrl_mosi => c_mem_mosi_rst,
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_V_si_db,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd_ctrl_mosi => c_mem_mosi_rst,
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
-- Beamformers
gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
u_bf : entity lofar2_sdp_lib.node_sdp_beamformer
- generic map(
- g_sim => g_sim,
- g_beamset_id => beamset_id,
- g_scope_selected_beamlet => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => OPEN,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
-
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => cep_eth_src_mac,
- ip_src_addr => cep_ip_src_addr,
- udp_src_port => cep_udp_src_port,
-
- hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
- );
+ generic map(
+ g_sim => g_sim,
+ g_beamset_id => beamset_id,
+ g_scope_selected_beamlet => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => OPEN,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
+ ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
+ ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => cep_eth_src_mac,
+ ip_src_addr => cep_ip_src_addr,
+ udp_src_port => cep_udp_src_port,
+
+ hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ );
end generate;
-- MM multiplexing
u_mem_mux_ram_ss_ss_wide : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- port map (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ port map (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
u_mem_mux_ram_bf_weights : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- port map (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ port map (
+ mosi => ram_bf_weights_mosi,
+ miso => ram_bf_weights_miso,
+ mosi_arr => ram_bf_weights_mosi_arr,
+ miso_arr => ram_bf_weights_miso_arr
+ );
u_mem_mux_reg_bf_scale : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- port map (
- mosi => reg_bf_scale_mosi,
- miso => reg_bf_scale_miso,
- mosi_arr => reg_bf_scale_mosi_arr,
- miso_arr => reg_bf_scale_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ port map (
+ mosi => reg_bf_scale_mosi,
+ miso => reg_bf_scale_miso,
+ mosi_arr => reg_bf_scale_mosi_arr,
+ miso_arr => reg_bf_scale_miso_arr
+ );
u_mem_mux_reg_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
u_mem_mux_reg_dp_xonoff : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- port map (
- mosi => reg_dp_xonoff_mosi,
- miso => reg_dp_xonoff_miso,
- mosi_arr => reg_dp_xonoff_mosi_arr,
- miso_arr => reg_dp_xonoff_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ port map (
+ mosi => reg_dp_xonoff_mosi,
+ miso => reg_dp_xonoff_miso,
+ mosi_arr => reg_dp_xonoff_mosi_arr,
+ miso_arr => reg_dp_xonoff_miso_arr
+ );
u_mem_mux_ram_st_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- port map (
- mosi => ram_st_bst_mosi,
- miso => ram_st_bst_miso,
- mosi_arr => ram_st_bst_mosi_arr,
- miso_arr => ram_st_bst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ port map (
+ mosi => ram_st_bst_mosi,
+ miso => ram_st_bst_miso,
+ mosi_arr => ram_st_bst_mosi_arr,
+ miso_arr => ram_st_bst_miso_arr
+ );
@@ -902,35 +902,35 @@ begin
nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
-
- src_out => nw_10gbe_snk_in_arr(0),
- src_in => nw_10gbe_snk_out_arr(0)
- );
+ generic map (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => true,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
+
+ src_out => nw_10gbe_snk_in_arr(0),
+ src_in => nw_10gbe_snk_out_arr(0)
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
- -- put the QSFP_TX/RX ports into arrays
- i_QSFP_RX(0) <= QSFP_1_RX;
- QSFP_1_TX <= i_QSFP_TX(0);
- ------------
- -- Front IO
- ------------
- u_front_io : entity unb2b_board_lib.unb2b_board_front_io
+ -- put the QSFP_TX/RX ports into arrays
+ i_QSFP_RX(0) <= QSFP_1_RX;
+ QSFP_1_TX <= i_QSFP_TX(0);
+ ------------
+ -- Front IO
+ ------------
+ u_front_io : entity unb2b_board_lib.unb2b_board_front_io
generic map (
g_nof_qsfp_bus => c_nof_qsfp_bus
)
@@ -948,10 +948,10 @@ begin
);
- ---------
- -- PLL
- ---------
- u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ ---------
+ -- PLL
+ ---------
+ u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
generic map (
)
port map (
@@ -964,10 +964,10 @@ begin
);
- ---------------
- -- nw_10GbE
- ---------------
- u_nw_10GbE: entity nw_10GbE_lib.nw_10GbE
+ ---------------
+ -- nw_10GbE
+ ---------------
+ u_nw_10GbE: entity nw_10GbE_lib.nw_10GbE
generic map (
g_sim => g_sim,
g_sim_level => 1,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
index c9c60af0b8..ea10e16227 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
@@ -20,14 +20,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_beamformer_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -43,7 +43,7 @@ package lofar2_unb2b_beamformer_pkg is
constant c_one_node_256MHz : t_lofar2_unb2b_beamformer_config := ( 12, 2, 12, c_unb2b_board_ext_clk_freq_256M );
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_beamformer_config;
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_beamformer_config;
end lofar2_unb2b_beamformer_pkg;
@@ -51,7 +51,7 @@ end lofar2_unb2b_beamformer_pkg;
package body lofar2_unb2b_beamformer_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_beamformer_config is
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_beamformer_config is
begin
if g_design_name = "lofar2_unb2b_beamformer_one_node" then return c_one_node;
elsif g_design_name = "lofar2_unb2b_beamformer_one_node_256MHz" then return c_one_node_256MHz;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
index 75fed2788b..9aa2e16eb1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_beamformer_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_beamformer_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_beamformer is
generic (
@@ -154,49 +154,49 @@ entity mmm_lofar2_unb2b_beamformer is
reg_si_mosi : out t_mem_mosi;
reg_si_miso : in t_mem_miso;
- -- Equalizer gains
- ram_equalizer_gains_mosi : out t_mem_mosi;
- ram_equalizer_gains_miso : in t_mem_miso;
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : out t_mem_mosi;
+ ram_equalizer_gains_miso : in t_mem_miso;
- -- DP Selector
- reg_dp_selector_mosi : out t_mem_mosi;
- reg_dp_selector_miso : in t_mem_miso;
+ -- DP Selector
+ reg_dp_selector_mosi : out t_mem_mosi;
+ reg_dp_selector_miso : in t_mem_miso;
- -- SDP Info
- reg_sdp_info_mosi : out t_mem_mosi;
- reg_sdp_info_miso : in t_mem_miso;
+ -- SDP Info
+ reg_sdp_info_mosi : out t_mem_mosi;
+ reg_sdp_info_miso : in t_mem_miso;
- -- Beamlet Subband Select
- ram_ss_ss_wide_mosi : out t_mem_mosi;
- ram_ss_ss_wide_miso : in t_mem_miso;
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_mosi : out t_mem_mosi;
+ ram_ss_ss_wide_miso : in t_mem_miso;
- -- Local BF bf weights
- ram_bf_weights_mosi : out t_mem_mosi;
- ram_bf_weights_miso : in t_mem_miso;
+ -- Local BF bf weights
+ ram_bf_weights_mosi : out t_mem_mosi;
+ ram_bf_weights_miso : in t_mem_miso;
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : out t_mem_mosi;
- reg_bf_scale_miso : in t_mem_miso;
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_mosi : out t_mem_mosi;
+ reg_bf_scale_miso : in t_mem_miso;
- -- Beamlet Data Output header fields
- reg_hdr_dat_mosi : out t_mem_mosi;
- reg_hdr_dat_miso : in t_mem_miso;
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_mosi : out t_mem_mosi;
+ reg_hdr_dat_miso : in t_mem_miso;
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : out t_mem_mosi;
- reg_dp_xonoff_miso : in t_mem_miso;
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_mosi : out t_mem_mosi;
+ reg_dp_xonoff_miso : in t_mem_miso;
- -- Beamlet Statistics (BST)
- ram_st_bst_mosi : out t_mem_mosi;
- ram_st_bst_miso : in t_mem_miso;
+ -- Beamlet Statistics (BST)
+ ram_st_bst_mosi : out t_mem_mosi;
+ ram_st_bst_miso : in t_mem_miso;
- -- 10 GbE mac
- reg_nw_10GbE_mac_mosi : out t_mem_mosi;
- reg_nw_10GbE_mac_miso : in t_mem_miso;
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_mosi : out t_mem_mosi;
+ reg_nw_10GbE_mac_miso : in t_mem_miso;
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_mosi : out t_mem_mosi;
- reg_nw_10GbE_eth10g_miso : in t_mem_miso;
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_mosi : out t_mem_mosi;
+ reg_nw_10GbE_eth10g_miso : in t_mem_miso;
-- Scrap ram
ram_scrap_mosi : out t_mem_mosi;
@@ -220,112 +220,112 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+ port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
+ port map(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
+ port map(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+ port map(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -340,367 +340,367 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2b_beamformer
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- jesd204b_reset_export => OPEN,
- jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
- reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- waveform generators (multiplexed)
- reg_wg_clk_export => OPEN,
- reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
- reg_wg_read_export => reg_wg_mosi.rd,
- reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w - 1 downto 0),
- reg_wg_write_export => reg_wg_mosi.wr,
- reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_wg_clk_export => OPEN,
- ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
- ram_wg_read_export => ram_wg_mosi.rd,
- ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w - 1 downto 0),
- ram_wg_write_export => ram_wg_mosi.wr,
- ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_dp_shiftram_clk_export => OPEN,
- reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_source_clk_export => OPEN,
- reg_bsn_source_reset_export => OPEN,
- reg_bsn_source_address_export => reg_bsn_source_mosi.address(2 - 1 downto 0),
- reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
- reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
- reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_scheduler_clk_export => OPEN,
- reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- ram_diag_data_buf_bsn_clk_export => OPEN,
- ram_diag_data_buf_bsn_reset_export => OPEN,
- ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(14 - 1 downto 0),
- ram_diag_data_buf_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buf_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buf_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buf_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buf_bsn_reset_export => OPEN,
- reg_diag_data_buf_bsn_clk_export => OPEN,
- reg_diag_data_buf_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
- reg_diag_data_buf_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buf_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buf_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buf_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buf_jesd_clk_export => OPEN,
- ram_diag_data_buf_jesd_reset_export => OPEN,
- ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(11 - 1 downto 0),
- ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
- ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
- ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buf_jesd_reset_export => OPEN,
- reg_diag_data_buf_jesd_clk_export => OPEN,
- reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(2 - 1 downto 0),
- reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
- reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
- reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
- reg_aduh_monitor_reset_export => OPEN,
- reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w - 1 downto 0),
-
- ram_fil_coefs_clk_export => OPEN,
- ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
- ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w - 1 downto 0),
- ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w - 1 downto 0),
-
- ram_st_sst_clk_export => OPEN,
- ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
- ram_st_sst_write_export => ram_st_sst_mosi.wr,
- ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w - 1 downto 0),
- ram_st_sst_read_export => ram_st_sst_mosi.rd,
- ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w - 1 downto 0),
-
- reg_si_clk_export => OPEN,
- reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w - 1 downto 0),
- reg_si_write_export => reg_si_mosi.wr,
- reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w - 1 downto 0),
- reg_si_read_export => reg_si_mosi.rd,
- reg_si_readdata_export => reg_si_miso.rddata(c_word_w - 1 downto 0),
-
- ram_equalizer_gains_clk_export => OPEN,
- ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w - 1 downto 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dp_selector_clk_export => OPEN,
- reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
- reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w - 1 downto 0),
-
- reg_sdp_info_clk_export => OPEN,
- reg_sdp_info_reset_export => OPEN,
- reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
- reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w - 1 downto 0),
- reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w - 1 downto 0),
-
- ram_ss_ss_wide_clk_export => OPEN,
- ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_address_export => ram_ss_ss_wide_mosi.address(c_sdp_ram_ss_ss_wide_addr_w - 1 downto 0),
- ram_ss_ss_wide_write_export => ram_ss_ss_wide_mosi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_mosi.wrdata(c_word_w - 1 downto 0),
- ram_ss_ss_wide_read_export => ram_ss_ss_wide_mosi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_miso.rddata(c_word_w - 1 downto 0),
-
- ram_bf_weights_clk_export => OPEN,
- ram_bf_weights_reset_export => OPEN,
- ram_bf_weights_address_export => ram_bf_weights_mosi.address(c_sdp_ram_bf_weights_addr_w - 1 downto 0),
- ram_bf_weights_write_export => ram_bf_weights_mosi.wr,
- ram_bf_weights_writedata_export => ram_bf_weights_mosi.wrdata(c_word_w - 1 downto 0),
- ram_bf_weights_read_export => ram_bf_weights_mosi.rd,
- ram_bf_weights_readdata_export => ram_bf_weights_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bf_scale_clk_export => OPEN,
- reg_bf_scale_reset_export => OPEN,
- reg_bf_scale_address_export => reg_bf_scale_mosi.address(c_sdp_reg_bf_scale_addr_w - 1 downto 0),
- reg_bf_scale_write_export => reg_bf_scale_mosi.wr,
- reg_bf_scale_writedata_export => reg_bf_scale_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bf_scale_read_export => reg_bf_scale_mosi.rd,
- reg_bf_scale_readdata_export => reg_bf_scale_miso.rddata(c_word_w - 1 downto 0),
-
- reg_hdr_dat_clk_export => OPEN,
- reg_hdr_dat_reset_export => OPEN,
- reg_hdr_dat_address_export => reg_hdr_dat_mosi.address(c_sdp_reg_bf_hdr_dat_addr_w - 1 downto 0),
- reg_hdr_dat_write_export => reg_hdr_dat_mosi.wr,
- reg_hdr_dat_writedata_export => reg_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
- reg_hdr_dat_read_export => reg_hdr_dat_mosi.rd,
- reg_hdr_dat_readdata_export => reg_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_clk_export => OPEN,
- reg_dp_xonoff_reset_export => OPEN,
- reg_dp_xonoff_address_export => reg_dp_xonoff_mosi.address(c_sdp_reg_dp_xonoff_addr_w - 1 downto 0),
- reg_dp_xonoff_write_export => reg_dp_xonoff_mosi.wr,
- reg_dp_xonoff_writedata_export => reg_dp_xonoff_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dp_xonoff_read_export => reg_dp_xonoff_mosi.rd,
- reg_dp_xonoff_readdata_export => reg_dp_xonoff_miso.rddata(c_word_w - 1 downto 0),
-
- ram_st_bst_clk_export => OPEN,
- ram_st_bst_reset_export => OPEN,
- ram_st_bst_address_export => ram_st_bst_mosi.address(c_sdp_ram_st_bst_addr_w - 1 downto 0),
- ram_st_bst_write_export => ram_st_bst_mosi.wr,
- ram_st_bst_writedata_export => ram_st_bst_mosi.wrdata(c_word_w - 1 downto 0),
- ram_st_bst_read_export => ram_st_bst_mosi.rd,
- ram_st_bst_readdata_export => ram_st_bst_miso.rddata(c_word_w - 1 downto 0),
-
- reg_nw_10GbE_mac_clk_export => OPEN,
- reg_nw_10GbE_mac_reset_export => OPEN,
- reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w - 1 downto 0),
- reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_mosi.wr,
- reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_mosi.wrdata(c_word_w - 1 downto 0),
- reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_mosi.rd,
- reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_miso.rddata(c_word_w - 1 downto 0),
-
- reg_nw_10GbE_eth10g_clk_export => OPEN,
- reg_nw_10GbE_eth10g_reset_export => OPEN,
- reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_mosi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w - 1 downto 0),
- reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_mosi.wr,
- reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_mosi.wrdata(c_word_w - 1 downto 0),
- reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_mosi.rd,
- reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_miso.rddata(c_word_w - 1 downto 0),
-
- ram_scrap_clk_export => OPEN,
- ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(9 - 1 downto 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ jesd204b_reset_export => OPEN,
+ jesd204b_clk_export => OPEN,
+ jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
+ jesd204b_write_export => jesd204b_mosi.wr,
+ jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
+ jesd204b_read_export => jesd204b_mosi.rd,
+ jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
+ reg_bsn_monitor_input_clk_export => OPEN,
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_input_reset_export => OPEN,
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- waveform generators (multiplexed)
+ reg_wg_clk_export => OPEN,
+ reg_wg_reset_export => OPEN,
+ reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
+ reg_wg_read_export => reg_wg_mosi.rd,
+ reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w - 1 downto 0),
+ reg_wg_write_export => reg_wg_mosi.wr,
+ reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_wg_clk_export => OPEN,
+ ram_wg_reset_export => OPEN,
+ ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
+ ram_wg_read_export => ram_wg_mosi.rd,
+ ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w - 1 downto 0),
+ ram_wg_write_export => ram_wg_mosi.wr,
+ ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_dp_shiftram_clk_export => OPEN,
+ reg_dp_shiftram_reset_export => OPEN,
+ reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_source_clk_export => OPEN,
+ reg_bsn_source_reset_export => OPEN,
+ reg_bsn_source_address_export => reg_bsn_source_mosi.address(2 - 1 downto 0),
+ reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
+ reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
+ reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_scheduler_clk_export => OPEN,
+ reg_bsn_scheduler_reset_export => OPEN,
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ ram_diag_data_buf_bsn_clk_export => OPEN,
+ ram_diag_data_buf_bsn_reset_export => OPEN,
+ ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(14 - 1 downto 0),
+ ram_diag_data_buf_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
+ ram_diag_data_buf_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
+ ram_diag_data_buf_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buf_bsn_reset_export => OPEN,
+ reg_diag_data_buf_bsn_clk_export => OPEN,
+ reg_diag_data_buf_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
+ reg_diag_data_buf_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
+ reg_diag_data_buf_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
+ reg_diag_data_buf_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buf_jesd_clk_export => OPEN,
+ ram_diag_data_buf_jesd_reset_export => OPEN,
+ ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(11 - 1 downto 0),
+ ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
+ ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
+ ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buf_jesd_reset_export => OPEN,
+ reg_diag_data_buf_jesd_clk_export => OPEN,
+ reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(2 - 1 downto 0),
+ reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
+ reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
+ reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_aduh_monitor_reset_export => OPEN,
+ reg_aduh_monitor_clk_export => OPEN,
+ reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_fil_coefs_clk_export => OPEN,
+ ram_fil_coefs_reset_export => OPEN,
+ ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_st_sst_clk_export => OPEN,
+ ram_st_sst_reset_export => OPEN,
+ ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
+ ram_st_sst_write_export => ram_st_sst_mosi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_st_sst_read_export => ram_st_sst_mosi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_si_clk_export => OPEN,
+ reg_si_reset_export => OPEN,
+ reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w - 1 downto 0),
+ reg_si_write_export => reg_si_mosi.wr,
+ reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_si_read_export => reg_si_mosi.rd,
+ reg_si_readdata_export => reg_si_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_equalizer_gains_clk_export => OPEN,
+ ram_equalizer_gains_reset_export => OPEN,
+ ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_selector_clk_export => OPEN,
+ reg_dp_selector_reset_export => OPEN,
+ reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
+ reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_sdp_info_clk_export => OPEN,
+ reg_sdp_info_reset_export => OPEN,
+ reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
+ reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_ss_ss_wide_clk_export => OPEN,
+ ram_ss_ss_wide_reset_export => OPEN,
+ ram_ss_ss_wide_address_export => ram_ss_ss_wide_mosi.address(c_sdp_ram_ss_ss_wide_addr_w - 1 downto 0),
+ ram_ss_ss_wide_write_export => ram_ss_ss_wide_mosi.wr,
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_ss_ss_wide_read_export => ram_ss_ss_wide_mosi.rd,
+ ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_bf_weights_clk_export => OPEN,
+ ram_bf_weights_reset_export => OPEN,
+ ram_bf_weights_address_export => ram_bf_weights_mosi.address(c_sdp_ram_bf_weights_addr_w - 1 downto 0),
+ ram_bf_weights_write_export => ram_bf_weights_mosi.wr,
+ ram_bf_weights_writedata_export => ram_bf_weights_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_bf_weights_read_export => ram_bf_weights_mosi.rd,
+ ram_bf_weights_readdata_export => ram_bf_weights_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bf_scale_clk_export => OPEN,
+ reg_bf_scale_reset_export => OPEN,
+ reg_bf_scale_address_export => reg_bf_scale_mosi.address(c_sdp_reg_bf_scale_addr_w - 1 downto 0),
+ reg_bf_scale_write_export => reg_bf_scale_mosi.wr,
+ reg_bf_scale_writedata_export => reg_bf_scale_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bf_scale_read_export => reg_bf_scale_mosi.rd,
+ reg_bf_scale_readdata_export => reg_bf_scale_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_hdr_dat_clk_export => OPEN,
+ reg_hdr_dat_reset_export => OPEN,
+ reg_hdr_dat_address_export => reg_hdr_dat_mosi.address(c_sdp_reg_bf_hdr_dat_addr_w - 1 downto 0),
+ reg_hdr_dat_write_export => reg_hdr_dat_mosi.wr,
+ reg_hdr_dat_writedata_export => reg_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_hdr_dat_read_export => reg_hdr_dat_mosi.rd,
+ reg_hdr_dat_readdata_export => reg_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_clk_export => OPEN,
+ reg_dp_xonoff_reset_export => OPEN,
+ reg_dp_xonoff_address_export => reg_dp_xonoff_mosi.address(c_sdp_reg_dp_xonoff_addr_w - 1 downto 0),
+ reg_dp_xonoff_write_export => reg_dp_xonoff_mosi.wr,
+ reg_dp_xonoff_writedata_export => reg_dp_xonoff_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_read_export => reg_dp_xonoff_mosi.rd,
+ reg_dp_xonoff_readdata_export => reg_dp_xonoff_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_st_bst_clk_export => OPEN,
+ ram_st_bst_reset_export => OPEN,
+ ram_st_bst_address_export => ram_st_bst_mosi.address(c_sdp_ram_st_bst_addr_w - 1 downto 0),
+ ram_st_bst_write_export => ram_st_bst_mosi.wr,
+ ram_st_bst_writedata_export => ram_st_bst_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_st_bst_read_export => ram_st_bst_mosi.rd,
+ ram_st_bst_readdata_export => ram_st_bst_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_nw_10GbE_mac_clk_export => OPEN,
+ reg_nw_10GbE_mac_reset_export => OPEN,
+ reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w - 1 downto 0),
+ reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_mosi.wr,
+ reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_mosi.rd,
+ reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_nw_10GbE_eth10g_clk_export => OPEN,
+ reg_nw_10GbE_eth10g_reset_export => OPEN,
+ reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_mosi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w - 1 downto 0),
+ reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_mosi.wr,
+ reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_mosi.rd,
+ reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(9 - 1 downto 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
index eec711a09d..b4b2c4613f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
@@ -19,332 +19,332 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_beamformer_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_beamformer is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_beamformer;
+ component qsys_lofar2_unb2b_beamformer is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_beamformer;
end qsys_lofar2_unb2b_beamformer_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index 64c94a7e6b..8b234bae6a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -49,20 +49,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_beamformer is
end tb_lofar2_unb2b_beamformer;
@@ -223,60 +223,60 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_beamformer : entity work.lofar2_unb2b_beamformer
- generic map (
- g_design_name => "lofar2_unb2b_beamformer_full",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_1_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_0,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
-
- u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ generic map (
+ g_design_name => "lofar2_unb2b_beamformer_full",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
port map (
refclk_644 => SA_CLK,
rst_in => pps_rst,
@@ -286,7 +286,7 @@ begin
rst_312 => open
);
- u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
+ u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_sim => true,
g_sim_level => 1,
@@ -435,8 +435,8 @@ begin
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_beamlet_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_beamlet_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_beamlet_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_beamlet_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
+ real(TO_UINT(sp_beamlet_powers_arr2(v_S)(v_B)(29 downto 0)));
-- sum
sp_beamlet_power_sum(v_S) <= sp_beamlet_power_sum(v_S) + v_sp_beamlet_power;
end if;
@@ -447,7 +447,7 @@ begin
-- because the input is a sinus, so most power will be in 1 subband. The sp_beamlet_power_leakage_sum shows
-- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
sp_beamlet_power_0 <= real(TO_UINT(sp_beamlet_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_beamlet_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
+ real(TO_UINT(sp_beamlet_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
sp_beamlet_power_sum_0 <= sp_beamlet_power_sum(0);
@@ -499,13 +499,13 @@ begin
if v_S = 0 then
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_beamlet_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_beamlet_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_beamlet_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_beamlet_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
+ real(TO_UINT(sp_beamlet_powers_arr2(v_S)(v_B)(29 downto 0)));
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_subband_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
+ real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
-- verify if subband power and beamlet power are the same. This is expected because we only use 1 WG input and the BF weights have unit value.
-- the difference should not be larger than 0.5% (+/- 2^13 for low values)
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
index f40c7e0420..dd0e496789 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_filterbank_full is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2b_filterbank_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -112,51 +112,51 @@ begin
u_revision : entity lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
index 74c1bb4c1d..4b8fe968d3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_filterbank_full_256MHz is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2b_filterbank_full_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -112,51 +112,51 @@ begin
u_revision : entity lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index 99bc1ee68f..450d5d11e0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -27,19 +27,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_filterbank_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_filterbank_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2b_filterbank is
generic (
@@ -87,9 +87,9 @@ entity lofar2_unb2b_filterbank is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -304,243 +304,243 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_dp_clk_freq,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_dp_clk_freq,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_filterbank
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Statistics offload
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
- reg_stat_enable_mosi => reg_stat_enable_mosi,
- reg_stat_enable_miso => reg_stat_enable_miso,
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Statistics offload
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+ reg_stat_enable_mosi => reg_stat_enable_mosi,
+ reg_stat_enable_miso => reg_stat_enable_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_miso
+ );
-----------------------------------------------------------------------------
-- SDP Info register
@@ -553,25 +553,25 @@ begin
sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
@@ -579,103 +579,103 @@ begin
-----------------------------------------------------------------------------
u_ait: entity lofar2_unb2b_adc_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_V_si_db,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_V_si_db,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_mosi,
- reg_enable_miso => reg_stat_enable_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
index 54639dc946..f1be9ebfe3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
@@ -20,14 +20,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_filterbank_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -43,7 +43,7 @@ package lofar2_unb2b_filterbank_pkg is
constant c_full_256MHz : t_lofar2_unb2b_filterbank_config := ( 12, 2, 12, c_unb2b_board_ext_clk_freq_256M );
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_filterbank_config;
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_filterbank_config;
end lofar2_unb2b_filterbank_pkg;
@@ -51,7 +51,7 @@ end lofar2_unb2b_filterbank_pkg;
package body lofar2_unb2b_filterbank_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_filterbank_config is
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_filterbank_config is
begin
if g_design_name = "lofar2_unb2b_filterbank_full" then return c_full;
elsif g_design_name = "lofar2_unb2b_filterbank_full_256MHz" then return c_full_256MHz;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
index 27c0955ee3..a4f9e82e39 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_filterbank_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_filterbank_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_filterbank is
generic (
@@ -200,94 +200,94 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
u_mm_file_reg_stat_enable : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
- port map(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
+ port map(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
u_mm_file_reg_stat_hdr_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -303,325 +303,325 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2b_filterbank
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- jesd204b_reset_export => OPEN,
- jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
-
- pio_jesd_ctrl_reset_export => OPEN,
- pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(0 downto 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
- reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- waveform generators (multiplexed)
- reg_wg_clk_export => OPEN,
- reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
- reg_wg_read_export => reg_wg_mosi.rd,
- reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w - 1 downto 0),
- reg_wg_write_export => reg_wg_mosi.wr,
- reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_wg_clk_export => OPEN,
- ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
- ram_wg_read_export => ram_wg_mosi.rd,
- ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w - 1 downto 0),
- ram_wg_write_export => ram_wg_mosi.wr,
- ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_dp_shiftram_clk_export => OPEN,
- reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_source_clk_export => OPEN,
- reg_bsn_source_reset_export => OPEN,
- reg_bsn_source_address_export => reg_bsn_source_mosi.address(2 - 1 downto 0),
- reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
- reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
- reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_scheduler_clk_export => OPEN,
- reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- ram_diag_data_buf_bsn_clk_export => OPEN,
- ram_diag_data_buf_bsn_reset_export => OPEN,
- ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(14 - 1 downto 0),
- ram_diag_data_buf_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buf_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buf_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buf_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buf_bsn_reset_export => OPEN,
- reg_diag_data_buf_bsn_clk_export => OPEN,
- reg_diag_data_buf_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
- reg_diag_data_buf_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buf_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buf_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buf_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buf_jesd_clk_export => OPEN,
- ram_diag_data_buf_jesd_reset_export => OPEN,
- ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(11 - 1 downto 0),
- ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
- ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
- ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buf_jesd_reset_export => OPEN,
- reg_diag_data_buf_jesd_clk_export => OPEN,
- reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(2 - 1 downto 0),
- reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
- reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
- reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
- reg_aduh_monitor_reset_export => OPEN,
- reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w - 1 downto 0),
-
- ram_fil_coefs_clk_export => OPEN,
- ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
- ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w - 1 downto 0),
- ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w - 1 downto 0),
-
- ram_st_sst_clk_export => OPEN,
- ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
- ram_st_sst_write_export => ram_st_sst_mosi.wr,
- ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w - 1 downto 0),
- ram_st_sst_read_export => ram_st_sst_mosi.rd,
- ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w - 1 downto 0),
-
- reg_si_clk_export => OPEN,
- reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w - 1 downto 0),
- reg_si_write_export => reg_si_mosi.wr,
- reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w - 1 downto 0),
- reg_si_read_export => reg_si_mosi.rd,
- reg_si_readdata_export => reg_si_miso.rddata(c_word_w - 1 downto 0),
-
- ram_equalizer_gains_clk_export => OPEN,
- ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w - 1 downto 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dp_selector_clk_export => OPEN,
- reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
- reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w - 1 downto 0),
-
- ram_scrap_clk_export => OPEN,
- ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(9 - 1 downto 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0),
-
- reg_sdp_info_clk_export => OPEN,
- reg_sdp_info_reset_export => OPEN,
- reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
- reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w - 1 downto 0),
- reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w - 1 downto 0),
-
- reg_stat_enable_clk_export => OPEN,
- reg_stat_enable_reset_export => OPEN,
- reg_stat_enable_address_export => reg_stat_enable_mosi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
- reg_stat_enable_write_export => reg_stat_enable_mosi.wr,
- reg_stat_enable_writedata_export => reg_stat_enable_mosi.wrdata(c_word_w - 1 downto 0),
- reg_stat_enable_read_export => reg_stat_enable_mosi.rd,
- reg_stat_enable_readdata_export => reg_stat_enable_miso.rddata(c_word_w - 1 downto 0),
-
- reg_stat_hdr_dat_clk_export => OPEN,
- reg_stat_hdr_dat_reset_export => OPEN,
- reg_stat_hdr_dat_address_export => reg_stat_hdr_dat_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
- reg_stat_hdr_dat_write_export => reg_stat_hdr_dat_mosi.wr,
- reg_stat_hdr_dat_writedata_export => reg_stat_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
- reg_stat_hdr_dat_read_export => reg_stat_hdr_dat_mosi.rd,
- reg_stat_hdr_dat_readdata_export => reg_stat_hdr_dat_miso.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ jesd204b_reset_export => OPEN,
+ jesd204b_clk_export => OPEN,
+ jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
+ jesd204b_write_export => jesd204b_mosi.wr,
+ jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
+ jesd204b_read_export => jesd204b_mosi.rd,
+ jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_jesd_ctrl_reset_export => OPEN,
+ pio_jesd_ctrl_clk_export => OPEN,
+ pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(0 downto 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
+ reg_bsn_monitor_input_clk_export => OPEN,
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_input_reset_export => OPEN,
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- waveform generators (multiplexed)
+ reg_wg_clk_export => OPEN,
+ reg_wg_reset_export => OPEN,
+ reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
+ reg_wg_read_export => reg_wg_mosi.rd,
+ reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w - 1 downto 0),
+ reg_wg_write_export => reg_wg_mosi.wr,
+ reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_wg_clk_export => OPEN,
+ ram_wg_reset_export => OPEN,
+ ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
+ ram_wg_read_export => ram_wg_mosi.rd,
+ ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w - 1 downto 0),
+ ram_wg_write_export => ram_wg_mosi.wr,
+ ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_dp_shiftram_clk_export => OPEN,
+ reg_dp_shiftram_reset_export => OPEN,
+ reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_source_clk_export => OPEN,
+ reg_bsn_source_reset_export => OPEN,
+ reg_bsn_source_address_export => reg_bsn_source_mosi.address(2 - 1 downto 0),
+ reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
+ reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
+ reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_scheduler_clk_export => OPEN,
+ reg_bsn_scheduler_reset_export => OPEN,
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ ram_diag_data_buf_bsn_clk_export => OPEN,
+ ram_diag_data_buf_bsn_reset_export => OPEN,
+ ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(14 - 1 downto 0),
+ ram_diag_data_buf_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
+ ram_diag_data_buf_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
+ ram_diag_data_buf_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buf_bsn_reset_export => OPEN,
+ reg_diag_data_buf_bsn_clk_export => OPEN,
+ reg_diag_data_buf_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
+ reg_diag_data_buf_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
+ reg_diag_data_buf_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
+ reg_diag_data_buf_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buf_jesd_clk_export => OPEN,
+ ram_diag_data_buf_jesd_reset_export => OPEN,
+ ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(11 - 1 downto 0),
+ ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
+ ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
+ ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buf_jesd_reset_export => OPEN,
+ reg_diag_data_buf_jesd_clk_export => OPEN,
+ reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(2 - 1 downto 0),
+ reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
+ reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
+ reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_aduh_monitor_reset_export => OPEN,
+ reg_aduh_monitor_clk_export => OPEN,
+ reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_fil_coefs_clk_export => OPEN,
+ ram_fil_coefs_reset_export => OPEN,
+ ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_st_sst_clk_export => OPEN,
+ ram_st_sst_reset_export => OPEN,
+ ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
+ ram_st_sst_write_export => ram_st_sst_mosi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_st_sst_read_export => ram_st_sst_mosi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_si_clk_export => OPEN,
+ reg_si_reset_export => OPEN,
+ reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w - 1 downto 0),
+ reg_si_write_export => reg_si_mosi.wr,
+ reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_si_read_export => reg_si_mosi.rd,
+ reg_si_readdata_export => reg_si_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_equalizer_gains_clk_export => OPEN,
+ ram_equalizer_gains_reset_export => OPEN,
+ ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_selector_clk_export => OPEN,
+ reg_dp_selector_reset_export => OPEN,
+ reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
+ reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(9 - 1 downto 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_sdp_info_clk_export => OPEN,
+ reg_sdp_info_reset_export => OPEN,
+ reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
+ reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_enable_clk_export => OPEN,
+ reg_stat_enable_reset_export => OPEN,
+ reg_stat_enable_address_export => reg_stat_enable_mosi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
+ reg_stat_enable_write_export => reg_stat_enable_mosi.wr,
+ reg_stat_enable_writedata_export => reg_stat_enable_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_enable_read_export => reg_stat_enable_mosi.rd,
+ reg_stat_enable_readdata_export => reg_stat_enable_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_hdr_dat_clk_export => OPEN,
+ reg_stat_hdr_dat_reset_export => OPEN,
+ reg_stat_hdr_dat_address_export => reg_stat_hdr_dat_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
+ reg_stat_hdr_dat_write_export => reg_stat_hdr_dat_mosi.wr,
+ reg_stat_hdr_dat_writedata_export => reg_stat_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_hdr_dat_read_export => reg_stat_hdr_dat_mosi.rd,
+ reg_stat_hdr_dat_readdata_export => reg_stat_hdr_dat_miso.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
index e06b06d095..894df9cff2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
@@ -19,300 +19,300 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_filterbank_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_filterbank is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ component qsys_lofar2_unb2b_filterbank is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_clk_export : out std_logic; -- export
- reg_stat_enable_read_export : out std_logic; -- export
- reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_reset_export : out std_logic; -- export
- reg_stat_enable_write_export : out std_logic; -- export
- reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_read_export : out std_logic; -- export
- reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_write_export : out std_logic; -- export
- reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_clk_export : out std_logic; -- export
+ reg_stat_enable_read_export : out std_logic; -- export
+ reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_reset_export : out std_logic; -- export
+ reg_stat_enable_write_export : out std_logic; -- export
+ reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2b_filterbank;
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2b_filterbank;
end qsys_lofar2_unb2b_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
index 034c6ca655..9b3226d29c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
@@ -51,19 +51,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_filterbank is
end tb_lofar2_unb2b_filterbank;
@@ -203,52 +203,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_filterbank : entity work.lofar2_unb2b_filterbank
- generic map (
- g_design_name => "lofar2_unb2b_filterbank_full",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_filterbank_full",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -379,8 +379,8 @@ begin
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_subband_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
+ real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
-- sum
sp_subband_power_sum(v_S) <= sp_subband_power_sum(v_S) + v_sp_subband_power;
end if;
@@ -390,7 +390,7 @@ begin
-- because the input is a sinus, so most power will be in 1 subband. The sp_subband_power_leakage_sum shows
-- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
sp_subband_power_0 <= real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
+ real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
sp_subband_power_sum_0 <= sp_subband_power_sum(0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
index 812ae5e19a..062bb38acd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_ring_full is
generic (
@@ -95,57 +95,57 @@ architecture str of lofar2_unb2b_ring_full is
begin
u_revision : entity lofar2_unb2b_ring_lib.lofar2_unb2b_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
index 1731e4fb08..a45aee1ff0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_ring_full is
end tb_lofar2_unb2b_ring_full;
@@ -105,53 +105,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_ring_full : entity work.lofar2_unb2b_ring_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
index b2b6bae2fc..871201b1de 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
@@ -30,13 +30,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_ring_one is
generic (
@@ -98,57 +98,57 @@ architecture str of lofar2_unb2b_ring_one is
begin
u_revision : entity lofar2_unb2b_ring_lib.lofar2_unb2b_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
index 171687d127..0bf177b074 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_ring_one is
end tb_lofar2_unb2b_ring_one;
@@ -105,53 +105,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_ring_one : entity work.lofar2_unb2b_ring_one
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index 709c058321..012624c561 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -27,21 +27,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_ring_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_ring_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity lofar2_unb2b_ring is
@@ -113,7 +113,7 @@ architecture str of lofar2_unb2b_ring is
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync; -- fixed 200 MHz for LOFAR2.0 stage 1
- -- QSFP
+ -- QSFP
constant c_nof_qsfp_bus : natural := 1;
constant c_nof_streams_qsfp : natural := c_unb2b_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
@@ -153,11 +153,13 @@ architecture str of lofar2_unb2b_ring is
constant c_addr_w_reg_dp_block_validate_bsn_at_sync : natural := ceil_log2(3);
- constant c_reg_ring_input_select : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_lanes),
- dat_w => 1,
- nof_dat => c_nof_lanes,
- init_sl => '0'); -- default use lane input = 0, 1 = local input.
+ constant c_reg_ring_input_select : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_lanes),
+ dat_w => 1,
+ nof_dat => c_nof_lanes,
+ init_sl => '0'
+ ); -- default use lane input = 0, 1 = local input.
signal gn_index : natural;
signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
@@ -352,292 +354,292 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_copi,
- reg_unb_sens_miso => reg_unb_sens_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
- reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_copi,
+ reg_unb_sens_miso => reg_unb_sens_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM controller
-----------------------------------------------------------------------------
u_mmc : entity work.mmc_lofar2_unb2b_ring
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_unb_sens_copi => reg_unb_sens_copi,
- reg_unb_sens_cipo => reg_unb_sens_cipo,
- reg_unb_pmbus_copi => reg_unb_pmbus_copi,
- reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
- reg_diag_bg_copi => reg_diag_bg_copi,
- reg_diag_bg_cipo => reg_diag_bg_cipo,
- ram_diag_bg_copi => ram_diag_bg_copi,
- ram_diag_bg_cipo => ram_diag_bg_cipo,
- reg_ring_lane_info_copi => reg_ring_lane_info_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
- reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
- reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
- reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
- reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_unb_sens_copi => reg_unb_sens_copi,
+ reg_unb_sens_cipo => reg_unb_sens_cipo,
+ reg_unb_pmbus_copi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
+ reg_diag_bg_copi => reg_diag_bg_copi,
+ reg_diag_bg_cipo => reg_diag_bg_cipo,
+ ram_diag_bg_copi => ram_diag_bg_copi,
+ ram_diag_bg_cipo => ram_diag_bg_cipo,
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
+ reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
+ reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
+ reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
+ reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo
+ );
-----------------------------------------------------------------------------
-- MM Mux
-----------------------------------------------------------------------------
u_mem_mux_ring_lane_info : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info
- )
- port map (
- mosi => reg_ring_lane_info_copi,
- miso => reg_ring_lane_info_cipo,
- mosi_arr => reg_ring_lane_info_copi_arr,
- miso_arr => reg_ring_lane_info_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info
+ )
+ port map (
+ mosi => reg_ring_lane_info_copi,
+ miso => reg_ring_lane_info_cipo,
+ mosi_arr => reg_ring_lane_info_copi_arr,
+ miso_arr => reg_ring_lane_info_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_rx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_copi,
- miso => reg_bsn_monitor_v2_ring_rx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_tx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_copi,
- miso => reg_bsn_monitor_v2_ring_tx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
+ );
u_mem_mux_dp_block_validate_err : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
- )
- port map (
- mosi => reg_dp_block_validate_err_copi,
- miso => reg_dp_block_validate_err_cipo,
- mosi_arr => reg_dp_block_validate_err_copi_arr,
- miso_arr => reg_dp_block_validate_err_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_copi,
+ miso => reg_dp_block_validate_err_cipo,
+ mosi_arr => reg_dp_block_validate_err_copi_arr,
+ miso_arr => reg_dp_block_validate_err_cipo_arr
+ );
u_mem_mux_dp_block_validate_bsn_at_sync : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_copi,
- miso => reg_dp_block_validate_bsn_at_sync_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
+ );
-----------------------------------------------------------------------------
-- MMP diag_block_gen
-----------------------------------------------------------------------------
u_mmp_diag_block_gen : entity diag_lib.mms_diag_block_gen
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
-
- reg_bg_ctrl_mosi => reg_diag_bg_copi,
- reg_bg_ctrl_miso => reg_diag_bg_cipo,
- ram_bg_data_mosi => ram_diag_bg_copi,
- ram_bg_data_miso => ram_diag_bg_cipo,
-
- out_sosi_arr(0) => local_sosi
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_copi,
+ reg_bg_ctrl_miso => reg_diag_bg_cipo,
+ ram_bg_data_mosi => ram_diag_bg_copi,
+ ram_bg_data_miso => ram_diag_bg_cipo,
+
+ out_sosi_arr(0) => local_sosi
+ );
bs_sosi <= local_sosi;
@@ -645,26 +647,26 @@ begin
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
u_mmp_dp_xonoff_lane : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_lane_copi,
- reg_miso => reg_dp_xonoff_lane_cipo,
+ reg_mosi => reg_dp_xonoff_lane_copi,
+ reg_miso => reg_dp_xonoff_lane_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => from_lane_sosi_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => from_lane_sosi_arr,
- src_in_arr => dp_xonoff_lane_src_in_arr,
- src_out_arr => dp_xonoff_lane_src_out_arr
- );
+ src_in_arr => dp_xonoff_lane_src_in_arr,
+ src_out_arr => dp_xonoff_lane_src_out_arr
+ );
-----------------------------------------------------------------------------
-- MMP dp_xonoff local_sosi
@@ -674,26 +676,26 @@ begin
end generate;
u_mmp_dp_xonoff_local : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_local_copi,
- reg_miso => reg_dp_xonoff_local_cipo,
+ reg_mosi => reg_dp_xonoff_local_copi,
+ reg_miso => reg_dp_xonoff_local_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => dp_xonoff_local_snk_in_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => dp_xonoff_local_snk_in_arr,
- src_in_arr => dp_xonoff_local_src_in_arr,
- src_out_arr => dp_xonoff_local_src_out_arr
- );
+ src_in_arr => dp_xonoff_local_src_in_arr,
+ src_out_arr => dp_xonoff_local_src_out_arr
+ );
-----------------------------------------------------------------------------
-- DP Mux
@@ -706,49 +708,49 @@ begin
dp_mux_snk_in_2arr(I)(1) <= dp_xonoff_local_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true,
- g_use_fifo => true,
- g_bsn_w => c_longword_w,
- g_data_w => c_lane_data_w,
- g_in_channel_w => c_byte_w,
- g_error_w => c_nof_err_counts,
- g_use_bsn => true,
- g_use_in_channel => true,
- g_use_error => true,
- g_use_sync => true,
- -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
- g_fifo_size => array_init(2 * c_lane_packet_length, 2)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_mux_snk_out_2arr(I),
- snk_in_arr => dp_mux_snk_in_2arr(I),
-
- src_in => c_dp_siso_rdy,
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true,
+ g_use_fifo => true,
+ g_bsn_w => c_longword_w,
+ g_data_w => c_lane_data_w,
+ g_in_channel_w => c_byte_w,
+ g_error_w => c_nof_err_counts,
+ g_use_bsn => true,
+ g_use_in_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
+ g_fifo_size => array_init(2 * c_lane_packet_length, 2)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_mux_snk_out_2arr(I),
+ snk_in_arr => dp_mux_snk_in_2arr(I),
+
+ src_in => c_dp_siso_rdy,
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
-- Use full c_byte_w range of ID for gn_index and ring_info.O_rn
gn_index <= TO_UINT(ID);
@@ -759,50 +761,50 @@ begin
-----------------------------------------------------------------------------
gen_even_lanes: for I in 0 to c_nof_even_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
- to_lane_sosi => to_lane_sosi_arr(2 * I),
- lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I),
+ lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -810,50 +812,50 @@ begin
-----------------------------------------------------------------------------
gen_odd_lanes : for I in 0 to c_nof_odd_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 0, -- transport in negative direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
- to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
- lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
- tx_select => ring_info.use_cable_to_previous_rn
- );
+ generic map (
+ g_lane_direction => 0, -- transport in negative direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
+ lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ tx_select => ring_info.use_cable_to_previous_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -882,45 +884,45 @@ begin
-- tr_10GbE
-----------------------------------------------------------------------------
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_mac,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill,
- g_tx_fifo_size => c_fifo_tx_size
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
-
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => tr_10gbe_src_out_arr,
- src_in_arr => tr_10gbe_src_in_arr,
-
- snk_out_arr => tr_10gbe_snk_out_arr,
- snk_in_arr => tr_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => tr_10gbe_serial_tx_arr,
- serial_rx_arr => tr_10gbe_serial_rx_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_mac,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill,
+ g_tx_fifo_size => c_fifo_tx_size
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
+
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => tr_10gbe_src_out_arr,
+ src_in_arr => tr_10gbe_src_in_arr,
+
+ snk_out_arr => tr_10gbe_snk_out_arr,
+ snk_in_arr => tr_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_serial_rx_arr
+ );
-----------------------------------------------------------------------------
@@ -949,14 +951,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- Front IO
@@ -966,21 +968,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- RING IO
@@ -995,19 +997,19 @@ begin
------------
unb2_board_qsfp_leds_tx_siso_arr(0) <= tr_10gbe_snk_out_arr(0);
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
index d594f682ef..a6827d93fe 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
@@ -19,14 +19,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_ring_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -39,7 +39,7 @@ package lofar2_unb2b_ring_pkg is
constant c_full : t_lofar2_unb2b_ring_config := (8, 8);
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_ring_config;
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_ring_config;
end lofar2_unb2b_ring_pkg;
@@ -47,7 +47,7 @@ end lofar2_unb2b_ring_pkg;
package body lofar2_unb2b_ring_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_ring_config is
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_ring_config is
begin
if g_design_name = "lofar2_unb2b_ring_one" then return c_one;
else return c_full;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
index b1396c516b..42946ef234 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_ring_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_ring_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmc_lofar2_unb2b_ring is
generic (
@@ -165,70 +165,70 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
+ port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
u_mm_file_reg_dp_block_validate_err : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
u_mm_file_reg_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
+ port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
u_mm_file_ram_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
+ port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
u_mm_file_reg_ring_lane_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
- port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
+ port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
u_mm_file_reg_dp_xonoff_lane : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
u_mm_file_reg_dp_xonoff_local : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
- port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -243,250 +243,250 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2b_ring
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_copi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_copi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_copi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_copi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_copi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_copi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_copi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_copi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_copi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_copi.wr,
- pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_copi.rd,
- pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_copi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_copi.wr,
- reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_copi.rd,
- reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_copi.wr,
- reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_copi.rd,
- reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_rx_address_export => reg_bsn_monitor_v2_ring_rx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_read_export => reg_bsn_monitor_v2_ring_rx_copi.rd,
- reg_bsn_monitor_v2_ring_rx_readdata_export => reg_bsn_monitor_v2_ring_rx_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_write_export => reg_bsn_monitor_v2_ring_rx_copi.wr,
- reg_bsn_monitor_v2_ring_rx_writedata_export => reg_bsn_monitor_v2_ring_rx_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_tx_address_export => reg_bsn_monitor_v2_ring_tx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_read_export => reg_bsn_monitor_v2_ring_tx_copi.rd,
- reg_bsn_monitor_v2_ring_tx_readdata_export => reg_bsn_monitor_v2_ring_tx_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_write_export => reg_bsn_monitor_v2_ring_tx_copi.wr,
- reg_bsn_monitor_v2_ring_tx_writedata_export => reg_bsn_monitor_v2_ring_tx_copi.wrdata(c_word_w - 1 downto 0),
-
- -- waveform generators (multiplexed)
- reg_diag_bg_clk_export => OPEN,
- reg_diag_bg_reset_export => OPEN,
- reg_diag_bg_address_export => reg_diag_bg_copi.address(c_sdp_reg_diag_bg_addr_w - 1 downto 0),
- reg_diag_bg_read_export => reg_diag_bg_copi.rd,
- reg_diag_bg_readdata_export => reg_diag_bg_cipo.rddata(c_word_w - 1 downto 0),
- reg_diag_bg_write_export => reg_diag_bg_copi.wr,
- reg_diag_bg_writedata_export => reg_diag_bg_copi.wrdata(c_word_w - 1 downto 0),
-
- ram_diag_bg_clk_export => OPEN,
- ram_diag_bg_reset_export => OPEN,
- ram_diag_bg_address_export => ram_diag_bg_copi.address(c_sdp_ram_diag_bg_addr_w - 1 downto 0),
- ram_diag_bg_read_export => ram_diag_bg_copi.rd,
- ram_diag_bg_readdata_export => ram_diag_bg_cipo.rddata(c_word_w - 1 downto 0),
- ram_diag_bg_write_export => ram_diag_bg_copi.wr,
- ram_diag_bg_writedata_export => ram_diag_bg_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_copi.wr,
- reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_copi.rd,
- reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_ring_lane_info_clk_export => OPEN,
- reg_ring_lane_info_reset_export => OPEN,
- reg_ring_lane_info_address_export => reg_ring_lane_info_copi.address(c_sdp_reg_ring_lane_info_addr_w - 1 downto 0),
- reg_ring_lane_info_write_export => reg_ring_lane_info_copi.wr,
- reg_ring_lane_info_writedata_export => reg_ring_lane_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_lane_info_read_export => reg_ring_lane_info_copi.rd,
- reg_ring_lane_info_readdata_export => reg_ring_lane_info_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_lane_clk_export => OPEN,
- reg_dp_xonoff_lane_reset_export => OPEN,
- reg_dp_xonoff_lane_address_export => reg_dp_xonoff_lane_copi.address(c_sdp_reg_dp_xonoff_lane_addr_w - 1 downto 0),
- reg_dp_xonoff_lane_write_export => reg_dp_xonoff_lane_copi.wr,
- reg_dp_xonoff_lane_writedata_export => reg_dp_xonoff_lane_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_xonoff_lane_read_export => reg_dp_xonoff_lane_copi.rd,
- reg_dp_xonoff_lane_readdata_export => reg_dp_xonoff_lane_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_local_clk_export => OPEN,
- reg_dp_xonoff_local_reset_export => OPEN,
- reg_dp_xonoff_local_address_export => reg_dp_xonoff_local_copi.address(c_sdp_reg_dp_xonoff_local_addr_w - 1 downto 0),
- reg_dp_xonoff_local_write_export => reg_dp_xonoff_local_copi.wr,
- reg_dp_xonoff_local_writedata_export => reg_dp_xonoff_local_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_xonoff_local_read_export => reg_dp_xonoff_local_copi.rd,
- reg_dp_xonoff_local_readdata_export => reg_dp_xonoff_local_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_err_clk_export => OPEN,
- reg_dp_block_validate_err_reset_export => OPEN,
- reg_dp_block_validate_err_address_export => reg_dp_block_validate_err_copi.address(c_sdp_reg_dp_block_validate_err_addr_w - 1 downto 0),
- reg_dp_block_validate_err_write_export => reg_dp_block_validate_err_copi.wr,
- reg_dp_block_validate_err_writedata_export => reg_dp_block_validate_err_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_err_read_export => reg_dp_block_validate_err_copi.rd,
- reg_dp_block_validate_err_readdata_export => reg_dp_block_validate_err_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_bsn_at_sync_clk_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_reset_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_address_export => reg_dp_block_validate_bsn_at_sync_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_write_export => reg_dp_block_validate_bsn_at_sync_copi.wr,
- reg_dp_block_validate_bsn_at_sync_writedata_export => reg_dp_block_validate_bsn_at_sync_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_read_export => reg_dp_block_validate_bsn_at_sync_copi.rd,
- reg_dp_block_validate_bsn_at_sync_readdata_export => reg_dp_block_validate_bsn_at_sync_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_ring_info_clk_export => OPEN,
- reg_ring_info_reset_export => OPEN,
- reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w - 1 downto 0),
- reg_ring_info_write_export => reg_ring_info_copi.wr,
- reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_info_read_export => reg_ring_info_copi.rd,
- reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_tr_10GbE_mac_clk_export => OPEN,
- reg_tr_10GbE_mac_reset_export => OPEN,
- reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w - 1 downto 0),
- reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr,
- reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd,
- reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_tr_10GbE_eth10g_clk_export => OPEN,
- reg_tr_10GbE_eth10g_reset_export => OPEN,
- reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w - 1 downto 0),
- reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr,
- reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd,
- reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_scrap_clk_export => OPEN,
- ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_copi.address(9 - 1 downto 0),
- ram_scrap_write_export => ram_scrap_copi.wr,
- ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_copi.rd,
- ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_copi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_copi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_copi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_copi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_copi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_copi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_copi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_copi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_copi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_copi.wr,
+ pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_copi.rd,
+ pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_copi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_copi.wr,
+ reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_copi.rd,
+ reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_copi.wr,
+ reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_copi.rd,
+ reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_rx_address_export => reg_bsn_monitor_v2_ring_rx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_read_export => reg_bsn_monitor_v2_ring_rx_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_readdata_export => reg_bsn_monitor_v2_ring_rx_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_write_export => reg_bsn_monitor_v2_ring_rx_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_writedata_export => reg_bsn_monitor_v2_ring_rx_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_tx_address_export => reg_bsn_monitor_v2_ring_tx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_read_export => reg_bsn_monitor_v2_ring_tx_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_readdata_export => reg_bsn_monitor_v2_ring_tx_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_write_export => reg_bsn_monitor_v2_ring_tx_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_writedata_export => reg_bsn_monitor_v2_ring_tx_copi.wrdata(c_word_w - 1 downto 0),
+
+ -- waveform generators (multiplexed)
+ reg_diag_bg_clk_export => OPEN,
+ reg_diag_bg_reset_export => OPEN,
+ reg_diag_bg_address_export => reg_diag_bg_copi.address(c_sdp_reg_diag_bg_addr_w - 1 downto 0),
+ reg_diag_bg_read_export => reg_diag_bg_copi.rd,
+ reg_diag_bg_readdata_export => reg_diag_bg_cipo.rddata(c_word_w - 1 downto 0),
+ reg_diag_bg_write_export => reg_diag_bg_copi.wr,
+ reg_diag_bg_writedata_export => reg_diag_bg_copi.wrdata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_clk_export => OPEN,
+ ram_diag_bg_reset_export => OPEN,
+ ram_diag_bg_address_export => ram_diag_bg_copi.address(c_sdp_ram_diag_bg_addr_w - 1 downto 0),
+ ram_diag_bg_read_export => ram_diag_bg_copi.rd,
+ ram_diag_bg_readdata_export => ram_diag_bg_cipo.rddata(c_word_w - 1 downto 0),
+ ram_diag_bg_write_export => ram_diag_bg_copi.wr,
+ ram_diag_bg_writedata_export => ram_diag_bg_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_copi.wr,
+ reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_copi.rd,
+ reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_ring_lane_info_clk_export => OPEN,
+ reg_ring_lane_info_reset_export => OPEN,
+ reg_ring_lane_info_address_export => reg_ring_lane_info_copi.address(c_sdp_reg_ring_lane_info_addr_w - 1 downto 0),
+ reg_ring_lane_info_write_export => reg_ring_lane_info_copi.wr,
+ reg_ring_lane_info_writedata_export => reg_ring_lane_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_lane_info_read_export => reg_ring_lane_info_copi.rd,
+ reg_ring_lane_info_readdata_export => reg_ring_lane_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_lane_clk_export => OPEN,
+ reg_dp_xonoff_lane_reset_export => OPEN,
+ reg_dp_xonoff_lane_address_export => reg_dp_xonoff_lane_copi.address(c_sdp_reg_dp_xonoff_lane_addr_w - 1 downto 0),
+ reg_dp_xonoff_lane_write_export => reg_dp_xonoff_lane_copi.wr,
+ reg_dp_xonoff_lane_writedata_export => reg_dp_xonoff_lane_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_lane_read_export => reg_dp_xonoff_lane_copi.rd,
+ reg_dp_xonoff_lane_readdata_export => reg_dp_xonoff_lane_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_local_clk_export => OPEN,
+ reg_dp_xonoff_local_reset_export => OPEN,
+ reg_dp_xonoff_local_address_export => reg_dp_xonoff_local_copi.address(c_sdp_reg_dp_xonoff_local_addr_w - 1 downto 0),
+ reg_dp_xonoff_local_write_export => reg_dp_xonoff_local_copi.wr,
+ reg_dp_xonoff_local_writedata_export => reg_dp_xonoff_local_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_local_read_export => reg_dp_xonoff_local_copi.rd,
+ reg_dp_xonoff_local_readdata_export => reg_dp_xonoff_local_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_err_clk_export => OPEN,
+ reg_dp_block_validate_err_reset_export => OPEN,
+ reg_dp_block_validate_err_address_export => reg_dp_block_validate_err_copi.address(c_sdp_reg_dp_block_validate_err_addr_w - 1 downto 0),
+ reg_dp_block_validate_err_write_export => reg_dp_block_validate_err_copi.wr,
+ reg_dp_block_validate_err_writedata_export => reg_dp_block_validate_err_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_err_read_export => reg_dp_block_validate_err_copi.rd,
+ reg_dp_block_validate_err_readdata_export => reg_dp_block_validate_err_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_bsn_at_sync_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_address_export => reg_dp_block_validate_bsn_at_sync_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_write_export => reg_dp_block_validate_bsn_at_sync_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_writedata_export => reg_dp_block_validate_bsn_at_sync_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_read_export => reg_dp_block_validate_bsn_at_sync_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_readdata_export => reg_dp_block_validate_bsn_at_sync_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_ring_info_clk_export => OPEN,
+ reg_ring_info_reset_export => OPEN,
+ reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w - 1 downto 0),
+ reg_ring_info_write_export => reg_ring_info_copi.wr,
+ reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_info_read_export => reg_ring_info_copi.rd,
+ reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_tr_10GbE_mac_clk_export => OPEN,
+ reg_tr_10GbE_mac_reset_export => OPEN,
+ reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w - 1 downto 0),
+ reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr,
+ reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd,
+ reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_tr_10GbE_eth10g_clk_export => OPEN,
+ reg_tr_10GbE_eth10g_reset_export => OPEN,
+ reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w - 1 downto 0),
+ reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr,
+ reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd,
+ reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_address_export => ram_scrap_copi.address(9 - 1 downto 0),
+ ram_scrap_write_export => ram_scrap_copi.wr,
+ ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_copi.rd,
+ ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index d30654d49c..7472297f11 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -19,7 +19,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_ring_pkg is
@@ -27,220 +27,220 @@ package qsys_lofar2_unb2b_ring_pkg is
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_ring is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_block_validate_err_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_read_export : out std_logic; -- export
- reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_write_export : out std_logic; -- export
- reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_local_clk_export : out std_logic; -- export
- reg_dp_xonoff_local_read_export : out std_logic; -- export
- reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_local_reset_export : out std_logic; -- export
- reg_dp_xonoff_local_write_export : out std_logic; -- export
- reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_ring_lane_info_clk_export : out std_logic; -- export
- reg_ring_lane_info_read_export : out std_logic; -- export
- reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_reset_export : out std_logic; -- export
- reg_ring_lane_info_write_export : out std_logic; -- export
- reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_ring;
+ component qsys_lofar2_unb2b_ring is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
+ ram_diag_bg_clk_export : out std_logic; -- export
+ ram_diag_bg_read_export : out std_logic; -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_reset_export : out std_logic; -- export
+ ram_diag_bg_write_export : out std_logic; -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_clk_export : out std_logic; -- export
+ reg_diag_bg_read_export : out std_logic; -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_reset_export : out std_logic; -- export
+ reg_diag_bg_write_export : out std_logic; -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_block_validate_err_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_local_clk_export : out std_logic; -- export
+ reg_dp_xonoff_local_read_export : out std_logic; -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_local_reset_export : out std_logic; -- export
+ reg_dp_xonoff_local_write_export : out std_logic; -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_ring_lane_info_clk_export : out std_logic; -- export
+ reg_ring_lane_info_read_export : out std_logic; -- export
+ reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_reset_export : out std_logic; -- export
+ reg_ring_lane_info_write_export : out std_logic; -- export
+ reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_ring;
end qsys_lofar2_unb2b_ring_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
index d8e3d80726..26332fb3e5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -33,22 +33,22 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.lofar2_unb2b_ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.lofar2_unb2b_ring_pkg.all;
entity tb_lofar2_unb2b_ring is
generic (
@@ -170,55 +170,55 @@ begin
------------------------------------------------------------------------------
gen_dut : for RN in 0 to g_nof_rn - 1 generate
u_lofar_unb2b_ring : entity work.lofar2_unb2b_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => g_unb_nr + (RN / c_quad),
- g_sim_node_nr => RN mod c_quad,
- g_sim_sync_timeout => c_sync_timeout
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2b_board_nof_chip_w) ),
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX(RN),
- QSFP_0_TX => i_QSFP_0_TX(RN),
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX(RN),
- RING_0_TX => i_RING_0_TX(RN),
- RING_1_RX => i_RING_1_RX(RN),
- RING_1_TX => i_RING_1_TX(RN),
- -- LEDs
- QSFP_LED => open
-
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => g_unb_nr + (RN / c_quad),
+ g_sim_node_nr => RN mod c_quad,
+ g_sim_sync_timeout => c_sync_timeout
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2b_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+ -- LEDs
+ QSFP_LED => open
+
+ );
end generate;
-- Ring connections
@@ -327,8 +327,8 @@ begin
-- Verify Access scheme 2,3 by reading rx / tx monitors on all RN
----------------------------------------------------------------------------
else
- -- Wait for bsn monitor to have received a sync period.
- mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
+ -- Wait for bsn monitor to have received a sync period.
+ mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
"SIGNED", rd_data, ">", 0, -- this is the wait until condition
1 us, tb_clk); -- read every 1 us
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
index d71e7bdcae..11955c5ea7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
@@ -29,9 +29,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_tb_lofar2_unb2b_ring is
end tb_tb_lofar2_unb2b_ring;
@@ -43,14 +43,14 @@ architecture tb of tb_tb_lofar2_unb2b_ring is
signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
begin
--- g_multi_tb : BOOLEAN := FALSE;
--- g_unb_nr : NATURAL := 4;
--- g_design_name : STRING := "lofar2_unb2c_ring_one";
--- g_nof_rn : NATURAL := 16;
--- g_nof_block_per_sync : NATURAL := 32;
--- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
+ -- g_multi_tb : BOOLEAN := FALSE;
+ -- g_unb_nr : NATURAL := 4;
+ -- g_design_name : STRING := "lofar2_unb2c_ring_one";
+ -- g_nof_rn : NATURAL := 16;
+ -- g_nof_block_per_sync : NATURAL := 32;
+ -- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
--- using different g_unb_nr to avoid MM file clashing.
+ -- using different g_unb_nr to avoid MM file clashing.
u_one_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 0, "lofar2_unb2b_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0)); -- access scheme 1.
u_one_2_3 : entity work.tb_lofar2_unb2b_ring generic map(true, 1, "lofar2_unb2b_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 2, "lofar2_unb2b_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2)); -- access scheme 1.
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
index b8a3553025..633bea65eb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2b_sdp_station_full is
generic (
@@ -91,7 +91,7 @@ entity disturb2_unb2b_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -128,67 +128,67 @@ begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
index 06248f9562..c461398e42 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
@@ -27,15 +27,15 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity disturb2_unb2b_sdp_station_full_wg is
@@ -104,61 +104,61 @@ architecture str of disturb2_unb2b_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
index 8b30fa74fd..d1abb51ad5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
@@ -63,20 +63,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_disturb2_unb2b_sdp_station_full_wg is
end tb_disturb2_unb2b_sdp_station_full_wg;
@@ -250,52 +250,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_disturb2_unb2b_sdp_station_full_wg : entity work.disturb2_unb2b_sdp_station_full_wg
- generic map (
- g_design_name => "disturb2_unb2b_sdp_station_full_wg",
- g_design_note => "SIM Disturb2 SDP station full design WG",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_wpfb_complex => c_wpfb_complex_sim
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_1_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_0,
-
- -- LEDs
- QSFP_LED => open
- );
-
- u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ generic map (
+ g_design_name => "disturb2_unb2b_sdp_station_full_wg",
+ g_design_note => "SIM Disturb2 SDP station full design WG",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_wpfb_complex => c_wpfb_complex_sim
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open
+ );
+
+ u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
port map (
refclk_644 => SA_CLK,
rst_in => pps_rst,
@@ -305,7 +305,7 @@ begin
rst_312 => open
);
- u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
+ u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_sim => true,
g_sim_level => 1,
@@ -475,14 +475,14 @@ begin
-- . get last beamlet of block
beamlet_arr2_re(v_beamlet_index_offset + c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block - 1) <= tr_10GbE_src_out.data(63 downto 56);
beamlet_arr2_im(v_beamlet_index_offset + c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block - 1) <= tr_10GbE_src_out.data(55 downto 48);
- -- Loop for next block in packet
+ -- Loop for next block in packet
end loop;
-- Make rx_beamlet_valid low for next header or after loop during verify.
-- Cannot wait one ext_clk cycle here to include last beamlet of block,
-- because next packet sop may follow immediately after this packet eop.
rx_beamlet_valid <= '0';
- -- Loop and wait for next packet.
+ -- Loop and wait for next packet.
end loop;
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
index e1cf5d4b90..4003c02121 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_adc is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2b_sdp_station_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -112,51 +112,51 @@ begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
index 415eb6e682..abab427126 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
@@ -44,19 +44,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_adc is
end tb_lofar2_unb2b_sdp_station_adc;
@@ -171,52 +171,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_adc : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_adc",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_adc",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
index ee4ec32e9d..1db614c734 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_bf is
generic (
@@ -82,7 +82,7 @@ entity lofar2_unb2b_sdp_station_bf is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -119,58 +119,58 @@ begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index 1d0a9613ed..35df18785c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -65,24 +65,24 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_sdp_station_bf is
generic (
@@ -143,16 +143,20 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
constant c_exp_beamlet_scale : natural := natural(g_beamlet_scale * real(c_sdp_unit_beamlet_scale)); -- c_sdp_unit_beamlet_scale = 2**15;
constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ TO_UVEC(
+ 3,
+ 6), -- antenna_field_index
+ TO_UVEC(
+ 601,
+ 10), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
-- WG
constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
@@ -382,126 +386,126 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_bf : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_1_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_0,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => dest_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => dest_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => true,
- g_sim_level => 1,
- g_nof_macs => 1,
- g_use_mdio => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM interface
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- -- DP interface
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- serial_rx_arr(0) => si_lpbk_0(0),
-
- src_out_arr(0) => tr_10GbE_src_out,
- src_in_arr(0) => tr_10GbE_src_in
- );
+ generic map (
+ g_sim => true,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => si_lpbk_0(0),
+
+ src_out_arr(0) => tr_10GbE_src_out,
+ src_in_arr(0) => tr_10GbE_src_in
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_octet_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
-
- snk_in_arr(0) => tr_10GbE_src_out,
- snk_out_arr(0) => tr_10GbE_src_in,
-
- src_out_arr(0) => test_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_octet_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
+
+ snk_in_arr(0) => tr_10GbE_src_out,
+ snk_out_arr(0) => tr_10GbE_src_in,
+
+ src_out_arr(0) => test_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
index 44fb9e2230..87d96910b7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
@@ -39,19 +39,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_bf_bst_offload is
end tb_lofar2_unb2b_sdp_station_bf_bst_offload;
@@ -153,52 +153,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_bf : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -244,10 +244,10 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
index 7ec3d86fa0..2df61399b6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_fsub is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2b_sdp_station_fsub is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -111,51 +111,51 @@ begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index 8527173e38..7089fea2a8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -59,19 +59,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
entity tb_lofar2_unb2b_sdp_station_fsub is
generic (
@@ -248,53 +248,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_fsub : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_fsub",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
-- Raw or weighted subbands
exp_subband_ampl <= sel_a_b(sst_offload_weighted_subbands = '0', c_exp_subband_ampl_raw, c_exp_subband_ampl_weighted);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
index 14f55f913c..dc387106c8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
@@ -38,19 +38,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_fsub_sst_offload is
end tb_lofar2_unb2b_sdp_station_fsub_sst_offload;
@@ -152,52 +152,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_fsub : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_fsub",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -243,10 +243,10 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
index 10bb1a1329..4bbce4b2f3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_full is
generic (
@@ -91,7 +91,7 @@ entity lofar2_unb2b_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -128,67 +128,67 @@ begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
index d2000d761e..04bcf78bce 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_full_wg is
generic (
@@ -99,59 +99,59 @@ architecture str of lofar2_unb2b_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
index 3fd7c6e5f7..004fb056b6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_xsub_one is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2b_sdp_station_xsub_one is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -111,51 +111,51 @@ begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index 91392de7bb..3a67f1e3bb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -46,19 +46,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_xsub_one is
end tb_lofar2_unb2b_sdp_station_xsub_one;
@@ -180,53 +180,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_xsub_one : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
index fc89b3f07f..9e37aee052 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -39,19 +39,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload is
end tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload;
@@ -152,52 +152,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_xsub_one : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -255,10 +255,10 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
index bdc156ac01..7f635b195b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_xsub_ring is
generic (
@@ -91,7 +91,7 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -128,67 +128,67 @@ begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index aaf28671a3..d1b7eb65c2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -46,20 +46,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_xsub_ring is
end tb_lofar2_unb2b_sdp_station_xsub_ring;
@@ -196,65 +196,65 @@ begin
------------------------------------------------------------------------------
gen_dut : for RN in 0 to c_nof_rn - 1 generate
u_lofar_unb2b_sdp_station_xsub_ring : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_xsub_ring",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr + (RN / c_quad),
- g_sim_node_nr => RN mod c_quad,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2b_board_nof_chip_w) ),
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX(RN),
- QSFP_0_TX => i_QSFP_0_TX(RN),
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX(RN),
- RING_0_TX => i_RING_0_TX(RN),
- RING_1_RX => i_RING_1_RX(RN),
- RING_1_TX => i_RING_1_TX(RN),
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_ring",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr + (RN / c_quad),
+ g_sim_node_nr => RN mod c_quad,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2b_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
end generate;
-- Ring connections
@@ -320,18 +320,18 @@ begin
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_LANE_INFO_XST", I * 2 + 1, c_nof_rn - 1, tb_clk);
end loop;
- ----------------------------------------------------------------------------
- -- Disable unused streams in dp_bsn_align_v2
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Disable unused streams in dp_bsn_align_v2
+ ----------------------------------------------------------------------------
for I in 0 to c_sdp_P_sq - 1 loop
if I >= c_P_sq then
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_ALIGN_V2_XSUB", I, 0, tb_clk);
end if;
end loop;
- ----------------------------------------------------------------------------
- -- Crosslets Info
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Crosslets Info
+ ----------------------------------------------------------------------------
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 0, integer(c_subband_sp_0), tb_clk); -- offset
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 15, 0 , tb_clk); -- stepsize
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index df3f7acae0..98f6fc16db 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -27,20 +27,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_sdp_station_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_sdp_station_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2b_sdp_station is
@@ -105,9 +105,9 @@ entity lofar2_unb2b_sdp_station is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0'); -- c_sdp_S_pn = 12, c_unb2b_board_nof_tr_jesd204b = 6
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -491,315 +491,315 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_copi,
- reg_unb_sens_miso => reg_unb_sens_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
- reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_copi,
+ reg_unb_sens_miso => reg_unb_sens_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_sdp_station
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_unb_sens_copi => reg_unb_sens_copi,
- reg_unb_sens_cipo => reg_unb_sens_cipo,
- reg_unb_pmbus_copi => reg_unb_pmbus_copi,
- reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo,
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_unb_sens_copi => reg_unb_sens_copi,
+ reg_unb_sens_cipo => reg_unb_sens_cipo,
+ reg_unb_pmbus_copi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
+ );
-- Use full 8 bit gn_id = ID
@@ -809,200 +809,200 @@ begin
-- sdp nodes
-----------------------------------------------------------------------------
u_sdp_station : entity lofar2_sdp_lib.sdp_station
- generic map (
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_scope_selected_subband => g_scope_selected_subband,
- g_no_jesd => c_revision_select.no_jesd,
- g_use_fsub => c_revision_select.use_fsub,
- g_use_oversample => c_revision_select.use_oversample,
- g_use_xsub => c_revision_select.use_xsub,
- g_use_bf => c_revision_select.use_bf,
- g_use_ring => c_revision_select.use_ring,
- g_P_sq => c_revision_select.P_sq
- )
- port map (
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_pps => dp_pps,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- gn_id => gn_id,
- this_bck_id => this_bck_id,
- this_chip_id => this_chip_id,
-
- SA_CLK => SA_CLK,
-
- -- jesd204b
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => JESD204B_SYNC_N,
-
- -- UDP Offload
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- -- 10 GbE
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-
- -- AIT
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-
- -- FSUB
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
-
- -- SDP Info
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
-
- -- RING Info
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
-
- -- XSUB
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- -- BF
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
-
- -- SST
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- -- XST
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-
- -- BST
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- RING_0_TX => RING_0_TX,
- RING_0_RX => RING_0_RX,
- RING_1_TX => RING_1_TX,
- RING_1_RX => RING_1_RX,
-
- -- QSFP serial
- unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
-
- -- QSFP LEDS
- unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_scope_selected_subband => g_scope_selected_subband,
+ g_no_jesd => c_revision_select.no_jesd,
+ g_use_fsub => c_revision_select.use_fsub,
+ g_use_oversample => c_revision_select.use_oversample,
+ g_use_xsub => c_revision_select.use_xsub,
+ g_use_bf => c_revision_select.use_bf,
+ g_use_ring => c_revision_select.use_ring,
+ g_P_sq => c_revision_select.P_sq
+ )
+ port map (
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_pps => dp_pps,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ gn_id => gn_id,
+ this_bck_id => this_bck_id,
+ this_chip_id => this_chip_id,
+
+ SA_CLK => SA_CLK,
+
+ -- jesd204b
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N,
+
+ -- UDP Offload
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ -- 10 GbE
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+
+ -- AIT
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+
+ -- FSUB
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+
+ -- SDP Info
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+
+ -- RING Info
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+
+ -- XSUB
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ -- BF
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
+ -- SST
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ -- XST
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+
+ -- BST
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ RING_0_TX => RING_0_TX,
+ RING_0_RX => RING_0_RX,
+ RING_1_TX => RING_1_TX,
+ RING_1_RX => RING_1_RX,
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
@@ -1016,41 +1016,41 @@ begin
-- Front IO
------------
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- LEDs
------------
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index e8670d3d44..0e33cbe577 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -20,14 +20,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_sdp_station_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -53,7 +53,7 @@ package lofar2_unb2b_sdp_station_pkg is
constant c_full_os : t_lofar2_unb2b_sdp_station_config := (false, true, true, true, true, true, 9);
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_sdp_station_config;
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_sdp_station_config;
end lofar2_unb2b_sdp_station_pkg;
@@ -61,7 +61,7 @@ end lofar2_unb2b_sdp_station_pkg;
package body lofar2_unb2b_sdp_station_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_sdp_station_config is
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2b_sdp_station_config is
begin
if g_design_name = "lofar2_unb2b_sdp_station_adc" then return c_ait;
elsif g_design_name = "lofar2_unb2b_sdp_station_fsub" then return c_fsub;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index feaf68b374..a5438f4373 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_sdp_station_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_sdp_station_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_sdp_station is
generic (
@@ -150,187 +150,187 @@ entity mmm_lofar2_unb2b_sdp_station is
reg_si_copi : out t_mem_copi;
reg_si_cipo : in t_mem_cipo;
- -- Equalizer gains
- ram_equalizer_gains_copi : out t_mem_copi;
- ram_equalizer_gains_cipo : in t_mem_cipo;
- ram_equalizer_gains_cross_copi : out t_mem_copi;
- ram_equalizer_gains_cross_cipo : in t_mem_cipo;
+ -- Equalizer gains
+ ram_equalizer_gains_copi : out t_mem_copi;
+ ram_equalizer_gains_cipo : in t_mem_cipo;
+ ram_equalizer_gains_cross_copi : out t_mem_copi;
+ ram_equalizer_gains_cross_cipo : in t_mem_cipo;
- -- DP Selector
- reg_dp_selector_copi : out t_mem_copi;
- reg_dp_selector_cipo : in t_mem_cipo;
+ -- DP Selector
+ reg_dp_selector_copi : out t_mem_copi;
+ reg_dp_selector_cipo : in t_mem_cipo;
- -- SDP Info
- reg_sdp_info_copi : out t_mem_copi;
- reg_sdp_info_cipo : in t_mem_cipo;
+ -- SDP Info
+ reg_sdp_info_copi : out t_mem_copi;
+ reg_sdp_info_cipo : in t_mem_cipo;
- -- RING Info
- reg_ring_info_copi : out t_mem_copi;
- reg_ring_info_cipo : in t_mem_cipo;
+ -- RING Info
+ reg_ring_info_copi : out t_mem_copi;
+ reg_ring_info_cipo : in t_mem_cipo;
- -- Beamlet Subband Select
- ram_ss_ss_wide_copi : out t_mem_copi;
- ram_ss_ss_wide_cipo : in t_mem_cipo;
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_copi : out t_mem_copi;
+ ram_ss_ss_wide_cipo : in t_mem_cipo;
- -- Local BF bf weights
- ram_bf_weights_copi : out t_mem_copi;
- ram_bf_weights_cipo : in t_mem_cipo;
+ -- Local BF bf weights
+ ram_bf_weights_copi : out t_mem_copi;
+ ram_bf_weights_cipo : in t_mem_cipo;
- -- BF bsn aligner_v2
- reg_bsn_align_v2_bf_copi : out t_mem_copi;
- reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : out t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
- -- BF bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
-
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_copi : out t_mem_copi;
- reg_bf_scale_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output header fields
- reg_hdr_dat_copi : out t_mem_copi;
- reg_hdr_dat_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_copi : out t_mem_copi;
- reg_dp_xonoff_cipo : in t_mem_cipo;
-
- -- BF ring lane info
- reg_ring_lane_info_bf_copi : out t_mem_copi;
- reg_ring_lane_info_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
-
- -- BF ring validate err
- reg_dp_block_validate_err_bf_copi : out t_mem_copi;
- reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics (BST)
- ram_st_bst_copi : out t_mem_copi;
- ram_st_bst_cipo : in t_mem_cipo;
-
- -- Subband Statistics offload
- reg_stat_enable_sst_copi : out t_mem_copi;
- reg_stat_enable_sst_cipo : in t_mem_cipo;
-
- -- Statistics header info
- reg_stat_hdr_dat_sst_copi : out t_mem_copi;
- reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics offload
- reg_stat_enable_xst_copi : out t_mem_copi;
- reg_stat_enable_xst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_copi : out t_mem_copi;
- reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics offload
- reg_stat_enable_bst_copi : out t_mem_copi;
- reg_stat_enable_bst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_copi : out t_mem_copi;
- reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_crosslets_info_copi : out t_mem_copi;
- reg_crosslets_info_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_nof_crosslets_copi : out t_mem_copi;
- reg_nof_crosslets_cipo : in t_mem_cipo;
-
- -- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
- reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
-
- -- st_xsq (XST)
- ram_st_xsq_copi : out t_mem_copi;
- ram_st_xsq_cipo : in t_mem_cipo;
-
- -- 10 GbE mac
- reg_nw_10GbE_mac_copi : out t_mem_copi;
- reg_nw_10GbE_mac_cipo : in t_mem_cipo;
-
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_copi : out t_mem_copi;
- reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2
- reg_bsn_align_v2_xsub_copi : out t_mem_copi;
- reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
-
- -- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
-
- -- BST UDP offload bsn monitor
- reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
-
- -- Beamlet output bsn monitor
- reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
- reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
-
- -- SST UDP offload bsn monitor
- reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
-
- -- XST ring lane info
- reg_ring_lane_info_xst_copi : out t_mem_copi;
- reg_ring_lane_info_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
-
- -- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
-
- -- XST ring validate err
- reg_dp_block_validate_err_xst_copi : out t_mem_copi;
- reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
-
- -- XST ring MAC
- reg_tr_10GbE_mac_copi : out t_mem_copi;
- reg_tr_10GbE_mac_cipo : in t_mem_cipo;
-
- -- XST ring ETH
- reg_tr_10GbE_eth10g_copi : out t_mem_copi;
- reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- Scrap ram
- ram_scrap_copi : out t_mem_copi;
- ram_scrap_cipo : in t_mem_cipo;
-
- -- Jesd reset control
- jesd_ctrl_copi : out t_mem_copi;
- jesd_ctrl_cipo : in t_mem_cipo
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
+
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_copi : out t_mem_copi;
+ reg_bf_scale_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_copi : out t_mem_copi;
+ reg_hdr_dat_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_copi : out t_mem_copi;
+ reg_dp_xonoff_cipo : in t_mem_cipo;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : out t_mem_copi;
+ reg_ring_lane_info_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics (BST)
+ ram_st_bst_copi : out t_mem_copi;
+ ram_st_bst_cipo : in t_mem_cipo;
+
+ -- Subband Statistics offload
+ reg_stat_enable_sst_copi : out t_mem_copi;
+ reg_stat_enable_sst_cipo : in t_mem_cipo;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics offload
+ reg_stat_enable_xst_copi : out t_mem_copi;
+ reg_stat_enable_xst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics header info
+ reg_stat_hdr_dat_xst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics offload
+ reg_stat_enable_bst_copi : out t_mem_copi;
+ reg_stat_enable_bst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics header info
+ reg_stat_hdr_dat_bst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_crosslets_info_copi : out t_mem_copi;
+ reg_crosslets_info_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_nof_crosslets_copi : out t_mem_copi;
+ reg_nof_crosslets_cipo : in t_mem_cipo;
+
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
+
+ -- st_xsq (XST)
+ ram_st_xsq_copi : out t_mem_copi;
+ ram_st_xsq_cipo : in t_mem_cipo;
+
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_copi : out t_mem_copi;
+ reg_nw_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_copi : out t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2
+ reg_bsn_align_v2_xsub_copi : out t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
+
+ -- XST UDP offload bsn monitor
+ reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
+
+ -- Beamlet output bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
+
+ -- XST ring lane info
+ reg_ring_lane_info_xst_copi : out t_mem_copi;
+ reg_ring_lane_info_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
+
+ -- XST ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
+
+ -- XST ring validate err
+ reg_dp_block_validate_err_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
+
+ -- XST ring MAC
+ reg_tr_10GbE_mac_copi : out t_mem_copi;
+ reg_tr_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- XST ring ETH
+ reg_tr_10GbE_eth10g_copi : out t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- Scrap ram
+ ram_scrap_copi : out t_mem_copi;
+ ram_scrap_cipo : in t_mem_cipo;
+
+ -- Jesd reset control
+ jesd_ctrl_copi : out t_mem_copi;
+ jesd_ctrl_cipo : in t_mem_cipo
);
end mmm_lofar2_unb2b_sdp_station;
@@ -350,213 +350,213 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
+ port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
-- Must use exact g_mm_rd_latency = 1 instead of default 2, because JESD204B IP forces rddata = 0 after it has been read
u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
- port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+ port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
u_mm_file_pio_jesd_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
- port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+ port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+ port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
+ port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
+ port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
u_mm_file_ram_st_histogram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
+ port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
+ port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
+ port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
+ port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
+ port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
+ port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
u_mm_file_ram_equalizer_gains_cross : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
+ port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
+ port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
+ port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
+ port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
+ port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
+ port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
+ port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
u_mm_file_reg_stat_enable_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
+ port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
u_mm_file_reg_stat_hdr_info_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
u_mm_file_reg_stat_enable_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
+ port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
u_mm_file_reg_stat_hdr_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
u_mm_file_reg_stat_enable_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
+ port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
u_mm_file_reg_stat_hdr_info_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
u_mm_file_reg_crosslets_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
+ port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
u_mm_file_reg_nof_crosslets : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
+ port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
+ port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
u_mm_file_ram_st_xsq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
+ port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
u_mm_file_reg_bsn_align_v2_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
u_mm_file_reg_ring_lane_info_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
- port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
+ port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
u_mm_file_reg_dp_block_validate_err_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
u_mm_file_reg_bsn_align_v2_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
u_mm_file_reg_ring_lane_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
+ port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
u_mm_file_reg_dp_block_validate_err_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -571,636 +571,636 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2b_sdp_station
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_copi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_copi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_copi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_copi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_copi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
- rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_copi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_copi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_copi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_copi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_copi.wr,
- pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_copi.rd,
- pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_copi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_copi.wr,
- reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_copi.rd,
- reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_copi.wr,
- reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_copi.rd,
- reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w - 1 downto 0),
-
- jesd204b_reset_export => OPEN,
- jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_copi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
- jesd204b_write_export => jesd204b_copi.wr,
- jesd204b_writedata_export => jesd204b_copi.wrdata(c_word_w - 1 downto 0),
- jesd204b_read_export => jesd204b_copi.rd,
- jesd204b_readdata_export => jesd204b_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_jesd_ctrl_reset_export => OPEN,
- pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_copi.address(c_sdp_jesd_ctrl_addr_w - 1 downto 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_copi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_copi.wrdata(c_word_w - 1 downto 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_copi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_copi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
- reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_copi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_copi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_copi.wrdata(c_word_w - 1 downto 0),
-
- -- waveform generators (multiplexed)
- reg_wg_clk_export => OPEN,
- reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_copi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
- reg_wg_read_export => reg_wg_copi.rd,
- reg_wg_readdata_export => reg_wg_cipo.rddata(c_word_w - 1 downto 0),
- reg_wg_write_export => reg_wg_copi.wr,
- reg_wg_writedata_export => reg_wg_copi.wrdata(c_word_w - 1 downto 0),
-
- ram_wg_clk_export => OPEN,
- ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_copi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
- ram_wg_read_export => ram_wg_copi.rd,
- ram_wg_readdata_export => ram_wg_cipo.rddata(c_word_w - 1 downto 0),
- ram_wg_write_export => ram_wg_copi.wr,
- ram_wg_writedata_export => ram_wg_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_dp_shiftram_clk_export => OPEN,
- reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_copi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_copi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_cipo.rddata(c_word_w - 1 downto 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_copi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_source_v2_clk_export => OPEN,
- reg_bsn_source_v2_reset_export => OPEN,
- reg_bsn_source_v2_address_export => reg_bsn_source_v2_copi.address(c_sdp_reg_bsn_source_v2_addr_w - 1 downto 0),
- reg_bsn_source_v2_read_export => reg_bsn_source_v2_copi.rd,
- reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_source_v2_write_export => reg_bsn_source_v2_copi.wr,
- reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_scheduler_clk_export => OPEN,
- reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_copi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_copi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_copi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_copi.wr,
- reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_copi.rd,
- reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_bsn_clk_export => OPEN,
- ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_copi.address(c_sdp_ram_diag_data_buf_bsn_addr_w - 1 downto 0),
- ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_copi.wr,
- ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_copi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_copi.rd,
- ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_bsn_reset_export => OPEN,
- reg_diag_data_buffer_bsn_clk_export => OPEN,
- reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_copi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
- reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_copi.wr,
- reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_copi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_copi.rd,
- reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_st_histogram_clk_export => OPEN,
- ram_st_histogram_reset_export => OPEN,
- ram_st_histogram_address_export => ram_st_histogram_copi.address(c_sdp_ram_st_histogram_addr_w - 1 downto 0),
- ram_st_histogram_write_export => ram_st_histogram_copi.wr,
- ram_st_histogram_writedata_export => ram_st_histogram_copi.wrdata(c_word_w - 1 downto 0),
- ram_st_histogram_read_export => ram_st_histogram_copi.rd,
- ram_st_histogram_readdata_export => ram_st_histogram_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_aduh_monitor_reset_export => OPEN,
- reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_copi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_copi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_copi.wrdata(c_word_w - 1 downto 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_copi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_fil_coefs_clk_export => OPEN,
- ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_copi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
- ram_fil_coefs_write_export => ram_fil_coefs_copi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_copi.wrdata(c_word_w - 1 downto 0),
- ram_fil_coefs_read_export => ram_fil_coefs_copi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_st_sst_clk_export => OPEN,
- ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_copi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
- ram_st_sst_write_export => ram_st_sst_copi.wr,
- ram_st_sst_writedata_export => ram_st_sst_copi.wrdata(c_word_w - 1 downto 0),
- ram_st_sst_read_export => ram_st_sst_copi.rd,
- ram_st_sst_readdata_export => ram_st_sst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_si_clk_export => OPEN,
- reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_copi.address(c_sdp_reg_si_addr_w - 1 downto 0),
- reg_si_write_export => reg_si_copi.wr,
- reg_si_writedata_export => reg_si_copi.wrdata(c_word_w - 1 downto 0),
- reg_si_read_export => reg_si_copi.rd,
- reg_si_readdata_export => reg_si_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_equalizer_gains_clk_export => OPEN,
- ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_copi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_copi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_copi.wrdata(c_word_w - 1 downto 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_equalizer_gains_cross_clk_export => OPEN,
- ram_equalizer_gains_cross_reset_export => OPEN,
- ram_equalizer_gains_cross_address_export => ram_equalizer_gains_cross_copi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
- ram_equalizer_gains_cross_write_export => ram_equalizer_gains_cross_copi.wr,
- ram_equalizer_gains_cross_writedata_export => ram_equalizer_gains_cross_copi.wrdata(c_word_w - 1 downto 0),
- ram_equalizer_gains_cross_read_export => ram_equalizer_gains_cross_copi.rd,
- ram_equalizer_gains_cross_readdata_export => ram_equalizer_gains_cross_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_selector_clk_export => OPEN,
- reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
- reg_dp_selector_write_export => reg_dp_selector_copi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_selector_read_export => reg_dp_selector_copi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_sdp_info_clk_export => OPEN,
- reg_sdp_info_reset_export => OPEN,
- reg_sdp_info_address_export => reg_sdp_info_copi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
- reg_sdp_info_write_export => reg_sdp_info_copi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_sdp_info_read_export => reg_sdp_info_copi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_ring_info_clk_export => OPEN,
- reg_ring_info_reset_export => OPEN,
- reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w - 1 downto 0),
- reg_ring_info_write_export => reg_ring_info_copi.wr,
- reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_info_read_export => reg_ring_info_copi.rd,
- reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_ss_ss_wide_clk_export => OPEN,
- ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_address_export => ram_ss_ss_wide_copi.address(c_sdp_ram_ss_ss_wide_addr_w - 1 downto 0),
- ram_ss_ss_wide_write_export => ram_ss_ss_wide_copi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_copi.wrdata(c_word_w - 1 downto 0),
- ram_ss_ss_wide_read_export => ram_ss_ss_wide_copi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_bf_weights_clk_export => OPEN,
- ram_bf_weights_reset_export => OPEN,
- ram_bf_weights_address_export => ram_bf_weights_copi.address(c_sdp_ram_bf_weights_addr_w - 1 downto 0),
- ram_bf_weights_write_export => ram_bf_weights_copi.wr,
- ram_bf_weights_writedata_export => ram_bf_weights_copi.wrdata(c_word_w - 1 downto 0),
- ram_bf_weights_read_export => ram_bf_weights_copi.rd,
- ram_bf_weights_readdata_export => ram_bf_weights_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bf_scale_clk_export => OPEN,
- reg_bf_scale_reset_export => OPEN,
- reg_bf_scale_address_export => reg_bf_scale_copi.address(c_sdp_reg_bf_scale_addr_w - 1 downto 0),
- reg_bf_scale_write_export => reg_bf_scale_copi.wr,
- reg_bf_scale_writedata_export => reg_bf_scale_copi.wrdata(c_word_w - 1 downto 0),
- reg_bf_scale_read_export => reg_bf_scale_copi.rd,
- reg_bf_scale_readdata_export => reg_bf_scale_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_hdr_dat_clk_export => OPEN,
- reg_hdr_dat_reset_export => OPEN,
- reg_hdr_dat_address_export => reg_hdr_dat_copi.address(c_sdp_reg_bf_hdr_dat_addr_w - 1 downto 0),
- reg_hdr_dat_write_export => reg_hdr_dat_copi.wr,
- reg_hdr_dat_writedata_export => reg_hdr_dat_copi.wrdata(c_word_w - 1 downto 0),
- reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
- reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_clk_export => OPEN,
- reg_dp_xonoff_reset_export => OPEN,
- reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w - 1 downto 0),
- reg_dp_xonoff_write_export => reg_dp_xonoff_copi.wr,
- reg_dp_xonoff_writedata_export => reg_dp_xonoff_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_xonoff_read_export => reg_dp_xonoff_copi.rd,
- reg_dp_xonoff_readdata_export => reg_dp_xonoff_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_st_bst_clk_export => OPEN,
- ram_st_bst_reset_export => OPEN,
- ram_st_bst_address_export => ram_st_bst_copi.address(c_sdp_ram_st_bst_addr_w - 1 downto 0),
- ram_st_bst_write_export => ram_st_bst_copi.wr,
- ram_st_bst_writedata_export => ram_st_bst_copi.wrdata(c_word_w - 1 downto 0),
- ram_st_bst_read_export => ram_st_bst_copi.rd,
- ram_st_bst_readdata_export => ram_st_bst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_enable_sst_clk_export => OPEN,
- reg_stat_enable_sst_reset_export => OPEN,
- reg_stat_enable_sst_address_export => reg_stat_enable_sst_copi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
- reg_stat_enable_sst_write_export => reg_stat_enable_sst_copi.wr,
- reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_enable_sst_read_export => reg_stat_enable_sst_copi.rd,
- reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_hdr_dat_sst_clk_export => OPEN,
- reg_stat_hdr_dat_sst_reset_export => OPEN,
- reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
- reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_copi.wr,
- reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_copi.rd,
- reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_enable_xst_clk_export => OPEN,
- reg_stat_enable_xst_reset_export => OPEN,
- reg_stat_enable_xst_address_export => reg_stat_enable_xst_copi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
- reg_stat_enable_xst_write_export => reg_stat_enable_xst_copi.wr,
- reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_enable_xst_read_export => reg_stat_enable_xst_copi.rd,
- reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_hdr_dat_xst_clk_export => OPEN,
- reg_stat_hdr_dat_xst_reset_export => OPEN,
- reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
- reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_copi.wr,
- reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_copi.rd,
- reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_enable_bst_clk_export => OPEN,
- reg_stat_enable_bst_reset_export => OPEN,
- reg_stat_enable_bst_address_export => reg_stat_enable_bst_copi.address(c_sdp_reg_stat_enable_bst_addr_w - 1 downto 0),
- reg_stat_enable_bst_write_export => reg_stat_enable_bst_copi.wr,
- reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_enable_bst_read_export => reg_stat_enable_bst_copi.rd,
- reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_hdr_dat_bst_clk_export => OPEN,
- reg_stat_hdr_dat_bst_reset_export => OPEN,
- reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_copi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w - 1 downto 0),
- reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_copi.wr,
- reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_copi.rd,
- reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_crosslets_info_clk_export => OPEN,
- reg_crosslets_info_reset_export => OPEN,
- reg_crosslets_info_address_export => reg_crosslets_info_copi.address(c_sdp_reg_crosslets_info_addr_w - 1 downto 0),
- reg_crosslets_info_write_export => reg_crosslets_info_copi.wr,
- reg_crosslets_info_writedata_export => reg_crosslets_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_crosslets_info_read_export => reg_crosslets_info_copi.rd,
- reg_crosslets_info_readdata_export => reg_crosslets_info_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_nof_crosslets_clk_export => OPEN,
- reg_nof_crosslets_reset_export => OPEN,
- reg_nof_crosslets_address_export => reg_nof_crosslets_copi.address(c_sdp_reg_nof_crosslets_addr_w - 1 downto 0),
- reg_nof_crosslets_write_export => reg_nof_crosslets_copi.wr,
- reg_nof_crosslets_writedata_export => reg_nof_crosslets_copi.wrdata(c_word_w - 1 downto 0),
- reg_nof_crosslets_read_export => reg_nof_crosslets_copi.rd,
- reg_nof_crosslets_readdata_export => reg_nof_crosslets_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
- reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
- reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_copi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w - 1 downto 0),
- reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_copi.wr,
- reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_copi.rd,
- reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_st_xsq_clk_export => OPEN,
- ram_st_xsq_reset_export => OPEN,
- ram_st_xsq_address_export => ram_st_xsq_copi.address(c_sdp_ram_st_xsq_arr_addr_w - 1 downto 0),
- ram_st_xsq_write_export => ram_st_xsq_copi.wr,
- ram_st_xsq_writedata_export => ram_st_xsq_copi.wrdata(c_word_w - 1 downto 0),
- ram_st_xsq_read_export => ram_st_xsq_copi.rd,
- ram_st_xsq_readdata_export => ram_st_xsq_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_nw_10GbE_mac_clk_export => OPEN,
- reg_nw_10GbE_mac_reset_export => OPEN,
- reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_copi.address(c_sdp_reg_nw_10GbE_mac_addr_w - 1 downto 0),
- reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_copi.wr,
- reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
- reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_copi.rd,
- reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_nw_10GbE_eth10g_clk_export => OPEN,
- reg_nw_10GbE_eth10g_reset_export => OPEN,
- reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_copi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w - 1 downto 0),
- reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_copi.wr,
- reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
- reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
- reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_align_v2_bf_clk_export => OPEN,
- reg_bsn_align_v2_bf_reset_export => OPEN,
- reg_bsn_align_v2_bf_address_export => reg_bsn_align_v2_bf_copi.address(c_sdp_reg_bsn_align_v2_bf_addr_w - 1 downto 0),
- reg_bsn_align_v2_bf_write_export => reg_bsn_align_v2_bf_copi.wr,
- reg_bsn_align_v2_bf_writedata_export => reg_bsn_align_v2_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_align_v2_bf_read_export => reg_bsn_align_v2_bf_copi.rd,
- reg_bsn_align_v2_bf_readdata_export => reg_bsn_align_v2_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_rx_align_bf_clk_export => OPEN,
- reg_bsn_monitor_v2_rx_align_bf_reset_export => OPEN,
- reg_bsn_monitor_v2_rx_align_bf_address_export => reg_bsn_monitor_v2_rx_align_bf_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_align_bf_write_export => reg_bsn_monitor_v2_rx_align_bf_copi.wr,
- reg_bsn_monitor_v2_rx_align_bf_writedata_export => reg_bsn_monitor_v2_rx_align_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_align_bf_read_export => reg_bsn_monitor_v2_rx_align_bf_copi.rd,
- reg_bsn_monitor_v2_rx_align_bf_readdata_export => reg_bsn_monitor_v2_rx_align_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_aligned_bf_clk_export => OPEN,
- reg_bsn_monitor_v2_aligned_bf_reset_export => OPEN,
- reg_bsn_monitor_v2_aligned_bf_address_export => reg_bsn_monitor_v2_aligned_bf_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_aligned_bf_write_export => reg_bsn_monitor_v2_aligned_bf_copi.wr,
- reg_bsn_monitor_v2_aligned_bf_writedata_export => reg_bsn_monitor_v2_aligned_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_aligned_bf_read_export => reg_bsn_monitor_v2_aligned_bf_copi.rd,
- reg_bsn_monitor_v2_aligned_bf_readdata_export => reg_bsn_monitor_v2_aligned_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_align_v2_xsub_clk_export => OPEN,
- reg_bsn_align_v2_xsub_reset_export => OPEN,
- reg_bsn_align_v2_xsub_address_export => reg_bsn_align_v2_xsub_copi.address(c_sdp_reg_bsn_align_v2_xsub_addr_w - 1 downto 0),
- reg_bsn_align_v2_xsub_write_export => reg_bsn_align_v2_xsub_copi.wr,
- reg_bsn_align_v2_xsub_writedata_export => reg_bsn_align_v2_xsub_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_align_v2_xsub_read_export => reg_bsn_align_v2_xsub_copi.rd,
- reg_bsn_align_v2_xsub_readdata_export => reg_bsn_align_v2_xsub_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_rx_align_xsub_clk_export => OPEN,
- reg_bsn_monitor_v2_rx_align_xsub_reset_export => OPEN,
- reg_bsn_monitor_v2_rx_align_xsub_address_export => reg_bsn_monitor_v2_rx_align_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_align_xsub_write_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wr,
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_align_xsub_read_export => reg_bsn_monitor_v2_rx_align_xsub_copi.rd,
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export => reg_bsn_monitor_v2_rx_align_xsub_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_aligned_xsub_clk_export => OPEN,
- reg_bsn_monitor_v2_aligned_xsub_reset_export => OPEN,
- reg_bsn_monitor_v2_aligned_xsub_address_export => reg_bsn_monitor_v2_aligned_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_aligned_xsub_write_export => reg_bsn_monitor_v2_aligned_xsub_copi.wr,
- reg_bsn_monitor_v2_aligned_xsub_writedata_export => reg_bsn_monitor_v2_aligned_xsub_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_aligned_xsub_read_export => reg_bsn_monitor_v2_aligned_xsub_copi.rd,
- reg_bsn_monitor_v2_aligned_xsub_readdata_export => reg_bsn_monitor_v2_aligned_xsub_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
- reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
- reg_bsn_monitor_v2_sst_offload_address_export => reg_bsn_monitor_v2_sst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_sst_offload_write_export => reg_bsn_monitor_v2_sst_offload_copi.wr,
- reg_bsn_monitor_v2_sst_offload_writedata_export => reg_bsn_monitor_v2_sst_offload_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_sst_offload_read_export => reg_bsn_monitor_v2_sst_offload_copi.rd,
- reg_bsn_monitor_v2_sst_offload_readdata_export => reg_bsn_monitor_v2_sst_offload_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_bst_offload_clk_export => OPEN,
- reg_bsn_monitor_v2_bst_offload_reset_export => OPEN,
- reg_bsn_monitor_v2_bst_offload_address_export => reg_bsn_monitor_v2_bst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_bst_offload_write_export => reg_bsn_monitor_v2_bst_offload_copi.wr,
- reg_bsn_monitor_v2_bst_offload_writedata_export => reg_bsn_monitor_v2_bst_offload_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_bst_offload_read_export => reg_bsn_monitor_v2_bst_offload_copi.rd,
- reg_bsn_monitor_v2_bst_offload_readdata_export => reg_bsn_monitor_v2_bst_offload_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_beamlet_output_clk_export => OPEN,
- reg_bsn_monitor_v2_beamlet_output_reset_export => OPEN,
- reg_bsn_monitor_v2_beamlet_output_address_export => reg_bsn_monitor_v2_beamlet_output_copi.address(c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_beamlet_output_write_export => reg_bsn_monitor_v2_beamlet_output_copi.wr,
- reg_bsn_monitor_v2_beamlet_output_writedata_export => reg_bsn_monitor_v2_beamlet_output_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_beamlet_output_read_export => reg_bsn_monitor_v2_beamlet_output_copi.rd,
- reg_bsn_monitor_v2_beamlet_output_readdata_export => reg_bsn_monitor_v2_beamlet_output_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_xst_offload_clk_export => OPEN,
- reg_bsn_monitor_v2_xst_offload_reset_export => OPEN,
- reg_bsn_monitor_v2_xst_offload_address_export => reg_bsn_monitor_v2_xst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_xst_offload_write_export => reg_bsn_monitor_v2_xst_offload_copi.wr,
- reg_bsn_monitor_v2_xst_offload_writedata_export => reg_bsn_monitor_v2_xst_offload_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_xst_offload_read_export => reg_bsn_monitor_v2_xst_offload_copi.rd,
- reg_bsn_monitor_v2_xst_offload_readdata_export => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_ring_lane_info_bf_clk_export => OPEN,
- reg_ring_lane_info_bf_reset_export => OPEN,
- reg_ring_lane_info_bf_address_export => reg_ring_lane_info_bf_copi.address(c_sdp_reg_ring_lane_info_bf_addr_w - 1 downto 0),
- reg_ring_lane_info_bf_write_export => reg_ring_lane_info_bf_copi.wr,
- reg_ring_lane_info_bf_writedata_export => reg_ring_lane_info_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_lane_info_bf_read_export => reg_ring_lane_info_bf_copi.rd,
- reg_ring_lane_info_bf_readdata_export => reg_ring_lane_info_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_rx_bf_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_bf_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_bf_address_export => reg_bsn_monitor_v2_ring_rx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_bf_write_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wr,
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_bf_read_export => reg_bsn_monitor_v2_ring_rx_bf_copi.rd,
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export => reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_tx_bf_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_bf_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_bf_address_export => reg_bsn_monitor_v2_ring_tx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_bf_write_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wr,
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_bf_read_export => reg_bsn_monitor_v2_ring_tx_bf_copi.rd,
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export => reg_bsn_monitor_v2_ring_tx_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_err_bf_clk_export => OPEN,
- reg_dp_block_validate_err_bf_reset_export => OPEN,
- reg_dp_block_validate_err_bf_address_export => reg_dp_block_validate_err_bf_copi.address(c_sdp_reg_dp_block_validate_err_bf_addr_w - 1 downto 0),
- reg_dp_block_validate_err_bf_write_export => reg_dp_block_validate_err_bf_copi.wr,
- reg_dp_block_validate_err_bf_writedata_export => reg_dp_block_validate_err_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_err_bf_read_export => reg_dp_block_validate_err_bf_copi.rd,
- reg_dp_block_validate_err_bf_readdata_export => reg_dp_block_validate_err_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_bsn_at_sync_bf_clk_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_bf_reset_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_bf_address_export => reg_dp_block_validate_bsn_at_sync_bf_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_bf_write_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wr,
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_bf_read_export => reg_dp_block_validate_bsn_at_sync_bf_copi.rd,
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export => reg_dp_block_validate_bsn_at_sync_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_ring_lane_info_xst_clk_export => OPEN,
- reg_ring_lane_info_xst_reset_export => OPEN,
- reg_ring_lane_info_xst_address_export => reg_ring_lane_info_xst_copi.address(c_sdp_reg_ring_lane_info_xst_addr_w - 1 downto 0),
- reg_ring_lane_info_xst_write_export => reg_ring_lane_info_xst_copi.wr,
- reg_ring_lane_info_xst_writedata_export => reg_ring_lane_info_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_lane_info_xst_read_export => reg_ring_lane_info_xst_copi.rd,
- reg_ring_lane_info_xst_readdata_export => reg_ring_lane_info_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_rx_xst_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_xst_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_xst_address_export => reg_bsn_monitor_v2_ring_rx_xst_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_xst_write_export => reg_bsn_monitor_v2_ring_rx_xst_copi.wr,
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export => reg_bsn_monitor_v2_ring_rx_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_xst_read_export => reg_bsn_monitor_v2_ring_rx_xst_copi.rd,
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export => reg_bsn_monitor_v2_ring_rx_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_tx_xst_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_xst_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_xst_address_export => reg_bsn_monitor_v2_ring_tx_xst_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_xst_write_export => reg_bsn_monitor_v2_ring_tx_xst_copi.wr,
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export => reg_bsn_monitor_v2_ring_tx_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_xst_read_export => reg_bsn_monitor_v2_ring_tx_xst_copi.rd,
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export => reg_bsn_monitor_v2_ring_tx_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_err_xst_clk_export => OPEN,
- reg_dp_block_validate_err_xst_reset_export => OPEN,
- reg_dp_block_validate_err_xst_address_export => reg_dp_block_validate_err_xst_copi.address(c_sdp_reg_dp_block_validate_err_xst_addr_w - 1 downto 0),
- reg_dp_block_validate_err_xst_write_export => reg_dp_block_validate_err_xst_copi.wr,
- reg_dp_block_validate_err_xst_writedata_export => reg_dp_block_validate_err_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_err_xst_read_export => reg_dp_block_validate_err_xst_copi.rd,
- reg_dp_block_validate_err_xst_readdata_export => reg_dp_block_validate_err_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_bsn_at_sync_xst_clk_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_xst_reset_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_xst_address_export => reg_dp_block_validate_bsn_at_sync_xst_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_xst_write_export => reg_dp_block_validate_bsn_at_sync_xst_copi.wr,
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export => reg_dp_block_validate_bsn_at_sync_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_xst_read_export => reg_dp_block_validate_bsn_at_sync_xst_copi.rd,
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export => reg_dp_block_validate_bsn_at_sync_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_tr_10GbE_mac_clk_export => OPEN,
- reg_tr_10GbE_mac_reset_export => OPEN,
- reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w - 1 downto 0),
- reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr,
- reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd,
- reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_tr_10GbE_eth10g_clk_export => OPEN,
- reg_tr_10GbE_eth10g_reset_export => OPEN,
- reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w - 1 downto 0),
- reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr,
- reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd,
- reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_scrap_clk_export => OPEN,
- ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_copi.address(9 - 1 downto 0),
- ram_scrap_write_export => ram_scrap_copi.wr,
- ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_copi.rd,
- ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_copi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_copi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_copi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_copi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_copi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ -- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_copi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_copi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_copi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_copi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_copi.wr,
+ pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_copi.rd,
+ pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_copi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_copi.wr,
+ reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_copi.rd,
+ reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_copi.wr,
+ reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_copi.rd,
+ reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w - 1 downto 0),
+
+ jesd204b_reset_export => OPEN,
+ jesd204b_clk_export => OPEN,
+ jesd204b_address_export => jesd204b_copi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
+ jesd204b_write_export => jesd204b_copi.wr,
+ jesd204b_writedata_export => jesd204b_copi.wrdata(c_word_w - 1 downto 0),
+ jesd204b_read_export => jesd204b_copi.rd,
+ jesd204b_readdata_export => jesd204b_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_jesd_ctrl_reset_export => OPEN,
+ pio_jesd_ctrl_clk_export => OPEN,
+ pio_jesd_ctrl_address_export => jesd_ctrl_copi.address(c_sdp_jesd_ctrl_addr_w - 1 downto 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_copi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_copi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_copi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
+ reg_bsn_monitor_input_clk_export => OPEN,
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_copi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_input_reset_export => OPEN,
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_copi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_copi.wrdata(c_word_w - 1 downto 0),
+
+ -- waveform generators (multiplexed)
+ reg_wg_clk_export => OPEN,
+ reg_wg_reset_export => OPEN,
+ reg_wg_address_export => reg_wg_copi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
+ reg_wg_read_export => reg_wg_copi.rd,
+ reg_wg_readdata_export => reg_wg_cipo.rddata(c_word_w - 1 downto 0),
+ reg_wg_write_export => reg_wg_copi.wr,
+ reg_wg_writedata_export => reg_wg_copi.wrdata(c_word_w - 1 downto 0),
+
+ ram_wg_clk_export => OPEN,
+ ram_wg_reset_export => OPEN,
+ ram_wg_address_export => ram_wg_copi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
+ ram_wg_read_export => ram_wg_copi.rd,
+ ram_wg_readdata_export => ram_wg_cipo.rddata(c_word_w - 1 downto 0),
+ ram_wg_write_export => ram_wg_copi.wr,
+ ram_wg_writedata_export => ram_wg_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_dp_shiftram_clk_export => OPEN,
+ reg_dp_shiftram_reset_export => OPEN,
+ reg_dp_shiftram_address_export => reg_dp_shiftram_copi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_copi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_cipo.rddata(c_word_w - 1 downto 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_copi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_source_v2_clk_export => OPEN,
+ reg_bsn_source_v2_reset_export => OPEN,
+ reg_bsn_source_v2_address_export => reg_bsn_source_v2_copi.address(c_sdp_reg_bsn_source_v2_addr_w - 1 downto 0),
+ reg_bsn_source_v2_read_export => reg_bsn_source_v2_copi.rd,
+ reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_source_v2_write_export => reg_bsn_source_v2_copi.wr,
+ reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_scheduler_clk_export => OPEN,
+ reg_bsn_scheduler_reset_export => OPEN,
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_copi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_copi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_copi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_copi.wr,
+ reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_copi.rd,
+ reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_bsn_clk_export => OPEN,
+ ram_diag_data_buffer_bsn_reset_export => OPEN,
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_copi.address(c_sdp_ram_diag_data_buf_bsn_addr_w - 1 downto 0),
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_copi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_copi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_copi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_bsn_reset_export => OPEN,
+ reg_diag_data_buffer_bsn_clk_export => OPEN,
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_copi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_copi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_copi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_copi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_st_histogram_clk_export => OPEN,
+ ram_st_histogram_reset_export => OPEN,
+ ram_st_histogram_address_export => ram_st_histogram_copi.address(c_sdp_ram_st_histogram_addr_w - 1 downto 0),
+ ram_st_histogram_write_export => ram_st_histogram_copi.wr,
+ ram_st_histogram_writedata_export => ram_st_histogram_copi.wrdata(c_word_w - 1 downto 0),
+ ram_st_histogram_read_export => ram_st_histogram_copi.rd,
+ ram_st_histogram_readdata_export => ram_st_histogram_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_aduh_monitor_reset_export => OPEN,
+ reg_aduh_monitor_clk_export => OPEN,
+ reg_aduh_monitor_address_export => reg_aduh_monitor_copi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_copi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_copi.wrdata(c_word_w - 1 downto 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_copi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_fil_coefs_clk_export => OPEN,
+ ram_fil_coefs_reset_export => OPEN,
+ ram_fil_coefs_address_export => ram_fil_coefs_copi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_copi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_copi.wrdata(c_word_w - 1 downto 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_copi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_st_sst_clk_export => OPEN,
+ ram_st_sst_reset_export => OPEN,
+ ram_st_sst_address_export => ram_st_sst_copi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
+ ram_st_sst_write_export => ram_st_sst_copi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_copi.wrdata(c_word_w - 1 downto 0),
+ ram_st_sst_read_export => ram_st_sst_copi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_si_clk_export => OPEN,
+ reg_si_reset_export => OPEN,
+ reg_si_address_export => reg_si_copi.address(c_sdp_reg_si_addr_w - 1 downto 0),
+ reg_si_write_export => reg_si_copi.wr,
+ reg_si_writedata_export => reg_si_copi.wrdata(c_word_w - 1 downto 0),
+ reg_si_read_export => reg_si_copi.rd,
+ reg_si_readdata_export => reg_si_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_equalizer_gains_clk_export => OPEN,
+ ram_equalizer_gains_reset_export => OPEN,
+ ram_equalizer_gains_address_export => ram_equalizer_gains_copi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_copi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_copi.wrdata(c_word_w - 1 downto 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_equalizer_gains_cross_clk_export => OPEN,
+ ram_equalizer_gains_cross_reset_export => OPEN,
+ ram_equalizer_gains_cross_address_export => ram_equalizer_gains_cross_copi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
+ ram_equalizer_gains_cross_write_export => ram_equalizer_gains_cross_copi.wr,
+ ram_equalizer_gains_cross_writedata_export => ram_equalizer_gains_cross_copi.wrdata(c_word_w - 1 downto 0),
+ ram_equalizer_gains_cross_read_export => ram_equalizer_gains_cross_copi.rd,
+ ram_equalizer_gains_cross_readdata_export => ram_equalizer_gains_cross_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_selector_clk_export => OPEN,
+ reg_dp_selector_reset_export => OPEN,
+ reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
+ reg_dp_selector_write_export => reg_dp_selector_copi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_selector_read_export => reg_dp_selector_copi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_sdp_info_clk_export => OPEN,
+ reg_sdp_info_reset_export => OPEN,
+ reg_sdp_info_address_export => reg_sdp_info_copi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
+ reg_sdp_info_write_export => reg_sdp_info_copi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_sdp_info_read_export => reg_sdp_info_copi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_ring_info_clk_export => OPEN,
+ reg_ring_info_reset_export => OPEN,
+ reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w - 1 downto 0),
+ reg_ring_info_write_export => reg_ring_info_copi.wr,
+ reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_info_read_export => reg_ring_info_copi.rd,
+ reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_ss_ss_wide_clk_export => OPEN,
+ ram_ss_ss_wide_reset_export => OPEN,
+ ram_ss_ss_wide_address_export => ram_ss_ss_wide_copi.address(c_sdp_ram_ss_ss_wide_addr_w - 1 downto 0),
+ ram_ss_ss_wide_write_export => ram_ss_ss_wide_copi.wr,
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_copi.wrdata(c_word_w - 1 downto 0),
+ ram_ss_ss_wide_read_export => ram_ss_ss_wide_copi.rd,
+ ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_bf_weights_clk_export => OPEN,
+ ram_bf_weights_reset_export => OPEN,
+ ram_bf_weights_address_export => ram_bf_weights_copi.address(c_sdp_ram_bf_weights_addr_w - 1 downto 0),
+ ram_bf_weights_write_export => ram_bf_weights_copi.wr,
+ ram_bf_weights_writedata_export => ram_bf_weights_copi.wrdata(c_word_w - 1 downto 0),
+ ram_bf_weights_read_export => ram_bf_weights_copi.rd,
+ ram_bf_weights_readdata_export => ram_bf_weights_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bf_scale_clk_export => OPEN,
+ reg_bf_scale_reset_export => OPEN,
+ reg_bf_scale_address_export => reg_bf_scale_copi.address(c_sdp_reg_bf_scale_addr_w - 1 downto 0),
+ reg_bf_scale_write_export => reg_bf_scale_copi.wr,
+ reg_bf_scale_writedata_export => reg_bf_scale_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bf_scale_read_export => reg_bf_scale_copi.rd,
+ reg_bf_scale_readdata_export => reg_bf_scale_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_hdr_dat_clk_export => OPEN,
+ reg_hdr_dat_reset_export => OPEN,
+ reg_hdr_dat_address_export => reg_hdr_dat_copi.address(c_sdp_reg_bf_hdr_dat_addr_w - 1 downto 0),
+ reg_hdr_dat_write_export => reg_hdr_dat_copi.wr,
+ reg_hdr_dat_writedata_export => reg_hdr_dat_copi.wrdata(c_word_w - 1 downto 0),
+ reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
+ reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_clk_export => OPEN,
+ reg_dp_xonoff_reset_export => OPEN,
+ reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w - 1 downto 0),
+ reg_dp_xonoff_write_export => reg_dp_xonoff_copi.wr,
+ reg_dp_xonoff_writedata_export => reg_dp_xonoff_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_read_export => reg_dp_xonoff_copi.rd,
+ reg_dp_xonoff_readdata_export => reg_dp_xonoff_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_st_bst_clk_export => OPEN,
+ ram_st_bst_reset_export => OPEN,
+ ram_st_bst_address_export => ram_st_bst_copi.address(c_sdp_ram_st_bst_addr_w - 1 downto 0),
+ ram_st_bst_write_export => ram_st_bst_copi.wr,
+ ram_st_bst_writedata_export => ram_st_bst_copi.wrdata(c_word_w - 1 downto 0),
+ ram_st_bst_read_export => ram_st_bst_copi.rd,
+ ram_st_bst_readdata_export => ram_st_bst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_enable_sst_clk_export => OPEN,
+ reg_stat_enable_sst_reset_export => OPEN,
+ reg_stat_enable_sst_address_export => reg_stat_enable_sst_copi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
+ reg_stat_enable_sst_write_export => reg_stat_enable_sst_copi.wr,
+ reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_enable_sst_read_export => reg_stat_enable_sst_copi.rd,
+ reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_hdr_dat_sst_clk_export => OPEN,
+ reg_stat_hdr_dat_sst_reset_export => OPEN,
+ reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
+ reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_copi.wr,
+ reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_copi.rd,
+ reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_enable_xst_clk_export => OPEN,
+ reg_stat_enable_xst_reset_export => OPEN,
+ reg_stat_enable_xst_address_export => reg_stat_enable_xst_copi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
+ reg_stat_enable_xst_write_export => reg_stat_enable_xst_copi.wr,
+ reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_enable_xst_read_export => reg_stat_enable_xst_copi.rd,
+ reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_hdr_dat_xst_clk_export => OPEN,
+ reg_stat_hdr_dat_xst_reset_export => OPEN,
+ reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
+ reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_copi.wr,
+ reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_copi.rd,
+ reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_enable_bst_clk_export => OPEN,
+ reg_stat_enable_bst_reset_export => OPEN,
+ reg_stat_enable_bst_address_export => reg_stat_enable_bst_copi.address(c_sdp_reg_stat_enable_bst_addr_w - 1 downto 0),
+ reg_stat_enable_bst_write_export => reg_stat_enable_bst_copi.wr,
+ reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_enable_bst_read_export => reg_stat_enable_bst_copi.rd,
+ reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_hdr_dat_bst_clk_export => OPEN,
+ reg_stat_hdr_dat_bst_reset_export => OPEN,
+ reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_copi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w - 1 downto 0),
+ reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_copi.wr,
+ reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_copi.rd,
+ reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_crosslets_info_clk_export => OPEN,
+ reg_crosslets_info_reset_export => OPEN,
+ reg_crosslets_info_address_export => reg_crosslets_info_copi.address(c_sdp_reg_crosslets_info_addr_w - 1 downto 0),
+ reg_crosslets_info_write_export => reg_crosslets_info_copi.wr,
+ reg_crosslets_info_writedata_export => reg_crosslets_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_crosslets_info_read_export => reg_crosslets_info_copi.rd,
+ reg_crosslets_info_readdata_export => reg_crosslets_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_nof_crosslets_clk_export => OPEN,
+ reg_nof_crosslets_reset_export => OPEN,
+ reg_nof_crosslets_address_export => reg_nof_crosslets_copi.address(c_sdp_reg_nof_crosslets_addr_w - 1 downto 0),
+ reg_nof_crosslets_write_export => reg_nof_crosslets_copi.wr,
+ reg_nof_crosslets_writedata_export => reg_nof_crosslets_copi.wrdata(c_word_w - 1 downto 0),
+ reg_nof_crosslets_read_export => reg_nof_crosslets_copi.rd,
+ reg_nof_crosslets_readdata_export => reg_nof_crosslets_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_copi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w - 1 downto 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_copi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_copi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_st_xsq_clk_export => OPEN,
+ ram_st_xsq_reset_export => OPEN,
+ ram_st_xsq_address_export => ram_st_xsq_copi.address(c_sdp_ram_st_xsq_arr_addr_w - 1 downto 0),
+ ram_st_xsq_write_export => ram_st_xsq_copi.wr,
+ ram_st_xsq_writedata_export => ram_st_xsq_copi.wrdata(c_word_w - 1 downto 0),
+ ram_st_xsq_read_export => ram_st_xsq_copi.rd,
+ ram_st_xsq_readdata_export => ram_st_xsq_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_nw_10GbE_mac_clk_export => OPEN,
+ reg_nw_10GbE_mac_reset_export => OPEN,
+ reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_copi.address(c_sdp_reg_nw_10GbE_mac_addr_w - 1 downto 0),
+ reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_copi.wr,
+ reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
+ reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_copi.rd,
+ reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_nw_10GbE_eth10g_clk_export => OPEN,
+ reg_nw_10GbE_eth10g_reset_export => OPEN,
+ reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_copi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w - 1 downto 0),
+ reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_copi.wr,
+ reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
+ reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
+ reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_align_v2_bf_clk_export => OPEN,
+ reg_bsn_align_v2_bf_reset_export => OPEN,
+ reg_bsn_align_v2_bf_address_export => reg_bsn_align_v2_bf_copi.address(c_sdp_reg_bsn_align_v2_bf_addr_w - 1 downto 0),
+ reg_bsn_align_v2_bf_write_export => reg_bsn_align_v2_bf_copi.wr,
+ reg_bsn_align_v2_bf_writedata_export => reg_bsn_align_v2_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_align_v2_bf_read_export => reg_bsn_align_v2_bf_copi.rd,
+ reg_bsn_align_v2_bf_readdata_export => reg_bsn_align_v2_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_rx_align_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_address_export => reg_bsn_monitor_v2_rx_align_bf_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_align_bf_write_export => reg_bsn_monitor_v2_rx_align_bf_copi.wr,
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export => reg_bsn_monitor_v2_rx_align_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_align_bf_read_export => reg_bsn_monitor_v2_rx_align_bf_copi.rd,
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export => reg_bsn_monitor_v2_rx_align_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_aligned_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_address_export => reg_bsn_monitor_v2_aligned_bf_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_aligned_bf_write_export => reg_bsn_monitor_v2_aligned_bf_copi.wr,
+ reg_bsn_monitor_v2_aligned_bf_writedata_export => reg_bsn_monitor_v2_aligned_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_aligned_bf_read_export => reg_bsn_monitor_v2_aligned_bf_copi.rd,
+ reg_bsn_monitor_v2_aligned_bf_readdata_export => reg_bsn_monitor_v2_aligned_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_align_v2_xsub_clk_export => OPEN,
+ reg_bsn_align_v2_xsub_reset_export => OPEN,
+ reg_bsn_align_v2_xsub_address_export => reg_bsn_align_v2_xsub_copi.address(c_sdp_reg_bsn_align_v2_xsub_addr_w - 1 downto 0),
+ reg_bsn_align_v2_xsub_write_export => reg_bsn_align_v2_xsub_copi.wr,
+ reg_bsn_align_v2_xsub_writedata_export => reg_bsn_align_v2_xsub_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_align_v2_xsub_read_export => reg_bsn_align_v2_xsub_copi.rd,
+ reg_bsn_align_v2_xsub_readdata_export => reg_bsn_align_v2_xsub_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_address_export => reg_bsn_monitor_v2_rx_align_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_align_xsub_write_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wr,
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_align_xsub_read_export => reg_bsn_monitor_v2_rx_align_xsub_copi.rd,
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export => reg_bsn_monitor_v2_rx_align_xsub_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_aligned_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_address_export => reg_bsn_monitor_v2_aligned_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_aligned_xsub_write_export => reg_bsn_monitor_v2_aligned_xsub_copi.wr,
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export => reg_bsn_monitor_v2_aligned_xsub_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_aligned_xsub_read_export => reg_bsn_monitor_v2_aligned_xsub_copi.rd,
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export => reg_bsn_monitor_v2_aligned_xsub_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_address_export => reg_bsn_monitor_v2_sst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_sst_offload_write_export => reg_bsn_monitor_v2_sst_offload_copi.wr,
+ reg_bsn_monitor_v2_sst_offload_writedata_export => reg_bsn_monitor_v2_sst_offload_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_sst_offload_read_export => reg_bsn_monitor_v2_sst_offload_copi.rd,
+ reg_bsn_monitor_v2_sst_offload_readdata_export => reg_bsn_monitor_v2_sst_offload_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_bst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_address_export => reg_bsn_monitor_v2_bst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_bst_offload_write_export => reg_bsn_monitor_v2_bst_offload_copi.wr,
+ reg_bsn_monitor_v2_bst_offload_writedata_export => reg_bsn_monitor_v2_bst_offload_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_bst_offload_read_export => reg_bsn_monitor_v2_bst_offload_copi.rd,
+ reg_bsn_monitor_v2_bst_offload_readdata_export => reg_bsn_monitor_v2_bst_offload_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_beamlet_output_clk_export => OPEN,
+ reg_bsn_monitor_v2_beamlet_output_reset_export => OPEN,
+ reg_bsn_monitor_v2_beamlet_output_address_export => reg_bsn_monitor_v2_beamlet_output_copi.address(c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_beamlet_output_write_export => reg_bsn_monitor_v2_beamlet_output_copi.wr,
+ reg_bsn_monitor_v2_beamlet_output_writedata_export => reg_bsn_monitor_v2_beamlet_output_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_beamlet_output_read_export => reg_bsn_monitor_v2_beamlet_output_copi.rd,
+ reg_bsn_monitor_v2_beamlet_output_readdata_export => reg_bsn_monitor_v2_beamlet_output_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_xst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_xst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_xst_offload_address_export => reg_bsn_monitor_v2_xst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_xst_offload_write_export => reg_bsn_monitor_v2_xst_offload_copi.wr,
+ reg_bsn_monitor_v2_xst_offload_writedata_export => reg_bsn_monitor_v2_xst_offload_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_xst_offload_read_export => reg_bsn_monitor_v2_xst_offload_copi.rd,
+ reg_bsn_monitor_v2_xst_offload_readdata_export => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_ring_lane_info_bf_clk_export => OPEN,
+ reg_ring_lane_info_bf_reset_export => OPEN,
+ reg_ring_lane_info_bf_address_export => reg_ring_lane_info_bf_copi.address(c_sdp_reg_ring_lane_info_bf_addr_w - 1 downto 0),
+ reg_ring_lane_info_bf_write_export => reg_ring_lane_info_bf_copi.wr,
+ reg_ring_lane_info_bf_writedata_export => reg_ring_lane_info_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_lane_info_bf_read_export => reg_ring_lane_info_bf_copi.rd,
+ reg_ring_lane_info_bf_readdata_export => reg_ring_lane_info_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_address_export => reg_bsn_monitor_v2_ring_rx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_bf_write_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_bf_read_export => reg_bsn_monitor_v2_ring_rx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export => reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_address_export => reg_bsn_monitor_v2_ring_tx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_bf_write_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_bf_read_export => reg_bsn_monitor_v2_ring_tx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export => reg_bsn_monitor_v2_ring_tx_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_err_bf_clk_export => OPEN,
+ reg_dp_block_validate_err_bf_reset_export => OPEN,
+ reg_dp_block_validate_err_bf_address_export => reg_dp_block_validate_err_bf_copi.address(c_sdp_reg_dp_block_validate_err_bf_addr_w - 1 downto 0),
+ reg_dp_block_validate_err_bf_write_export => reg_dp_block_validate_err_bf_copi.wr,
+ reg_dp_block_validate_err_bf_writedata_export => reg_dp_block_validate_err_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_err_bf_read_export => reg_dp_block_validate_err_bf_copi.rd,
+ reg_dp_block_validate_err_bf_readdata_export => reg_dp_block_validate_err_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_address_export => reg_dp_block_validate_bsn_at_sync_bf_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_bf_write_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_bf_read_export => reg_dp_block_validate_bsn_at_sync_bf_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export => reg_dp_block_validate_bsn_at_sync_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_ring_lane_info_xst_clk_export => OPEN,
+ reg_ring_lane_info_xst_reset_export => OPEN,
+ reg_ring_lane_info_xst_address_export => reg_ring_lane_info_xst_copi.address(c_sdp_reg_ring_lane_info_xst_addr_w - 1 downto 0),
+ reg_ring_lane_info_xst_write_export => reg_ring_lane_info_xst_copi.wr,
+ reg_ring_lane_info_xst_writedata_export => reg_ring_lane_info_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_lane_info_xst_read_export => reg_ring_lane_info_xst_copi.rd,
+ reg_ring_lane_info_xst_readdata_export => reg_ring_lane_info_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_xst_address_export => reg_bsn_monitor_v2_ring_rx_xst_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_xst_write_export => reg_bsn_monitor_v2_ring_rx_xst_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export => reg_bsn_monitor_v2_ring_rx_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_xst_read_export => reg_bsn_monitor_v2_ring_rx_xst_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export => reg_bsn_monitor_v2_ring_rx_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_xst_address_export => reg_bsn_monitor_v2_ring_tx_xst_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_xst_write_export => reg_bsn_monitor_v2_ring_tx_xst_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export => reg_bsn_monitor_v2_ring_tx_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_xst_read_export => reg_bsn_monitor_v2_ring_tx_xst_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export => reg_bsn_monitor_v2_ring_tx_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_err_xst_clk_export => OPEN,
+ reg_dp_block_validate_err_xst_reset_export => OPEN,
+ reg_dp_block_validate_err_xst_address_export => reg_dp_block_validate_err_xst_copi.address(c_sdp_reg_dp_block_validate_err_xst_addr_w - 1 downto 0),
+ reg_dp_block_validate_err_xst_write_export => reg_dp_block_validate_err_xst_copi.wr,
+ reg_dp_block_validate_err_xst_writedata_export => reg_dp_block_validate_err_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_err_xst_read_export => reg_dp_block_validate_err_xst_copi.rd,
+ reg_dp_block_validate_err_xst_readdata_export => reg_dp_block_validate_err_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_xst_address_export => reg_dp_block_validate_bsn_at_sync_xst_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_xst_write_export => reg_dp_block_validate_bsn_at_sync_xst_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export => reg_dp_block_validate_bsn_at_sync_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_xst_read_export => reg_dp_block_validate_bsn_at_sync_xst_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export => reg_dp_block_validate_bsn_at_sync_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_tr_10GbE_mac_clk_export => OPEN,
+ reg_tr_10GbE_mac_reset_export => OPEN,
+ reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w - 1 downto 0),
+ reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr,
+ reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd,
+ reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_tr_10GbE_eth10g_clk_export => OPEN,
+ reg_tr_10GbE_eth10g_reset_export => OPEN,
+ reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w - 1 downto 0),
+ reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr,
+ reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd,
+ reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_address_export => ram_scrap_copi.address(9 - 1 downto 0),
+ ram_scrap_write_export => ram_scrap_copi.wr,
+ ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_copi.rd,
+ ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index d9693c5838..61c8ec794a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -19,563 +19,563 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_sdp_station_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_sdp_station is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_sdp_station;
+ component qsys_lofar2_unb2b_sdp_station is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_sdp_station;
end qsys_lofar2_unb2b_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
index bb7bc1ceff..8f292aa483 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -31,20 +31,20 @@
-- c_eth_check_nof_packets = 1 instead of S_pn = 12.
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use eth_lib.eth_pkg.all;
entity tb_lofar2_unb2b_sdp_station is
end tb_lofar2_unb2b_sdp_station;
@@ -73,7 +73,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station is
constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
--- . 1GbE output
+ -- . 1GbE output
constant c_eth_check_nof_packets : natural := 1;
constant c_eth_runtime_timeout : time := 300 us;
@@ -143,52 +143,52 @@ begin
-- >> DUT <<
u_lofar_unb2b_sdp_station : entity work.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
---------------------------------------------------------------------------------------------------------------------
-- Stimuli
@@ -248,13 +248,13 @@ begin
-- >> Verify proper DUT output using Ethernet packet statistics <<
u_eth_statistics : entity eth_lib.eth_statistics
- generic map (
- g_runtime_nof_packets => c_eth_check_nof_packets,
- g_runtime_timeout => c_eth_runtime_timeout
- )
- port map (
- eth_serial_in => eth_txp(0),
- tb_end => eth_done
- );
+ generic map (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
index a40ce9956b..01c9fe5c83 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, lofar2_ddrctrl_lib, tech_ddr_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use diag_lib.diag_pkg.all;
@@ -77,10 +77,10 @@ entity lofar2_unb2c_ddrctrl is
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou
- -- SO-DIMM Memory Bank II
- --MB_II_IN : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
- --MB_II_IO : INOUT t_tech_ddr4_phy_io;
- --MB_II_OU : OUT t_tech_ddr4_phy_ou;
+ -- SO-DIMM Memory Bank II
+ --MB_II_IN : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ --MB_II_IO : INOUT t_tech_ddr4_phy_io;
+ --MB_II_OU : OUT t_tech_ddr4_phy_ou;
);
@@ -270,86 +270,86 @@ begin
u_bsn_source_v2 : entity dp_lib.mms_dp_bsn_source_v2
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_clk_per_sync => c_bsn_nof_clk_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_v2_mosi,
- reg_miso => reg_bsn_source_v2_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi,
-
- bs_restart => open
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_clk_per_sync => c_bsn_nof_clk_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_v2_mosi,
+ reg_miso => reg_bsn_source_v2_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi,
+
+ bs_restart => open
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_mosi,
- reg_miso => reg_bsn_scheduler_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_mosi,
+ reg_miso => reg_bsn_scheduler_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => c_nof_streams,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_wideband_arr_mosi,
- reg_miso => reg_wg_wideband_arr_miso,
-
- buf_mosi => ram_wg_wideband_arr_mosi,
- buf_miso => ram_wg_wideband_arr_miso,
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_wideband_arr_mosi,
+ reg_miso => reg_wg_wideband_arr_miso,
+
+ buf_mosi => ram_wg_wideband_arr_mosi,
+ buf_miso => ram_wg_wideband_arr_miso,
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
gen_concat : for I in 0 to c_sdp_S_pn - 1 generate
@@ -362,403 +362,403 @@ begin
u_stop_in_reg : entity common_lib.mms_common_reg
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_stop_in_mosi,
- reg_miso => reg_stop_in_miso,
+ reg_mosi => reg_stop_in_mosi,
+ reg_miso => reg_stop_in_miso,
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
- in_reg => stop_in_arr,
- out_reg => stop_in_arr
- );
+ in_reg => stop_in_arr,
+ out_reg => stop_in_arr
+ );
u_ddrctrl_ctrl_state_reg : entity common_lib.mms_common_reg
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_ddrctrl_ctrl_state_mosi,
- reg_miso => reg_ddrctrl_ctrl_state_miso,
+ reg_mosi => reg_ddrctrl_ctrl_state_mosi,
+ reg_miso => reg_ddrctrl_ctrl_state_miso,
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
- in_reg => ddrctrl_ctrl_state,
- out_reg => open
- );
+ in_reg => ddrctrl_ctrl_state,
+ out_reg => open
+ );
u_ddrctrl : entity lofar2_ddrctrl_lib.ddrctrl
- generic map (
- g_tech_ddr => c_tech_ddr,
- g_sim_model => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_stop_percentage => c_stop_percentage,
- g_block_size => c_bs_block_size
- )
- port map (
- clk => st_clk,
- rst => st_rst,
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- in_sosi_arr => st_sosi_arr,
- stop_in => stop_in_arr(0),
- out_sosi_arr => out_sosi_arr_ddrctrl,
- out_siso => out_siso,
- ddrctrl_ctrl_state => ddrctrl_ctrl_state,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- --PHY
- phy3_in => phy3_in,
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr,
+ g_sim_model => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_stop_percentage => c_stop_percentage,
+ g_block_size => c_bs_block_size
+ )
+ port map (
+ clk => st_clk,
+ rst => st_rst,
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ in_sosi_arr => st_sosi_arr,
+ stop_in => stop_in_arr(0),
+ out_sosi_arr => out_sosi_arr_ddrctrl,
+ out_siso => out_siso,
+ ddrctrl_ctrl_state => ddrctrl_ctrl_state,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ --PHY
+ phy3_in => phy3_in,
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU
+ );
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
-
- -- General
- g_nof_streams => c_nof_streams,
-
- -- DB settings
- g_data_type => c_data_type,
- g_data_w => c_word_w,
- g_buf_nof_data => c_buf_nof_words,
- g_buf_use_sync => false,
- g_use_steps => false,
- g_nof_steps => c_diag_seq_rx_reg_nof_steps
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_data_buf_mosi => reg_data_buf_mosi,
- reg_data_buf_miso => reg_data_buf_miso,
-
- ram_data_buf_mosi => ram_data_buf_mosi,
- ram_data_buf_miso => ram_data_buf_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- in_sync => st_pps,
- in_sosi_arr => in_sosi_arr_data_buf,
- out_wr_done_arr => out_wr_data_done_arr
- );
+ generic map (
+ g_technology => g_technology,
+
+ -- General
+ g_nof_streams => c_nof_streams,
+
+ -- DB settings
+ g_data_type => c_data_type,
+ g_data_w => c_word_w,
+ g_buf_nof_data => c_buf_nof_words,
+ g_buf_use_sync => false,
+ g_use_steps => false,
+ g_nof_steps => c_diag_seq_rx_reg_nof_steps
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_data_buf_mosi => reg_data_buf_mosi,
+ reg_data_buf_miso => reg_data_buf_miso,
+
+ ram_data_buf_mosi => ram_data_buf_mosi,
+ ram_data_buf_miso => ram_data_buf_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ in_sync => st_pps,
+ in_sosi_arr => in_sosi_arr_data_buf,
+ out_wr_done_arr => out_wr_data_done_arr
+ );
u_diag_bsn_buffer : entity diag_lib.mms_diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
-
- -- General
- g_nof_streams => c_nof_streams,
-
- -- DB settings
- g_data_type => c_bsn_type,
- g_data_w => c_dp_stream_bsn_w,
- g_buf_nof_data => c_buf_nof_words,
- g_buf_use_sync => false,
- g_use_steps => false,
- g_nof_steps => c_diag_seq_rx_reg_nof_steps
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_data_buf_mosi => reg_bsn_buf_mosi,
- reg_data_buf_miso => reg_bsn_buf_miso,
-
- ram_data_buf_mosi => ram_bsn_buf_mosi,
- ram_data_buf_miso => ram_bsn_buf_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- in_sync => st_pps,
- in_sosi_arr => in_sosi_arr_data_buf,
- out_wr_done_arr => out_wr_bsn_done_arr
- );
+ generic map (
+ g_technology => g_technology,
+
+ -- General
+ g_nof_streams => c_nof_streams,
+
+ -- DB settings
+ g_data_type => c_bsn_type,
+ g_data_w => c_dp_stream_bsn_w,
+ g_buf_nof_data => c_buf_nof_words,
+ g_buf_use_sync => false,
+ g_use_steps => false,
+ g_nof_steps => c_diag_seq_rx_reg_nof_steps
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_data_buf_mosi => reg_bsn_buf_mosi,
+ reg_data_buf_miso => reg_bsn_buf_miso,
+
+ ram_data_buf_mosi => ram_bsn_buf_mosi,
+ ram_data_buf_miso => ram_bsn_buf_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ in_sync => st_pps,
+ in_sosi_arr => in_sosi_arr_data_buf,
+ out_wr_done_arr => out_wr_bsn_done_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
--- ETH_clk => ETH_CLK(0),
--- ETH_SGIN => ETH_SGIN(0),
--- ETH_SGOUT => ETH_SGOUT(0)
-
- ETH_clk => ETH_CLK(1),
- ETH_SGIN => ETH_SGIN(1),
- ETH_SGOUT => ETH_SGOUT(1)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ -- ETH_clk => ETH_CLK(0),
+ -- ETH_SGIN => ETH_SGIN(0),
+ -- ETH_SGOUT => ETH_SGOUT(0)
+
+ ETH_clk => ETH_CLK(1),
+ ETH_SGIN => ETH_SGIN(1),
+ ETH_SGOUT => ETH_SGOUT(1)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_ddrctrl
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- bsn_source_v2
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
-
- -- bsn_scheduler
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_miso,
-
- -- wg_wideband_arr
- reg_wg_wideband_arr_mosi => reg_wg_wideband_arr_mosi,
- reg_wg_wideband_arr_miso => reg_wg_wideband_arr_miso,
- ram_wg_wideband_arr_mosi => ram_wg_wideband_arr_mosi,
- ram_wg_wideband_arr_miso => ram_wg_wideband_arr_miso,
-
- -- stop_in
- reg_stop_in_mosi => reg_stop_in_mosi,
- reg_stop_in_miso => reg_stop_in_miso,
-
- -- ddrctrl_ctrl_state
- reg_ddrctrl_ctrl_state_mosi => reg_ddrctrl_ctrl_state_mosi,
- reg_ddrctrl_ctrl_state_miso => reg_ddrctrl_ctrl_state_miso,
-
- -- io_ddr
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- data_buffer
- reg_data_buf_mosi => reg_data_buf_mosi,
- reg_data_buf_miso => reg_data_buf_miso,
- ram_data_buf_mosi => ram_data_buf_mosi,
- ram_data_buf_miso => ram_data_buf_miso,
- reg_rx_seq_data_mosi => reg_rx_seq_data_mosi,
- reg_rx_seq_data_miso => reg_rx_seq_data_miso,
-
- -- bsn_buffer
- reg_bsn_buf_mosi => reg_bsn_buf_mosi,
- reg_bsn_buf_miso => reg_bsn_buf_miso,
- ram_bsn_buf_mosi => ram_bsn_buf_mosi,
- ram_bsn_buf_miso => ram_bsn_buf_miso,
- reg_rx_seq_bsn_mosi => reg_rx_seq_bsn_mosi,
- reg_rx_seq_bsn_miso => reg_rx_seq_bsn_miso
-
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- bsn_source_v2
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
+
+ -- bsn_scheduler
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_miso,
+
+ -- wg_wideband_arr
+ reg_wg_wideband_arr_mosi => reg_wg_wideband_arr_mosi,
+ reg_wg_wideband_arr_miso => reg_wg_wideband_arr_miso,
+ ram_wg_wideband_arr_mosi => ram_wg_wideband_arr_mosi,
+ ram_wg_wideband_arr_miso => ram_wg_wideband_arr_miso,
+
+ -- stop_in
+ reg_stop_in_mosi => reg_stop_in_mosi,
+ reg_stop_in_miso => reg_stop_in_miso,
+
+ -- ddrctrl_ctrl_state
+ reg_ddrctrl_ctrl_state_mosi => reg_ddrctrl_ctrl_state_mosi,
+ reg_ddrctrl_ctrl_state_miso => reg_ddrctrl_ctrl_state_miso,
+
+ -- io_ddr
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- data_buffer
+ reg_data_buf_mosi => reg_data_buf_mosi,
+ reg_data_buf_miso => reg_data_buf_miso,
+ ram_data_buf_mosi => ram_data_buf_mosi,
+ ram_data_buf_miso => ram_data_buf_miso,
+ reg_rx_seq_data_mosi => reg_rx_seq_data_mosi,
+ reg_rx_seq_data_miso => reg_rx_seq_data_miso,
+
+ -- bsn_buffer
+ reg_bsn_buf_mosi => reg_bsn_buf_mosi,
+ reg_bsn_buf_miso => reg_bsn_buf_miso,
+ ram_bsn_buf_mosi => ram_bsn_buf_mosi,
+ ram_bsn_buf_miso => ram_bsn_buf_miso,
+ reg_rx_seq_bsn_mosi => reg_rx_seq_bsn_mosi,
+ reg_rx_seq_bsn_miso => reg_rx_seq_bsn_miso
+
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
index 7d53952914..967e08ad26 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_ddrctrl_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_ddrctrl_pkg.all;
entity mmm_lofar2_unb2c_ddrctrl is
@@ -141,7 +141,7 @@ entity mmm_lofar2_unb2c_ddrctrl is
reg_rx_seq_bsn_miso : in t_mem_miso
-);
+ );
end mmm_lofar2_unb2c_ddrctrl;
architecture str of mmm_lofar2_unb2c_ddrctrl is
@@ -159,68 +159,68 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
u_mm_file_reg_wg_wideband_arr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG_WIDEBAND_ARR")
- port map(mm_rst, mm_clk, reg_wg_wideband_arr_mosi, reg_wg_wideband_arr_miso);
+ port map(mm_rst, mm_clk, reg_wg_wideband_arr_mosi, reg_wg_wideband_arr_miso);
u_mm_file_ram_wg_wideband_arr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG_WIDEBAND_ARR")
- port map(mm_rst, mm_clk, ram_wg_wideband_arr_mosi, ram_wg_wideband_arr_miso);
+ port map(mm_rst, mm_clk, ram_wg_wideband_arr_mosi, ram_wg_wideband_arr_miso);
u_mm_file_reg_stop_in : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STOP_IN")
- port map(mm_rst, mm_clk, reg_stop_in_mosi, reg_stop_in_miso);
+ port map(mm_rst, mm_clk, reg_stop_in_mosi, reg_stop_in_miso);
u_mm_file_reg_ddrctrl_state : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDRCTRL_CTRL_STATE")
- port map(mm_rst, mm_clk, reg_ddrctrl_ctrl_state_mosi, reg_ddrctrl_ctrl_state_miso);
+ port map(mm_rst, mm_clk, reg_ddrctrl_ctrl_state_mosi, reg_ddrctrl_ctrl_state_miso);
u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
u_mm_file_reg_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DATA_BUF")
- port map(mm_rst, mm_clk, reg_data_buf_mosi, reg_data_buf_miso);
+ port map(mm_rst, mm_clk, reg_data_buf_mosi, reg_data_buf_miso);
u_mm_file_ram_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DATA_BUF")
- port map(mm_rst, mm_clk, ram_data_buf_mosi, ram_data_buf_miso);
+ port map(mm_rst, mm_clk, ram_data_buf_mosi, ram_data_buf_miso);
u_mm_file_reg_rx_seq_data : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_DATA")
- port map(mm_rst, mm_clk, reg_rx_seq_data_mosi, reg_rx_seq_data_miso);
+ port map(mm_rst, mm_clk, reg_rx_seq_data_mosi, reg_rx_seq_data_miso);
u_mm_file_reg_bsn_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_BUF")
- port map(mm_rst, mm_clk, reg_bsn_buf_mosi, reg_bsn_buf_miso);
+ port map(mm_rst, mm_clk, reg_bsn_buf_mosi, reg_bsn_buf_miso);
u_mm_file_ram_bsn_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BSN_BUF")
- port map(mm_rst, mm_clk, ram_bsn_buf_mosi, ram_bsn_buf_miso);
+ port map(mm_rst, mm_clk, ram_bsn_buf_mosi, ram_bsn_buf_miso);
u_mm_file_reg_rx_seq_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_BSN")
- port map(mm_rst, mm_clk, reg_rx_seq_bsn_mosi, reg_rx_seq_bsn_miso);
+ port map(mm_rst, mm_clk, reg_rx_seq_bsn_mosi, reg_rx_seq_bsn_miso);
@@ -240,209 +240,209 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2c_ddrctrl
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_scrap_reset_export => OPEN,
- ram_scrap_clk_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_source_v2_reset_export => OPEN,
- reg_bsn_source_v2_clk_export => OPEN,
- reg_bsn_source_v2_address_export => reg_bsn_source_v2_mosi.address(2 downto 0),
- reg_bsn_source_v2_read_export => reg_bsn_source_v2_mosi.rd,
- reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_source_v2_write_export => reg_bsn_source_v2_mosi.wr,
- reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_clk_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(0 downto 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_wg_wideband_arr_reset_export => OPEN,
- reg_wg_wideband_arr_clk_export => OPEN,
- reg_wg_wideband_arr_address_export => reg_wg_wideband_arr_mosi.address(5 downto 0),
- reg_wg_wideband_arr_read_export => reg_wg_wideband_arr_mosi.rd,
- reg_wg_wideband_arr_readdata_export => reg_wg_wideband_arr_miso.rddata(c_word_w - 1 downto 0),
- reg_wg_wideband_arr_write_export => reg_wg_wideband_arr_mosi.wr,
- reg_wg_wideband_arr_writedata_export => reg_wg_wideband_arr_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_wg_wideband_arr_reset_export => OPEN,
- ram_wg_wideband_arr_clk_export => OPEN,
- ram_wg_wideband_arr_address_export => ram_wg_wideband_arr_mosi.address(13 downto 0),
- ram_wg_wideband_arr_read_export => ram_wg_wideband_arr_mosi.rd,
- ram_wg_wideband_arr_readdata_export => ram_wg_wideband_arr_miso.rddata(c_word_w - 1 downto 0),
- ram_wg_wideband_arr_write_export => ram_wg_wideband_arr_mosi.wr,
- ram_wg_wideband_arr_writedata_export => ram_wg_wideband_arr_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_stop_in_reset_export => OPEN,
- reg_stop_in_clk_export => OPEN,
- reg_stop_in_address_export => reg_stop_in_mosi.address(0 downto 0),
- reg_stop_in_read_export => reg_stop_in_mosi.rd,
- reg_stop_in_readdata_export => reg_stop_in_miso.rddata(c_word_w - 1 downto 0),
- reg_stop_in_write_export => reg_stop_in_mosi.wr,
- reg_stop_in_writedata_export => reg_stop_in_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_data_buf_reset_export => OPEN,
- ram_data_buf_clk_export => OPEN,
- ram_data_buf_address_export => ram_data_buf_mosi.address(13 downto 0),
- ram_data_buf_read_export => ram_data_buf_mosi.rd,
- ram_data_buf_readdata_export => ram_data_buf_miso.rddata(c_word_w - 1 downto 0),
- ram_data_buf_write_export => ram_data_buf_mosi.wr,
- ram_data_buf_writedata_export => ram_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_bsn_buf_reset_export => OPEN,
- ram_bsn_buf_clk_export => OPEN,
- ram_bsn_buf_address_export => ram_bsn_buf_mosi.address(14 downto 0),
- ram_bsn_buf_read_export => ram_bsn_buf_mosi.rd,
- ram_bsn_buf_readdata_export => ram_bsn_buf_miso.rddata(c_word_w - 1 downto 0),
- ram_bsn_buf_write_export => ram_bsn_buf_mosi.wr,
- ram_bsn_buf_writedata_export => ram_bsn_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_io_ddr_reset_export => OPEN,
- reg_io_ddr_clk_export => OPEN,
- reg_io_ddr_address_export => reg_io_ddr_mosi.address(1 downto 0),
- reg_io_ddr_read_export => reg_io_ddr_mosi.rd,
- reg_io_ddr_readdata_export => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_write_export => reg_io_ddr_mosi.wr,
- reg_io_ddr_writedata_export => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_ddrctrl_ctrl_state_reset_export => OPEN,
- reg_ddrctrl_ctrl_state_clk_export => OPEN,
- reg_ddrctrl_ctrl_state_address_export => reg_ddrctrl_ctrl_state_mosi.address(0 downto 0),
- reg_ddrctrl_ctrl_state_read_export => reg_ddrctrl_ctrl_state_mosi.rd,
- reg_ddrctrl_ctrl_state_readdata_export => reg_ddrctrl_ctrl_state_miso.rddata(c_word_w - 1 downto 0),
- reg_ddrctrl_ctrl_state_write_export => reg_ddrctrl_ctrl_state_mosi.wr,
- reg_ddrctrl_ctrl_state_writedata_export => reg_ddrctrl_ctrl_state_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_source_v2_reset_export => OPEN,
+ reg_bsn_source_v2_clk_export => OPEN,
+ reg_bsn_source_v2_address_export => reg_bsn_source_v2_mosi.address(2 downto 0),
+ reg_bsn_source_v2_read_export => reg_bsn_source_v2_mosi.rd,
+ reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_source_v2_write_export => reg_bsn_source_v2_mosi.wr,
+ reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_scheduler_reset_export => OPEN,
+ reg_bsn_scheduler_clk_export => OPEN,
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(0 downto 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_wg_wideband_arr_reset_export => OPEN,
+ reg_wg_wideband_arr_clk_export => OPEN,
+ reg_wg_wideband_arr_address_export => reg_wg_wideband_arr_mosi.address(5 downto 0),
+ reg_wg_wideband_arr_read_export => reg_wg_wideband_arr_mosi.rd,
+ reg_wg_wideband_arr_readdata_export => reg_wg_wideband_arr_miso.rddata(c_word_w - 1 downto 0),
+ reg_wg_wideband_arr_write_export => reg_wg_wideband_arr_mosi.wr,
+ reg_wg_wideband_arr_writedata_export => reg_wg_wideband_arr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_wg_wideband_arr_reset_export => OPEN,
+ ram_wg_wideband_arr_clk_export => OPEN,
+ ram_wg_wideband_arr_address_export => ram_wg_wideband_arr_mosi.address(13 downto 0),
+ ram_wg_wideband_arr_read_export => ram_wg_wideband_arr_mosi.rd,
+ ram_wg_wideband_arr_readdata_export => ram_wg_wideband_arr_miso.rddata(c_word_w - 1 downto 0),
+ ram_wg_wideband_arr_write_export => ram_wg_wideband_arr_mosi.wr,
+ ram_wg_wideband_arr_writedata_export => ram_wg_wideband_arr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_stop_in_reset_export => OPEN,
+ reg_stop_in_clk_export => OPEN,
+ reg_stop_in_address_export => reg_stop_in_mosi.address(0 downto 0),
+ reg_stop_in_read_export => reg_stop_in_mosi.rd,
+ reg_stop_in_readdata_export => reg_stop_in_miso.rddata(c_word_w - 1 downto 0),
+ reg_stop_in_write_export => reg_stop_in_mosi.wr,
+ reg_stop_in_writedata_export => reg_stop_in_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_data_buf_reset_export => OPEN,
+ ram_data_buf_clk_export => OPEN,
+ ram_data_buf_address_export => ram_data_buf_mosi.address(13 downto 0),
+ ram_data_buf_read_export => ram_data_buf_mosi.rd,
+ ram_data_buf_readdata_export => ram_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ ram_data_buf_write_export => ram_data_buf_mosi.wr,
+ ram_data_buf_writedata_export => ram_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_bsn_buf_reset_export => OPEN,
+ ram_bsn_buf_clk_export => OPEN,
+ ram_bsn_buf_address_export => ram_bsn_buf_mosi.address(14 downto 0),
+ ram_bsn_buf_read_export => ram_bsn_buf_mosi.rd,
+ ram_bsn_buf_readdata_export => ram_bsn_buf_miso.rddata(c_word_w - 1 downto 0),
+ ram_bsn_buf_write_export => ram_bsn_buf_mosi.wr,
+ ram_bsn_buf_writedata_export => ram_bsn_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_reset_export => OPEN,
+ reg_io_ddr_clk_export => OPEN,
+ reg_io_ddr_address_export => reg_io_ddr_mosi.address(1 downto 0),
+ reg_io_ddr_read_export => reg_io_ddr_mosi.rd,
+ reg_io_ddr_readdata_export => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_write_export => reg_io_ddr_mosi.wr,
+ reg_io_ddr_writedata_export => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_ddrctrl_ctrl_state_reset_export => OPEN,
+ reg_ddrctrl_ctrl_state_clk_export => OPEN,
+ reg_ddrctrl_ctrl_state_address_export => reg_ddrctrl_ctrl_state_mosi.address(0 downto 0),
+ reg_ddrctrl_ctrl_state_read_export => reg_ddrctrl_ctrl_state_mosi.rd,
+ reg_ddrctrl_ctrl_state_readdata_export => reg_ddrctrl_ctrl_state_miso.rddata(c_word_w - 1 downto 0),
+ reg_ddrctrl_ctrl_state_write_export => reg_ddrctrl_ctrl_state_mosi.wr,
+ reg_ddrctrl_ctrl_state_writedata_export => reg_ddrctrl_ctrl_state_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
index 0b4b8cd68b..45f2709cc4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
@@ -20,193 +20,193 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_ddrctrl_pkg is
- ----------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus QSYS builder
- ----------------------------------------------------------------------
+ ----------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus QSYS builder
+ ----------------------------------------------------------------------
- component qsys_lofar2_unb2c_ddrctrl is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bsn_buf_reset_export : out std_logic; -- export
- ram_bsn_buf_clk_export : out std_logic; -- export
- ram_bsn_buf_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bsn_buf_write_export : out std_logic; -- export
- ram_bsn_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bsn_buf_read_export : out std_logic; -- export
- ram_bsn_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_data_buf_reset_export : out std_logic; -- export
- ram_data_buf_clk_export : out std_logic; -- export
- ram_data_buf_address_export : out std_logic_vector(13 downto 0); -- export
- ram_data_buf_write_export : out std_logic; -- export
- ram_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_data_buf_read_export : out std_logic; -- export
- ram_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_wideband_arr_reset_export : out std_logic; -- export
- ram_wg_wideband_arr_clk_export : out std_logic; -- export
- ram_wg_wideband_arr_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_wideband_arr_write_export : out std_logic; -- export
- ram_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_wideband_arr_read_export : out std_logic; -- export
- ram_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stop_in_reset_export : out std_logic; -- export
- reg_stop_in_clk_export : out std_logic; -- export
- reg_stop_in_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stop_in_write_export : out std_logic; -- export
- reg_stop_in_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stop_in_read_export : out std_logic; -- export
- reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_reset_export : out std_logic; -- export
- reg_io_ddr_clk_export : out std_logic; -- export
- reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_io_ddr_write_export : out std_logic; -- export
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_read_export : out std_logic; -- export
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_wideband_arr_reset_export : out std_logic; -- export
- reg_wg_wideband_arr_clk_export : out std_logic; -- export
- reg_wg_wideband_arr_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_wideband_arr_write_export : out std_logic; -- export
- reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_wideband_arr_read_export : out std_logic; -- export
- reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ddrctrl_ctrl_state_reset_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_clk_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ddrctrl_ctrl_state_write_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_ddrctrl_ctrl_state_read_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2c_ddrctrl;
+ component qsys_lofar2_unb2c_ddrctrl is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bsn_buf_reset_export : out std_logic; -- export
+ ram_bsn_buf_clk_export : out std_logic; -- export
+ ram_bsn_buf_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bsn_buf_write_export : out std_logic; -- export
+ ram_bsn_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bsn_buf_read_export : out std_logic; -- export
+ ram_bsn_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_data_buf_reset_export : out std_logic; -- export
+ ram_data_buf_clk_export : out std_logic; -- export
+ ram_data_buf_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_data_buf_write_export : out std_logic; -- export
+ ram_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_data_buf_read_export : out std_logic; -- export
+ ram_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_wideband_arr_reset_export : out std_logic; -- export
+ ram_wg_wideband_arr_clk_export : out std_logic; -- export
+ ram_wg_wideband_arr_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_wideband_arr_write_export : out std_logic; -- export
+ ram_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_wideband_arr_read_export : out std_logic; -- export
+ ram_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stop_in_reset_export : out std_logic; -- export
+ reg_stop_in_clk_export : out std_logic; -- export
+ reg_stop_in_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stop_in_write_export : out std_logic; -- export
+ reg_stop_in_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stop_in_read_export : out std_logic; -- export
+ reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_reset_export : out std_logic; -- export
+ reg_io_ddr_clk_export : out std_logic; -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_io_ddr_write_export : out std_logic; -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_read_export : out std_logic; -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_wideband_arr_reset_export : out std_logic; -- export
+ reg_wg_wideband_arr_clk_export : out std_logic; -- export
+ reg_wg_wideband_arr_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_wideband_arr_write_export : out std_logic; -- export
+ reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_wideband_arr_read_export : out std_logic; -- export
+ reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ddrctrl_ctrl_state_reset_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_clk_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ddrctrl_ctrl_state_write_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_ddrctrl_ctrl_state_read_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2c_ddrctrl;
end qsys_lofar2_unb2c_ddrctrl_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index 10f176c35f..84d9dfa580 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -42,28 +42,28 @@
--
library IEEE, common_lib, unb2c_board_lib, i2c_lib, technology_lib, mm_lib, dp_lib, tech_ddr_lib, lofar2_sdp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use diag_lib.diag_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
entity tb_lofar2_unb2c_ddrctrl is
- generic (
- g_design_name : string := "lofar2_unb2c_ddrctrl";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "lofar2_unb2c_ddrctrl";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_lofar2_unb2c_ddrctrl;
architecture tb of tb_lofar2_unb2c_ddrctrl is
@@ -186,7 +186,7 @@ begin
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- u_lofar2_unb2c_ddrctrl : entity work.lofar2_unb2c_ddrctrl
+ u_lofar2_unb2c_ddrctrl : entity work.lofar2_unb2c_ddrctrl
generic map (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
@@ -218,7 +218,7 @@ begin
);
- -- WG
+ -- WG
------------------------------------------------------------------------------
@@ -230,7 +230,7 @@ begin
p_mm_stimuli : process
- variable v_bsn : natural := 0;
+ variable v_bsn : natural := 0;
begin
@@ -274,7 +274,7 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -296,7 +296,7 @@ begin
wait for c_st_clk_period * c_block_size;
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -317,7 +317,7 @@ begin
wait for c_st_clk_period * c_block_size;
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -339,7 +339,7 @@ begin
wait for c_st_clk_period * c_block_size;
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 240000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -360,7 +360,7 @@ begin
wait for c_st_clk_period * (c_block_size-500);
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -381,7 +381,7 @@ begin
wait for c_st_clk_period * (c_block_size);
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -402,7 +402,7 @@ begin
wait for c_st_clk_period * (c_block_size);
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
tb_end <= '1';
assert false report "Test: OK" severity FAILURE;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
index 66148b3a52..824a2a1e04 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_filterbank_full is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2c_filterbank_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2c)
+ -- back transceivers (note only 6 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b - 1 downto c_unb2c_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -112,51 +112,51 @@ begin
u_revision : entity lofar2_unb2c_filterbank_lib.lofar2_unb2c_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
index 0fb7c26807..7971ea657d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_filterbank_full_256MHz is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2c_filterbank_full_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2c)
+ -- back transceivers (note only 6 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b - 1 downto c_unb2c_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -112,51 +112,51 @@ begin
u_revision : entity lofar2_unb2c_filterbank_lib.lofar2_unb2c_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
index 395f52da85..f8e3db5e54 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
@@ -27,17 +27,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_filterbank_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_filterbank_pkg.all;
entity lofar2_unb2c_filterbank is
generic (
@@ -85,9 +85,9 @@ entity lofar2_unb2c_filterbank is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -263,221 +263,221 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_filterbank
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
-----------------------------------------------------------------------------
@@ -486,84 +486,84 @@ begin
-----------------------------------------------------------------------------
u_ait: entity lofar2_sdp_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_ait_buf_nof_data_bsn,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_ait_buf_nof_data_bsn,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
index 8bc26b1b3c..a7e33719cc 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
@@ -20,14 +20,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_filterbank_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -43,7 +43,7 @@ package lofar2_unb2c_filterbank_pkg is
constant c_full_256MHz : t_lofar2_unb2c_filterbank_config := ( 12, 2, 12, c_unb2c_board_ext_clk_freq_256M );
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_filterbank_config;
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2c_filterbank_config;
end lofar2_unb2c_filterbank_pkg;
@@ -51,7 +51,7 @@ end lofar2_unb2c_filterbank_pkg;
package body lofar2_unb2c_filterbank_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_filterbank_config is
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2c_filterbank_config is
begin
if g_design_name = "lofar2_unb2c_filterbank_full" then return c_full;
elsif g_design_name = "lofar2_unb2c_filterbank_full_256MHz" then return c_full_256MHz;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
index d9e1229f7b..b0b1038679 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_filterbank_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_filterbank_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2c_filterbank is
generic (
@@ -154,13 +154,13 @@ entity mmm_lofar2_unb2c_filterbank is
reg_si_mosi : out t_mem_mosi;
reg_si_miso : in t_mem_miso;
- -- Equalizer gains
- ram_equalizer_gains_mosi : out t_mem_mosi;
- ram_equalizer_gains_miso : in t_mem_miso;
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : out t_mem_mosi;
+ ram_equalizer_gains_miso : in t_mem_miso;
- -- DP Selector
- reg_dp_selector_mosi : out t_mem_mosi;
- reg_dp_selector_miso : in t_mem_miso;
+ -- DP Selector
+ reg_dp_selector_mosi : out t_mem_mosi;
+ reg_dp_selector_miso : in t_mem_miso;
-- Scrap ram
ram_scrap_mosi : out t_mem_mosi;
@@ -184,85 +184,85 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -277,295 +277,295 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2c_filterbank
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- jesd204b_reset_export => OPEN,
- jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
- reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- waveform generators (multiplexed)
- reg_wg_clk_export => OPEN,
- reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
- reg_wg_read_export => reg_wg_mosi.rd,
- reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w - 1 downto 0),
- reg_wg_write_export => reg_wg_mosi.wr,
- reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_wg_clk_export => OPEN,
- ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
- ram_wg_read_export => ram_wg_mosi.rd,
- ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w - 1 downto 0),
- ram_wg_write_export => ram_wg_mosi.wr,
- ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_dp_shiftram_clk_export => OPEN,
- reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_source_clk_export => OPEN,
- reg_bsn_source_reset_export => OPEN,
- reg_bsn_source_address_export => reg_bsn_source_mosi.address(c_sdp_reg_bsn_source_addr_w - 1 downto 0),
- reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
- reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
- reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_scheduler_clk_export => OPEN,
- reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- ram_diag_data_buf_bsn_clk_export => OPEN,
- ram_diag_data_buf_bsn_reset_export => OPEN,
- ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w - 1 downto 0),
- ram_diag_data_buf_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buf_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buf_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buf_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buf_bsn_reset_export => OPEN,
- reg_diag_data_buf_bsn_clk_export => OPEN,
- reg_diag_data_buf_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
- reg_diag_data_buf_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buf_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buf_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buf_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buf_jesd_clk_export => OPEN,
- ram_diag_data_buf_jesd_reset_export => OPEN,
- ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(c_sdp_ram_diag_data_buf_jesd_addr_w - 1 downto 0),
- ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
- ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
- ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buf_jesd_reset_export => OPEN,
- reg_diag_data_buf_jesd_clk_export => OPEN,
- reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(c_sdp_reg_diag_data_buf_jesd_addr_w - 1 downto 0),
- reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
- reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
- reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
- reg_aduh_monitor_reset_export => OPEN,
- reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w - 1 downto 0),
-
- ram_fil_coefs_clk_export => OPEN,
- ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
- ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w - 1 downto 0),
- ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w - 1 downto 0),
-
- ram_st_sst_clk_export => OPEN,
- ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
- ram_st_sst_write_export => ram_st_sst_mosi.wr,
- ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w - 1 downto 0),
- ram_st_sst_read_export => ram_st_sst_mosi.rd,
- ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w - 1 downto 0),
-
- reg_si_clk_export => OPEN,
- reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w - 1 downto 0),
- reg_si_write_export => reg_si_mosi.wr,
- reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w - 1 downto 0),
- reg_si_read_export => reg_si_mosi.rd,
- reg_si_readdata_export => reg_si_miso.rddata(c_word_w - 1 downto 0),
-
- ram_equalizer_gains_clk_export => OPEN,
- ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w - 1 downto 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dp_selector_clk_export => OPEN,
- reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
- reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w - 1 downto 0),
-
- ram_scrap_clk_export => OPEN,
- ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(9 - 1 downto 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ jesd204b_reset_export => OPEN,
+ jesd204b_clk_export => OPEN,
+ jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
+ jesd204b_write_export => jesd204b_mosi.wr,
+ jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
+ jesd204b_read_export => jesd204b_mosi.rd,
+ jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
+ reg_bsn_monitor_input_clk_export => OPEN,
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_input_reset_export => OPEN,
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- waveform generators (multiplexed)
+ reg_wg_clk_export => OPEN,
+ reg_wg_reset_export => OPEN,
+ reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
+ reg_wg_read_export => reg_wg_mosi.rd,
+ reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w - 1 downto 0),
+ reg_wg_write_export => reg_wg_mosi.wr,
+ reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_wg_clk_export => OPEN,
+ ram_wg_reset_export => OPEN,
+ ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
+ ram_wg_read_export => ram_wg_mosi.rd,
+ ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w - 1 downto 0),
+ ram_wg_write_export => ram_wg_mosi.wr,
+ ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_dp_shiftram_clk_export => OPEN,
+ reg_dp_shiftram_reset_export => OPEN,
+ reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_source_clk_export => OPEN,
+ reg_bsn_source_reset_export => OPEN,
+ reg_bsn_source_address_export => reg_bsn_source_mosi.address(c_sdp_reg_bsn_source_addr_w - 1 downto 0),
+ reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
+ reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
+ reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_scheduler_clk_export => OPEN,
+ reg_bsn_scheduler_reset_export => OPEN,
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ ram_diag_data_buf_bsn_clk_export => OPEN,
+ ram_diag_data_buf_bsn_reset_export => OPEN,
+ ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w - 1 downto 0),
+ ram_diag_data_buf_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
+ ram_diag_data_buf_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
+ ram_diag_data_buf_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buf_bsn_reset_export => OPEN,
+ reg_diag_data_buf_bsn_clk_export => OPEN,
+ reg_diag_data_buf_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
+ reg_diag_data_buf_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
+ reg_diag_data_buf_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
+ reg_diag_data_buf_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buf_jesd_clk_export => OPEN,
+ ram_diag_data_buf_jesd_reset_export => OPEN,
+ ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(c_sdp_ram_diag_data_buf_jesd_addr_w - 1 downto 0),
+ ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
+ ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
+ ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buf_jesd_reset_export => OPEN,
+ reg_diag_data_buf_jesd_clk_export => OPEN,
+ reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(c_sdp_reg_diag_data_buf_jesd_addr_w - 1 downto 0),
+ reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
+ reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
+ reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_aduh_monitor_reset_export => OPEN,
+ reg_aduh_monitor_clk_export => OPEN,
+ reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_fil_coefs_clk_export => OPEN,
+ ram_fil_coefs_reset_export => OPEN,
+ ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_st_sst_clk_export => OPEN,
+ ram_st_sst_reset_export => OPEN,
+ ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
+ ram_st_sst_write_export => ram_st_sst_mosi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_st_sst_read_export => ram_st_sst_mosi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_si_clk_export => OPEN,
+ reg_si_reset_export => OPEN,
+ reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w - 1 downto 0),
+ reg_si_write_export => reg_si_mosi.wr,
+ reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_si_read_export => reg_si_mosi.rd,
+ reg_si_readdata_export => reg_si_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_equalizer_gains_clk_export => OPEN,
+ ram_equalizer_gains_reset_export => OPEN,
+ ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_selector_clk_export => OPEN,
+ reg_dp_selector_reset_export => OPEN,
+ reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
+ reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(9 - 1 downto 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
index 72f0f9eb43..b8273f6423 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
@@ -19,269 +19,269 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_filterbank_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_filterbank is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2c_filterbank;
+ component qsys_lofar2_unb2c_filterbank is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2c_filterbank;
end qsys_lofar2_unb2c_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
index 20f124a66e..50b8b162c8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
@@ -51,19 +51,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_filterbank is
end tb_lofar2_unb2c_filterbank;
@@ -203,52 +203,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_filterbank : entity work.lofar2_unb2c_filterbank
- generic map (
- g_design_name => "lofar2_unb2c_filterbank_full",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_filterbank_full",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -379,8 +379,8 @@ begin
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_subband_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
+ real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
-- sum
sp_subband_power_sum(v_S) <= sp_subband_power_sum(v_S) + v_sp_subband_power;
end if;
@@ -390,7 +390,7 @@ begin
-- because the input is a sinus, so most power will be in 1 subband. The sp_subband_power_leakage_sum shows
-- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
sp_subband_power_0 <= real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
+ real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
sp_subband_power_sum_0 <= sp_subband_power_sum(0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
index 9b01c6973e..e735955ac7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_ring_full is
generic (
@@ -87,49 +87,49 @@ architecture str of lofar2_unb2c_ring_full is
begin
u_revision : entity lofar2_unb2c_ring_lib.lofar2_unb2c_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
index 9cbf1b0569..2163590e6e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2c_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_ring_full is
end tb_lofar2_unb2c_ring_full;
@@ -99,45 +99,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_ring_full : entity work.lofar2_unb2c_ring_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
index add9341693..ffdc344337 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
@@ -30,13 +30,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_ring_one is
generic (
@@ -90,49 +90,49 @@ architecture str of lofar2_unb2c_ring_one is
begin
u_revision : entity lofar2_unb2c_ring_lib.lofar2_unb2c_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
index 375d1289ac..ef91d61209 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2c_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_ring_one is
end tb_lofar2_unb2c_ring_one;
@@ -99,45 +99,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_ring_one : entity work.lofar2_unb2c_ring_one
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
index 781bd97de9..957e161380 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
@@ -27,21 +27,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_ring_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_ring_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity lofar2_unb2c_ring is
@@ -105,7 +105,7 @@ architecture str of lofar2_unb2c_ring is
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_100M;
constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync; -- fixed 200 MHz for LOFAR2.0 stage 1
- -- QSFP
+ -- QSFP
constant c_nof_qsfp_bus : natural := 1;
constant c_nof_streams_qsfp : natural := c_unb2c_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
@@ -145,11 +145,13 @@ architecture str of lofar2_unb2c_ring is
constant c_addr_w_reg_dp_block_validate_bsn_at_sync : natural := ceil_log2(3);
- constant c_reg_ring_input_select : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_lanes),
- dat_w => 1,
- nof_dat => c_nof_lanes,
- init_sl => '0'); -- default use lane input = 0, 1 = local input.
+ constant c_reg_ring_input_select : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_lanes),
+ dat_w => 1,
+ nof_dat => c_nof_lanes,
+ init_sl => '0'
+ ); -- default use lane input = 0, 1 = local input.
signal gn_index : natural;
signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
@@ -336,274 +338,274 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM controller
-----------------------------------------------------------------------------
u_mmc : entity work.mmc_lofar2_unb2c_ring
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
- reg_diag_bg_copi => reg_diag_bg_copi,
- reg_diag_bg_cipo => reg_diag_bg_cipo,
- ram_diag_bg_copi => ram_diag_bg_copi,
- ram_diag_bg_cipo => ram_diag_bg_cipo,
- reg_ring_lane_info_copi => reg_ring_lane_info_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
- reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
- reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
- reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
- reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
+ reg_diag_bg_copi => reg_diag_bg_copi,
+ reg_diag_bg_cipo => reg_diag_bg_cipo,
+ ram_diag_bg_copi => ram_diag_bg_copi,
+ ram_diag_bg_cipo => ram_diag_bg_cipo,
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
+ reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
+ reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
+ reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
+ reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo
+ );
-----------------------------------------------------------------------------
-- MM Mux
-----------------------------------------------------------------------------
u_mem_mux_ring_lane_info : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info
- )
- port map (
- mosi => reg_ring_lane_info_copi,
- miso => reg_ring_lane_info_cipo,
- mosi_arr => reg_ring_lane_info_copi_arr,
- miso_arr => reg_ring_lane_info_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info
+ )
+ port map (
+ mosi => reg_ring_lane_info_copi,
+ miso => reg_ring_lane_info_cipo,
+ mosi_arr => reg_ring_lane_info_copi_arr,
+ miso_arr => reg_ring_lane_info_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_rx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_copi,
- miso => reg_bsn_monitor_v2_ring_rx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_tx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_copi,
- miso => reg_bsn_monitor_v2_ring_tx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
+ );
u_mem_mux_dp_block_validate_err : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
- )
- port map (
- mosi => reg_dp_block_validate_err_copi,
- miso => reg_dp_block_validate_err_cipo,
- mosi_arr => reg_dp_block_validate_err_copi_arr,
- miso_arr => reg_dp_block_validate_err_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_copi,
+ miso => reg_dp_block_validate_err_cipo,
+ mosi_arr => reg_dp_block_validate_err_copi_arr,
+ miso_arr => reg_dp_block_validate_err_cipo_arr
+ );
u_mem_mux_dp_block_validate_bsn_at_sync : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_copi,
- miso => reg_dp_block_validate_bsn_at_sync_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
+ );
-----------------------------------------------------------------------------
-- MMP diag_block_gen
-----------------------------------------------------------------------------
u_mmp_diag_block_gen : entity diag_lib.mms_diag_block_gen
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
-
- reg_bg_ctrl_mosi => reg_diag_bg_copi,
- reg_bg_ctrl_miso => reg_diag_bg_cipo,
- ram_bg_data_mosi => ram_diag_bg_copi,
- ram_bg_data_miso => ram_diag_bg_cipo,
-
- out_sosi_arr(0) => local_sosi
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_copi,
+ reg_bg_ctrl_miso => reg_diag_bg_cipo,
+ ram_bg_data_mosi => ram_diag_bg_copi,
+ ram_bg_data_miso => ram_diag_bg_cipo,
+
+ out_sosi_arr(0) => local_sosi
+ );
bs_sosi <= local_sosi;
@@ -611,26 +613,26 @@ begin
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
u_mmp_dp_xonoff_lane : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_lane_copi,
- reg_miso => reg_dp_xonoff_lane_cipo,
+ reg_mosi => reg_dp_xonoff_lane_copi,
+ reg_miso => reg_dp_xonoff_lane_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => from_lane_sosi_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => from_lane_sosi_arr,
- src_in_arr => dp_xonoff_lane_src_in_arr,
- src_out_arr => dp_xonoff_lane_src_out_arr
- );
+ src_in_arr => dp_xonoff_lane_src_in_arr,
+ src_out_arr => dp_xonoff_lane_src_out_arr
+ );
-----------------------------------------------------------------------------
-- MMP dp_xonoff local_sosi
@@ -640,26 +642,26 @@ begin
end generate;
u_mmp_dp_xonoff_local : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_local_copi,
- reg_miso => reg_dp_xonoff_local_cipo,
+ reg_mosi => reg_dp_xonoff_local_copi,
+ reg_miso => reg_dp_xonoff_local_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => dp_xonoff_local_snk_in_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => dp_xonoff_local_snk_in_arr,
- src_in_arr => dp_xonoff_local_src_in_arr,
- src_out_arr => dp_xonoff_local_src_out_arr
- );
+ src_in_arr => dp_xonoff_local_src_in_arr,
+ src_out_arr => dp_xonoff_local_src_out_arr
+ );
-----------------------------------------------------------------------------
-- DP Mux
@@ -672,49 +674,49 @@ begin
dp_mux_snk_in_2arr(I)(1) <= dp_xonoff_local_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true,
- g_use_fifo => true,
- g_bsn_w => c_longword_w,
- g_data_w => c_lane_data_w,
- g_in_channel_w => c_byte_w,
- g_error_w => c_nof_err_counts,
- g_use_bsn => true,
- g_use_in_channel => true,
- g_use_error => true,
- g_use_sync => true,
- -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
- g_fifo_size => array_init(2 * c_lane_packet_length, 2)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_mux_snk_out_2arr(I),
- snk_in_arr => dp_mux_snk_in_2arr(I),
-
- src_in => c_dp_siso_rdy,
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true,
+ g_use_fifo => true,
+ g_bsn_w => c_longword_w,
+ g_data_w => c_lane_data_w,
+ g_in_channel_w => c_byte_w,
+ g_error_w => c_nof_err_counts,
+ g_use_bsn => true,
+ g_use_in_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
+ g_fifo_size => array_init(2 * c_lane_packet_length, 2)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_mux_snk_out_2arr(I),
+ snk_in_arr => dp_mux_snk_in_2arr(I),
+
+ src_in => c_dp_siso_rdy,
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
-- Use full c_byte_w range of ID for gn_index and ring_info.O_rn
gn_index <= TO_UINT(ID);
@@ -725,50 +727,50 @@ begin
-----------------------------------------------------------------------------
gen_even_lanes: for I in 0 to c_nof_even_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
- to_lane_sosi => to_lane_sosi_arr(2 * I),
- lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I),
+ lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -776,50 +778,50 @@ begin
-----------------------------------------------------------------------------
gen_odd_lanes : for I in 0 to c_nof_odd_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 0, -- transport in negative direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
- to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
- lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
- tx_select => ring_info.use_cable_to_previous_rn
- );
+ generic map (
+ g_lane_direction => 0, -- transport in negative direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
+ lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ tx_select => ring_info.use_cable_to_previous_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -848,45 +850,45 @@ begin
-- tr_10GbE
-----------------------------------------------------------------------------
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_mac,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill,
- g_tx_fifo_size => c_fifo_tx_size
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
-
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => tr_10gbe_src_out_arr,
- src_in_arr => tr_10gbe_src_in_arr,
-
- snk_out_arr => tr_10gbe_snk_out_arr,
- snk_in_arr => tr_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => tr_10gbe_serial_tx_arr,
- serial_rx_arr => tr_10gbe_serial_rx_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_mac,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill,
+ g_tx_fifo_size => c_fifo_tx_size
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
+
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => tr_10gbe_src_out_arr,
+ src_in_arr => tr_10gbe_src_in_arr,
+
+ snk_out_arr => tr_10gbe_snk_out_arr,
+ snk_in_arr => tr_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_serial_rx_arr
+ );
-----------------------------------------------------------------------------
@@ -915,14 +917,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- Front IO
@@ -932,21 +934,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- RING IO
@@ -961,19 +963,19 @@ begin
------------
unb2_board_qsfp_leds_tx_siso_arr(0) <= tr_10gbe_snk_out_arr(0);
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
index bb9c567d90..9f92000fe4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
@@ -20,14 +20,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_ring_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -40,7 +40,7 @@ package lofar2_unb2c_ring_pkg is
constant c_full : t_lofar2_unb2c_ring_config := (8, 8);
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_ring_config;
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2c_ring_config;
end lofar2_unb2c_ring_pkg;
@@ -48,7 +48,7 @@ end lofar2_unb2c_ring_pkg;
package body lofar2_unb2c_ring_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_ring_config is
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2c_ring_config is
begin
if g_design_name = "lofar2_unb2c_ring_one" then return c_one;
else return c_full;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
index 2787532589..f09ef05b70 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_ring_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_ring_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmc_lofar2_unb2c_ring is
generic (
@@ -159,64 +159,64 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
u_mm_file_reg_dp_block_validate_err : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
u_mm_file_reg_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
+ port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
u_mm_file_ram_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
+ port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
u_mm_file_reg_ring_lane_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
- port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
+ port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
u_mm_file_reg_dp_xonoff_lane : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
u_mm_file_reg_dp_xonoff_local : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
- port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -231,234 +231,234 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2c_ring
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_copi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_copi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_copi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_copi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_copi.wr,
- pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_copi.rd,
- pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_copi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_copi.wr,
- reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_copi.rd,
- reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_copi.wr,
- reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_copi.rd,
- reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_rx_address_export => reg_bsn_monitor_v2_ring_rx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_read_export => reg_bsn_monitor_v2_ring_rx_copi.rd,
- reg_bsn_monitor_v2_ring_rx_readdata_export => reg_bsn_monitor_v2_ring_rx_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_write_export => reg_bsn_monitor_v2_ring_rx_copi.wr,
- reg_bsn_monitor_v2_ring_rx_writedata_export => reg_bsn_monitor_v2_ring_rx_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_tx_address_export => reg_bsn_monitor_v2_ring_tx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_read_export => reg_bsn_monitor_v2_ring_tx_copi.rd,
- reg_bsn_monitor_v2_ring_tx_readdata_export => reg_bsn_monitor_v2_ring_tx_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_write_export => reg_bsn_monitor_v2_ring_tx_copi.wr,
- reg_bsn_monitor_v2_ring_tx_writedata_export => reg_bsn_monitor_v2_ring_tx_copi.wrdata(c_word_w - 1 downto 0),
-
- -- waveform generators (multiplexed)
- reg_diag_bg_clk_export => OPEN,
- reg_diag_bg_reset_export => OPEN,
- reg_diag_bg_address_export => reg_diag_bg_copi.address(c_sdp_reg_diag_bg_addr_w - 1 downto 0),
- reg_diag_bg_read_export => reg_diag_bg_copi.rd,
- reg_diag_bg_readdata_export => reg_diag_bg_cipo.rddata(c_word_w - 1 downto 0),
- reg_diag_bg_write_export => reg_diag_bg_copi.wr,
- reg_diag_bg_writedata_export => reg_diag_bg_copi.wrdata(c_word_w - 1 downto 0),
-
- ram_diag_bg_clk_export => OPEN,
- ram_diag_bg_reset_export => OPEN,
- ram_diag_bg_address_export => ram_diag_bg_copi.address(c_sdp_ram_diag_bg_addr_w - 1 downto 0),
- ram_diag_bg_read_export => ram_diag_bg_copi.rd,
- ram_diag_bg_readdata_export => ram_diag_bg_cipo.rddata(c_word_w - 1 downto 0),
- ram_diag_bg_write_export => ram_diag_bg_copi.wr,
- ram_diag_bg_writedata_export => ram_diag_bg_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_copi.wr,
- reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_copi.rd,
- reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_ring_lane_info_clk_export => OPEN,
- reg_ring_lane_info_reset_export => OPEN,
- reg_ring_lane_info_address_export => reg_ring_lane_info_copi.address(c_sdp_reg_ring_lane_info_addr_w - 1 downto 0),
- reg_ring_lane_info_write_export => reg_ring_lane_info_copi.wr,
- reg_ring_lane_info_writedata_export => reg_ring_lane_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_lane_info_read_export => reg_ring_lane_info_copi.rd,
- reg_ring_lane_info_readdata_export => reg_ring_lane_info_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_lane_clk_export => OPEN,
- reg_dp_xonoff_lane_reset_export => OPEN,
- reg_dp_xonoff_lane_address_export => reg_dp_xonoff_lane_copi.address(c_sdp_reg_dp_xonoff_lane_addr_w - 1 downto 0),
- reg_dp_xonoff_lane_write_export => reg_dp_xonoff_lane_copi.wr,
- reg_dp_xonoff_lane_writedata_export => reg_dp_xonoff_lane_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_xonoff_lane_read_export => reg_dp_xonoff_lane_copi.rd,
- reg_dp_xonoff_lane_readdata_export => reg_dp_xonoff_lane_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_local_clk_export => OPEN,
- reg_dp_xonoff_local_reset_export => OPEN,
- reg_dp_xonoff_local_address_export => reg_dp_xonoff_local_copi.address(c_sdp_reg_dp_xonoff_local_addr_w - 1 downto 0),
- reg_dp_xonoff_local_write_export => reg_dp_xonoff_local_copi.wr,
- reg_dp_xonoff_local_writedata_export => reg_dp_xonoff_local_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_xonoff_local_read_export => reg_dp_xonoff_local_copi.rd,
- reg_dp_xonoff_local_readdata_export => reg_dp_xonoff_local_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_err_clk_export => OPEN,
- reg_dp_block_validate_err_reset_export => OPEN,
- reg_dp_block_validate_err_address_export => reg_dp_block_validate_err_copi.address(c_sdp_reg_dp_block_validate_err_addr_w - 1 downto 0),
- reg_dp_block_validate_err_write_export => reg_dp_block_validate_err_copi.wr,
- reg_dp_block_validate_err_writedata_export => reg_dp_block_validate_err_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_err_read_export => reg_dp_block_validate_err_copi.rd,
- reg_dp_block_validate_err_readdata_export => reg_dp_block_validate_err_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_bsn_at_sync_clk_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_reset_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_address_export => reg_dp_block_validate_bsn_at_sync_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_write_export => reg_dp_block_validate_bsn_at_sync_copi.wr,
- reg_dp_block_validate_bsn_at_sync_writedata_export => reg_dp_block_validate_bsn_at_sync_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_read_export => reg_dp_block_validate_bsn_at_sync_copi.rd,
- reg_dp_block_validate_bsn_at_sync_readdata_export => reg_dp_block_validate_bsn_at_sync_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_ring_info_clk_export => OPEN,
- reg_ring_info_reset_export => OPEN,
- reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w - 1 downto 0),
- reg_ring_info_write_export => reg_ring_info_copi.wr,
- reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_info_read_export => reg_ring_info_copi.rd,
- reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_tr_10GbE_mac_clk_export => OPEN,
- reg_tr_10GbE_mac_reset_export => OPEN,
- reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w - 1 downto 0),
- reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr,
- reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd,
- reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_tr_10GbE_eth10g_clk_export => OPEN,
- reg_tr_10GbE_eth10g_reset_export => OPEN,
- reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w - 1 downto 0),
- reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr,
- reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd,
- reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_scrap_clk_export => OPEN,
- ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_copi.address(9 - 1 downto 0),
- ram_scrap_write_export => ram_scrap_copi.wr,
- ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_copi.rd,
- ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_copi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_copi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_copi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_copi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_copi.wr,
+ pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_copi.rd,
+ pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_copi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_copi.wr,
+ reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_copi.rd,
+ reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_copi.wr,
+ reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_copi.rd,
+ reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_rx_address_export => reg_bsn_monitor_v2_ring_rx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_read_export => reg_bsn_monitor_v2_ring_rx_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_readdata_export => reg_bsn_monitor_v2_ring_rx_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_write_export => reg_bsn_monitor_v2_ring_rx_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_writedata_export => reg_bsn_monitor_v2_ring_rx_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_tx_address_export => reg_bsn_monitor_v2_ring_tx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_read_export => reg_bsn_monitor_v2_ring_tx_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_readdata_export => reg_bsn_monitor_v2_ring_tx_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_write_export => reg_bsn_monitor_v2_ring_tx_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_writedata_export => reg_bsn_monitor_v2_ring_tx_copi.wrdata(c_word_w - 1 downto 0),
+
+ -- waveform generators (multiplexed)
+ reg_diag_bg_clk_export => OPEN,
+ reg_diag_bg_reset_export => OPEN,
+ reg_diag_bg_address_export => reg_diag_bg_copi.address(c_sdp_reg_diag_bg_addr_w - 1 downto 0),
+ reg_diag_bg_read_export => reg_diag_bg_copi.rd,
+ reg_diag_bg_readdata_export => reg_diag_bg_cipo.rddata(c_word_w - 1 downto 0),
+ reg_diag_bg_write_export => reg_diag_bg_copi.wr,
+ reg_diag_bg_writedata_export => reg_diag_bg_copi.wrdata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_clk_export => OPEN,
+ ram_diag_bg_reset_export => OPEN,
+ ram_diag_bg_address_export => ram_diag_bg_copi.address(c_sdp_ram_diag_bg_addr_w - 1 downto 0),
+ ram_diag_bg_read_export => ram_diag_bg_copi.rd,
+ ram_diag_bg_readdata_export => ram_diag_bg_cipo.rddata(c_word_w - 1 downto 0),
+ ram_diag_bg_write_export => ram_diag_bg_copi.wr,
+ ram_diag_bg_writedata_export => ram_diag_bg_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_copi.wr,
+ reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_copi.rd,
+ reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_ring_lane_info_clk_export => OPEN,
+ reg_ring_lane_info_reset_export => OPEN,
+ reg_ring_lane_info_address_export => reg_ring_lane_info_copi.address(c_sdp_reg_ring_lane_info_addr_w - 1 downto 0),
+ reg_ring_lane_info_write_export => reg_ring_lane_info_copi.wr,
+ reg_ring_lane_info_writedata_export => reg_ring_lane_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_lane_info_read_export => reg_ring_lane_info_copi.rd,
+ reg_ring_lane_info_readdata_export => reg_ring_lane_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_lane_clk_export => OPEN,
+ reg_dp_xonoff_lane_reset_export => OPEN,
+ reg_dp_xonoff_lane_address_export => reg_dp_xonoff_lane_copi.address(c_sdp_reg_dp_xonoff_lane_addr_w - 1 downto 0),
+ reg_dp_xonoff_lane_write_export => reg_dp_xonoff_lane_copi.wr,
+ reg_dp_xonoff_lane_writedata_export => reg_dp_xonoff_lane_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_lane_read_export => reg_dp_xonoff_lane_copi.rd,
+ reg_dp_xonoff_lane_readdata_export => reg_dp_xonoff_lane_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_local_clk_export => OPEN,
+ reg_dp_xonoff_local_reset_export => OPEN,
+ reg_dp_xonoff_local_address_export => reg_dp_xonoff_local_copi.address(c_sdp_reg_dp_xonoff_local_addr_w - 1 downto 0),
+ reg_dp_xonoff_local_write_export => reg_dp_xonoff_local_copi.wr,
+ reg_dp_xonoff_local_writedata_export => reg_dp_xonoff_local_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_local_read_export => reg_dp_xonoff_local_copi.rd,
+ reg_dp_xonoff_local_readdata_export => reg_dp_xonoff_local_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_err_clk_export => OPEN,
+ reg_dp_block_validate_err_reset_export => OPEN,
+ reg_dp_block_validate_err_address_export => reg_dp_block_validate_err_copi.address(c_sdp_reg_dp_block_validate_err_addr_w - 1 downto 0),
+ reg_dp_block_validate_err_write_export => reg_dp_block_validate_err_copi.wr,
+ reg_dp_block_validate_err_writedata_export => reg_dp_block_validate_err_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_err_read_export => reg_dp_block_validate_err_copi.rd,
+ reg_dp_block_validate_err_readdata_export => reg_dp_block_validate_err_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_bsn_at_sync_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_address_export => reg_dp_block_validate_bsn_at_sync_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_write_export => reg_dp_block_validate_bsn_at_sync_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_writedata_export => reg_dp_block_validate_bsn_at_sync_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_read_export => reg_dp_block_validate_bsn_at_sync_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_readdata_export => reg_dp_block_validate_bsn_at_sync_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_ring_info_clk_export => OPEN,
+ reg_ring_info_reset_export => OPEN,
+ reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w - 1 downto 0),
+ reg_ring_info_write_export => reg_ring_info_copi.wr,
+ reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_info_read_export => reg_ring_info_copi.rd,
+ reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_tr_10GbE_mac_clk_export => OPEN,
+ reg_tr_10GbE_mac_reset_export => OPEN,
+ reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w - 1 downto 0),
+ reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr,
+ reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd,
+ reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_tr_10GbE_eth10g_clk_export => OPEN,
+ reg_tr_10GbE_eth10g_reset_export => OPEN,
+ reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w - 1 downto 0),
+ reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr,
+ reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd,
+ reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_address_export => ram_scrap_copi.address(9 - 1 downto 0),
+ ram_scrap_write_export => ram_scrap_copi.wr,
+ ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_copi.rd,
+ ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
index 6cdf83dd53..5f9c2b6183 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
@@ -19,7 +19,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_ring_pkg is
@@ -27,206 +27,206 @@ package qsys_lofar2_unb2c_ring_pkg is
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_ring is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_block_validate_err_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_read_export : out std_logic; -- export
- reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_write_export : out std_logic; -- export
- reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_local_clk_export : out std_logic; -- export
- reg_dp_xonoff_local_read_export : out std_logic; -- export
- reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_local_reset_export : out std_logic; -- export
- reg_dp_xonoff_local_write_export : out std_logic; -- export
- reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_ring_lane_info_clk_export : out std_logic; -- export
- reg_ring_lane_info_read_export : out std_logic; -- export
- reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_reset_export : out std_logic; -- export
- reg_ring_lane_info_write_export : out std_logic; -- export
- reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2c_ring;
+ component qsys_lofar2_unb2c_ring is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
+ ram_diag_bg_clk_export : out std_logic; -- export
+ ram_diag_bg_read_export : out std_logic; -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_reset_export : out std_logic; -- export
+ ram_diag_bg_write_export : out std_logic; -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_clk_export : out std_logic; -- export
+ reg_diag_bg_read_export : out std_logic; -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_reset_export : out std_logic; -- export
+ reg_diag_bg_write_export : out std_logic; -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_block_validate_err_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_local_clk_export : out std_logic; -- export
+ reg_dp_xonoff_local_read_export : out std_logic; -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_local_reset_export : out std_logic; -- export
+ reg_dp_xonoff_local_write_export : out std_logic; -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_ring_lane_info_clk_export : out std_logic; -- export
+ reg_ring_lane_info_read_export : out std_logic; -- export
+ reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_reset_export : out std_logic; -- export
+ reg_ring_lane_info_write_export : out std_logic; -- export
+ reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2c_ring;
end qsys_lofar2_unb2c_ring_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
index 2af846791d..d25cffd201 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
@@ -33,22 +33,22 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.lofar2_unb2c_ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.lofar2_unb2c_ring_pkg.all;
entity tb_lofar2_unb2c_ring is
generic (
@@ -168,49 +168,49 @@ begin
------------------------------------------------------------------------------
-- DUTs
------------------------------------------------------------------------------
- gen_dut_rn : for RN in 0 to g_nof_rn - 1 generate
+ gen_dut_rn : for RN in 0 to g_nof_rn - 1 generate
u_lofar_unb2c_ring : entity work.lofar2_unb2c_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => g_unb_nr + (RN / c_quad),
- g_sim_node_nr => RN mod c_quad,
- g_sim_sync_timeout => c_sync_timeout
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2c_board_nof_chip_w) ),
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX(RN),
- QSFP_0_TX => i_QSFP_0_TX(RN),
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX(RN),
- RING_0_TX => i_RING_0_TX(RN),
- RING_1_RX => i_RING_1_RX(RN),
- RING_1_TX => i_RING_1_TX(RN),
- -- LEDs
- QSFP_LED => open
-
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => g_unb_nr + (RN / c_quad),
+ g_sim_node_nr => RN mod c_quad,
+ g_sim_sync_timeout => c_sync_timeout
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2c_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+ -- LEDs
+ QSFP_LED => open
+
+ );
end generate;
-- Ring connections
@@ -319,8 +319,8 @@ begin
-- Verify Access scheme 2,3 by reading rx / tx monitors on all RN
----------------------------------------------------------------------------
else
- -- Wait for bsn monitor to have received a sync period.
- mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
+ -- Wait for bsn monitor to have received a sync period.
+ mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
"SIGNED", rd_data, ">", 0, -- this is the wait until condition
1 us, tb_clk); -- read every 1 us
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
index 5646c6aacf..f14f9e30ea 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
@@ -29,9 +29,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_tb_lofar2_unb2c_ring is
end tb_tb_lofar2_unb2c_ring;
@@ -43,14 +43,14 @@ architecture tb of tb_tb_lofar2_unb2c_ring is
signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
begin
--- g_multi_tb : BOOLEAN := FALSE;
--- g_unb_nr : NATURAL := 4;
--- g_design_name : STRING := "lofar2_unb2c_ring_one";
--- g_nof_rn : NATURAL := 16;
--- g_nof_block_per_sync : NATURAL := 32;
--- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
+ -- g_multi_tb : BOOLEAN := FALSE;
+ -- g_unb_nr : NATURAL := 4;
+ -- g_design_name : STRING := "lofar2_unb2c_ring_one";
+ -- g_nof_rn : NATURAL := 16;
+ -- g_nof_block_per_sync : NATURAL := 32;
+ -- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
--- using different g_unb_nr to avoid MM file clashing.
+ -- using different g_unb_nr to avoid MM file clashing.
u_one_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 0, "lofar2_unb2c_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0)); -- access scheme 1.
u_one_2_3 : entity work.tb_lofar2_unb2c_ring generic map(true, 1, "lofar2_unb2c_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 2, "lofar2_unb2c_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2)); -- access scheme 1.
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
index e1dcded39d..cf1f463637 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2c_sdp_station_full is
generic (
@@ -83,7 +83,7 @@ entity disturb2_unb2c_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -107,59 +107,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
index bd4765698e..a249119842 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2c_sdp_station_full_wg is
generic (
@@ -90,51 +90,51 @@ architecture str of disturb2_unb2c_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index 47b9396044..e84c717e73 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_adc is
generic (
@@ -67,7 +67,7 @@ entity lofar2_unb2c_sdp_station_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -93,43 +93,43 @@ begin
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
index e0a8c79d03..751ef38889 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
@@ -44,19 +44,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_adc is
end tb_lofar2_unb2c_sdp_station_adc;
@@ -161,44 +161,44 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_adc : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_adc",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_adc",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
index 48aaf31309..63a04b2445 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
@@ -53,20 +53,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_jesd204b_lib.tech_jesd204b_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_jesd204b_lib.tech_jesd204b_pkg.all;
entity tb_lofar2_unb2c_sdp_station_adc_jesd is
end tb_lofar2_unb2c_sdp_station_adc_jesd;
@@ -218,17 +218,18 @@ architecture tb of tb_lofar2_unb2c_sdp_station_adc_jesd is
signal dbg_link_reinit : std_logic := '0';
-- Read JESD204B IP status per signal input c_si
- procedure proc_read_jesd204b(c_si : in natural;
- signal rd_clk : in std_logic;
- signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
- signal dbg_read : out std_logic;
- signal rx_err_enable : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_err_link_reinit : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_syncn_sysref_ctrl : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_err0 : out std_logic_vector(tech_jesd204b_field_rx_err0_w - 1 downto 0);
- signal rx_err1 : out std_logic_vector(tech_jesd204b_field_rx_err1_w - 1 downto 0);
- signal csr_rbd_count : out std_logic_vector(tech_jesd204b_field_csr_rbd_count_w - 1 downto 0);
- signal csr_dev_syncn : out std_logic_vector(tech_jesd204b_field_csr_dev_syncn_w - 1 downto 0)) is
+ procedure proc_read_jesd204b (
+ c_si : in natural;
+ signal rd_clk : in std_logic;
+ signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
+ signal dbg_read : out std_logic;
+ signal rx_err_enable : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_err_link_reinit : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_syncn_sysref_ctrl : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_err0 : out std_logic_vector(tech_jesd204b_field_rx_err0_w - 1 downto 0);
+ signal rx_err1 : out std_logic_vector(tech_jesd204b_field_rx_err1_w - 1 downto 0);
+ signal csr_rbd_count : out std_logic_vector(tech_jesd204b_field_csr_rbd_count_w - 1 downto 0);
+ signal csr_dev_syncn : out std_logic_vector(tech_jesd204b_field_csr_dev_syncn_w - 1 downto 0)) is
constant c_offset : natural := c_si * tech_jesd204b_port_span;
begin
dbg_read <= '1';
@@ -249,16 +250,17 @@ architecture tb of tb_lofar2_unb2c_sdp_station_adc_jesd is
dbg_read <= '0';
end;
- procedure proc_read_jesd204b_arr(signal rd_clk : in std_logic;
- signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
- signal dbg_read : out std_logic;
- signal rx_err_enable : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_err_link_reinit : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_syncn_sysref_ctrl : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_err0 : out std_logic_vector(tech_jesd204b_field_rx_err0_w - 1 downto 0);
- signal rx_err1 : out std_logic_vector(tech_jesd204b_field_rx_err1_w - 1 downto 0);
- signal csr_rbd_count : out std_logic_vector(tech_jesd204b_field_csr_rbd_count_w - 1 downto 0);
- signal csr_dev_syncn : out std_logic_vector(tech_jesd204b_field_csr_dev_syncn_w - 1 downto 0)) is
+ procedure proc_read_jesd204b_arr (
+ signal rd_clk : in std_logic;
+ signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
+ signal dbg_read : out std_logic;
+ signal rx_err_enable : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_err_link_reinit : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_syncn_sysref_ctrl : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_err0 : out std_logic_vector(tech_jesd204b_field_rx_err0_w - 1 downto 0);
+ signal rx_err1 : out std_logic_vector(tech_jesd204b_field_rx_err1_w - 1 downto 0);
+ signal csr_rbd_count : out std_logic_vector(tech_jesd204b_field_csr_rbd_count_w - 1 downto 0);
+ signal csr_dev_syncn : out std_logic_vector(tech_jesd204b_field_csr_dev_syncn_w - 1 downto 0)) is
begin
for I in 0 to c_sdp_S_pn - 1 loop
proc_read_jesd204b(I, rd_clk, rd_data, dbg_read,
@@ -295,44 +297,44 @@ begin
-- DUT with JESD204B Rx
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_adc : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_adc",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => JESD204B_SYNC_N
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_adc",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N
+ );
-----------------------------------------------------------------------------
-- Use a JESD204b Tx instance to model the ADCs
@@ -374,55 +376,55 @@ begin
gen_jesd204b_tx : for i in 0 to c_nof_jesd204b_tx - 1 generate
-- Tb DAC
u_tech_jesd204b_tx : entity tech_jesd204b_lib.tech_jesd204b_tx
- port map (
- csr_cf => OPEN,
- csr_cs => OPEN,
- csr_f => OPEN,
- csr_hd => OPEN,
- csr_k => OPEN,
- csr_l => OPEN,
- csr_lane_powerdown => open, -- out
- csr_m => OPEN,
- csr_n => OPEN,
- csr_np => OPEN,
- csr_tx_testmode => OPEN,
- csr_tx_testpattern_a => OPEN,
- csr_tx_testpattern_b => OPEN,
- csr_tx_testpattern_c => OPEN,
- csr_tx_testpattern_d => OPEN,
- csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), -- out
- jesd204_tx_avs_chipselect => tx_avs_chipselect(i),
- jesd204_tx_avs_address => tx_avs_address(i),
- jesd204_tx_avs_read => tx_avs_read(i),
- jesd204_tx_avs_readdata => tx_avs_readdata(i),
- jesd204_tx_avs_waitrequest => open,
- jesd204_tx_avs_write => '0',
- jesd204_tx_avs_writedata => (others => '0'),
- jesd204_tx_avs_clk => tx_avs_clk,
- jesd204_tx_avs_rst_n => tx_avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
- jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
- jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
- mdev_sync_n => dev_sync_n(i), -- in
- pll_locked => pll_locked, -- in
- sync_n => jesd204b_sync_adc_n(i), -- in
- tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy => open,
- tx_digitalreset => tx_digitalreset,
- tx_serial_data => JESD204B_SERIAL_DATA(i downto i),
- txlink_clk => txlink_clk(i),
- txlink_rst_n_reset_n => txlink_rst_n,
- txphy_clk => txphy_clk(i downto i),
- somf => OPEN,
- sysref => JESD204B_SYSREF
- );
+ port map (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, -- out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), -- out
+ jesd204_tx_avs_chipselect => tx_avs_chipselect(i),
+ jesd204_tx_avs_address => tx_avs_address(i),
+ jesd204_tx_avs_read => tx_avs_read(i),
+ jesd204_tx_avs_readdata => tx_avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => tx_avs_clk,
+ jesd204_tx_avs_rst_n => tx_avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
+ mdev_sync_n => dev_sync_n(i), -- in
+ pll_locked => pll_locked, -- in
+ sync_n => jesd204b_sync_adc_n(i), -- in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => JESD204B_SERIAL_DATA(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => JESD204B_SYSREF
+ );
-- One JESD204B_SYNC_N per RCU2
jesd204b_sync_adc_n(i) <= JESD204B_SYNC_N(i / c_sdp_S_rcu);
@@ -433,34 +435,34 @@ begin
variable v_even_sample : boolean := true;
begin
if mm_rst = '1' then
- jesd204b_tx_link_data_arr(i) <= (others => '0');
- jesd204b_tx_link_valid(i) <= '0';
- txlink_clk(i) <= '0';
- v_data := 0;
- v_even_sample := true;
- elsif rising_edge(JESD204B_REFCLK) then
- txlink_clk(i) <= not txlink_clk(i);
-
- -- Incrementing data in c_sdp_W_adc_jesd = 16 bits
- -- . use range c_sdp_W_adc_jesd-1 to avoid simulation warnings:
- -- Warning: NUMERIC_STD.TO_SIGNED: vector truncated
- -- Time: 164635 ns Iteration: 0 Region: /tb_lofar2_unb2c_sdp_station_adc_jesd/gen_jesd204b_tx(2)
- v_data := (v_data + 1) mod 2**(c_sdp_W_adc_jesd - 1);
-
- -- Frame the data to 32 bits at half the rate
- if jesd204b_tx_link_ready(i) = '0' then
- v_even_sample := true;
- else
- v_even_sample := not v_even_sample;
- end if;
- if v_even_sample = true then
- jesd204b_tx_link_data_arr(i)(c_sdp_W_adc_jesd - 1 downto 0) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
- jesd204b_tx_link_valid(i) <= '0';
- else
- jesd204b_tx_link_data_arr(i)(2 * c_sdp_W_adc_jesd - 1 downto c_sdp_W_adc_jesd) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
- jesd204b_tx_link_valid(i) <= '1';
- end if;
- end if;
+ jesd204b_tx_link_data_arr(i) <= (others => '0');
+ jesd204b_tx_link_valid(i) <= '0';
+ txlink_clk(i) <= '0';
+ v_data := 0;
+ v_even_sample := true;
+ elsif rising_edge(JESD204B_REFCLK) then
+ txlink_clk(i) <= not txlink_clk(i);
+
+ -- Incrementing data in c_sdp_W_adc_jesd = 16 bits
+ -- . use range c_sdp_W_adc_jesd-1 to avoid simulation warnings:
+ -- Warning: NUMERIC_STD.TO_SIGNED: vector truncated
+ -- Time: 164635 ns Iteration: 0 Region: /tb_lofar2_unb2c_sdp_station_adc_jesd/gen_jesd204b_tx(2)
+ v_data := (v_data + 1) mod 2**(c_sdp_W_adc_jesd - 1);
+
+ -- Frame the data to 32 bits at half the rate
+ if jesd204b_tx_link_ready(i) = '0' then
+ v_even_sample := true;
+ else
+ v_even_sample := not v_even_sample;
+ end if;
+ if v_even_sample = true then
+ jesd204b_tx_link_data_arr(i)(c_sdp_W_adc_jesd - 1 downto 0) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
+ jesd204b_tx_link_valid(i) <= '0';
+ else
+ jesd204b_tx_link_data_arr(i)(2 * c_sdp_W_adc_jesd - 1 downto c_sdp_W_adc_jesd) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
+ jesd204b_tx_link_valid(i) <= '1';
+ end if;
+ end if;
end process;
end generate;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 6c63cfa6b5..be92aed478 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_bf is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2c_sdp_station_bf is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -99,50 +99,50 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index a925ba49ae..43984a371c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -133,24 +133,24 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_sdp_station_bf is
generic (
@@ -225,16 +225,20 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ TO_UVEC(
+ 3,
+ 6), -- antenna_field_index
+ TO_UVEC(
+ 601,
+ 10), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
-- WG
constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
@@ -285,18 +289,18 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
-- . Beamlet internal
constant c_nof_remnant : natural := c_sdp_S_pn - 1;
constant c_exp_beamlet_x_tuple : t_real_arr(0 to 3) := func_sdp_beamformer(
- c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
- c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase,
- c_nof_remnant);
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase,
+ c_nof_remnant);
constant c_exp_beamlet_x_ampl : real := c_exp_beamlet_x_tuple(0);
constant c_exp_beamlet_x_phase : real := c_exp_beamlet_x_tuple(1);
constant c_exp_beamlet_x_re : real := c_exp_beamlet_x_tuple(2);
constant c_exp_beamlet_x_im : real := c_exp_beamlet_x_tuple(3);
constant c_exp_beamlet_y_tuple : t_real_arr(0 to 3) := func_sdp_beamformer(
- c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
- c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase,
- c_nof_remnant);
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase,
+ c_nof_remnant);
constant c_exp_beamlet_y_ampl : real := c_exp_beamlet_y_tuple(0);
constant c_exp_beamlet_y_phase : real := c_exp_beamlet_y_tuple(1);
constant c_exp_beamlet_y_re : real := c_exp_beamlet_y_tuple(2);
@@ -508,121 +512,121 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_bf : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_1_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_0,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- CEP model
------------------------------------------------------------------------------
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => dest_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => dest_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => true,
- g_sim_level => 1,
- g_nof_macs => 1,
- g_use_mdio => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM interface
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- -- DP interface
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- serial_rx_arr(0) => si_lpbk_0(0),
-
- src_out_arr(0) => tr_10GbE_src_out,
- src_in_arr(0) => tr_10GbE_src_in
- );
+ generic map (
+ g_sim => true,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => si_lpbk_0(0),
+
+ src_out_arr(0) => tr_10GbE_src_out,
+ src_in_arr(0) => tr_10GbE_src_in
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_octet_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- reg_hdr_dat_mosi => rx_hdr_dat_mosi,
- reg_hdr_dat_miso => rx_hdr_dat_miso,
-
- snk_in_arr(0) => tr_10GbE_src_out,
- snk_out_arr(0) => tr_10GbE_src_in,
-
- src_out_arr(0) => rx_beamlet_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_octet_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ reg_hdr_dat_mosi => rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => rx_hdr_dat_miso,
+
+ snk_in_arr(0) => tr_10GbE_src_out,
+ snk_out_arr(0) => tr_10GbE_src_in,
+
+ src_out_arr(0) => rx_beamlet_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
index 2e3e9aa825..600f7f99f9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
@@ -39,20 +39,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_bf_bst_offload is
end tb_lofar2_unb2c_sdp_station_bf_bst_offload;
@@ -84,16 +84,20 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_bst_offload is
constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ TO_UVEC(
+ 3,
+ 6), -- antenna_field_index
+ TO_UVEC(
+ 601,
+ 10), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
-- MM
constant c_mm_file_reg_sdp_info : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
@@ -176,44 +180,44 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_bf : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -279,38 +283,38 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- eth_src_out => eth_rx_sosi,
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ eth_src_out => eth_rx_sosi,
+ tb_end => eth_done
+ );
eth_rx_data <= eth_rx_sosi.data(c_32 - 1 downto 0);
-- . Verify XST packet header
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => pps_rst,
- mm_clk => tb_clk,
-
- dp_rst => pps_rst,
- dp_clk => eth_clk(0),
-
- snk_in_arr(0) => eth_rx_sosi,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => pps_rst,
+ dp_clk => eth_clk(0),
+
+ snk_in_arr(0) => eth_rx_sosi,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
index 1516651fc4..35f40f1a1c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_tb_lofar2_unb2c_sdp_station_bf is
@@ -42,25 +42,25 @@ architecture tb of tb_tb_lofar2_unb2c_sdp_station_bf is
begin
u_bf : entity work.tb_lofar2_unb2c_sdp_station_bf
- generic map (
- g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
- g_sp_ampl => 0.5, -- WG normalized amplitude
- g_sp_phase => -110.0, -- WG phase in degrees = subband phase
- g_sp_remnant_ampl => 0.1, -- WG normalized amplitude for remnant sp
- g_sp_remnant_phase => 15.0, -- WG phase in degrees for remnant sp
- g_subband => 102, -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_beamlet => c_sdp_S_sub_bf - 1, -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
- g_beamlet_scale => 1.0 / 2.0**9, -- g_beamlet output scale factor
- g_bf_x_gain => 0.7, -- g_beamlet X BF weight normalized gain for g_sp
- g_bf_y_gain => 0.6, -- g_beamlet Y BF weight normalized gain for g_sp
- g_bf_x_phase => 30.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_y_phase => 40.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_bf_remnant_x_gain => 0.05, -- g_beamlet X BF weight normalized gain for remnant sp
- g_bf_remnant_y_gain => 0.04, -- g_beamlet Y BF weight normalized gain for remnant sp
- g_bf_remnant_x_phase => 170.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_remnant_y_phase => -135.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_read_all_SST => false, -- when FALSE only read SST for g_subband, to save sim time
- g_read_all_BST => false -- when FALSE only read BST for g_beamlet, to save sim time
- );
+ generic map (
+ g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
+ g_sp_ampl => 0.5, -- WG normalized amplitude
+ g_sp_phase => -110.0, -- WG phase in degrees = subband phase
+ g_sp_remnant_ampl => 0.1, -- WG normalized amplitude for remnant sp
+ g_sp_remnant_phase => 15.0, -- WG phase in degrees for remnant sp
+ g_subband => 102, -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_beamlet => c_sdp_S_sub_bf - 1, -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet_scale => 1.0 / 2.0**9, -- g_beamlet output scale factor
+ g_bf_x_gain => 0.7, -- g_beamlet X BF weight normalized gain for g_sp
+ g_bf_y_gain => 0.6, -- g_beamlet Y BF weight normalized gain for g_sp
+ g_bf_x_phase => 30.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_y_phase => 40.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_x_gain => 0.05, -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain => 0.04, -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_x_phase => 170.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_y_phase => -135.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_read_all_SST => false, -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_BST => false -- when FALSE only read BST for g_beamlet, to save sim time
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
index d449e94b38..53d931e95f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_bf is
generic (
@@ -86,7 +86,7 @@ entity lofar2_unb2c_sdp_station_bf is
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -111,59 +111,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
index 879bc4cfe1..86078030a9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -125,24 +125,24 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_sdp_station_bf_ring is
generic (
@@ -230,16 +230,20 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ TO_UVEC(
+ 3,
+ 6), -- antenna_field_index
+ TO_UVEC(
+ 601,
+ 10), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
-- WG
constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
@@ -290,18 +294,18 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
-- . Beamlet internal
constant c_nof_remnant : natural := g_nof_rn * c_sdp_S_pn - 1;
constant c_exp_beamlet_x_tuple : t_real_arr(0 to 3) := func_sdp_beamformer(
- c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
- c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase,
- c_nof_remnant);
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase,
+ c_nof_remnant);
constant c_exp_beamlet_x_ampl : real := c_exp_beamlet_x_tuple(0);
constant c_exp_beamlet_x_phase : real := c_exp_beamlet_x_tuple(1);
constant c_exp_beamlet_x_re : real := c_exp_beamlet_x_tuple(2);
constant c_exp_beamlet_x_im : real := c_exp_beamlet_x_tuple(3);
constant c_exp_beamlet_y_tuple : t_real_arr(0 to 3) := func_sdp_beamformer(
- c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
- c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase,
- c_nof_remnant);
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase,
+ c_nof_remnant);
constant c_exp_beamlet_y_ampl : real := c_exp_beamlet_y_tuple(0);
constant c_exp_beamlet_y_phase : real := c_exp_beamlet_y_tuple(1);
constant c_exp_beamlet_y_re : real := c_exp_beamlet_y_tuple(2);
@@ -513,61 +517,61 @@ begin
------------------------------------------------------------------------------
gen_dut : for RN in 0 to c_last_rn generate
u_lofar_unb2c_sdp_station_bf : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_bf_ring",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => (g_first_gn + RN) / c_quad,
- g_sim_node_nr => (g_first_gn + RN) mod c_quad,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => ( TO_UVEC((g_first_gn + RN) / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC((g_first_gn + RN) mod c_quad, c_unb2c_board_nof_chip_w) ),
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers for ring
- QSFP_0_RX => i_QSFP_0_RX(RN),
- QSFP_0_TX => i_QSFP_0_TX(RN),
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX(RN),
- RING_0_TX => i_RING_0_TX(RN),
- RING_1_RX => i_RING_1_RX(RN),
- RING_1_TX => i_RING_1_TX(RN),
-
- -- front transceivers for CEP
- QSFP_1_RX => i_QSFP_1_lpbk(RN),
- QSFP_1_TX => i_QSFP_1_lpbk(RN),
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_bf_ring",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => (g_first_gn + RN) / c_quad,
+ g_sim_node_nr => (g_first_gn + RN) mod c_quad,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC((g_first_gn + RN) / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC((g_first_gn + RN) mod c_quad, c_unb2c_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers for ring
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+
+ -- front transceivers for CEP
+ QSFP_1_RX => i_QSFP_1_lpbk(RN),
+ QSFP_1_TX => i_QSFP_1_lpbk(RN),
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
end generate;
-- Ring connections
@@ -585,71 +589,71 @@ begin
-- CEP model
------------------------------------------------------------------------------
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => dest_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => dest_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => true,
- g_sim_level => 1,
- g_nof_macs => 1,
- g_use_mdio => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM interface
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- -- DP interface
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- serial_rx_arr(0) => i_QSFP_1_lpbk(c_last_rn)(0), -- Last RN must be used as end node.
-
- src_out_arr(0) => tr_10GbE_src_out,
- src_in_arr(0) => tr_10GbE_src_in
- );
+ generic map (
+ g_sim => true,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => i_QSFP_1_lpbk(c_last_rn)(0), -- Last RN must be used as end node.
+
+ src_out_arr(0) => tr_10GbE_src_out,
+ src_in_arr(0) => tr_10GbE_src_in
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_octet_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- reg_hdr_dat_mosi => rx_hdr_dat_mosi,
- reg_hdr_dat_miso => rx_hdr_dat_miso,
-
- snk_in_arr(0) => tr_10GbE_src_out,
- snk_out_arr(0) => tr_10GbE_src_in,
-
- src_out_arr(0) => rx_beamlet_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_octet_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ reg_hdr_dat_mosi => rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => rx_hdr_dat_miso,
+
+ snk_in_arr(0) => tr_10GbE_src_out,
+ snk_out_arr(0) => tr_10GbE_src_in,
+
+ src_out_arr(0) => rx_beamlet_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index 0beac1eb37..7a46ff4e87 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_fsub is
generic (
@@ -67,7 +67,7 @@ entity lofar2_unb2c_sdp_station_fsub is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -91,43 +91,43 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
index cea5b8ce34..61148b0c8d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -62,20 +62,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
entity tb_lofar2_unb2c_sdp_station_fsub is
generic (
@@ -154,8 +154,8 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
constant c_exp_co_subband_ampl_weighted : real := c_exp_co_subband_ampl_raw * g_co_subband_weight_gain;
constant c_exp_cross_subband_ampl_weighted : real := c_exp_cross_subband_ampl_raw * 1.0; -- unit gain, this is co gain for cross sp
constant c_exp_jones_subband_tuple : t_real_arr(0 to 3) := func_sdp_subband_equalizer(
- c_exp_co_subband_ampl_raw, c_co_subband_phase, g_co_subband_weight_gain, g_co_subband_weight_phase,
- c_exp_cross_subband_ampl_raw, c_cross_subband_phase, g_sp_cross_subband_weight_gain, g_sp_cross_subband_weight_phase);
+ c_exp_co_subband_ampl_raw, c_co_subband_phase, g_co_subband_weight_gain, g_co_subband_weight_phase,
+ c_exp_cross_subband_ampl_raw, c_cross_subband_phase, g_sp_cross_subband_weight_gain, g_sp_cross_subband_weight_phase);
constant c_exp_sp_subband_ampl_weighted : real := sel_a_b(g_use_cross_weight, c_exp_jones_subband_tuple(0), c_exp_co_subband_ampl_weighted);
constant c_exp_co_subband_power_raw : real := c_exp_co_subband_ampl_raw**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
@@ -284,45 +284,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_fsub : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_fsub",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
-- Raw or weighted subbands
exp_sp_subband_ampl <= sel_a_b(sst_offload_weighted_subbands = '0', c_exp_co_subband_ampl_raw, c_exp_sp_subband_ampl_weighted);
@@ -432,7 +432,7 @@ begin
sp_co_subband_weight_im <= v_im;
sp_co_subband_weight_gain <= COMPLEX_RADIUS(real(v_re), real(v_im)) / real(c_sdp_unit_sub_weight);
sp_co_subband_weight_phase <= COMPLEX_PHASE(real(v_re), real(v_im));
- proc_common_wait_some_cycles(tb_clk, 1);
+ proc_common_wait_some_cycles(tb_clk, 1);
assert sp_co_subband_weight_re = c_co_subband_weight_re report "Readback sp_co_subband_weight_re /= c_co_subband_weight_re" severity ERROR;
assert sp_co_subband_weight_im = c_co_subband_weight_im report "Readback sp_co_subband_weight_im /= c_co_subband_weight_im" severity ERROR;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
index 9803806bb7..6e71aaa779 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
@@ -39,19 +39,19 @@
-- Takes about 1h 15 m
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_fsub_sst_offload is
end tb_lofar2_unb2c_sdp_station_fsub_sst_offload;
@@ -157,44 +157,44 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_fsub : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_fsub",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -247,38 +247,38 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- eth_src_out => eth_rx_sosi,
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ eth_src_out => eth_rx_sosi,
+ tb_end => eth_done
+ );
eth_rx_data <= eth_rx_sosi.data(c_32 - 1 downto 0);
-- . Verify XST packet header
u_rx_statistics : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => pps_rst,
- mm_clk => tb_clk,
-
- dp_rst => pps_rst,
- dp_clk => eth_clk(0),
-
- snk_in_arr(0) => eth_rx_sosi,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => pps_rst,
+ dp_clk => eth_clk(0),
+
+ snk_in_arr(0) => eth_rx_sosi,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
index 5882edc640..cf63f00546 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_tb_lofar2_unb2c_sdp_station_fsub is
@@ -41,35 +41,35 @@ architecture tb of tb_tb_lofar2_unb2c_sdp_station_fsub is
begin
--- Commented to save sim time in regression test
--- u_fsub_only_co : ENTITY work.tb_lofar2_unb2c_sdp_station_fsub
--- GENERIC MAP (
--- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
--- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
--- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
--- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
--- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
--- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
--- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
--- g_use_cross_weight => FALSE,
--- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
--- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
--- g_read_all_SST => TRUE -- when FALSE only read SST for g_subband, to save sim time
--- );
+ -- Commented to save sim time in regression test
+ -- u_fsub_only_co : ENTITY work.tb_lofar2_unb2c_sdp_station_fsub
+ -- GENERIC MAP (
+ -- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
+ -- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ -- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ -- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
+ -- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
+ -- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ -- g_use_cross_weight => FALSE,
+ -- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
+ -- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
+ -- g_read_all_SST => TRUE -- when FALSE only read SST for g_subband, to save sim time
+ -- );
u_fsub_use_cross : entity work.tb_lofar2_unb2c_sdp_station_fsub
- generic map (
- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
- g_use_cross_weight => true,
- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
- g_read_all_SST => true -- when FALSE only read SST for g_subband, to save sim time
- );
+ generic map (
+ g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
+ g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
+ g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
+ g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ g_use_cross_weight => true,
+ g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
+ g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
+ g_read_all_SST => true -- when FALSE only read SST for g_subband, to save sim time
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index 4e029c5caf..2fcf73f043 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_full is
generic (
@@ -83,7 +83,7 @@ entity lofar2_unb2c_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -107,59 +107,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
index 4997f42d39..21bcab4159 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_full_wg is
generic (
@@ -90,51 +90,51 @@ architecture str of lofar2_unb2c_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index 1941049c49..21da4d445a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_xsub_one is
generic (
@@ -67,7 +67,7 @@ entity lofar2_unb2c_sdp_station_xsub_one is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -91,43 +91,43 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
index 6cf991c91b..ec40834d66 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -47,19 +47,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_xsub_one is
end tb_lofar2_unb2c_sdp_station_xsub_one;
@@ -169,45 +169,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_xsub_one : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_xsub_one",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
index 56f2437d8d..32dc5d6f30 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
@@ -52,19 +52,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload is
generic (
@@ -208,44 +208,44 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_xsub_one : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_xsub_one",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -363,38 +363,38 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- eth_src_out => eth_rx_sosi,
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ eth_src_out => eth_rx_sosi,
+ tb_end => eth_done
+ );
eth_rx_data <= eth_rx_sosi.data(c_32 - 1 downto 0);
-- . View / verify XST packet header
u_rx_statistics : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => pps_rst,
- mm_clk => tb_clk,
-
- dp_rst => pps_rst,
- dp_clk => eth_clk(0),
-
- snk_in_arr(0) => eth_rx_sosi,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => pps_rst,
+ dp_clk => eth_clk(0),
+
+ snk_in_arr(0) => eth_rx_sosi,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
@@ -416,10 +416,10 @@ begin
case rx_word_cnt is
when 0 => rx_sdp_stat_data <= rx_offload_sosi.data(c_32 - 1 downto 0);
when 1 => rx_sdp_stat_re <= rx_sdp_stat_data & rx_offload_sosi.data(c_32 - 1 downto 0);
- rx_sdp_stat_re_val <= '1';
+ rx_sdp_stat_re_val <= '1';
when 2 => rx_sdp_stat_data <= rx_offload_sosi.data(c_32 - 1 downto 0);
when 3 => rx_sdp_stat_im <= rx_sdp_stat_data & rx_offload_sosi.data(c_32 - 1 downto 0);
- rx_sdp_stat_im_val <= '1';
+ rx_sdp_stat_im_val <= '1';
when others => null;
end case;
end if;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
index 57fc97484c..53f9c35778 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
@@ -27,13 +27,13 @@
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_xsub_ring is
generic (
@@ -83,7 +83,7 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -107,59 +107,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 19bc94fc79..7804992c28 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -27,20 +27,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_sdp_station_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_sdp_station_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2c_sdp_station is
@@ -97,9 +97,9 @@ entity lofar2_unb2c_sdp_station is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0'); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -475,297 +475,297 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_sdp_station
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo,
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
+ );
-- Use full 8 bit gn_id = ID
gn_id <= ID;
@@ -774,199 +774,199 @@ begin
-- sdp nodes
-----------------------------------------------------------------------------
u_sdp_station : entity lofar2_sdp_lib.sdp_station
- generic map (
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_scope_selected_subband => g_scope_selected_subband,
- g_no_jesd => c_revision_select.no_jesd,
- g_use_fsub => c_revision_select.use_fsub,
- g_use_oversample => c_revision_select.use_oversample,
- g_use_xsub => c_revision_select.use_xsub,
- g_use_bf => c_revision_select.use_bf,
- g_use_ring => c_revision_select.use_ring,
- g_P_sq => c_revision_select.P_sq
- )
- port map (
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_pps => dp_pps,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- gn_id => gn_id,
- this_bck_id => this_bck_id,
- this_chip_id => this_chip_id,
-
- SA_CLK => SA_CLK,
-
- -- jesd204b
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => JESD204B_SYNC_N,
-
- -- UDP Offload
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- -- 10 GbE
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-
- -- AIT
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-
- -- FSUB
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
-
- -- SDP Info
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
-
- -- RING Info
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
-
- -- XSUB
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- -- BF
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
-
- -- SST
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- -- XST
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-
- -- BST
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- RING_0_TX => RING_0_TX,
- RING_0_RX => RING_0_RX,
- RING_1_TX => RING_1_TX,
- RING_1_RX => RING_1_RX,
-
- -- QSFP serial
- unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
-
- -- QSFP LEDS
- unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_scope_selected_subband => g_scope_selected_subband,
+ g_no_jesd => c_revision_select.no_jesd,
+ g_use_fsub => c_revision_select.use_fsub,
+ g_use_oversample => c_revision_select.use_oversample,
+ g_use_xsub => c_revision_select.use_xsub,
+ g_use_bf => c_revision_select.use_bf,
+ g_use_ring => c_revision_select.use_ring,
+ g_P_sq => c_revision_select.P_sq
+ )
+ port map (
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_pps => dp_pps,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ gn_id => gn_id,
+ this_bck_id => this_bck_id,
+ this_chip_id => this_chip_id,
+
+ SA_CLK => SA_CLK,
+
+ -- jesd204b
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N,
+
+ -- UDP Offload
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ -- 10 GbE
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+
+ -- AIT
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+
+ -- FSUB
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+
+ -- SDP Info
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+
+ -- RING Info
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+
+ -- XSUB
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ -- BF
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
+ -- SST
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ -- XST
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+
+ -- BST
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ RING_0_TX => RING_0_TX,
+ RING_0_RX => RING_0_RX,
+ RING_1_TX => RING_1_TX,
+ RING_1_RX => RING_1_RX,
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
@@ -980,41 +980,41 @@ begin
-- Front IO
------------
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- LEDs
------------
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index f7b15514a3..85382e9c9a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -20,14 +20,14 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_sdp_station_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -53,7 +53,7 @@ package lofar2_unb2c_sdp_station_pkg is
constant c_full_os : t_lofar2_unb2c_sdp_station_config := (false, true, true, true, true, true, 9);
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_sdp_station_config;
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2c_sdp_station_config;
end lofar2_unb2c_sdp_station_pkg;
@@ -61,7 +61,7 @@ end lofar2_unb2c_sdp_station_pkg;
package body lofar2_unb2c_sdp_station_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_sdp_station_config is
+ function func_sel_revision_rec (g_design_name : string) return t_lofar2_unb2c_sdp_station_config is
begin
if g_design_name = "lofar2_unb2c_sdp_station_adc" then return c_ait;
elsif g_design_name = "lofar2_unb2c_sdp_station_fsub" then return c_fsub;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index ebfd3d5a24..775aec6880 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_sdp_station_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_sdp_station_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2c_sdp_station is
generic (
@@ -143,187 +143,187 @@ entity mmm_lofar2_unb2c_sdp_station is
reg_si_copi : out t_mem_copi;
reg_si_cipo : in t_mem_cipo;
- -- Equalizer gains
- ram_equalizer_gains_copi : out t_mem_copi;
- ram_equalizer_gains_cipo : in t_mem_cipo;
- ram_equalizer_gains_cross_copi : out t_mem_copi;
- ram_equalizer_gains_cross_cipo : in t_mem_cipo;
+ -- Equalizer gains
+ ram_equalizer_gains_copi : out t_mem_copi;
+ ram_equalizer_gains_cipo : in t_mem_cipo;
+ ram_equalizer_gains_cross_copi : out t_mem_copi;
+ ram_equalizer_gains_cross_cipo : in t_mem_cipo;
- -- DP Selector
- reg_dp_selector_copi : out t_mem_copi;
- reg_dp_selector_cipo : in t_mem_cipo;
+ -- DP Selector
+ reg_dp_selector_copi : out t_mem_copi;
+ reg_dp_selector_cipo : in t_mem_cipo;
- -- SDP Info
- reg_sdp_info_copi : out t_mem_copi;
- reg_sdp_info_cipo : in t_mem_cipo;
+ -- SDP Info
+ reg_sdp_info_copi : out t_mem_copi;
+ reg_sdp_info_cipo : in t_mem_cipo;
- -- RING Info
- reg_ring_info_copi : out t_mem_copi;
- reg_ring_info_cipo : in t_mem_cipo;
+ -- RING Info
+ reg_ring_info_copi : out t_mem_copi;
+ reg_ring_info_cipo : in t_mem_cipo;
- -- Beamlet Subband Select
- ram_ss_ss_wide_copi : out t_mem_copi;
- ram_ss_ss_wide_cipo : in t_mem_cipo;
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_copi : out t_mem_copi;
+ ram_ss_ss_wide_cipo : in t_mem_cipo;
- -- Local BF bf weights
- ram_bf_weights_copi : out t_mem_copi;
- ram_bf_weights_cipo : in t_mem_cipo;
+ -- Local BF bf weights
+ ram_bf_weights_copi : out t_mem_copi;
+ ram_bf_weights_cipo : in t_mem_cipo;
- -- BF bsn aligner_v2
- reg_bsn_align_v2_bf_copi : out t_mem_copi;
- reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : out t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
- -- BF bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
-
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_copi : out t_mem_copi;
- reg_bf_scale_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output header fields
- reg_hdr_dat_copi : out t_mem_copi;
- reg_hdr_dat_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_copi : out t_mem_copi;
- reg_dp_xonoff_cipo : in t_mem_cipo;
-
- -- BF ring lane info
- reg_ring_lane_info_bf_copi : out t_mem_copi;
- reg_ring_lane_info_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
-
- -- BF ring validate err
- reg_dp_block_validate_err_bf_copi : out t_mem_copi;
- reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics (BST)
- ram_st_bst_copi : out t_mem_copi;
- ram_st_bst_cipo : in t_mem_cipo;
-
- -- Subband Statistics offload
- reg_stat_enable_sst_copi : out t_mem_copi;
- reg_stat_enable_sst_cipo : in t_mem_cipo;
-
- -- Statistics header info
- reg_stat_hdr_dat_sst_copi : out t_mem_copi;
- reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics offload
- reg_stat_enable_xst_copi : out t_mem_copi;
- reg_stat_enable_xst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_copi : out t_mem_copi;
- reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics offload
- reg_stat_enable_bst_copi : out t_mem_copi;
- reg_stat_enable_bst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_copi : out t_mem_copi;
- reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_crosslets_info_copi : out t_mem_copi;
- reg_crosslets_info_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_nof_crosslets_copi : out t_mem_copi;
- reg_nof_crosslets_cipo : in t_mem_cipo;
-
- -- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
- reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
-
- -- st_xsq (XST)
- ram_st_xsq_copi : out t_mem_copi;
- ram_st_xsq_cipo : in t_mem_cipo;
-
- -- 10 GbE mac
- reg_nw_10GbE_mac_copi : out t_mem_copi;
- reg_nw_10GbE_mac_cipo : in t_mem_cipo;
-
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_copi : out t_mem_copi;
- reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2
- reg_bsn_align_v2_xsub_copi : out t_mem_copi;
- reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
-
- -- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
-
- -- BST UDP offload bsn monitor
- reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
-
- -- Beamlet output bsn monitor
- reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
- reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
-
- -- SST UDP offload bsn monitor
- reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
-
- -- XST ring lane info
- reg_ring_lane_info_xst_copi : out t_mem_copi;
- reg_ring_lane_info_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
-
- -- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
-
- -- XST ring validate err
- reg_dp_block_validate_err_xst_copi : out t_mem_copi;
- reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
-
- -- XST ring MAC
- reg_tr_10GbE_mac_copi : out t_mem_copi;
- reg_tr_10GbE_mac_cipo : in t_mem_cipo;
-
- -- XST ring ETH
- reg_tr_10GbE_eth10g_copi : out t_mem_copi;
- reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- Scrap ram
- ram_scrap_copi : out t_mem_copi;
- ram_scrap_cipo : in t_mem_cipo;
-
- -- Jesd reset control
- jesd_ctrl_copi : out t_mem_copi;
- jesd_ctrl_cipo : in t_mem_cipo
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
+
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_copi : out t_mem_copi;
+ reg_bf_scale_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_copi : out t_mem_copi;
+ reg_hdr_dat_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_copi : out t_mem_copi;
+ reg_dp_xonoff_cipo : in t_mem_cipo;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : out t_mem_copi;
+ reg_ring_lane_info_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics (BST)
+ ram_st_bst_copi : out t_mem_copi;
+ ram_st_bst_cipo : in t_mem_cipo;
+
+ -- Subband Statistics offload
+ reg_stat_enable_sst_copi : out t_mem_copi;
+ reg_stat_enable_sst_cipo : in t_mem_cipo;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics offload
+ reg_stat_enable_xst_copi : out t_mem_copi;
+ reg_stat_enable_xst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics header info
+ reg_stat_hdr_dat_xst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics offload
+ reg_stat_enable_bst_copi : out t_mem_copi;
+ reg_stat_enable_bst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics header info
+ reg_stat_hdr_dat_bst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_crosslets_info_copi : out t_mem_copi;
+ reg_crosslets_info_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_nof_crosslets_copi : out t_mem_copi;
+ reg_nof_crosslets_cipo : in t_mem_cipo;
+
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
+
+ -- st_xsq (XST)
+ ram_st_xsq_copi : out t_mem_copi;
+ ram_st_xsq_cipo : in t_mem_cipo;
+
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_copi : out t_mem_copi;
+ reg_nw_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_copi : out t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2
+ reg_bsn_align_v2_xsub_copi : out t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
+
+ -- XST UDP offload bsn monitor
+ reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
+
+ -- Beamlet output bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
+
+ -- XST ring lane info
+ reg_ring_lane_info_xst_copi : out t_mem_copi;
+ reg_ring_lane_info_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
+
+ -- XST ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
+
+ -- XST ring validate err
+ reg_dp_block_validate_err_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
+
+ -- XST ring MAC
+ reg_tr_10GbE_mac_copi : out t_mem_copi;
+ reg_tr_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- XST ring ETH
+ reg_tr_10GbE_eth10g_copi : out t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- Scrap ram
+ ram_scrap_copi : out t_mem_copi;
+ ram_scrap_cipo : in t_mem_cipo;
+
+ -- Jesd reset control
+ jesd_ctrl_copi : out t_mem_copi;
+ jesd_ctrl_cipo : in t_mem_cipo
);
end mmm_lofar2_unb2c_sdp_station;
@@ -343,207 +343,207 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
-- Must use exact g_mm_rd_latency = 1 instead of default 2, because JESD204B IP forces rddata = 0 after it has been read
u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
- port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+ port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
u_mm_file_pio_jesd_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
- port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+ port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+ port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
+ port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
+ port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
u_mm_file_ram_st_histogram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
+ port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
+ port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
+ port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
+ port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
+ port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
+ port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
u_mm_file_ram_equalizer_gains_cross : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
+ port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
+ port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
+ port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
+ port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
+ port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
+ port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
+ port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
u_mm_file_reg_stat_enable_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
+ port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
u_mm_file_reg_stat_hdr_info_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
u_mm_file_reg_stat_enable_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
+ port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
u_mm_file_reg_stat_hdr_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
u_mm_file_reg_stat_enable_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
+ port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
u_mm_file_reg_stat_hdr_info_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
u_mm_file_reg_crosslets_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
+ port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
u_mm_file_reg_nof_crosslets : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
+ port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
+ port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
u_mm_file_ram_st_xsq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
+ port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
u_mm_file_reg_bsn_align_v2_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
u_mm_file_reg_ring_lane_info_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
- port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
+ port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
u_mm_file_reg_dp_block_validate_err_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
u_mm_file_reg_bsn_align_v2_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
u_mm_file_reg_ring_lane_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
+ port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
u_mm_file_reg_dp_block_validate_err_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -558,620 +558,620 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_lofar2_unb2c_sdp_station
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
- rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_copi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_copi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_copi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_copi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_copi.wr,
- pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_copi.rd,
- pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_copi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_copi.wr,
- reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_copi.rd,
- reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_copi.wr,
- reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_copi.rd,
- reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w - 1 downto 0),
-
- jesd204b_reset_export => OPEN,
- jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_copi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
- jesd204b_write_export => jesd204b_copi.wr,
- jesd204b_writedata_export => jesd204b_copi.wrdata(c_word_w - 1 downto 0),
- jesd204b_read_export => jesd204b_copi.rd,
- jesd204b_readdata_export => jesd204b_cipo.rddata(c_word_w - 1 downto 0),
-
- pio_jesd_ctrl_reset_export => OPEN,
- pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_copi.address(c_sdp_jesd_ctrl_addr_w - 1 downto 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_copi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_copi.wrdata(c_word_w - 1 downto 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_copi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_copi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
- reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_copi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_copi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_copi.wrdata(c_word_w - 1 downto 0),
-
- -- waveform generators (multiplexed)
- reg_wg_clk_export => OPEN,
- reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_copi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
- reg_wg_read_export => reg_wg_copi.rd,
- reg_wg_readdata_export => reg_wg_cipo.rddata(c_word_w - 1 downto 0),
- reg_wg_write_export => reg_wg_copi.wr,
- reg_wg_writedata_export => reg_wg_copi.wrdata(c_word_w - 1 downto 0),
-
- ram_wg_clk_export => OPEN,
- ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_copi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
- ram_wg_read_export => ram_wg_copi.rd,
- ram_wg_readdata_export => ram_wg_cipo.rddata(c_word_w - 1 downto 0),
- ram_wg_write_export => ram_wg_copi.wr,
- ram_wg_writedata_export => ram_wg_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_dp_shiftram_clk_export => OPEN,
- reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_copi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_copi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_cipo.rddata(c_word_w - 1 downto 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_copi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_source_v2_clk_export => OPEN,
- reg_bsn_source_v2_reset_export => OPEN,
- reg_bsn_source_v2_address_export => reg_bsn_source_v2_copi.address(c_sdp_reg_bsn_source_v2_addr_w - 1 downto 0),
- reg_bsn_source_v2_read_export => reg_bsn_source_v2_copi.rd,
- reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_source_v2_write_export => reg_bsn_source_v2_copi.wr,
- reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_scheduler_clk_export => OPEN,
- reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_copi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_copi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_cipo.rddata(c_word_w - 1 downto 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_copi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_copi.wr,
- reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_copi.rd,
- reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_bsn_clk_export => OPEN,
- ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_copi.address(c_sdp_ram_diag_data_buf_bsn_addr_w - 1 downto 0),
- ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_copi.wr,
- ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_copi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_copi.rd,
- ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_bsn_reset_export => OPEN,
- reg_diag_data_buffer_bsn_clk_export => OPEN,
- reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_copi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
- reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_copi.wr,
- reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_copi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_copi.rd,
- reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_st_histogram_clk_export => OPEN,
- ram_st_histogram_reset_export => OPEN,
- ram_st_histogram_address_export => ram_st_histogram_copi.address(c_sdp_ram_st_histogram_addr_w - 1 downto 0),
- ram_st_histogram_write_export => ram_st_histogram_copi.wr,
- ram_st_histogram_writedata_export => ram_st_histogram_copi.wrdata(c_word_w - 1 downto 0),
- ram_st_histogram_read_export => ram_st_histogram_copi.rd,
- ram_st_histogram_readdata_export => ram_st_histogram_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_aduh_monitor_reset_export => OPEN,
- reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_copi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_copi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_copi.wrdata(c_word_w - 1 downto 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_copi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_fil_coefs_clk_export => OPEN,
- ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_copi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
- ram_fil_coefs_write_export => ram_fil_coefs_copi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_copi.wrdata(c_word_w - 1 downto 0),
- ram_fil_coefs_read_export => ram_fil_coefs_copi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_st_sst_clk_export => OPEN,
- ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_copi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
- ram_st_sst_write_export => ram_st_sst_copi.wr,
- ram_st_sst_writedata_export => ram_st_sst_copi.wrdata(c_word_w - 1 downto 0),
- ram_st_sst_read_export => ram_st_sst_copi.rd,
- ram_st_sst_readdata_export => ram_st_sst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_si_clk_export => OPEN,
- reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_copi.address(c_sdp_reg_si_addr_w - 1 downto 0),
- reg_si_write_export => reg_si_copi.wr,
- reg_si_writedata_export => reg_si_copi.wrdata(c_word_w - 1 downto 0),
- reg_si_read_export => reg_si_copi.rd,
- reg_si_readdata_export => reg_si_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_equalizer_gains_clk_export => OPEN,
- ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_copi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_copi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_copi.wrdata(c_word_w - 1 downto 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_equalizer_gains_cross_clk_export => OPEN,
- ram_equalizer_gains_cross_reset_export => OPEN,
- ram_equalizer_gains_cross_address_export => ram_equalizer_gains_cross_copi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
- ram_equalizer_gains_cross_write_export => ram_equalizer_gains_cross_copi.wr,
- ram_equalizer_gains_cross_writedata_export => ram_equalizer_gains_cross_copi.wrdata(c_word_w - 1 downto 0),
- ram_equalizer_gains_cross_read_export => ram_equalizer_gains_cross_copi.rd,
- ram_equalizer_gains_cross_readdata_export => ram_equalizer_gains_cross_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_selector_clk_export => OPEN,
- reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
- reg_dp_selector_write_export => reg_dp_selector_copi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_selector_read_export => reg_dp_selector_copi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_sdp_info_clk_export => OPEN,
- reg_sdp_info_reset_export => OPEN,
- reg_sdp_info_address_export => reg_sdp_info_copi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
- reg_sdp_info_write_export => reg_sdp_info_copi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_sdp_info_read_export => reg_sdp_info_copi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_ring_info_clk_export => OPEN,
- reg_ring_info_reset_export => OPEN,
- reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w - 1 downto 0),
- reg_ring_info_write_export => reg_ring_info_copi.wr,
- reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_info_read_export => reg_ring_info_copi.rd,
- reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_ss_ss_wide_clk_export => OPEN,
- ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_address_export => ram_ss_ss_wide_copi.address(c_sdp_ram_ss_ss_wide_addr_w - 1 downto 0),
- ram_ss_ss_wide_write_export => ram_ss_ss_wide_copi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_copi.wrdata(c_word_w - 1 downto 0),
- ram_ss_ss_wide_read_export => ram_ss_ss_wide_copi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_bf_weights_clk_export => OPEN,
- ram_bf_weights_reset_export => OPEN,
- ram_bf_weights_address_export => ram_bf_weights_copi.address(c_sdp_ram_bf_weights_addr_w - 1 downto 0),
- ram_bf_weights_write_export => ram_bf_weights_copi.wr,
- ram_bf_weights_writedata_export => ram_bf_weights_copi.wrdata(c_word_w - 1 downto 0),
- ram_bf_weights_read_export => ram_bf_weights_copi.rd,
- ram_bf_weights_readdata_export => ram_bf_weights_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bf_scale_clk_export => OPEN,
- reg_bf_scale_reset_export => OPEN,
- reg_bf_scale_address_export => reg_bf_scale_copi.address(c_sdp_reg_bf_scale_addr_w - 1 downto 0),
- reg_bf_scale_write_export => reg_bf_scale_copi.wr,
- reg_bf_scale_writedata_export => reg_bf_scale_copi.wrdata(c_word_w - 1 downto 0),
- reg_bf_scale_read_export => reg_bf_scale_copi.rd,
- reg_bf_scale_readdata_export => reg_bf_scale_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_hdr_dat_clk_export => OPEN,
- reg_hdr_dat_reset_export => OPEN,
- reg_hdr_dat_address_export => reg_hdr_dat_copi.address(c_sdp_reg_bf_hdr_dat_addr_w - 1 downto 0),
- reg_hdr_dat_write_export => reg_hdr_dat_copi.wr,
- reg_hdr_dat_writedata_export => reg_hdr_dat_copi.wrdata(c_word_w - 1 downto 0),
- reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
- reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_clk_export => OPEN,
- reg_dp_xonoff_reset_export => OPEN,
- reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w - 1 downto 0),
- reg_dp_xonoff_write_export => reg_dp_xonoff_copi.wr,
- reg_dp_xonoff_writedata_export => reg_dp_xonoff_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_xonoff_read_export => reg_dp_xonoff_copi.rd,
- reg_dp_xonoff_readdata_export => reg_dp_xonoff_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_st_bst_clk_export => OPEN,
- ram_st_bst_reset_export => OPEN,
- ram_st_bst_address_export => ram_st_bst_copi.address(c_sdp_ram_st_bst_addr_w - 1 downto 0),
- ram_st_bst_write_export => ram_st_bst_copi.wr,
- ram_st_bst_writedata_export => ram_st_bst_copi.wrdata(c_word_w - 1 downto 0),
- ram_st_bst_read_export => ram_st_bst_copi.rd,
- ram_st_bst_readdata_export => ram_st_bst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_enable_sst_clk_export => OPEN,
- reg_stat_enable_sst_reset_export => OPEN,
- reg_stat_enable_sst_address_export => reg_stat_enable_sst_copi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
- reg_stat_enable_sst_write_export => reg_stat_enable_sst_copi.wr,
- reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_enable_sst_read_export => reg_stat_enable_sst_copi.rd,
- reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_hdr_dat_sst_clk_export => OPEN,
- reg_stat_hdr_dat_sst_reset_export => OPEN,
- reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
- reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_copi.wr,
- reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_copi.rd,
- reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_enable_xst_clk_export => OPEN,
- reg_stat_enable_xst_reset_export => OPEN,
- reg_stat_enable_xst_address_export => reg_stat_enable_xst_copi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
- reg_stat_enable_xst_write_export => reg_stat_enable_xst_copi.wr,
- reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_enable_xst_read_export => reg_stat_enable_xst_copi.rd,
- reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_hdr_dat_xst_clk_export => OPEN,
- reg_stat_hdr_dat_xst_reset_export => OPEN,
- reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
- reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_copi.wr,
- reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_copi.rd,
- reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_enable_bst_clk_export => OPEN,
- reg_stat_enable_bst_reset_export => OPEN,
- reg_stat_enable_bst_address_export => reg_stat_enable_bst_copi.address(c_sdp_reg_stat_enable_bst_addr_w - 1 downto 0),
- reg_stat_enable_bst_write_export => reg_stat_enable_bst_copi.wr,
- reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_enable_bst_read_export => reg_stat_enable_bst_copi.rd,
- reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_stat_hdr_dat_bst_clk_export => OPEN,
- reg_stat_hdr_dat_bst_reset_export => OPEN,
- reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_copi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w - 1 downto 0),
- reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_copi.wr,
- reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_copi.wrdata(c_word_w - 1 downto 0),
- reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_copi.rd,
- reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_crosslets_info_clk_export => OPEN,
- reg_crosslets_info_reset_export => OPEN,
- reg_crosslets_info_address_export => reg_crosslets_info_copi.address(c_sdp_reg_crosslets_info_addr_w - 1 downto 0),
- reg_crosslets_info_write_export => reg_crosslets_info_copi.wr,
- reg_crosslets_info_writedata_export => reg_crosslets_info_copi.wrdata(c_word_w - 1 downto 0),
- reg_crosslets_info_read_export => reg_crosslets_info_copi.rd,
- reg_crosslets_info_readdata_export => reg_crosslets_info_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_nof_crosslets_clk_export => OPEN,
- reg_nof_crosslets_reset_export => OPEN,
- reg_nof_crosslets_address_export => reg_nof_crosslets_copi.address(c_sdp_reg_nof_crosslets_addr_w - 1 downto 0),
- reg_nof_crosslets_write_export => reg_nof_crosslets_copi.wr,
- reg_nof_crosslets_writedata_export => reg_nof_crosslets_copi.wrdata(c_word_w - 1 downto 0),
- reg_nof_crosslets_read_export => reg_nof_crosslets_copi.rd,
- reg_nof_crosslets_readdata_export => reg_nof_crosslets_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
- reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
- reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_copi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w - 1 downto 0),
- reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_copi.wr,
- reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_copi.rd,
- reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_st_xsq_clk_export => OPEN,
- ram_st_xsq_reset_export => OPEN,
- ram_st_xsq_address_export => ram_st_xsq_copi.address(c_sdp_ram_st_xsq_arr_addr_w - 1 downto 0),
- ram_st_xsq_write_export => ram_st_xsq_copi.wr,
- ram_st_xsq_writedata_export => ram_st_xsq_copi.wrdata(c_word_w - 1 downto 0),
- ram_st_xsq_read_export => ram_st_xsq_copi.rd,
- ram_st_xsq_readdata_export => ram_st_xsq_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_nw_10GbE_mac_clk_export => OPEN,
- reg_nw_10GbE_mac_reset_export => OPEN,
- reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_copi.address(c_sdp_reg_nw_10GbE_mac_addr_w - 1 downto 0),
- reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_copi.wr,
- reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
- reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_copi.rd,
- reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_nw_10GbE_eth10g_clk_export => OPEN,
- reg_nw_10GbE_eth10g_reset_export => OPEN,
- reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_copi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w - 1 downto 0),
- reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_copi.wr,
- reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
- reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
- reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_align_v2_bf_clk_export => OPEN,
- reg_bsn_align_v2_bf_reset_export => OPEN,
- reg_bsn_align_v2_bf_address_export => reg_bsn_align_v2_bf_copi.address(c_sdp_reg_bsn_align_v2_bf_addr_w - 1 downto 0),
- reg_bsn_align_v2_bf_write_export => reg_bsn_align_v2_bf_copi.wr,
- reg_bsn_align_v2_bf_writedata_export => reg_bsn_align_v2_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_align_v2_bf_read_export => reg_bsn_align_v2_bf_copi.rd,
- reg_bsn_align_v2_bf_readdata_export => reg_bsn_align_v2_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_rx_align_bf_clk_export => OPEN,
- reg_bsn_monitor_v2_rx_align_bf_reset_export => OPEN,
- reg_bsn_monitor_v2_rx_align_bf_address_export => reg_bsn_monitor_v2_rx_align_bf_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_align_bf_write_export => reg_bsn_monitor_v2_rx_align_bf_copi.wr,
- reg_bsn_monitor_v2_rx_align_bf_writedata_export => reg_bsn_monitor_v2_rx_align_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_align_bf_read_export => reg_bsn_monitor_v2_rx_align_bf_copi.rd,
- reg_bsn_monitor_v2_rx_align_bf_readdata_export => reg_bsn_monitor_v2_rx_align_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_aligned_bf_clk_export => OPEN,
- reg_bsn_monitor_v2_aligned_bf_reset_export => OPEN,
- reg_bsn_monitor_v2_aligned_bf_address_export => reg_bsn_monitor_v2_aligned_bf_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_aligned_bf_write_export => reg_bsn_monitor_v2_aligned_bf_copi.wr,
- reg_bsn_monitor_v2_aligned_bf_writedata_export => reg_bsn_monitor_v2_aligned_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_aligned_bf_read_export => reg_bsn_monitor_v2_aligned_bf_copi.rd,
- reg_bsn_monitor_v2_aligned_bf_readdata_export => reg_bsn_monitor_v2_aligned_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_align_v2_xsub_clk_export => OPEN,
- reg_bsn_align_v2_xsub_reset_export => OPEN,
- reg_bsn_align_v2_xsub_address_export => reg_bsn_align_v2_xsub_copi.address(c_sdp_reg_bsn_align_v2_xsub_addr_w - 1 downto 0),
- reg_bsn_align_v2_xsub_write_export => reg_bsn_align_v2_xsub_copi.wr,
- reg_bsn_align_v2_xsub_writedata_export => reg_bsn_align_v2_xsub_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_align_v2_xsub_read_export => reg_bsn_align_v2_xsub_copi.rd,
- reg_bsn_align_v2_xsub_readdata_export => reg_bsn_align_v2_xsub_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_rx_align_xsub_clk_export => OPEN,
- reg_bsn_monitor_v2_rx_align_xsub_reset_export => OPEN,
- reg_bsn_monitor_v2_rx_align_xsub_address_export => reg_bsn_monitor_v2_rx_align_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_align_xsub_write_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wr,
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_align_xsub_read_export => reg_bsn_monitor_v2_rx_align_xsub_copi.rd,
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export => reg_bsn_monitor_v2_rx_align_xsub_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_aligned_xsub_clk_export => OPEN,
- reg_bsn_monitor_v2_aligned_xsub_reset_export => OPEN,
- reg_bsn_monitor_v2_aligned_xsub_address_export => reg_bsn_monitor_v2_aligned_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_aligned_xsub_write_export => reg_bsn_monitor_v2_aligned_xsub_copi.wr,
- reg_bsn_monitor_v2_aligned_xsub_writedata_export => reg_bsn_monitor_v2_aligned_xsub_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_aligned_xsub_read_export => reg_bsn_monitor_v2_aligned_xsub_copi.rd,
- reg_bsn_monitor_v2_aligned_xsub_readdata_export => reg_bsn_monitor_v2_aligned_xsub_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
- reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
- reg_bsn_monitor_v2_sst_offload_address_export => reg_bsn_monitor_v2_sst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_sst_offload_write_export => reg_bsn_monitor_v2_sst_offload_copi.wr,
- reg_bsn_monitor_v2_sst_offload_writedata_export => reg_bsn_monitor_v2_sst_offload_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_sst_offload_read_export => reg_bsn_monitor_v2_sst_offload_copi.rd,
- reg_bsn_monitor_v2_sst_offload_readdata_export => reg_bsn_monitor_v2_sst_offload_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_bst_offload_clk_export => OPEN,
- reg_bsn_monitor_v2_bst_offload_reset_export => OPEN,
- reg_bsn_monitor_v2_bst_offload_address_export => reg_bsn_monitor_v2_bst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_bst_offload_write_export => reg_bsn_monitor_v2_bst_offload_copi.wr,
- reg_bsn_monitor_v2_bst_offload_writedata_export => reg_bsn_monitor_v2_bst_offload_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_bst_offload_read_export => reg_bsn_monitor_v2_bst_offload_copi.rd,
- reg_bsn_monitor_v2_bst_offload_readdata_export => reg_bsn_monitor_v2_bst_offload_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_beamlet_output_clk_export => OPEN,
- reg_bsn_monitor_v2_beamlet_output_reset_export => OPEN,
- reg_bsn_monitor_v2_beamlet_output_address_export => reg_bsn_monitor_v2_beamlet_output_copi.address(c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_beamlet_output_write_export => reg_bsn_monitor_v2_beamlet_output_copi.wr,
- reg_bsn_monitor_v2_beamlet_output_writedata_export => reg_bsn_monitor_v2_beamlet_output_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_beamlet_output_read_export => reg_bsn_monitor_v2_beamlet_output_copi.rd,
- reg_bsn_monitor_v2_beamlet_output_readdata_export => reg_bsn_monitor_v2_beamlet_output_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_xst_offload_clk_export => OPEN,
- reg_bsn_monitor_v2_xst_offload_reset_export => OPEN,
- reg_bsn_monitor_v2_xst_offload_address_export => reg_bsn_monitor_v2_xst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_xst_offload_write_export => reg_bsn_monitor_v2_xst_offload_copi.wr,
- reg_bsn_monitor_v2_xst_offload_writedata_export => reg_bsn_monitor_v2_xst_offload_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_xst_offload_read_export => reg_bsn_monitor_v2_xst_offload_copi.rd,
- reg_bsn_monitor_v2_xst_offload_readdata_export => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_ring_lane_info_bf_clk_export => OPEN,
- reg_ring_lane_info_bf_reset_export => OPEN,
- reg_ring_lane_info_bf_address_export => reg_ring_lane_info_bf_copi.address(c_sdp_reg_ring_lane_info_bf_addr_w - 1 downto 0),
- reg_ring_lane_info_bf_write_export => reg_ring_lane_info_bf_copi.wr,
- reg_ring_lane_info_bf_writedata_export => reg_ring_lane_info_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_lane_info_bf_read_export => reg_ring_lane_info_bf_copi.rd,
- reg_ring_lane_info_bf_readdata_export => reg_ring_lane_info_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_rx_bf_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_bf_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_bf_address_export => reg_bsn_monitor_v2_ring_rx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_bf_write_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wr,
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_bf_read_export => reg_bsn_monitor_v2_ring_rx_bf_copi.rd,
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export => reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_tx_bf_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_bf_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_bf_address_export => reg_bsn_monitor_v2_ring_tx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_bf_write_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wr,
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_bf_read_export => reg_bsn_monitor_v2_ring_tx_bf_copi.rd,
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export => reg_bsn_monitor_v2_ring_tx_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_err_bf_clk_export => OPEN,
- reg_dp_block_validate_err_bf_reset_export => OPEN,
- reg_dp_block_validate_err_bf_address_export => reg_dp_block_validate_err_bf_copi.address(c_sdp_reg_dp_block_validate_err_bf_addr_w - 1 downto 0),
- reg_dp_block_validate_err_bf_write_export => reg_dp_block_validate_err_bf_copi.wr,
- reg_dp_block_validate_err_bf_writedata_export => reg_dp_block_validate_err_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_err_bf_read_export => reg_dp_block_validate_err_bf_copi.rd,
- reg_dp_block_validate_err_bf_readdata_export => reg_dp_block_validate_err_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_bsn_at_sync_bf_clk_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_bf_reset_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_bf_address_export => reg_dp_block_validate_bsn_at_sync_bf_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_bf_write_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wr,
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_bf_read_export => reg_dp_block_validate_bsn_at_sync_bf_copi.rd,
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export => reg_dp_block_validate_bsn_at_sync_bf_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_ring_lane_info_xst_clk_export => OPEN,
- reg_ring_lane_info_xst_reset_export => OPEN,
- reg_ring_lane_info_xst_address_export => reg_ring_lane_info_xst_copi.address(c_sdp_reg_ring_lane_info_xst_addr_w - 1 downto 0),
- reg_ring_lane_info_xst_write_export => reg_ring_lane_info_xst_copi.wr,
- reg_ring_lane_info_xst_writedata_export => reg_ring_lane_info_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_ring_lane_info_xst_read_export => reg_ring_lane_info_xst_copi.rd,
- reg_ring_lane_info_xst_readdata_export => reg_ring_lane_info_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_rx_xst_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_xst_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_rx_xst_address_export => reg_bsn_monitor_v2_ring_rx_xst_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_xst_write_export => reg_bsn_monitor_v2_ring_rx_xst_copi.wr,
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export => reg_bsn_monitor_v2_ring_rx_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_rx_xst_read_export => reg_bsn_monitor_v2_ring_rx_xst_copi.rd,
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export => reg_bsn_monitor_v2_ring_rx_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_ring_tx_xst_clk_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_xst_reset_export => OPEN,
- reg_bsn_monitor_v2_ring_tx_xst_address_export => reg_bsn_monitor_v2_ring_tx_xst_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_xst_write_export => reg_bsn_monitor_v2_ring_tx_xst_copi.wr,
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export => reg_bsn_monitor_v2_ring_tx_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_ring_tx_xst_read_export => reg_bsn_monitor_v2_ring_tx_xst_copi.rd,
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export => reg_bsn_monitor_v2_ring_tx_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_err_xst_clk_export => OPEN,
- reg_dp_block_validate_err_xst_reset_export => OPEN,
- reg_dp_block_validate_err_xst_address_export => reg_dp_block_validate_err_xst_copi.address(c_sdp_reg_dp_block_validate_err_xst_addr_w - 1 downto 0),
- reg_dp_block_validate_err_xst_write_export => reg_dp_block_validate_err_xst_copi.wr,
- reg_dp_block_validate_err_xst_writedata_export => reg_dp_block_validate_err_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_err_xst_read_export => reg_dp_block_validate_err_xst_copi.rd,
- reg_dp_block_validate_err_xst_readdata_export => reg_dp_block_validate_err_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_dp_block_validate_bsn_at_sync_xst_clk_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_xst_reset_export => OPEN,
- reg_dp_block_validate_bsn_at_sync_xst_address_export => reg_dp_block_validate_bsn_at_sync_xst_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_xst_write_export => reg_dp_block_validate_bsn_at_sync_xst_copi.wr,
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export => reg_dp_block_validate_bsn_at_sync_xst_copi.wrdata(c_word_w - 1 downto 0),
- reg_dp_block_validate_bsn_at_sync_xst_read_export => reg_dp_block_validate_bsn_at_sync_xst_copi.rd,
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export => reg_dp_block_validate_bsn_at_sync_xst_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_tr_10GbE_mac_clk_export => OPEN,
- reg_tr_10GbE_mac_reset_export => OPEN,
- reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w - 1 downto 0),
- reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr,
- reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd,
- reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_tr_10GbE_eth10g_clk_export => OPEN,
- reg_tr_10GbE_eth10g_reset_export => OPEN,
- reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w - 1 downto 0),
- reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr,
- reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd,
- reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
-
- ram_scrap_clk_export => OPEN,
- ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_copi.address(9 - 1 downto 0),
- ram_scrap_write_export => ram_scrap_copi.wr,
- ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_copi.rd,
- ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ -- ToDo: This has changed in the peripherals package
+ -- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_copi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_copi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_copi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_copi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_copi.wr,
+ pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_copi.rd,
+ pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_copi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_copi.wr,
+ reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_copi.rd,
+ reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_copi.wr,
+ reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_copi.rd,
+ reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w - 1 downto 0),
+
+ jesd204b_reset_export => OPEN,
+ jesd204b_clk_export => OPEN,
+ jesd204b_address_export => jesd204b_copi.address(c_sdp_jesd204b_addr_w - 1 downto 0),
+ jesd204b_write_export => jesd204b_copi.wr,
+ jesd204b_writedata_export => jesd204b_copi.wrdata(c_word_w - 1 downto 0),
+ jesd204b_read_export => jesd204b_copi.rd,
+ jesd204b_readdata_export => jesd204b_cipo.rddata(c_word_w - 1 downto 0),
+
+ pio_jesd_ctrl_reset_export => OPEN,
+ pio_jesd_ctrl_clk_export => OPEN,
+ pio_jesd_ctrl_address_export => jesd_ctrl_copi.address(c_sdp_jesd_ctrl_addr_w - 1 downto 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_copi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_copi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_copi.address(c_sdp_reg_bsn_monitor_input_addr_w - 1 downto 0),
+ reg_bsn_monitor_input_clk_export => OPEN,
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_copi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_input_reset_export => OPEN,
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_copi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_copi.wrdata(c_word_w - 1 downto 0),
+
+ -- waveform generators (multiplexed)
+ reg_wg_clk_export => OPEN,
+ reg_wg_reset_export => OPEN,
+ reg_wg_address_export => reg_wg_copi.address(c_sdp_reg_wg_addr_w - 1 downto 0),
+ reg_wg_read_export => reg_wg_copi.rd,
+ reg_wg_readdata_export => reg_wg_cipo.rddata(c_word_w - 1 downto 0),
+ reg_wg_write_export => reg_wg_copi.wr,
+ reg_wg_writedata_export => reg_wg_copi.wrdata(c_word_w - 1 downto 0),
+
+ ram_wg_clk_export => OPEN,
+ ram_wg_reset_export => OPEN,
+ ram_wg_address_export => ram_wg_copi.address(c_sdp_ram_wg_addr_w - 1 downto 0),
+ ram_wg_read_export => ram_wg_copi.rd,
+ ram_wg_readdata_export => ram_wg_cipo.rddata(c_word_w - 1 downto 0),
+ ram_wg_write_export => ram_wg_copi.wr,
+ ram_wg_writedata_export => ram_wg_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_dp_shiftram_clk_export => OPEN,
+ reg_dp_shiftram_reset_export => OPEN,
+ reg_dp_shiftram_address_export => reg_dp_shiftram_copi.address(c_sdp_reg_dp_shiftram_addr_w - 1 downto 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_copi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_cipo.rddata(c_word_w - 1 downto 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_copi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_source_v2_clk_export => OPEN,
+ reg_bsn_source_v2_reset_export => OPEN,
+ reg_bsn_source_v2_address_export => reg_bsn_source_v2_copi.address(c_sdp_reg_bsn_source_v2_addr_w - 1 downto 0),
+ reg_bsn_source_v2_read_export => reg_bsn_source_v2_copi.rd,
+ reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_source_v2_write_export => reg_bsn_source_v2_copi.wr,
+ reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_scheduler_clk_export => OPEN,
+ reg_bsn_scheduler_reset_export => OPEN,
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_copi.address(c_sdp_reg_bsn_scheduler_addr_w - 1 downto 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_copi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_copi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_copi.wr,
+ reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_copi.rd,
+ reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_bsn_clk_export => OPEN,
+ ram_diag_data_buffer_bsn_reset_export => OPEN,
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_copi.address(c_sdp_ram_diag_data_buf_bsn_addr_w - 1 downto 0),
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_copi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_copi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_copi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_bsn_reset_export => OPEN,
+ reg_diag_data_buffer_bsn_clk_export => OPEN,
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_copi.address(c_sdp_reg_diag_data_buf_bsn_addr_w - 1 downto 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_copi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_copi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_copi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_st_histogram_clk_export => OPEN,
+ ram_st_histogram_reset_export => OPEN,
+ ram_st_histogram_address_export => ram_st_histogram_copi.address(c_sdp_ram_st_histogram_addr_w - 1 downto 0),
+ ram_st_histogram_write_export => ram_st_histogram_copi.wr,
+ ram_st_histogram_writedata_export => ram_st_histogram_copi.wrdata(c_word_w - 1 downto 0),
+ ram_st_histogram_read_export => ram_st_histogram_copi.rd,
+ ram_st_histogram_readdata_export => ram_st_histogram_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_aduh_monitor_reset_export => OPEN,
+ reg_aduh_monitor_clk_export => OPEN,
+ reg_aduh_monitor_address_export => reg_aduh_monitor_copi.address(c_sdp_reg_aduh_monitor_addr_w - 1 downto 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_copi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_copi.wrdata(c_word_w - 1 downto 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_copi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_fil_coefs_clk_export => OPEN,
+ ram_fil_coefs_reset_export => OPEN,
+ ram_fil_coefs_address_export => ram_fil_coefs_copi.address(c_sdp_ram_fil_coefs_addr_w - 1 downto 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_copi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_copi.wrdata(c_word_w - 1 downto 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_copi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_st_sst_clk_export => OPEN,
+ ram_st_sst_reset_export => OPEN,
+ ram_st_sst_address_export => ram_st_sst_copi.address(c_sdp_ram_st_sst_addr_w - 1 downto 0),
+ ram_st_sst_write_export => ram_st_sst_copi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_copi.wrdata(c_word_w - 1 downto 0),
+ ram_st_sst_read_export => ram_st_sst_copi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_si_clk_export => OPEN,
+ reg_si_reset_export => OPEN,
+ reg_si_address_export => reg_si_copi.address(c_sdp_reg_si_addr_w - 1 downto 0),
+ reg_si_write_export => reg_si_copi.wr,
+ reg_si_writedata_export => reg_si_copi.wrdata(c_word_w - 1 downto 0),
+ reg_si_read_export => reg_si_copi.rd,
+ reg_si_readdata_export => reg_si_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_equalizer_gains_clk_export => OPEN,
+ ram_equalizer_gains_reset_export => OPEN,
+ ram_equalizer_gains_address_export => ram_equalizer_gains_copi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_copi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_copi.wrdata(c_word_w - 1 downto 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_equalizer_gains_cross_clk_export => OPEN,
+ ram_equalizer_gains_cross_reset_export => OPEN,
+ ram_equalizer_gains_cross_address_export => ram_equalizer_gains_cross_copi.address(c_sdp_ram_equalizer_gains_addr_w - 1 downto 0),
+ ram_equalizer_gains_cross_write_export => ram_equalizer_gains_cross_copi.wr,
+ ram_equalizer_gains_cross_writedata_export => ram_equalizer_gains_cross_copi.wrdata(c_word_w - 1 downto 0),
+ ram_equalizer_gains_cross_read_export => ram_equalizer_gains_cross_copi.rd,
+ ram_equalizer_gains_cross_readdata_export => ram_equalizer_gains_cross_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_selector_clk_export => OPEN,
+ reg_dp_selector_reset_export => OPEN,
+ reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w - 1 downto 0),
+ reg_dp_selector_write_export => reg_dp_selector_copi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_selector_read_export => reg_dp_selector_copi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_sdp_info_clk_export => OPEN,
+ reg_sdp_info_reset_export => OPEN,
+ reg_sdp_info_address_export => reg_sdp_info_copi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
+ reg_sdp_info_write_export => reg_sdp_info_copi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_sdp_info_read_export => reg_sdp_info_copi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_ring_info_clk_export => OPEN,
+ reg_ring_info_reset_export => OPEN,
+ reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w - 1 downto 0),
+ reg_ring_info_write_export => reg_ring_info_copi.wr,
+ reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_info_read_export => reg_ring_info_copi.rd,
+ reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_ss_ss_wide_clk_export => OPEN,
+ ram_ss_ss_wide_reset_export => OPEN,
+ ram_ss_ss_wide_address_export => ram_ss_ss_wide_copi.address(c_sdp_ram_ss_ss_wide_addr_w - 1 downto 0),
+ ram_ss_ss_wide_write_export => ram_ss_ss_wide_copi.wr,
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_copi.wrdata(c_word_w - 1 downto 0),
+ ram_ss_ss_wide_read_export => ram_ss_ss_wide_copi.rd,
+ ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_bf_weights_clk_export => OPEN,
+ ram_bf_weights_reset_export => OPEN,
+ ram_bf_weights_address_export => ram_bf_weights_copi.address(c_sdp_ram_bf_weights_addr_w - 1 downto 0),
+ ram_bf_weights_write_export => ram_bf_weights_copi.wr,
+ ram_bf_weights_writedata_export => ram_bf_weights_copi.wrdata(c_word_w - 1 downto 0),
+ ram_bf_weights_read_export => ram_bf_weights_copi.rd,
+ ram_bf_weights_readdata_export => ram_bf_weights_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bf_scale_clk_export => OPEN,
+ reg_bf_scale_reset_export => OPEN,
+ reg_bf_scale_address_export => reg_bf_scale_copi.address(c_sdp_reg_bf_scale_addr_w - 1 downto 0),
+ reg_bf_scale_write_export => reg_bf_scale_copi.wr,
+ reg_bf_scale_writedata_export => reg_bf_scale_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bf_scale_read_export => reg_bf_scale_copi.rd,
+ reg_bf_scale_readdata_export => reg_bf_scale_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_hdr_dat_clk_export => OPEN,
+ reg_hdr_dat_reset_export => OPEN,
+ reg_hdr_dat_address_export => reg_hdr_dat_copi.address(c_sdp_reg_bf_hdr_dat_addr_w - 1 downto 0),
+ reg_hdr_dat_write_export => reg_hdr_dat_copi.wr,
+ reg_hdr_dat_writedata_export => reg_hdr_dat_copi.wrdata(c_word_w - 1 downto 0),
+ reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
+ reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_clk_export => OPEN,
+ reg_dp_xonoff_reset_export => OPEN,
+ reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w - 1 downto 0),
+ reg_dp_xonoff_write_export => reg_dp_xonoff_copi.wr,
+ reg_dp_xonoff_writedata_export => reg_dp_xonoff_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_read_export => reg_dp_xonoff_copi.rd,
+ reg_dp_xonoff_readdata_export => reg_dp_xonoff_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_st_bst_clk_export => OPEN,
+ ram_st_bst_reset_export => OPEN,
+ ram_st_bst_address_export => ram_st_bst_copi.address(c_sdp_ram_st_bst_addr_w - 1 downto 0),
+ ram_st_bst_write_export => ram_st_bst_copi.wr,
+ ram_st_bst_writedata_export => ram_st_bst_copi.wrdata(c_word_w - 1 downto 0),
+ ram_st_bst_read_export => ram_st_bst_copi.rd,
+ ram_st_bst_readdata_export => ram_st_bst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_enable_sst_clk_export => OPEN,
+ reg_stat_enable_sst_reset_export => OPEN,
+ reg_stat_enable_sst_address_export => reg_stat_enable_sst_copi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
+ reg_stat_enable_sst_write_export => reg_stat_enable_sst_copi.wr,
+ reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_enable_sst_read_export => reg_stat_enable_sst_copi.rd,
+ reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_hdr_dat_sst_clk_export => OPEN,
+ reg_stat_hdr_dat_sst_reset_export => OPEN,
+ reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
+ reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_copi.wr,
+ reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_copi.rd,
+ reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_enable_xst_clk_export => OPEN,
+ reg_stat_enable_xst_reset_export => OPEN,
+ reg_stat_enable_xst_address_export => reg_stat_enable_xst_copi.address(c_sdp_reg_stat_enable_addr_w - 1 downto 0),
+ reg_stat_enable_xst_write_export => reg_stat_enable_xst_copi.wr,
+ reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_enable_xst_read_export => reg_stat_enable_xst_copi.rd,
+ reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_hdr_dat_xst_clk_export => OPEN,
+ reg_stat_hdr_dat_xst_reset_export => OPEN,
+ reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w - 1 downto 0),
+ reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_copi.wr,
+ reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_copi.rd,
+ reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_enable_bst_clk_export => OPEN,
+ reg_stat_enable_bst_reset_export => OPEN,
+ reg_stat_enable_bst_address_export => reg_stat_enable_bst_copi.address(c_sdp_reg_stat_enable_bst_addr_w - 1 downto 0),
+ reg_stat_enable_bst_write_export => reg_stat_enable_bst_copi.wr,
+ reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_enable_bst_read_export => reg_stat_enable_bst_copi.rd,
+ reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_stat_hdr_dat_bst_clk_export => OPEN,
+ reg_stat_hdr_dat_bst_reset_export => OPEN,
+ reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_copi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w - 1 downto 0),
+ reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_copi.wr,
+ reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_copi.rd,
+ reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_crosslets_info_clk_export => OPEN,
+ reg_crosslets_info_reset_export => OPEN,
+ reg_crosslets_info_address_export => reg_crosslets_info_copi.address(c_sdp_reg_crosslets_info_addr_w - 1 downto 0),
+ reg_crosslets_info_write_export => reg_crosslets_info_copi.wr,
+ reg_crosslets_info_writedata_export => reg_crosslets_info_copi.wrdata(c_word_w - 1 downto 0),
+ reg_crosslets_info_read_export => reg_crosslets_info_copi.rd,
+ reg_crosslets_info_readdata_export => reg_crosslets_info_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_nof_crosslets_clk_export => OPEN,
+ reg_nof_crosslets_reset_export => OPEN,
+ reg_nof_crosslets_address_export => reg_nof_crosslets_copi.address(c_sdp_reg_nof_crosslets_addr_w - 1 downto 0),
+ reg_nof_crosslets_write_export => reg_nof_crosslets_copi.wr,
+ reg_nof_crosslets_writedata_export => reg_nof_crosslets_copi.wrdata(c_word_w - 1 downto 0),
+ reg_nof_crosslets_read_export => reg_nof_crosslets_copi.rd,
+ reg_nof_crosslets_readdata_export => reg_nof_crosslets_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_copi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w - 1 downto 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_copi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_copi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_st_xsq_clk_export => OPEN,
+ ram_st_xsq_reset_export => OPEN,
+ ram_st_xsq_address_export => ram_st_xsq_copi.address(c_sdp_ram_st_xsq_arr_addr_w - 1 downto 0),
+ ram_st_xsq_write_export => ram_st_xsq_copi.wr,
+ ram_st_xsq_writedata_export => ram_st_xsq_copi.wrdata(c_word_w - 1 downto 0),
+ ram_st_xsq_read_export => ram_st_xsq_copi.rd,
+ ram_st_xsq_readdata_export => ram_st_xsq_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_nw_10GbE_mac_clk_export => OPEN,
+ reg_nw_10GbE_mac_reset_export => OPEN,
+ reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_copi.address(c_sdp_reg_nw_10GbE_mac_addr_w - 1 downto 0),
+ reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_copi.wr,
+ reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
+ reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_copi.rd,
+ reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_nw_10GbE_eth10g_clk_export => OPEN,
+ reg_nw_10GbE_eth10g_reset_export => OPEN,
+ reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_copi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w - 1 downto 0),
+ reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_copi.wr,
+ reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
+ reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
+ reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_align_v2_bf_clk_export => OPEN,
+ reg_bsn_align_v2_bf_reset_export => OPEN,
+ reg_bsn_align_v2_bf_address_export => reg_bsn_align_v2_bf_copi.address(c_sdp_reg_bsn_align_v2_bf_addr_w - 1 downto 0),
+ reg_bsn_align_v2_bf_write_export => reg_bsn_align_v2_bf_copi.wr,
+ reg_bsn_align_v2_bf_writedata_export => reg_bsn_align_v2_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_align_v2_bf_read_export => reg_bsn_align_v2_bf_copi.rd,
+ reg_bsn_align_v2_bf_readdata_export => reg_bsn_align_v2_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_rx_align_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_address_export => reg_bsn_monitor_v2_rx_align_bf_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_align_bf_write_export => reg_bsn_monitor_v2_rx_align_bf_copi.wr,
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export => reg_bsn_monitor_v2_rx_align_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_align_bf_read_export => reg_bsn_monitor_v2_rx_align_bf_copi.rd,
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export => reg_bsn_monitor_v2_rx_align_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_aligned_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_address_export => reg_bsn_monitor_v2_aligned_bf_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_aligned_bf_write_export => reg_bsn_monitor_v2_aligned_bf_copi.wr,
+ reg_bsn_monitor_v2_aligned_bf_writedata_export => reg_bsn_monitor_v2_aligned_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_aligned_bf_read_export => reg_bsn_monitor_v2_aligned_bf_copi.rd,
+ reg_bsn_monitor_v2_aligned_bf_readdata_export => reg_bsn_monitor_v2_aligned_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_align_v2_xsub_clk_export => OPEN,
+ reg_bsn_align_v2_xsub_reset_export => OPEN,
+ reg_bsn_align_v2_xsub_address_export => reg_bsn_align_v2_xsub_copi.address(c_sdp_reg_bsn_align_v2_xsub_addr_w - 1 downto 0),
+ reg_bsn_align_v2_xsub_write_export => reg_bsn_align_v2_xsub_copi.wr,
+ reg_bsn_align_v2_xsub_writedata_export => reg_bsn_align_v2_xsub_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_align_v2_xsub_read_export => reg_bsn_align_v2_xsub_copi.rd,
+ reg_bsn_align_v2_xsub_readdata_export => reg_bsn_align_v2_xsub_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_address_export => reg_bsn_monitor_v2_rx_align_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_align_xsub_write_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wr,
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_align_xsub_read_export => reg_bsn_monitor_v2_rx_align_xsub_copi.rd,
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export => reg_bsn_monitor_v2_rx_align_xsub_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_aligned_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_address_export => reg_bsn_monitor_v2_aligned_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_aligned_xsub_write_export => reg_bsn_monitor_v2_aligned_xsub_copi.wr,
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export => reg_bsn_monitor_v2_aligned_xsub_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_aligned_xsub_read_export => reg_bsn_monitor_v2_aligned_xsub_copi.rd,
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export => reg_bsn_monitor_v2_aligned_xsub_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_address_export => reg_bsn_monitor_v2_sst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_sst_offload_write_export => reg_bsn_monitor_v2_sst_offload_copi.wr,
+ reg_bsn_monitor_v2_sst_offload_writedata_export => reg_bsn_monitor_v2_sst_offload_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_sst_offload_read_export => reg_bsn_monitor_v2_sst_offload_copi.rd,
+ reg_bsn_monitor_v2_sst_offload_readdata_export => reg_bsn_monitor_v2_sst_offload_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_bst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_address_export => reg_bsn_monitor_v2_bst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_bst_offload_write_export => reg_bsn_monitor_v2_bst_offload_copi.wr,
+ reg_bsn_monitor_v2_bst_offload_writedata_export => reg_bsn_monitor_v2_bst_offload_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_bst_offload_read_export => reg_bsn_monitor_v2_bst_offload_copi.rd,
+ reg_bsn_monitor_v2_bst_offload_readdata_export => reg_bsn_monitor_v2_bst_offload_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_beamlet_output_clk_export => OPEN,
+ reg_bsn_monitor_v2_beamlet_output_reset_export => OPEN,
+ reg_bsn_monitor_v2_beamlet_output_address_export => reg_bsn_monitor_v2_beamlet_output_copi.address(c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_beamlet_output_write_export => reg_bsn_monitor_v2_beamlet_output_copi.wr,
+ reg_bsn_monitor_v2_beamlet_output_writedata_export => reg_bsn_monitor_v2_beamlet_output_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_beamlet_output_read_export => reg_bsn_monitor_v2_beamlet_output_copi.rd,
+ reg_bsn_monitor_v2_beamlet_output_readdata_export => reg_bsn_monitor_v2_beamlet_output_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_xst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_xst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_xst_offload_address_export => reg_bsn_monitor_v2_xst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_xst_offload_write_export => reg_bsn_monitor_v2_xst_offload_copi.wr,
+ reg_bsn_monitor_v2_xst_offload_writedata_export => reg_bsn_monitor_v2_xst_offload_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_xst_offload_read_export => reg_bsn_monitor_v2_xst_offload_copi.rd,
+ reg_bsn_monitor_v2_xst_offload_readdata_export => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_ring_lane_info_bf_clk_export => OPEN,
+ reg_ring_lane_info_bf_reset_export => OPEN,
+ reg_ring_lane_info_bf_address_export => reg_ring_lane_info_bf_copi.address(c_sdp_reg_ring_lane_info_bf_addr_w - 1 downto 0),
+ reg_ring_lane_info_bf_write_export => reg_ring_lane_info_bf_copi.wr,
+ reg_ring_lane_info_bf_writedata_export => reg_ring_lane_info_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_lane_info_bf_read_export => reg_ring_lane_info_bf_copi.rd,
+ reg_ring_lane_info_bf_readdata_export => reg_ring_lane_info_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_address_export => reg_bsn_monitor_v2_ring_rx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_bf_write_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_bf_read_export => reg_bsn_monitor_v2_ring_rx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export => reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_address_export => reg_bsn_monitor_v2_ring_tx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_bf_write_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_bf_read_export => reg_bsn_monitor_v2_ring_tx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export => reg_bsn_monitor_v2_ring_tx_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_err_bf_clk_export => OPEN,
+ reg_dp_block_validate_err_bf_reset_export => OPEN,
+ reg_dp_block_validate_err_bf_address_export => reg_dp_block_validate_err_bf_copi.address(c_sdp_reg_dp_block_validate_err_bf_addr_w - 1 downto 0),
+ reg_dp_block_validate_err_bf_write_export => reg_dp_block_validate_err_bf_copi.wr,
+ reg_dp_block_validate_err_bf_writedata_export => reg_dp_block_validate_err_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_err_bf_read_export => reg_dp_block_validate_err_bf_copi.rd,
+ reg_dp_block_validate_err_bf_readdata_export => reg_dp_block_validate_err_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_address_export => reg_dp_block_validate_bsn_at_sync_bf_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_bf_write_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_bf_read_export => reg_dp_block_validate_bsn_at_sync_bf_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export => reg_dp_block_validate_bsn_at_sync_bf_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_ring_lane_info_xst_clk_export => OPEN,
+ reg_ring_lane_info_xst_reset_export => OPEN,
+ reg_ring_lane_info_xst_address_export => reg_ring_lane_info_xst_copi.address(c_sdp_reg_ring_lane_info_xst_addr_w - 1 downto 0),
+ reg_ring_lane_info_xst_write_export => reg_ring_lane_info_xst_copi.wr,
+ reg_ring_lane_info_xst_writedata_export => reg_ring_lane_info_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_ring_lane_info_xst_read_export => reg_ring_lane_info_xst_copi.rd,
+ reg_ring_lane_info_xst_readdata_export => reg_ring_lane_info_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_xst_address_export => reg_bsn_monitor_v2_ring_rx_xst_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_xst_write_export => reg_bsn_monitor_v2_ring_rx_xst_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export => reg_bsn_monitor_v2_ring_rx_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_rx_xst_read_export => reg_bsn_monitor_v2_ring_rx_xst_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export => reg_bsn_monitor_v2_ring_rx_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_xst_address_export => reg_bsn_monitor_v2_ring_tx_xst_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_xst_write_export => reg_bsn_monitor_v2_ring_tx_xst_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export => reg_bsn_monitor_v2_ring_tx_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_ring_tx_xst_read_export => reg_bsn_monitor_v2_ring_tx_xst_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export => reg_bsn_monitor_v2_ring_tx_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_err_xst_clk_export => OPEN,
+ reg_dp_block_validate_err_xst_reset_export => OPEN,
+ reg_dp_block_validate_err_xst_address_export => reg_dp_block_validate_err_xst_copi.address(c_sdp_reg_dp_block_validate_err_xst_addr_w - 1 downto 0),
+ reg_dp_block_validate_err_xst_write_export => reg_dp_block_validate_err_xst_copi.wr,
+ reg_dp_block_validate_err_xst_writedata_export => reg_dp_block_validate_err_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_err_xst_read_export => reg_dp_block_validate_err_xst_copi.rd,
+ reg_dp_block_validate_err_xst_readdata_export => reg_dp_block_validate_err_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_xst_address_export => reg_dp_block_validate_bsn_at_sync_xst_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_xst_write_export => reg_dp_block_validate_bsn_at_sync_xst_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export => reg_dp_block_validate_bsn_at_sync_xst_copi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_block_validate_bsn_at_sync_xst_read_export => reg_dp_block_validate_bsn_at_sync_xst_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export => reg_dp_block_validate_bsn_at_sync_xst_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_tr_10GbE_mac_clk_export => OPEN,
+ reg_tr_10GbE_mac_reset_export => OPEN,
+ reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w - 1 downto 0),
+ reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr,
+ reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd,
+ reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_tr_10GbE_eth10g_clk_export => OPEN,
+ reg_tr_10GbE_eth10g_reset_export => OPEN,
+ reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w - 1 downto 0),
+ reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr,
+ reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd,
+ reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w - 1 downto 0),
+
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_address_export => ram_scrap_copi.address(9 - 1 downto 0),
+ ram_scrap_write_export => ram_scrap_copi.wr,
+ ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_copi.rd,
+ ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 74c071dcbf..d89fe430e8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -19,549 +19,549 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_sdp_station_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_sdp_station is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2c_sdp_station;
+ component qsys_lofar2_unb2c_sdp_station is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2c_sdp_station;
end qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
index 2d86198b40..32660fe8c2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
@@ -31,20 +31,20 @@
-- c_eth_check_nof_packets = 1 instead of S_pn = 12.
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use eth_lib.eth_pkg.all;
entity tb_lofar2_unb2c_sdp_station is
end tb_lofar2_unb2c_sdp_station;
@@ -138,44 +138,44 @@ begin
-- >> DUT <<
u_lofar_unb2c_sdp_station : entity work.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk_slv,
- ETH_SGIN => eth_rxp_slv,
- ETH_SGOUT => eth_txp_slv,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk_slv,
+ ETH_SGIN => eth_rxp_slv,
+ ETH_SGOUT => eth_txp_slv,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
---------------------------------------------------------------------------------------------------------------------
-- Stimuli
@@ -235,13 +235,13 @@ begin
-- >> Verify proper DUT output using Ethernet packet statistics <<
u_eth_statistics : entity eth_lib.eth_statistics
- generic map (
- g_runtime_nof_packets => c_eth_check_nof_packets,
- g_runtime_timeout => c_eth_runtime_timeout
- )
- port map (
- eth_serial_in => eth_txp_slv(0),
- tb_end => eth_done
- );
+ generic map (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout
+ )
+ port map (
+ eth_serial_in => eth_txp_slv(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
index 6e8b86e22b..c05bf03068 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
@@ -28,12 +28,12 @@
--
library IEEE, dp_lib, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_controller is
@@ -102,31 +102,31 @@ architecture rtl of ddrctrl_controller is
-- record for readability
type t_reg is record
- -- state of program
- state : t_state;
- started : std_logic;
-
- -- stopping signals
- filled_mem : std_logic;
- ready_for_set_stop : std_logic;
- stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
- last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
- stop_burstsize : natural;
- stopped : std_logic;
- rst_ddrctrl_input : std_logic;
-
- -- writing signals
- wr_burst_en : std_logic;
- wr_bursts_ready : natural;
-
- -- reading signals
- outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- read_adr : natural;
- rd_burst_en : std_logic;
-
- -- output
- dvr_mosi : t_mem_ctlr_mosi;
- wr_sosi : t_dp_sosi;
+ -- state of program
+ state : t_state;
+ started : std_logic;
+
+ -- stopping signals
+ filled_mem : std_logic;
+ ready_for_set_stop : std_logic;
+ stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
+ last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
+ stop_burstsize : natural;
+ stopped : std_logic;
+ rst_ddrctrl_input : std_logic;
+
+ -- writing signals
+ wr_burst_en : std_logic;
+ wr_bursts_ready : natural;
+
+ -- reading signals
+ outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ read_adr : natural;
+ rd_burst_en : std_logic;
+
+ -- output
+ dvr_mosi : t_mem_ctlr_mosi;
+ wr_sosi : t_dp_sosi;
end record;
constant c_t_reg_init : t_reg := (RESET, '0', '0', '0', TO_UVEC(g_max_adr, c_adr_w), (others => '0'), 0, '1', '1', '0', 0, (others => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
@@ -153,240 +153,240 @@ begin
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
- v.dvr_mosi.wr := '1';
- v.wr_sosi.valid := '1';
-
- if rst = '0' then
- v.state := STOP_READING;
- end if;
-
-
- when STOP_READING =>
- -- this is the last read burst, this make sure every data containing word in the memory has been read.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.stopped := '0';
- v.wr_sosi.valid := '0';
- v.state := WAIT_FOR_SOP;
- v.wr_burst_en := '1';
- v.rst_ddrctrl_input := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
-
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
-
-
- when WAIT_FOR_SOP =>
- v.dvr_mosi.burstbegin := '0';
- v.rst_ddrctrl_input := '0';
- if q_reg.started = '0' and inp_sosi.eop = '1' then
- v.wr_sosi.valid := '1';
- elsif inp_sosi.sop = '1' then
- v.state := WRITING;
- else
- v.wr_sosi.valid := '0';
- end if;
-
-
- when WRITING =>
- -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ when RESET =>
+ v := c_t_reg_init;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
+ v.dvr_mosi.wr := '1';
+ v.wr_sosi.valid := '1';
+
+ if rst = '0' then
+ v.state := STOP_READING;
+ end if;
+
+
+ when STOP_READING =>
+ -- this is the last read burst, this make sure every data containing word in the memory has been read.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.stopped := '0';
+ v.wr_sosi.valid := '0';
+ v.state := WAIT_FOR_SOP;
+ v.wr_burst_en := '1';
+ v.rst_ddrctrl_input := '1';
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.burstbegin := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
-
- if stop_in = '1' then
- v.ready_for_set_stop := '1';
- end if;
-
- if inp_adr >= c_pof_ma then
- v.filled_mem := '1';
- end if
-
- if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' and v.filled_mem = '1' then
- v.state := SET_STOP;
- elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- end if;
-
-
- when SET_STOP =>
- -- this state sets a stop address dependend on the g_stop_percentage.
- if inp_adr - c_pof_ma >= 0 then
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
- else
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
- end if;
- v.ready_for_set_stop := '0';
- v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
- v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
- v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w - 1 downto 0)) - TO_UINT(v.last_adr_to_write_to) + 1;
-
- -- still a write cyle
- -- if adr mod g_burstsize = 0
- -- this makes sure that only ones every 64 writes a writeburst is started.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+
+ when WAIT_FOR_SOP =>
+ v.dvr_mosi.burstbegin := '0';
+ v.rst_ddrctrl_input := '0';
+ if q_reg.started = '0' and inp_sosi.eop = '1' then
+ v.wr_sosi.valid := '1';
+ elsif inp_sosi.sop = '1' then
+ v.state := WRITING;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.wr_sosi.valid := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- else
- v.state := WRITING;
- end if;
-
-
- when STOP_WRITING =>
- -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
- v.wr_sosi.valid := '0';
- v.dvr_mosi.burstbegin := '0';
- v.stopped := '1';
- v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-
- -- still receiving write data.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+
+
+ when WRITING =>
+ -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 then
- v.state := LAST_WRITE_BURST;
- end if;
-
-
- when LAST_WRITE_BURST =>
- -- this state stops the writing by generatign one last write burst which empties wr_fifo.
- if dvr_miso.done = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.state := START_READING;
- v.rd_burst_en := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
-
- when START_READING =>
- -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
- v.dvr_mosi.burstbegin := '0';
- v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn) - g_bim, c_dp_stream_bsn_w);
-
- if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize, c_adr_w);
- v.rd_burst_en := '0';
- v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
- end if;
-
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
- v.rd_burst_en := '1';
- v.state := READING;
- end if;
-
-
- when READING =>
- -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.burstbegin := '1';
- v.rd_burst_en := '0';
- if q_reg.read_adr > g_max_adr - g_burstsize then
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := 0;
+
+ if stop_in = '1' then
+ v.ready_for_set_stop := '1';
+ end if;
+
+ if inp_adr >= c_pof_ma then
+ v.filled_mem := '1';
+ end if
+
+ if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' and v.filled_mem = '1' then
+ v.state := SET_STOP;
+ elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
+ end if;
+
+
+ when SET_STOP =>
+ -- this state sets a stop address dependend on the g_stop_percentage.
+ if inp_adr - c_pof_ma >= 0 then
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
else
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := q_reg.read_adr + g_burstsize;
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
+ end if;
+ v.ready_for_set_stop := '0';
+ v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
+ v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
+ v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w - 1 downto 0)) - TO_UINT(v.last_adr_to_write_to) + 1;
+
+ -- still a write cyle
+ -- if adr mod g_burstsize = 0
+ -- this makes sure that only ones every 64 writes a writeburst is started.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
end if;
- else
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
+ else
+ v.state := WRITING;
+ end if;
+
+
+ when STOP_WRITING =>
+ -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
+ v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
- end if;
+ v.stopped := '1';
+ v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
+
+ -- still receiving write data.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 then
+ v.state := LAST_WRITE_BURST;
+ end if;
+
+
+ when LAST_WRITE_BURST =>
+ -- this state stops the writing by generatign one last write burst which empties wr_fifo.
+ if dvr_miso.done = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.state := START_READING;
+ v.rd_burst_en := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+
+ when START_READING =>
+ -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
+ v.dvr_mosi.burstbegin := '0';
+ v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn) - g_bim, c_dp_stream_bsn_w);
+
+ if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize, c_adr_w);
+ v.rd_burst_en := '0';
+ v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
+ v.rd_burst_en := '1';
+ v.state := READING;
+ end if;
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
- -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
- if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
- v.state := STOP_READING;
- end if;
+ when READING =>
+ -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.burstbegin := '1';
+ v.rd_burst_en := '0';
+ if q_reg.read_adr > g_max_adr - g_burstsize then
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := 0;
+ else
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := q_reg.read_adr + g_burstsize;
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+ -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
+ if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
+ v.state := STOP_READING;
+ end if;
end case;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index f9e02cedd9..6f922e3aeb 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -33,16 +33,16 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use io_ddr_lib.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use io_ddr_lib.all;
entity ddrctrl is
@@ -153,175 +153,175 @@ begin
-- input to io_ddr
u_ddrctrl_input : entity work.ddrctrl_input
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_max_adr => c_nof_adr,
- g_bim => c_bim,
- g_of_pb => c_of_pb,
- g_block_size => g_block_size
- )
- port map(
- clk => clk,
- rst => rst,
- rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
- in_sosi_arr => in_sosi_arr,
- in_stop => stop,
- out_sosi => out_sosi,
- out_adr => out_adr,
- out_bsn_adr => inp_bsn_adr,
- out_data_stopped => data_stopped
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_max_adr => c_nof_adr,
+ g_bim => c_bim,
+ g_of_pb => c_of_pb,
+ g_block_size => g_block_size
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
+ in_sosi_arr => in_sosi_arr,
+ in_stop => stop,
+ out_sosi => out_sosi,
+ out_adr => out_adr,
+ out_bsn_adr => inp_bsn_adr,
+ out_data_stopped => data_stopped
+ );
-- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
u_io_ddr : entity io_ddr_lib.io_ddr
- generic map(
- g_sim_model => g_sim_model,
- g_technology => g_technology,
- g_tech_ddr => g_tech_ddr,
- g_cross_domain_dvr_ctlr => false,
- g_wr_data_w => c_io_ddr_data_w,
- g_wr_fifo_depth => c_wr_fifo_depth,
- g_rd_fifo_depth => c_rd_fifo_depth,
- g_rd_data_w => c_io_ddr_data_w,
- g_wr_flush_mode => "VAL",
- g_wr_flush_use_channel => false,
- g_wr_flush_start_channel => 0,
- g_wr_flush_nof_channels => 1
+ generic map(
+ g_sim_model => g_sim_model,
+ g_technology => g_technology,
+ g_tech_ddr => g_tech_ddr,
+ g_cross_domain_dvr_ctlr => false,
+ g_wr_data_w => c_io_ddr_data_w,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_io_ddr_data_w,
+ g_wr_flush_mode => "VAL",
+ g_wr_flush_use_channel => false,
+ g_wr_flush_start_channel => 0,
+ g_wr_flush_nof_channels => 1
)
port map(
- -- DDR reference clock
- ctlr_ref_clk => ctlr_ref_clk,
- ctlr_ref_rst => ctlr_ref_rst,
+ -- DDR reference clock
+ ctlr_ref_clk => ctlr_ref_clk,
+ ctlr_ref_rst => ctlr_ref_rst,
- -- DDR controller clock domain
- ctlr_clk_out => ctrl_clk,
- ctlr_rst_out => ctrl_rst,
+ -- DDR controller clock domain
+ ctlr_clk_out => ctrl_clk,
+ ctlr_rst_out => ctrl_rst,
- ctlr_clk_in => ctrl_clk,
- ctlr_rst_in => ctrl_rst,
+ ctlr_clk_in => ctrl_clk,
+ ctlr_rst_in => ctrl_rst,
- -- MM clock + reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
- state_vec => state_vec,
- ctlr_wr_flush_en_o => ctlr_wr_flush_en,
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+ state_vec => state_vec,
+ ctlr_wr_flush_en_o => ctlr_wr_flush_en,
- -- Driver clock domain
- dvr_clk => clk,
- dvr_rst => rst,
+ -- Driver clock domain
+ dvr_clk => clk,
+ dvr_rst => rst,
- dvr_miso => dvr_miso,
- dvr_mosi => dvr_mosi,
+ dvr_miso => dvr_miso,
+ dvr_mosi => dvr_mosi,
- -- Write FIFO clock domain
- wr_clk => clk,
- wr_rst => rst,
+ -- Write FIFO clock domain
+ wr_clk => clk,
+ wr_rst => rst,
- wr_fifo_usedw => wr_fifo_usedw,
- wr_sosi => wr_sosi,
- wr_siso => open,
+ wr_fifo_usedw => wr_fifo_usedw,
+ wr_sosi => wr_sosi,
+ wr_siso => open,
- -- Read FIFO clock domain
- rd_clk => clk,
- rd_rst => rst,
+ -- Read FIFO clock domain
+ rd_clk => clk,
+ rd_rst => rst,
- rd_fifo_usedw => rd_fifo_usedw,
- rd_sosi => rd_sosi,
- rd_siso => rd_siso,
+ rd_fifo_usedw => rd_fifo_usedw,
+ rd_sosi => rd_sosi,
+ rd_siso => rd_siso,
- term_ctrl_out => term_ctrl_out,
- term_ctrl_in => term_ctrl_in,
+ term_ctrl_out => term_ctrl_out,
+ term_ctrl_in => term_ctrl_in,
- -- DDR3 PHY external interface
- phy3_in => phy3_in,
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
+ -- DDR3 PHY external interface
+ phy3_in => phy3_in,
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
- -- DDR4 PHY external interface
- phy4_in => phy4_in,
- phy4_io => phy4_io,
- phy4_ou => phy4_ou
- );
+ -- DDR4 PHY external interface
+ phy4_in => phy4_in,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
+ );
-- reading ddr memory
u_ddrctrl_output : entity work.ddrctrl_output
- generic map(
- g_technology => g_technology,
- g_tech_ddr => g_tech_ddr,
- g_sim_model => g_sim_model,
- g_in_data_w => c_io_ddr_data_w,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_block_size => g_block_size,
- g_bim => c_bim
- )
- port map(
- clk => clk,
- rst => rst,
-
- in_sosi => rd_sosi,
- in_bsn => bsn_co,
-
- out_sosi_arr => out_sosi_arr,
- out_siso => out_siso,
- out_ready => rd_ready
- );
+ generic map(
+ g_technology => g_technology,
+ g_tech_ddr => g_tech_ddr,
+ g_sim_model => g_sim_model,
+ g_in_data_w => c_io_ddr_data_w,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_block_size => g_block_size,
+ g_bim => c_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+
+ in_sosi => rd_sosi,
+ in_bsn => bsn_co,
+
+ out_sosi_arr => out_sosi_arr,
+ out_siso => out_siso,
+ out_ready => rd_ready
+ );
-- controller of ddrctrl
u_ddrctrl_controller : entity work.ddrctrl_controller
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_stop_percentage => g_stop_percentage,
- g_nof_streams => g_nof_streams,
- g_out_data_w => g_data_w,
- g_wr_data_w => c_io_ddr_data_w,
- g_rd_fifo_depth => c_rd_fifo_depth,
- g_rd_data_w => c_io_ddr_data_w,
- g_block_size => g_block_size,
- g_wr_fifo_uw_w => c_wr_fifo_uw_w,
- g_rd_fifo_uw_w => c_rd_fifo_uw_w,
- g_max_adr => c_nof_adr,
- g_burstsize => c_burstsize,
- g_last_burstsize => c_last_burstsize,
- g_adr_per_b => c_adr_per_b,
- g_bim => c_bim
- )
- port map(
- clk => clk,
- rst => rst,
-
- -- ddrctrl_input
- inp_of => out_of,
- inp_sosi => out_sosi,
- inp_adr => out_adr,
- inp_bsn_adr => inp_bsn_adr,
- inp_data_stopped => data_stopped,
- rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
-
- -- io_ddr
- dvr_mosi => dvr_mosi,
- dvr_miso => dvr_miso,
- wr_sosi => wr_sosi,
- wr_siso => c_dp_siso_rdy,
- wr_fifo_usedw => wr_fifo_usedw,
- rd_fifo_usedw => rd_fifo_usedw,
- ctlr_wr_flush_en => ctlr_wr_flush_en,
- flush_state => state_vec,
-
- -- ddrctrl_output
- outp_bsn => bsn_co,
-
- -- ddrctrl_controller
- stop_in => stop_in,
- stop_out => stop,
- ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_stop_percentage => g_stop_percentage,
+ g_nof_streams => g_nof_streams,
+ g_out_data_w => g_data_w,
+ g_wr_data_w => c_io_ddr_data_w,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_io_ddr_data_w,
+ g_block_size => g_block_size,
+ g_wr_fifo_uw_w => c_wr_fifo_uw_w,
+ g_rd_fifo_uw_w => c_rd_fifo_uw_w,
+ g_max_adr => c_nof_adr,
+ g_burstsize => c_burstsize,
+ g_last_burstsize => c_last_burstsize,
+ g_adr_per_b => c_adr_per_b,
+ g_bim => c_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+
+ -- ddrctrl_input
+ inp_of => out_of,
+ inp_sosi => out_sosi,
+ inp_adr => out_adr,
+ inp_bsn_adr => inp_bsn_adr,
+ inp_data_stopped => data_stopped,
+ rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
+
+ -- io_ddr
+ dvr_mosi => dvr_mosi,
+ dvr_miso => dvr_miso,
+ wr_sosi => wr_sosi,
+ wr_siso => c_dp_siso_rdy,
+ wr_fifo_usedw => wr_fifo_usedw,
+ rd_fifo_usedw => rd_fifo_usedw,
+ ctlr_wr_flush_en => ctlr_wr_flush_en,
+ flush_state => state_vec,
+
+ -- ddrctrl_output
+ outp_bsn => bsn_co,
+
+ -- ddrctrl_controller
+ stop_in => stop_in,
+ stop_out => stop,
+ ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
+ );
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 95495f5428..fe159f4946 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -28,12 +28,12 @@
--
library IEEE, dp_lib, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_controller is
@@ -127,34 +127,34 @@ architecture rtl of ddrctrl_controller is
-- record for readability
type t_reg is record
- -- state of program
- state : t_state;
- started : std_logic;
-
- -- stopping flush
- timer : natural;
-
- -- stopping signals
- ready_for_set_stop : std_logic;
- stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
- last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
- stop_burstsize : natural;
- stopped : std_logic;
- rst_ddrctrl_input_ac : std_logic;
-
- -- writing signals
- wr_burst_en : std_logic;
- wr_bursts_ready : natural;
-
- -- reading signals
- outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- read_adr : natural;
- rd_burst_en : std_logic;
-
- -- output
- dvr_mosi : t_mem_ctlr_mosi;
- wr_sosi : t_dp_sosi;
- ddrctrl_ctrl_state : std_logic_vector(32 - 1 downto 0);
+ -- state of program
+ state : t_state;
+ started : std_logic;
+
+ -- stopping flush
+ timer : natural;
+
+ -- stopping signals
+ ready_for_set_stop : std_logic;
+ stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
+ last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
+ stop_burstsize : natural;
+ stopped : std_logic;
+ rst_ddrctrl_input_ac : std_logic;
+
+ -- writing signals
+ wr_burst_en : std_logic;
+ wr_bursts_ready : natural;
+
+ -- reading signals
+ outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ read_adr : natural;
+ rd_burst_en : std_logic;
+
+ -- output
+ dvr_mosi : t_mem_ctlr_mosi;
+ wr_sosi : t_dp_sosi;
+ ddrctrl_ctrl_state : std_logic_vector(32 - 1 downto 0);
end record;
constant c_t_reg_init : t_reg := (RESET, '0', 4, '0', TO_UVEC(g_max_adr, c_adr_w), (others => '0'), 0, '1', '1', '0', 0, (others => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init, (others => '0'));
@@ -182,285 +182,285 @@ begin
--v.ddrctrl_ctrl_state(c_high_adr_ndx DOWNTO c_low_adr_ndx) := TO_UVEC(inp_adr, 32)(c_adr_ndx_w-1 DOWNTO 0);
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(0, c_state_ndx_w);
+ when RESET =>
+ v := c_t_reg_init;
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(0, c_state_ndx_w);
- if rst = '0' and wr_siso.ready = '1' then
- v.state := STOP_FLUSH;
- v.timer := 0;
- end if;
+ if rst = '0' and wr_siso.ready = '1' then
+ v.state := STOP_FLUSH;
+ v.timer := 0;
+ end if;
+
+
+ when STOP_FLUSH =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
+ v.wr_sosi.valid := '0';
+ if flush_state = "10" then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
+ v.dvr_mosi.wr := '1';
+ elsif flush_state = "11" and q_reg.timer = 0 then
+ v.wr_sosi.valid := '1';
+ v.timer := 127;
+ end if;
+
+ if q_reg.timer > 0 and rst = '0' then
+ v.timer := q_reg.timer - 1;
+ end if;
+
+ if flush_state = "01" then
+ v.state := WAIT_FOR_SOP;
+ v.stopped := '0';
+ end if;
- when STOP_FLUSH =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
- v.wr_sosi.valid := '0';
- if flush_state = "10" then
- v.dvr_mosi.burstbegin := '1';
+ when STOP_READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
+ -- this is the last read burst, this make sure every data containing word in the memory has been read.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.stopped := '0';
+ v.wr_sosi.valid := '1';
+ v.state := WAIT_FOR_SOP;
+ v.wr_burst_en := '1';
+ v.rst_ddrctrl_input_ac := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+
+ when WAIT_FOR_SOP =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
+ v.dvr_mosi.burstbegin := '0';
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
v.dvr_mosi.wr := '1';
- elsif flush_state = "11" and q_reg.timer = 0 then
- v.wr_sosi.valid := '1';
- v.timer := 127;
- end if;
-
- if q_reg.timer > 0 and rst = '0' then
- v.timer := q_reg.timer - 1;
- end if;
-
- if flush_state = "01" then
- v.state := WAIT_FOR_SOP;
- v.stopped := '0';
- end if;
-
-
- when STOP_READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
- -- this is the last read burst, this make sure every data containing word in the memory has been read.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.stopped := '0';
- v.wr_sosi.valid := '1';
- v.state := WAIT_FOR_SOP;
- v.wr_burst_en := '1';
- v.rst_ddrctrl_input_ac := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
-
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
-
-
- when WAIT_FOR_SOP =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
- v.dvr_mosi.burstbegin := '0';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
- v.rst_ddrctrl_input_ac := '0';
- if q_reg.started = '0' and inp_sosi.eop = '1' then
- v.wr_sosi.valid := '0';
- elsif inp_sosi.sop = '1' then
- v.state := WRITING;
- else
- v.wr_sosi.valid := '0';
- end if;
-
-
- when WRITING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
- -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.rd := '0';
+ v.rst_ddrctrl_input_ac := '0';
+ if q_reg.started = '0' and inp_sosi.eop = '1' then
+ v.wr_sosi.valid := '0';
+ elsif inp_sosi.sop = '1' then
+ v.state := WRITING;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.wr_sosi.valid := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
-
- if stop_in = '1' then
- v.ready_for_set_stop := '1';
- end if;
-
- if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' then
- v.state := SET_STOP;
- elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- end if;
-
-
- when SET_STOP =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
- -- this state sets a stop address dependend on the g_stop_percentage.
- if inp_adr - c_pof_ma >= 0 then
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
- else
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
- end if;
- v.ready_for_set_stop := '0';
- if v.stop_adr(c_adr_w - 1 downto 0) = c_stop_adr_zeros(c_adr_w - 1 downto 0) then
- v.last_adr_to_write_to(c_adr_w - 1 downto 0) := TO_UVEC(g_max_adr - g_last_burstsize, c_adr_w);
- else
- v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
- end if;
- v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
- v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w - 1 downto 0), -1 * TO_UINT(v.last_adr_to_write_to)),1));
-
- -- still a write cyle
- -- if adr mod g_burstsize = 0
- -- this makes sure that only ones every 64 writes a writeburst is started.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+
+
+ when WRITING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
+ -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.burstbegin := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- else
- v.state := WRITING;
- end if;
-
-
- when STOP_WRITING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
- -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
- v.wr_sosi.valid := '0';
- v.dvr_mosi.burstbegin := '0';
- v.stopped := '1';
- v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-
- -- still receiving write data.
- v.wr_bursts_ready := TO_UINT(INCR_UVEC(wr_fifo_usedw, 2)(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+
+ if stop_in = '1' then
+ v.ready_for_set_stop := '1';
+ end if;
+
+ if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' then
+ v.state := SET_STOP;
+ elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
+ end if;
+
+
+ when SET_STOP =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
+ -- this state sets a stop address dependend on the g_stop_percentage.
+ if inp_adr - c_pof_ma >= 0 then
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 and inp_data_stopped = '1' and TO_UINT(wr_fifo_usedw) <= q_reg.stop_burstsize then
- v.state := LAST_WRITE_BURST;
- end if;
-
-
- when LAST_WRITE_BURST =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
- -- this state stops the writing by generatign one last write burst which empties wr_fifo.
- v.wr_sosi.valid := '0';
- if dvr_miso.done = '1' then
- if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) >= g_max_adr then
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.ready_for_set_stop := '0';
+ if v.stop_adr(c_adr_w - 1 downto 0) = c_stop_adr_zeros(c_adr_w - 1 downto 0) then
+ v.last_adr_to_write_to(c_adr_w - 1 downto 0) := TO_UVEC(g_max_adr - g_last_burstsize, c_adr_w);
else
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
+ end if;
+ v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
+ v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w - 1 downto 0), -1 * TO_UINT(v.last_adr_to_write_to)),1));
+
+ -- still a write cyle
+ -- if adr mod g_burstsize = 0
+ -- this makes sure that only ones every 64 writes a writeburst is started.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
end if;
- v.dvr_mosi.burstbegin := '1';
- v.state := START_READING;
- v.rd_burst_en := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
-
- when START_READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
- -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
- v.dvr_mosi.burstbegin := '0';
- v.outp_bsn := INCR_UVEC(inp_sosi.bsn, -1 * g_bim);
- v.wr_sosi.valid := '0';
-
- if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize >= g_max_adr then
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
- v.read_adr := g_burstsize;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := INCR_UVEC(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0), q_reg.stop_burstsize);
- v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ v.dvr_mosi.burstbegin := '0';
end if;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.rd_burst_en := '0';
- end if;
-
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
- v.rd_burst_en := '1';
- v.state := READING;
- end if;
-
-
- when READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(9, c_state_ndx_w);
- v.wr_sosi.valid := '0';
- -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.burstbegin := '1';
- v.rd_burst_en := '0';
- if q_reg.read_adr > g_max_adr - g_burstsize then
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := 0;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
else
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := q_reg.read_adr + g_burstsize;
+ v.state := WRITING;
end if;
- else
+
+
+ when STOP_WRITING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
+ -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
+ v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
- end if;
+ v.stopped := '1';
+ v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
+
+ -- still receiving write data.
+ v.wr_bursts_ready := TO_UINT(INCR_UVEC(wr_fifo_usedw, 2)(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 and inp_data_stopped = '1' and TO_UINT(wr_fifo_usedw) <= q_reg.stop_burstsize then
+ v.state := LAST_WRITE_BURST;
+ end if;
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
- -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
- if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
- v.state := STOP_READING;
- end if;
+ when LAST_WRITE_BURST =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
+ -- this state stops the writing by generatign one last write burst which empties wr_fifo.
+ v.wr_sosi.valid := '0';
+ if dvr_miso.done = '1' then
+ if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) >= g_max_adr then
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ v.dvr_mosi.burstbegin := '1';
+ v.state := START_READING;
+ v.rd_burst_en := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+
+ when START_READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
+ -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
+ v.dvr_mosi.burstbegin := '0';
+ v.outp_bsn := INCR_UVEC(inp_sosi.bsn, -1 * g_bim);
+ v.wr_sosi.valid := '0';
+
+ if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize >= g_max_adr then
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
+ v.read_adr := g_burstsize;
+ else
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := INCR_UVEC(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0), q_reg.stop_burstsize);
+ v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ end if;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.rd_burst_en := '0';
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
+ v.rd_burst_en := '1';
+ v.state := READING;
+ end if;
+
+
+ when READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(9, c_state_ndx_w);
+ v.wr_sosi.valid := '0';
+ -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.burstbegin := '1';
+ v.rd_burst_en := '0';
+ if q_reg.read_adr > g_max_adr - g_burstsize then
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := 0;
+ else
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := q_reg.read_adr + g_burstsize;
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+ -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
+ if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
+ v.state := STOP_READING;
+ end if;
end case;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index 7947c5d3f4..4c25ce3e2d 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -33,13 +33,13 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input is
@@ -85,48 +85,48 @@ begin
-- makes one data vector out of all the data from the t_dp_sosi_arr
u_ddrctrl_input_pack : entity work.ddrctrl_input_pack
- generic map(
- g_nof_streams => g_nof_streams, -- number of input streams
- g_data_w => g_data_w -- data with of input data vectors
- )
- port map(
- in_sosi_arr => in_sosi_arr, -- input data
- out_sosi => sosi_p_rp -- output data
- );
+ generic map(
+ g_nof_streams => g_nof_streams, -- number of input streams
+ g_data_w => g_data_w -- data with of input data vectors
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr, -- input data
+ out_sosi => sosi_p_rp -- output data
+ );
-- resizes the input data vector so that the output data vector can be stored into the ddr memory
u_ddrctrl_input_repack : entity work.ddrctrl_input_repack
- generic map(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_in_data_w => c_out_data_w, -- the input data with
- g_bim => g_bim,
- g_of_pb => g_of_pb,
- g_block_size => g_block_size
- )
- port map(
- clk => clk,
- rst => rst,
- in_sosi => sosi_p_rp, -- input data
- in_stop => in_stop,
- out_sosi => sosi_rp_ac, -- output data
- out_data_stopped => data_stopped_rp_ac
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_in_data_w => c_out_data_w, -- the input data with
+ g_bim => g_bim,
+ g_of_pb => g_of_pb,
+ g_block_size => g_block_size
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ in_sosi => sosi_p_rp, -- input data
+ in_stop => in_stop,
+ out_sosi => sosi_rp_ac, -- output data
+ out_data_stopped => data_stopped_rp_ac
+ );
-- creates address by counting input valids
u_ddrctrl_input_address_counter : entity work.ddrctrl_input_address_counter
- generic map(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_max_adr => g_max_adr
- )
- port map(
- clk => clk,
- rst => rst_ddrctrl_input_ac,
- in_sosi => sosi_rp_ac, -- input data
- in_data_stopped => data_stopped_rp_ac,
- out_sosi => out_sosi, -- output data
- out_adr => adr,
- out_bsn_adr => out_bsn_adr,
- out_data_stopped => out_data_stopped
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_max_adr => g_max_adr
+ )
+ port map(
+ clk => clk,
+ rst => rst_ddrctrl_input_ac,
+ in_sosi => sosi_rp_ac, -- input data
+ in_data_stopped => data_stopped_rp_ac,
+ out_sosi => out_sosi, -- output data
+ out_adr => adr,
+ out_bsn_adr => out_bsn_adr,
+ out_data_stopped => out_data_stopped
+ );
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index bd1d65946f..617e3f5c3c 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -30,13 +30,13 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input_address_counter is
@@ -67,14 +67,14 @@ architecture rtl of ddrctrl_input_address_counter is
-- record for readability
type t_reg is record
- state : t_state;
- bsn_passed : std_logic;
- out_sosi : t_dp_sosi;
- out_bsn_adr : natural;
- out_data_stopped : std_logic;
- s_in_sosi : t_dp_sosi;
- s_in_data_stopped : std_logic;
- s_adr : natural;
+ state : t_state;
+ bsn_passed : std_logic;
+ out_sosi : t_dp_sosi;
+ out_bsn_adr : natural;
+ out_data_stopped : std_logic;
+ s_in_sosi : t_dp_sosi;
+ s_in_data_stopped : std_logic;
+ s_adr : natural;
end record;
constant c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, '0', c_dp_sosi_init, '0', 0);
@@ -91,7 +91,7 @@ begin
-- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
p_adr : process(rst, in_sosi, in_data_stopped, q_reg)
- variable v : t_reg;
+ variable v : t_reg;
begin
v := q_reg;
@@ -104,35 +104,35 @@ begin
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
+ when RESET =>
+ v := c_t_reg_init;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when COUNTING =>
- v.s_adr := q_reg.s_adr + 1;
+ when COUNTING =>
+ v.s_adr := q_reg.s_adr + 1;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when MAX =>
- v.s_adr := 0;
+ when MAX =>
+ v.s_adr := 0;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when IDLE =>
- -- after a reset wait for a sop so the memory will be filled with whole blocks.
- if in_sosi.sop = '1' then
- v.bsn_passed := '1';
- end if;
+ when IDLE =>
+ -- after a reset wait for a sop so the memory will be filled with whole blocks.
+ if in_sosi.sop = '1' then
+ v.bsn_passed := '1';
+ end if;
end case;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
index 5990dbd818..d01d9457d8 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
@@ -28,8 +28,8 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input_pack is
generic (
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 046f8889ff..a5b2390d81 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -30,9 +30,9 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_input_repack is
generic (
@@ -65,16 +65,16 @@ architecture rtl of ddrctrl_input_repack is
-- record for readability
type t_reg is record
- state : t_state; -- the state the process is currently in;
- c_v : std_logic_vector(k_c_v_w - 1 downto 0); -- the vector that stores the input data until the data is put into the output data vector
- c_v_count : natural; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
- q_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- q_sop : std_logic;
- s_input_cnt : natural;
- out_of : natural;
- out_data_count : std_logic; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
- out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
- out_data_stopped : std_logic; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
+ state : t_state; -- the state the process is currently in;
+ c_v : std_logic_vector(k_c_v_w - 1 downto 0); -- the vector that stores the input data until the data is put into the output data vector
+ c_v_count : natural; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
+ q_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ q_sop : std_logic;
+ s_input_cnt : natural;
+ out_of : natural;
+ out_data_count : std_logic; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
+ out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
+ out_data_stopped : std_logic; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
end record;
constant c_t_reg_init : t_reg := (RESET, (others => '0'), 0, (others => '0'), '0', 0, 0, '0', c_dp_sosi_init, '0');
@@ -98,74 +98,74 @@ begin
v := q_reg;
case q_reg.state is
- when FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
- v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.valid := '0'; -- out_sosi.valid 0
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.out_sosi.sop := '0';
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
-
- when FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
- v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := q_reg.q_bsn(c_dp_stream_bsn_w - 1 downto 0);
- v.out_sosi.sop := q_reg.q_sop;
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
-
- when OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
- v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2); -- check how much overflow there is and safe it in out_of
- v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0); -- fill the rest of c_v untill the end
- v.c_v(v.out_of - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto g_in_data_w - v.out_of); -- fill the start of c_v untill the out_of
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.c_v_count := 0; -- reset counter
- v.out_data_count := '0'; -- reset counter
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.q_sop := '0';
- v.out_sosi.sop := '0';
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
-
- when BSN =>
-
- v.c_v(k_c_v_w - 1 downto ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of)) := (others => '0');
- v.out_of := 0;
- if ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of < c_out_data_w * 1) then
+ when FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
+ v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
+ v.out_sosi.valid := '0'; -- out_sosi.valid 0
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.out_sosi.sop := '0';
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+
+ when FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
+ v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- else
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := q_reg.q_bsn(c_dp_stream_bsn_w - 1 downto 0);
+ v.out_sosi.sop := q_reg.q_sop;
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+
+ when OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
+ v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2); -- check how much overflow there is and safe it in out_of
+ v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0); -- fill the rest of c_v untill the end
+ v.c_v(v.out_of - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto g_in_data_w - v.out_of); -- fill the start of c_v untill the out_of
v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- end if;
-
- -- BSN_INPUT
- v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
- v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
- v.c_v(g_in_data_w - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := 1; -- increase the counter of c_v with 1
- v.out_data_count := '0';
- v.out_sosi.eop := '1';
-
-
- when RESET =>
- v := c_t_reg_init;
- v.q_bsn(c_dp_stream_bsn_w - 1 downto 0) := in_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0);
-
-
- when STOP =>
- v.out_sosi.valid := '0';
- v.q_sop := '0';
- v.out_data_stopped := '1';
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.c_v_count := 0; -- reset counter
+ v.out_data_count := '0'; -- reset counter
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.q_sop := '0';
+ v.out_sosi.sop := '0';
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+
+ when BSN =>
+
+ v.c_v(k_c_v_w - 1 downto ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of)) := (others => '0');
+ v.out_of := 0;
+ if ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of < c_out_data_w * 1) then
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ else
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ end if;
+
+ -- BSN_INPUT
+ v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
+ v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
+ v.c_v(g_in_data_w - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := 1; -- increase the counter of c_v with 1
+ v.out_data_count := '0';
+ v.out_sosi.eop := '1';
+
+
+ when RESET =>
+ v := c_t_reg_init;
+ v.q_bsn(c_dp_stream_bsn_w - 1 downto 0) := in_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0);
+
+
+ when STOP =>
+ v.out_sosi.valid := '0';
+ v.q_sop := '0';
+ v.out_data_stopped := '1';
end case;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index 1a1b8efa1d..a384eceb23 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -30,13 +30,13 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_output is
@@ -74,8 +74,8 @@ architecture str of ddrctrl_output is
-- signals for connecting the components
signal sosi : t_dp_sosi := c_dp_sosi_init;
signal out_sosi : t_dp_sosi := c_dp_sosi_init;
--- SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
--- SIGNAL fifo_snk_in_sosi : t_dp_sosi := c_dp_sosi_init;
+ -- SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
+ -- SIGNAL fifo_snk_in_sosi : t_dp_sosi := c_dp_sosi_init;
signal q_out_siso : t_dp_siso := c_dp_siso_rst;
signal q_q_out_siso : t_dp_siso := c_dp_siso_rst;
signal unpack_state_off : std_logic := '0';
@@ -87,79 +87,79 @@ begin
-- makes one data vector out of all the data from the t_dp_sosi_arr
u_ddrctrl_output_unpack : entity work.ddrctrl_output_unpack
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_in_data_w => g_in_data_w,
- g_out_data_w => c_out_data_w,
- g_block_size => g_block_size,
- g_bim => g_bim
- )
- port map(
- clk => clk,
- rst => rst,
- in_sosi => in_sosi, -- input data
- in_bsn => in_bsn,
- out_siso => out_siso,
- out_sosi => out_sosi, -- output data
- out_ready => out_ready,
- state_off => unpack_state_off
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_in_data_w => g_in_data_w,
+ g_out_data_w => c_out_data_w,
+ g_block_size => g_block_size,
+ g_bim => g_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ in_sosi => in_sosi, -- input data
+ in_bsn => in_bsn,
+ out_siso => out_siso,
+ out_sosi => out_sosi, -- output data
+ out_ready => out_ready,
+ state_off => unpack_state_off
+ );
-- resizes the input data vector so that the output data vector can be stored into the ddr memory
u_ddrctrl_output_repack : entity work.ddrctrl_output_repack
- generic map(
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w
- )
- port map(
- in_sosi => sosi,
- out_sosi_arr => out_sosi_arr
- );
-
-
--- u_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
--- GENERIC MAP (
--- g_technology => g_technology,
--- g_wr_data_w => c_out_data_w,
--- g_rd_data_w => c_out_data_w,
--- g_use_ctrl => FALSE,
--- g_wr_fifo_size => c_fifo_size,
--- g_wr_fifo_af_margin => 0,
--- g_rd_fifo_rl => 0
--- )
--- PORT MAP (
--- wr_rst => rst,
--- wr_clk => clk,
--- rd_rst => rst,
--- rd_clk => clk,
---
--- snk_out => OPEN,
--- snk_in => fifo_snk_in_sosi,
---
--- wr_ful => OPEN,
--- wr_usedw => fifo_usedw,
--- rd_usedw => OPEN,
--- rd_emp => OPEN,
---
--- src_in => siso,
--- src_out => fifo_src_out_sosi
--- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w
+ )
+ port map(
+ in_sosi => sosi,
+ out_sosi_arr => out_sosi_arr
+ );
+
+
+ -- u_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+ -- GENERIC MAP (
+ -- g_technology => g_technology,
+ -- g_wr_data_w => c_out_data_w,
+ -- g_rd_data_w => c_out_data_w,
+ -- g_use_ctrl => FALSE,
+ -- g_wr_fifo_size => c_fifo_size,
+ -- g_wr_fifo_af_margin => 0,
+ -- g_rd_fifo_rl => 0
+ -- )
+ -- PORT MAP (
+ -- wr_rst => rst,
+ -- wr_clk => clk,
+ -- rd_rst => rst,
+ -- rd_clk => clk,
+ --
+ -- snk_out => OPEN,
+ -- snk_in => fifo_snk_in_sosi,
+ --
+ -- wr_ful => OPEN,
+ -- wr_usedw => fifo_usedw,
+ -- rd_usedw => OPEN,
+ -- rd_emp => OPEN,
+ --
+ -- src_in => siso,
+ -- src_out => fifo_src_out_sosi
+ -- );
p_out_siso_ready : process(out_siso, clk, out_sosi, q_out_siso)
- variable sosi_valid : std_logic := '0';
+ variable sosi_valid : std_logic := '0';
begin
if out_siso.ready = '0' and not (q_out_siso.ready = out_siso.ready) then
sosi <= out_sosi;
sosi_valid := '0';
- -- assert false report "sosi.valid = '0'" severity note;
+ -- assert false report "sosi.valid = '0'" severity note;
elsif q_out_siso.ready = '1' and not (q_q_out_siso.ready = q_out_siso.ready) and unpack_state_off = '0' then
sosi <= out_sosi;
sosi_valid := '1';
- -- assert false report "sosi.valid = '1'" severity note;
+ -- assert false report "sosi.valid = '1'" severity note;
else
sosi <= out_sosi;
sosi_valid := out_sosi.valid;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
index 0996454c91..93f243129c 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
@@ -29,9 +29,9 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
entity ddrctrl_output_repack is
generic (
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index 328e80cc75..8b23ce8a41 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -32,10 +32,10 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, tech_ddr_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
entity ddrctrl_output_unpack is
generic (
@@ -67,17 +67,17 @@ architecture rtl of ddrctrl_output_unpack is
-- record for readability
type t_reg is record
- state : t_state;
- a_of : natural;
- op_data_cnt : natural;
- delay_data : std_logic_vector(g_in_data_w - 1 downto 0);
- dd_fresh : std_logic;
- valid_data : std_logic;
- c_v : std_logic_vector(c_v_w - 1 downto 0);
- bsn_cnt : natural;
- out_sosi : t_dp_sosi;
- out_ready : std_logic;
- state_off : std_logic;
+ state : t_state;
+ a_of : natural;
+ op_data_cnt : natural;
+ delay_data : std_logic_vector(g_in_data_w - 1 downto 0);
+ dd_fresh : std_logic;
+ valid_data : std_logic;
+ c_v : std_logic_vector(c_v_w - 1 downto 0);
+ bsn_cnt : natural;
+ out_sosi : t_dp_sosi;
+ out_ready : std_logic;
+ state_off : std_logic;
end record;
constant c_t_reg_init : t_reg := (RESET, 0, 0, (others => '0'), '0', '0', (others => '0'), 0, c_dp_sosi_init, '0', '0');
@@ -101,98 +101,98 @@ begin
if out_siso.ready = '1' or q_reg.state = OFF or q_reg.state = IDLE or q_reg.state = RESET or rst = '1' then
case q_reg.state is
- when READING =>
- -- generating output from the data already present in c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- v.op_data_cnt := q_reg.op_data_cnt + 1;
-
- if q_reg.out_sosi.eop = '1' then
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
- v.out_sosi.eop := '0';
- v.out_sosi.sop := '1';
- v.bsn_cnt := 0;
- elsif q_reg.out_sosi.sop = '1' then
- v.out_sosi.sop := '0';
- end if;
-
-
- when OVER_HALF =>
- -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
- if q_reg.valid_data = '1' then
- -- generate output from the middle of c_v
+ when READING =>
+ -- generating output from the data already present in c_v
v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
v.out_sosi.valid := '1';
v.bsn_cnt := q_reg.bsn_cnt + 1;
- -- put the second half of c_v into the first half of c_v
- v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.valid_data := '0';
- v.a_of := ((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of) - g_in_data_w;
- v.op_data_cnt := 0;
- elsif q_reg.valid_data = '0' then
+ v.op_data_cnt := q_reg.op_data_cnt + 1;
+
+ if q_reg.out_sosi.eop = '1' then
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+ v.out_sosi.eop := '0';
+ v.out_sosi.sop := '1';
+ v.bsn_cnt := 0;
+ elsif q_reg.out_sosi.sop = '1' then
+ v.out_sosi.sop := '0';
+ end if;
+
+
+ when OVER_HALF =>
+ -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
+ if q_reg.valid_data = '1' then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
+ v.valid_data := '0';
+ v.a_of := ((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of) - g_in_data_w;
+ v.op_data_cnt := 0;
+ elsif q_reg.valid_data = '0' then
-- there is no data ready.
- end if;
-
- if q_reg.out_sosi.sop = '1' then
- v.out_sosi.sop := '0';
- end if;
-
-
- when FIRST_READ =>
- -- put the second half of c_v into the first half of c_v
- v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.valid_data := '0';
-
- -- fills the first half of c_v and generates output from it.
- v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.out_sosi.data(g_out_data_w - 1 downto 0) := v.c_v(g_out_data_w - 1 downto 0);
- v.out_sosi.valid := '1';
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := in_bsn(c_dp_stream_bsn_w - 1 downto 0);
- v.out_sosi.sop := '1';
- v.out_sosi.eop := '0';
- v.bsn_cnt := 0;
- v.op_data_cnt := 1;
-
-
- when BSN =>
- -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
- v.out_sosi.valid := '0';
- if q_reg.valid_data = '1' then
- -- generate output from the middle of c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- -- put the second half of c_v into the first half of c_v
- v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.valid_data := '0';
- v.op_data_cnt := 0;
- elsif (g_out_data_w * (v.op_data_cnt + 1)) + q_reg.a_of < g_in_data_w then
- -- generate output from the middle of c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- end if;
-
- v.out_sosi.eop := '1';
- v.a_of := 0;
- v.bsn_cnt := q_reg.bsn_cnt + 1;
-
-
- when RESET =>
- v := c_t_reg_init;
+ end if;
+ if q_reg.out_sosi.sop = '1' then
+ v.out_sosi.sop := '0';
+ end if;
- when IDLE =>
- -- the statemachine goes to Idle when its finished or when its waiting on other components.
- v.out_sosi.valid := '0';
+ when FIRST_READ =>
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
+ v.valid_data := '0';
- when OFF =>
- -- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
- v.out_sosi := c_dp_sosi_init;
- v.bsn_cnt := 0;
- v.state_off := '1';
+ -- fills the first half of c_v and generates output from it.
+ v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := v.c_v(g_out_data_w - 1 downto 0);
+ v.out_sosi.valid := '1';
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := in_bsn(c_dp_stream_bsn_w - 1 downto 0);
+ v.out_sosi.sop := '1';
+ v.out_sosi.eop := '0';
+ v.bsn_cnt := 0;
+ v.op_data_cnt := 1;
+
+
+ when BSN =>
+ -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
+ v.out_sosi.valid := '0';
+ if q_reg.valid_data = '1' then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
+ v.valid_data := '0';
+ v.op_data_cnt := 0;
+ elsif (g_out_data_w * (v.op_data_cnt + 1)) + q_reg.a_of < g_in_data_w then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ end if;
+
+ v.out_sosi.eop := '1';
+ v.a_of := 0;
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+
+
+ when RESET =>
+ v := c_t_reg_init;
+
+
+ when IDLE =>
+ -- the statemachine goes to Idle when its finished or when its waiting on other components.
+ v.out_sosi.valid := '0';
+
+
+ when OFF =>
+ -- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
+ v.out_sosi := c_dp_sosi_init;
+ v.bsn_cnt := 0;
+ v.state_off := '1';
end case;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 45282ae543..ce22415a6b 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -24,15 +24,15 @@
-- > run -a
library IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_ddrctrl is
@@ -100,7 +100,7 @@ architecture tb of tb_ddrctrl is
constant c_of_after_nof_adr : natural := c_of_after_nof_adr_init;
-- function for making total data vector
- function c_total_vector_init return std_logic_vector is
+ function c_total_vector_init return std_logic_vector is
variable temp : std_logic_vector(g_data_w * g_nof_streams * c_bim * g_block_size-1 downto 0);
variable conv : std_logic_vector(32 - 1 downto 0) := (others => '0'); -- removes a warning
begin
@@ -162,7 +162,7 @@ begin
-- excecuting test
p_test : process
- variable out_siso_ready : natural := 0;
+ variable out_siso_ready : natural := 0;
begin
@@ -250,9 +250,9 @@ begin
if out_sosi_arr(0).valid = '1' then
for I in 0 to g_nof_streams - 1 loop
if c_output_stop_adr + output_data_cnt <= c_max_adr then
- --ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
+ --ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
else
- --ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
+ --ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
end if;
end loop;
output_data_cnt <= output_data_cnt + 1;
@@ -264,32 +264,32 @@ begin
-- DUT
u_ddrctrl : entity work.ddrctrl
- generic map (
- g_tech_ddr => c_tech_ddr,
- g_sim_model => c_sim_model,
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_stop_percentage => g_stop_percentage,
- g_block_size => g_block_size
- )
- port map (
- clk => clk,
- rst => rst,
- ctlr_ref_clk => clk,
- ctlr_ref_rst => rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- in_sosi_arr => in_sosi_arr,
- stop_in => stop_in,
- out_sosi_arr => out_sosi_arr,
- out_siso => out_siso,
-
- --PHY
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
- phy4_io => phy4_io,
- phy4_ou => phy4_ou
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr,
+ g_sim_model => c_sim_model,
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_stop_percentage => g_stop_percentage,
+ g_block_size => g_block_size
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ ctlr_ref_clk => clk,
+ ctlr_ref_rst => rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ in_sosi_arr => in_sosi_arr,
+ stop_in => stop_in,
+ out_sosi_arr => out_sosi_arr,
+ out_siso => out_siso,
+
+ --PHY
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
+ );
end tb;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index ece0816c57..6ca3e2b941 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -27,13 +27,13 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_adc_input_and_timing is
generic (
@@ -191,35 +191,35 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
- g_nof_streams => c_sdp_S_pn,
- g_nof_sync_n => c_sdp_N_sync_jesd,
- g_jesd_freq => c_sdp_jesd204b_freq
- )
- port map(
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_jesd,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn - 1 downto 0)
- );
+ generic map(
+ g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
+ g_nof_streams => c_sdp_S_pn,
+ g_nof_sync_n => c_sdp_N_sync_jesd,
+ g_jesd_freq => c_sdp_jesd204b_freq
+ )
+ port map(
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_jesd,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
@@ -240,80 +240,80 @@ begin
end process;
u_dp_shiftram : entity dp_lib.dp_shiftram
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_nof_words => c_sdp_V_sample_delay,
- g_data_w => c_sdp_W_adc,
- g_use_sync_in => true
- )
- port map (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_nof_words => c_sdp_V_sample_delay,
+ g_data_w => c_sdp_W_adc,
+ g_use_sync_in => true
+ )
+ port map (
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sync_in => bs_sosi.sync,
+ sync_in => bs_sosi.sync,
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => dp_shiftram_snk_in_arr,
+ snk_in_arr => dp_shiftram_snk_in_arr,
- src_out_arr => ant_sosi_arr
- );
+ src_out_arr => ant_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source_v2 : entity dp_lib.mms_dp_bsn_source_v2
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_v2_mosi,
- reg_miso => reg_bsn_source_v2_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi,
-
- bs_restart => rx_bsn_source_restart,
- bs_new_interval => rx_bsn_source_new_interval,
- bs_nof_clk_per_sync => rx_bsn_source_nof_clk_per_sync
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_v2_mosi,
+ reg_miso => reg_bsn_source_v2_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi,
+
+ bs_restart => rx_bsn_source_restart,
+ bs_new_interval => rx_bsn_source_new_interval,
+ bs_nof_clk_per_sync => rx_bsn_source_nof_clk_per_sync
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
-----------------------------------------------------------------------------
@@ -321,39 +321,39 @@ begin
-----------------------------------------------------------------------------
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi,
- reg_miso => reg_wg_miso,
-
- buf_mosi => ram_wg_mosi,
- buf_miso => ram_wg_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_mosi,
+ reg_miso => reg_wg_miso,
+
+ buf_mosi => ram_wg_mosi,
+ buf_miso => ram_wg_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
-----------------------------------------------------------------------------
@@ -399,53 +399,53 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => c_bs_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => c_bs_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-----------------------------------------------------------------------------
u_aduh_monitor : entity aduh_lib.mms_aduh_monitor_arr
- generic map (
- g_cross_clock_domain => true,
- g_nof_streams => c_sdp_S_pn,
- g_symbol_w => c_sdp_W_adc,
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => g_bsn_nof_clk_per_sync
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_aduh_monitor_miso,
- buf_mosi => c_mem_mosi_rst, -- Unused
- buf_miso => OPEN,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
-
- in_sosi_arr => st_sosi_arr
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_nof_streams => c_sdp_S_pn,
+ g_symbol_w => c_sdp_W_adc,
+ g_nof_symbols_per_data => 1, -- Wideband factor is 1
+ g_nof_accumulations => g_bsn_nof_clk_per_sync
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+ reg_miso => reg_aduh_monitor_miso,
+ buf_mosi => c_mem_mosi_rst, -- Unused
+ buf_miso => OPEN,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+
+ in_sosi_arr => st_sosi_arr
+ );
-----------------------------------------------------------------------------
@@ -453,49 +453,49 @@ begin
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
-- ST Histogram
-----------------------------------------------------------------------------
u_st_histogram : entity st_lib.mmp_st_histogram
- generic map (
- g_nof_instances => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc,
- g_nof_bins => c_sdp_V_si_histogram,
- g_nof_data_per_sync => g_bsn_nof_clk_per_sync,
- g_nof_data_per_sync_diff => c_sdp_N_fft / 2
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_copi => ram_st_histogram_mosi,
- ram_cipo => ram_st_histogram_miso,
-
- snk_in_arr => st_sosi_arr
- );
+ generic map (
+ g_nof_instances => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_nof_bins => c_sdp_V_si_histogram,
+ g_nof_data_per_sync => g_bsn_nof_clk_per_sync,
+ g_nof_data_per_sync_diff => c_sdp_N_fft / 2
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_copi => ram_st_histogram_mosi,
+ ram_cipo => ram_st_histogram_miso,
+
+ snk_in_arr => st_sosi_arr
+ );
-----------------------------------------------------------------------------
@@ -541,37 +541,37 @@ begin
-- in mms_dp_bsn_monitor, and from rx_clk to dp_clk here. No need to go via
-- u_dp_fifo_dc_arr, use common_reg_cross_domain instead to save logic and/or RAM.
u_dp_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => rx_rst,
- in_clk => rx_clk,
- in_dat => rx_bsn_source_nof_clk_per_sync,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_dat => dp_bsn_source_nof_clk_per_sync
- );
+ port map (
+ in_rst => rx_rst,
+ in_clk => rx_clk,
+ in_dat => rx_bsn_source_nof_clk_per_sync,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_dat => dp_bsn_source_nof_clk_per_sync
+ );
-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_sdp_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg_wr,
- in_reg => mm_jesd_ctrl_reg_rd
- );
+ generic map (
+ g_reg => c_sdp_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg_wr,
+ in_reg => mm_jesd_ctrl_reg_rd
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index ccca16990b..0b9c4e6712 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -30,13 +30,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_beamformer is
generic (
@@ -150,74 +150,74 @@ begin
-- Beamlet Subband Select
---------------------------------------------------------------
u_reorder_col_wide : entity reorder_lib.reorder_col_wide
- generic map (
- g_wb_factor => c_sdp_P_pfb, -- g_wb_factor is only used for number of parallel streams
- g_dsp_data_w => g_subband_raw_dat_w,
- g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
- g_nof_ch_sel => c_sdp_S_sub_bf * c_sdp_Q_fft,
- g_select_file_prefix => c_bf_select_file_prefix,
- g_use_complex => true
- )
- port map(
- input_sosi_arr => in_sosi_arr,
- output_sosi_arr => bsel_sosi_arr,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_wb_factor => c_sdp_P_pfb, -- g_wb_factor is only used for number of parallel streams
+ g_dsp_data_w => g_subband_raw_dat_w,
+ g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
+ g_nof_ch_sel => c_sdp_S_sub_bf * c_sdp_Q_fft,
+ g_select_file_prefix => c_bf_select_file_prefix,
+ g_use_complex => true
+ )
+ port map(
+ input_sosi_arr => in_sosi_arr,
+ output_sosi_arr => bsel_sosi_arr,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- Local BF
---------------------------------------------------------------
u_sdp_beamformer_local : entity work.sdp_beamformer_local
- generic map (
- g_bf_weights_file_name => c_bf_weights_file_name,
- g_raw_dat_w => g_subband_raw_dat_w,
- g_raw_fraction_w => g_subband_raw_fraction_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
-
- in_sosi_arr => bsel_sosi_arr,
- out_sosi => local_bf_sosi
- );
+ generic map (
+ g_bf_weights_file_name => c_bf_weights_file_name,
+ g_raw_dat_w => g_subband_raw_dat_w,
+ g_raw_fraction_w => g_subband_raw_fraction_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+
+ in_sosi_arr => bsel_sosi_arr,
+ out_sosi => local_bf_sosi
+ );
---------------------------------------------------------------
-- Remote BF
---------------------------------------------------------------
u_sdp_beamformer_remote : entity work.sdp_beamformer_remote
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- rn_index => rn_index,
- local_bf_sosi => local_bf_sosi,
- from_ri_sosi => from_ri_sosi,
- to_ri_sosi => to_ri_sosi,
- bf_sum_sosi => bf_sum_sosi,
-
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
-
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
-
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
- );
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ rn_index => rn_index,
+ local_bf_sosi => local_bf_sosi,
+ from_ri_sosi => from_ri_sosi,
+ to_ri_sosi => to_ri_sosi,
+ bf_sum_sosi => bf_sum_sosi,
+
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
+ );
---------------------------------------------------------------
-- Scale Beamlets
@@ -256,82 +256,82 @@ begin
-- Beamlet Data Output (BDO)
---------------------------------------------------------------
u_sdp_beamformer_output : entity work.sdp_beamformer_output
- generic map(
- g_beamset_id => g_beamset_id
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_sosi => bf_out_sosi,
- out_sosi => mon_bf_udp_sosi,
- out_siso => bf_udp_siso,
-
- beamlet_scale => beamlet_scale,
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => bdo_eth_src_mac,
- ip_src_addr => bdo_ip_src_addr,
- udp_src_port => bdo_udp_src_port,
-
- hdr_fields_out => bdo_hdr_fields_out,
-
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso
- );
+ generic map(
+ g_beamset_id => g_beamset_id
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_sosi => bf_out_sosi,
+ out_sosi => mon_bf_udp_sosi,
+ out_siso => bf_udp_siso,
+
+ beamlet_scale => beamlet_scale,
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => bdo_eth_src_mac,
+ ip_src_addr => bdo_ip_src_addr,
+ udp_src_port => bdo_udp_src_port,
+
+ hdr_fields_out => bdo_hdr_fields_out,
+
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso
+ );
bf_udp_sosi <= mon_bf_udp_sosi;
u_bsn_mon_udp : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1,
- g_cross_clock_domain => true,
- g_sync_timeout => c_sdp_N_clk_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_miso => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr(0) => mon_bf_udp_sosi
- );
+ generic map (
+ g_nof_streams => 1,
+ g_cross_clock_domain => true,
+ g_sync_timeout => c_sdp_N_clk_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_miso => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr(0) => mon_bf_udp_sosi
+ );
---------------------------------------------------------------
-- Beamlet Statistics (BST)
---------------------------------------------------------------
u_beamlet_stats : entity st_lib.st_sst
- generic map(
- g_nof_stat => c_sdp_S_sub_bf * c_sdp_N_pol_bf,
- g_in_data_w => c_sdp_W_beamlet_sum,
- g_stat_data_w => c_longword_w,
- g_stat_data_sz => c_longword_sz / c_word_sz,
- g_stat_multiplex => c_sdp_N_pol_bf
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_complex => bf_sum_sosi,
- ram_st_sst_mosi => master_mem_mux_mosi,
- ram_st_sst_miso => master_mem_mux_miso
- );
+ generic map(
+ g_nof_stat => c_sdp_S_sub_bf * c_sdp_N_pol_bf,
+ g_in_data_w => c_sdp_W_beamlet_sum,
+ g_stat_data_w => c_longword_w,
+ g_stat_data_sz => c_longword_sz / c_word_sz,
+ g_stat_multiplex => c_sdp_N_pol_bf
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_complex => bf_sum_sosi,
+ ram_st_sst_mosi => master_mem_mux_mosi,
+ ram_st_sst_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- MM master multiplexer
@@ -343,62 +343,62 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- BST UDP offload
---------------------------------------------------------------
u_sdp_bst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "BST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
- g_beamset_id => g_beamset_id
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "BST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
+ g_beamset_id => g_beamset_id
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_stat_enable_mosi,
- reg_enable_miso => reg_stat_enable_miso,
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- in_sosi => bf_sum_sosi,
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => bf_sum_sosi,
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => bst_udp_sosi,
- out_siso => bst_udp_siso,
+ out_sosi => bst_udp_sosi,
+ out_siso => bst_udp_siso,
- eth_src_mac => stat_eth_src_mac,
- udp_src_port => stat_udp_src_port,
- ip_src_addr => stat_ip_src_addr,
+ eth_src_mac => stat_eth_src_mac,
+ udp_src_port => stat_udp_src_port,
+ ip_src_addr => stat_ip_src_addr,
- gn_index => TO_UINT(gn_id),
- ring_info => ring_info,
- sdp_info => sdp_info,
- weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
- );
+ gn_index => TO_UINT(gn_id),
+ ring_info => ring_info,
+ sdp_info => sdp_info,
+ weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ );
---------------------------------------------------------------
-- SIGNAL SCOPES
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 0a1c4695c8..d7b35706b6 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -32,13 +32,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_correlator is
generic (
@@ -99,16 +99,16 @@ architecture str of node_sdp_correlator is
constant c_block_size_longwords : natural := ceil_div(c_block_size, 2); -- 32b -> 64b
constant c_data_w : natural := c_sdp_W_crosslet * c_nof_complex;
--- The size for 1 block is probably already enough as the number of blocks received
--- on the remote input of the mux probably have enough gap time in between. Just
--- to be sure to not run into issues in the future, the fifo size is increased to
--- buffer the maximum nof blocks per block period.
+ -- The size for 1 block is probably already enough as the number of blocks received
+ -- on the remote input of the mux probably have enough gap time in between. Just
+ -- to be sure to not run into issues in the future, the fifo size is increased to
+ -- buffer the maximum nof blocks per block period.
constant c_mux_fifo_size : natural := 2**ceil_log2(g_P_sq * c_block_size_longwords);
--- c_fifo_fill_size should be at least 2 * c_block_size_longwords as dp_repack_data
--- repacks from 64bit to 32bit. Chosing 3x to have some room.
+ -- c_fifo_fill_size should be at least 2 * c_block_size_longwords as dp_repack_data
+ -- repacks from 64bit to 32bit. Chosing 3x to have some room.
constant c_fifo_fill_size : natural := 2**ceil_log2(3 * c_block_size_longwords);
--- crosslet statistics offload
+ -- crosslet statistics offload
signal ram_st_offload_copi : t_mem_copi := c_mem_copi_rst;
signal ram_st_offload_cipo : t_mem_cipo := c_mem_cipo_rst;
@@ -149,57 +149,57 @@ begin
---------------------------------------------------------------
gen_requantize : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_requantize : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => g_subband_raw_fraction_w,
- g_lsb_round => true, -- round subband fraction
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 1,
- g_in_dat_w => g_subband_raw_dat_w,
- g_out_dat_w => c_sdp_W_crosslet
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => in_sosi_arr(I),
- src_out => quant_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => g_subband_raw_fraction_w,
+ g_lsb_round => true, -- round subband fraction
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 1,
+ g_in_dat_w => g_subband_raw_dat_w,
+ g_out_dat_w => c_sdp_W_crosslet
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => in_sosi_arr(I),
+ src_out => quant_sosi_arr(I)
+ );
end generate;
---------------------------------------------------------------
-- Crosslet Subband Select
---------------------------------------------------------------
u_crosslets_subband_select : entity work.sdp_crosslets_subband_select
- generic map (
- g_N_crosslets => c_sdp_N_crosslets_max,
- g_ctrl_interval_size_min => sel_a_b(g_sim, g_sim_sdp.xst_nof_clk_per_sync_min, c_sdp_xst_nof_clk_per_sync_min)
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ generic map (
+ g_N_crosslets => c_sdp_N_crosslets_max,
+ g_ctrl_interval_size_min => sel_a_b(g_sim, g_sim_sdp.xst_nof_clk_per_sync_min, c_sdp_xst_nof_clk_per_sync_min)
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- in_sosi_arr => quant_sosi_arr,
- out_sosi => xsel_sosi,
+ in_sosi_arr => quant_sosi_arr,
+ out_sosi => xsel_sosi,
- new_interval => new_interval,
+ new_interval => new_interval,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_crosslets_info_mosi => reg_crosslets_info_copi,
- reg_crosslets_info_miso => reg_crosslets_info_cipo,
+ reg_crosslets_info_mosi => reg_crosslets_info_copi,
+ reg_crosslets_info_miso => reg_crosslets_info_cipo,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_cipo,
- cur_crosslets_info_rec => OPEN,
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ cur_crosslets_info_rec => OPEN,
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
-- Use xsel_sosi as local bsn and sync reference since the sync
-- is generated by the bsn_sync_scheduler in sdp_crosslets_subband_select.
@@ -217,110 +217,110 @@ begin
end process;
u_dp_repack_data_local : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => c_longword_w / c_data_w,
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 1,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => xsel_data_sosi,
- src_out => local_sosi
- );
+ generic map (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => c_longword_w / c_data_w,
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 1,
+ g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => xsel_data_sosi,
+ src_out => local_sosi
+ );
---------------------------------------------------------------
-- ring_mux
---------------------------------------------------------------
u_ring_mux : entity ring_lib.ring_mux
- generic map (
- g_bsn_w => c_dp_stream_bsn_w,
- g_data_w => c_longword_w,
- g_channel_w => c_word_w,
- g_use_error => false,
- g_fifo_size => array_init(c_mux_fifo_size, 2)
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- remote_sosi => from_ri_sosi,
- local_sosi => local_sosi,
- mux_sosi => ring_mux_sosi,
- mux_siso => ring_mux_siso
- );
+ generic map (
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_data_w => c_longword_w,
+ g_channel_w => c_word_w,
+ g_use_error => false,
+ g_fifo_size => array_init(c_mux_fifo_size, 2)
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ remote_sosi => from_ri_sosi,
+ local_sosi => local_sosi,
+ mux_sosi => ring_mux_sosi,
+ mux_siso => ring_mux_siso
+ );
to_ri_sosi <= ring_mux_sosi;
-- fill fifo to remove gaps
u_dp_fifo_fill_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_data_w => c_longword_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_fifo_fill => c_block_size_longwords,
- g_fifo_size => c_fifo_fill_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- snk_out => ring_mux_siso,
- snk_in => ring_mux_sosi,
-
- src_in => dp_fifo_fill_siso,
- src_out => dp_fifo_fill_sosi
- );
+ generic map (
+ g_data_w => c_longword_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_fifo_fill => c_block_size_longwords,
+ g_fifo_size => c_fifo_fill_size
+ )
+ port map (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ snk_out => ring_mux_siso,
+ snk_in => ring_mux_sosi,
+
+ src_in => dp_fifo_fill_siso,
+ src_out => dp_fifo_fill_sosi
+ );
---------------------------------------------------------------
-- Repack 64b to 32b
---------------------------------------------------------------
u_dp_repack_data_rx : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_longword_w,
- g_in_nof_words => 1,
- g_out_dat_w => c_data_w,
- g_out_nof_words => c_longword_w / c_data_w,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_fill_sosi,
- snk_out => dp_fifo_fill_siso,
- src_out => rx_sosi
- );
+ generic map (
+ g_in_dat_w => c_longword_w,
+ g_in_nof_words => 1,
+ g_out_dat_w => c_data_w,
+ g_out_nof_words => c_longword_w / c_data_w,
+ g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_fill_sosi,
+ snk_out => dp_fifo_fill_siso,
+ src_out => rx_sosi
+ );
---------------------------------------------------------------
-- dp_demux
---------------------------------------------------------------
u_dp_demux : entity dp_lib.dp_demux
- generic map (
- g_mode => 0,
- g_nof_output => g_P_sq,
- g_remove_channel_lo => false,
- g_sel_ctrl_invert => true -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => rx_sosi,
- src_out_arr => dispatch_invert_sosi_arr
- );
+ generic map (
+ g_mode => 0,
+ g_nof_output => g_P_sq,
+ g_remove_channel_lo => false,
+ g_sel_ctrl_invert => true -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => rx_sosi,
+ src_out_arr => dispatch_invert_sosi_arr
+ );
dispatch_sosi_arr <= func_dp_stream_arr_reverse_range(dispatch_invert_sosi_arr);
@@ -329,71 +329,71 @@ begin
-- dp_bsn_aligner_v2
---------------------------------------------------------------
u_mmp_dp_bsn_align_v2 : entity dp_lib.mmp_dp_bsn_align_v2
- generic map(
- -- for dp_bsn_align_v2
- g_nof_streams => g_P_sq,
- g_bsn_latency_max => 2,
- g_nof_aligners_max => 1, -- 1 for Access scheme 3.
- g_block_size => c_block_size,
- g_data_w => c_data_w,
- g_use_mm_output => true,
- g_rd_latency => 1, -- Required for st_xst
- -- for mms_dp_bsn_monitor_v2
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub, -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
- g_nof_input_bsn_monitors => g_P_sq,
- g_use_bsn_output_monitor => true
+ generic map(
+ -- for dp_bsn_align_v2
+ g_nof_streams => g_P_sq,
+ g_bsn_latency_max => 2,
+ g_nof_aligners_max => 1, -- 1 for Access scheme 3.
+ g_block_size => c_block_size,
+ g_data_w => c_data_w,
+ g_use_mm_output => true,
+ g_rd_latency => 1, -- Required for st_xst
+ -- for mms_dp_bsn_monitor_v2
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub, -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_input_bsn_monitors => g_P_sq,
+ g_use_bsn_output_monitor => true
)
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
- reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+ reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
- reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
+ reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- Streaming input
- in_sosi_arr => dispatch_sosi_arr,
+ -- Streaming input
+ in_sosi_arr => dispatch_sosi_arr,
- -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
- mm_sosi => crosslets_sosi,
- mm_copi => crosslets_copi,
- mm_cipo_arr => crosslets_cipo_arr
- );
+ -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
+ mm_sosi => crosslets_sosi,
+ mm_copi => crosslets_copi,
+ mm_cipo_arr => crosslets_cipo_arr
+ );
---------------------------------------------------------------
-- Crosslets Statistics (XST)
---------------------------------------------------------------
u_crosslets_stats : entity st_lib.st_xst
- generic map(
- g_nof_streams => g_P_sq,
- g_nof_crosslets => c_sdp_N_crosslets_max,
- g_nof_signal_inputs => c_sdp_S_pn,
- g_in_data_w => c_sdp_W_crosslet,
- g_stat_data_w => c_longword_w,
- g_stat_data_sz => c_longword_sz / c_word_sz
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_sosi => crosslets_sosi,
- mm_mosi => crosslets_copi,
- mm_miso_arr => crosslets_cipo_arr,
-
- ram_st_xsq_mosi => controller_mem_mux_copi,
- ram_st_xsq_miso => controller_mem_mux_cipo
- );
+ generic map(
+ g_nof_streams => g_P_sq,
+ g_nof_crosslets => c_sdp_N_crosslets_max,
+ g_nof_signal_inputs => c_sdp_S_pn,
+ g_in_data_w => c_sdp_W_crosslet,
+ g_stat_data_w => c_longword_w,
+ g_stat_data_sz => c_longword_sz / c_word_sz
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi => crosslets_sosi,
+ mm_mosi => crosslets_copi,
+ mm_miso_arr => crosslets_cipo_arr,
+
+ ram_st_xsq_mosi => controller_mem_mux_copi,
+ ram_st_xsq_miso => controller_mem_mux_cipo
+ );
---------------------------------------------------------------
-- MM controller multiplexer
@@ -405,40 +405,40 @@ begin
ram_st_offload_cipo <= controller_cipo_arr(1);
u_mem_controller_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_controllers,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => controller_copi_arr,
- master_miso_arr => controller_cipo_arr,
- mux_mosi => controller_mem_mux_copi,
- mux_miso => controller_mem_mux_cipo
- );
+ generic map (
+ g_nof_masters => c_nof_controllers,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => controller_copi_arr,
+ master_miso_arr => controller_cipo_arr,
+ mux_mosi => controller_mem_mux_copi,
+ mux_miso => controller_mem_mux_cipo
+ );
---------------------------------------------------------------
-- REG_NOF_CROSSLETS
---------------------------------------------------------------
u_nof_crosslets : entity common_lib.mms_common_reg
- generic map(
- g_mm_reg => c_sdp_mm_reg_nof_crosslets
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- MM bus access in memory-mapped clock domain
- reg_mosi => reg_nof_crosslets_copi,
- reg_miso => reg_nof_crosslets_cipo,
-
- in_reg => nof_crosslets,
- out_reg => nof_crosslets_reg
- );
+ generic map(
+ g_mm_reg => c_sdp_mm_reg_nof_crosslets
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- MM bus access in memory-mapped clock domain
+ reg_mosi => reg_nof_crosslets_copi,
+ reg_miso => reg_nof_crosslets_cipo,
+
+ in_reg => nof_crosslets,
+ out_reg => nof_crosslets_reg
+ );
-- Force nof crosslets to max nof crosslets if a higher value is written or to 1 if a lower value is written via MM.
nof_crosslets <= TO_UVEC(1, c_sdp_nof_crosslets_reg_w) when TO_UINT(nof_crosslets_reg) < 1 else
@@ -451,49 +451,49 @@ begin
xst_udp_sosi <= mon_xst_udp_sosi_arr(0);
u_sdp_xst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "XST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
- g_P_sq => g_P_sq,
- g_crosslets_direction => 1, -- = lane direction
- g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "XST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
+ g_P_sq => g_P_sq,
+ g_crosslets_direction => 1, -- = lane direction
+ g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_copi,
- master_miso => ram_st_offload_cipo,
+ master_mosi => ram_st_offload_copi,
+ master_miso => ram_st_offload_cipo,
- reg_enable_mosi => reg_stat_enable_copi,
- reg_enable_miso => reg_stat_enable_cipo,
+ reg_enable_mosi => reg_stat_enable_copi,
+ reg_enable_miso => reg_stat_enable_cipo,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_cipo,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- in_sosi => crosslets_sosi,
- new_interval => new_interval,
+ in_sosi => crosslets_sosi,
+ new_interval => new_interval,
- out_sosi => mon_xst_udp_sosi_arr(0),
- out_siso => xst_udp_siso,
+ out_sosi => mon_xst_udp_sosi_arr(0),
+ out_siso => xst_udp_siso,
- eth_src_mac => stat_eth_src_mac,
- udp_src_port => stat_udp_src_port,
- ip_src_addr => stat_ip_src_addr,
+ eth_src_mac => stat_eth_src_mac,
+ udp_src_port => stat_udp_src_port,
+ ip_src_addr => stat_ip_src_addr,
- gn_index => TO_UINT(gn_id),
- ring_info => ring_info,
- sdp_info => sdp_info,
- weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ gn_index => TO_UINT(gn_id),
+ ring_info => ring_info,
+ sdp_info => sdp_info,
+ weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
- nof_crosslets => nof_crosslets, -- from MM
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ nof_crosslets => nof_crosslets, -- from MM
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index ca4473fed7..ccf83dbd6a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -53,16 +53,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, rTwoSDF_lib, fft_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use filter_lib.fil_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use filter_lib.fil_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_filterbank is
generic (
@@ -181,23 +181,23 @@ begin
-- SPECTRAL INVERSION
---------------------------------------------------------------
u_si_arr : entity si_lib.si_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_pipeline => c_si_pipeline,
- g_dat_w => c_sdp_W_adc
- )
- port map(
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => si_sosi_arr,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_pipeline => c_si_pipeline,
+ g_dat_w => c_sdp_W_adc
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => si_sosi_arr,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- POLY-PHASE FILTERBANK
@@ -214,42 +214,42 @@ begin
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_si_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart,
- out_dat => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_pipeline => c_si_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart,
+ out_dat => dp_bsn_source_restart_pipe
+ );
-- PFB
u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
-
- in_sosi_arr => wpfb_unit_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_wpfb => g_wpfb,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+
+ in_sosi_arr => wpfb_unit_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe
+ );
---------------------------------------------------------------
-- SUBBAND EQUALIZER
@@ -344,7 +344,7 @@ begin
-- SUBBAND STATISTICS
---------------------------------------------------------------
gen_stats_streams: for I in 0 to c_sdp_P_pfb - 1 generate
- u_subband_stats : entity st_lib.st_sst
+ u_subband_stats : entity st_lib.st_sst
generic map(
g_nof_stat => c_sdp_N_sub * c_sdp_Q_fft,
g_in_data_w => c_sdp_W_subband,
@@ -369,16 +369,16 @@ begin
-- Combine the internal array of mm interfaces for the subband
-- statistics to one array.
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_P_pfb,
- g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
- )
- port map (
- mosi => master_mem_mux_mosi,
- miso => master_mem_mux_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_P_pfb,
+ g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
+ )
+ port map (
+ mosi => master_mem_mux_mosi,
+ miso => master_mem_mux_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
+ );
-- Connect 2 mm_masters to the common_mem_mux output
master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
@@ -387,18 +387,18 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- STATISTICS OFFLOAD
@@ -406,42 +406,42 @@ begin
weighted_subbands_flag <= not selector_en when rising_edge(dp_clk);
u_sdp_sst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "SST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "SST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- in_sosi => dp_selector_quant_sosi_arr(0),
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => dp_selector_quant_sosi_arr(0),
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => sst_udp_sosi,
- out_siso => sst_udp_siso,
+ out_sosi => sst_udp_sosi,
+ out_siso => sst_udp_siso,
- eth_src_mac => eth_src_mac,
- udp_src_port => udp_src_port,
- ip_src_addr => ip_src_addr,
+ eth_src_mac => eth_src_mac,
+ udp_src_port => udp_src_port,
+ ip_src_addr => ip_src_addr,
- gn_index => TO_UINT(gn_id),
- sdp_info => sdp_info,
- weighted_subbands_flag => weighted_subbands_flag
- );
+ gn_index => TO_UINT(gn_id),
+ sdp_info => sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
index 93d3d21baf..541b361069 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
@@ -37,17 +37,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, rTwoSDF_lib, common_mult_lib, fft_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use filter_lib.fil_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use filter_lib.fil_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_oversampled_filterbank is
generic (
@@ -127,19 +127,27 @@ architecture str of node_sdp_oversampled_filterbank is
-- Use WG as local oscillator, buf contains 16b sin and 16b cos
-- . c_sdp_W_local_oscillator = 16b
-- . c_sdp_W_local_oscillator_fraction = 16b - 1 sign bit = 15b
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2 * c_sdp_N_fft),
- dat_w => c_nof_complex * c_sdp_W_local_oscillator,
- nof_dat => c_sdp_R_os * c_sdp_N_fft,
- init_sl => '0');
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2 * c_sdp_N_fft),
+ dat_w => c_nof_complex * c_sdp_W_local_oscillator,
+ nof_dat => c_sdp_R_os * c_sdp_N_fft,
+ init_sl => '0'
+ );
constant c_buf_file : string := "data/freq_shift_half_subband_2048x16_im_re.hex";
- constant c_wg_ctrl : t_diag_wg := (TO_UVEC(c_diag_wg_mode_repeat, c_diag_wg_mode_w),
- TO_UVEC(c_buf.nof_dat, c_diag_wg_nofsamples_w),
- (others => '0'),
- (others => '0'),
- (others => '0'));
+ constant c_wg_ctrl : t_diag_wg := (
+ TO_UVEC(
+ c_diag_wg_mode_repeat,
+ c_diag_wg_mode_w),
+ TO_UVEC(
+ c_buf.nof_dat,
+ c_diag_wg_nofsamples_w),
+ (others => '0'),
+ (others => '0'),
+ (others => '0')
+ );
constant c_wg_phase_offset : natural := 6; -- Compensate for WG start latency. In nof samples.
constant c_fil_coefs_mem_addr_w : natural := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
@@ -220,23 +228,23 @@ begin
-- SPECTRAL INVERSION
---------------------------------------------------------------
u_si_arr : entity si_lib.si_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_pipeline => c_si_pipeline,
- g_dat_w => c_sdp_W_adc
- )
- port map(
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => si_sosi_arr,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_pipeline => c_si_pipeline,
+ g_dat_w => c_sdp_W_adc
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => si_sosi_arr,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- POLY-PHASE FILTERBANK
@@ -254,42 +262,42 @@ begin
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_si_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart,
- out_dat => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_pipeline => c_si_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart,
+ out_dat => dp_bsn_source_restart_pipe
+ );
-- PFB
u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(0),
- ram_fil_coefs_miso => ram_fil_coefs_miso_arr(0),
-
- in_sosi_arr => wpfb_unit_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_wpfb => g_wpfb,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(0),
+ ram_fil_coefs_miso => ram_fil_coefs_miso_arr(0),
+
+ in_sosi_arr => wpfb_unit_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe
+ );
---------------------------------------------------------------
@@ -299,18 +307,18 @@ begin
-- real part is in LSB and imaginary part in MSB.
-- Waveform buffer
u_buf : entity common_lib.common_rom
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- rd_adr => wg_address,
- rd_en => wg_rd,
- rd_val => wg_rdval,
- rd_dat => wg_rddata
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ rd_adr => wg_address,
+ rd_en => wg_rd,
+ rd_val => wg_rdval,
+ rd_dat => wg_rddata
+ );
-- Waveform generator as local oscillator.
p_lo_restart : process(dp_clk, dp_rst)
@@ -331,101 +339,101 @@ begin
end process;
u_lo_wg : entity diag_lib.diag_wg
- generic map (
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w,
- g_rate_offset => c_wg_phase_offset,
- g_calc_support => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- restart => dp_bsn_source_restart_wg,
-
- buf_rddat => wg_rddata,
- buf_rdval => wg_rdval,
- buf_addr => wg_address,
- buf_rden => wg_rd,
-
- ctrl => c_wg_ctrl,
-
- out_dat => wg_out_dat,
- out_val => open
- );
-
- -- Complex mult
- gen_complex_mult: for I in 0 to c_sdp_S_pn - 1 generate
- u_common_complex_mult : entity common_mult_lib.common_complex_mult
generic map (
- g_in_a_w => c_sdp_W_local_oscillator, -- = 16
- g_in_b_w => c_sdp_W_adc, -- = 14
- g_out_p_w => c_sdp_W_local_oscillator + c_sdp_W_adc, -- = 16 + 14 = 30
- g_conjugate_b => false
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w,
+ g_rate_offset => c_wg_phase_offset,
+ g_calc_support => false
)
port map (
- clk => dp_clk,
- clken => '1',
- rst => dp_rst,
- in_ar => wg_out_dat(c_sdp_W_local_oscillator - 1 downto 0),
- in_ai => wg_out_dat(2 * c_sdp_W_local_oscillator - 1 downto c_sdp_W_local_oscillator),
- in_br => si_sosi_arr(I).data(c_sdp_W_adc - 1 downto 0),
- in_bi => (others => '0'),
- in_val => si_sosi_arr(I).valid,
- out_pr => mixer_complex_mult_src_out_arr(I).re(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
- out_pi => mixer_complex_mult_src_out_arr(I).im(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
- out_val => mixer_complex_mult_src_out_arr(I).valid
+ rst => dp_rst,
+ clk => dp_clk,
+ restart => dp_bsn_source_restart_wg,
+
+ buf_rddat => wg_rddata,
+ buf_rdval => wg_rdval,
+ buf_addr => wg_address,
+ buf_rden => wg_rd,
+
+ ctrl => c_wg_ctrl,
+
+ out_dat => wg_out_dat,
+ out_val => open
);
+ -- Complex mult
+ gen_complex_mult: for I in 0 to c_sdp_S_pn - 1 generate
+ u_common_complex_mult : entity common_mult_lib.common_complex_mult
+ generic map (
+ g_in_a_w => c_sdp_W_local_oscillator, -- = 16
+ g_in_b_w => c_sdp_W_adc, -- = 14
+ g_out_p_w => c_sdp_W_local_oscillator + c_sdp_W_adc, -- = 16 + 14 = 30
+ g_conjugate_b => false
+ )
+ port map (
+ clk => dp_clk,
+ clken => '1',
+ rst => dp_rst,
+ in_ar => wg_out_dat(c_sdp_W_local_oscillator - 1 downto 0),
+ in_ai => wg_out_dat(2 * c_sdp_W_local_oscillator - 1 downto c_sdp_W_local_oscillator),
+ in_br => si_sosi_arr(I).data(c_sdp_W_adc - 1 downto 0),
+ in_bi => (others => '0'),
+ in_val => si_sosi_arr(I).valid,
+ out_pr => mixer_complex_mult_src_out_arr(I).re(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
+ out_pi => mixer_complex_mult_src_out_arr(I).im(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
+ out_val => mixer_complex_mult_src_out_arr(I).valid
+ );
+
--requantize
u_dp_requantize : entity dp_lib.dp_requantize
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_local_oscillator_fraction,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 0,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_sdp_W_local_oscillator + c_sdp_W_adc,
+ g_out_dat_w => c_sdp_W_adc
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => mixer_complex_mult_src_out_arr(I),
+ -- ST source
+ src_out => mixer_complex_requantize_src_out_arr(I)
+ );
+ end generate;
+
+ -- Pipeline to compensate for complex mult and dp_requantize.
+ u_dp_pipeline : entity dp_lib.dp_pipeline
generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_local_oscillator_fraction,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 0,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_sdp_W_local_oscillator + c_sdp_W_adc,
- g_out_dat_w => c_sdp_W_adc
+ g_pipeline => c_complex_mult_pipeline
)
port map (
rst => dp_rst,
clk => dp_clk,
-- ST sink
- snk_in => mixer_complex_mult_src_out_arr(I),
+ snk_in => si_sosi_arr(0),
-- ST source
- src_out => mixer_complex_requantize_src_out_arr(I)
+ src_out => si_sosi_0_piped
);
- end generate;
-
- -- Pipeline to compensate for complex mult and dp_requantize.
- u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_complex_mult_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => si_sosi_arr(0),
- -- ST source
- src_out => si_sosi_0_piped
- );
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl_cplx : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_complex_mult_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart_pipe,
- out_dat => dp_bsn_source_restart_pipe_complex
- );
+ generic map (
+ g_pipeline => c_complex_mult_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart_pipe,
+ out_dat => dp_bsn_source_restart_pipe_complex
+ );
process(mixer_complex_requantize_src_out_arr, si_sosi_0_piped)
begin
for I in 0 to c_sdp_S_pn - 1 loop
@@ -437,30 +445,30 @@ begin
-- PFB complex
u_wpfb_unit_dev_complex : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb_complex,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(1),
- ram_fil_coefs_miso => ram_fil_coefs_miso_arr(1),
-
- in_sosi_arr => wpfb_unit_complex_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_complex_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_complex_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_complex_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe_complex
- );
+ generic map (
+ g_wpfb => g_wpfb_complex,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(1),
+ ram_fil_coefs_miso => ram_fil_coefs_miso_arr(1),
+
+ in_sosi_arr => wpfb_unit_complex_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_complex_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_complex_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_complex_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe_complex
+ );
---------------------------------------------------------------
-- Interleave for PFB complex
@@ -497,7 +505,7 @@ begin
snk_in => wpfb_complex_out_resized_sosi_arr(I),
src_out => wpfb_complex_out_fifo_sosi_arr(I),
src_in => wpfb_complex_out_fifo_siso_arr(I)
- );
+ );
end generate;
-- rewire 1d array of 1 X S_pn to 2d array of 2 X P_pfb
@@ -520,7 +528,7 @@ begin
snk_in_arr => wpfb_complex_out_resized_sosi_2arr(I),
snk_out_arr => wpfb_complex_out_resized_siso_2arr(I),
src_out => wpfb_complex_out_interleaved_sosi_arr(I)
- );
+ );
-- Align data width of wpfb_complex output with wpfb_real output as the real wpfb
-- has an extra bit that is used for the FFT seperate function which the complex FFT
@@ -554,16 +562,16 @@ begin
-- COMBINE MEMORY MAPPED INTERFACES OF RAM_FIL_COEFS
---------------------------------------------------------------
u_mem_mux_coef : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_R_os,
- g_mult_addr_w => c_fil_coefs_mem_addr_w
- )
- port map (
- mosi => ram_fil_coefs_mosi,
- miso => ram_fil_coefs_miso,
- mosi_arr => ram_fil_coefs_mosi_arr,
- miso_arr => ram_fil_coefs_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_R_os,
+ g_mult_addr_w => c_fil_coefs_mem_addr_w
+ )
+ port map (
+ mosi => ram_fil_coefs_mosi,
+ miso => ram_fil_coefs_miso,
+ mosi_arr => ram_fil_coefs_mosi_arr,
+ miso_arr => ram_fil_coefs_miso_arr
+ );
---------------------------------------------------------------
-- SUBBAND EQUALIZER
@@ -706,16 +714,16 @@ begin
-- Combine the internal array of mm interfaces for the subband
-- statistics to one array.
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_R_os * c_sdp_P_pfb,
- g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
- )
- port map (
- mosi => master_mem_mux_mosi,
- miso => master_mem_mux_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_R_os * c_sdp_P_pfb,
+ g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
+ )
+ port map (
+ mosi => master_mem_mux_mosi,
+ miso => master_mem_mux_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
+ );
-- Connect 2 mm_masters to the common_mem_mux output
master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
@@ -724,18 +732,18 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- STATISTICS OFFLOAD
@@ -743,42 +751,42 @@ begin
weighted_subbands_flag <= not selector_en when rising_edge(dp_clk);
u_sdp_sst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "SST_OS",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "SST_OS",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- in_sosi => dp_selector_out_sosi_arr(0),
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => dp_selector_out_sosi_arr(0),
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => sst_udp_sosi,
- out_siso => sst_udp_siso,
+ out_sosi => sst_udp_sosi,
+ out_siso => sst_udp_siso,
- eth_src_mac => eth_src_mac,
- udp_src_port => udp_src_port,
- ip_src_addr => ip_src_addr,
+ eth_src_mac => eth_src_mac,
+ udp_src_port => udp_src_port,
+ ip_src_addr => ip_src_addr,
- gn_index => TO_UINT(gn_id),
- sdp_info => sdp_info,
- weighted_subbands_flag => weighted_subbands_flag
- );
+ gn_index => TO_UINT(gn_id),
+ sdp_info => sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
index aabbc80077..06d358883e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
@@ -31,11 +31,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_beamformer_local is
generic (
@@ -137,17 +137,17 @@ begin
---------------------------------------------------------------
gen_deinterleave_x_pol : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_deinterleave_x_pol : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_nof_outputs => c_sdp_Q_fft
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_weights_x_sosi_arr(I),
- src_out_arr(0) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I),
- src_out_arr(1) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I + 1)
- );
+ generic map(
+ g_nof_outputs => c_sdp_Q_fft
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_weights_x_sosi_arr(I),
+ src_out_arr(0) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I),
+ src_out_arr(1) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I + 1)
+ );
end generate;
---------------------------------------------------------------
@@ -155,17 +155,17 @@ begin
---------------------------------------------------------------
gen_deinterleave_y_pol : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_deinterleave_y_pol : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_nof_outputs => c_sdp_Q_fft
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_weights_y_sosi_arr(I),
- src_out_arr(0) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I),
- src_out_arr(1) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I + 1)
- );
+ generic map(
+ g_nof_outputs => c_sdp_Q_fft
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_weights_y_sosi_arr(I),
+ src_out_arr(0) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I),
+ src_out_arr(1) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I + 1)
+ );
end generate;
---------------------------------------------------------------
@@ -173,48 +173,48 @@ begin
---------------------------------------------------------------
gen_interleave : for I in 0 to c_sdp_S_pn - 1 generate
u_dp_interleave : entity dp_lib.dp_interleave_n_to_one
+ generic map(
+ g_nof_inputs => c_sdp_N_pol_bf
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr(0) => deinterleaved_x_sosi_arr(I),
+ snk_in_arr(1) => deinterleaved_y_sosi_arr(I),
+ src_out => interleave_out_sosi_arr(I)
+ );
+ end generate;
+
+ ---------------------------------------------------------------
+ -- ADD
+ ---------------------------------------------------------------
+ u_dp_complex_add : entity dp_lib.dp_complex_add
generic map(
- g_nof_inputs => c_sdp_N_pol_bf
+ g_nof_inputs => c_sdp_S_pn,
+ g_data_w => c_product_w
)
port map(
rst => dp_rst,
clk => dp_clk,
- snk_in_arr(0) => deinterleaved_x_sosi_arr(I),
- snk_in_arr(1) => deinterleaved_y_sosi_arr(I),
- src_out => interleave_out_sosi_arr(I)
+ snk_in_arr => interleave_out_sosi_arr,
+ src_out => complex_add_out_sosi
);
- end generate;
-
- ---------------------------------------------------------------
- -- ADD
- ---------------------------------------------------------------
- u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_sdp_S_pn,
- g_data_w => c_product_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => interleave_out_sosi_arr,
- src_out => complex_add_out_sosi
- );
---------------------------------------------------------------
-- DP PIPELINE IN_SOSI FIELDS
---------------------------------------------------------------
u_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_total_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(0),
- src_out => pipelined_in_sosi
- );
+ generic map (
+ g_pipeline => c_total_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(0),
+ src_out => pipelined_in_sosi
+ );
---------------------------------------------------------------
-- COMBINE OUTPUT WITH PIPELINED IN_SOSI
@@ -230,26 +230,26 @@ begin
-- REQUANTIZE
---------------------------------------------------------------
u_dp_requantize : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_bf_weight_fraction + g_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false, -- wrap beamlet overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 0, -- no msb clipping, so no need for pipeline
- g_in_dat_w => c_complex_adder_sum_w,
- g_out_dat_w => c_sdp_W_beamlet_sum
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => dp_requantize_in_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_bf_weight_fraction + g_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false, -- wrap beamlet overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 0, -- no msb clipping, so no need for pipeline
+ g_in_dat_w => c_complex_adder_sum_w,
+ g_out_dat_w => c_sdp_W_beamlet_sum
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => dp_requantize_in_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
index 2ba6c2fb7a..031a1c2477 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
@@ -31,20 +31,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_beamformer_output is
generic (
g_beamset_id : natural := 0
- );
+ );
port (
dp_clk : in std_logic;
dp_rst : in std_logic;
@@ -151,7 +151,7 @@ begin
dbg_bsn_offset <= '1';
snk_in_concat.bsn <= INCR_UVEC(in_sosi.bsn, 1);
end if;
- -- synthesis translate_on
+ -- synthesis translate_on
end process;
-------------------------------------------------------------------------------
@@ -160,64 +160,64 @@ begin
-- . We don't need to flow control the source because we're going from 16b->64b
-------------------------------------------------------------------------------
u_dp_repack_data : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => 4,
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 1
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in => snk_in_concat,
- snk_out => OPEN,
-
- src_out => dp_repack_data_src_out,
- src_in => c_dp_siso_rdy
- );
+ generic map (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => 4,
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 1
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in => snk_in_concat,
+ snk_out => OPEN,
+
+ src_out => dp_repack_data_src_out,
+ src_in => c_dp_siso_rdy
+ );
-------------------------------------------------------------------------------
-- dp_packet_merge
-------------------------------------------------------------------------------
u_dp_packet_merge : entity dp_lib.dp_packet_merge
- generic map(
- g_nof_pkt => c_sdp_cep_nof_blocks_per_packet,
- g_bsn_increment => 1
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => OPEN,
- snk_in => dp_repack_data_src_out,
-
- src_in => c_dp_siso_rdy,
- src_out => dp_packet_merge_src_out
- );
+ generic map(
+ g_nof_pkt => c_sdp_cep_nof_blocks_per_packet,
+ g_bsn_increment => 1
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => OPEN,
+ snk_in => dp_repack_data_src_out,
+
+ src_in => c_dp_siso_rdy,
+ src_out => dp_packet_merge_src_out
+ );
-------------------------------------------------------------------------------
-- FIFO
-------------------------------------------------------------------------------
u_dp_fifo_fill_eop_sc : entity dp_lib.dp_fifo_fill_eop_sc
- generic map ( -- pass on dp_packet_merge_src_out.err via u_common_fifo_sc_err
- g_data_w => c_longword_w,
- g_empty_w => c_byte_w,
- g_use_empty => true,
- g_use_bsn => true,
- g_bsn_w => 64,
- g_use_sync => true,
- g_fifo_size => c_fifo_size,
- g_fifo_fill => c_fifo_fill,
- g_fifo_rl => 1
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
- snk_in => dp_packet_merge_src_out,
- src_out => dp_fifo_merge_src_out,
- src_in => dp_fifo_merge_src_in
- );
+ generic map ( -- pass on dp_packet_merge_src_out.err via u_common_fifo_sc_err
+ g_data_w => c_longword_w,
+ g_empty_w => c_byte_w,
+ g_use_empty => true,
+ g_use_bsn => true,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_fifo_size => c_fifo_size,
+ g_fifo_fill => c_fifo_fill,
+ g_fifo_rl => 1
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+ snk_in => dp_packet_merge_src_out,
+ src_out => dp_fifo_merge_src_out,
+ src_in => dp_fifo_merge_src_in
+ );
-- Simple fifo to store the payload error bit at eop of FIFO input to be used at sop of FIFO
-- output, so that payload_err can then be used in the packet header.
@@ -225,34 +225,34 @@ begin
-- Choose g_nof_words > c_sdp_N_beamsets to have some margin compared to c_fifo_size of the
-- data FIFO.
u_common_fifo_sc_err : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => 1,
- g_nof_words => c_sdp_N_beamsets + 2
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_dat => dp_packet_merge_src_out.err(0 downto 0),
- wr_req => dp_packet_merge_src_out.eop,
- rd_dat => payload_err,
- rd_req => dp_fifo_merge_src_out.sop
- );
+ generic map (
+ g_dat_w => 1,
+ g_nof_words => c_sdp_N_beamsets + 2
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_dat => dp_packet_merge_src_out.err(0 downto 0),
+ wr_req => dp_packet_merge_src_out.eop,
+ rd_dat => payload_err,
+ rd_req => dp_fifo_merge_src_out.sop
+ );
-- Pipeline FIFO output to align payload_err at dp_pipeline_src_out.sop
u_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => dp_fifo_merge_src_in,
- snk_in => dp_fifo_merge_src_out,
- -- ST source
- src_in => dp_pipeline_src_in,
- src_out => dp_pipeline_src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => dp_fifo_merge_src_in,
+ snk_in => dp_fifo_merge_src_out,
+ -- ST source
+ src_in => dp_pipeline_src_in,
+ src_out => dp_pipeline_src_out
+ );
-------------------------------------------------------------------------------
-- Assemble offload info
@@ -344,88 +344,88 @@ begin
-- dp_offload_tx_v3
-------------------------------------------------------------------------------
u_dp_offload_tx_v3 : entity dp_lib.dp_offload_tx_v3
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_byte_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_hdr_field_sel => c_sdp_cep_hdr_field_sel,
- g_pipeline_ready => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
-
- snk_in_arr(0) => dp_pipeline_src_out,
- snk_out_arr(0) => dp_pipeline_src_in,
-
- src_out_arr(0) => dp_offload_tx_src_out,
- src_in_arr(0) => dp_offload_tx_src_in,
-
- hdr_fields_in_arr(0) => dp_offload_tx_hdr_fields,
- hdr_fields_out_arr(0) => hdr_fields_out
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_hdr_field_sel => c_sdp_cep_hdr_field_sel,
+ g_pipeline_ready => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+
+ snk_in_arr(0) => dp_pipeline_src_out,
+ snk_out_arr(0) => dp_pipeline_src_in,
+
+ src_out_arr(0) => dp_offload_tx_src_out,
+ src_in_arr(0) => dp_offload_tx_src_in,
+
+ hdr_fields_in_arr(0) => dp_offload_tx_hdr_fields,
+ hdr_fields_out_arr(0) => hdr_fields_out
+ );
-------------------------------------------------------------------------------
-- tr_10GbE_ip_checksum
-------------------------------------------------------------------------------
u_tr_10GbE_ip_checksum : entity tr_10GbE_lib.tr_10GbE_ip_checksum
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in => dp_offload_tx_src_out,
- snk_out => dp_offload_tx_src_in,
+ snk_in => dp_offload_tx_src_out,
+ snk_out => dp_offload_tx_src_in,
- src_out => ip_checksum_src_out,
- src_in => ip_checksum_src_in
- );
+ src_out => ip_checksum_src_out,
+ src_in => ip_checksum_src_in
+ );
-------------------------------------------------------------------------------
-- dp_pipeline_ready to ease timing closure
-------------------------------------------------------------------------------
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => ip_checksum_src_in,
- snk_in => ip_checksum_src_out,
- src_in => dp_pipeline_ready_src_in,
- src_out => dp_pipeline_ready_src_out
- );
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => ip_checksum_src_in,
+ snk_in => ip_checksum_src_out,
+ src_in => dp_pipeline_ready_src_in,
+ src_out => dp_pipeline_ready_src_out
+ );
-------------------------------------------------------------------------------
-- mms_dp_xonoff
-------------------------------------------------------------------------------
u_mms_dp_xonoff : entity dp_lib.mms_dp_xonoff
- generic map(
- g_default_value => '0'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_mosi,
- reg_miso => reg_dp_xonoff_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- ST sinks
- snk_out_arr(0) => dp_pipeline_ready_src_in,
- snk_in_arr(0) => dp_pipeline_ready_src_out,
- -- ST source
- src_in_arr(0) => out_siso,
- src_out_arr(0) => out_sosi
- );
+ generic map(
+ g_default_value => '0'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_mosi,
+ reg_miso => reg_dp_xonoff_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- ST sinks
+ snk_out_arr(0) => dp_pipeline_ready_src_in,
+ snk_in_arr(0) => dp_pipeline_ready_src_out,
+ -- ST source
+ src_in_arr(0) => out_siso,
+ src_out_arr(0) => out_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
index 4d917a2a77..4f386530e5 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
@@ -30,11 +30,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_beamformer_remote is
port (
@@ -90,84 +90,84 @@ begin
-- FIFO
---------------------------------------------------------------
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_longword_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => from_ri_sosi,
- src_in => dp_fifo_siso,
- src_out => dp_fifo_sosi
- );
+ generic map (
+ g_data_w => c_longword_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => from_ri_sosi,
+ src_in => dp_fifo_siso,
+ src_out => dp_fifo_sosi
+ );
---------------------------------------------------------------
-- Repack 64b to 36b
---------------------------------------------------------------
u_dp_repack_data_rx : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_longword_w,
- g_in_nof_words => 9, -- 9/16 = 36/64
- g_out_dat_w => c_data_w,
- g_out_nof_words => 16, -- 9/16 = 36/64
- g_pipeline_ready => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_sosi,
- snk_out => dp_fifo_siso,
- src_out => dispatch_sosi_arr(1)
- );
+ generic map (
+ g_in_dat_w => c_longword_w,
+ g_in_nof_words => 9, -- 9/16 = 36/64
+ g_out_dat_w => c_data_w,
+ g_out_nof_words => 16, -- 9/16 = 36/64
+ g_pipeline_ready => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_sosi,
+ snk_out => dp_fifo_siso,
+ src_out => dispatch_sosi_arr(1)
+ );
---------------------------------------------------------------
-- dp_bsn_aligner_v2
---------------------------------------------------------------
u_mmp_dp_bsn_align_v2 : entity dp_lib.mmp_dp_bsn_align_v2
- generic map(
- -- for dp_bsn_align_v2
- g_nof_streams => c_dual,
- g_bsn_latency_max => 2, -- max 2 blocks latency
- g_nof_aligners_max => c_sdp_N_pn_max,
- g_block_size => c_block_size,
- g_data_w => c_data_w,
- g_use_mm_output => false,
- g_rd_latency => 1,
- -- for mms_dp_bsn_monitor_v2
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
- g_nof_input_bsn_monitors => c_dual,
- g_use_bsn_output_monitor => true
+ generic map(
+ -- for dp_bsn_align_v2
+ g_nof_streams => c_dual,
+ g_bsn_latency_max => 2, -- max 2 blocks latency
+ g_nof_aligners_max => c_sdp_N_pn_max,
+ g_block_size => c_block_size,
+ g_data_w => c_data_w,
+ g_use_mm_output => false,
+ g_rd_latency => 1,
+ -- for mms_dp_bsn_monitor_v2
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_input_bsn_monitors => c_dual,
+ g_use_bsn_output_monitor => true
)
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
- reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+ reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
- reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
+ reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- node_index => rn_index,
+ node_index => rn_index,
- -- Streaming input
- in_sosi_arr => dispatch_sosi_arr,
- out_sosi_arr => beamlets_data_sosi_arr
- );
+ -- Streaming input
+ in_sosi_arr => dispatch_sosi_arr,
+ out_sosi_arr => beamlets_data_sosi_arr
+ );
-- repacking beamlets data to re/im field.
p_wire_beamlets_sosi : process(beamlets_data_sosi_arr)
@@ -185,17 +185,17 @@ begin
-- ADD local + remote
---------------------------------------------------------------
u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_dual,
- g_data_w => c_sdp_W_beamlet_sum
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => beamlets_sosi_arr,
- src_out => i_bf_sum_sosi
- );
+ generic map(
+ g_nof_inputs => c_dual,
+ g_data_w => c_sdp_W_beamlet_sum
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => beamlets_sosi_arr,
+ src_out => i_bf_sum_sosi
+ );
---------------------------------------------------------------
@@ -216,19 +216,19 @@ begin
end process;
u_dp_repack_data_local : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => 16, -- 16/9 = 64/36
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 9, -- 16/9 = 64/36
- g_pipeline_ready => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_sum_data_sosi,
- src_out => to_ri_sosi
- );
+ generic map (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => 16, -- 16/9 = 64/36
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 9, -- 16/9 = 64/36
+ g_pipeline_ready => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_sum_data_sosi,
+ src_out => to_ri_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index 471c8c4f09..5034b0effa 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -35,11 +35,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_bf_weights is
generic (
@@ -121,32 +121,32 @@ begin
-- Gain
---------------------------------------------------------------
u_mms_dp_gain_serial_arr : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => c_sdp_N_pol_bf * c_sdp_P_pfb,
- g_nof_gains => c_sdp_Q_fft * c_sdp_S_sub_bf,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_bf_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_sdp_N_pol_bf * c_sdp_P_pfb,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_S_sub_bf,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_bf_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => g_gains_file_name
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address,
+
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 9482e28ea7..0a55e0a16c 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -45,12 +45,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_crosslets_subband_select is
generic (
@@ -133,48 +133,48 @@ begin
-- BSN sync scheduler
---------------------------------------------------------------
u_mmp_dp_bsn_sync_scheduler_arr : entity dp_lib.mmp_dp_bsn_sync_scheduler_arr
- generic map (
- g_nof_streams => c_sdp_P_pfb,
- g_block_size => c_sdp_N_fft,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_miso => reg_bsn_sync_scheduler_xsub_miso,
-
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
-
- out_start => start_trigger,
- out_start_interval => new_interval
- );
+ generic map (
+ g_nof_streams => c_sdp_P_pfb,
+ g_block_size => c_sdp_N_fft,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_miso => reg_bsn_sync_scheduler_xsub_miso,
+
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
+
+ out_start => start_trigger,
+ out_start_interval => new_interval
+ );
---------------------------------------------------------------
-- Crosslets info
---------------------------------------------------------------
u_crosslets_info : entity common_lib.mms_common_reg
- generic map(
- g_mm_reg => c_sdp_mm_reg_crosslets_info
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- MM bus access in memory-mapped clock domain
- reg_mosi => reg_crosslets_info_mosi,
- reg_miso => reg_crosslets_info_miso,
-
- in_reg => crosslets_info_reg_in,
- out_reg => crosslets_info_reg
- );
+ generic map(
+ g_mm_reg => c_sdp_mm_reg_crosslets_info
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- MM bus access in memory-mapped clock domain
+ reg_mosi => reg_crosslets_info_mosi,
+ reg_miso => reg_crosslets_info_miso,
+
+ in_reg => crosslets_info_reg_in,
+ out_reg => crosslets_info_reg
+ );
p_set_unused_crosslets : process(cur_crosslets_info)
begin
@@ -269,62 +269,62 @@ begin
col_select_mosi <= r.col_select_mosi;
-- pipeline to time row select
u_pipe_row_select : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_row_select_pipeline,
- g_in_dat_w => c_row_select_slv_w,
- g_out_dat_w => c_row_select_slv_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_dat => r.row_select_slv,
- out_dat => row_select_slv
- );
+ generic map(
+ g_pipeline => c_row_select_pipeline,
+ g_in_dat_w => c_row_select_slv_w,
+ g_out_dat_w => c_row_select_slv_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => r.row_select_slv,
+ out_dat => row_select_slv
+ );
---------------------------------------------------------------
-- Crosslet Select
---------------------------------------------------------------
u_reorder_col_wide_select : entity reorder_lib.reorder_col_wide_select
- generic map (
- g_nof_inputs => c_sdp_P_pfb,
- g_dsp_data_w => c_sdp_W_crosslet,
- g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
- g_nof_ch_sel => g_N_crosslets * c_sdp_S_pn
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- col_select_mosi => col_select_mosi,
- col_select_miso => col_select_miso,
-
- -- Streaming
- input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
-
- output_sosi_arr => col_sosi_arr
- );
+ generic map (
+ g_nof_inputs => c_sdp_P_pfb,
+ g_dsp_data_w => c_sdp_W_crosslet,
+ g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
+ g_nof_ch_sel => g_N_crosslets * c_sdp_S_pn
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ col_select_mosi => col_select_mosi,
+ col_select_miso => col_select_miso,
+
+ -- Streaming
+ input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
+
+ output_sosi_arr => col_sosi_arr
+ );
u_reorder_row_select : entity reorder_lib.reorder_row_select
- generic map (
- g_dsp_data_w => c_sdp_W_crosslet,
- g_nof_inputs => c_sdp_P_pfb,
- g_nof_outputs => 1,
- g_pipeline_in => 0,
- g_pipeline_in_m => 1,
- g_pipeline_out => 1
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_select => row_select_slv,
-
- -- Streaming
- input_sosi_arr => col_sosi_arr,
-
- output_sosi_arr(0) => row_sosi
- );
+ generic map (
+ g_dsp_data_w => c_sdp_W_crosslet,
+ g_nof_inputs => c_sdp_P_pfb,
+ g_nof_outputs => 1,
+ g_pipeline_in => 0,
+ g_pipeline_in_m => 1,
+ g_pipeline_out => 1
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_select => row_select_slv,
+
+ -- Streaming
+ input_sosi_arr => col_sosi_arr,
+
+ output_sosi_arr(0) => row_sosi
+ );
---------------------------------------------------------------
-- Out Crosslet info pipeline
@@ -336,48 +336,48 @@ begin
-- pipeline for alignment with sync
u_common_pipeline_cur : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_crosslets_info_dly,
- g_in_dat_w => c_sdp_crosslets_info_reg_w,
- g_out_dat_w => c_sdp_crosslets_info_reg_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_en => row_sosi.sync,
- in_dat => active_crosslets_info,
- out_dat => cur_crosslets_info
- );
+ generic map(
+ g_pipeline => c_crosslets_info_dly,
+ g_in_dat_w => c_sdp_crosslets_info_reg_w,
+ g_out_dat_w => c_sdp_crosslets_info_reg_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_en => row_sosi.sync,
+ in_dat => active_crosslets_info,
+ out_dat => cur_crosslets_info
+ );
u_common_pipeline_prev : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_crosslets_info_dly,
- g_in_dat_w => c_sdp_crosslets_info_reg_w,
- g_out_dat_w => c_sdp_crosslets_info_reg_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_en => row_sosi.sync,
- in_dat => cur_crosslets_info,
- out_dat => prev_crosslets_info
- );
+ generic map(
+ g_pipeline => c_crosslets_info_dly,
+ g_in_dat_w => c_sdp_crosslets_info_reg_w,
+ g_out_dat_w => c_sdp_crosslets_info_reg_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_en => row_sosi.sync,
+ in_dat => cur_crosslets_info,
+ out_dat => prev_crosslets_info
+ );
---------------------------------------------------------------
-- Out sosi pipeline
---------------------------------------------------------------
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_out_sosi_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => row_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => c_out_sosi_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => row_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
-- Map crosslets_info slv to record for easier view in Wave window
crosslets_info_rec <= func_sdp_map_crosslets_info(crosslets_info_reg);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
index ef69b79c2b..f236eb0aee 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_info is
port (
@@ -69,21 +69,21 @@ architecture str of sdp_info is
begin
u_mm_fields: entity work.sdp_info_reg
- port map (
+ port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
- -- sdp info
- sdp_info_ro => sdp_info_ro,
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info_ro => sdp_info_ro,
+ sdp_info => sdp_info
+ );
-- f_adc : '0' => 160M, '1' => 200M
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
index dfd62b3ff6..f5027800c3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_info_reg is
port (
@@ -61,15 +61,15 @@ end sdp_info_reg;
architecture str of sdp_info_reg is
constant c_field_arr : t_common_field_arr(8 downto 0) :=
- ( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)), -- = station_info[15:10]
- (field_name_pad("station_id"), "RW", 10, field_default(0)), -- = station_info[9:0]
- (field_name_pad("antenna_band_index"), "RW", 1, field_default(0)),
- (field_name_pad("observation_id"), "RW", 32, field_default(0)),
- (field_name_pad("nyquist_zone_index"), "RW", 2, field_default(0)),
- (field_name_pad("f_adc"), "RO", 1, field_default(0)),
- (field_name_pad("fsub_type"), "RO", 1, field_default(0)),
- (field_name_pad("beam_repositioning_flag"), "RW", 1, field_default(0)),
- (field_name_pad("block_period"), "RO", 16, field_default(0)) );
+ ( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)), -- = station_info[15:10]
+ (field_name_pad("station_id"), "RW", 10, field_default(0)), -- = station_info[9:0]
+ (field_name_pad("antenna_band_index"), "RW", 1, field_default(0)),
+ (field_name_pad("observation_id"), "RW", 32, field_default(0)),
+ (field_name_pad("nyquist_zone_index"), "RW", 2, field_default(0)),
+ (field_name_pad("f_adc"), "RO", 1, field_default(0)),
+ (field_name_pad("fsub_type"), "RO", 1, field_default(0)),
+ (field_name_pad("beam_repositioning_flag"), "RW", 1, field_default(0)),
+ (field_name_pad("block_period"), "RO", 16, field_default(0)) );
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -94,25 +94,25 @@ begin
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in => mm_fields_in,
- slv_in_val => '1',
+ slv_in => mm_fields_in,
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
-- add "RO" fields to mm_fields
mm_fields_in(field_hi(c_field_arr, "f_adc") downto field_lo(c_field_arr, "f_adc")) <= slv(sdp_info_rd.f_adc);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index cae9604c18..6c45b848a9 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -28,18 +28,18 @@
-- . [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+SDP+Parameter+definitions
-------------------------------------------------------------------------------
library IEEE, common_lib, rTwoSDF_lib, fft_lib, filter_lib, wpfb_lib, diag_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use diag_lib.diag_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use fft_lib.fft_pkg.all;
-use filter_lib.fil_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use tech_jesd204b_lib.tech_jesd204b_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use fft_lib.fft_pkg.all;
+ use filter_lib.fil_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use tech_jesd204b_lib.tech_jesd204b_pkg.all;
package sdp_pkg is
-------------------------------------------------
@@ -58,10 +58,17 @@ package sdp_pkg is
block_period : std_logic_vector(15 downto 0);
end record;
- constant c_sdp_info_rst : t_sdp_info :=
- ( (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
- '0', '0', '0',
- (others => '0') );
+ constant c_sdp_info_rst : t_sdp_info := (
+ (others => '0'),
+ (others => '0'),
+ '0',
+ (others => '0'),
+ (others => '0'),
+ '0',
+ '0',
+ '0',
+ (others => '0')
+ );
-------------------------------------------------
-- SDP specific parameters as defined in [1]
@@ -217,13 +224,32 @@ package sdp_pkg is
constant c_sdp_W_fft_out_gain : natural := 2;
constant c_sdp_W_stat_data : natural := c_sdp_W_subband * 2 + ceil_log2(c_sdp_N_int_sub_hi); -- = 54
- constant c_sdp_wpfb_subbands : t_wpfb :=
- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
- c_sdp_N_taps, c_sdp_W_fil_backoff, c_sdp_W_adc, c_sdp_W_fft_in_dat, c_sdp_W_fir_coef,
- true, false, true,
- c_sdp_W_fft_in_dat, c_sdp_W_subband, c_sdp_W_fft_out_gain, c_sdp_W_fft_stage_dat, c_sdp_W_fft_guard, true,
- c_sdp_W_stat_data, c_sdp_W_statistic_sz, c_sdp_N_int_sub_hi,
- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_l2ts_18b
+ constant c_sdp_wpfb_subbands : t_wpfb := (
+ 1,
+ c_sdp_N_fft,
+ 0,
+ c_sdp_P_pfb,
+ c_sdp_N_taps,
+ c_sdp_W_fil_backoff,
+ c_sdp_W_adc,
+ c_sdp_W_fft_in_dat,
+ c_sdp_W_fir_coef,
+ true,
+ false,
+ true,
+ c_sdp_W_fft_in_dat,
+ c_sdp_W_subband,
+ c_sdp_W_fft_out_gain,
+ c_sdp_W_fft_stage_dat,
+ c_sdp_W_fft_guard,
+ true,
+ c_sdp_W_stat_data,
+ c_sdp_W_statistic_sz,
+ c_sdp_N_int_sub_hi,
+ c_fft_pipeline,
+ c_fft_pipeline,
+ c_fil_ppf_pipeline
+ ); -- = c_wpfb_lofar2_subbands_l2ts_18b
constant c_sdp_wpfb_complex_subbands : t_wpfb := func_wpfb_map_real_input_wpfb_parameters_to_complex_input(c_sdp_wpfb_subbands);
@@ -286,58 +312,58 @@ package sdp_pkg is
-- and default hdr_fields_in_arr = 0 or via MM controlled and field_default(0).
-- eth ip udp app
constant c_sdp_stat_hdr_field_sel : std_logic_vector(c_sdp_stat_nof_hdr_fields - 1 downto 0) := "1" & "101" & "111011111001" & "0100" & "0100" & "00000000" & "1000000" & "0"; -- current
---CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111011111001"&"0101"&"0100"&"00000000"&"0000100"&"0"; -- previous 26 nov 2021
---CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"00000000"&"1000000"&"0"; -- initial
+ --CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111011111001"&"0101"&"0100"&"00000000"&"0000100"&"0"; -- previous 26 nov 2021
+ --CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"00000000"&"1000000"&"0"; -- initial
-- Default use destination MAC/IP/UDP = 0, so these have to be MM programmed before
-- statistics offload packets can be send.
constant c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("word_align" ), "RW", 16, field_default(0) ), -- Tx TSE IP will strip these 2 padding bytes
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_stat_eth_dst_mac
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
-
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_stat_ip_dst_addr
-
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_stat_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ), -- differs for SST, BST, XST so set by data path
- ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_stat_version_id) ),
- ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
- ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_beam_repositioning_flag" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_weighted_subbands_flag" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_gn_id" ), "RW", 8, field_default(0) ),
-
- ( field_name_pad("sdp_reserved" ), "RW", 8, field_default(0) ),
- ( field_name_pad("sdp_integration_interval" ), "RW", 24, field_default(0) ),
- ( field_name_pad("sdp_data_id" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_nof_signal_inputs" ), "RW", 8, field_default(0) ),
- ( field_name_pad("sdp_nof_bytes_per_statistic" ), "RW", 8, field_default(c_sdp_nof_bytes_per_statistic) ),
- ( field_name_pad("sdp_nof_statistics_per_packet" ), "RW", 16, field_default(0) ),
- ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
-
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
+ ( field_name_pad("word_align" ), "RW", 16, field_default(0) ), -- Tx TSE IP will strip these 2 padding bytes
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_stat_eth_dst_mac
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_stat_ip_dst_addr
+
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_stat_udp_dst_port
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ), -- differs for SST, BST, XST so set by data path
+ ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_stat_version_id) ),
+ ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
+ ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_beam_repositioning_flag" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_weighted_subbands_flag" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_gn_id" ), "RW", 8, field_default(0) ),
+
+ ( field_name_pad("sdp_reserved" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("sdp_integration_interval" ), "RW", 24, field_default(0) ),
+ ( field_name_pad("sdp_data_id" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_nof_signal_inputs" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("sdp_nof_bytes_per_statistic" ), "RW", 8, field_default(c_sdp_nof_bytes_per_statistic) ),
+ ( field_name_pad("sdp_nof_statistics_per_packet" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
+
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
);
constant c_sdp_reg_stat_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
@@ -419,57 +445,57 @@ package sdp_pkg is
-- Remarks: see remarks at c_sdp_stat_nof_hdr_fields.
-- eth ip udp app
constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" & "111111111011" & "1110" & "1100" & "100000010" & "100110" & "0"; -- current
---CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"100000010"&"000110"&"0"; -- previous 27 sep 2022
---CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"100000000"&"101000"&"0"; -- initial
+ --CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"100000010"&"000110"&"0"; -- previous 27 sep 2022
+ --CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"100000000"&"101000"&"0"; -- initial
-- Default use source MAC/IP/UDP = 0 and destination MAC/IP/UDP = 0, so these have to be MM programmed
-- before beamlet output packets can be send.
constant c_sdp_cep_hdr_field_arr : t_common_field_arr(c_sdp_cep_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_cep_eth_dst_mac
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
-
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(c_sdp_cep_ip_total_length) ),
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_cep_ip_dst_addr
-
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_cep_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(c_sdp_cep_udp_total_length) ),
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("sdp_marker" ), "RW", 8, field_default(c_sdp_marker_beamlets) ),
- ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_cep_version_id) ),
- ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("sdp_source_info_reserved" ), "RW", 5, field_default(0) ),
- ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
- ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_beam_repositioning_flag"), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_beamlet_width" ), "RW", 4, field_default(c_sdp_W_beamlet) ),
- ( field_name_pad("sdp_source_info_gn_id" ), "RW", 8, field_default(0) ),
-
- ( field_name_pad("sdp_reserved" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_beamlet_scale" ), "RW", 16, field_default(c_sdp_unit_beamlet_scale) ),
- ( field_name_pad("sdp_beamlet_index" ), "RW", 16, field_default(0) ),
- ( field_name_pad("sdp_nof_blocks_per_packet" ), "RW", 8, field_default(c_sdp_cep_nof_blocks_per_packet) ),
- ( field_name_pad("sdp_nof_beamlets_per_block" ), "RW", 16, field_default(c_sdp_cep_nof_beamlets_per_block) ),
- ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
-
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_cep_eth_dst_mac
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(c_sdp_cep_ip_total_length) ),
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_sdp_cep_ip_dst_addr
+
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_sdp_cep_udp_dst_port
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(c_sdp_cep_udp_total_length) ),
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_marker" ), "RW", 8, field_default(c_sdp_marker_beamlets) ),
+ ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(c_sdp_cep_version_id) ),
+ ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_station_info" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_source_info_reserved" ), "RW", 5, field_default(0) ),
+ ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
+ ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_beam_repositioning_flag"), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_beamlet_width" ), "RW", 4, field_default(c_sdp_W_beamlet) ),
+ ( field_name_pad("sdp_source_info_gn_id" ), "RW", 8, field_default(0) ),
+
+ ( field_name_pad("sdp_reserved" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_beamlet_scale" ), "RW", 16, field_default(c_sdp_unit_beamlet_scale) ),
+ ( field_name_pad("sdp_beamlet_index" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("sdp_nof_blocks_per_packet" ), "RW", 8, field_default(c_sdp_cep_nof_blocks_per_packet) ),
+ ( field_name_pad("sdp_nof_beamlets_per_block" ), "RW", 16, field_default(c_sdp_cep_nof_beamlets_per_block) ),
+ ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
+
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
);
constant c_sdp_reg_cep_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
@@ -520,11 +546,13 @@ package sdp_pkg is
-- JESD204B
constant c_sdp_jesd204b_freq : string := "200MHz";
- constant c_sdp_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0'); -- PIO_JESD_CTRL
+ constant c_sdp_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0'
+ ); -- PIO_JESD_CTRL
-- AIT MM address widths
constant c_sdp_jesd204b_addr_w : natural := ceil_log2(c_sdp_S_pn) + tech_jesd204b_port_span_w; -- = 4 + 8
@@ -575,11 +603,13 @@ package sdp_pkg is
-- XSUB
constant c_sdp_crosslets_index_w : natural := ceil_log2(c_sdp_N_sub);
- constant c_sdp_mm_reg_crosslets_info : t_c_mem := (latency => 1,
- adr_w => 4,
- dat_w => c_sdp_crosslets_index_w,
- nof_dat => 16, -- 15 offsets + 1 step
- init_sl => '0');
+ constant c_sdp_mm_reg_crosslets_info : t_c_mem := (
+ latency => 1,
+ adr_w => 4,
+ dat_w => c_sdp_crosslets_index_w,
+ nof_dat => 16, -- 15 offsets + 1 step
+ init_sl => '0'
+ );
constant c_sdp_crosslets_info_reg_w : natural := c_sdp_mm_reg_crosslets_info.nof_dat * c_sdp_mm_reg_crosslets_info.dat_w;
constant c_sdp_crosslets_info_nof_offsets : natural := c_sdp_mm_reg_crosslets_info.nof_dat - 1;
@@ -590,11 +620,13 @@ package sdp_pkg is
constant c_sdp_crosslets_info_rst : t_sdp_crosslets_info := (offset_arr => (others => 0), step => 0);
- constant c_sdp_mm_reg_nof_crosslets : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => ceil_log2(c_sdp_N_crosslets_max + 1),
- nof_dat => 1,
- init_sl => '0'); -- Default = 1
+ constant c_sdp_mm_reg_nof_crosslets : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => ceil_log2(c_sdp_N_crosslets_max + 1),
+ nof_dat => 1,
+ init_sl => '0'
+ ); -- Default = 1
constant c_sdp_nof_crosslets_reg_w : natural := c_sdp_mm_reg_nof_crosslets.nof_dat * c_sdp_mm_reg_nof_crosslets.dat_w;
constant c_sdp_xst_nof_clk_per_sync_min : natural := c_sdp_N_clk_per_sync / 10; -- 0.1 second
@@ -647,41 +679,41 @@ package sdp_pkg is
-- SDP functions
-------------------------------------------------
- function func_sdp_gn_index_to_pn_index(gn_index : natural) return natural;
- function func_sdp_modulo_N_sub(sub_index : natural) return natural;
+ function func_sdp_gn_index_to_pn_index (gn_index : natural) return natural;
+ function func_sdp_modulo_N_sub (sub_index : natural) return natural;
- function func_sdp_get_stat_marker(g_statistics_type : string) return natural;
- function func_sdp_get_stat_nof_signal_inputs(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_marker (g_statistics_type : string) return natural;
+ function func_sdp_get_stat_nof_signal_inputs (g_statistics_type : string) return natural;
-- nof_statistics_per_packet = mm_nof_data * mm_data_size / c_sdp_W_statistic_sz
- function func_sdp_get_stat_from_mm_user_size(g_statistics_type : string) return natural;
- function func_sdp_get_stat_from_mm_data_size(g_statistics_type : string) return natural;
- function func_sdp_get_stat_from_mm_step_size(g_statistics_type : string) return natural;
- function func_sdp_get_stat_from_mm_nof_data(g_statistics_type : string) return natural;
- function func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_from_mm_user_size (g_statistics_type : string) return natural;
+ function func_sdp_get_stat_from_mm_data_size (g_statistics_type : string) return natural;
+ function func_sdp_get_stat_from_mm_step_size (g_statistics_type : string) return natural;
+ function func_sdp_get_stat_from_mm_nof_data (g_statistics_type : string) return natural;
+ function func_sdp_get_stat_nof_statistics_per_packet (g_statistics_type : string) return natural;
- function func_sdp_get_stat_app_total_length(g_statistics_type : string) return natural;
- function func_sdp_get_stat_udp_total_length(g_statistics_type : string) return natural;
- function func_sdp_get_stat_ip_total_length(g_statistics_type : string) return natural;
- function func_sdp_get_stat_udp_src_port(g_statistics_type : string; gn_index : natural) return std_logic_vector;
- function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural;
- function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural; -- use c_sdp_S_pn, c_sdp_P_sq, c_sdp_N_crosslets_max
+ function func_sdp_get_stat_app_total_length (g_statistics_type : string) return natural;
+ function func_sdp_get_stat_udp_total_length (g_statistics_type : string) return natural;
+ function func_sdp_get_stat_ip_total_length (g_statistics_type : string) return natural;
+ function func_sdp_get_stat_udp_src_port (g_statistics_type : string; gn_index : natural) return std_logic_vector;
+ function func_sdp_get_stat_nof_packets (g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural;
+ function func_sdp_get_stat_nof_packets (g_statistics_type : string) return natural; -- use c_sdp_S_pn, c_sdp_P_sq, c_sdp_N_crosslets_max
- function func_sdp_map_stat_header(hdr_fields_raw : std_logic_vector) return t_sdp_stat_header;
- function func_sdp_map_cep_header(hdr_fields_raw : std_logic_vector) return t_sdp_cep_header;
+ function func_sdp_map_stat_header (hdr_fields_raw : std_logic_vector) return t_sdp_stat_header;
+ function func_sdp_map_cep_header (hdr_fields_raw : std_logic_vector) return t_sdp_cep_header;
- function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_slv : std_logic_vector) return t_sdp_stat_data_id;
- function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_rec : t_sdp_stat_data_id) return std_logic_vector;
+ function func_sdp_map_stat_data_id (g_statistics_type : string; data_id_slv : std_logic_vector) return t_sdp_stat_data_id;
+ function func_sdp_map_stat_data_id (g_statistics_type : string; data_id_rec : t_sdp_stat_data_id) return std_logic_vector;
- function func_sdp_map_crosslets_info(info_slv : std_logic_vector) return t_sdp_crosslets_info; -- map all c_sdp_N_crosslets_max offsets
- function func_sdp_map_crosslets_info(info_rec : t_sdp_crosslets_info) return std_logic_vector; -- map all c_sdp_N_crosslets_max offsets
- function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info; -- step all c_sdp_N_crosslets_max offsets
+ function func_sdp_map_crosslets_info (info_slv : std_logic_vector) return t_sdp_crosslets_info; -- map all c_sdp_N_crosslets_max offsets
+ function func_sdp_map_crosslets_info (info_rec : t_sdp_crosslets_info) return std_logic_vector; -- map all c_sdp_N_crosslets_max offsets
+ function func_sdp_step_crosslets_info (info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info; -- step all c_sdp_N_crosslets_max offsets
end package sdp_pkg;
package body sdp_pkg is
- function func_sdp_gn_index_to_pn_index(gn_index : natural) return natural is
+ function func_sdp_gn_index_to_pn_index (gn_index : natural) return natural is
-- Determine PN index that starts at 0 per antenna band. For LOFAR2 SDP
-- each antenna_band has c_sdp_N_pn_max = 16 PN. The pn_index defines the
-- PN index within an antenna_band:
@@ -704,7 +736,7 @@ package body sdp_pkg is
return TO_UINT(v_index(c_w - 1 downto 0));
end func_sdp_gn_index_to_pn_index;
- function func_sdp_modulo_N_sub(sub_index : natural) return natural is
+ function func_sdp_modulo_N_sub (sub_index : natural) return natural is
begin
assert sub_index < 2 * c_sdp_N_sub report "func_sdp_modulo_N_sub: sub_index too large" severity FAILURE;
if sub_index < c_sdp_N_sub - 1 then
@@ -714,7 +746,7 @@ package body sdp_pkg is
end if;
end func_sdp_modulo_N_sub;
- function func_sdp_get_stat_marker(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_marker (g_statistics_type : string) return natural is
constant c_marker_sst : natural := 83; -- = 0x53 = 'S'
constant c_marker_bst : natural := 66; -- = 0x42 = 'B'
constant c_marker_xst : natural := 88; -- = 0x58 = 'X'
@@ -724,14 +756,14 @@ package body sdp_pkg is
c_marker_sst)); -- SST, SST_OS
end func_sdp_get_stat_marker;
- function func_sdp_get_stat_nof_signal_inputs(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_nof_signal_inputs (g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", 0, -- not applicable for BST, so use 0,
sel_a_b(g_statistics_type = "XST", c_sdp_S_pn,
1)); -- SST, SST_OS
end func_sdp_get_stat_nof_signal_inputs;
- function func_sdp_get_stat_from_mm_user_size(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_from_mm_user_size (g_statistics_type : string) return natural is
-- see sdp_statistics_offload.vhd for description
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_W_statistic_sz, -- = 2, so preserve X, Y order
@@ -739,14 +771,14 @@ package body sdp_pkg is
c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
end func_sdp_get_stat_from_mm_user_size;
- function func_sdp_get_stat_from_mm_data_size(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_from_mm_data_size (g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_N_pol_bf * c_sdp_W_statistic_sz, -- = 4
sel_a_b(g_statistics_type = "XST", c_nof_complex * c_sdp_W_statistic_sz, -- = 4
c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
end func_sdp_get_stat_from_mm_data_size;
- function func_sdp_get_stat_from_mm_step_size(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_from_mm_step_size (g_statistics_type : string) return natural is
constant c_data_size : natural := func_sdp_get_stat_from_mm_data_size(g_statistics_type);
begin
return sel_a_b(g_statistics_type = "BST", c_data_size, -- = 4
@@ -754,7 +786,7 @@ package body sdp_pkg is
c_data_size * c_sdp_Q_fft)); -- = 4, SST, SST_OS
end func_sdp_get_stat_from_mm_step_size;
- function func_sdp_get_stat_from_mm_nof_data(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_from_mm_nof_data (g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf, -- = 488
sel_a_b(g_statistics_type = "XST", c_sdp_X_sq, -- = 144
@@ -762,14 +794,14 @@ package body sdp_pkg is
end func_sdp_get_stat_from_mm_nof_data;
-- nof_statistics_per_packet = mm_nof_data * mm_data_size / c_sdp_W_statistic_sz
- function func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_nof_statistics_per_packet (g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf * c_sdp_N_pol_bf, -- = 976
sel_a_b(g_statistics_type = "XST", c_sdp_X_sq * c_nof_complex, -- = 288
c_sdp_N_sub)); -- = 512, SST, SST_OS
end func_sdp_get_stat_nof_statistics_per_packet;
- function func_sdp_get_stat_app_total_length(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_app_total_length (g_statistics_type : string) return natural is
constant c_nof_statistics_per_packet : natural := func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type);
begin
-- RETURN:
@@ -779,7 +811,7 @@ package body sdp_pkg is
return c_nof_statistics_per_packet * c_sdp_nof_bytes_per_statistic + c_sdp_stat_app_header_len;
end func_sdp_get_stat_app_total_length;
- function func_sdp_get_stat_udp_total_length(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_udp_total_length (g_statistics_type : string) return natural is
constant c_sdp_app_total_length : natural := func_sdp_get_stat_app_total_length(g_statistics_type);
begin
-- RETURN:
@@ -789,7 +821,7 @@ package body sdp_pkg is
return c_sdp_app_total_length + c_network_udp_header_len;
end func_sdp_get_stat_udp_total_length;
- function func_sdp_get_stat_ip_total_length(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_ip_total_length (g_statistics_type : string) return natural is
constant c_sdp_udp_total_length : natural := func_sdp_get_stat_udp_total_length(g_statistics_type);
begin
-- RETURN:
@@ -799,7 +831,7 @@ package body sdp_pkg is
return c_sdp_udp_total_length + c_network_ip_header_len;
end func_sdp_get_stat_ip_total_length;
- function func_sdp_get_stat_udp_src_port(g_statistics_type : string; gn_index : natural) return std_logic_vector is
+ function func_sdp_get_stat_udp_src_port (g_statistics_type : string; gn_index : natural) return std_logic_vector is
constant c_gn_index : std_logic_vector(7 downto 0) := TO_UVEC(gn_index, 8);
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_bst_udp_src_port_15_8 & c_gn_index, -- BST = 0xD1 & gn_index
@@ -807,7 +839,7 @@ package body sdp_pkg is
c_sdp_sst_udp_src_port_15_8 & c_gn_index)); -- SST = 0xD0 & gn_index, SST_OS
end func_sdp_get_stat_udp_src_port;
- function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural is
+ function func_sdp_get_stat_nof_packets (g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural is
begin
return sel_a_b(g_statistics_type = "BST", 1,
sel_a_b(g_statistics_type = "XST", P_sq * N_crosslets,
@@ -815,13 +847,13 @@ package body sdp_pkg is
c_sdp_R_os * S_pn))); -- SST_OS
end func_sdp_get_stat_nof_packets;
- function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural is
+ function func_sdp_get_stat_nof_packets (g_statistics_type : string) return natural is
begin
return func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, c_sdp_P_sq, c_sdp_N_crosslets_max);
end func_sdp_get_stat_nof_packets;
- function func_sdp_map_stat_header(hdr_fields_raw : std_logic_vector) return t_sdp_stat_header is
+ function func_sdp_map_stat_header (hdr_fields_raw : std_logic_vector) return t_sdp_stat_header is
variable v : t_sdp_stat_header;
begin
-- eth header
@@ -882,7 +914,7 @@ package body sdp_pkg is
end func_sdp_map_stat_header;
- function func_sdp_map_cep_header(hdr_fields_raw : std_logic_vector) return t_sdp_cep_header is
+ function func_sdp_map_cep_header (hdr_fields_raw : std_logic_vector) return t_sdp_cep_header is
variable v : t_sdp_cep_header;
begin
-- eth header
@@ -938,7 +970,7 @@ package body sdp_pkg is
end func_sdp_map_cep_header;
- function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_slv : std_logic_vector) return t_sdp_stat_data_id is
+ function func_sdp_map_stat_data_id (g_statistics_type : string; data_id_slv : std_logic_vector) return t_sdp_stat_data_id is
variable v_rec : t_sdp_stat_data_id;
begin
if g_statistics_type = "BST" then
@@ -953,7 +985,7 @@ package body sdp_pkg is
return v_rec;
end func_sdp_map_stat_data_id;
- function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_rec : t_sdp_stat_data_id) return std_logic_vector is
+ function func_sdp_map_stat_data_id (g_statistics_type : string; data_id_rec : t_sdp_stat_data_id) return std_logic_vector is
variable v_slv : std_logic_vector(31 downto 0) := x"00000000";
begin
if g_statistics_type = "BST" then
@@ -969,7 +1001,7 @@ package body sdp_pkg is
end func_sdp_map_stat_data_id;
- function func_sdp_map_crosslets_info(info_slv : std_logic_vector) return t_sdp_crosslets_info is
+ function func_sdp_map_crosslets_info (info_slv : std_logic_vector) return t_sdp_crosslets_info is
variable v_info : t_sdp_crosslets_info;
begin
for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop -- map al offsets
@@ -979,7 +1011,7 @@ package body sdp_pkg is
return v_info;
end func_sdp_map_crosslets_info;
- function func_sdp_map_crosslets_info(info_rec : t_sdp_crosslets_info) return std_logic_vector is
+ function func_sdp_map_crosslets_info (info_rec : t_sdp_crosslets_info) return std_logic_vector is
variable v_info : std_logic_vector(c_sdp_crosslets_info_reg_w - 1 downto 0);
begin
for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop -- map all offsets
@@ -990,7 +1022,7 @@ package body sdp_pkg is
end func_sdp_map_crosslets_info;
- function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info is
+ function func_sdp_step_crosslets_info (info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info is
variable v_info : t_sdp_crosslets_info := info_rec;
begin
for I in 0 to c_sdp_crosslets_info_nof_offsets - 1 loop -- step all offsets
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
index 1028933de6..e368548bc9 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
@@ -32,10 +32,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_scope is
generic (
@@ -73,17 +73,17 @@ begin
gen_deinterleave : for I in 0 to g_nof_input - 1 generate
u_dp_deinterleave : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_pipeline => 0,
- g_nof_outputs => g_n_deinterleave
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => sp_sosi_arr(I),
- src_out_arr => deinterleaved_sosi_2arr_n(I)
- );
+ generic map(
+ g_pipeline => 0,
+ g_nof_outputs => g_n_deinterleave
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => sp_sosi_arr(I),
+ src_out_arr => deinterleaved_sosi_2arr_n(I)
+ );
gen_flat : for J in 0 to g_n_deinterleave-1 generate
deinterleaved_sosi_arr(g_n_deinterleave * I + J) <= deinterleaved_sosi_2arr_n(I)(J);
@@ -112,18 +112,18 @@ begin
-- SIGNAL SCOPE
---------------------------------------------------------------
u_dp_wideband_sp_arr_scope : entity dp_lib.dp_wideband_sp_arr_scope
- generic map (
- g_sim => g_sim,
- g_use_sclk => false,
- g_complex => true,
- g_nof_streams => g_nof_input * g_n_deinterleave,
- g_wideband_factor => 1,
- g_dat_w => g_dat_w
- )
- port map (
- DCLK => clk,
- sp_sosi_arr => selected_sosi_arr,
- scope_sosi_arr => scope_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_use_sclk => false,
+ g_complex => true,
+ g_nof_streams => g_nof_input * g_n_deinterleave,
+ g_wideband_factor => 1,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ DCLK => clk,
+ sp_sosi_arr => selected_sosi_arr,
+ scope_sosi_arr => scope_sosi_arr
+ );
end generate;
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index cf4189c6ce..d88ab5d2e9 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -38,19 +38,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, diag_lib, dp_lib, tech_jesd204b_lib, fft_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, nw_10GbE_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use work.sdp_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use work.sdp_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity sdp_station is
generic (
@@ -86,9 +86,9 @@ entity sdp_station is
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -621,41 +621,41 @@ begin
xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & gn_id;
u_sdp_info : entity work.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_copi,
- reg_miso => reg_sdp_info_cipo,
+ reg_mosi => reg_sdp_info_copi,
+ reg_miso => reg_sdp_info_cipo,
- -- inputs from other blocks
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk); -- Using register to ease timing closure.
@@ -664,56 +664,56 @@ begin
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
-----------------------------------------------------------------------------
u_ait: entity work.node_sdp_adc_input_and_timing
- generic map(
- g_sim => g_sim,
- g_no_jesd => g_no_jesd,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- dp_pps => dp_pps,
-
- -- mm control buses
- jesd_ctrl_mosi => jesd_ctrl_copi,
- jesd_ctrl_miso => jesd_ctrl_cipo,
- jesd204b_mosi => jesd204b_copi,
- jesd204b_miso => jesd204b_cipo,
- reg_dp_shiftram_mosi => reg_dp_shiftram_copi,
- reg_dp_shiftram_miso => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_cipo,
- reg_wg_mosi => reg_wg_copi,
- reg_wg_miso => reg_wg_cipo,
- ram_wg_mosi => ram_wg_copi,
- ram_wg_miso => ram_wg_cipo,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_mosi => ram_st_histogram_copi,
- ram_st_histogram_miso => ram_st_histogram_cipo,
- reg_aduh_monitor_mosi => reg_aduh_monitor_copi,
- reg_aduh_monitor_miso => reg_aduh_monitor_cipo,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval
- );
+ generic map(
+ g_sim => g_sim,
+ g_no_jesd => g_no_jesd,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_pps => dp_pps,
+
+ -- mm control buses
+ jesd_ctrl_mosi => jesd_ctrl_copi,
+ jesd_ctrl_miso => jesd_ctrl_cipo,
+ jesd204b_mosi => jesd204b_copi,
+ jesd204b_miso => jesd204b_cipo,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_cipo,
+ reg_wg_mosi => reg_wg_copi,
+ reg_wg_miso => reg_wg_cipo,
+ ram_wg_mosi => ram_wg_copi,
+ ram_wg_miso => ram_wg_cipo,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_mosi => ram_st_histogram_copi,
+ ram_st_histogram_miso => ram_st_histogram_cipo,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_cipo,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
@@ -721,54 +721,54 @@ begin
gen_use_fsub : if g_use_fsub generate
gen_use_no_oversample : if not g_use_oversample generate -- Use normal filterbank
u_fsub : entity work.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- fsub_raw_sosi_arr => fsub_raw_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_copi,
- reg_si_miso => reg_si_cipo,
- ram_st_sst_mosi => ram_st_sst_copi,
- ram_st_sst_miso => ram_st_sst_cipo,
- ram_fil_coefs_mosi => ram_fil_coefs_copi,
- ram_fil_coefs_miso => ram_fil_coefs_cipo,
- ram_gains_mosi => ram_equalizer_gains_copi,
- ram_gains_miso => ram_equalizer_gains_cipo,
- ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
- ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
- reg_selector_mosi => reg_dp_selector_copi,
- reg_selector_miso => reg_dp_selector_cipo,
-
- reg_enable_mosi => reg_stat_enable_sst_copi,
- reg_enable_miso => reg_stat_enable_sst_cipo,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
-
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ fsub_raw_sosi_arr => fsub_raw_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_copi,
+ reg_si_miso => reg_si_cipo,
+ ram_st_sst_mosi => ram_st_sst_copi,
+ ram_st_sst_miso => ram_st_sst_cipo,
+ ram_fil_coefs_mosi => ram_fil_coefs_copi,
+ ram_fil_coefs_miso => ram_fil_coefs_cipo,
+ ram_gains_mosi => ram_equalizer_gains_copi,
+ ram_gains_miso => ram_equalizer_gains_cipo,
+ ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
+ ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
+ reg_selector_miso => reg_dp_selector_cipo,
+
+ reg_enable_mosi => reg_stat_enable_sst_copi,
+ reg_enable_miso => reg_stat_enable_sst_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
+
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
gen_bf_sosi : for I in 0 to c_sdp_N_beamsets - 1 generate
-- Wire same subbands to all beamsets
@@ -781,55 +781,55 @@ begin
-----------------------------------------------------------------------------
gen_use_oversample : if g_use_oversample generate -- use oversampled filterbank instead of normal filterbank
u_fsub : entity work.node_sdp_oversampled_filterbank
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- fsub_raw_sosi_arr => fsub_oversampled_raw_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_copi,
- reg_si_miso => reg_si_cipo,
- ram_st_sst_mosi => ram_st_sst_copi,
- ram_st_sst_miso => ram_st_sst_cipo,
- ram_fil_coefs_mosi => ram_fil_coefs_copi,
- ram_fil_coefs_miso => ram_fil_coefs_cipo,
- ram_gains_mosi => ram_equalizer_gains_copi,
- ram_gains_miso => ram_equalizer_gains_cipo,
- ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
- ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
- reg_selector_mosi => reg_dp_selector_copi,
- reg_selector_miso => reg_dp_selector_cipo,
-
- reg_enable_mosi => reg_stat_enable_sst_copi,
- reg_enable_miso => reg_stat_enable_sst_cipo,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
-
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ fsub_raw_sosi_arr => fsub_oversampled_raw_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_copi,
+ reg_si_miso => reg_si_cipo,
+ ram_st_sst_mosi => ram_st_sst_copi,
+ ram_st_sst_miso => ram_st_sst_cipo,
+ ram_fil_coefs_mosi => ram_fil_coefs_copi,
+ ram_fil_coefs_miso => ram_fil_coefs_cipo,
+ ram_gains_mosi => ram_equalizer_gains_copi,
+ ram_gains_miso => ram_equalizer_gains_cipo,
+ ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
+ ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
+ reg_selector_miso => reg_dp_selector_cipo,
+
+ reg_enable_mosi => reg_stat_enable_sst_copi,
+ reg_enable_miso => reg_stat_enable_sst_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
+
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
-- Lower part contains normal subbands, higher part contains shifted subbands.
-- . Use normal subbands for subband correlator
@@ -848,60 +848,60 @@ begin
-----------------------------------------------------------------------------
gen_use_xsub : if g_use_xsub generate
u_xsub : entity work.node_sdp_correlator
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_P_sq => g_P_sq,
- g_subband_raw_dat_w => c_subband_raw_dat_w,
- g_subband_raw_fraction_w => c_subband_raw_fraction_w
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_raw_sosi_arr,
-
- xst_udp_sosi => udp_tx_sosi_arr(1),
- xst_udp_siso => udp_tx_siso_arr(1),
-
- from_ri_sosi => xst_from_ri_sosi,
- to_ri_sosi => xst_to_ri_sosi,
-
- xst_bs_sosi => xst_bs_sosi,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- reg_stat_enable_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
-
- sdp_info => sdp_info,
- ring_info => ring_info,
- gn_id => gn_id,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => xst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_P_sq => g_P_sq,
+ g_subband_raw_dat_w => c_subband_raw_dat_w,
+ g_subband_raw_fraction_w => c_subband_raw_fraction_w
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_raw_sosi_arr,
+
+ xst_udp_sosi => udp_tx_sosi_arr(1),
+ xst_udp_siso => udp_tx_siso_arr(1),
+
+ from_ri_sosi => xst_from_ri_sosi,
+ to_ri_sosi => xst_to_ri_sosi,
+
+ xst_bs_sosi => xst_bs_sosi,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ reg_stat_enable_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+
+ sdp_info => sdp_info,
+ ring_info => ring_info,
+ gn_id => gn_id,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => xst_udp_src_port
+ );
end generate;
@@ -912,230 +912,230 @@ begin
-- Beamformers
gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
u_bf : entity work.node_sdp_beamformer
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_beamset_id => beamset_id,
- g_scope_selected_beamlet => g_scope_selected_subband,
- g_subband_raw_dat_w => c_subband_raw_dat_w,
- g_subband_raw_fraction_w => c_subband_raw_fraction_w
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_raw_sosi_2arr(beamset_id),
- from_ri_sosi => bf_from_ri_sosi_arr(beamset_id),
- to_ri_sosi => bf_to_ri_sosi_arr(beamset_id),
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => udp_tx_sosi_arr(2 + beamset_id),
- bst_udp_siso => udp_tx_siso_arr(2 + beamset_id),
-
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_copi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_cipo_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_copi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_cipo_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_copi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
- ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
- ram_st_bst_miso => ram_st_bst_cipo_arr(beamset_id),
- reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
- reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
- reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(beamset_id),
- reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
-
- sdp_info => sdp_info,
- ring_info => ring_info,
- gn_id => gn_id,
-
- bdo_eth_src_mac => cep_eth_src_mac,
- bdo_ip_src_addr => cep_ip_src_addr,
- bdo_udp_src_port => cep_udp_src_port,
- bdo_hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id),
-
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => bst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_beamset_id => beamset_id,
+ g_scope_selected_beamlet => g_scope_selected_subband,
+ g_subband_raw_dat_w => c_subband_raw_dat_w,
+ g_subband_raw_fraction_w => c_subband_raw_fraction_w
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_raw_sosi_2arr(beamset_id),
+ from_ri_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_ri_sosi => bf_to_ri_sosi_arr(beamset_id),
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => udp_tx_sosi_arr(2 + beamset_id),
+ bst_udp_siso => udp_tx_siso_arr(2 + beamset_id),
+
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_copi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_cipo_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_copi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_cipo_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_copi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
+ ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
+ ram_st_bst_miso => ram_st_bst_cipo_arr(beamset_id),
+ reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
+ reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
+ reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(beamset_id),
+ reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ ring_info => ring_info,
+ gn_id => gn_id,
+
+ bdo_eth_src_mac => cep_eth_src_mac,
+ bdo_ip_src_addr => cep_ip_src_addr,
+ bdo_udp_src_port => cep_udp_src_port,
+ bdo_hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id),
+
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => bst_udp_src_port
+ );
end generate;
-- MM multiplexing
u_mem_mux_ram_ss_ss_wide : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- port map (
- mosi => ram_ss_ss_wide_copi,
- miso => ram_ss_ss_wide_cipo,
- mosi_arr => ram_ss_ss_wide_copi_arr,
- miso_arr => ram_ss_ss_wide_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ port map (
+ mosi => ram_ss_ss_wide_copi,
+ miso => ram_ss_ss_wide_cipo,
+ mosi_arr => ram_ss_ss_wide_copi_arr,
+ miso_arr => ram_ss_ss_wide_cipo_arr
+ );
u_mem_mux_ram_bf_weights : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- port map (
- mosi => ram_bf_weights_copi,
- miso => ram_bf_weights_cipo,
- mosi_arr => ram_bf_weights_copi_arr,
- miso_arr => ram_bf_weights_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ port map (
+ mosi => ram_bf_weights_copi,
+ miso => ram_bf_weights_cipo,
+ mosi_arr => ram_bf_weights_copi_arr,
+ miso_arr => ram_bf_weights_cipo_arr
+ );
u_mem_mux_reg_bsn_align_v2_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bsn_align_v2_bf
- )
- port map (
- mosi => reg_bsn_align_v2_bf_copi,
- miso => reg_bsn_align_v2_bf_cipo,
- mosi_arr => reg_bsn_align_v2_bf_copi_arr,
- miso_arr => reg_bsn_align_v2_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_align_v2_bf
+ )
+ port map (
+ mosi => reg_bsn_align_v2_bf_copi,
+ miso => reg_bsn_align_v2_bf_cipo,
+ mosi_arr => reg_bsn_align_v2_bf_copi_arr,
+ miso_arr => reg_bsn_align_v2_bf_cipo_arr
+ );
u_mem_mux_reg_bf_scale : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- port map (
- mosi => reg_bf_scale_copi,
- miso => reg_bf_scale_cipo,
- mosi_arr => reg_bf_scale_copi_arr,
- miso_arr => reg_bf_scale_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ port map (
+ mosi => reg_bf_scale_copi,
+ miso => reg_bf_scale_cipo,
+ mosi_arr => reg_bf_scale_copi_arr,
+ miso_arr => reg_bf_scale_cipo_arr
+ );
u_mem_mux_reg_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- port map (
- mosi => reg_hdr_dat_copi,
- miso => reg_hdr_dat_cipo,
- mosi_arr => reg_hdr_dat_copi_arr,
- miso_arr => reg_hdr_dat_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ port map (
+ mosi => reg_hdr_dat_copi,
+ miso => reg_hdr_dat_cipo,
+ mosi_arr => reg_hdr_dat_copi_arr,
+ miso_arr => reg_hdr_dat_cipo_arr
+ );
u_mem_mux_reg_dp_xonoff : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- port map (
- mosi => reg_dp_xonoff_copi,
- miso => reg_dp_xonoff_cipo,
- mosi_arr => reg_dp_xonoff_copi_arr,
- miso_arr => reg_dp_xonoff_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ port map (
+ mosi => reg_dp_xonoff_copi,
+ miso => reg_dp_xonoff_cipo,
+ mosi_arr => reg_dp_xonoff_copi_arr,
+ miso_arr => reg_dp_xonoff_cipo_arr
+ );
u_mem_mux_ram_st_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- port map (
- mosi => ram_st_bst_copi,
- miso => ram_st_bst_cipo,
- mosi_arr => ram_st_bst_copi_arr,
- miso_arr => ram_st_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ port map (
+ mosi => ram_st_bst_copi,
+ miso => ram_st_bst_cipo,
+ mosi_arr => ram_st_bst_copi_arr,
+ miso_arr => ram_st_bst_cipo_arr
+ );
u_mem_mux_reg_stat_enable_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
- )
- port map (
- mosi => reg_stat_enable_bst_copi,
- miso => reg_stat_enable_bst_cipo,
- mosi_arr => reg_stat_enable_bst_copi_arr,
- miso_arr => reg_stat_enable_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
+ )
+ port map (
+ mosi => reg_stat_enable_bst_copi,
+ miso => reg_stat_enable_bst_cipo,
+ mosi_arr => reg_stat_enable_bst_copi_arr,
+ miso_arr => reg_stat_enable_bst_cipo_arr
+ );
u_mem_mux_reg_stat_hdr_dat_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
- )
- port map (
- mosi => reg_stat_hdr_dat_bst_copi,
- miso => reg_stat_hdr_dat_bst_cipo,
- mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
- miso_arr => reg_stat_hdr_dat_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
+ )
+ port map (
+ mosi => reg_stat_hdr_dat_bst_copi,
+ miso => reg_stat_hdr_dat_bst_cipo,
+ mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
+ miso_arr => reg_stat_hdr_dat_bst_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_rx_align_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_rx_align_bf
- )
- port map (
- mosi => reg_bsn_monitor_v2_rx_align_bf_copi,
- miso => reg_bsn_monitor_v2_rx_align_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_rx_align_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_rx_align_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_rx_align_bf
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ miso => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_rx_align_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_align_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_aligned_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_aligned_bf_copi,
- miso => reg_bsn_monitor_v2_aligned_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_aligned_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_aligned_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_aligned_bf_copi,
+ miso => reg_bsn_monitor_v2_aligned_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_aligned_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_aligned_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_bst_offload : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_bst_offload_copi,
- miso => reg_bsn_monitor_v2_bst_offload_cipo,
- mosi_arr => reg_bsn_monitor_v2_bst_offload_copi_arr,
- miso_arr => reg_bsn_monitor_v2_bst_offload_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_bst_offload_copi,
+ miso => reg_bsn_monitor_v2_bst_offload_cipo,
+ mosi_arr => reg_bsn_monitor_v2_bst_offload_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_bst_offload_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_beamlet_output : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_beamlet_output_copi,
- miso => reg_bsn_monitor_v2_beamlet_output_cipo,
- mosi_arr => reg_bsn_monitor_v2_beamlet_output_copi_arr,
- miso_arr => reg_bsn_monitor_v2_beamlet_output_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_beamlet_output_copi,
+ miso => reg_bsn_monitor_v2_beamlet_output_cipo,
+ mosi_arr => reg_bsn_monitor_v2_beamlet_output_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_beamlet_output_cipo_arr
+ );
-----------------------------------------------------------------------------
-- DP MUX to multiplex the c_sdp_N_beamsets via one beamlet output 10GbE link
@@ -1146,137 +1146,85 @@ begin
nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
+ generic map (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => true,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
- src_out => nw_10gbe_beamlet_output_snk_in_arr(0),
- src_in => nw_10gbe_beamlet_output_snk_out_arr(0)
- );
+ src_out => nw_10gbe_beamlet_output_snk_in_arr(0),
+ src_in => nw_10gbe_beamlet_output_snk_out_arr(0)
+ );
---------------
-- nw_10GbE beamlet output via front_io QSFP[1]
---------------
u_nw_10GbE_beamlet_output: entity nw_10GbE_lib.nw_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_beamlet_output,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill_beamlet_output,
- g_tx_fifo_size => c_fifo_tx_size_beamlet_output,
- g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_xon_backpressure => true
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_beamlet_output,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill_beamlet_output,
+ g_tx_fifo_size => c_fifo_tx_size_beamlet_output,
+ g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_xon_backpressure => true
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mac_mosi => reg_nw_10GbE_mac_copi,
- reg_mac_miso => reg_nw_10GbE_mac_cipo,
+ reg_mac_mosi => reg_nw_10GbE_mac_copi,
+ reg_mac_miso => reg_nw_10GbE_mac_cipo,
- reg_eth10g_mosi => reg_nw_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_nw_10GbE_eth10g_cipo,
+ reg_eth10g_mosi => reg_nw_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_nw_10GbE_eth10g_cipo,
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
- snk_out_arr => nw_10gbe_beamlet_output_snk_out_arr,
- snk_in_arr => nw_10gbe_beamlet_output_snk_in_arr,
+ snk_out_arr => nw_10gbe_beamlet_output_snk_out_arr,
+ snk_in_arr => nw_10gbe_beamlet_output_snk_in_arr,
- src_out_arr => nw_10gbe_beamlet_output_src_out_arr,
- src_in_arr => nw_10gbe_beamlet_output_src_in_arr,
+ src_out_arr => nw_10gbe_beamlet_output_src_out_arr,
+ src_in_arr => nw_10gbe_beamlet_output_src_in_arr,
- -- Serial IO
- serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
- serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
+ -- Serial IO
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
- hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
- );
+ hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
+ );
end generate;
gen_use_ring : if g_use_ring generate
gen_xst_ring : if g_use_xsub generate
u_ring_lane_xst : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_longword_w,
- g_lane_packet_length => c_lane_payload_nof_longwords_xst,
- g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
- g_use_dp_layer => true,
- g_nof_rx_monitors => c_sdp_N_pn_max,
- g_nof_tx_monitors => c_sdp_N_pn_max,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => xst_from_ri_sosi,
- to_lane_sosi => xst_to_ri_sosi,
- lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
- lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
- lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
- lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
- bs_sosi => xst_bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
- end generate;
-
- gen_bf_ring : if g_use_bf generate
- bf_bs_sosi <= fsub_raw_sosi_arr(0);
-
- gen_beamset_ring : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
- u_ring_lane_bf : entity ring_lib.ring_lane
generic map (
g_lane_direction => 1, -- transport in positive direction.
g_lane_data_w => c_longword_w,
- g_lane_packet_length => c_lane_payload_nof_longwords_bf,
+ g_lane_packet_length => c_lane_payload_nof_longwords_xst,
g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
g_use_dp_layer => true,
- g_nof_rx_monitors => 1,
- g_nof_tx_monitors => 1,
+ g_nof_rx_monitors => c_sdp_N_pn_max,
+ g_nof_tx_monitors => c_sdp_N_pn_max,
g_err_bi => c_err_bi,
g_nof_err_counts => c_nof_err_counts,
g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
@@ -1290,92 +1238,144 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
- from_lane_sosi => bf_from_ri_sosi_arr(beamset_id),
- to_lane_sosi => bf_to_ri_sosi_arr(beamset_id),
- lane_rx_cable_sosi => lane_rx_cable_sosi_arr(1 + beamset_id),
- lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
- lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
- lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
- bs_sosi => bf_bs_sosi, -- used for bsn and sync
-
- reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
- reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr(beamset_id),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_bf_copi_arr(beamset_id),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_bf_cipo_arr(beamset_id),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_bf_copi_arr(beamset_id),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr(beamset_id),
+ from_lane_sosi => xst_from_ri_sosi,
+ to_lane_sosi => xst_to_ri_sosi,
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
+ bs_sosi => xst_bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
this_rn => this_rn,
N_rn => ring_info.N_rn,
rx_select => ring_info.use_cable_to_previous_rn,
tx_select => ring_info.use_cable_to_next_rn
);
+ end generate;
+
+ gen_bf_ring : if g_use_bf generate
+ bf_bs_sosi <= fsub_raw_sosi_arr(0);
+
+ gen_beamset_ring : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
+ u_ring_lane_bf : entity ring_lib.ring_lane
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_longword_w,
+ g_lane_packet_length => c_lane_payload_nof_longwords_bf,
+ g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
+ g_use_dp_layer => true,
+ g_nof_rx_monitors => 1,
+ g_nof_tx_monitors => 1,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_lane_sosi => bf_to_ri_sosi_arr(beamset_id),
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(1 + beamset_id),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
+ bs_sosi => bf_bs_sosi, -- used for bsn and sync
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr(beamset_id),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
u_mem_mux_reg_ring_lane_info_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info_bf
- )
- port map (
- mosi => reg_ring_lane_info_bf_copi,
- miso => reg_ring_lane_info_bf_cipo,
- mosi_arr => reg_ring_lane_info_bf_copi_arr,
- miso_arr => reg_ring_lane_info_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info_bf
+ )
+ port map (
+ mosi => reg_ring_lane_info_bf_copi,
+ miso => reg_ring_lane_info_bf_cipo,
+ mosi_arr => reg_ring_lane_info_bf_copi_arr,
+ miso_arr => reg_ring_lane_info_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_ring_rx_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- miso => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_ring_tx_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
+ );
u_mem_mux_reg_dp_block_validate_err_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_dp_block_validate_err_addr_w
- )
- port map (
- mosi => reg_dp_block_validate_err_bf_copi,
- miso => reg_dp_block_validate_err_bf_cipo,
- mosi_arr => reg_dp_block_validate_err_bf_copi_arr,
- miso_arr => reg_dp_block_validate_err_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_err_addr_w
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_bf_copi,
+ miso => reg_dp_block_validate_err_bf_cipo,
+ mosi_arr => reg_dp_block_validate_err_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_err_bf_cipo_arr
+ );
u_mem_mux_reg_dp_block_validate_bsn_at_sync_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- miso => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_bf_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1399,45 +1399,45 @@ begin
-- tr_10GbE ring via front_io QSFP[0]
-----------------------------------------------------------------------------
u_tr_10GbE_ring: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_ring_nof_mac_ip,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill_ring,
- g_tx_fifo_size => c_fifo_tx_size_ring
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_ring_nof_mac_ip,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill_ring,
+ g_tx_fifo_size => c_fifo_tx_size_ring
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- src_out_arr => tr_10gbe_ring_src_out_arr,
- src_in_arr => tr_10gbe_ring_src_in_arr,
+ src_out_arr => tr_10gbe_ring_src_out_arr,
+ src_in_arr => tr_10gbe_ring_src_in_arr,
- snk_out_arr => tr_10gbe_ring_snk_out_arr,
- snk_in_arr => tr_10gbe_ring_snk_in_arr,
+ snk_out_arr => tr_10gbe_ring_snk_out_arr,
+ snk_in_arr => tr_10gbe_ring_snk_in_arr,
- -- Serial IO
- serial_tx_arr => tr_10gbe_ring_serial_tx_arr,
- serial_rx_arr => tr_10gbe_ring_serial_rx_arr
- );
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_ring_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_ring_serial_rx_arr
+ );
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
@@ -1466,14 +1466,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- LEDs
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index d362ef6006..39abb369e1 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -98,14 +98,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib, dp_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_statistics_offload is
generic (
@@ -593,48 +593,48 @@ begin
in_trigger <= in_sosi.sync and not reg_new_interval;
u_mms_common_variable_delay : entity common_lib.mms_common_variable_delay
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
-
- delay => p.nof_cycles_dly,
- trigger => in_trigger,
- trigger_en => trigger_en,
- trigger_dly => trigger_offload
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
+
+ delay => p.nof_cycles_dly,
+ trigger => in_trigger,
+ trigger_en => trigger_en,
+ trigger_dly => trigger_offload
+ );
u_dp_block_from_mm_dc : entity dp_lib.dp_block_from_mm_dc
- generic map (
- g_user_size => c_mm_user_size,
- g_data_size => c_mm_data_size,
- g_step_size => c_mm_step_size,
- g_nof_data => c_mm_nof_data,
- g_word_w => c_word_w,
- g_reverse_word_order => g_reverse_word_order,
- g_bsn_w => c_dp_stream_bsn_w,
- g_bsn_incr_enable => false -- all offload block have same bsn_at_sync
- )
- port map(
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start_pulse => r.start_pulse,
- sync_in => r.start_sync,
- bsn_at_sync => hdr_input.bsn_at_sync,
- start_address => r.start_address,
- mm_mosi => master_mosi,
- mm_miso => master_miso,
- out_sop => dp_sop, -- = dp_block_from_mm_src_out.sop
- out_sosi => dp_block_from_mm_src_out,
- out_siso => dp_block_from_mm_src_in
- );
+ generic map (
+ g_user_size => c_mm_user_size,
+ g_data_size => c_mm_data_size,
+ g_step_size => c_mm_step_size,
+ g_nof_data => c_mm_nof_data,
+ g_word_w => c_word_w,
+ g_reverse_word_order => g_reverse_word_order,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_bsn_incr_enable => false -- all offload block have same bsn_at_sync
+ )
+ port map(
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start_pulse => r.start_pulse,
+ sync_in => r.start_sync,
+ bsn_at_sync => hdr_input.bsn_at_sync,
+ start_address => r.start_address,
+ mm_mosi => master_mosi,
+ mm_miso => master_miso,
+ out_sop => dp_sop, -- = dp_block_from_mm_src_out.sop
+ out_sosi => dp_block_from_mm_src_out,
+ out_siso => dp_block_from_mm_src_in
+ );
-- The dp_sop is the sop of the packet that is about to be offloaded by
-- u_dp_offload_tx_v3. The r.dp_header_info must be available at the
@@ -645,16 +645,16 @@ begin
-- u_dp_pipeline_ready.
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map(
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => dp_block_from_mm_src_in,
- snk_in => dp_block_from_mm_src_out,
- -- ST source
- src_in => dp_offload_snk_out,
- src_out => dp_offload_snk_in
- );
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => dp_block_from_mm_src_in,
+ snk_in => dp_block_from_mm_src_out,
+ -- ST source
+ src_in => dp_offload_snk_out,
+ src_out => dp_offload_snk_in
+ );
-- The hdr_input.bsn_at_sync is passed on via r.dp_header_info so that
-- u_dp_offload_tx_v3 can put it in the udp_sosi header.
@@ -664,27 +664,27 @@ begin
-- is in fact not used, but useful to have in udp_sosi.sync (e.g. for the
-- tb).
u_dp_offload_tx_v3: entity dp_lib.dp_offload_tx_v3
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_word_w,
- g_symbol_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_hdr_field_sel => c_sdp_stat_hdr_field_sel,
- g_pipeline_ready => true
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- snk_in_arr(0) => dp_offload_snk_in,
- snk_out_arr(0) => dp_offload_snk_out,
- src_out_arr(0) => udp_sosi,
- src_in_arr(0) => out_siso,
- hdr_fields_in_arr(0) => r.dp_header_info
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_word_w,
+ g_symbol_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_hdr_field_sel => c_sdp_stat_hdr_field_sel,
+ g_pipeline_ready => true
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ snk_in_arr(0) => dp_offload_snk_in,
+ snk_out_arr(0) => dp_offload_snk_out,
+ src_out_arr(0) => udp_sosi,
+ src_in_arr(0) => out_siso,
+ hdr_fields_in_arr(0) => r.dp_header_info
+ );
-- Debug signal, r_dp_header_rec must be available at the r_dp_header_sop
r_dp_header_sop <= dp_offload_snk_in.sop;
@@ -693,29 +693,29 @@ begin
out_sosi <= udp_sosi;
u_bsn_mon_udp : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bsn_monitor_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_offload_copi,
- reg_miso => reg_bsn_monitor_v2_offload_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => in_sosi.sync,
-
- in_sosi_arr(0) => udp_sosi
- );
+ generic map (
+ g_nof_streams => 1,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bsn_monitor_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_offload_copi,
+ reg_miso => reg_bsn_monitor_v2_offload_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => in_sosi.sync,
+
+ in_sosi_arr(0) => udp_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index edb7f9964f..7e8498e58b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -49,11 +49,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_subband_equalizer is
generic (
@@ -115,18 +115,18 @@ begin
-- g_reverse_len - 1 +
-- g_pipeline_mux_in + g_pipeline_mux_out = 1 + 0 + 2-1 + 0 + 1 = 3
u_pipeline_co_pol : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => 3
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_raw_sosi_arr,
- -- ST source
- src_out_arr => in_pipe_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => 3
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_raw_sosi_arr,
+ -- ST source
+ src_out_arr => in_pipe_raw_sosi_arr
+ );
-- The input subband data order is fsub[S_pn/Q_fft]_[N_sub][Q_fft] and
-- the [Q_fft] = [N_pol] index contains the X and Y polarizations.
@@ -135,23 +135,23 @@ begin
-- in_pipeline_raw_sosi_arr.
gen_cross_pol : for I in 0 to g_nof_streams - 1 generate
u_cross_pol : entity dp_lib.dp_reverse_n_data
- generic map (
- g_pipeline_demux_in => 1, -- serial to parallel section
- g_pipeline_demux_out => 0,
- g_pipeline_mux_in => 0, -- parallel to serial section
- g_pipeline_mux_out => 1,
- g_reverse_len => c_sdp_N_pol, -- = 2
- g_data_w => g_raw_dat_w * c_nof_complex,
- g_use_complex => true,
- g_signed => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => in_raw_sosi_arr(I),
- src_out => in_cross_raw_sosi_arr(I)
- );
+ generic map (
+ g_pipeline_demux_in => 1, -- serial to parallel section
+ g_pipeline_demux_out => 0,
+ g_pipeline_mux_in => 0, -- parallel to serial section
+ g_pipeline_mux_out => 1,
+ g_reverse_len => c_sdp_N_pol, -- = 2
+ g_data_w => g_raw_dat_w * c_nof_complex,
+ g_use_complex => true,
+ g_signed => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => in_raw_sosi_arr(I),
+ src_out => in_cross_raw_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -159,30 +159,30 @@ begin
-----------------------------------------------------------------------------
-- Total pipeline of sdp_subband_weights is: 5
u_sdp_subband_weigths : entity work.sdp_subband_weights
- generic map (
- g_gains_file_name => g_gains_file_name, -- for co polarization
- g_nof_streams => g_nof_streams,
- g_raw_dat_w => g_raw_dat_w
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ generic map (
+ g_gains_file_name => g_gains_file_name, -- for co polarization
+ g_nof_streams => g_nof_streams,
+ g_raw_dat_w => g_raw_dat_w
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- in_raw_sosi_arr => in_pipe_raw_sosi_arr,
- in_cross_raw_sosi_arr => in_cross_raw_sosi_arr,
+ in_raw_sosi_arr => in_pipe_raw_sosi_arr,
+ in_cross_raw_sosi_arr => in_cross_raw_sosi_arr,
- weighted_raw_sosi_arr => weighted_raw_sosi_arr,
- weighted_cross_raw_sosi_arr => weighted_cross_raw_sosi_arr,
+ weighted_raw_sosi_arr => weighted_raw_sosi_arr,
+ weighted_cross_raw_sosi_arr => weighted_cross_raw_sosi_arr,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
- ram_gains_cross_mosi => ram_gains_cross_mosi,
- ram_gains_cross_miso => ram_gains_cross_miso
- );
+ ram_gains_cross_mosi => ram_gains_cross_mosi,
+ ram_gains_cross_miso => ram_gains_cross_miso
+ );
-----------------------------------------------------------------------------
-- Sum co + cross
@@ -194,17 +194,17 @@ begin
in_raw_sosi_2arr_2(I)(1) <= weighted_cross_raw_sosi_arr(I);
u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_sdp_N_pol,
- g_data_w => c_gain_out_dat_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => in_raw_sosi_2arr_2(I),
- src_out => sum_raw_sosi_arr(I)
- );
+ generic map(
+ g_nof_inputs => c_sdp_N_pol,
+ g_data_w => c_gain_out_dat_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => in_raw_sosi_2arr_2(I),
+ src_out => sum_raw_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -219,51 +219,51 @@ begin
-- g_raw_fraction_w, so that the output width remains the same as the input
-- width g_raw_dat_w.
u_dp_requantize_out_raw : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_sub_weight_fraction,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => c_pipeline_remove_msb,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => g_raw_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => sum_raw_sosi_arr(I),
- -- ST source
- src_out => out_raw_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_sub_weight_fraction,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => c_pipeline_remove_msb,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => g_raw_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => sum_raw_sosi_arr(I),
+ -- ST source
+ src_out => out_raw_sosi_arr(I)
+ );
-- For quant output round the entire fraction, so that the output width
-- becomes c_quant_dat_w.
u_dp_requantize_out_quant : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_sub_weight_fraction + g_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => c_pipeline_remove_msb,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => c_quant_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => sum_raw_sosi_arr(I),
- -- ST source
- src_out => out_quant_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_sub_weight_fraction + g_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => c_pipeline_remove_msb,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => c_quant_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => sum_raw_sosi_arr(I),
+ -- ST source
+ src_out => out_quant_sosi_arr(I)
+ );
end generate;
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
index 8b2c4e4eb3..f44c2ef594 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
@@ -39,11 +39,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_subband_weights is
generic (
@@ -132,61 +132,61 @@ begin
-- Gain
-----------------------------------------------------------------------------
u_gains_co : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_sub_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_raw_sosi_arr,
- out_sosi_arr => weighted_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_sub_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => g_gains_file_name
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address,
+
+ in_sosi_arr => in_raw_sosi_arr,
+ out_sosi_arr => weighted_raw_sosi_arr
+ );
u_gains_cross : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_sub_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => "UNUSED"
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_cross_mosi,
- ram_gains_miso => ram_gains_cross_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_cross_raw_sosi_arr,
- out_sosi_arr => weighted_cross_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_sub_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => "UNUSED"
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_cross_mosi,
+ ram_gains_miso => ram_gains_cross_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address,
+
+ in_sosi_arr => in_cross_raw_sosi_arr,
+ out_sosi_arr => weighted_cross_raw_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index d677643371..fd0b876540 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -33,15 +33,15 @@
-- and cur_crosslets_info of the dut by comparing it to the expected output.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.sdp_pkg.all;
entity tb_sdp_crosslets_subband_select is
@@ -283,29 +283,29 @@ begin
end process;
u_dut : entity work.sdp_crosslets_subband_select
- generic map (
- g_N_crosslets => c_N_crosslets,
- g_ctrl_interval_size_min => 1
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
-
- mm_rst => rst,
- mm_clk => mm_clk,
-
- reg_crosslets_info_mosi => mm_mosi,
- reg_crosslets_info_miso => mm_miso,
-
- reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
- reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
-
- -- Streaming
- in_sosi_arr => in_sosi_arr,
- out_sosi => out_sosi,
-
- cur_crosslets_info_rec => cur_crosslets_info_rec,
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ generic map (
+ g_N_crosslets => c_N_crosslets,
+ g_ctrl_interval_size_min => 1
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_mosi => mm_mosi,
+ reg_crosslets_info_miso => mm_miso,
+
+ reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
+
+ -- Streaming
+ in_sosi_arr => in_sosi_arr,
+ out_sosi => out_sosi,
+
+ cur_crosslets_info_rec => cur_crosslets_info_rec,
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
end tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
index cc7d5ac3fb..0c02e6ebec 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
@@ -34,12 +34,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.sdp_pkg.all;
entity tb_sdp_info is
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index d84f73d36b..922f221c93 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -26,58 +26,61 @@
-- Description:
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use work.sdp_pkg.all;
package tb_sdp_pkg is
-----------------------------------------------------------------------------
-- Derive low part of MAC, IP from global node (GN) index
-----------------------------------------------------------------------------
- function func_sdp_gn_index_to_mac_15_0(gn_index : natural) return std_logic_vector;
- function func_sdp_gn_index_to_ip_15_0(gn_index : natural) return std_logic_vector;
+ function func_sdp_gn_index_to_mac_15_0 (gn_index : natural) return std_logic_vector;
+ function func_sdp_gn_index_to_ip_15_0 (gn_index : natural) return std_logic_vector;
-----------------------------------------------------------------------------
-- Statistics offload
-----------------------------------------------------------------------------
- function func_sdp_compose_stat_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- g_statistics_type : string;
- weighted_subbands_flag : std_logic;
- gn_index : natural;
- nof_block_per_sync : natural;
- sst_signal_input : natural;
- beamlet_index : natural;
- subband_index : natural;
- xst_signal_input_A : natural;
- xst_signal_input_B : natural;
- dp_bsn : natural) return t_sdp_stat_header;
-
- function func_sdp_verify_stat_header(g_statistics_type : string; in_hdr, exp_hdr : t_sdp_stat_header) return boolean;
+ function func_sdp_compose_stat_header (
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ g_statistics_type : string;
+ weighted_subbands_flag : std_logic;
+ gn_index : natural;
+ nof_block_per_sync : natural;
+ sst_signal_input : natural;
+ beamlet_index : natural;
+ subband_index : natural;
+ xst_signal_input_A : natural;
+ xst_signal_input_B : natural;
+ dp_bsn : natural) return t_sdp_stat_header;
+
+ function func_sdp_verify_stat_header (g_statistics_type : string; in_hdr, exp_hdr : t_sdp_stat_header) return boolean;
-----------------------------------------------------------------------------
-- Beamlet output via 10GbE to CEP (= central processor)
-----------------------------------------------------------------------------
- function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
- ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header;
-
- function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header;
-
- function func_sdp_verify_cep_header(in_hdr, exp_hdr : t_sdp_cep_header) return boolean;
+ function func_sdp_compose_cep_header (
+ ip_src_addr : std_logic_vector;
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header;
+
+ function func_sdp_compose_cep_header (
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header;
+
+ function func_sdp_verify_cep_header (in_hdr, exp_hdr : t_sdp_cep_header) return boolean;
-----------------------------------------------------------------------------
-- Subband equalizer (ESub)
@@ -89,8 +92,9 @@ package tb_sdp_pkg is
-- . sp_weight = (sp_esub_gain, sp_esub_phase)
-- . cross_phasor = (cross_subband_ampl, cross_subband_phase)
-- . cross_weight = (cross_esub_gain, cross_esub_phase)
- function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
- cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
+ function func_sdp_subband_equalizer (
+ sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
+ cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
return t_real_arr; -- 0:3 = ampl, phase, re, im
@@ -100,16 +104,17 @@ package tb_sdp_pkg is
-- Model the SDP beamformer for one signal input (sp) and nof_rem remnant signal inputs (rem)
-- . for local beamformer on one node use nof_rem = S_pn - 1
-- . for remote beamformer with nof_rn ring nodes use nof_rem = nof_rn * S_pn - 1
- function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
- rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
- nof_rem : natural)
+ function func_sdp_beamformer (
+ sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
+ rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
+ nof_rem : natural)
return t_real_arr; -- 0:3 = ampl, phase, re, im
end package tb_sdp_pkg;
package body tb_sdp_pkg is
- function func_sdp_gn_index_to_mac_15_0(gn_index : natural) return std_logic_vector is
+ function func_sdp_gn_index_to_mac_15_0 (gn_index : natural) return std_logic_vector is
constant c_unb_nr : natural := gn_index / 4; -- 4 PN per Uniboard2
constant c_node_nr : natural := gn_index mod 4;
constant c_mac_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr, 8);
@@ -117,7 +122,7 @@ package body tb_sdp_pkg is
return c_mac_15_0;
end func_sdp_gn_index_to_mac_15_0;
- function func_sdp_gn_index_to_ip_15_0(gn_index : natural) return std_logic_vector is
+ function func_sdp_gn_index_to_ip_15_0 (gn_index : natural) return std_logic_vector is
constant c_unb_nr : natural := gn_index / 4; -- 4 PN per Uniboard2
constant c_node_nr : natural := gn_index mod 4;
constant c_ip_15_0 : std_logic_vector(15 downto 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr + 1, 8); -- +1 to avoid IP = *.*.*.0
@@ -125,18 +130,19 @@ package body tb_sdp_pkg is
return c_ip_15_0;
end func_sdp_gn_index_to_ip_15_0;
- function func_sdp_compose_stat_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- g_statistics_type : string;
- weighted_subbands_flag : std_logic;
- gn_index : natural;
- nof_block_per_sync : natural;
- sst_signal_input : natural;
- beamlet_index : natural;
- subband_index : natural;
- xst_signal_input_A : natural;
- xst_signal_input_B : natural;
- dp_bsn : natural) return t_sdp_stat_header is
+ function func_sdp_compose_stat_header (
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ g_statistics_type : string;
+ weighted_subbands_flag : std_logic;
+ gn_index : natural;
+ nof_block_per_sync : natural;
+ sst_signal_input : natural;
+ beamlet_index : natural;
+ subband_index : natural;
+ xst_signal_input_A : natural;
+ xst_signal_input_B : natural;
+ dp_bsn : natural) return t_sdp_stat_header is
-- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_mac_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_mac_15_0(gn_index);
constant c_ip_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_ip_15_0(gn_index);
@@ -213,7 +219,7 @@ package body tb_sdp_pkg is
return v_hdr;
end func_sdp_compose_stat_header;
- function func_sdp_verify_stat_header(g_statistics_type : string; in_hdr, exp_hdr : t_sdp_stat_header) return boolean is
+ function func_sdp_verify_stat_header (g_statistics_type : string; in_hdr, exp_hdr : t_sdp_stat_header) return boolean is
begin
-- eth header
assert in_hdr.eth.dst_mac = exp_hdr.eth.dst_mac report "Wrong " & g_statistics_type & " eth.dst_mac" severity ERROR;
@@ -281,14 +287,15 @@ package body tb_sdp_pkg is
return true;
end func_sdp_verify_stat_header;
- function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
- ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header is
+ function func_sdp_compose_cep_header (
+ ip_src_addr : std_logic_vector;
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header is
-- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_mac_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_mac_15_0(gn_index);
variable v_hdr : t_sdp_cep_header;
@@ -345,13 +352,14 @@ package body tb_sdp_pkg is
return v_hdr;
end func_sdp_compose_cep_header;
- function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header is
+ function func_sdp_compose_cep_header (
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header is
-- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_ip_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_ip_15_0(gn_index);
constant c_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & c_ip_15_0;
@@ -366,7 +374,7 @@ package body tb_sdp_pkg is
dp_bsn);
end func_sdp_compose_cep_header;
- function func_sdp_verify_cep_header(in_hdr, exp_hdr : t_sdp_cep_header) return boolean is
+ function func_sdp_verify_cep_header (in_hdr, exp_hdr : t_sdp_cep_header) return boolean is
variable v_beamlet_index : natural;
begin
-- eth header
@@ -424,8 +432,9 @@ package body tb_sdp_pkg is
end func_sdp_verify_cep_header;
- function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
- cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
+ function func_sdp_subband_equalizer (
+ sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
+ cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
return t_real_arr is -- 0:3 = ampl, phase, re, im
variable v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : real;
variable v_cross_ampl, v_cross_phase, v_cross_re, v_cross_im : real;
@@ -449,9 +458,10 @@ package body tb_sdp_pkg is
end;
- function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
- rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
- nof_rem : natural)
+ function func_sdp_beamformer (
+ sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
+ rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
+ nof_rem : natural)
return t_real_arr is -- 0:3 = ampl, phase, re, im
variable v_nof_rem : real := real(nof_rem); -- BF for one sp and nof_rem remnant signal inputs
variable v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : real;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 5dccef4959..ea8935e4f0 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -37,25 +37,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_str_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
-use work.tb_sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
+ use work.tb_sdp_pkg.all;
entity tb_sdp_statistics_offload is
generic (
-- All
g_fast_mm_clk : boolean := true; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
+ -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
g_statistics_type : string := "XST";
g_offload_time : natural := 50;
g_reverse_word_order : boolean := true; -- when TRUE then stream LSB word after MSB word.
@@ -100,22 +100,32 @@ architecture tb of tb_sdp_statistics_offload is
constant c_exp_ip_header_checksum : natural := 0; -- 0 in this local tb, calculated by IO eth when used in design
- constant c_exp_sdp_info : t_sdp_info := (TO_UVEC(7, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"FFFFFFFF", -- observation_id
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
-
- constant c_exp_ring_info : t_ring_info := (TO_UVEC(g_O_rn, 8), -- GN index of first GN in ring
- TO_UVEC(g_N_rn, 8), -- number of GN in ring
- '0', -- use_cable_to_next_rn
- '0' -- use_cable_to_previous_rn
- );
+ constant c_exp_sdp_info : t_sdp_info := (
+ TO_UVEC(
+ 7,
+ 6), -- antenna_field_index
+ TO_UVEC(
+ 601,
+ 10), -- station_id
+ '0', -- antenna_band_index
+ x"FFFFFFFF", -- observation_id
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
+
+ constant c_exp_ring_info : t_ring_info := (
+ TO_UVEC(
+ g_O_rn,
+ 8), -- GN index of first GN in ring
+ TO_UVEC(
+ g_N_rn,
+ 8), -- number of GN in ring
+ '0', -- use_cable_to_next_rn
+ '0' -- use_cable_to_previous_rn
+ );
constant c_beamlet_index : natural := g_beamset_id * c_sdp_S_sub_bf;
@@ -490,7 +500,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 1024 32bit Words
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 512 Statistic values
D := S; -- range c_mm_nof_data = 512 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 1
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 1
U := S; -- range c_sdp_N_sub = 512 SST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = 12 = c_sdp_S_pn packets
@@ -522,7 +532,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 1952
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 976 Statistic values
D := S / c_sdp_N_pol_bf; -- range c_mm_nof_data = 488 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_sdp_N_pol_bf
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_sdp_N_pol_bf
B := D; -- range c_sdp_S_sub_bf = 488 dual polarization BST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = 1 packet
@@ -563,7 +573,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 576
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 288 Statistic values
D := S / c_nof_complex; -- range c_mm_nof_data = 144 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
X := D; -- range c_sdp_X_sq = 144 complex XST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = c_nof_used_P_sq * g_nof_crosslets packets
@@ -598,100 +608,100 @@ begin
end process;
u_ram: entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_ram_buf
- )
- port map (
- -- MM write port clock domain.
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_wr_en,
- wr_dat_a => ram_wr_data,
- adr_a => ram_wr_addr,
-
- -- DP read only port clock domain.
- rst_b => mm_rst,
- clk_b => mm_clk,
- adr_b => master_mosi.address(c_ram_buf.adr_w - 1 downto 0),
- rd_en_b => master_mosi.rd,
- rd_dat_b => master_miso.rddata(c_ram_buf.dat_w - 1 downto 0),
- rd_val_b => master_miso.rdval
- );
+ generic map (
+ g_ram => c_ram_buf
+ )
+ port map (
+ -- MM write port clock domain.
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_wr_en,
+ wr_dat_a => ram_wr_data,
+ adr_a => ram_wr_addr,
+
+ -- DP read only port clock domain.
+ rst_b => mm_rst,
+ clk_b => mm_clk,
+ adr_b => master_mosi.address(c_ram_buf.adr_w - 1 downto 0),
+ rd_en_b => master_mosi.rd,
+ rd_dat_b => master_miso.rddata(c_ram_buf.dat_w - 1 downto 0),
+ rd_val_b => master_miso.rdval
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
-
- snk_in_arr(0) => sdp_offload_sosi,
- snk_out_arr(0) => sdp_offload_siso,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
+
+ snk_in_arr(0) => sdp_offload_sosi,
+ snk_out_arr(0) => sdp_offload_siso,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
-- SDP info
u_dut: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => g_statistics_type,
- g_offload_time => g_offload_time,
- g_reverse_word_order => g_reverse_word_order,
- g_beamset_id => g_beamset_id,
- g_P_sq => g_P_sq,
- g_crosslets_direction => g_crosslets_direction
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- MM
- master_mosi => master_mosi,
- master_miso => master_miso,
-
- reg_enable_mosi => enable_mosi,
- reg_enable_miso => enable_miso,
-
- reg_hdr_dat_mosi => hdr_dat_mosi,
- reg_hdr_dat_miso => hdr_dat_miso,
-
- -- ST
- in_sosi => in_sosi,
- new_interval => new_interval,
-
- out_sosi => sdp_offload_sosi,
- out_siso => sdp_offload_siso,
-
- -- Inputs from other blocks
- eth_src_mac => c_node_eth_src_mac,
- udp_src_port => c_node_udp_src_port,
- ip_src_addr => c_node_ip_src_addr,
-
- gn_index => gn_index,
- ring_info => c_exp_ring_info,
- sdp_info => c_exp_sdp_info,
- weighted_subbands_flag => weighted_subbands_flag,
-
- nof_crosslets => c_mm_nof_crosslets,
- prev_crosslets_info_rec => in_crosslets_info_rec
- );
+ generic map (
+ g_statistics_type => g_statistics_type,
+ g_offload_time => g_offload_time,
+ g_reverse_word_order => g_reverse_word_order,
+ g_beamset_id => g_beamset_id,
+ g_P_sq => g_P_sq,
+ g_crosslets_direction => g_crosslets_direction
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- MM
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+
+ reg_enable_mosi => enable_mosi,
+ reg_enable_miso => enable_miso,
+
+ reg_hdr_dat_mosi => hdr_dat_mosi,
+ reg_hdr_dat_miso => hdr_dat_miso,
+
+ -- ST
+ in_sosi => in_sosi,
+ new_interval => new_interval,
+
+ out_sosi => sdp_offload_sosi,
+ out_siso => sdp_offload_siso,
+
+ -- Inputs from other blocks
+ eth_src_mac => c_node_eth_src_mac,
+ udp_src_port => c_node_udp_src_port,
+ ip_src_addr => c_node_ip_src_addr,
+
+ gn_index => gn_index,
+ ring_info => c_exp_ring_info,
+ sdp_info => c_exp_sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag,
+
+ nof_crosslets => c_mm_nof_crosslets,
+ prev_crosslets_info_rec => in_crosslets_info_rec
+ );
-- Verify crosslets_info functions
assert c_crosslets_info_rec = func_sdp_map_crosslets_info(c_crosslets_info_slv) report "Error in func_sdp_map_crosslets_info()" severity FAILURE;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
index 50b2e2ec7a..7424d9fc11 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
@@ -28,7 +28,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_sdp_statistics_offload is
end tb_tb_sdp_statistics_offload;
@@ -37,22 +37,22 @@ architecture tb of tb_tb_sdp_statistics_offload is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- -- All
--- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
--- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
--- g_statistics_type : STRING := "SST";
--- g_offload_time : NATURAL := 500;
--- g_reverse_word_order : BOOLEAN := TRUE -- when TRUE then stream LSB word after MSB word.
--- g_gn_index : NATURAL := 1; -- global node (GN) index, use > 0 to see effect of g_offload_time
--- g_nof_sync : NATURAL := 3;
--- -- BST
--- g_beamset_id : NATURAL := 0;
--- -- XST
--- g_O_rn : NATURAL := 0; -- GN index of first ring node (RN)
--- g_N_rn : NATURAL := 16; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
--- g_P_sq : NATURAL := c_sdp_P_sq
--- g_nof_crosslets : NATURAL := 1;
--- g_crosslets_direction : INTEGER := 1; -- +1 or -1
+ -- -- All
+ -- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
+ -- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
+ -- g_statistics_type : STRING := "SST";
+ -- g_offload_time : NATURAL := 500;
+ -- g_reverse_word_order : BOOLEAN := TRUE -- when TRUE then stream LSB word after MSB word.
+ -- g_gn_index : NATURAL := 1; -- global node (GN) index, use > 0 to see effect of g_offload_time
+ -- g_nof_sync : NATURAL := 3;
+ -- -- BST
+ -- g_beamset_id : NATURAL := 0;
+ -- -- XST
+ -- g_O_rn : NATURAL := 0; -- GN index of first ring node (RN)
+ -- g_N_rn : NATURAL := 16; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
+ -- g_P_sq : NATURAL := c_sdp_P_sq
+ -- g_nof_crosslets : NATURAL := 1;
+ -- g_crosslets_direction : INTEGER := 1; -- +1 or -1
u_sst : entity work.tb_sdp_statistics_offload generic map( true, "SST", 50, true, 3, 3);
u_sst_no_reverse : entity work.tb_sdp_statistics_offload generic map( true, "SST", 50, false, 3, 3);
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
index a8639774e0..d6bbd8a5fb 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
@@ -31,16 +31,16 @@
-- vivado using the AXI AMM Bridge IP.
library IEEE, common_lib, dp_lib, axi4_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_components_pkg.all;
-use axi4_lib.axi4_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use work.rdma_demo_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_components_pkg.all;
+ use axi4_lib.axi4_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use work.rdma_demo_pkg.all;
entity rdma_demo_eth_tester_wrapper is
port (
@@ -147,7 +147,7 @@ entity rdma_demo_eth_tester_wrapper is
reg_strobe_total_count_rx_avs_write : in std_logic;
reg_strobe_total_count_rx_avs_writedata : in std_logic_vector(32 - 1 downto 0)
- );
+ );
end rdma_demo_eth_tester_wrapper;
@@ -186,91 +186,91 @@ architecture str of rdma_demo_eth_tester_wrapper is
begin
u_eth_tester : entity eth_lib.eth_tester
- generic map (
- g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
- g_nof_octet_output => c_rdma_demo_nof_octet_output_100gbe,
- g_use_eth_header => false,
- g_use_ip_udp_header => false,
- g_use_dp_header => true,
- g_hdr_field_arr => c_rdma_demo_dp_hdr_field_arr,
- g_hdr_field_sel => c_rdma_demo_dp_hdr_field_sel,
- g_remove_crc => false
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => tx_udp_sosi_arr,
- tx_udp_siso_arr => tx_udp_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
- reg_dp_split_copi => reg_dp_split_copi,
- reg_dp_split_cipo => reg_dp_split_cipo,
-
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
+ generic map (
+ g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
+ g_nof_octet_output => c_rdma_demo_nof_octet_output_100gbe,
+ g_use_eth_header => false,
+ g_use_ip_udp_header => false,
+ g_use_dp_header => true,
+ g_hdr_field_arr => c_rdma_demo_dp_hdr_field_arr,
+ g_hdr_field_sel => c_rdma_demo_dp_hdr_field_sel,
+ g_remove_crc => false
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ reg_dp_split_copi => reg_dp_split_copi,
+ reg_dp_split_cipo => reg_dp_split_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
-- DP to AXI4
u_axi4_tx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- dp_rst => st_rst,
-
- dp_in_sosi => tx_udp_sosi_arr(0),
- dp_in_siso => tx_udp_siso_arr(0),
-
- axi4_out_sosi => tx_udp_axi4_sosi,
- axi4_out_siso => tx_udp_axi4_siso
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ dp_rst => st_rst,
+
+ dp_in_sosi => tx_udp_sosi_arr(0),
+ dp_in_siso => tx_udp_siso_arr(0),
+
+ axi4_out_sosi => tx_udp_axi4_sosi,
+ axi4_out_siso => tx_udp_axi4_siso
+ );
u_axi4_rx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- axi4_in_sosi => rx_udp_axi4_sosi,
- axi4_in_siso => rx_udp_axi4_siso,
-
- dp_out_sosi => rx_udp_sosi_arr(0),
- dp_out_siso => rx_udp_siso_arr(0)
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ axi4_in_sosi => rx_udp_axi4_sosi,
+ axi4_in_siso => rx_udp_axi4_siso,
+
+ dp_out_sosi => rx_udp_sosi_arr(0),
+ dp_out_siso => rx_udp_siso_arr(0)
+ );
-- Wire Records to IN/OUT ports.
-- tx_udp
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
index 438bd8acd6..e881956efd 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
@@ -23,11 +23,11 @@
-- Description:
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
package rdma_demo_pkg is
@@ -57,10 +57,10 @@ package rdma_demo_pkg is
constant c_rdma_demo_dp_hdr_field_sel : std_logic_vector(c_rdma_demo_dp_nof_hdr_fields - 1 downto 0) := "0100";
constant c_rdma_demo_dp_hdr_field_arr : t_common_field_arr(c_rdma_demo_dp_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("dp_length" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_reserved"), "RW", 15, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
+ ( field_name_pad("dp_length" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_reserved"), "RW", 15, field_default(0) ),
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
);
constant c_rdma_demo_dp_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_demo_dp_hdr_field_arr, c_word_w));
constant c_rdma_demo_dp_reg_hdr_dat_addr_span : natural := 2**c_rdma_demo_dp_reg_hdr_dat_addr_w;
@@ -74,43 +74,43 @@ package rdma_demo_pkg is
constant c_rdma_demo_roce_hdr_field_sel : std_logic_vector(c_rdma_demo_roce_nof_hdr_fields - 1 downto 0) := "111011111001" & "0100" & "1111111111111" & "111" & "1";
constant c_rdma_demo_roce_hdr_field_arr : t_common_field_arr(c_rdma_demo_roce_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_eth_tester_ip_dst_addr
-
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_eth_tester_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
-
- ( field_name_pad("bth_opcode" ), "RW", 8, field_default(0) ),
- ( field_name_pad("bth_se" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_m" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_pad" ), "RW", 2, field_default(0) ),
- ( field_name_pad("bth_tver" ), "RW", 4, field_default(0) ),
- ( field_name_pad("bth_partition_key" ), "RW", 16, field_default(0) ),
- ( field_name_pad("bth_fres" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_bres" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_reserved_a" ), "RW", 6, field_default(0) ),
- ( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
- ( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
- ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
-
- ( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
- ( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
- ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) ),
-
- ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_eth_tester_ip_dst_addr
+
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_eth_tester_udp_dst_port
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("bth_opcode" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("bth_se" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_m" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_pad" ), "RW", 2, field_default(0) ),
+ ( field_name_pad("bth_tver" ), "RW", 4, field_default(0) ),
+ ( field_name_pad("bth_partition_key" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("bth_fres" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_bres" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_reserved_a" ), "RW", 6, field_default(0) ),
+ ( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
+ ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
+
+ ( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
+ ( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) ),
+
+ ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
);
constant c_rdma_demo_roce_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_demo_roce_hdr_field_arr, c_word_w));
constant c_rdma_demo_roce_reg_hdr_dat_addr_span : natural := 2**c_rdma_demo_roce_reg_hdr_dat_addr_w;
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
index 7eab44990b..8786b5b195 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
@@ -32,16 +32,16 @@
-- vivado using the AXI AMM Bridge IP.
library IEEE, common_lib, dp_lib, axi4_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_components_pkg.all;
-use axi4_lib.axi4_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use work.rdma_demo_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_components_pkg.all;
+ use axi4_lib.axi4_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use work.rdma_demo_pkg.all;
entity rdma_demo_roce_tester_wrapper is
port (
@@ -148,7 +148,7 @@ entity rdma_demo_roce_tester_wrapper is
reg_strobe_total_count_rx_avs_write : in std_logic;
reg_strobe_total_count_rx_avs_writedata : in std_logic_vector(32 - 1 downto 0)
- );
+ );
end rdma_demo_roce_tester_wrapper;
@@ -187,94 +187,94 @@ architecture str of rdma_demo_roce_tester_wrapper is
begin
u_eth_tester : entity eth_lib.eth_tester
- generic map (
- g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
- g_nof_octet_output => c_rdma_demo_nof_octet_output_100gbe,
- g_use_eth_header => false,
- g_use_ip_udp_header => true,
- g_use_dp_header => false,
- g_hdr_calc_ip_crc => true,
- g_hdr_field_arr => c_rdma_demo_roce_hdr_field_arr,
- g_hdr_field_sel => c_rdma_demo_roce_hdr_field_sel,
- -- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.
- g_hdr_app_len => c_rdma_demo_roce_hdr_len + c_rdma_demo_roce_icrc_len,
- g_remove_crc => false
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => tx_udp_sosi_arr,
- tx_udp_siso_arr => tx_udp_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
- reg_dp_split_copi => reg_dp_split_copi,
- reg_dp_split_cipo => reg_dp_split_cipo,
-
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
+ generic map (
+ g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
+ g_nof_octet_output => c_rdma_demo_nof_octet_output_100gbe,
+ g_use_eth_header => false,
+ g_use_ip_udp_header => true,
+ g_use_dp_header => false,
+ g_hdr_calc_ip_crc => true,
+ g_hdr_field_arr => c_rdma_demo_roce_hdr_field_arr,
+ g_hdr_field_sel => c_rdma_demo_roce_hdr_field_sel,
+ -- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.
+ g_hdr_app_len => c_rdma_demo_roce_hdr_len + c_rdma_demo_roce_icrc_len,
+ g_remove_crc => false
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ reg_dp_split_copi => reg_dp_split_copi,
+ reg_dp_split_cipo => reg_dp_split_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
-- DP to AXI4
u_axi4_tx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- dp_rst => st_rst,
-
- dp_in_sosi => tx_udp_sosi_arr(0),
- dp_in_siso => tx_udp_siso_arr(0),
-
- axi4_out_sosi => tx_udp_axi4_sosi,
- axi4_out_siso => tx_udp_axi4_siso
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ dp_rst => st_rst,
+
+ dp_in_sosi => tx_udp_sosi_arr(0),
+ dp_in_siso => tx_udp_siso_arr(0),
+
+ axi4_out_sosi => tx_udp_axi4_sosi,
+ axi4_out_siso => tx_udp_axi4_siso
+ );
u_axi4_rx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- axi4_in_sosi => rx_udp_axi4_sosi,
- axi4_in_siso => rx_udp_axi4_siso,
-
- dp_out_sosi => rx_udp_sosi_arr(0),
- dp_out_siso => rx_udp_siso_arr(0)
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ axi4_in_sosi => rx_udp_axi4_sosi,
+ axi4_in_siso => rx_udp_axi4_siso,
+
+ dp_out_sosi => rx_udp_sosi_arr(0),
+ dp_out_siso => rx_udp_siso_arr(0)
+ );
-- Wire Records to IN/OUT ports.
-- tx_udp
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
index b04f2c161c..6ebe011e8c 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
@@ -22,20 +22,20 @@
-- . Collection of functions for the ring design
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package ring_pkg is
- function nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return integer;
- function nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector; -- return vector length is same as hops vector length
+ function nof_hops_to_source_rn (hops, this_rn, N_rn, lane_dir : natural) return integer;
+ function nof_hops_to_source_rn (hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector; -- return vector length is same as hops vector length
end ring_pkg;
package body ring_pkg is
- function nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return integer is
+ function nof_hops_to_source_rn (hops, this_rn, N_rn, lane_dir : natural) return integer is
variable v_source_rn : integer;
begin
if lane_dir > 0 then
@@ -56,7 +56,7 @@ package body ring_pkg is
return v_source_rn;
end;
- function nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector is
+ function nof_hops_to_source_rn (hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector is
begin
return TO_SVEC(nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(N_rn), TO_UINT(N_rn), lane_dir),hops'length);
end;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
index 9597c5e56d..dca1abe9d2 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
@@ -49,18 +49,18 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_ring_bsp is
end tb_lofar2_unb2b_ring_bsp;
@@ -159,56 +159,56 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_ring_bsp : entity work.top
- generic map (
- g_design_name => "lofar2_unb2b_ring_bsp",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_0_RX => si_lpbk_0,
- QSFP_0_TX => si_lpbk_0,
- -- ring transceivers
- RING_0_RX => si_lpbk_2,
- RING_0_TX => si_lpbk_1,
- RING_1_RX => si_lpbk_1,
- RING_1_TX => si_lpbk_2,
-
- -- LEDs
- QSFP_LED => open
-
- );
-
- u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ generic map (
+ g_design_name => "lofar2_unb2b_ring_bsp",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => si_lpbk_0,
+ QSFP_0_TX => si_lpbk_0,
+ -- ring transceivers
+ RING_0_RX => si_lpbk_2,
+ RING_0_TX => si_lpbk_1,
+ RING_1_RX => si_lpbk_1,
+ RING_1_TX => si_lpbk_2,
+
+ -- LEDs
+ QSFP_LED => open
+
+ );
+
+ u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
port map (
refclk_644 => SA_CLK,
rst_in => pps_rst,
@@ -218,7 +218,7 @@ begin
rst_312 => open
);
- u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
+ u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_sim => true,
g_sim_level => 1,
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index f7b313a11e..04e1b56dd1 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -31,19 +31,19 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, tech_pll_lib, dp_lib, diag_lib, mm_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.ring_pkg.all;
-use work.top_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.ring_pkg.all;
+ use work.top_components_pkg.all;
entity top is
generic (
@@ -400,21 +400,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_unb2b_board_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
- --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX -- ,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX -- ,
--QSFP_LED => QSFP_LED
- );
+ );
------------------------
-- qsfp LEDs controller
@@ -422,21 +422,21 @@ begin
unb2b_board_qsfp_leds_tx_src_in_arr(0).xon <= ta2_unb2b_10GbE_qsfp_snk_out_arr(0).xon;
u_unb2b_board_qsfp_leds : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
gen_leds : for i in 0 to c_nof_qsfp_bus - 1 generate
QSFP_LED(i * 2) <= qsfp_green_led_arr(i);
@@ -464,17 +464,17 @@ begin
-- PLL
--------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg
- )
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => clk_156,
- clk_312 => clk_312,
- rst_156 => rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg
+ )
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => clk_156,
+ clk_312 => clk_312,
+ rst_156 => rst_156,
+ rst_312 => open
+ );
----------
-- 10GbE
@@ -517,129 +517,129 @@ begin
-- tr_10GbE
u_ta2_unb2b_10GbE : entity ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
- generic map (
- g_nof_mac => c_max_nof_mac,
- g_use_err => true,
- g_use_pll => true
- )
- port map (
- mm_clk => '0', -- mm_clk,
- mm_rst => mm_rst,
-
- clk_ref_r => SA_CLK,
-
- tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- src_out_arr => ta2_unb2b_10GbE_src_out_arr,
- src_in_arr => ta2_unb2b_10GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
- );
+ generic map (
+ g_nof_mac => c_max_nof_mac,
+ g_use_err => true,
+ g_use_pll => true
+ )
+ port map (
+ mm_clk => '0', -- mm_clk,
+ mm_rst => mm_rst,
+
+ clk_ref_r => SA_CLK,
+
+ tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ src_out_arr => ta2_unb2b_10GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_10GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
+ );
--------------------------------------
-- Monitoring & Control UNB protocol
--------------------------------------
u_ta2_unb2b_mm_io : entity ta2_unb2b_mm_io_lib.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => true
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- mm_mosi => reg_ta2_unb2b_mm_io_mosi,
- mm_miso => reg_ta2_unb2b_mm_io_miso,
-
- snk_in => ta2_unb2b_mm_io_snk_in,
- snk_out => ta2_unb2b_mm_io_snk_out,
- src_out => ta2_unb2b_mm_io_src_out,
- src_in => ta2_unb2b_mm_io_src_in
- );
+ generic map(
+ g_use_opencl => true
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ mm_mosi => reg_ta2_unb2b_mm_io_mosi,
+ mm_miso => reg_ta2_unb2b_mm_io_miso,
+
+ snk_in => ta2_unb2b_mm_io_snk_in,
+ snk_out => ta2_unb2b_mm_io_snk_out,
+ src_out => ta2_unb2b_mm_io_src_out,
+ src_in => ta2_unb2b_mm_io_src_in
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for from/to lane sosi
-----------------------------------------------------------------------------
u_ta2_channel_cross_lanes : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
- dp_src_out_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- dp_snk_out_arr => to_lane_siso_arr(g_nof_lanes - 1 downto 0),
- dp_snk_in_arr => to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_src_out_arr => kernel_to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- kernel_src_in_arr => kernel_to_lane_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_out_arr => kernel_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+ dp_src_out_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ dp_snk_out_arr => to_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ dp_snk_in_arr => to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_src_out_arr => kernel_to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ kernel_src_in_arr => kernel_to_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_out_arr => kernel_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for bs sosi
-----------------------------------------------------------------------------
u_ta2_channel_cross_bs_sosi : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => 1,
- g_nof_bytes => c_word_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- dp_snk_in_arr(0) => bs_sosi,
- kernel_src_out_arr(0) => kernel_bs_sosi
- );
+ generic map(
+ g_nof_streams => 1,
+ g_nof_bytes => c_word_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ dp_snk_in_arr(0) => bs_sosi,
+ kernel_src_out_arr(0) => kernel_bs_sosi
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for rx_monitors
-----------------------------------------------------------------------------
u_ta2_channel_cross_rx_monitor : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- dp_src_out_arr => rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_snk_out_arr => kernel_rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ dp_src_out_arr => rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_snk_out_arr => kernel_rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for tx_monitors
@@ -650,27 +650,27 @@ begin
end generate;
u_ta2_channel_cross_tx_monitor : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- dp_src_out_arr => tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_snk_out_arr => kernel_tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ dp_src_out_arr => tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_snk_out_arr => kernel_tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
rx_monitor_siso_arr <= dp_demux_rx_monitor_siso_arr;
tx_monitor_siso_arr <= dp_demux_tx_monitor_siso_arr;
@@ -690,189 +690,189 @@ begin
-- demux rx_monitor inputs
-----------------------------------------------------------------------------
u_dp_demux_rx_monitor : entity dp_lib.dp_demux
- generic map(
- g_nof_output => g_nof_rx_monitors,
- g_sel_ctrl_invert => true
- )
- port map(
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_demux_rx_monitor_siso_arr(I),
- snk_in => dp_demux_rx_monitor_sosi_arr(I),
-
- src_in_arr => rx_monitor_siso_2arr(I),
- src_out_arr => rx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_output => g_nof_rx_monitors,
+ g_sel_ctrl_invert => true
+ )
+ port map(
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_demux_rx_monitor_siso_arr(I),
+ snk_in => dp_demux_rx_monitor_sosi_arr(I),
+
+ src_in_arr => rx_monitor_siso_2arr(I),
+ src_out_arr => rx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- rx_monitors
-----------------------------------------------------------------------------
u_mms_dp_bsn_monitor_v2_rx : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map(
- g_nof_streams => g_nof_rx_monitors
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_rx_mosi_arr(I),
- reg_miso => reg_bsn_monitor_v2_rx_miso_arr(I),
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- ref_sync => bs_sosi.sync,
-
- in_siso_arr => rx_monitor_siso_2arr(I),
- in_sosi_arr => rx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_streams => g_nof_rx_monitors
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_rx_mosi_arr(I),
+ reg_miso => reg_bsn_monitor_v2_rx_miso_arr(I),
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ ref_sync => bs_sosi.sync,
+
+ in_siso_arr => rx_monitor_siso_2arr(I),
+ in_sosi_arr => rx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- demux tx_monitor inputs
-----------------------------------------------------------------------------
u_dp_demux_tx_monitor : entity dp_lib.dp_demux
- generic map(
- g_nof_output => g_nof_tx_monitors,
- g_sel_ctrl_invert => true
- )
- port map(
- rst => st_rst,
- clk => st_clk,
+ generic map(
+ g_nof_output => g_nof_tx_monitors,
+ g_sel_ctrl_invert => true
+ )
+ port map(
+ rst => st_rst,
+ clk => st_clk,
- snk_out => dp_demux_tx_monitor_siso_arr(I),
- snk_in => dp_demux_tx_monitor_sosi_arr(I),
+ snk_out => dp_demux_tx_monitor_siso_arr(I),
+ snk_in => dp_demux_tx_monitor_sosi_arr(I),
- src_in_arr => tx_monitor_siso_2arr(I),
- src_out_arr => tx_monitor_sosi_2arr(I)
- );
+ src_in_arr => tx_monitor_siso_2arr(I),
+ src_out_arr => tx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- tx_monitors
-----------------------------------------------------------------------------
u_mms_dp_bsn_monitor_v2_tx : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map(
- g_nof_streams => g_nof_tx_monitors
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_tx_mosi_arr(I),
- reg_miso => reg_bsn_monitor_v2_tx_miso_arr(I),
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- ref_sync => bs_sosi.sync,
-
- in_siso_arr => tx_monitor_siso_2arr(I),
- in_sosi_arr => tx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_streams => g_nof_tx_monitors
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_tx_mosi_arr(I),
+ reg_miso => reg_bsn_monitor_v2_tx_miso_arr(I),
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ ref_sync => bs_sosi.sync,
+
+ in_siso_arr => tx_monitor_siso_2arr(I),
+ in_sosi_arr => tx_monitor_sosi_2arr(I)
+ );
end generate;
u_common_mem_mux_rx_monitors : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_lanes,
- g_mult_addr_w => ceil_log2(g_nof_rx_monitors) + 3
- )
- port map (
- mosi => reg_bsn_monitor_v2_rx_mosi,
- miso => reg_bsn_monitor_v2_rx_miso,
- mosi_arr => reg_bsn_monitor_v2_rx_mosi_arr,
- miso_arr => reg_bsn_monitor_v2_rx_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_lanes,
+ g_mult_addr_w => ceil_log2(g_nof_rx_monitors) + 3
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_rx_mosi,
+ miso => reg_bsn_monitor_v2_rx_miso,
+ mosi_arr => reg_bsn_monitor_v2_rx_mosi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_miso_arr
+ );
u_common_mem_mux_tx_monitors : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_lanes,
- g_mult_addr_w => ceil_log2(g_nof_tx_monitors) + 3
- )
- port map (
- mosi => reg_bsn_monitor_v2_tx_mosi,
- miso => reg_bsn_monitor_v2_tx_miso,
- mosi_arr => reg_bsn_monitor_v2_tx_mosi_arr,
- miso_arr => reg_bsn_monitor_v2_tx_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_lanes,
+ g_mult_addr_w => ceil_log2(g_nof_tx_monitors) + 3
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_tx_mosi,
+ miso => reg_bsn_monitor_v2_tx_miso,
+ mosi_arr => reg_bsn_monitor_v2_tx_mosi_arr,
+ miso_arr => reg_bsn_monitor_v2_tx_miso_arr
+ );
-----------------------------------------------------------------------------
-- Design part, mms_diag_block_gen
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_nof_lanes,
- g_use_bg_buffer_ram => true,
- g_buf_dat_w => 32, -- BG is limited to 32 bits data
- g_buf_addr_w => 7,
- g_file_name_prefix => "data/bf_in_data"
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
- en_sync => st_pps,
-
- -- MM interface
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => reg_bg_ctrl_miso,
- ram_bg_data_mosi => ram_bg_data_mosi,
- ram_bg_data_miso => ram_bg_data_miso,
-
- -- ST interface
- out_siso_arr => local_siso_arr,
- out_sosi_arr => local_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_use_bg_buffer_ram => true,
+ g_buf_dat_w => 32, -- BG is limited to 32 bits data
+ g_buf_addr_w => 7,
+ g_file_name_prefix => "data/bf_in_data"
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ en_sync => st_pps,
+
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => reg_bg_ctrl_miso,
+ ram_bg_data_mosi => ram_bg_data_mosi,
+ ram_bg_data_miso => ram_bg_data_miso,
+
+ -- ST interface
+ out_siso_arr => local_siso_arr,
+ out_sosi_arr => local_sosi_arr
+ );
bs_sosi <= local_sosi_arr(0);
u_mms_dp_xonoff_bg : entity dp_lib.mms_dp_xonoff
- generic map(
- g_nof_streams => g_nof_lanes,
- g_combine_streams => false,
- g_default_value => '0'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_bg_mosi,
- reg_miso => reg_dp_xonoff_bg_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- -- ST sinks
- snk_out_arr => local_siso_arr,
- snk_in_arr => local_sosi_arr,
- -- ST source
- src_in_arr => dp_xonoff_bg_siso_arr,
- src_out_arr => dp_xonoff_bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_combine_streams => false,
+ g_default_value => '0'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_bg_mosi,
+ reg_miso => reg_dp_xonoff_bg_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ -- ST sinks
+ snk_out_arr => local_siso_arr,
+ snk_in_arr => local_sosi_arr,
+ -- ST source
+ src_in_arr => dp_xonoff_bg_siso_arr,
+ src_out_arr => dp_xonoff_bg_sosi_arr
+ );
u_mms_dp_xonoff_from_lane : entity dp_lib.mms_dp_xonoff
- generic map(
- g_nof_streams => g_nof_lanes,
- g_combine_streams => false,
- g_default_value => '1'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_from_lane_mosi,
- reg_miso => reg_dp_xonoff_from_lane_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- -- ST sinks
- snk_out_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- snk_in_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- -- ST source
- src_in_arr => dp_xonoff_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- src_out_arr => dp_xonoff_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_combine_streams => false,
+ g_default_value => '1'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_from_lane_mosi,
+ reg_miso => reg_dp_xonoff_from_lane_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ -- ST sinks
+ snk_out_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ snk_in_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ -- ST source
+ src_in_arr => dp_xonoff_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ src_out_arr => dp_xonoff_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
gen_streams : for I in 0 to g_nof_lanes - 1 generate
-- Multiplex the inputs:
@@ -885,28 +885,28 @@ begin
mux_snk_in_2arr_2(I)(1) <= dp_xonoff_bg_sosi_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_technology => g_technology,
- -- MUX
- g_mode => 0,
- g_nof_input => 2,
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, 2), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
- snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
- -- ST source
- src_in => to_lane_siso_arr(I),
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ -- MUX
+ g_mode => 0,
+ g_nof_input => 2,
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, 2), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- ST source
+ src_in => to_lane_siso_arr(I),
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -915,263 +915,263 @@ begin
gn_index <= TO_UINT(ID(c_sdp_W_gn_id - 1 downto 0));
this_rn_id <= TO_UVEC(gn_index - TO_UINT(sdp_info.O_rn), c_sdp_W_gn_id);
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => st_clk,
- dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_rst => st_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => '1',
- fsub_type => '0',
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => '1',
+ fsub_type => '0',
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- Freeze wrapper instantiation
-----------------------------------------------------------------------------
gen_opencl: if g_sim = false generate
- freeze_wrapper_inst : freeze_wrapper
- port map(
- board_kernel_clk_clk => board_kernel_clk_clk,
- board_kernel_clk2x_clk => board_kernel_clk2x_clk,
- board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
- board_kernel_irq_irq => board_kernel_irq_irq,
- board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- board_kernel_cra_readdata => board_kernel_cra_readdata,
- board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- board_kernel_cra_burstcount => board_kernel_cra_burstcount,
- board_kernel_cra_writedata => board_kernel_cra_writedata,
- board_kernel_cra_address => board_kernel_cra_address,
- board_kernel_cra_write => board_kernel_cra_write,
- board_kernel_cra_read => board_kernel_cra_read,
- board_kernel_cra_byteenable => board_kernel_cra_byteenable,
- board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
-
- board_kernel_register_mem_address => board_kernel_register_mem_address,
- board_kernel_register_mem_clken => board_kernel_register_mem_clken,
- board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
- board_kernel_register_mem_write => board_kernel_register_mem_write,
- board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
- board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
-
- board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
- board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
- board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
-
- board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
- board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
- board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
- board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
- board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
-
- board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
- board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
- board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
- board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
-
- board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
- board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
- board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
- board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
-
- board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
- board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
- board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
- board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
-
- board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
- board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
- board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
- board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
-
- board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
-
- board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
- board_kernel_stream_src_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
- board_kernel_stream_snk_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
-
- board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
- board_kernel_stream_src_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
- board_kernel_stream_snk_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
- board_kernel_stream_src_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
- board_kernel_stream_snk_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
-
- board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_0_valid => kernel_to_lane_sosi_arr(0).valid,
- board_kernel_stream_src_lane_0_ready => kernel_to_lane_siso_arr(0).ready,
- board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_0_valid => kernel_from_lane_sosi_arr(0).valid,
- board_kernel_stream_snk_lane_0_ready => kernel_from_lane_siso_arr(0).ready,
-
- board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_1_valid => kernel_to_lane_sosi_arr(1).valid,
- board_kernel_stream_src_lane_1_ready => kernel_to_lane_siso_arr(1).ready,
- board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_1_valid => kernel_from_lane_sosi_arr(1).valid,
- board_kernel_stream_snk_lane_1_ready => kernel_from_lane_siso_arr(1).ready,
-
- board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_2_valid => kernel_to_lane_sosi_arr(2).valid,
- board_kernel_stream_src_lane_2_ready => kernel_to_lane_siso_arr(2).ready,
- board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_2_valid => kernel_from_lane_sosi_arr(2).valid,
- board_kernel_stream_snk_lane_2_ready => kernel_from_lane_siso_arr(2).ready,
-
- board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_3_valid => kernel_to_lane_sosi_arr(3).valid,
- board_kernel_stream_src_lane_3_ready => kernel_to_lane_siso_arr(3).ready,
- board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_3_valid => kernel_from_lane_sosi_arr(3).valid,
- board_kernel_stream_snk_lane_3_ready => kernel_from_lane_siso_arr(3).ready,
-
- board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_4_valid => kernel_to_lane_sosi_arr(4).valid,
- board_kernel_stream_src_lane_4_ready => kernel_to_lane_siso_arr(4).ready,
- board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_4_valid => kernel_from_lane_sosi_arr(4).valid,
- board_kernel_stream_snk_lane_4_ready => kernel_from_lane_siso_arr(4).ready,
-
- board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_5_valid => kernel_to_lane_sosi_arr(5).valid,
- board_kernel_stream_src_lane_5_ready => kernel_to_lane_siso_arr(5).ready,
- board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_5_valid => kernel_from_lane_sosi_arr(5).valid,
- board_kernel_stream_snk_lane_5_ready => kernel_from_lane_siso_arr(5).ready,
-
- board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_6_valid => kernel_to_lane_sosi_arr(6).valid,
- board_kernel_stream_src_lane_6_ready => kernel_to_lane_siso_arr(6).ready,
- board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_6_valid => kernel_from_lane_sosi_arr(6).valid,
- board_kernel_stream_snk_lane_6_ready => kernel_from_lane_siso_arr(6).ready,
-
- board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_7_valid => kernel_to_lane_sosi_arr(7).valid,
- board_kernel_stream_src_lane_7_ready => kernel_to_lane_siso_arr(7).ready,
- board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_7_valid => kernel_from_lane_sosi_arr(7).valid,
- board_kernel_stream_snk_lane_7_ready => kernel_from_lane_siso_arr(7).ready,
-
- board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_0_valid => kernel_rx_monitor_sosi_arr(0).valid,
- board_kernel_stream_snk_rx_monitor_0_ready => kernel_rx_monitor_siso_arr(0).ready,
- board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_0_valid => kernel_tx_monitor_sosi_arr(0).valid,
- board_kernel_stream_snk_tx_monitor_0_ready => kernel_tx_monitor_siso_arr(0).ready,
-
- board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_1_valid => kernel_rx_monitor_sosi_arr(1).valid,
- board_kernel_stream_snk_rx_monitor_1_ready => kernel_rx_monitor_siso_arr(1).ready,
- board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_1_valid => kernel_tx_monitor_sosi_arr(1).valid,
- board_kernel_stream_snk_tx_monitor_1_ready => kernel_tx_monitor_siso_arr(1).ready,
-
- board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_2_valid => kernel_rx_monitor_sosi_arr(2).valid,
- board_kernel_stream_snk_rx_monitor_2_ready => kernel_rx_monitor_siso_arr(2).ready,
- board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_2_valid => kernel_tx_monitor_sosi_arr(2).valid,
- board_kernel_stream_snk_tx_monitor_2_ready => kernel_tx_monitor_siso_arr(2).ready,
-
- board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_3_valid => kernel_rx_monitor_sosi_arr(3).valid,
- board_kernel_stream_snk_rx_monitor_3_ready => kernel_rx_monitor_siso_arr(3).ready,
- board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_3_valid => kernel_tx_monitor_sosi_arr(3).valid,
- board_kernel_stream_snk_tx_monitor_3_ready => kernel_tx_monitor_siso_arr(3).ready,
-
- board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_4_valid => kernel_rx_monitor_sosi_arr(4).valid,
- board_kernel_stream_snk_rx_monitor_4_ready => kernel_rx_monitor_siso_arr(4).ready,
- board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_4_valid => kernel_tx_monitor_sosi_arr(4).valid,
- board_kernel_stream_snk_tx_monitor_4_ready => kernel_tx_monitor_siso_arr(4).ready,
-
- board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_5_valid => kernel_rx_monitor_sosi_arr(5).valid,
- board_kernel_stream_snk_rx_monitor_5_ready => kernel_rx_monitor_siso_arr(5).ready,
- board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_5_valid => kernel_tx_monitor_sosi_arr(5).valid,
- board_kernel_stream_snk_tx_monitor_5_ready => kernel_tx_monitor_siso_arr(5).ready,
-
- board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_6_valid => kernel_rx_monitor_sosi_arr(6).valid,
- board_kernel_stream_snk_rx_monitor_6_ready => kernel_rx_monitor_siso_arr(6).ready,
- board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_6_valid => kernel_tx_monitor_sosi_arr(6).valid,
- board_kernel_stream_snk_tx_monitor_6_ready => kernel_tx_monitor_siso_arr(6).ready,
-
- board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_7_valid => kernel_rx_monitor_sosi_arr(7).valid,
- board_kernel_stream_snk_rx_monitor_7_ready => kernel_rx_monitor_siso_arr(7).ready,
- board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_7_valid => kernel_tx_monitor_sosi_arr(7).valid,
- board_kernel_stream_snk_tx_monitor_7_ready => kernel_tx_monitor_siso_arr(7).ready,
-
- board_kernel_stream_src_bs_data => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_bs_valid => kernel_bs_sosi.valid,
- board_kernel_stream_src_bs_ready => OPEN,
-
- board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w - 1 downto 0),
- board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
- board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
- board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w - 1 downto 0),
- board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
- board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready
-
- );
+ freeze_wrapper_inst : freeze_wrapper
+ port map(
+ board_kernel_clk_clk => board_kernel_clk_clk,
+ board_kernel_clk2x_clk => board_kernel_clk2x_clk,
+ board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
+ board_kernel_irq_irq => board_kernel_irq_irq,
+ board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ board_kernel_cra_readdata => board_kernel_cra_readdata,
+ board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ board_kernel_cra_burstcount => board_kernel_cra_burstcount,
+ board_kernel_cra_writedata => board_kernel_cra_writedata,
+ board_kernel_cra_address => board_kernel_cra_address,
+ board_kernel_cra_write => board_kernel_cra_write,
+ board_kernel_cra_read => board_kernel_cra_read,
+ board_kernel_cra_byteenable => board_kernel_cra_byteenable,
+ board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+
+ board_kernel_register_mem_address => board_kernel_register_mem_address,
+ board_kernel_register_mem_clken => board_kernel_register_mem_clken,
+ board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
+ board_kernel_register_mem_write => board_kernel_register_mem_write,
+ board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
+ board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
+ board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
+
+ board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
+ board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
+ board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
+ board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
+ board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
+ board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
+ board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
+ board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
+ board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
+ board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
+
+ board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
+ board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
+ board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
+ board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
+
+ board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
+ board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
+ board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
+ board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
+
+ board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
+ board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
+ board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
+ board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
+
+ board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
+ board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
+ board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
+ board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
+ board_kernel_stream_src_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
+ board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
+ board_kernel_stream_snk_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
+ board_kernel_stream_src_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
+ board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
+ board_kernel_stream_snk_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
+ board_kernel_stream_src_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
+ board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
+ board_kernel_stream_snk_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
+
+ board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_0_valid => kernel_to_lane_sosi_arr(0).valid,
+ board_kernel_stream_src_lane_0_ready => kernel_to_lane_siso_arr(0).ready,
+ board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_0_valid => kernel_from_lane_sosi_arr(0).valid,
+ board_kernel_stream_snk_lane_0_ready => kernel_from_lane_siso_arr(0).ready,
+
+ board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_1_valid => kernel_to_lane_sosi_arr(1).valid,
+ board_kernel_stream_src_lane_1_ready => kernel_to_lane_siso_arr(1).ready,
+ board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_1_valid => kernel_from_lane_sosi_arr(1).valid,
+ board_kernel_stream_snk_lane_1_ready => kernel_from_lane_siso_arr(1).ready,
+
+ board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_2_valid => kernel_to_lane_sosi_arr(2).valid,
+ board_kernel_stream_src_lane_2_ready => kernel_to_lane_siso_arr(2).ready,
+ board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_2_valid => kernel_from_lane_sosi_arr(2).valid,
+ board_kernel_stream_snk_lane_2_ready => kernel_from_lane_siso_arr(2).ready,
+
+ board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_3_valid => kernel_to_lane_sosi_arr(3).valid,
+ board_kernel_stream_src_lane_3_ready => kernel_to_lane_siso_arr(3).ready,
+ board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_3_valid => kernel_from_lane_sosi_arr(3).valid,
+ board_kernel_stream_snk_lane_3_ready => kernel_from_lane_siso_arr(3).ready,
+
+ board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_4_valid => kernel_to_lane_sosi_arr(4).valid,
+ board_kernel_stream_src_lane_4_ready => kernel_to_lane_siso_arr(4).ready,
+ board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_4_valid => kernel_from_lane_sosi_arr(4).valid,
+ board_kernel_stream_snk_lane_4_ready => kernel_from_lane_siso_arr(4).ready,
+
+ board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_5_valid => kernel_to_lane_sosi_arr(5).valid,
+ board_kernel_stream_src_lane_5_ready => kernel_to_lane_siso_arr(5).ready,
+ board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_5_valid => kernel_from_lane_sosi_arr(5).valid,
+ board_kernel_stream_snk_lane_5_ready => kernel_from_lane_siso_arr(5).ready,
+
+ board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_6_valid => kernel_to_lane_sosi_arr(6).valid,
+ board_kernel_stream_src_lane_6_ready => kernel_to_lane_siso_arr(6).ready,
+ board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_6_valid => kernel_from_lane_sosi_arr(6).valid,
+ board_kernel_stream_snk_lane_6_ready => kernel_from_lane_siso_arr(6).ready,
+
+ board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_7_valid => kernel_to_lane_sosi_arr(7).valid,
+ board_kernel_stream_src_lane_7_ready => kernel_to_lane_siso_arr(7).ready,
+ board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_7_valid => kernel_from_lane_sosi_arr(7).valid,
+ board_kernel_stream_snk_lane_7_ready => kernel_from_lane_siso_arr(7).ready,
+
+ board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_0_valid => kernel_rx_monitor_sosi_arr(0).valid,
+ board_kernel_stream_snk_rx_monitor_0_ready => kernel_rx_monitor_siso_arr(0).ready,
+ board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_0_valid => kernel_tx_monitor_sosi_arr(0).valid,
+ board_kernel_stream_snk_tx_monitor_0_ready => kernel_tx_monitor_siso_arr(0).ready,
+
+ board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_1_valid => kernel_rx_monitor_sosi_arr(1).valid,
+ board_kernel_stream_snk_rx_monitor_1_ready => kernel_rx_monitor_siso_arr(1).ready,
+ board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_1_valid => kernel_tx_monitor_sosi_arr(1).valid,
+ board_kernel_stream_snk_tx_monitor_1_ready => kernel_tx_monitor_siso_arr(1).ready,
+
+ board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_2_valid => kernel_rx_monitor_sosi_arr(2).valid,
+ board_kernel_stream_snk_rx_monitor_2_ready => kernel_rx_monitor_siso_arr(2).ready,
+ board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_2_valid => kernel_tx_monitor_sosi_arr(2).valid,
+ board_kernel_stream_snk_tx_monitor_2_ready => kernel_tx_monitor_siso_arr(2).ready,
+
+ board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_3_valid => kernel_rx_monitor_sosi_arr(3).valid,
+ board_kernel_stream_snk_rx_monitor_3_ready => kernel_rx_monitor_siso_arr(3).ready,
+ board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_3_valid => kernel_tx_monitor_sosi_arr(3).valid,
+ board_kernel_stream_snk_tx_monitor_3_ready => kernel_tx_monitor_siso_arr(3).ready,
+
+ board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_4_valid => kernel_rx_monitor_sosi_arr(4).valid,
+ board_kernel_stream_snk_rx_monitor_4_ready => kernel_rx_monitor_siso_arr(4).ready,
+ board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_4_valid => kernel_tx_monitor_sosi_arr(4).valid,
+ board_kernel_stream_snk_tx_monitor_4_ready => kernel_tx_monitor_siso_arr(4).ready,
+
+ board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_5_valid => kernel_rx_monitor_sosi_arr(5).valid,
+ board_kernel_stream_snk_rx_monitor_5_ready => kernel_rx_monitor_siso_arr(5).ready,
+ board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_5_valid => kernel_tx_monitor_sosi_arr(5).valid,
+ board_kernel_stream_snk_tx_monitor_5_ready => kernel_tx_monitor_siso_arr(5).ready,
+
+ board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_6_valid => kernel_rx_monitor_sosi_arr(6).valid,
+ board_kernel_stream_snk_rx_monitor_6_ready => kernel_rx_monitor_siso_arr(6).ready,
+ board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_6_valid => kernel_tx_monitor_sosi_arr(6).valid,
+ board_kernel_stream_snk_tx_monitor_6_ready => kernel_tx_monitor_siso_arr(6).ready,
+
+ board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_7_valid => kernel_rx_monitor_sosi_arr(7).valid,
+ board_kernel_stream_snk_rx_monitor_7_ready => kernel_rx_monitor_siso_arr(7).ready,
+ board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_7_valid => kernel_tx_monitor_sosi_arr(7).valid,
+ board_kernel_stream_snk_tx_monitor_7_ready => kernel_tx_monitor_siso_arr(7).ready,
+
+ board_kernel_stream_src_bs_data => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_bs_valid => kernel_bs_sosi.valid,
+ board_kernel_stream_src_bs_ready => OPEN,
+
+ board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
+ board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
+ board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w - 1 downto 0),
+ board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
+ board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready
+
+ );
i_kernel_rst <= not board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
end generate;
@@ -1181,346 +1181,346 @@ begin
board_kernel_clk_clk <= st_clk;
u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
u_mm_file_reg_dp_xonoff_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
- port map(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
u_mm_file_reg_dp_xonoff_from_lane: mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
+ port map(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
u_mm_file_reg_bsn_monitor_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
u_mm_file_reg_bsn_monitor_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
u_mm_file_reg_bg_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
- port map(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
+ port map(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
end generate;
i_reset_n <= not mm_rst; -- First reset OpenCL components in qsys (board)
-- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
-- This way it is ensured the OpenCL kernel does not start reading/writing data before the components in the OpenCL BSP are ready.
u_common_areset : entity common_lib.common_areset
- generic map (
- g_rst_level => '0',
- g_delay_len => 9
- )
- port map (
- in_rst => i_kernel_rst,
- clk => board_kernel_clk_clk,
- out_rst => board_kernel_reset_reset_n_in
- );
------------------------------------------------------------------------------
+ generic map (
+ g_rst_level => '0',
+ g_delay_len => 9
+ )
+ port map (
+ in_rst => i_kernel_rst,
+ clk => board_kernel_clk_clk,
+ out_rst => board_kernel_reset_reset_n_in
+ );
+ -----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb2b_board : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- RAM scrap
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- RAM scrap
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
gen_board: if g_sim = false generate
- board_inst : board
- port map (
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- kernel_clk_clk => board_kernel_clk_clk,
- kernel_clk2x_clk => board_kernel_clk2x_clk,
- kernel_reset_reset_n => board_kernel_reset_reset_n,
-
- kernel_interface_sw_reset_in_reset => mm_rst,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0), -- temp fix
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0), -- temp fix
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_rx_address_export => reg_bsn_monitor_v2_rx_mosi.address(9 downto 0),
- reg_bsn_monitor_v2_rx_read_export => reg_bsn_monitor_v2_rx_mosi.rd,
- reg_bsn_monitor_v2_rx_readdata_export => reg_bsn_monitor_v2_rx_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_write_export => reg_bsn_monitor_v2_rx_mosi.wr,
- reg_bsn_monitor_v2_rx_writedata_export => reg_bsn_monitor_v2_rx_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_tx_address_export => reg_bsn_monitor_v2_tx_mosi.address(9 downto 0),
- reg_bsn_monitor_v2_tx_read_export => reg_bsn_monitor_v2_tx_mosi.rd,
- reg_bsn_monitor_v2_tx_readdata_export => reg_bsn_monitor_v2_tx_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_tx_write_export => reg_bsn_monitor_v2_tx_mosi.wr,
- reg_bsn_monitor_v2_tx_writedata_export => reg_bsn_monitor_v2_tx_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_diag_bg_ring_address_export => ram_bg_data_mosi.address(9 downto 0),
- ram_diag_bg_ring_read_export => ram_bg_data_mosi.rd,
- ram_diag_bg_ring_readdata_export => ram_bg_data_miso.rddata(c_word_w - 1 downto 0),
- ram_diag_bg_ring_write_export => ram_bg_data_mosi.wr,
- ram_diag_bg_ring_writedata_export => ram_bg_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_diag_bg_ring_address_export => reg_bg_ctrl_mosi.address(2 downto 0),
- reg_diag_bg_ring_read_export => reg_bg_ctrl_mosi.rd,
- reg_diag_bg_ring_readdata_export => reg_bg_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_bg_ring_write_export => reg_bg_ctrl_mosi.wr,
- reg_diag_bg_ring_writedata_export => reg_bg_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_bg_address_export => reg_dp_xonoff_bg_mosi.address(2 downto 0),
- reg_dp_xonoff_bg_read_export => reg_dp_xonoff_bg_mosi.rd,
- reg_dp_xonoff_bg_readdata_export => reg_dp_xonoff_bg_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_xonoff_bg_write_export => reg_dp_xonoff_bg_mosi.wr,
- reg_dp_xonoff_bg_writedata_export => reg_dp_xonoff_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_dp_xonoff_from_lane_address_export => reg_dp_xonoff_from_lane_mosi.address(2 downto 0),
- reg_dp_xonoff_from_lane_read_export => reg_dp_xonoff_from_lane_mosi.rd,
- reg_dp_xonoff_from_lane_readdata_export => reg_dp_xonoff_from_lane_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_xonoff_from_lane_write_export => reg_dp_xonoff_from_lane_mosi.wr,
- reg_dp_xonoff_from_lane_writedata_export => reg_dp_xonoff_from_lane_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
- reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w - 1 downto 0),
- reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w - 1 downto 0),
-
- kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- kernel_cra_readdata => board_kernel_cra_readdata,
- kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- kernel_cra_burstcount => board_kernel_cra_burstcount,
- kernel_cra_writedata => board_kernel_cra_writedata,
- kernel_cra_address => board_kernel_cra_address,
- kernel_cra_write => board_kernel_cra_write,
- kernel_cra_read => board_kernel_cra_read,
- kernel_cra_byteenable => board_kernel_cra_byteenable,
- kernel_cra_debugaccess => board_kernel_cra_debugaccess,
-
- kernel_irq_irq => board_kernel_irq_irq,
-
- reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(c_kernel_regmap_addr_w - 1 downto 0),
- reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
- reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
- reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest
- );
+ board_inst : board
+ port map (
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ kernel_clk_clk => board_kernel_clk_clk,
+ kernel_clk2x_clk => board_kernel_clk2x_clk,
+ kernel_reset_reset_n => board_kernel_reset_reset_n,
+
+ kernel_interface_sw_reset_in_reset => mm_rst,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0), -- temp fix
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0), -- temp fix
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_rx_address_export => reg_bsn_monitor_v2_rx_mosi.address(9 downto 0),
+ reg_bsn_monitor_v2_rx_read_export => reg_bsn_monitor_v2_rx_mosi.rd,
+ reg_bsn_monitor_v2_rx_readdata_export => reg_bsn_monitor_v2_rx_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_write_export => reg_bsn_monitor_v2_rx_mosi.wr,
+ reg_bsn_monitor_v2_rx_writedata_export => reg_bsn_monitor_v2_rx_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_tx_address_export => reg_bsn_monitor_v2_tx_mosi.address(9 downto 0),
+ reg_bsn_monitor_v2_tx_read_export => reg_bsn_monitor_v2_tx_mosi.rd,
+ reg_bsn_monitor_v2_tx_readdata_export => reg_bsn_monitor_v2_tx_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_tx_write_export => reg_bsn_monitor_v2_tx_mosi.wr,
+ reg_bsn_monitor_v2_tx_writedata_export => reg_bsn_monitor_v2_tx_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_ring_address_export => ram_bg_data_mosi.address(9 downto 0),
+ ram_diag_bg_ring_read_export => ram_bg_data_mosi.rd,
+ ram_diag_bg_ring_readdata_export => ram_bg_data_miso.rddata(c_word_w - 1 downto 0),
+ ram_diag_bg_ring_write_export => ram_bg_data_mosi.wr,
+ ram_diag_bg_ring_writedata_export => ram_bg_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_ring_address_export => reg_bg_ctrl_mosi.address(2 downto 0),
+ reg_diag_bg_ring_read_export => reg_bg_ctrl_mosi.rd,
+ reg_diag_bg_ring_readdata_export => reg_bg_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_bg_ring_write_export => reg_bg_ctrl_mosi.wr,
+ reg_diag_bg_ring_writedata_export => reg_bg_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_bg_address_export => reg_dp_xonoff_bg_mosi.address(2 downto 0),
+ reg_dp_xonoff_bg_read_export => reg_dp_xonoff_bg_mosi.rd,
+ reg_dp_xonoff_bg_readdata_export => reg_dp_xonoff_bg_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_bg_write_export => reg_dp_xonoff_bg_mosi.wr,
+ reg_dp_xonoff_bg_writedata_export => reg_dp_xonoff_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_dp_xonoff_from_lane_address_export => reg_dp_xonoff_from_lane_mosi.address(2 downto 0),
+ reg_dp_xonoff_from_lane_read_export => reg_dp_xonoff_from_lane_mosi.rd,
+ reg_dp_xonoff_from_lane_readdata_export => reg_dp_xonoff_from_lane_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_xonoff_from_lane_write_export => reg_dp_xonoff_from_lane_mosi.wr,
+ reg_dp_xonoff_from_lane_writedata_export => reg_dp_xonoff_from_lane_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w - 1 downto 0),
+ reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w - 1 downto 0),
+
+ kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ kernel_cra_readdata => board_kernel_cra_readdata,
+ kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ kernel_cra_burstcount => board_kernel_cra_burstcount,
+ kernel_cra_writedata => board_kernel_cra_writedata,
+ kernel_cra_address => board_kernel_cra_address,
+ kernel_cra_write => board_kernel_cra_write,
+ kernel_cra_read => board_kernel_cra_read,
+ kernel_cra_byteenable => board_kernel_cra_byteenable,
+ kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+
+ kernel_irq_irq => board_kernel_irq_irq,
+
+ reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(c_kernel_regmap_addr_w - 1 downto 0),
+ reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
+ reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
+ reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest
+ );
end generate;
end str;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index 7300ceb6ee..3261ad722e 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -25,213 +25,213 @@
-- . Contains components instantiated by top.vhd
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package top_components_pkg is
- component board is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_ring_reset_export : out std_logic; -- export
- ram_diag_bg_ring_clk_export : out std_logic; -- export
- ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_ring_write_export : out std_logic; -- export
- ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_ring_read_export : out std_logic; -- export
- ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_ring_reset_export : out std_logic; -- export
- reg_diag_bg_ring_clk_export : out std_logic; -- export
- reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_ring_write_export : out std_logic; -- export
- reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_ring_read_export : out std_logic; -- export
- reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_bg_reset_export : out std_logic; -- export
- reg_dp_xonoff_bg_clk_export : out std_logic; -- export
- reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_xonoff_bg_write_export : out std_logic; -- export
- reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_bg_read_export : out std_logic; -- export
- reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_from_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_xonoff_from_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_from_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component board;
+ component board is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ kernel_clk_clk : out std_logic; -- clk
+ kernel_reset_reset_n : out std_logic; -- reset_n
+ kernel_clk2x_clk : out std_logic; -- clk
+ kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+ kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
+ kernel_cra_address : out std_logic_vector(29 downto 0); -- address
+ kernel_cra_write : out std_logic; -- write
+ kernel_cra_read : out std_logic; -- read
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
+ kernel_cra_debugaccess : out std_logic; -- debugaccess
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_ring_reset_export : out std_logic; -- export
+ ram_diag_bg_ring_clk_export : out std_logic; -- export
+ ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_ring_write_export : out std_logic; -- export
+ ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_ring_read_export : out std_logic; -- export
+ ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_ring_reset_export : out std_logic; -- export
+ reg_diag_bg_ring_clk_export : out std_logic; -- export
+ reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_ring_write_export : out std_logic; -- export
+ reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_ring_read_export : out std_logic; -- export
+ reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_bg_reset_export : out std_logic; -- export
+ reg_dp_xonoff_bg_clk_export : out std_logic; -- export
+ reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_xonoff_bg_write_export : out std_logic; -- export
+ reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_bg_read_export : out std_logic; -- export
+ reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_from_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_xonoff_from_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_from_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component board;
component freeze_wrapper is
port (
@@ -465,7 +465,7 @@ package top_components_pkg is
board_kernel_stream_snk_mm_io_data : out std_logic_vector(31 downto 0);
board_kernel_stream_snk_mm_io_valid : out std_logic;
board_kernel_stream_snk_mm_io_ready : out std_logic
- );
+ );
end component freeze_wrapper;
end top_components_pkg;
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
index f747878245..4bb47a80bb 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
@@ -32,17 +32,17 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib, ta2_unb2b_40GbE_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_1gbe_lib, ta2_unb2b_mm_io_lib, ta2_unb2b_jesd204b_lib ;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_component_pkg.all;
-use work.top_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_component_pkg.all;
+ use work.top_components_pkg.all;
entity top is
generic (
@@ -104,7 +104,7 @@ entity top is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0);
- -- back transceivers
+ -- back transceivers
BCK_RX : in std_logic_vector(0 downto 0);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -304,10 +304,10 @@ architecture str of top is
signal board_kernel_mem0_read : std_logic; -- := 'X'; -- write
signal board_kernel_mem0_byteenable : std_logic_vector(63 downto 0); -- := (others => 'X'); -- byteenable
signal board_kernel_mem0_debugaccess : std_logic; -- := 'X'; -- write
--- SIGNAL amm_readdata : std_logic_vector(575 downto 0); -- readdata
--- SIGNAL amm_burstcount : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
--- SIGNAL amm_writedata : std_logic_vector(575 downto 0); -- := (others => 'X'); -- address
--- SIGNAL amm_byteenable : std_logic_vector(71 downto 0); -- := (others => 'X'); -- byteenable
+ -- SIGNAL amm_readdata : std_logic_vector(575 downto 0); -- readdata
+ -- SIGNAL amm_burstcount : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
+ -- SIGNAL amm_writedata : std_logic_vector(575 downto 0); -- := (others => 'X'); -- address
+ -- SIGNAL amm_byteenable : std_logic_vector(71 downto 0); -- := (others => 'X'); -- byteenable
signal board_kernel_register_mem_address : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
signal board_kernel_register_mem_clken : std_logic; -- := 'X'; -- clken
@@ -360,21 +360,21 @@ begin
QSFP_1_TX <= i_QSFP_TX(1);
u_unb2b_board_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
- --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX -- ,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX -- ,
--QSFP_LED => QSFP_LED
- );
+ );
------------------------
-- qsfp LEDs controller
@@ -386,21 +386,21 @@ begin
unb2b_board_qsfp_leds_tx_src_in_arr(12).xon <= ta2_unb2b_40GbE_snk_out_arr(2).xon;
u_unb2b_board_qsfp_leds : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus + c_nof_ring_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus + c_nof_ring_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0)
+ );
gen_leds : for i in 0 to c_nof_qsfp_bus + c_nof_ring_bus - 1 generate
QSFP_LED(i * 2) <= qsfp_green_led_arr(i);
@@ -418,15 +418,15 @@ begin
RING_1_TX <= i_RING_TX(1);
u_ring_io : entity unb2b_board_lib.unb2b_board_ring_io
- generic map (
- g_nof_ring_bus => c_nof_ring_bus
- )
- port map (
- serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
- RING_RX => i_RING_RX,
- RING_TX => i_RING_TX
- );
+ generic map (
+ g_nof_ring_bus => c_nof_ring_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
+ RING_RX => i_RING_RX,
+ RING_TX => i_RING_TX
+ );
---------
-- 40GbE
@@ -444,26 +444,26 @@ begin
ta2_unb2b_40GbE_rx_serial_r(11 downto 8) <= unb2b_board_ring_io_serial_rx_arr(3 + c_ring_bus_w downto c_ring_bus_w);
u_ta2_unb2b_40GbE : entity ta2_unb2b_40GbE_lib.ta2_unb2b_40GbE
- generic map (
- g_nof_mac => c_nof_40GbE_IP
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_nof_mac => c_nof_40GbE_IP
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- clk_ref_r => SA_CLK,
+ clk_ref_r => SA_CLK,
- tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
+ tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_40GbE_src_out_arr,
- src_in_arr => ta2_unb2b_40GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
- );
+ src_out_arr => ta2_unb2b_40GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_40GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
+ );
----------
-- 10GbE
@@ -474,103 +474,103 @@ begin
u_ta2_unb2b_10GbE : entity ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
- generic map (
- g_nof_mac => c_nof_10GbE_IP
- )
- port map (
- mm_clk => '0', -- mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_nof_mac => c_nof_10GbE_IP
+ )
+ port map (
+ mm_clk => '0', -- mm_clk,
+ mm_rst => mm_rst,
- clk_ref_r => SA_CLK,
+ clk_ref_r => SA_CLK,
- tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
+ tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_10GbE_src_out_arr,
- src_in_arr => ta2_unb2b_10GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
- );
+ src_out_arr => ta2_unb2b_10GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_10GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
+ );
-----------------------------
-- 1GbE Monitoring & Control
-----------------------------
u_ta2_unb2b_1GbE : entity ta2_unb2b_1GbE_lib.ta2_unb2b_1GbE
- port map (
- st_clk => st_clk,
- st_rst => st_rst,
-
- udp_tx_sosi => eth1g_udp_tx_sosi_arr(0),
- udp_tx_siso => eth1g_udp_tx_siso_arr(0),
- udp_rx_sosi => eth1g_udp_rx_sosi_arr(0),
- udp_rx_siso => eth1g_udp_rx_siso_arr(0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- src_out => ta2_unb2b_1GbE_src_out,
- src_in => ta2_unb2b_1GbE_src_in,
- snk_out => ta2_unb2b_1GbE_snk_out,
- snk_in => ta2_unb2b_1GbE_snk_in
- );
+ port map (
+ st_clk => st_clk,
+ st_rst => st_rst,
+
+ udp_tx_sosi => eth1g_udp_tx_sosi_arr(0),
+ udp_tx_siso => eth1g_udp_tx_siso_arr(0),
+ udp_rx_sosi => eth1g_udp_rx_sosi_arr(0),
+ udp_rx_siso => eth1g_udp_rx_siso_arr(0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ src_out => ta2_unb2b_1GbE_src_out,
+ src_in => ta2_unb2b_1GbE_src_in,
+ snk_out => ta2_unb2b_1GbE_snk_out,
+ snk_in => ta2_unb2b_1GbE_snk_in
+ );
--------------------------------------
-- Monitoring & Control UNB protocol
--------------------------------------
u_ta2_unb2b_mm_io : entity ta2_unb2b_mm_io_lib.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => true
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_opencl => true
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- mm_mosi => reg_ta2_unb2b_mm_io_mosi,
- mm_miso => reg_ta2_unb2b_mm_io_miso,
+ mm_mosi => reg_ta2_unb2b_mm_io_mosi,
+ mm_miso => reg_ta2_unb2b_mm_io_miso,
- snk_in => ta2_unb2b_mm_io_snk_in,
- snk_out => ta2_unb2b_mm_io_snk_out,
- src_out => ta2_unb2b_mm_io_src_out,
- src_in => ta2_unb2b_mm_io_src_in
+ snk_in => ta2_unb2b_mm_io_snk_in,
+ snk_out => ta2_unb2b_mm_io_snk_out,
+ src_out => ta2_unb2b_mm_io_src_out,
+ src_in => ta2_unb2b_mm_io_src_in
- );
+ );
----------
-- ADC
----------
u_ta2_unb2b_jesd204b : entity ta2_unb2b_jesd204b_lib.ta2_unb2b_jesd204b
- generic map(
- g_nof_streams => c_nof_ADC
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_nof_streams => c_nof_ADC
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- jesd204b_mosi => reg_ta2_unb2b_jesd204b_mosi,
- jesd204b_miso => reg_ta2_unb2b_jesd204b_miso,
+ jesd204b_mosi => reg_ta2_unb2b_jesd204b_mosi,
+ jesd204b_miso => reg_ta2_unb2b_jesd204b_miso,
- -- JESD204B external signals
- jesd204b_refclk => BCK_REF_CLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => JESD204B_SYNC,
+ -- JESD204B external signals
+ jesd204b_refclk => BCK_REF_CLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => JESD204B_SYNC,
- serial_rx_arr => BCK_RX,
+ serial_rx_arr => BCK_RX,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_ADC_src_out_arr,
- src_in_arr => ta2_unb2b_ADC_src_in_arr
- );
+ src_out_arr => ta2_unb2b_ADC_src_out_arr,
+ src_in_arr => ta2_unb2b_ADC_src_in_arr
+ );
----------
-- DDR4
@@ -606,261 +606,261 @@ begin
-- Freeze wrapper instantiation
-----------------------------------------------------------------------------
freeze_wrapper_inst : freeze_wrapper
- port map(
- board_kernel_clk_clk => board_kernel_clk_clk,
- board_kernel_clk2x_clk => board_kernel_clk2x_clk,
- board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
- board_kernel_irq_irq => board_kernel_irq_irq,
- board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- board_kernel_cra_readdata => board_kernel_cra_readdata,
- board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- board_kernel_cra_burstcount => board_kernel_cra_burstcount,
- board_kernel_cra_writedata => board_kernel_cra_writedata,
- board_kernel_cra_address => board_kernel_cra_address,
- board_kernel_cra_write => board_kernel_cra_write,
- board_kernel_cra_read => board_kernel_cra_read,
- board_kernel_cra_byteenable => board_kernel_cra_byteenable,
- board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
-
- --board_kernel_mem0_waitrequest => '0',
- --board_kernel_mem0_readdata => c_ones,
- --board_kernel_mem0_readdatavalid => '1',
- --board_kernel_mem0_burstcount => OPEN,
- --board_kernel_mem0_writedata => OPEN,
- --board_kernel_mem0_address => OPEN,
- --board_kernel_mem0_write => OPEN,
- --board_kernel_mem0_read => OPEN,
- --board_kernel_mem0_byteenable => OPEN,
- --board_kernel_mem0_debugaccess => OPEN,
-
- board_kernel_mem0_waitrequest => board_kernel_mem0_waitrequest,
- board_kernel_mem0_readdata => board_kernel_mem0_readdata,
- board_kernel_mem0_readdatavalid => board_kernel_mem0_readdatavalid,
- board_kernel_mem0_burstcount => board_kernel_mem0_burstcount,
- board_kernel_mem0_writedata => board_kernel_mem0_writedata,
- board_kernel_mem0_address => board_kernel_mem0_address,
- board_kernel_mem0_write => board_kernel_mem0_write,
- board_kernel_mem0_read => board_kernel_mem0_read,
- board_kernel_mem0_byteenable => board_kernel_mem0_byteenable,
- board_kernel_mem0_debugaccess => board_kernel_mem0_debugaccess,
-
- board_kernel_register_mem_address => board_kernel_register_mem_address,
- board_kernel_register_mem_clken => board_kernel_register_mem_clken,
- board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
- board_kernel_register_mem_write => board_kernel_register_mem_write,
- board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
- board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- board_kernel_stream_src_40GbE_data => ta2_unb2b_40GbE_src_out_arr(0).data(263 downto 0),
- board_kernel_stream_src_40GbE_valid => ta2_unb2b_40GbE_src_out_arr(0).valid,
- board_kernel_stream_src_40GbE_ready => ta2_unb2b_40GbE_src_in_arr(0).ready,
- board_kernel_stream_snk_40GbE_data => ta2_unb2b_40GbE_snk_in_arr(0).data(263 downto 0),
- board_kernel_stream_snk_40GbE_valid => ta2_unb2b_40GbE_snk_in_arr(0).valid,
- board_kernel_stream_snk_40GbE_ready => ta2_unb2b_40GbE_snk_out_arr(0).ready,
-
- board_kernel_stream_src_40GbE_ring_0_data => ta2_unb2b_40GbE_src_out_arr(1).data(263 downto 0),
- board_kernel_stream_src_40GbE_ring_0_valid => ta2_unb2b_40GbE_src_out_arr(1).valid,
- board_kernel_stream_src_40GbE_ring_0_ready => ta2_unb2b_40GbE_src_in_arr(1).ready,
- board_kernel_stream_snk_40GbE_ring_0_data => ta2_unb2b_40GbE_snk_in_arr(1).data(263 downto 0),
- board_kernel_stream_snk_40GbE_ring_0_valid => ta2_unb2b_40GbE_snk_in_arr(1).valid,
- board_kernel_stream_snk_40GbE_ring_0_ready => ta2_unb2b_40GbE_snk_out_arr(1).ready,
-
- board_kernel_stream_src_40GbE_ring_1_data => ta2_unb2b_40GbE_src_out_arr(2).data(263 downto 0),
- board_kernel_stream_src_40GbE_ring_1_valid => ta2_unb2b_40GbE_src_out_arr(2).valid,
- board_kernel_stream_src_40GbE_ring_1_ready => ta2_unb2b_40GbE_src_in_arr(2).ready,
- board_kernel_stream_snk_40GbE_ring_1_data => ta2_unb2b_40GbE_snk_in_arr(2).data(263 downto 0),
- board_kernel_stream_snk_40GbE_ring_1_valid => ta2_unb2b_40GbE_snk_in_arr(2).valid,
- board_kernel_stream_snk_40GbE_ring_1_ready => ta2_unb2b_40GbE_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_data => ta2_unb2b_10GbE_src_out_arr(0).data(71 downto 0),
- board_kernel_stream_src_10GbE_valid => ta2_unb2b_10GbE_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_ready => ta2_unb2b_10GbE_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_data => ta2_unb2b_10GbE_snk_in_arr(0).data(71 downto 0),
- board_kernel_stream_snk_10GbE_valid => ta2_unb2b_10GbE_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_ready => ta2_unb2b_10GbE_snk_out_arr(0).ready,
-
- board_kernel_stream_src_1GbE_data => ta2_unb2b_1GbE_src_out.data(39 downto 0),
- board_kernel_stream_src_1GbE_valid => ta2_unb2b_1GbE_src_out.valid,
- board_kernel_stream_src_1GbE_ready => ta2_unb2b_1GbE_src_in.ready,
- board_kernel_stream_snk_1GbE_data => ta2_unb2b_1GbE_snk_in.data(39 downto 0),
- board_kernel_stream_snk_1GbE_valid => ta2_unb2b_1GbE_snk_in.valid,
- board_kernel_stream_snk_1GbE_ready => ta2_unb2b_1GbE_snk_out.ready,
-
- board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(71 downto 0),
- board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
- board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
- board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(31 downto 0),
- board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
- board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready,
-
- board_kernel_stream_src_ADC_data => ta2_unb2b_ADC_src_out_arr(0).data(15 downto 0),
- board_kernel_stream_src_ADC_valid => ta2_unb2b_ADC_src_out_arr(0).valid,
- board_kernel_stream_src_ADC_ready => ta2_unb2b_ADC_src_in_arr(0).ready
-
- );
+ port map(
+ board_kernel_clk_clk => board_kernel_clk_clk,
+ board_kernel_clk2x_clk => board_kernel_clk2x_clk,
+ board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
+ board_kernel_irq_irq => board_kernel_irq_irq,
+ board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ board_kernel_cra_readdata => board_kernel_cra_readdata,
+ board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ board_kernel_cra_burstcount => board_kernel_cra_burstcount,
+ board_kernel_cra_writedata => board_kernel_cra_writedata,
+ board_kernel_cra_address => board_kernel_cra_address,
+ board_kernel_cra_write => board_kernel_cra_write,
+ board_kernel_cra_read => board_kernel_cra_read,
+ board_kernel_cra_byteenable => board_kernel_cra_byteenable,
+ board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+
+ --board_kernel_mem0_waitrequest => '0',
+ --board_kernel_mem0_readdata => c_ones,
+ --board_kernel_mem0_readdatavalid => '1',
+ --board_kernel_mem0_burstcount => OPEN,
+ --board_kernel_mem0_writedata => OPEN,
+ --board_kernel_mem0_address => OPEN,
+ --board_kernel_mem0_write => OPEN,
+ --board_kernel_mem0_read => OPEN,
+ --board_kernel_mem0_byteenable => OPEN,
+ --board_kernel_mem0_debugaccess => OPEN,
+
+ board_kernel_mem0_waitrequest => board_kernel_mem0_waitrequest,
+ board_kernel_mem0_readdata => board_kernel_mem0_readdata,
+ board_kernel_mem0_readdatavalid => board_kernel_mem0_readdatavalid,
+ board_kernel_mem0_burstcount => board_kernel_mem0_burstcount,
+ board_kernel_mem0_writedata => board_kernel_mem0_writedata,
+ board_kernel_mem0_address => board_kernel_mem0_address,
+ board_kernel_mem0_write => board_kernel_mem0_write,
+ board_kernel_mem0_read => board_kernel_mem0_read,
+ board_kernel_mem0_byteenable => board_kernel_mem0_byteenable,
+ board_kernel_mem0_debugaccess => board_kernel_mem0_debugaccess,
+
+ board_kernel_register_mem_address => board_kernel_register_mem_address,
+ board_kernel_register_mem_clken => board_kernel_register_mem_clken,
+ board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
+ board_kernel_register_mem_write => board_kernel_register_mem_write,
+ board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
+ board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
+ board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
+
+ board_kernel_stream_src_40GbE_data => ta2_unb2b_40GbE_src_out_arr(0).data(263 downto 0),
+ board_kernel_stream_src_40GbE_valid => ta2_unb2b_40GbE_src_out_arr(0).valid,
+ board_kernel_stream_src_40GbE_ready => ta2_unb2b_40GbE_src_in_arr(0).ready,
+ board_kernel_stream_snk_40GbE_data => ta2_unb2b_40GbE_snk_in_arr(0).data(263 downto 0),
+ board_kernel_stream_snk_40GbE_valid => ta2_unb2b_40GbE_snk_in_arr(0).valid,
+ board_kernel_stream_snk_40GbE_ready => ta2_unb2b_40GbE_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_40GbE_ring_0_data => ta2_unb2b_40GbE_src_out_arr(1).data(263 downto 0),
+ board_kernel_stream_src_40GbE_ring_0_valid => ta2_unb2b_40GbE_src_out_arr(1).valid,
+ board_kernel_stream_src_40GbE_ring_0_ready => ta2_unb2b_40GbE_src_in_arr(1).ready,
+ board_kernel_stream_snk_40GbE_ring_0_data => ta2_unb2b_40GbE_snk_in_arr(1).data(263 downto 0),
+ board_kernel_stream_snk_40GbE_ring_0_valid => ta2_unb2b_40GbE_snk_in_arr(1).valid,
+ board_kernel_stream_snk_40GbE_ring_0_ready => ta2_unb2b_40GbE_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_40GbE_ring_1_data => ta2_unb2b_40GbE_src_out_arr(2).data(263 downto 0),
+ board_kernel_stream_src_40GbE_ring_1_valid => ta2_unb2b_40GbE_src_out_arr(2).valid,
+ board_kernel_stream_src_40GbE_ring_1_ready => ta2_unb2b_40GbE_src_in_arr(2).ready,
+ board_kernel_stream_snk_40GbE_ring_1_data => ta2_unb2b_40GbE_snk_in_arr(2).data(263 downto 0),
+ board_kernel_stream_snk_40GbE_ring_1_valid => ta2_unb2b_40GbE_snk_in_arr(2).valid,
+ board_kernel_stream_snk_40GbE_ring_1_ready => ta2_unb2b_40GbE_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_data => ta2_unb2b_10GbE_src_out_arr(0).data(71 downto 0),
+ board_kernel_stream_src_10GbE_valid => ta2_unb2b_10GbE_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_ready => ta2_unb2b_10GbE_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_data => ta2_unb2b_10GbE_snk_in_arr(0).data(71 downto 0),
+ board_kernel_stream_snk_10GbE_valid => ta2_unb2b_10GbE_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_ready => ta2_unb2b_10GbE_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_1GbE_data => ta2_unb2b_1GbE_src_out.data(39 downto 0),
+ board_kernel_stream_src_1GbE_valid => ta2_unb2b_1GbE_src_out.valid,
+ board_kernel_stream_src_1GbE_ready => ta2_unb2b_1GbE_src_in.ready,
+ board_kernel_stream_snk_1GbE_data => ta2_unb2b_1GbE_snk_in.data(39 downto 0),
+ board_kernel_stream_snk_1GbE_valid => ta2_unb2b_1GbE_snk_in.valid,
+ board_kernel_stream_snk_1GbE_ready => ta2_unb2b_1GbE_snk_out.ready,
+
+ board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(71 downto 0),
+ board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
+ board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
+ board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(31 downto 0),
+ board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
+ board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready,
+
+ board_kernel_stream_src_ADC_data => ta2_unb2b_ADC_src_out_arr(0).data(15 downto 0),
+ board_kernel_stream_src_ADC_valid => ta2_unb2b_ADC_src_out_arr(0).valid,
+ board_kernel_stream_src_ADC_ready => ta2_unb2b_ADC_src_in_arr(0).ready
+
+ );
i_reset_n <= not mm_rst;
i_kernel_rst <= not board_kernel_reset_reset_n;
-- Kernel should start later than BSP
u_common_areset : entity common_lib.common_areset
- generic map (
- g_rst_level => '0',
- g_delay_len => 9
- )
- port map (
- in_rst => i_kernel_rst,
- clk => board_kernel_clk_clk,
- out_rst => board_kernel_reset_reset_n_in
- );
+ generic map (
+ g_rst_level => '0',
+ g_delay_len => 9
+ )
+ port map (
+ in_rst => i_kernel_rst,
+ clk => board_kernel_clk_clk,
+ out_rst => board_kernel_reset_reset_n_in
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb2b_board : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_udp_offload => c_use_1GbE_udp_offload,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- RAM scrap
- ram_scrap_mosi => c_mem_mosi_rst,
- ram_scrap_miso => OPEN,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_udp_offload => c_use_1GbE_udp_offload,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- RAM scrap
+ ram_scrap_mosi => c_mem_mosi_rst,
+ ram_scrap_miso => OPEN,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
board_inst : board
- port map (
+ port map (
clk_clk => mm_clk,
reset_reset_n => i_reset_n,
@@ -1028,14 +1028,14 @@ begin
ddr4a_mem_ck => MB_I_OU.ck(g_tech_ddr.ck_w - 1 downto 0),
ddr4a_mem_ck_n => MB_I_OU.ck_n(g_tech_ddr.ck_w - 1 downto 0),
ddr4a_mem_a => MB_I_OU.a(g_tech_ddr.a_w - 1 downto 0),
- sl(ddr4a_mem_act_n) => MB_I_OU.act_n,
+ sl(ddr4a_mem_act_n) => MB_I_OU.act_n,
ddr4a_mem_ba => MB_I_OU.ba(g_tech_ddr.ba_w - 1 downto 0),
ddr4a_mem_bg => MB_I_OU.bg(g_tech_ddr.bg_w - 1 downto 0),
ddr4a_mem_cke => MB_I_OU.cke(g_tech_ddr.cke_w - 1 downto 0),
ddr4a_mem_cs_n => MB_I_OU.cs_n(g_tech_ddr.cs_w - 1 downto 0),
ddr4a_mem_odt => MB_I_OU.odt(g_tech_ddr.odt_w - 1 downto 0),
- sl(ddr4a_mem_reset_n) => MB_I_OU.reset_n,
- sl(ddr4a_mem_par) => MB_I_OU.par,
+ sl(ddr4a_mem_reset_n) => MB_I_OU.reset_n,
+ sl(ddr4a_mem_par) => MB_I_OU.par,
ddr4a_mem_alert_n => slv(MB_I_IN.alert_n),
ddr4a_mem_dqs => MB_I_IO.dqs(g_tech_ddr.dqs_w - 1 downto 0),
ddr4a_mem_dqs_n => MB_I_IO.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
@@ -1043,7 +1043,7 @@ begin
ddr4a_mem_dbi_n => MB_I_IO.dbi_n(g_tech_ddr.dbi_w - 1 downto 0)
- );
+ );
end str;
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
index 4b96f52db1..fed7dae8ae 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
@@ -25,200 +25,200 @@
-- . Contains components instantiated by top.vhd
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package top_components_pkg is
- component board is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
- kernel_register_mem_clken : in std_logic := 'X'; -- clken
- kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
- kernel_register_mem_write : in std_logic := 'X'; -- write
- kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
- kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
- kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_mem0_waitrequest : out std_logic; -- waitrequest
- kernel_mem0_readdata : out std_logic_vector(511 downto 0); -- readdata
- kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
- kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
- kernel_mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
- kernel_mem0_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
- kernel_mem0_write : in std_logic := 'X'; -- write
- kernel_mem0_read : in std_logic := 'X'; -- read
- kernel_mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
- ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
- ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
- ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
- ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
- ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
- ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dbi_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
- reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component board;
+ component board is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
+ kernel_register_mem_clken : in std_logic := 'X'; -- clken
+ kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
+ kernel_register_mem_write : in std_logic := 'X'; -- write
+ kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
+ kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
+ kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ kernel_clk_clk : out std_logic; -- clk
+ kernel_reset_reset_n : out std_logic; -- reset_n
+ kernel_clk2x_clk : out std_logic; -- clk
+ kernel_mem0_waitrequest : out std_logic; -- waitrequest
+ kernel_mem0_readdata : out std_logic_vector(511 downto 0); -- readdata
+ kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
+ kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
+ kernel_mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
+ kernel_mem0_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
+ kernel_mem0_write : in std_logic := 'X'; -- write
+ kernel_mem0_read : in std_logic := 'X'; -- read
+ kernel_mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
+ kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+ kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
+ kernel_cra_address : out std_logic_vector(29 downto 0); -- address
+ kernel_cra_write : out std_logic; -- write
+ kernel_cra_read : out std_logic; -- read
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
+ kernel_cra_debugaccess : out std_logic; -- debugaccess
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
+ ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
+ ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
+ ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
+ ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dbi_n
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
+ reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component board;
component freeze_wrapper is
port (
@@ -301,7 +301,7 @@ package top_components_pkg is
board_kernel_stream_src_ADC_data : in std_logic_vector(15 downto 0);
board_kernel_stream_src_ADC_valid : in std_logic;
board_kernel_stream_src_ADC_ready : out std_logic
- );
+ );
end component freeze_wrapper;
end top_components_pkg;
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index ba356beb86..9cdb9e27a8 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -61,10 +61,10 @@
-- in mind that IO channels must be a multiple of 8 bits (bytes).
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity ta2_channel_cross is
generic (
@@ -131,56 +131,56 @@ begin
assert g_nof_bytes <= 32 report "g_nof_bytes of ta2_channel_cross is configured higher than 32" severity ERROR;
gen_streams: for stream in 0 to g_nof_streams - 1 generate
- -- dp_snk_in -> kernel_src_out
+ -- dp_snk_in -> kernel_src_out
---------------------------------------------------------------------------------------
-- TX FIFO: dp_clk -> kernel_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_bsn_w,
- g_empty_w => c_empty_w,
- g_channel_w => c_channel_w,
- g_error_w => c_err_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => true,
- g_use_channel => g_use_channel,
- g_use_error => g_use_err,
- g_use_sync => g_use_sync,
- g_fifo_size => g_fifo_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => dp_snk_out_arr(stream),
- snk_in => dp_snk_in_arr(stream),
-
- src_in => dp_latency_adapter_tx_snk_out_arr(stream),
- src_out => dp_latency_adapter_tx_snk_in_arr(stream)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_bsn_w,
+ g_empty_w => c_empty_w,
+ g_channel_w => c_channel_w,
+ g_error_w => c_err_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => true,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_err,
+ g_use_sync => g_use_sync,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => dp_snk_out_arr(stream),
+ snk_in => dp_snk_in_arr(stream),
+
+ src_in => dp_latency_adapter_tx_snk_out_arr(stream),
+ src_out => dp_latency_adapter_tx_snk_in_arr(stream)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_tx_snk_in_arr(stream),
- snk_out => dp_latency_adapter_tx_snk_out_arr(stream),
+ snk_in => dp_latency_adapter_tx_snk_in_arr(stream),
+ snk_out => dp_latency_adapter_tx_snk_out_arr(stream),
- src_out => dp_latency_adapter_tx_src_out_arr(stream),
- src_in => dp_latency_adapter_tx_src_in_arr(stream)
- );
+ src_out => dp_latency_adapter_tx_src_out_arr(stream),
+ src_in => dp_latency_adapter_tx_src_in_arr(stream)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -192,7 +192,7 @@ begin
end generate;
end generate;
gen_no_reverse_rx_bytes : if not g_reverse_bytes generate
- kernel_src_out_arr(stream).data(c_data_w - 1 downto 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w - 1 downto 0);
+ kernel_src_out_arr(stream).data(c_data_w - 1 downto 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w - 1 downto 0);
end generate;
-- Assign control signals to correct data fields.
@@ -256,52 +256,52 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_rx_snk_in_arr(stream),
- snk_out => dp_latency_adapter_rx_snk_out_arr(stream),
+ snk_in => dp_latency_adapter_rx_snk_in_arr(stream),
+ snk_out => dp_latency_adapter_rx_snk_out_arr(stream),
- src_out => dp_latency_adapter_rx_src_out_arr(stream),
- src_in => dp_latency_adapter_rx_src_in_arr(stream)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(stream),
+ src_in => dp_latency_adapter_rx_src_in_arr(stream)
+ );
---------------------------------------------------------------------------------------
-- RX FIFO: kernel_clk -> dp_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_bsn_w,
- g_empty_w => c_empty_w,
- g_channel_w => c_channel_w,
- g_error_w => c_err_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => true,
- g_use_channel => g_use_channel,
- g_use_error => g_use_err,
- g_use_sync => g_use_sync,
- g_fifo_size => g_fifo_size
- )
- port map (
- wr_rst => kernel_reset,
- wr_clk => kernel_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- snk_out => dp_latency_adapter_rx_src_in_arr(stream),
- snk_in => dp_latency_adapter_rx_src_out_arr(stream),
-
- src_in => dp_src_in_arr(stream),
- src_out => dp_src_out_arr(stream)
- );
-
- end generate;
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_bsn_w,
+ g_empty_w => c_empty_w,
+ g_channel_w => c_channel_w,
+ g_error_w => c_err_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => true,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_err,
+ g_use_sync => g_use_sync,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ wr_rst => kernel_reset,
+ wr_clk => kernel_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ snk_out => dp_latency_adapter_rx_src_in_arr(stream),
+ snk_in => dp_latency_adapter_rx_src_out_arr(stream),
+
+ src_in => dp_src_in_arr(stream),
+ src_out => dp_src_out_arr(stream)
+ );
+
+ end generate;
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index 92e3b7e45f..93d1dc4a5f 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -54,12 +54,12 @@
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_eth_10g_lib, tech_mac_10g_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
entity ta2_unb2b_10GbE is
generic (
@@ -141,17 +141,17 @@ begin
--------
g_pll : if g_use_pll generate
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg
- )
- port map (
- refclk_644 => clk_ref_r,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg
+ )
+ port map (
+ refclk_644 => clk_ref_r,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
end generate;
gen_no_pll : if not g_use_pll generate
@@ -165,33 +165,33 @@ begin
---------------------------------------------------------------------------------------
-- Apply the clocks from top level down such that they have their rising_edge() aligned without any delta-delay
u_tech_eth_10g_clocks : entity tech_eth_10g_lib.tech_eth_10g_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_nof_channels => g_nof_mac
- )
- port map (
- -- Input clocks
- -- . Reference
- tr_ref_clk_644 => clk_ref_r,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
-
- -- Output clocks
- -- . Reference
- eth_ref_clk_644 => eth_ref_clk_644,
- eth_ref_clk_312 => eth_ref_clk_312,
- eth_ref_clk_156 => eth_ref_clk_156,
- eth_ref_rst_156 => eth_ref_rst_156,
-
- -- . Data
- eth_tx_clk_arr => eth_tx_clk_arr,
- eth_tx_rst_arr => eth_tx_rst_arr,
-
- eth_rx_clk_arr => eth_rx_clk_arr,
- eth_rx_rst_arr => eth_rx_rst_arr
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_nof_channels => g_nof_mac
+ )
+ port map (
+ -- Input clocks
+ -- . Reference
+ tr_ref_clk_644 => clk_ref_r,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+
+ -- Output clocks
+ -- . Reference
+ eth_ref_clk_644 => eth_ref_clk_644,
+ eth_ref_clk_312 => eth_ref_clk_312,
+ eth_ref_clk_156 => eth_ref_clk_156,
+ eth_ref_rst_156 => eth_ref_rst_156,
+
+ -- . Data
+ eth_tx_clk_arr => eth_tx_clk_arr,
+ eth_tx_rst_arr => eth_tx_rst_arr,
+
+ eth_rx_clk_arr => eth_rx_clk_arr,
+ eth_rx_rst_arr => eth_rx_rst_arr
+ );
gen_mac: for mac in 0 to g_nof_mac - 1 generate
----------------------------------------------------------------------------
@@ -217,105 +217,105 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_tx_snk_in_arr(mac),
- snk_out => dp_latency_adapter_tx_snk_out_arr(mac),
+ snk_in => dp_latency_adapter_tx_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_snk_out_arr(mac),
- src_out => dp_latency_adapter_tx_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_tx_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_src_in_arr(mac)
+ );
-----------------------------------------------------------------------------
-- RX XON frame control
-----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- rst => kernel_reset,
- clk => kernel_clk,
+ port map (
+ rst => kernel_reset,
+ clk => kernel_clk,
- in_siso => dp_latency_adapter_tx_src_in_arr(mac),
- in_sosi => dp_latency_adapter_tx_src_out_arr(mac),
+ in_siso => dp_latency_adapter_tx_src_in_arr(mac),
+ in_sosi => dp_latency_adapter_tx_src_out_arr(mac),
- out_siso => dp_xonoff_src_in_arr(mac),
- out_sosi => dp_xonoff_src_out_arr(mac)
- );
+ out_siso => dp_xonoff_src_in_arr(mac),
+ out_sosi => dp_xonoff_src_out_arr(mac)
+ );
---------------------------------------------------------------------------------------
-- FIFO FILL with fill level/eop trigger so we can deliver packets to the MAC fast enough
---------------------------------------------------------------------------------------
u_dp_fifo_fill_tx_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_use_dual_clock => true,
- g_data_w => c_xgmii_data_w,
- g_empty_w => c_tech_mac_10g_empty_w,
- g_use_empty => true,
- g_fifo_fill => c_tx_fifo_fill,
- g_fifo_size => c_tx_fifo_size
- )
- port map (
- wr_rst => kernel_reset,
- wr_clk => kernel_clk,
- rd_rst => eth_tx_rst_arr(mac),
- rd_clk => eth_tx_clk_arr(mac),
-
- snk_out => dp_xonoff_src_in_arr(mac),
- snk_in => dp_xonoff_src_out_arr(mac),
-
- src_in => dp_fifo_fill_tx_src_in_arr(mac),
- src_out => dp_fifo_fill_tx_src_out_arr(mac)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_use_dual_clock => true,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => true,
+ g_fifo_fill => c_tx_fifo_fill,
+ g_fifo_size => c_tx_fifo_size
+ )
+ port map (
+ wr_rst => kernel_reset,
+ wr_clk => kernel_clk,
+ rd_rst => eth_tx_rst_arr(mac),
+ rd_clk => eth_tx_clk_arr(mac),
+
+ snk_out => dp_xonoff_src_in_arr(mac),
+ snk_in => dp_xonoff_src_out_arr(mac),
+
+ src_in => dp_fifo_fill_tx_src_in_arr(mac),
+ src_out => dp_fifo_fill_tx_src_out_arr(mac)
+ );
---------------------------------------------------------------------------------------
-- RX FIFO: rx_clk -> dp_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_data_w => c_xgmii_data_w,
- g_empty_w => c_tech_mac_10g_empty_w,
- g_use_empty => true,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_rst => eth_rx_rst_arr(mac),
- wr_clk => eth_rx_clk_arr(mac),
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => mac_10g_src_in_arr(mac),
- snk_in => mac_10g_src_out_arr(mac),
-
- src_in => dp_fifo_dc_rx_src_in_arr(mac),
- src_out => dp_fifo_dc_rx_src_out_arr(mac)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => true,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_rst => eth_rx_rst_arr(mac),
+ wr_clk => eth_rx_clk_arr(mac),
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => mac_10g_src_in_arr(mac),
+ snk_in => mac_10g_src_out_arr(mac),
+
+ src_in => dp_fifo_dc_rx_src_in_arr(mac),
+ src_out => dp_fifo_dc_rx_src_out_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_fifo_dc_rx_src_out_arr(mac),
- snk_out => dp_fifo_dc_rx_src_in_arr(mac),
+ snk_in => dp_fifo_dc_rx_src_out_arr(mac),
+ snk_out => dp_fifo_dc_rx_src_in_arr(mac),
- src_out => dp_latency_adapter_rx_src_out_arr(mac),
- src_in => dp_latency_adapter_rx_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -335,43 +335,43 @@ begin
src_out_arr(mac).valid <= dp_latency_adapter_rx_src_out_arr(mac).valid;
dp_latency_adapter_rx_src_in_arr(mac).ready <= src_in_arr(mac).ready;
dp_latency_adapter_rx_src_in_arr(mac).xon <= '1';
- end generate;
+ end generate;
---------------------------------------------------------------------------------------
-- ETH MAC + PHY
---------------------------------------------------------------------------------------
u_tech_eth_10g : entity tech_eth_10g_lib.tech_eth_10g
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_sim => c_sim,
- g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
- g_nof_channels => g_nof_mac,
- g_direction => "TX_RX",
- g_pre_header_padding => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM
- mm_clk => '0',
- mm_rst => '0',
-
- -- ST
- tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
- tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
-
- rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
- rx_src_in_arr => mac_10g_src_in_arr,
-
- -- PHY serial IO
- -- . 10GBASE-R (single lane)
- serial_tx_arr => tx_serial_r,
- serial_rx_arr => rx_serial_r
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_sim => c_sim,
+ g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels => g_nof_mac,
+ g_direction => "TX_RX",
+ g_pre_header_padding => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM
+ mm_clk => '0',
+ mm_rst => '0',
+
+ -- ST
+ tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
+ tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
+
+ rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
+ rx_src_in_arr => mac_10g_src_in_arr,
+
+ -- PHY serial IO
+ -- . 10GBASE-R (single lane)
+ serial_tx_arr => tx_serial_r,
+ serial_rx_arr => rx_serial_r
+ );
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
index d1e8fe88dc..534fb21536 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
@@ -44,11 +44,11 @@
-- | [38:39] | empty | On EOP, this field indicates how many bytes are unused |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_1GbE is
port (
@@ -96,8 +96,8 @@ architecture str of ta2_unb2b_1GbE is
begin
--------------------------------------------------------
- -- Mapping Data from OpenCL kernel to 1GbE Interface --
+ -------------------------------------------------------
+ -- Mapping Data from OpenCL kernel to 1GbE Interface --
-------------------------------------------------------
----------------------------------------------------------------------------
@@ -120,20 +120,20 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_latency_adapter_tx_snk_in,
- snk_out => dp_latency_adapter_tx_snk_out,
-
- src_out => dp_latency_adapter_tx_src_out,
- src_in => dp_latency_adapter_tx_src_in
- );
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_latency_adapter_tx_snk_in,
+ snk_out => dp_latency_adapter_tx_snk_out,
+
+ src_out => dp_latency_adapter_tx_src_out,
+ src_in => dp_latency_adapter_tx_src_in
+ );
-----------------------------------------------------------------------------
@@ -141,22 +141,22 @@ begin
-----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- rst => kernel_reset,
- clk => kernel_clk,
+ port map (
+ rst => kernel_reset,
+ clk => kernel_clk,
- in_siso => dp_latency_adapter_tx_src_in,
- in_sosi => dp_latency_adapter_tx_src_out,
+ in_siso => dp_latency_adapter_tx_src_in,
+ in_sosi => dp_latency_adapter_tx_src_out,
- out_siso => dp_xonoff_src_in,
- out_sosi => dp_xonoff_src_out
- );
+ out_siso => dp_xonoff_src_in,
+ out_sosi => dp_xonoff_src_out
+ );
-----------------------------------------------------------------------------
-- TX dual clock FIFO
-----------------------------------------------------------------------------
- u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_word_w,
@@ -177,14 +177,14 @@ begin
src_out => udp_tx_sosi
);
--------------------------------------------------------
- -- Mapping Data from 1GbE Interface to OpenCL kernel --
+ -------------------------------------------------------
+ -- Mapping Data from 1GbE Interface to OpenCL kernel --
-------------------------------------------------------
-----------------------------------------------------------------------------
-- TX dual clock FIFO
-----------------------------------------------------------------------------
- u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_word_w,
@@ -209,20 +209,20 @@ begin
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_rx_src_out,
- snk_out => dp_fifo_dc_rx_src_in,
-
- src_out => dp_latency_adapter_rx_src_out,
- src_in => dp_latency_adapter_rx_src_in
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_rx_src_out,
+ snk_out => dp_fifo_dc_rx_src_in,
+
+ src_out => dp_latency_adapter_rx_src_out,
+ src_in => dp_latency_adapter_rx_src_in
+ );
----------------------------------------------------------------------------
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
index 0f59d6bcbb..6cd7d595a3 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
@@ -24,7 +24,7 @@
-- Purpose:
-- . Instantiates ta2_unb2b_1GbE component
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity ta2_unb2b_1GbE_ip_wrapper is
port (
@@ -67,38 +67,38 @@ architecture str of ta2_unb2b_1GbE_ip_wrapper is
-- ta2_unb2b_1GbE Component
----------------------------------------------------------------------------
component ta2_unb2b_1GbE is
- port (
- st_clk : in std_logic;
- st_rst : in std_logic;
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_data : out std_logic_vector(39 downto 0);
- udp_tx_sosi_valid : out std_logic;
- udp_tx_sosi_sop : out std_logic;
- udp_tx_sosi_eop : out std_logic;
- udp_tx_sosi_empty : out std_logic_vector(1 downto 0);
- udp_tx_siso_ready : in std_logic;
- udp_tx_siso_xon : in std_logic;
-
- udp_rx_sosi_data : in std_logic_vector(39 downto 0);
- udp_rx_sosi_valid : in std_logic;
- udp_rx_sosi_sop : in std_logic;
- udp_rx_sosi_eop : in std_logic;
- udp_rx_sosi_empty : in std_logic_vector(1 downto 0);
- udp_rx_siso_ready : out std_logic;
- udp_rx_siso_xon : out std_logic;
-
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : in std_logic;
-
- kernel_src_data : out std_logic_vector(39 downto 0); -- RX Data to kernel
- kernel_src_valid : out std_logic; -- RX data valid signal to kernel
- kernel_src_ready : in std_logic; -- Flow control from kernel
-
- kernel_snk_data : in std_logic_vector(39 downto 0); -- TX Data from kernel
- kernel_snk_valid : in std_logic; -- TX data valid signal from kernel
- kernel_snk_ready : out std_logic -- Flow control towards kernel
- );
+ port (
+ st_clk : in std_logic;
+ st_rst : in std_logic;
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_data : out std_logic_vector(39 downto 0);
+ udp_tx_sosi_valid : out std_logic;
+ udp_tx_sosi_sop : out std_logic;
+ udp_tx_sosi_eop : out std_logic;
+ udp_tx_sosi_empty : out std_logic_vector(1 downto 0);
+ udp_tx_siso_ready : in std_logic;
+ udp_tx_siso_xon : in std_logic;
+
+ udp_rx_sosi_data : in std_logic_vector(39 downto 0);
+ udp_rx_sosi_valid : in std_logic;
+ udp_rx_sosi_sop : in std_logic;
+ udp_rx_sosi_eop : in std_logic;
+ udp_rx_sosi_empty : in std_logic_vector(1 downto 0);
+ udp_rx_siso_ready : out std_logic;
+ udp_rx_siso_xon : out std_logic;
+
+ kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ kernel_reset : in std_logic;
+
+ kernel_src_data : out std_logic_vector(39 downto 0); -- RX Data to kernel
+ kernel_src_valid : out std_logic; -- RX data valid signal to kernel
+ kernel_src_ready : in std_logic; -- Flow control from kernel
+
+ kernel_snk_data : in std_logic_vector(39 downto 0); -- TX Data from kernel
+ kernel_snk_valid : in std_logic; -- TX data valid signal from kernel
+ kernel_snk_ready : out std_logic -- Flow control towards kernel
+ );
end component ta2_unb2b_1GbE;
begin
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 2fce7e9a33..ea02008cf0 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -51,9 +51,9 @@
-- | 259:263 | empty | On EOP, this field indicates how many bytes are unused |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ta2_unb2b_40GbE is
generic (
@@ -155,118 +155,118 @@ architecture str of ta2_unb2b_40GbE is
-- ATX PLL Component
----------------------------------------------------------------------------
component arria10_40g_atx_pll is
- port (
- pll_cal_busy : out std_logic; -- pll_cal_busy
- pll_locked : out std_logic; -- pll_locked
- pll_powerdown : in std_logic := 'X'; -- pll_powerdown
- pll_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_clk : out std_logic -- clk
- );
+ port (
+ pll_cal_busy : out std_logic; -- pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked
+ pll_powerdown : in std_logic := 'X'; -- pll_powerdown
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_clk : out std_logic -- clk
+ );
end component arria10_40g_atx_pll;
----------------------------------------------------------------------------
-- 40G ETH IP Component
----------------------------------------------------------------------------
component arria10_40g_mac is
- port (
- l4_rx_error : out std_logic_vector(5 downto 0); -- l4_rx_error
- l4_rx_status : out std_logic_vector(2 downto 0); -- l4_rx_status
- l4_rx_valid : out std_logic; -- l4_rx_valid
- l4_rx_startofpacket : out std_logic; -- l4_rx_startofpacket
- l4_rx_endofpacket : out std_logic; -- l4_rx_endofpacket
- l4_rx_data : out std_logic_vector(255 downto 0); -- l4_rx_data
- l4_rx_empty : out std_logic_vector(4 downto 0); -- l4_rx_empty
- l4_rx_fcs_error : out std_logic; -- l4_rx_fcs_error
- l4_rx_fcs_valid : out std_logic; -- l4_rx_fcs_valid
- l4_tx_startofpacket : in std_logic := 'X'; -- l4_tx_startofpacket
- l4_tx_endofpacket : in std_logic := 'X'; -- l4_tx_endofpacket
- l4_tx_valid : in std_logic := 'X'; -- l4_tx_valid
- l4_tx_ready : out std_logic; -- l4_tx_ready
- l4_tx_empty : in std_logic_vector(4 downto 0) := (others => 'X'); -- l4_tx_empty
- l4_tx_data : in std_logic_vector(255 downto 0) := (others => 'X'); -- l4_tx_data
- l4_tx_error : in std_logic := 'X'; -- l4_tx_error
- clk_ref : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_ref
- clk_rxmac : out std_logic_vector(0 downto 0); -- clk_rxmac
- clk_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_status
- clk_txmac : out std_logic_vector(0 downto 0); -- clk_txmac
- reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- reconfig_address
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_clk
- reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_read
- reconfig_readdata : out std_logic_vector(31 downto 0); -- reconfig_readdata
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_reset
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- reconfig_waitrequest
- reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_write
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- reconfig_writedata
- reset_async : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_async
- reset_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_status
- rx_pcs_ready : out std_logic_vector(0 downto 0); -- rx_pcs_ready
- rx_serial : in std_logic_vector(3 downto 0) := (others => 'X'); -- rx_serial
- rx_inc_octetsOK : out std_logic_vector(15 downto 0); -- rx_inc_octetsOK
- rx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- rx_inc_octetsOK_valid
- rx_inc_runt : out std_logic_vector(0 downto 0); -- rx_inc_runt
- rx_inc_64 : out std_logic_vector(0 downto 0); -- rx_inc_64
- rx_inc_127 : out std_logic_vector(0 downto 0); -- rx_inc_127
- rx_inc_255 : out std_logic_vector(0 downto 0); -- rx_inc_255
- rx_inc_511 : out std_logic_vector(0 downto 0); -- rx_inc_511
- rx_inc_1023 : out std_logic_vector(0 downto 0); -- rx_inc_1023
- rx_inc_1518 : out std_logic_vector(0 downto 0); -- rx_inc_1518
- rx_inc_max : out std_logic_vector(0 downto 0); -- rx_inc_max
- rx_inc_over : out std_logic_vector(0 downto 0); -- rx_inc_over
- rx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_err
- rx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_ok
- rx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_err
- rx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_ok
- rx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_err
- rx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_ok
- rx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl
- rx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl
- rx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl
- rx_inc_pause : out std_logic_vector(0 downto 0); -- rx_inc_pause
- rx_inc_fcs_err : out std_logic_vector(0 downto 0); -- rx_inc_fcs_err
- rx_inc_fragment : out std_logic_vector(0 downto 0); -- rx_inc_fragment
- rx_inc_jabber : out std_logic_vector(0 downto 0); -- rx_inc_jabber
- rx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0); -- rx_inc_sizeok_fcserr
- rx_inc_pause_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_pause_ctrl_err
- rx_inc_mcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl_err
- rx_inc_bcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl_err
- rx_inc_ucast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl_err
- status_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_write
- status_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_read
- status_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- status_addr
- status_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- status_writedata
- status_readdata : out std_logic_vector(31 downto 0); -- status_readdata
- status_readdata_valid : out std_logic_vector(0 downto 0); -- status_readdata_valid
- status_waitrequest : out std_logic_vector(0 downto 0); -- status_waitrequest
- status_read_timeout : out std_logic_vector(0 downto 0); -- status_read_timeout
- tx_lanes_stable : out std_logic_vector(0 downto 0); -- tx_lanes_stable
- tx_pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_pll_locked
- tx_serial : out std_logic_vector(3 downto 0); -- tx_serial
- tx_serial_clk : in std_logic_vector(3 downto 0) := (others => 'X'); -- tx_serial_clk
- tx_inc_octetsOK : out std_logic_vector(15 downto 0); -- tx_inc_octetsOK
- tx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- tx_inc_octetsOK_valid
- tx_inc_64 : out std_logic_vector(0 downto 0); -- tx_inc_64
- tx_inc_127 : out std_logic_vector(0 downto 0); -- tx_inc_127
- tx_inc_255 : out std_logic_vector(0 downto 0); -- tx_inc_255
- tx_inc_511 : out std_logic_vector(0 downto 0); -- tx_inc_511
- tx_inc_1023 : out std_logic_vector(0 downto 0); -- tx_inc_1023
- tx_inc_1518 : out std_logic_vector(0 downto 0); -- tx_inc_1518
- tx_inc_max : out std_logic_vector(0 downto 0); -- tx_inc_max
- tx_inc_over : out std_logic_vector(0 downto 0); -- tx_inc_over
- tx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_err
- tx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_ok
- tx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_err
- tx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_ok
- tx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_err
- tx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_ok
- tx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_mcast_ctrl
- tx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_bcast_ctrl
- tx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_ucast_ctrl
- tx_inc_pause : out std_logic_vector(0 downto 0); -- tx_inc_pause
- tx_inc_fcs_err : out std_logic_vector(0 downto 0); -- tx_inc_fcs_err
- tx_inc_fragment : out std_logic_vector(0 downto 0); -- tx_inc_fragment
- tx_inc_jabber : out std_logic_vector(0 downto 0); -- tx_inc_jabber
- tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0) -- tx_inc_sizeok_fcserr
- );
+ port (
+ l4_rx_error : out std_logic_vector(5 downto 0); -- l4_rx_error
+ l4_rx_status : out std_logic_vector(2 downto 0); -- l4_rx_status
+ l4_rx_valid : out std_logic; -- l4_rx_valid
+ l4_rx_startofpacket : out std_logic; -- l4_rx_startofpacket
+ l4_rx_endofpacket : out std_logic; -- l4_rx_endofpacket
+ l4_rx_data : out std_logic_vector(255 downto 0); -- l4_rx_data
+ l4_rx_empty : out std_logic_vector(4 downto 0); -- l4_rx_empty
+ l4_rx_fcs_error : out std_logic; -- l4_rx_fcs_error
+ l4_rx_fcs_valid : out std_logic; -- l4_rx_fcs_valid
+ l4_tx_startofpacket : in std_logic := 'X'; -- l4_tx_startofpacket
+ l4_tx_endofpacket : in std_logic := 'X'; -- l4_tx_endofpacket
+ l4_tx_valid : in std_logic := 'X'; -- l4_tx_valid
+ l4_tx_ready : out std_logic; -- l4_tx_ready
+ l4_tx_empty : in std_logic_vector(4 downto 0) := (others => 'X'); -- l4_tx_empty
+ l4_tx_data : in std_logic_vector(255 downto 0) := (others => 'X'); -- l4_tx_data
+ l4_tx_error : in std_logic := 'X'; -- l4_tx_error
+ clk_ref : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_ref
+ clk_rxmac : out std_logic_vector(0 downto 0); -- clk_rxmac
+ clk_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_status
+ clk_txmac : out std_logic_vector(0 downto 0); -- clk_txmac
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- reconfig_address
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_clk
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_read
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- reconfig_readdata
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_reset
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- reconfig_waitrequest
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_write
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- reconfig_writedata
+ reset_async : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_async
+ reset_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_status
+ rx_pcs_ready : out std_logic_vector(0 downto 0); -- rx_pcs_ready
+ rx_serial : in std_logic_vector(3 downto 0) := (others => 'X'); -- rx_serial
+ rx_inc_octetsOK : out std_logic_vector(15 downto 0); -- rx_inc_octetsOK
+ rx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- rx_inc_octetsOK_valid
+ rx_inc_runt : out std_logic_vector(0 downto 0); -- rx_inc_runt
+ rx_inc_64 : out std_logic_vector(0 downto 0); -- rx_inc_64
+ rx_inc_127 : out std_logic_vector(0 downto 0); -- rx_inc_127
+ rx_inc_255 : out std_logic_vector(0 downto 0); -- rx_inc_255
+ rx_inc_511 : out std_logic_vector(0 downto 0); -- rx_inc_511
+ rx_inc_1023 : out std_logic_vector(0 downto 0); -- rx_inc_1023
+ rx_inc_1518 : out std_logic_vector(0 downto 0); -- rx_inc_1518
+ rx_inc_max : out std_logic_vector(0 downto 0); -- rx_inc_max
+ rx_inc_over : out std_logic_vector(0 downto 0); -- rx_inc_over
+ rx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_err
+ rx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_ok
+ rx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_err
+ rx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_ok
+ rx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_err
+ rx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_ok
+ rx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl
+ rx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl
+ rx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl
+ rx_inc_pause : out std_logic_vector(0 downto 0); -- rx_inc_pause
+ rx_inc_fcs_err : out std_logic_vector(0 downto 0); -- rx_inc_fcs_err
+ rx_inc_fragment : out std_logic_vector(0 downto 0); -- rx_inc_fragment
+ rx_inc_jabber : out std_logic_vector(0 downto 0); -- rx_inc_jabber
+ rx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0); -- rx_inc_sizeok_fcserr
+ rx_inc_pause_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_pause_ctrl_err
+ rx_inc_mcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl_err
+ rx_inc_bcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl_err
+ rx_inc_ucast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl_err
+ status_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_write
+ status_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_read
+ status_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- status_addr
+ status_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- status_writedata
+ status_readdata : out std_logic_vector(31 downto 0); -- status_readdata
+ status_readdata_valid : out std_logic_vector(0 downto 0); -- status_readdata_valid
+ status_waitrequest : out std_logic_vector(0 downto 0); -- status_waitrequest
+ status_read_timeout : out std_logic_vector(0 downto 0); -- status_read_timeout
+ tx_lanes_stable : out std_logic_vector(0 downto 0); -- tx_lanes_stable
+ tx_pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_pll_locked
+ tx_serial : out std_logic_vector(3 downto 0); -- tx_serial
+ tx_serial_clk : in std_logic_vector(3 downto 0) := (others => 'X'); -- tx_serial_clk
+ tx_inc_octetsOK : out std_logic_vector(15 downto 0); -- tx_inc_octetsOK
+ tx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- tx_inc_octetsOK_valid
+ tx_inc_64 : out std_logic_vector(0 downto 0); -- tx_inc_64
+ tx_inc_127 : out std_logic_vector(0 downto 0); -- tx_inc_127
+ tx_inc_255 : out std_logic_vector(0 downto 0); -- tx_inc_255
+ tx_inc_511 : out std_logic_vector(0 downto 0); -- tx_inc_511
+ tx_inc_1023 : out std_logic_vector(0 downto 0); -- tx_inc_1023
+ tx_inc_1518 : out std_logic_vector(0 downto 0); -- tx_inc_1518
+ tx_inc_max : out std_logic_vector(0 downto 0); -- tx_inc_max
+ tx_inc_over : out std_logic_vector(0 downto 0); -- tx_inc_over
+ tx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_err
+ tx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_ok
+ tx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_err
+ tx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_ok
+ tx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_err
+ tx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_ok
+ tx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_mcast_ctrl
+ tx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_bcast_ctrl
+ tx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_ucast_ctrl
+ tx_inc_pause : out std_logic_vector(0 downto 0); -- tx_inc_pause
+ tx_inc_fcs_err : out std_logic_vector(0 downto 0); -- tx_inc_fcs_err
+ tx_inc_fragment : out std_logic_vector(0 downto 0); -- tx_inc_fragment
+ tx_inc_jabber : out std_logic_vector(0 downto 0); -- tx_inc_jabber
+ tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0) -- tx_inc_sizeok_fcserr
+ );
end component arria10_40g_mac;
@@ -294,84 +294,84 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx_a : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_latency_adapter_tx_a_snk_in_arr(mac),
- snk_out => dp_latency_adapter_tx_a_snk_out_arr(mac),
-
- src_out => dp_latency_adapter_tx_a_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_a_src_in_arr(mac)
- );
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_latency_adapter_tx_a_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_a_snk_out_arr(mac),
+
+ src_out => dp_latency_adapter_tx_a_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_a_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- dp_xonoff: discard all TX frames until 40G MAC TX side is ready
----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- in_sosi => dp_latency_adapter_tx_a_src_out_arr(mac),
- in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
+ in_sosi => dp_latency_adapter_tx_a_src_out_arr(mac),
+ in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
- out_sosi => dp_xonoff_src_out_arr(mac),
- out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
- );
+ out_sosi => dp_xonoff_src_out_arr(mac),
+ out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
+ );
----------------------------------------------------------------------------
-- TX FIFO
----------------------------------------------------------------------------
u_dp_fifo_fill_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_data_w => c_data_w,
- g_use_dual_clock => true,
- g_empty_w => 8,
- g_use_empty => true,
- g_use_bsn => false,
- g_bsn_w => 64,
- g_use_channel => false,
- g_use_sync => false,
- g_fifo_size => c_tx_fifo_size,
- g_fifo_fill => c_tx_fifo_fill
- )
- port map (
- wr_clk => kernel_clk,
- wr_rst => kernel_reset,
-
- rd_clk => clk_txmac_arr(mac),
- rd_rst => rst_txmac_arr(mac),
-
- snk_in => dp_xonoff_src_out_arr(mac),
- snk_out => dp_xonoff_src_in_arr(mac),
-
- src_out => dp_fifo_fill_eop_src_out_arr(mac),
- src_in => dp_fifo_fill_eop_src_in_arr(mac)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_use_dual_clock => true,
+ g_empty_w => 8,
+ g_use_empty => true,
+ g_use_bsn => false,
+ g_bsn_w => 64,
+ g_use_channel => false,
+ g_use_sync => false,
+ g_fifo_size => c_tx_fifo_size,
+ g_fifo_fill => c_tx_fifo_fill
+ )
+ port map (
+ wr_clk => kernel_clk,
+ wr_rst => kernel_reset,
+
+ rd_clk => clk_txmac_arr(mac),
+ rd_rst => rst_txmac_arr(mac),
+
+ snk_in => dp_xonoff_src_out_arr(mac),
+ snk_out => dp_xonoff_src_in_arr(mac),
+
+ src_out => dp_fifo_fill_eop_src_out_arr(mac),
+ src_in => dp_fifo_fill_eop_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (upstream) to RL=0 (MAC TX interface).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx_b : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => clk_txmac_arr(mac),
- rst => rst_txmac_arr(mac),
-
- snk_in => dp_fifo_fill_eop_src_out_arr(mac),
- snk_out => dp_fifo_fill_eop_src_in_arr(mac),
-
- src_out => dp_latency_adapter_tx_b_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_b_src_in_arr(mac)
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => clk_txmac_arr(mac),
+ rst => rst_txmac_arr(mac),
+
+ snk_in => dp_fifo_fill_eop_src_out_arr(mac),
+ snk_out => dp_fifo_fill_eop_src_in_arr(mac),
+
+ src_out => dp_latency_adapter_tx_b_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_b_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- 40G MAC IP
@@ -381,110 +381,110 @@ begin
u_arria10_40g_mac : arria10_40g_mac
port map (
- reset_async(0) => mm_rst,
- clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
- clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
- clk_ref(0) => clk_ref_r,
- rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
-
- tx_serial_clk => serial_clk_2arr(mac),
- tx_pll_locked(0) => pll_locked_arr(mac),
-
- clk_status(0) => mm_clk,
- reset_status(0) => mm_rst,
- status_addr => (others => '0'),
- status_read => (others => '0'),
- status_write => (others => '0'),
- status_writedata => (others => '0'),
--- status_readdata => status_readdata_eth,
--- status_read_timeout => status_read_timeout,
--- status_readdata_valid => status_readdata_valid_eth,
-
- reconfig_clk(0) => mm_clk,
- reconfig_reset(0) => mm_rst,
- reconfig_write => (others => '0'),
- reconfig_read => (others => '0'),
- reconfig_address => (others => '0'),
- reconfig_writedata => (others => '0'),
--- reconfig_readdata => reco_readdata[31:0],
--- reconfig_waitrequest => reco_waitrequest,
-
- l4_tx_data => l4_tx_sosi_arr(mac).data(255 downto 0),
- l4_tx_empty => l4_tx_sosi_arr(mac).empty(4 downto 0),
- l4_tx_startofpacket => l4_tx_sosi_arr(mac).sop,
- l4_tx_endofpacket => l4_tx_sosi_arr(mac).eop,
- l4_tx_ready => l4_tx_siso_arr(mac).ready,
- l4_tx_valid => l4_tx_sosi_arr(mac).valid,
- l4_tx_error => '0',
-
- l4_rx_data => l4_rx_sosi_arr(mac).data(255 downto 0),
- l4_rx_empty => l4_rx_sosi_arr(mac).empty(4 downto 0),
- l4_rx_startofpacket => l4_rx_sosi_arr(mac).sop,
- l4_rx_endofpacket => l4_rx_sosi_arr(mac).eop,
- -- l4_rx_error => ,
- l4_rx_valid => l4_rx_sosi_arr(mac).valid,
-
- -- l4_rx_status (),
- -- l4_rx_fcs_error (),
- -- l4_rx_fcs_valid (),
- -- rx_inc_octetsOK (),
- -- rx_inc_octetsOK_valid (),
- -- rx_inc_runt (),
- -- rx_inc_64 (),
- -- rx_inc_127 (),
- -- rx_inc_255 (),
- -- rx_inc_511 (),
- -- rx_inc_1023 (),
- -- rx_inc_1518 (),
- -- rx_inc_max (),
- -- rx_inc_over (),
- -- rx_inc_mcast_data_err (),
- -- rx_inc_mcast_data_ok (),
- -- rx_inc_bcast_data_err (),
- -- rx_inc_bcast_data_ok (),
- -- rx_inc_ucast_data_err (),
- -- rx_inc_ucast_data_ok (),
- -- rx_inc_mcast_ctrl (),
- -- rx_inc_bcast_ctrl (),
- -- rx_inc_ucast_ctrl (),
- -- rx_inc_pause (),
- -- rx_inc_fcs_err (),
- -- rx_inc_fragment (),
- -- rx_inc_jabber (),
- -- rx_inc_sizeok_fcserr (),
- -- rx_inc_pause_ctrl_err (),
- -- rx_inc_mcast_ctrl_err (),
- -- rx_inc_bcast_ctrl_err (),
- -- rx_inc_ucast_ctrl_err (),
- -- status_waitrequest (),
- tx_lanes_stable(0) => l4_tx_siso_arr(mac).xon,
- -- tx_inc_octetsOK (),
- -- tx_inc_octetsOK_valid (),
- -- tx_inc_64 (),
- -- tx_inc_127 (),
- -- tx_inc_255 (),
- -- tx_inc_511 (),
- -- tx_inc_1023 (),
- -- tx_inc_1518 (),
- -- tx_inc_max (),
- -- tx_inc_over (),
- -- tx_inc_mcast_data_err (),
- -- tx_inc_mcast_data_ok (),
- -- tx_inc_bcast_data_err (),
- -- tx_inc_bcast_data_ok (),
- -- tx_inc_ucast_data_err (),
- -- tx_inc_ucast_data_ok (),
- -- tx_inc_mcast_ctrl (),
- -- tx_inc_bcast_ctrl (),
- -- tx_inc_ucast_ctrl (),
- -- tx_inc_pause (),
- -- tx_inc_fcs_err (),
- -- tx_inc_fragment (),
- -- tx_inc_jabber (),
- -- tx_inc_sizeok_fcserr (),
-
- tx_serial => tx_serial_r(4 * (mac + 1) - 1 downto 4 * mac),
- rx_serial => rx_serial_r(4 * (mac + 1) - 1 downto 4 * mac)
+ reset_async(0) => mm_rst,
+ clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_ref(0) => clk_ref_r,
+ rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
+
+ tx_serial_clk => serial_clk_2arr(mac),
+ tx_pll_locked(0) => pll_locked_arr(mac),
+
+ clk_status(0) => mm_clk,
+ reset_status(0) => mm_rst,
+ status_addr => (others => '0'),
+ status_read => (others => '0'),
+ status_write => (others => '0'),
+ status_writedata => (others => '0'),
+ -- status_readdata => status_readdata_eth,
+ -- status_read_timeout => status_read_timeout,
+ -- status_readdata_valid => status_readdata_valid_eth,
+
+ reconfig_clk(0) => mm_clk,
+ reconfig_reset(0) => mm_rst,
+ reconfig_write => (others => '0'),
+ reconfig_read => (others => '0'),
+ reconfig_address => (others => '0'),
+ reconfig_writedata => (others => '0'),
+ -- reconfig_readdata => reco_readdata[31:0],
+ -- reconfig_waitrequest => reco_waitrequest,
+
+ l4_tx_data => l4_tx_sosi_arr(mac).data(255 downto 0),
+ l4_tx_empty => l4_tx_sosi_arr(mac).empty(4 downto 0),
+ l4_tx_startofpacket => l4_tx_sosi_arr(mac).sop,
+ l4_tx_endofpacket => l4_tx_sosi_arr(mac).eop,
+ l4_tx_ready => l4_tx_siso_arr(mac).ready,
+ l4_tx_valid => l4_tx_sosi_arr(mac).valid,
+ l4_tx_error => '0',
+
+ l4_rx_data => l4_rx_sosi_arr(mac).data(255 downto 0),
+ l4_rx_empty => l4_rx_sosi_arr(mac).empty(4 downto 0),
+ l4_rx_startofpacket => l4_rx_sosi_arr(mac).sop,
+ l4_rx_endofpacket => l4_rx_sosi_arr(mac).eop,
+ -- l4_rx_error => ,
+ l4_rx_valid => l4_rx_sosi_arr(mac).valid,
+
+ -- l4_rx_status (),
+ -- l4_rx_fcs_error (),
+ -- l4_rx_fcs_valid (),
+ -- rx_inc_octetsOK (),
+ -- rx_inc_octetsOK_valid (),
+ -- rx_inc_runt (),
+ -- rx_inc_64 (),
+ -- rx_inc_127 (),
+ -- rx_inc_255 (),
+ -- rx_inc_511 (),
+ -- rx_inc_1023 (),
+ -- rx_inc_1518 (),
+ -- rx_inc_max (),
+ -- rx_inc_over (),
+ -- rx_inc_mcast_data_err (),
+ -- rx_inc_mcast_data_ok (),
+ -- rx_inc_bcast_data_err (),
+ -- rx_inc_bcast_data_ok (),
+ -- rx_inc_ucast_data_err (),
+ -- rx_inc_ucast_data_ok (),
+ -- rx_inc_mcast_ctrl (),
+ -- rx_inc_bcast_ctrl (),
+ -- rx_inc_ucast_ctrl (),
+ -- rx_inc_pause (),
+ -- rx_inc_fcs_err (),
+ -- rx_inc_fragment (),
+ -- rx_inc_jabber (),
+ -- rx_inc_sizeok_fcserr (),
+ -- rx_inc_pause_ctrl_err (),
+ -- rx_inc_mcast_ctrl_err (),
+ -- rx_inc_bcast_ctrl_err (),
+ -- rx_inc_ucast_ctrl_err (),
+ -- status_waitrequest (),
+ tx_lanes_stable(0) => l4_tx_siso_arr(mac).xon,
+ -- tx_inc_octetsOK (),
+ -- tx_inc_octetsOK_valid (),
+ -- tx_inc_64 (),
+ -- tx_inc_127 (),
+ -- tx_inc_255 (),
+ -- tx_inc_511 (),
+ -- tx_inc_1023 (),
+ -- tx_inc_1518 (),
+ -- tx_inc_max (),
+ -- tx_inc_over (),
+ -- tx_inc_mcast_data_err (),
+ -- tx_inc_mcast_data_ok (),
+ -- tx_inc_bcast_data_err (),
+ -- tx_inc_bcast_data_ok (),
+ -- tx_inc_ucast_data_err (),
+ -- tx_inc_ucast_data_ok (),
+ -- tx_inc_mcast_ctrl (),
+ -- tx_inc_bcast_ctrl (),
+ -- tx_inc_ucast_ctrl (),
+ -- tx_inc_pause (),
+ -- tx_inc_fcs_err (),
+ -- tx_inc_fragment (),
+ -- tx_inc_jabber (),
+ -- tx_inc_sizeok_fcserr (),
+
+ tx_serial => tx_serial_r(4 * (mac + 1) - 1 downto 4 * mac),
+ rx_serial => rx_serial_r(4 * (mac + 1) - 1 downto 4 * mac)
);
@@ -494,49 +494,49 @@ begin
----------------------------------------------------------------------------
rst_rxmac_arr(mac) <= not rx_pcs_ready_arr(mac);
u_dp_fifo_dc : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_empty_w => 8,
- g_use_empty => true,
- g_use_bsn => false,
- g_bsn_w => 64,
- g_use_channel => false,
- g_use_sync => false,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_clk => clk_rxmac_arr(mac),
- wr_rst => rst_rxmac_arr(mac),
-
- rd_clk => kernel_clk,
- rd_rst => kernel_reset,
-
- snk_in => l4_rx_sosi_arr(mac),
- snk_out => OPEN,
-
- src_out => dp_fifo_dc_src_out_arr(mac),
- src_in => dp_fifo_dc_src_in_arr(mac)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_empty_w => 8,
+ g_use_empty => true,
+ g_use_bsn => false,
+ g_bsn_w => 64,
+ g_use_channel => false,
+ g_use_sync => false,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_clk => clk_rxmac_arr(mac),
+ wr_rst => rst_rxmac_arr(mac),
+
+ rd_clk => kernel_clk,
+ rd_rst => kernel_reset,
+
+ snk_in => l4_rx_sosi_arr(mac),
+ snk_out => OPEN,
+
+ src_out => dp_fifo_dc_src_out_arr(mac),
+ src_in => dp_fifo_dc_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (dp_fifo_dc) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_src_out_arr(mac),
- snk_out => dp_fifo_dc_src_in_arr(mac),
-
- src_out => dp_latency_adapter_rx_src_out_arr(mac),
- src_in => dp_latency_adapter_rx_src_in_arr(mac)
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_src_out_arr(mac),
+ snk_out => dp_fifo_dc_src_in_arr(mac),
+
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -559,28 +559,28 @@ begin
-------------------------------------------------------------------------------
u_common_areset_txmac : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => kernel_reset,
- clk => clk_txmac_arr(mac),
- out_rst => rst_txmac_arr(mac)
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => kernel_reset,
+ clk => clk_txmac_arr(mac),
+ out_rst => rst_txmac_arr(mac)
+ );
-------------------------------------------------------------------------------
-- PLL for clock generation, every mac needs its own, due to clock nework limitations
-------------------------------------------------------------------------------
u_arria10_40g_atx_pll : arria10_40g_atx_pll
- port map (
- pll_cal_busy => OPEN,
- pll_locked => pll_locked_arr(mac),
- pll_powerdown => mm_rst,
- pll_refclk0 => clk_ref_r,
- tx_serial_clk => serial_clk_arr(mac)
- );
+ port map (
+ pll_cal_busy => OPEN,
+ pll_locked => pll_locked_arr(mac),
+ pll_powerdown => mm_rst,
+ pll_refclk0 => clk_ref_r,
+ tx_serial_clk => serial_clk_arr(mac)
+ );
gen_serial_clk_arr : for i in 0 to 3 generate
serial_clk_2arr(mac)(i) <= serial_clk_arr(mac);
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
index 5f484fa675..da12e9d785 100644
--- a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
+++ b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
@@ -32,11 +32,11 @@
-- . This core was developed for use on the Uniboard2b.
-- . The curret implementation only works with ddr4_8g_1600m
library IEEE, common_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_component_pkg.all;
entity ta2_unb2b_ddr is
generic (
@@ -199,80 +199,80 @@ architecture str of ta2_unb2b_ddr is
-- MM Pipe stage component
component ta2_unb2b_ddr_pipe_stage is
- generic (
- DATA_WIDTH : integer := 32;
- SYMBOL_WIDTH : integer := 8;
- HDL_ADDR_WIDTH : integer := 10;
- BURSTCOUNT_WIDTH : integer := 1;
- PIPELINE_COMMAND : integer := 1;
- PIPELINE_RESPONSE : integer := 1;
- SYNC_RESET : integer := 0
- );
- port (
- clk : in std_logic := 'X'; -- clk
- m0_waitrequest : in std_logic := 'X'; -- waitrequest
- m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
- m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
- m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
- m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
- m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
- m0_write : out std_logic; -- write
- m0_read : out std_logic; -- read
- m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
- m0_debugaccess : out std_logic; -- debugaccess
- reset : in std_logic := 'X'; -- reset
- s0_waitrequest : out std_logic; -- waitrequest
- s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
- s0_readdatavalid : out std_logic; -- readdatavalid
- s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
- s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
- s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
- s0_write : in std_logic := 'X'; -- write
- s0_read : in std_logic := 'X'; -- read
- s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- s0_debugaccess : in std_logic := 'X' -- debugaccess
- );
- end component ta2_unb2b_ddr_pipe_stage;
-
- -- MM clock cross component
- component ta2_unb2b_ddr_clock_cross is
- generic (
- DATA_WIDTH : integer := 32;
- SYMBOL_WIDTH : integer := 8;
- HDL_ADDR_WIDTH : integer := 10;
- BURSTCOUNT_WIDTH : integer := 1;
- COMMAND_FIFO_DEPTH : integer := 4;
- RESPONSE_FIFO_DEPTH : integer := 4;
- MASTER_SYNC_DEPTH : integer := 2;
- SLAVE_SYNC_DEPTH : integer := 2
- );
- port (
- m0_waitrequest : in std_logic := 'X'; -- waitrequest
- m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
- m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
- m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
- m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
- m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
- m0_write : out std_logic; -- write
- m0_read : out std_logic; -- read
- m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
- m0_debugaccess : out std_logic; -- debugaccess
- m0_clk : in std_logic := 'X'; -- clk
- m0_reset : in std_logic := 'X'; -- reset
- s0_waitrequest : out std_logic; -- waitrequest
- s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
- s0_readdatavalid : out std_logic; -- readdatavalid
- s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
- s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
- s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
- s0_write : in std_logic := 'X'; -- write
- s0_read : in std_logic := 'X'; -- read
- s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- s0_debugaccess : in std_logic := 'X'; -- debugaccess
- s0_clk : in std_logic := 'X'; -- clk
- s0_reset : in std_logic := 'X' -- reset
- );
- end component ta2_unb2b_ddr_clock_cross;
+ generic (
+ DATA_WIDTH : integer := 32;
+ SYMBOL_WIDTH : integer := 8;
+ HDL_ADDR_WIDTH : integer := 10;
+ BURSTCOUNT_WIDTH : integer := 1;
+ PIPELINE_COMMAND : integer := 1;
+ PIPELINE_RESPONSE : integer := 1;
+ SYNC_RESET : integer := 0
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
+ m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
+ m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
+ m0_write : out std_logic; -- write
+ m0_read : out std_logic; -- read
+ m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ reset : in std_logic := 'X'; -- reset
+ s0_waitrequest : out std_logic; -- waitrequest
+ s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
+ s0_readdatavalid : out std_logic; -- readdatavalid
+ s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
+ s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
+ s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
+ s0_write : in std_logic := 'X'; -- write
+ s0_read : in std_logic := 'X'; -- read
+ s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ s0_debugaccess : in std_logic := 'X' -- debugaccess
+ );
+ end component ta2_unb2b_ddr_pipe_stage;
+
+ -- MM clock cross component
+ component ta2_unb2b_ddr_clock_cross is
+ generic (
+ DATA_WIDTH : integer := 32;
+ SYMBOL_WIDTH : integer := 8;
+ HDL_ADDR_WIDTH : integer := 10;
+ BURSTCOUNT_WIDTH : integer := 1;
+ COMMAND_FIFO_DEPTH : integer := 4;
+ RESPONSE_FIFO_DEPTH : integer := 4;
+ MASTER_SYNC_DEPTH : integer := 2;
+ SLAVE_SYNC_DEPTH : integer := 2
+ );
+ port (
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
+ m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
+ m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
+ m0_write : out std_logic; -- write
+ m0_read : out std_logic; -- read
+ m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_clk : in std_logic := 'X'; -- clk
+ m0_reset : in std_logic := 'X'; -- reset
+ s0_waitrequest : out std_logic; -- waitrequest
+ s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
+ s0_readdatavalid : out std_logic; -- readdatavalid
+ s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
+ s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
+ s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
+ s0_write : in std_logic := 'X'; -- write
+ s0_read : in std_logic := 'X'; -- read
+ s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ s0_debugaccess : in std_logic := 'X'; -- debugaccess
+ s0_clk : in std_logic := 'X'; -- clk
+ s0_reset : in std_logic := 'X' -- reset
+ );
+ end component ta2_unb2b_ddr_clock_cross;
begin
@@ -280,77 +280,77 @@ begin
gen_MB_I : if g_use_MB_I generate
u_mb_I_clock_cross : ta2_unb2b_ddr_clock_cross
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- COMMAND_FIFO_DEPTH => c_command_fifo_depth,
- RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
- MASTER_SYNC_DEPTH => c_master_sync_depth,
- SLAVE_SYNC_DEPTH => c_slave_sync_depth
- )
- port map (
- m0_waitrequest => mb_I_pipe_stage_s0_waitrequest,
- m0_readdata => mb_I_pipe_stage_s0_readdata,
- m0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid,
- m0_burstcount => mb_I_pipe_stage_s0_burstcount,
- m0_writedata => mb_I_pipe_stage_s0_writedata,
- m0_address => mb_I_pipe_stage_s0_address,
- m0_write => mb_I_pipe_stage_s0_write,
- m0_read => mb_I_pipe_stage_s0_read,
- m0_byteenable => mb_I_pipe_stage_s0_byteenable,
- m0_debugaccess => mb_I_pipe_stage_s0_debugaccess,
- m0_clk => mb_I_emif_usr_clk,
- m0_reset => mb_I_emif_usr_reset,
- s0_waitrequest => mem0_waitrequest,
- s0_readdata => mem0_readdata,
- s0_readdatavalid => mem0_readdatavalid,
- s0_burstcount => mem0_burstcount,
- s0_writedata => mem0_writedata,
- s0_address => mem0_address,
- s0_write => mem0_write,
- s0_read => mem0_read,
- s0_byteenable => mem0_byteenable,
- s0_debugaccess => mem0_debugaccess,
- s0_clk => kernel_clk,
- s0_reset => kernel_reset
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ COMMAND_FIFO_DEPTH => c_command_fifo_depth,
+ RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
+ MASTER_SYNC_DEPTH => c_master_sync_depth,
+ SLAVE_SYNC_DEPTH => c_slave_sync_depth
+ )
+ port map (
+ m0_waitrequest => mb_I_pipe_stage_s0_waitrequest,
+ m0_readdata => mb_I_pipe_stage_s0_readdata,
+ m0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid,
+ m0_burstcount => mb_I_pipe_stage_s0_burstcount,
+ m0_writedata => mb_I_pipe_stage_s0_writedata,
+ m0_address => mb_I_pipe_stage_s0_address,
+ m0_write => mb_I_pipe_stage_s0_write,
+ m0_read => mb_I_pipe_stage_s0_read,
+ m0_byteenable => mb_I_pipe_stage_s0_byteenable,
+ m0_debugaccess => mb_I_pipe_stage_s0_debugaccess,
+ m0_clk => mb_I_emif_usr_clk,
+ m0_reset => mb_I_emif_usr_reset,
+ s0_waitrequest => mem0_waitrequest,
+ s0_readdata => mem0_readdata,
+ s0_readdatavalid => mem0_readdatavalid,
+ s0_burstcount => mem0_burstcount,
+ s0_writedata => mem0_writedata,
+ s0_address => mem0_address,
+ s0_write => mem0_write,
+ s0_read => mem0_read,
+ s0_byteenable => mem0_byteenable,
+ s0_debugaccess => mem0_debugaccess,
+ s0_clk => kernel_clk,
+ s0_reset => kernel_reset
+ );
u_mb_I_pipe_stage : ta2_unb2b_ddr_pipe_stage
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- PIPELINE_COMMAND => c_pipeline_command,
- PIPELINE_RESPONSE => c_pipeline_response,
- SYNC_RESET => c_sync_reset
- )
- port map (
- clk => mb_I_emif_usr_clk, -- clk.clk
- m0_waitrequest => mb_I_pipe_stage_m0_waitrequest,
- m0_readdata => mb_I_pipe_stage_m0_readdata,
- m0_readdatavalid => mb_I_pipe_stage_m0_readdatavalid,
- m0_burstcount => mb_I_pipe_stage_m0_burstcount,
- m0_writedata => mb_I_pipe_stage_m0_writedata,
- m0_address => mb_I_pipe_stage_m0_address,
- m0_write => mb_I_pipe_stage_m0_write,
- m0_read => mb_I_pipe_stage_m0_read,
- m0_byteenable => mb_I_pipe_stage_m0_byteenable,
- m0_debugaccess => mb_I_pipe_stage_m0_debugaccess,
- reset => mb_I_emif_usr_reset, -- reset.reset
- s0_waitrequest => mb_I_pipe_stage_s0_waitrequest, -- s0.waitrequest
- s0_readdata => mb_I_pipe_stage_s0_readdata, -- .readdata
- s0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid, -- .readdatavalid
- s0_burstcount => mb_I_pipe_stage_s0_burstcount, -- .burstcount
- s0_writedata => mb_I_pipe_stage_s0_writedata, -- .writedata
- s0_address => mb_I_pipe_stage_s0_address, -- .address
- s0_write => mb_I_pipe_stage_s0_write, -- .write
- s0_read => mb_I_pipe_stage_s0_read, -- .read
- s0_byteenable => mb_I_pipe_stage_s0_byteenable, -- .byteenable
- s0_debugaccess => mb_I_pipe_stage_s0_debugaccess -- .debugaccess
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ PIPELINE_COMMAND => c_pipeline_command,
+ PIPELINE_RESPONSE => c_pipeline_response,
+ SYNC_RESET => c_sync_reset
+ )
+ port map (
+ clk => mb_I_emif_usr_clk, -- clk.clk
+ m0_waitrequest => mb_I_pipe_stage_m0_waitrequest,
+ m0_readdata => mb_I_pipe_stage_m0_readdata,
+ m0_readdatavalid => mb_I_pipe_stage_m0_readdatavalid,
+ m0_burstcount => mb_I_pipe_stage_m0_burstcount,
+ m0_writedata => mb_I_pipe_stage_m0_writedata,
+ m0_address => mb_I_pipe_stage_m0_address,
+ m0_write => mb_I_pipe_stage_m0_write,
+ m0_read => mb_I_pipe_stage_m0_read,
+ m0_byteenable => mb_I_pipe_stage_m0_byteenable,
+ m0_debugaccess => mb_I_pipe_stage_m0_debugaccess,
+ reset => mb_I_emif_usr_reset, -- reset.reset
+ s0_waitrequest => mb_I_pipe_stage_s0_waitrequest, -- s0.waitrequest
+ s0_readdata => mb_I_pipe_stage_s0_readdata, -- .readdata
+ s0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid, -- .readdatavalid
+ s0_burstcount => mb_I_pipe_stage_s0_burstcount, -- .burstcount
+ s0_writedata => mb_I_pipe_stage_s0_writedata, -- .writedata
+ s0_address => mb_I_pipe_stage_s0_address, -- .address
+ s0_write => mb_I_pipe_stage_s0_write, -- .write
+ s0_read => mb_I_pipe_stage_s0_read, -- .read
+ s0_byteenable => mb_I_pipe_stage_s0_byteenable, -- .byteenable
+ s0_debugaccess => mb_I_pipe_stage_s0_debugaccess -- .debugaccess
+ );
mb_I_pipe_stage_m0_waitrequest <= not mb_I_amm_ready_0;
mb_I_pipe_stage_m0_readdatavalid <= mb_I_amm_readdatavalid_0;
@@ -369,40 +369,40 @@ begin
gen_I_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_I.name = "DDR4" and c_gigabytes_MB_I = 8 and g_ddr_MB_I.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
- port map (
- amm_ready_0 => mb_I_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => mb_I_amm_read_0, -- .read
- amm_write_0 => mb_I_amm_write_0, -- .write
- amm_address_0 => mb_I_amm_address_0, -- .address
- amm_readdata_0 => mb_I_amm_readdata_0, -- .readdata
- amm_writedata_0 => mb_I_amm_writedata_0, -- .writedata
- amm_burstcount_0 => mb_I_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => mb_I_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => mb_I_amm_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => mb_I_emif_usr_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => mb_I_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => mb_I_ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => mb_I_ou.ck(g_ddr_MB_I.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => mb_I_ou.ck_n(g_ddr_MB_I.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => mb_I_ou.a(g_ddr_MB_I.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => mb_I_ou.act_n, -- .mem_act_n
- mem_ba => mb_I_ou.ba(g_ddr_MB_I.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => mb_I_ou.bg(g_ddr_MB_I.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => mb_I_ou.cke(g_ddr_MB_I.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => mb_I_ou.cs_n(g_ddr_MB_I.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => mb_I_ou.odt(g_ddr_MB_I.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => mb_I_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => mb_I_ou.par, -- .mem_par
- mem_alert_n => slv(mb_I_in.alert_n), -- .mem_alert_n
- mem_dqs => mb_I_io.dqs(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => mb_I_io.dqs_n(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => mb_I_io.dq(g_ddr_MB_I.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => mb_I_io.dbi_n(g_ddr_MB_I.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => mb_I_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => mb_I_ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => OPEN, -- status_conduit_end.local_cal_success
- local_cal_fail => open -- .local_cal_fail
- );
+ port map (
+ amm_ready_0 => mb_I_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 => mb_I_amm_read_0, -- .read
+ amm_write_0 => mb_I_amm_write_0, -- .write
+ amm_address_0 => mb_I_amm_address_0, -- .address
+ amm_readdata_0 => mb_I_amm_readdata_0, -- .readdata
+ amm_writedata_0 => mb_I_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => mb_I_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => mb_I_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => mb_I_amm_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => mb_I_emif_usr_clk, -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n => mb_I_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
+ global_reset_n => mb_I_ref_rst_n, -- global_reset_reset_sink.reset_n
+ mem_ck => mb_I_ou.ck(g_ddr_MB_I.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
+ mem_ck_n => mb_I_ou.ck_n(g_ddr_MB_I.ck_w - 1 downto 0), -- .mem_ck_n
+ mem_a => mb_I_ou.a(g_ddr_MB_I.a_w - 1 downto 0), -- .mem_a
+ sl(mem_act_n) => mb_I_ou.act_n, -- .mem_act_n
+ mem_ba => mb_I_ou.ba(g_ddr_MB_I.ba_w - 1 downto 0), -- .mem_ba
+ mem_bg => mb_I_ou.bg(g_ddr_MB_I.bg_w - 1 downto 0), -- .mem_bg
+ mem_cke => mb_I_ou.cke(g_ddr_MB_I.cke_w - 1 downto 0), -- .mem_cke
+ mem_cs_n => mb_I_ou.cs_n(g_ddr_MB_I.cs_w - 1 downto 0), -- .mem_cs_n
+ mem_odt => mb_I_ou.odt(g_ddr_MB_I.odt_w - 1 downto 0), -- .mem_odt
+ sl(mem_reset_n) => mb_I_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => mb_I_ou.par, -- .mem_par
+ mem_alert_n => slv(mb_I_in.alert_n), -- .mem_alert_n
+ mem_dqs => mb_I_io.dqs(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs
+ mem_dqs_n => mb_I_io.dqs_n(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs_n
+ mem_dq => mb_I_io.dq(g_ddr_MB_I.dq_w - 1 downto 0), -- .mem_dq
+ mem_dbi_n => mb_I_io.dbi_n(g_ddr_MB_I.dbi_w - 1 downto 0), -- .mem_dbi_n
+ oct_rzqin => mb_I_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
+ pll_ref_clk => mb_I_ref_clk, -- pll_ref_clk_clock_sink.clk
+ local_cal_success => OPEN, -- status_conduit_end.local_cal_success
+ local_cal_fail => open -- .local_cal_fail
+ );
end generate;
@@ -412,77 +412,77 @@ begin
gen_MB_II : if g_use_MB_II generate
u_mb_II_clock_cross : ta2_unb2b_ddr_clock_cross
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- COMMAND_FIFO_DEPTH => c_command_fifo_depth,
- RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
- MASTER_SYNC_DEPTH => c_master_sync_depth,
- SLAVE_SYNC_DEPTH => c_slave_sync_depth
- )
- port map (
- m0_waitrequest => mb_II_pipe_stage_s0_waitrequest,
- m0_readdata => mb_II_pipe_stage_s0_readdata,
- m0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid,
- m0_burstcount => mb_II_pipe_stage_s0_burstcount,
- m0_writedata => mb_II_pipe_stage_s0_writedata,
- m0_address => mb_II_pipe_stage_s0_address,
- m0_write => mb_II_pipe_stage_s0_write,
- m0_read => mb_II_pipe_stage_s0_read,
- m0_byteenable => mb_II_pipe_stage_s0_byteenable,
- m0_debugaccess => mb_II_pipe_stage_s0_debugaccess,
- m0_clk => mb_II_emif_usr_clk,
- m0_reset => mb_II_emif_usr_reset,
- s0_waitrequest => mem1_waitrequest,
- s0_readdata => mem1_readdata,
- s0_readdatavalid => mem1_readdatavalid,
- s0_burstcount => mem1_burstcount,
- s0_writedata => mem1_writedata,
- s0_address => mem1_address,
- s0_write => mem1_write,
- s0_read => mem1_read,
- s0_byteenable => mem1_byteenable,
- s0_debugaccess => mem1_debugaccess,
- s0_clk => kernel_clk,
- s0_reset => kernel_reset
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ COMMAND_FIFO_DEPTH => c_command_fifo_depth,
+ RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
+ MASTER_SYNC_DEPTH => c_master_sync_depth,
+ SLAVE_SYNC_DEPTH => c_slave_sync_depth
+ )
+ port map (
+ m0_waitrequest => mb_II_pipe_stage_s0_waitrequest,
+ m0_readdata => mb_II_pipe_stage_s0_readdata,
+ m0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid,
+ m0_burstcount => mb_II_pipe_stage_s0_burstcount,
+ m0_writedata => mb_II_pipe_stage_s0_writedata,
+ m0_address => mb_II_pipe_stage_s0_address,
+ m0_write => mb_II_pipe_stage_s0_write,
+ m0_read => mb_II_pipe_stage_s0_read,
+ m0_byteenable => mb_II_pipe_stage_s0_byteenable,
+ m0_debugaccess => mb_II_pipe_stage_s0_debugaccess,
+ m0_clk => mb_II_emif_usr_clk,
+ m0_reset => mb_II_emif_usr_reset,
+ s0_waitrequest => mem1_waitrequest,
+ s0_readdata => mem1_readdata,
+ s0_readdatavalid => mem1_readdatavalid,
+ s0_burstcount => mem1_burstcount,
+ s0_writedata => mem1_writedata,
+ s0_address => mem1_address,
+ s0_write => mem1_write,
+ s0_read => mem1_read,
+ s0_byteenable => mem1_byteenable,
+ s0_debugaccess => mem1_debugaccess,
+ s0_clk => kernel_clk,
+ s0_reset => kernel_reset
+ );
u_mb_II_pipe_stage : ta2_unb2b_ddr_pipe_stage
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- PIPELINE_COMMAND => c_pipeline_command,
- PIPELINE_RESPONSE => c_pipeline_response,
- SYNC_RESET => c_sync_reset
- )
- port map (
- clk => mb_II_emif_usr_clk, -- clk.clk
- m0_waitrequest => mb_II_pipe_stage_m0_waitrequest,
- m0_readdata => mb_II_pipe_stage_m0_readdata,
- m0_readdatavalid => mb_II_pipe_stage_m0_readdatavalid,
- m0_burstcount => mb_II_pipe_stage_m0_burstcount,
- m0_writedata => mb_II_pipe_stage_m0_writedata,
- m0_address => mb_II_pipe_stage_m0_address,
- m0_write => mb_II_pipe_stage_m0_write,
- m0_read => mb_II_pipe_stage_m0_read,
- m0_byteenable => mb_II_pipe_stage_m0_byteenable,
- m0_debugaccess => mb_II_pipe_stage_m0_debugaccess,
- reset => mb_II_emif_usr_reset, -- reset.reset
- s0_waitrequest => mb_II_pipe_stage_s0_waitrequest, -- s0.waitrequest
- s0_readdata => mb_II_pipe_stage_s0_readdata, -- .readdata
- s0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid, -- .readdatavalid
- s0_burstcount => mb_II_pipe_stage_s0_burstcount, -- .burstcount
- s0_writedata => mb_II_pipe_stage_s0_writedata, -- .writedata
- s0_address => mb_II_pipe_stage_s0_address, -- .address
- s0_write => mb_II_pipe_stage_s0_write, -- .write
- s0_read => mb_II_pipe_stage_s0_read, -- .read
- s0_byteenable => mb_II_pipe_stage_s0_byteenable, -- .byteenable
- s0_debugaccess => mb_II_pipe_stage_s0_debugaccess -- .debugaccess
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ PIPELINE_COMMAND => c_pipeline_command,
+ PIPELINE_RESPONSE => c_pipeline_response,
+ SYNC_RESET => c_sync_reset
+ )
+ port map (
+ clk => mb_II_emif_usr_clk, -- clk.clk
+ m0_waitrequest => mb_II_pipe_stage_m0_waitrequest,
+ m0_readdata => mb_II_pipe_stage_m0_readdata,
+ m0_readdatavalid => mb_II_pipe_stage_m0_readdatavalid,
+ m0_burstcount => mb_II_pipe_stage_m0_burstcount,
+ m0_writedata => mb_II_pipe_stage_m0_writedata,
+ m0_address => mb_II_pipe_stage_m0_address,
+ m0_write => mb_II_pipe_stage_m0_write,
+ m0_read => mb_II_pipe_stage_m0_read,
+ m0_byteenable => mb_II_pipe_stage_m0_byteenable,
+ m0_debugaccess => mb_II_pipe_stage_m0_debugaccess,
+ reset => mb_II_emif_usr_reset, -- reset.reset
+ s0_waitrequest => mb_II_pipe_stage_s0_waitrequest, -- s0.waitrequest
+ s0_readdata => mb_II_pipe_stage_s0_readdata, -- .readdata
+ s0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid, -- .readdatavalid
+ s0_burstcount => mb_II_pipe_stage_s0_burstcount, -- .burstcount
+ s0_writedata => mb_II_pipe_stage_s0_writedata, -- .writedata
+ s0_address => mb_II_pipe_stage_s0_address, -- .address
+ s0_write => mb_II_pipe_stage_s0_write, -- .write
+ s0_read => mb_II_pipe_stage_s0_read, -- .read
+ s0_byteenable => mb_II_pipe_stage_s0_byteenable, -- .byteenable
+ s0_debugaccess => mb_II_pipe_stage_s0_debugaccess -- .debugaccess
+ );
mb_II_pipe_stage_m0_waitrequest <= not mb_II_amm_ready_0;
mb_II_pipe_stage_m0_readdatavalid <= mb_II_amm_readdatavalid_0;
@@ -501,40 +501,40 @@ begin
gen_II_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_II.name = "DDR4" and c_gigabytes_MB_II = 8 and g_ddr_MB_II.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
- port map (
- amm_ready_0 => mb_II_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => mb_II_amm_read_0, -- .read
- amm_write_0 => mb_II_amm_write_0, -- .write
- amm_address_0 => mb_II_amm_address_0, -- .address
- amm_readdata_0 => mb_II_amm_readdata_0, -- .readdata
- amm_writedata_0 => mb_II_amm_writedata_0, -- .writedata
- amm_burstcount_0 => mb_II_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => mb_II_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => mb_II_amm_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => mb_II_emif_usr_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => mb_II_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => mb_II_ref_rst_n, -- global_reset_reset_sink.reset_n
- mem_ck => mb_II_ou.ck(g_ddr_MB_II.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
- mem_ck_n => mb_II_ou.ck_n(g_ddr_MB_II.ck_w - 1 downto 0), -- .mem_ck_n
- mem_a => mb_II_ou.a(g_ddr_MB_II.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => mb_II_ou.act_n, -- .mem_act_n
- mem_ba => mb_II_ou.ba(g_ddr_MB_II.ba_w - 1 downto 0), -- .mem_ba
- mem_bg => mb_II_ou.bg(g_ddr_MB_II.bg_w - 1 downto 0), -- .mem_bg
- mem_cke => mb_II_ou.cke(g_ddr_MB_II.cke_w - 1 downto 0), -- .mem_cke
- mem_cs_n => mb_II_ou.cs_n(g_ddr_MB_II.cs_w - 1 downto 0), -- .mem_cs_n
- mem_odt => mb_II_ou.odt(g_ddr_MB_II.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => mb_II_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => mb_II_ou.par, -- .mem_par
- mem_alert_n => slv(mb_II_in.alert_n), -- .mem_alert_n
- mem_dqs => mb_II_io.dqs(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs
- mem_dqs_n => mb_II_io.dqs_n(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs_n
- mem_dq => mb_II_io.dq(g_ddr_MB_II.dq_w - 1 downto 0), -- .mem_dq
- mem_dbi_n => mb_II_io.dbi_n(g_ddr_MB_II.dbi_w - 1 downto 0), -- .mem_dbi_n
- oct_rzqin => mb_II_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => mb_II_ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => OPEN, -- status_conduit_end.local_cal_success
- local_cal_fail => open -- .local_cal_fail
- );
+ port map (
+ amm_ready_0 => mb_II_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 => mb_II_amm_read_0, -- .read
+ amm_write_0 => mb_II_amm_write_0, -- .write
+ amm_address_0 => mb_II_amm_address_0, -- .address
+ amm_readdata_0 => mb_II_amm_readdata_0, -- .readdata
+ amm_writedata_0 => mb_II_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => mb_II_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => mb_II_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => mb_II_amm_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => mb_II_emif_usr_clk, -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n => mb_II_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
+ global_reset_n => mb_II_ref_rst_n, -- global_reset_reset_sink.reset_n
+ mem_ck => mb_II_ou.ck(g_ddr_MB_II.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
+ mem_ck_n => mb_II_ou.ck_n(g_ddr_MB_II.ck_w - 1 downto 0), -- .mem_ck_n
+ mem_a => mb_II_ou.a(g_ddr_MB_II.a_w - 1 downto 0), -- .mem_a
+ sl(mem_act_n) => mb_II_ou.act_n, -- .mem_act_n
+ mem_ba => mb_II_ou.ba(g_ddr_MB_II.ba_w - 1 downto 0), -- .mem_ba
+ mem_bg => mb_II_ou.bg(g_ddr_MB_II.bg_w - 1 downto 0), -- .mem_bg
+ mem_cke => mb_II_ou.cke(g_ddr_MB_II.cke_w - 1 downto 0), -- .mem_cke
+ mem_cs_n => mb_II_ou.cs_n(g_ddr_MB_II.cs_w - 1 downto 0), -- .mem_cs_n
+ mem_odt => mb_II_ou.odt(g_ddr_MB_II.odt_w - 1 downto 0), -- .mem_odt
+ sl(mem_reset_n) => mb_II_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => mb_II_ou.par, -- .mem_par
+ mem_alert_n => slv(mb_II_in.alert_n), -- .mem_alert_n
+ mem_dqs => mb_II_io.dqs(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs
+ mem_dqs_n => mb_II_io.dqs_n(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs_n
+ mem_dq => mb_II_io.dq(g_ddr_MB_II.dq_w - 1 downto 0), -- .mem_dq
+ mem_dbi_n => mb_II_io.dbi_n(g_ddr_MB_II.dbi_w - 1 downto 0), -- .mem_dbi_n
+ oct_rzqin => mb_II_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
+ pll_ref_clk => mb_II_ref_clk, -- pll_ref_clk_clock_sink.clk
+ local_cal_success => OPEN, -- status_conduit_end.local_cal_success
+ local_cal_fail => open -- .local_cal_fail
+ );
end generate;
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
index 0948a6c745..babd3730a0 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
@@ -42,12 +42,12 @@
-- | [0:15] | payload | ADC channel 0 sample |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_jesd204b is
generic (
@@ -109,32 +109,32 @@ begin
jesd204b_disable_arr <= (others => '0');
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => c_sim,
- g_nof_streams => c_nof_streams_jesd204b
- )
- port map(
- jesd204b_refclk => jesd204b_refclk,
- jesd204b_sysref => jesd204b_sysref,
- jesd204b_sync_n_arr => i_jesd204b_sync_n_arr,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- rx_sosi_arr => jesd204b_rx_sosi_arr,
- rx_clk => jesd204b_rx_clk,
- rx_rst => jesd204b_rx_rst,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => jesd204b_serial_rx_arr
- );
+ generic map(
+ g_sim => c_sim,
+ g_nof_streams => c_nof_streams_jesd204b
+ )
+ port map(
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => i_jesd204b_sync_n_arr,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ rx_sosi_arr => jesd204b_rx_sosi_arr,
+ rx_clk => jesd204b_rx_clk,
+ rx_rst => jesd204b_rx_rst,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => jesd204b_serial_rx_arr
+ );
gen_streams: for stream in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
@@ -147,46 +147,46 @@ begin
dp_fifo_dc_rx_snk_in_arr(stream).valid <= dp_fifo_dc_rx_snk_out_arr(stream).ready and jesd204b_rx_sosi_arr(stream).valid;
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_data_w => 16,
- g_empty_w => 1,
- g_use_empty => false,
- g_use_ctrl => false,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_rst => jesd204b_rx_rst,
- wr_clk => jesd204b_rx_clk,
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => dp_fifo_dc_rx_snk_out_arr(stream),
- snk_in => dp_fifo_dc_rx_snk_in_arr(stream),
-
- src_in => dp_fifo_dc_rx_src_in_arr(stream),
- src_out => dp_fifo_dc_rx_src_out_arr(stream)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => 16,
+ g_empty_w => 1,
+ g_use_empty => false,
+ g_use_ctrl => false,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_rst => jesd204b_rx_rst,
+ wr_clk => jesd204b_rx_clk,
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => dp_fifo_dc_rx_snk_out_arr(stream),
+ snk_in => dp_fifo_dc_rx_snk_in_arr(stream),
+
+ src_in => dp_fifo_dc_rx_src_in_arr(stream),
+ src_out => dp_fifo_dc_rx_src_out_arr(stream)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_rx_src_out_arr(stream),
- snk_out => dp_fifo_dc_rx_src_in_arr(stream),
-
- src_out => dp_latency_adapter_rx_src_out_arr(stream),
- src_in => dp_latency_adapter_rx_src_in_arr(stream)
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_rx_src_out_arr(stream),
+ snk_out => dp_fifo_dc_rx_src_in_arr(stream),
+
+ src_out => dp_latency_adapter_rx_src_out_arr(stream),
+ src_in => dp_latency_adapter_rx_src_in_arr(stream)
+ );
----------------------------------------------------------------------------
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
index 13f12f6820..c464ced2e9 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
@@ -24,7 +24,7 @@
-- Purpose:
-- . Instantiates ta2_unb2b_10GbE component
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity ta2_unb2b_jesd204b_ip_wrapper is
port (
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
index cd59a76a88..4a5da38f4e 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
@@ -61,12 +61,12 @@
-- registers are rddata = wrdata.
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_mm_io is
generic (
@@ -148,7 +148,7 @@ begin
-----------------------------------------------------------------------------
-- dual clock FIFOs
-----------------------------------------------------------------------------
- u_dp_fifo_dc_wr : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_wr : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_wr_data_w,
@@ -172,7 +172,7 @@ begin
);
- u_dp_fifo_dc_rd : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_rd : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_rd_data_w,
@@ -195,69 +195,69 @@ begin
src_out => rd_sosi
);
-gen_no_opencl : if not g_use_opencl generate
- -- simulate an OpenCL kernel response (rl=0)
- p_is_reading : process(kernel_clk)
- begin
- if rising_edge(kernel_clk) then
- if cnt >= c_cnt_max then
- cnt <= 0;
- is_reading <= false;
- else
- cnt <= cnt + 1;
- end if;
- if in_sosi.valid = '1' then
- is_reading <= true;
- cnt <= 0;
+ gen_no_opencl : if not g_use_opencl generate
+ -- simulate an OpenCL kernel response (rl=0)
+ p_is_reading : process(kernel_clk)
+ begin
+ if rising_edge(kernel_clk) then
+ if cnt >= c_cnt_max then
+ cnt <= 0;
+ is_reading <= false;
+ else
+ cnt <= cnt + 1;
+ end if;
+ if in_sosi.valid = '1' then
+ is_reading <= true;
+ cnt <= 0;
+ end if;
end if;
- end if;
- end process;
+ end process;
- p_stim_st : process(out_sosi, in_siso, is_reading)
- begin
- in_sosi.valid <= '0';
- if out_sosi.valid = '1' then
- if out_sosi.data(64) = '1' then -- Write request
- if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
- reg_a <= out_sosi.data(31 downto 0);
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
- reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 1, 8) & out_sosi.data(23 downto 0); -- wrdata +1 to make distinguishable
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
- reg_c <= out_sosi.data(31 downto 0);
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
- reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0); -- wrdata +2 to make distinguishable
- end if;
- out_siso.ready <= '1';
- else -- read request
- if not is_reading then
- out_siso.ready <= '1';
- in_sosi.valid <= '1';
+ p_stim_st : process(out_sosi, in_siso, is_reading)
+ begin
+ in_sosi.valid <= '0';
+ if out_sosi.valid = '1' then
+ if out_sosi.data(64) = '1' then -- Write request
if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
- in_sosi.data(31 downto 0) <= reg_a;
+ reg_a <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
- in_sosi.data(31 downto 0) <= reg_b;
+ reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 1, 8) & out_sosi.data(23 downto 0); -- wrdata +1 to make distinguishable
elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
- in_sosi.data(31 downto 0) <= reg_c;
+ reg_c <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
- in_sosi.data(31 downto 0) <= reg_d;
- else
- in_sosi.data(31 downto 0) <= (others => '0');
+ reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0); -- wrdata +2 to make distinguishable
+ end if;
+ out_siso.ready <= '1';
+ else -- read request
+ if not is_reading then
+ out_siso.ready <= '1';
+ in_sosi.valid <= '1';
+ if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
+ in_sosi.data(31 downto 0) <= reg_a;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
+ in_sosi.data(31 downto 0) <= reg_b;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
+ in_sosi.data(31 downto 0) <= reg_c;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
+ in_sosi.data(31 downto 0) <= reg_d;
+ else
+ in_sosi.data(31 downto 0) <= (others => '0');
+ end if;
end if;
end if;
end if;
- end if;
- end process;
-
- src_out <= c_dp_sosi_rst;
- snk_out <= c_dp_siso_rdy;
-end generate;
-
-gen_opencl : if g_use_opencl generate
- src_out <= out_sosi;
- out_siso <= src_in;
- snk_out <= in_siso;
- in_sosi <= snk_in;
-end generate;
+ end process;
+
+ src_out <= c_dp_sosi_rst;
+ snk_out <= c_dp_siso_rdy;
+ end generate;
+
+ gen_opencl : if g_use_opencl generate
+ src_out <= out_sosi;
+ out_siso <= src_in;
+ snk_out <= in_siso;
+ in_sosi <= snk_in;
+ end generate;
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
index 17aa38a00b..0e9dd123ca 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
@@ -27,15 +27,15 @@
-- . Usage -> as 10; run -a
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_ta2_unb2b_mm_io is
end tb_ta2_unb2b_mm_io;
@@ -75,28 +75,28 @@ begin
end process;
u_dut : entity work.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => false
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => rst,
- mm_clk => clk,
-
- mm_mosi => mm_mosi,
- mm_miso => mm_miso,
-
- -- Streaming clock domain
- kernel_reset => rst,
- kernel_clk => clk,
-
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map(
+ g_use_opencl => false
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ mm_mosi => mm_mosi,
+ mm_miso => mm_miso,
+
+ -- Streaming clock domain
+ kernel_reset => rst,
+ kernel_clk => clk,
+
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
p_stim_mm : process
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
index c886d0d656..361f96d35f 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
@@ -27,16 +27,16 @@
-- the MM interface
library IEEE, common_lib, unb1_board_lib, dp_lib, i2c_lib, ppsh_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use i2c_lib.i2c_commander_aduh_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use i2c_lib.i2c_commander_aduh_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
entity node_unb1_bn_capture is
generic (
@@ -190,67 +190,67 @@ begin
-- . input from 4 signal paths A, B, C and D of 8b @ 800 MSps each
-- . output 4 signal streams via sp_sosi_arr with 4 samples per 32b data word
u_input: entity work.unb1_bn_capture_input
- generic map (
- g_sim => g_sim,
- g_bn_capture => g_bn_capture,
- g_use_phy => g_use_phy,
- g_nof_dp_phs_clk => g_nof_dp_phs_clk,
- g_ai => g_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK,
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
-
- -- . ADU_CD
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK,
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
-
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM wideband waveform generator ports [A, B, C, B]
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM DP shiftram
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
-
- -- MM signal path data monitors [A, B, C, B]
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- Streaming output (can be from ADU or from internal WG)
- sp_sosi_arr => i_sp_sosi_arr,
- sp_siso_arr => sp_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_bn_capture => g_bn_capture,
+ g_use_phy => g_use_phy,
+ g_nof_dp_phs_clk => g_nof_dp_phs_clk,
+ g_ai => g_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK,
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
+
+ -- . ADU_CD
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK,
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
+
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM wideband waveform generator ports [A, B, C, B]
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM DP shiftram
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+
+ -- MM signal path data monitors [A, B, C, B]
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- Streaming output (can be from ADU or from internal WG)
+ sp_sosi_arr => i_sp_sosi_arr,
+ sp_siso_arr => sp_siso_arr
+ );
------------------------------------------------------------------------------
@@ -258,62 +258,62 @@ begin
------------------------------------------------------------------------------
u_i2c_adu_ab : entity i2c_lib.i2c_commander
- generic map (
- g_sim => g_sim,
- g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
- g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
- g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
- g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
- g_use_result_ram => c_use_result_ram
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- sync => '1',
-
- -- Memory Mapped slave interfaces
- commander_mosi => reg_commander_mosi_arr(0),
- commander_miso => reg_commander_miso_arr(0),
- protocol_mosi => ram_protocol_mosi_arr(0),
- protocol_miso => ram_protocol_miso_arr(0),
- result_mosi => ram_result_mosi_arr(0),
- result_miso => ram_result_miso_arr(0),
-
- -- I2C interface
- scl => ADC_AB_SCL,
- sda => ADC_AB_SDA
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
+ g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
+ g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
+ g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
+ g_use_result_ram => c_use_result_ram
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ sync => '1',
+
+ -- Memory Mapped slave interfaces
+ commander_mosi => reg_commander_mosi_arr(0),
+ commander_miso => reg_commander_miso_arr(0),
+ protocol_mosi => ram_protocol_mosi_arr(0),
+ protocol_miso => ram_protocol_miso_arr(0),
+ result_mosi => ram_result_mosi_arr(0),
+ result_miso => ram_result_miso_arr(0),
+
+ -- I2C interface
+ scl => ADC_AB_SCL,
+ sda => ADC_AB_SDA
+ );
------------------------------------------------------------------------------
-- 2b) I2C control for ADU CD
------------------------------------------------------------------------------
u_i2c_adu_cd : entity i2c_lib.i2c_commander
- generic map (
- g_sim => g_sim,
- g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
- g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
- g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
- g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
- g_use_result_ram => c_use_result_ram
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- sync => '1',
-
- -- Memory Mapped slave interfaces
- commander_mosi => reg_commander_mosi_arr(1),
- commander_miso => reg_commander_miso_arr(1),
- protocol_mosi => ram_protocol_mosi_arr(1),
- protocol_miso => ram_protocol_miso_arr(1),
- result_mosi => ram_result_mosi_arr(1),
- result_miso => ram_result_miso_arr(1),
-
- -- I2C interface
- scl => ADC_CD_SCL,
- sda => ADC_CD_SDA
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
+ g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
+ g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
+ g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
+ g_use_result_ram => c_use_result_ram
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ sync => '1',
+
+ -- Memory Mapped slave interfaces
+ commander_mosi => reg_commander_mosi_arr(1),
+ commander_miso => reg_commander_miso_arr(1),
+ protocol_mosi => ram_protocol_mosi_arr(1),
+ protocol_miso => ram_protocol_miso_arr(1),
+ result_mosi => ram_result_mosi_arr(1),
+ result_miso => ram_result_miso_arr(1),
+
+ -- I2C interface
+ scl => ADC_CD_SCL,
+ sda => ADC_CD_SDA
+ );
------------------------------------------------------------------------------
-- 3) Feed each SP through a flusher that is controlled by a scheduler
@@ -321,80 +321,80 @@ begin
gen_flushers: for i in 0 to g_ai.nof_sp - 1 generate
u_dp_flush: entity dp_lib.dp_flush
- generic map (
- g_framed_xon => true,
- g_framed_xoff => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => i_sp_sosi_arr(i),
- snk_out => sp_siso_arr(i),
- -- ST source
- src_in => scheduled_sp_siso_arr(i),
- src_out => scheduled_sp_sosi_arr(i),
- -- Enable flush
- flush_en => sp_flush_en
- );
+ generic map (
+ g_framed_xon => true,
+ g_framed_xoff => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => i_sp_sosi_arr(i),
+ snk_out => sp_siso_arr(i),
+ -- ST source
+ src_in => scheduled_sp_siso_arr(i),
+ src_out => scheduled_sp_sosi_arr(i),
+ -- Enable flush
+ flush_en => sp_flush_en
+ );
end generate;
-- Convert the schedulers trigger on/off pulses to flush disable/enable level
u_sp_flush_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- switch_high => dp_bsn_trigger_sp_off,
- switch_low => dp_bsn_trigger_sp_on,
- out_level => sp_flush_en
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ switch_high => dp_bsn_trigger_sp_off,
+ switch_low => dp_bsn_trigger_sp_on,
+ out_level => sp_flush_en
+ );
u_bsn_trigger_sp_on : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_sp_on_mosi,
- reg_miso => reg_bsn_scheduler_sp_on_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
- trigger_out => dp_bsn_trigger_sp_on
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_sp_on_mosi,
+ reg_miso => reg_bsn_scheduler_sp_on_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
+ trigger_out => dp_bsn_trigger_sp_on
+ );
u_bsn_trigger_sp_off : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_sp_off_mosi,
- reg_miso => reg_bsn_scheduler_sp_off_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
- trigger_out => dp_bsn_trigger_sp_off
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_sp_off_mosi,
+ reg_miso => reg_bsn_scheduler_sp_off_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
+ trigger_out => dp_bsn_trigger_sp_off
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
index 0020141698..41d06966ee 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
@@ -22,18 +22,18 @@
-- Purpose: Capture ADC samples from ADU on a BN
library IEEE, common_lib, unb1_board_lib, dp_lib, ppsh_lib, eth_lib, tech_tse_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use work.unb1_bn_capture_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use work.unb1_bn_capture_pkg.all;
entity unb1_bn_capture is
generic (
@@ -197,550 +197,550 @@ begin
-----------------------------------------------------------------------------
u_sopc : entity work.sopc_unb1_bn_capture
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_source
- coe_clk_export_from_the_reg_bsn_source => OPEN,
- coe_reset_export_from_the_reg_bsn_source => OPEN,
- coe_address_export_from_the_reg_bsn_source => reg_bsn_source_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_source_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_bsn_source => reg_bsn_source_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_source => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_wg
- coe_clk_export_from_the_reg_bsn_scheduler_wg => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_wg => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0), -- reg_bsn_scheduler_adr_w = 1
- coe_read_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adc_quad
- coe_clk_export_from_the_reg_adc_quad => OPEN,
- coe_reset_export_from_the_reg_adc_quad => OPEN,
- coe_address_export_from_the_reg_adc_quad => reg_adc_quad_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_adc_quad_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adc_quad => reg_adc_quad_mosi.rd,
- coe_readdata_export_to_the_reg_adc_quad => reg_adc_quad_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wr,
- coe_writedata_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_0
- coe_clk_export_from_the_reg_diag_wg_0 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_0 => OPEN,
- coe_address_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_diag_wg_0 => reg_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_1
- coe_clk_export_from_the_reg_diag_wg_1 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_1 => OPEN,
- coe_address_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_diag_wg_1 => reg_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_2
- coe_clk_export_from_the_reg_diag_wg_2 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_2 => OPEN,
- coe_address_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).rd,
- coe_readdata_export_to_the_reg_diag_wg_2 => reg_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wr,
- coe_writedata_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_3
- coe_clk_export_from_the_reg_diag_wg_3 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_3 => OPEN,
- coe_address_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).rd,
- coe_readdata_export_to_the_reg_diag_wg_3 => reg_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wr,
- coe_writedata_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_0
- coe_clk_export_from_the_ram_diag_wg_0 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_0 => OPEN,
- coe_address_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_diag_wg_0 => ram_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_1
- coe_clk_export_from_the_ram_diag_wg_1 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_1 => OPEN,
- coe_address_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_diag_wg_1 => ram_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_2
- coe_clk_export_from_the_ram_diag_wg_2 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_2 => OPEN,
- coe_address_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).rd,
- coe_readdata_export_to_the_ram_diag_wg_2 => ram_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wr,
- coe_writedata_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_3
- coe_clk_export_from_the_ram_diag_wg_3 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_3 => OPEN,
- coe_address_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).rd,
- coe_readdata_export_to_the_ram_diag_wg_3 => ram_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wr,
- coe_writedata_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_shiftram
- coe_clk_export_from_the_reg_dp_shiftram => OPEN,
- coe_reset_export_from_the_reg_dp_shiftram => OPEN,
- coe_address_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.address(c_reg_dp_shiftram_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.rd,
- coe_readdata_export_to_the_reg_dp_shiftram => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wr,
- coe_writedata_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_0
- coe_clk_export_from_the_reg_aduh_mon_0 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_0 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_aduh_mon_0 => reg_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_1
- coe_clk_export_from_the_reg_aduh_mon_1 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_1 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_aduh_mon_1 => reg_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_2
- coe_clk_export_from_the_reg_aduh_mon_2 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_2 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).rd,
- coe_readdata_export_to_the_reg_aduh_mon_2 => reg_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wr,
- coe_writedata_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_3
- coe_clk_export_from_the_reg_aduh_mon_3 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_3 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).rd,
- coe_readdata_export_to_the_reg_aduh_mon_3 => reg_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wr,
- coe_writedata_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_0
- coe_clk_export_from_the_ram_aduh_mon_0 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_0 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_aduh_mon_0 => ram_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_1
- coe_clk_export_from_the_ram_aduh_mon_1 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_1 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_aduh_mon_1 => ram_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_2
- coe_clk_export_from_the_ram_aduh_mon_2 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_2 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).rd,
- coe_readdata_export_to_the_ram_aduh_mon_2 => ram_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wr,
- coe_writedata_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_3
- coe_clk_export_from_the_ram_aduh_mon_3 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_3 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).rd,
- coe_readdata_export_to_the_ram_aduh_mon_3 => ram_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wr,
- coe_writedata_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adu_i2c_commander_ab
- coe_clk_export_from_the_reg_adu_i2c_commander_ab => OPEN,
- coe_reset_export_from_the_reg_adu_i2c_commander_ab => OPEN,
- coe_address_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_adu_i2c_commander_ab => reg_commander_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adu_i2c_commander_cd
- coe_clk_export_from_the_reg_adu_i2c_commander_cd => OPEN,
- coe_reset_export_from_the_reg_adu_i2c_commander_cd => OPEN,
- coe_address_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_adu_i2c_commander_cd => reg_commander_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_protocol_ab
- coe_clk_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
- coe_address_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_adu_i2c_protocol_ab => ram_protocol_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_protocol_cd
- coe_clk_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
- coe_address_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_adu_i2c_protocol_cd => ram_protocol_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_result_ab
- coe_clk_export_from_the_ram_adu_i2c_result_ab => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_result_ab => OPEN,
- coe_address_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_adu_i2c_result_ab => ram_result_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_result_cd
- coe_clk_export_from_the_ram_adu_i2c_result_cd => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_result_cd => OPEN,
- coe_address_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_adu_i2c_result_cd => ram_result_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_sp_on
- coe_clk_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.address(0),
- coe_read_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_sp_off
- coe_clk_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.address(0),
- coe_read_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => mm_clk, -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_source
+ coe_clk_export_from_the_reg_bsn_source => OPEN,
+ coe_reset_export_from_the_reg_bsn_source => OPEN,
+ coe_address_export_from_the_reg_bsn_source => reg_bsn_source_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_source_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_bsn_source => reg_bsn_source_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_source => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_wg
+ coe_clk_export_from_the_reg_bsn_scheduler_wg => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_wg => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0), -- reg_bsn_scheduler_adr_w = 1
+ coe_read_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adc_quad
+ coe_clk_export_from_the_reg_adc_quad => OPEN,
+ coe_reset_export_from_the_reg_adc_quad => OPEN,
+ coe_address_export_from_the_reg_adc_quad => reg_adc_quad_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_adc_quad_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adc_quad => reg_adc_quad_mosi.rd,
+ coe_readdata_export_to_the_reg_adc_quad => reg_adc_quad_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wr,
+ coe_writedata_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_0
+ coe_clk_export_from_the_reg_diag_wg_0 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_0 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_diag_wg_0 => reg_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_1
+ coe_clk_export_from_the_reg_diag_wg_1 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_1 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_diag_wg_1 => reg_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_2
+ coe_clk_export_from_the_reg_diag_wg_2 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_2 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).rd,
+ coe_readdata_export_to_the_reg_diag_wg_2 => reg_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wr,
+ coe_writedata_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_3
+ coe_clk_export_from_the_reg_diag_wg_3 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_3 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).rd,
+ coe_readdata_export_to_the_reg_diag_wg_3 => reg_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wr,
+ coe_writedata_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_0
+ coe_clk_export_from_the_ram_diag_wg_0 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_0 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_diag_wg_0 => ram_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_1
+ coe_clk_export_from_the_ram_diag_wg_1 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_1 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_diag_wg_1 => ram_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_2
+ coe_clk_export_from_the_ram_diag_wg_2 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_2 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).rd,
+ coe_readdata_export_to_the_ram_diag_wg_2 => ram_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wr,
+ coe_writedata_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_3
+ coe_clk_export_from_the_ram_diag_wg_3 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_3 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).rd,
+ coe_readdata_export_to_the_ram_diag_wg_3 => ram_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wr,
+ coe_writedata_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_shiftram
+ coe_clk_export_from_the_reg_dp_shiftram => OPEN,
+ coe_reset_export_from_the_reg_dp_shiftram => OPEN,
+ coe_address_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.address(c_reg_dp_shiftram_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_shiftram => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_0
+ coe_clk_export_from_the_reg_aduh_mon_0 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_0 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_0 => reg_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_1
+ coe_clk_export_from_the_reg_aduh_mon_1 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_1 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_1 => reg_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_2
+ coe_clk_export_from_the_reg_aduh_mon_2 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_2 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_2 => reg_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_3
+ coe_clk_export_from_the_reg_aduh_mon_3 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_3 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_3 => reg_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_0
+ coe_clk_export_from_the_ram_aduh_mon_0 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_0 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_0 => ram_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_1
+ coe_clk_export_from_the_ram_aduh_mon_1 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_1 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_1 => ram_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_2
+ coe_clk_export_from_the_ram_aduh_mon_2 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_2 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_2 => ram_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_3
+ coe_clk_export_from_the_ram_aduh_mon_3 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_3 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_3 => ram_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adu_i2c_commander_ab
+ coe_clk_export_from_the_reg_adu_i2c_commander_ab => OPEN,
+ coe_reset_export_from_the_reg_adu_i2c_commander_ab => OPEN,
+ coe_address_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_adu_i2c_commander_ab => reg_commander_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adu_i2c_commander_cd
+ coe_clk_export_from_the_reg_adu_i2c_commander_cd => OPEN,
+ coe_reset_export_from_the_reg_adu_i2c_commander_cd => OPEN,
+ coe_address_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_adu_i2c_commander_cd => reg_commander_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_protocol_ab
+ coe_clk_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_protocol_ab => ram_protocol_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_protocol_cd
+ coe_clk_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_protocol_cd => ram_protocol_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_result_ab
+ coe_clk_export_from_the_ram_adu_i2c_result_ab => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_result_ab => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_result_ab => ram_result_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_result_cd
+ coe_clk_export_from_the_ram_adu_i2c_result_cd => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_result_cd => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_result_cd => ram_result_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_sp_on
+ coe_clk_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.address(0),
+ coe_read_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_sp_off
+ coe_clk_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.address(0),
+ coe_read_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
--- u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
--- GENERIC MAP (
--- -- General
--- g_sim => g_sim,
--- g_design_name => g_design_name,
--- g_fw_version => g_fw_version,
--- g_stamp_date => g_stamp_date,
--- g_stamp_time => g_stamp_time,
--- g_stamp_svn => g_stamp_svn,
--- g_design_note => g_design_note,
--- g_mm_clk_freq => g_bn_capture.mm_clk_freq, -- must match PLL setting in sopc_bn_capture
--- g_dp_clk_freq => g_bn_capture.dp_clk_freq,
--- g_dp_phs_clk_vec_w => g_nof_dp_phs_clk,
--- -- Use PHY Interface
--- g_use_phy => g_use_phy,
--- -- Auxiliary Interface
--- g_aux => g_aux
--- )
+ -- u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
+ -- GENERIC MAP (
+ -- -- General
+ -- g_sim => g_sim,
+ -- g_design_name => g_design_name,
+ -- g_fw_version => g_fw_version,
+ -- g_stamp_date => g_stamp_date,
+ -- g_stamp_time => g_stamp_time,
+ -- g_stamp_svn => g_stamp_svn,
+ -- g_design_note => g_design_note,
+ -- g_mm_clk_freq => g_bn_capture.mm_clk_freq, -- must match PLL setting in sopc_bn_capture
+ -- g_dp_clk_freq => g_bn_capture.dp_clk_freq,
+ -- g_dp_phs_clk_vec_w => g_nof_dp_phs_clk,
+ -- -- Use PHY Interface
+ -- g_use_phy => g_use_phy,
+ -- -- Auxiliary Interface
+ -- g_aux => g_aux
+ -- )
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_phs_clk_vec_w => c_nof_dp_phs_clk,
- g_dp_clk_use_pll => c_dp_clk_use_pll,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- System
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec, -- divided and phase shifted dp_clk
-
- this_chip_id => this_chip_id,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- ppsh
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_phs_clk_vec_w => c_nof_dp_phs_clk,
+ g_dp_clk_use_pll => c_dp_clk_use_pll,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- System
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec, -- divided and phase shifted dp_clk
+
+ this_chip_id => this_chip_id,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- ppsh
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Specific node function
-----------------------------------------------------------------------------
u_node : entity work.node_unb1_bn_capture
- generic map (
- -- General
- g_sim => g_sim,
- -- BN capture specific
- g_bn_capture => c_bn_capture,
- -- Use PHY Interface
- g_use_phy => c_use_phy,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux,
- -- ADC Interface
- g_nof_dp_phs_clk => c_nof_dp_phs_clk,
- g_ai => c_ai
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- ext_clk => CLK,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM DP shiftram
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
-
- -- MM signal path monitors for [A, B, C, D]
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- MM registers [0,1] for I2C access with ADUs [AB,CD]
- reg_commander_mosi_arr => reg_commander_mosi_arr,
- reg_commander_miso_arr => reg_commander_miso_arr,
- ram_protocol_mosi_arr => ram_protocol_mosi_arr,
- ram_protocol_miso_arr => ram_protocol_miso_arr,
- ram_result_mosi_arr => ram_result_mosi_arr,
- ram_result_miso_arr => ram_result_miso_arr,
-
- -- MM registers to enable and disable signal path
- reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
- reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
- reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
- reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
- --
- -- >>> Node FPGA pins
- --
- -- ADC Interface
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK,
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK,
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
- ADC_AB_SCL => ADC_AB_SCL, -- I2C AB
- ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL, -- I2C CD
- ADC_CD_SDA => ADC_CD_SDA
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ -- BN capture specific
+ g_bn_capture => c_bn_capture,
+ -- Use PHY Interface
+ g_use_phy => c_use_phy,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux,
+ -- ADC Interface
+ g_nof_dp_phs_clk => c_nof_dp_phs_clk,
+ g_ai => c_ai
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ ext_clk => CLK,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM DP shiftram
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+
+ -- MM signal path monitors for [A, B, C, D]
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- MM registers [0,1] for I2C access with ADUs [AB,CD]
+ reg_commander_mosi_arr => reg_commander_mosi_arr,
+ reg_commander_miso_arr => reg_commander_miso_arr,
+ ram_protocol_mosi_arr => ram_protocol_mosi_arr,
+ ram_protocol_miso_arr => ram_protocol_miso_arr,
+ ram_result_mosi_arr => ram_result_mosi_arr,
+ ram_result_miso_arr => ram_result_miso_arr,
+
+ -- MM registers to enable and disable signal path
+ reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
+ reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
+ reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
+ reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
+ --
+ -- >>> Node FPGA pins
+ --
+ -- ADC Interface
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK,
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK,
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
+ ADC_AB_SCL => ADC_AB_SCL, -- I2C AB
+ ADC_AB_SDA => ADC_AB_SDA,
+ ADC_CD_SCL => ADC_CD_SCL, -- I2C CD
+ ADC_CD_SDA => ADC_CD_SDA
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
index 922af3e858..9504de03c4 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -23,17 +23,17 @@
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, ppsh_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.unb1_bn_capture_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.unb1_bn_capture_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
entity unb1_bn_capture_input is
generic (
@@ -150,82 +150,82 @@ begin
use_adc : if g_use_phy.adc /= 0 generate
u_aduh_quad : entity aduh_lib.mms_aduh_quad
- generic map (
- -- General
- g_sim => g_sim,
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- -- ADC Interface
- g_nof_dp_phs_clk => g_nof_dp_phs_clk,
- g_ai => g_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK, -- lvds clock from ADU_AB
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST, -- release synchronises ADU_AB DCLK divider
-
- -- . ADU_CD
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK, -- lvds clock from ADU_CD
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST, -- release synchronises ADU_CD DCLK divider
-
- -- MM clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_adc_quad_mosi,
- reg_miso => reg_adc_quad_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
-
- -- . data
- aduh_sosi_arr => aduh_sosi_arr
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ -- ADC Interface
+ g_nof_dp_phs_clk => g_nof_dp_phs_clk,
+ g_ai => g_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK, -- lvds clock from ADU_AB
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST, -- release synchronises ADU_AB DCLK divider
+
+ -- . ADU_CD
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK, -- lvds clock from ADU_CD
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST, -- release synchronises ADU_CD DCLK divider
+
+ -- MM clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_adc_quad_mosi,
+ reg_miso => reg_adc_quad_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+
+ -- . data
+ aduh_sosi_arr => aduh_sosi_arr
+ );
end generate;
gen_wg : for I in 0 to g_ai.nof_sp - 1 generate
u_sp : entity diag_lib.mms_diag_wg_wideband
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => c_wideband_factor,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_wg_buf_dat_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi_arr(I),
- reg_miso => reg_wg_miso_arr(I),
-
- buf_mosi => ram_wg_mosi_arr(I),
- buf_miso => ram_wg_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
- st_restart => dp_bsn_trigger_wg,
-
- out_ovr => wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ),
- out_dat => wg_dat( (I + 1) * c_wideband_factor * c_wg_buf_dat_w - 1 downto I * c_wideband_factor * c_wg_buf_dat_w),
- out_val => wg_val( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ),
- out_sync => wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => c_wideband_factor,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_wg_buf_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_mosi_arr(I),
+ reg_miso => reg_wg_miso_arr(I),
+
+ buf_mosi => ram_wg_mosi_arr(I),
+ buf_miso => ram_wg_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_restart => dp_bsn_trigger_wg,
+
+ out_ovr => wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ),
+ out_dat => wg_dat( (I + 1) * c_wideband_factor * c_wg_buf_dat_w - 1 downto I * c_wideband_factor * c_wg_buf_dat_w),
+ out_val => wg_val( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ),
+ out_sync => wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )
+ );
-- wires
-- . all wideband samples will be valid in parallel, so using vector_or() or vector_and() is fine
@@ -234,7 +234,7 @@ begin
wg_sosi_arr(I).valid <= vector_or(wg_val( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
wg_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
wg_sosi_arr(I).err <= TO_DP_ERROR(c_unb1_board_ok) when
- vector_or(wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )) = '0' else
+ vector_or(wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )) = '0' else
TO_DP_ERROR(2**c_unb1_board_error_adc_bi); -- pass ADC or WG overflow info on as an error signal
end generate;
@@ -278,75 +278,75 @@ begin
-- is ensured by g_use_sync_in=TRUE and bs_sosi.sync.
-----------------------------------------------------------------------------
u_dp_shiftram : entity dp_lib.dp_shiftram
- generic map (
- g_nof_streams => g_ai.nof_sp, -- 4 signal paths
- g_nof_words => 2048,
- g_data_w => c_wideband_factor * g_ai.port_w, -- 4 concatenated timesamples
- g_use_sync_in => true
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_nof_streams => g_ai.nof_sp, -- 4 signal paths
+ g_nof_words => 2048,
+ g_data_w => c_wideband_factor * g_ai.port_w, -- 4 concatenated timesamples
+ g_use_sync_in => true
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sync_in => bs_sosi.sync,
+ sync_in => bs_sosi.sync,
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => func_dp_stream_arr_reverse_range(mux_sosi_arr),
+ snk_in_arr => func_dp_stream_arr_reverse_range(mux_sosi_arr),
- func_dp_stream_arr_reverse_range(src_out_arr) => dp_shiftram_src_out_arr
- );
+ func_dp_stream_arr_reverse_range(src_out_arr) => dp_shiftram_src_out_arr
+ );
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_sosi : entity dp_lib.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_block_size => c_bs_block_size,
+ g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_mosi,
+ reg_miso => reg_bsn_source_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => dp_bsn_trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => dp_bsn_trigger_wg
+ );
gen_sosi_ctrl : for I in 0 to g_ai.nof_sp - 1 generate
p_sosi : process(dp_shiftram_src_out_arr, bs_sosi)
@@ -371,17 +371,17 @@ begin
-----------------------------------------------------------------------------
gen_sp_siso_rdy : for I in 0 to g_ai.nof_sp - 1 generate
u_dp_ready : entity dp_lib.dp_ready
- generic map (
- g_ready_latency => 1
+ generic map (
+ g_ready_latency => 1
)
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in => dp_shiftram_src_out_timestamped_arr(I),
+ snk_in => dp_shiftram_src_out_timestamped_arr(I),
- src_out => sp_sosi_arr(I),
- src_in => sp_siso_arr(I)
+ src_out => sp_sosi_arr(I),
+ src_in => sp_siso_arr(I)
);
end generate;
@@ -390,43 +390,43 @@ begin
-----------------------------------------------------------------------------
gen_mon : for I in 0 to g_ai.nof_sp - 1 generate
u_sp : entity aduh_lib.mms_aduh_monitor
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_symbol_w => g_ai.port_w,
- g_nof_symbols_per_data => c_wideband_factor, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
- g_nof_accumulations => g_bn_capture.sp.nof_samples_per_sync, -- integration time in symbols, defines internal accumulator widths
- g_buffer_nof_symbols => g_bn_capture.sp.monitor_buffer_nof_samples,
- g_buffer_use_sync => g_bn_capture.sp.monitor_buffer_use_sync
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_symbol_w => g_ai.port_w,
+ g_nof_symbols_per_data => c_wideband_factor, -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+ g_nof_accumulations => g_bn_capture.sp.nof_samples_per_sync, -- integration time in symbols, defines internal accumulator widths
+ g_buffer_nof_symbols => g_bn_capture.sp.monitor_buffer_nof_samples,
+ g_buffer_use_sync => g_bn_capture.sp.monitor_buffer_use_sync
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_mon_mosi_arr(I), -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_mon_miso_arr(I),
- buf_mosi => ram_mon_mosi_arr(I), -- read and overwrite access to the signal path data buffers
- buf_miso => ram_mon_miso_arr(I),
+ reg_mosi => reg_mon_mosi_arr(I), -- read only access to the signal path data mean sum and power sum registers
+ reg_miso => reg_mon_miso_arr(I),
+ buf_mosi => ram_mon_mosi_arr(I), -- read and overwrite access to the signal path data buffers
+ buf_miso => ram_mon_miso_arr(I),
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- in_sosi => dp_shiftram_src_out_timestamped_arr(I)
- );
+ in_sosi => dp_shiftram_src_out_timestamped_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
-- Scope monitor for Wave Window
-----------------------------------------------------------------------------
u_quad_scope : entity aduh_lib.aduh_quad_scope
- generic map (
- g_sim => g_sim,
- g_ai => g_ai
- )
- port map (
- DCLK => dp_clk,
- sp_sosi_arr => dp_shiftram_src_out_timestamped_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_ai => g_ai
+ )
+ port map (
+ DCLK => dp_clk,
+ sp_sosi_arr => dp_shiftram_src_out_timestamped_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
index b8dd6fbcd4..711b6efc00 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
@@ -22,10 +22,10 @@
-- Purpose: Multiplex the 4 signal streams into 1 wide stream
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity bn_capture_mux is
generic (
@@ -43,11 +43,11 @@ entity bn_capture_mux is
-- ST sinks (input signal paths)
in_siso_arr : out t_dp_siso_arr(0 to g_nof_input - 1);
in_sosi_arr : in t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A[31:0], B[31:0], C[31:0], D[31:0]]
- -- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 8b samples in time per one 32b word
+ -- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 8b samples in time per one 32b word
-- ST source (multiplexed output signal paths)
mux_wide_siso : in t_dp_siso := c_dp_siso_rdy;
mux_wide_sosi : out t_dp_sosi -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
+ -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
);
end bn_capture_mux;
@@ -56,61 +56,61 @@ architecture str of bn_capture_mux is
signal wide_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal wide_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A,B,C,D]
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 800M samples in time per one 256b word
+-- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 800M samples in time per one 256b word
begin
gen_fifo : for I in 0 to g_nof_input - 1 generate
u_n2w : entity dp_lib.dp_fifo_dc_mixed_widths
+ generic map (
+ g_wr_data_w => g_in_data_w,
+ g_rd_data_w => g_mux_data_w,
+ g_use_ctrl => true,
+ g_wr_fifo_size => g_in_fifo_size,
+ g_rd_fifo_rl => 1
+ )
+ port map (
+ wr_rst => in_rst,
+ wr_clk => in_clk,
+ rd_rst => mux_wide_rst,
+ rd_clk => mux_wide_clk,
+ -- ST sink
+ snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
+ -- Monitor FIFO filling
+ wr_usedw => OPEN,
+ rd_usedw => OPEN,
+ rd_emp => OPEN,
+ -- ST source
+ src_in => wide_siso_arr(I),
+ src_out => wide_sosi_arr(I)
+ );
+ end generate;
+
+ gen_mux : entity dp_lib.dp_mux
generic map (
- g_wr_data_w => g_in_data_w,
- g_rd_data_w => g_mux_data_w,
- g_use_ctrl => true,
- g_wr_fifo_size => g_in_fifo_size,
- g_rd_fifo_rl => 1
+ g_data_w => g_mux_data_w,
+ g_empty_w => 1,
+ g_in_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_in_channel => false,
+ g_use_error => false,
+ g_mode => 1,
+ g_nof_input => g_nof_input,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_input), -- dummy value must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_input) -- dummy value must match g_nof_input
)
port map (
- wr_rst => in_rst,
- wr_clk => in_clk,
- rd_rst => mux_wide_rst,
- rd_clk => mux_wide_clk,
- -- ST sink
- snk_out => in_siso_arr(I),
- snk_in => in_sosi_arr(I),
- -- Monitor FIFO filling
- wr_usedw => OPEN,
- rd_usedw => OPEN,
- rd_emp => OPEN,
+ rst => mux_wide_rst,
+ clk => mux_wide_clk,
+ -- ST sinks
+ snk_out_arr => wide_siso_arr,
+ snk_in_arr => wide_sosi_arr,
-- ST source
- src_in => wide_siso_arr(I),
- src_out => wide_sosi_arr(I)
+ src_in => mux_wide_siso,
+ src_out => mux_wide_sosi
);
- end generate;
-
- gen_mux : entity dp_lib.dp_mux
- generic map (
- g_data_w => g_mux_data_w,
- g_empty_w => 1,
- g_in_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_in_channel => false,
- g_use_error => false,
- g_mode => 1,
- g_nof_input => g_nof_input,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_input), -- dummy value must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_input) -- dummy value must match g_nof_input
- )
- port map (
- rst => mux_wide_rst,
- clk => mux_wide_clk,
- -- ST sinks
- snk_out_arr => wide_siso_arr,
- snk_in_arr => wide_sosi_arr,
- -- ST source
- src_in => mux_wide_siso,
- src_out => mux_wide_sosi
- );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
index 1534c16a81..541532127f 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
package unb1_bn_capture_pkg is
@@ -47,9 +47,11 @@ package unb1_bn_capture_pkg is
sp : t_c_bn_capture_sp;
end record;
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M, -- must match PLL setting in sopc_bn_capture
- c_unb1_board_ext_clk_freq_200M,
- c_bn_capture_sp);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb1_board_mm_clk_freq_50M, -- must match PLL setting in sopc_bn_capture
+ c_unb1_board_ext_clk_freq_200M,
+ c_bn_capture_sp
+ );
end unb1_bn_capture_pkg;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
index 6c014a6fe2..23ba7fc600 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
@@ -22,12 +22,12 @@
-- Purpose: Store the 4 multiplexed signal streams into one DDR3 and readback
library IEEE, common_lib, unb_common_lib, dp_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity bn_capture_storage is
generic (
@@ -57,7 +57,7 @@ entity bn_capture_storage is
-- ST sink (multiplexed input signal paths)
mux_wide_siso : out t_dp_siso := c_dp_siso_rdy;
mux_wide_sosi : in t_dp_sosi; -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
+ -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
-- MM registers
ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
ctrl_miso : out t_mem_miso;
@@ -114,56 +114,56 @@ begin
phy_rst <= i_phy_rst;
u_ddr3 : entity ddr3_lib.ddr3
- generic map(
- g_sim => g_sim,
- g_phy => 0,
- g_ddr => g_ddr,
- g_mts => 800,
- g_wr_data_w => c_ddr3_ctlr_data_w,
- g_rd_data_w => c_word_w,
- g_wr_fifo_depth => c_wr_fifo_depth,
- g_rd_fifo_depth => c_rd_fifo_depth / 8,
- g_wr_use_ctrl => true
- )
- port map (
- ctlr_ref_clk => ext_clk,
- ctlr_rst => dp_rst,
-
- ctlr_gen_clk => i_phy_clk,
- ctlr_gen_rst => i_phy_rst,
- ctlr_gen_clk_2x => phy_clk_2x,
- ctlr_gen_rst_2x => phy_rst_2x,
-
- ctlr_init_done => ctlr_init_done,
- ctlr_rdy => ctlr_rdy,
-
- dvr_start_addr => dvr_start_addr,
- dvr_end_addr => dvr_end_addr,
-
- dvr_en => dvr_en,
- dvr_wr_not_rd => dvr_wr_not_rd,
- dvr_done => dvr_done,
- --dvr_flush => dvr_flush,
-
- wr_clk => dp_clk,
- wr_rst => dp_rst,
-
- wr_sosi => mux_wide_sosi,
- wr_siso => mux_wide_siso,
-
- -- ddr3 rd FIFO ST interface to the dp->mm adapter
- rd_sosi => rd_sosi,
- rd_siso => rd_siso,
-
- rd_clk => mm_clk,
- rd_rst => mm_rst,
-
- rd_fifo_usedw => rd_usedw,
-
- phy_in => ddr3_in,
- phy_io => ddr3_io,
- phy_ou => ddr3_ou
- );
+ generic map(
+ g_sim => g_sim,
+ g_phy => 0,
+ g_ddr => g_ddr,
+ g_mts => 800,
+ g_wr_data_w => c_ddr3_ctlr_data_w,
+ g_rd_data_w => c_word_w,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth / 8,
+ g_wr_use_ctrl => true
+ )
+ port map (
+ ctlr_ref_clk => ext_clk,
+ ctlr_rst => dp_rst,
+
+ ctlr_gen_clk => i_phy_clk,
+ ctlr_gen_rst => i_phy_rst,
+ ctlr_gen_clk_2x => phy_clk_2x,
+ ctlr_gen_rst_2x => phy_rst_2x,
+
+ ctlr_init_done => ctlr_init_done,
+ ctlr_rdy => ctlr_rdy,
+
+ dvr_start_addr => dvr_start_addr,
+ dvr_end_addr => dvr_end_addr,
+
+ dvr_en => dvr_en,
+ dvr_wr_not_rd => dvr_wr_not_rd,
+ dvr_done => dvr_done,
+ --dvr_flush => dvr_flush,
+
+ wr_clk => dp_clk,
+ wr_rst => dp_rst,
+
+ wr_sosi => mux_wide_sosi,
+ wr_siso => mux_wide_siso,
+
+ -- ddr3 rd FIFO ST interface to the dp->mm adapter
+ rd_sosi => rd_sosi,
+ rd_siso => rd_siso,
+
+ rd_clk => mm_clk,
+ rd_rst => mm_rst,
+
+ rd_fifo_usedw => rd_usedw,
+
+ phy_in => ddr3_in,
+ phy_io => ddr3_io,
+ phy_ou => ddr3_ou
+ );
-- Flush ddr3 module's FIFO (keep sinking the stream but simply discard the
-- data) after reset to prevent ddr3 write fifo from filling up - which would
@@ -205,22 +205,22 @@ begin
u_dp_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => c_rd_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- snk_out => rd_siso,
- snk_in => rd_sosi,
- usedw => rd_usedw, -- used words from rd FIFO
-
- mm_rd => mm_rd,
- mm_rddata => mm_rd_data,
- mm_rdval => mm_rd_val,
- mm_usedw => mm_rd_usedw -- resized to 32 bits
- );
+ generic map(
+ g_fifo_size => c_rd_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ usedw => rd_usedw, -- used words from rd FIFO
+
+ mm_rd => mm_rd,
+ mm_rddata => mm_rd_data,
+ mm_rdval => mm_rd_val,
+ mm_usedw => mm_rd_usedw -- resized to 32 bits
+ );
-- DDR3 streaming read output to mm bus
data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
@@ -228,30 +228,30 @@ begin
mm_rd <= data_mosi.rd;
u_storage_reg : entity work.bn_capture_storage_reg
- generic map(
- g_ddr => g_ddr
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => i_phy_rst,
- st_clk => i_phy_clk,
-
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
-
- st_en_evt => dvr_en,
- st_wr_not_rd => dvr_wr_not_rd,
-
- st_start_addr => dvr_start_addr,
- st_end_addr => dvr_end_addr,
-
- st_done => dvr_done,
- st_init_done => ctlr_init_done,
- st_ctlr_rdy => ctlr_rdy,
-
- mm_rd_usedw => mm_rd_usedw
- );
+ generic map(
+ g_ddr => g_ddr
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => i_phy_rst,
+ st_clk => i_phy_clk,
+
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
+
+ st_en_evt => dvr_en,
+ st_wr_not_rd => dvr_wr_not_rd,
+
+ st_start_addr => dvr_start_addr,
+ st_end_addr => dvr_end_addr,
+
+ st_done => dvr_done,
+ st_init_done => ctlr_init_done,
+ st_ctlr_rdy => ctlr_rdy,
+
+ mm_rd_usedw => mm_rd_usedw
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
index 756ce1b7f7..982adfdbdd 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity bn_capture_storage_reg is
generic (
g_ddr : t_c_ddr3_phy
- );
+ );
port (
-- Clocks and reset
mm_rst : in std_logic; -- reset synchronous with mm_clk
@@ -53,17 +53,19 @@ entity bn_capture_storage_reg is
-- MM registers
mm_rd_usedw : in std_logic_vector(31 downto 0)
- );
+ );
end bn_capture_storage_reg;
architecture rtl of bn_capture_storage_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 8,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(8),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 8,
+ init_sl => '0'
+ );
-- Registers in mm_clk domain
signal mm_en_evt : std_logic;
signal mm_wr_not_rd : std_logic;
@@ -158,59 +160,59 @@ begin
------------------------------------------------------------------------------
u_spulse_en_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_en_evt,
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => st_en_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_en_evt,
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => st_en_evt
+ );
u_async_wr_not_rd : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- din => mm_wr_not_rd,
- dout => st_wr_not_rd
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ din => mm_wr_not_rd,
+ dout => st_wr_not_rd
+ );
u_async_done : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_done,
- dout => mm_done
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_done,
+ dout => mm_done
+ );
u_async_init_done : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_init_done,
- dout => mm_init_done
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_init_done,
+ dout => mm_init_done
+ );
u_async_rdy : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_ctlr_rdy,
- dout => mm_ctlr_rdy
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_ctlr_rdy,
+ dout => mm_ctlr_rdy
+ );
-- Address range should be set before asserting the DDR3 enable bit.
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
index 87e60073de..a1346b7655 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
@@ -41,22 +41,22 @@
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, aduh_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use i2c_lib.i2c_commander_pkg.all;
-use i2c_lib.i2c_commander_aduh_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use i2c_lib.i2c_commander_pkg.all;
+ use i2c_lib.i2c_commander_aduh_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity tb_node_unb1_bn_capture is
generic (
@@ -84,9 +84,11 @@ architecture tb of tb_node_unb1_bn_capture is
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true); -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M,
- c_unb1_board_ext_clk_freq_200M,
- c_bn_capture_sp_sim);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb1_board_mm_clk_freq_50M,
+ c_unb1_board_ext_clk_freq_200M,
+ c_bn_capture_sp_sim
+ );
constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
@@ -309,7 +311,7 @@ begin
proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi); -- first write low then high part
proc_mem_mm_bus_wr(1, 0, mm_clk, reg_bsn_scheduler_wg_mosi); -- assume v_bsn < 2**31-1
- -- Continue forever with WG data
+ -- Continue forever with WG data
end if;
proc_common_wait_some_cycles(mm_clk, 1000);
reg_input_stimuli_done <= '1';
@@ -389,134 +391,134 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => c_sim,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_bn_capture.mm_clk_freq,
- g_dp_clk_freq => c_bn_capture.dp_clk_freq,
- g_use_phy => g_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- System
- -- Clock an reset signals
- -- System
- cs_sim => OPEN,
- xo_clk => OPEN,
- xo_rst_n => OPEN,
-
- mm_clk => mm_clk, -- 50 MHz
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- 200 MHz from CLK system clock
- dp_pps => dp_pps, -- PPS in dp_clk domain
- dp_rst_in => dp_rst, -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in => dp_clk, -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk (due to dp_clk <= i_dp_clk assignment)
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- eth1g
- eth1g_tse_clk => '0',
- eth1g_mm_rst => '1',
- eth1g_tse_mosi => c_mem_mosi_rst,
- eth1g_tse_miso => OPEN,
- eth1g_reg_mosi => c_mem_mosi_rst,
- eth1g_reg_miso => OPEN,
- eth1g_reg_interrupt => OPEN,
- eth1g_ram_mosi => c_mem_mosi_rst,
- eth1g_ram_miso => OPEN,
-
- -- FPGA pins
- -- . General
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp
- );
+ generic map (
+ g_sim => c_sim,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_bn_capture.mm_clk_freq,
+ g_dp_clk_freq => c_bn_capture.dp_clk_freq,
+ g_use_phy => g_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- System
+ -- Clock an reset signals
+ -- System
+ cs_sim => OPEN,
+ xo_clk => OPEN,
+ xo_rst_n => OPEN,
+
+ mm_clk => mm_clk, -- 50 MHz
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- 200 MHz from CLK system clock
+ dp_pps => dp_pps, -- PPS in dp_clk domain
+ dp_rst_in => dp_rst, -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_clk_in => dp_clk, -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk (due to dp_clk <= i_dp_clk assignment)
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- eth1g
+ eth1g_tse_clk => '0',
+ eth1g_mm_rst => '1',
+ eth1g_tse_mosi => c_mem_mosi_rst,
+ eth1g_tse_miso => OPEN,
+ eth1g_reg_mosi => c_mem_mosi_rst,
+ eth1g_reg_miso => OPEN,
+ eth1g_reg_interrupt => OPEN,
+ eth1g_ram_mosi => c_mem_mosi_rst,
+ eth1g_ram_miso => OPEN,
+
+ -- FPGA pins
+ -- . General
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp
+ );
u_node : entity work.node_unb1_bn_capture
- generic map (
- -- General
- g_sim => c_sim,
- -- BN capture specific
- g_bn_capture => c_bn_capture,
- -- Use PHY Interface
- g_use_phy => g_use_phy,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux,
- -- ADC Interface
- g_ai => c_ai
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
-
- ext_clk => ext_clk,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM registers [0,1,2,3] for wideband waveform generators [A,B,C,D]
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM registers [0,1] for I2C access with ADU AB and with ADU CD
- reg_commander_mosi_arr => reg_commander_mosi_arr,
- reg_commander_miso_arr => reg_commander_miso_arr,
- ram_protocol_mosi_arr => ram_protocol_mosi_arr,
- ram_protocol_miso_arr => ram_protocol_miso_arr,
- ram_result_mosi_arr => ram_result_mosi_arr,
- ram_result_miso_arr => ram_result_miso_arr,
-
- -- MM registers to enable and disable signal path
- reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
- reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
- reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
- reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
-
- -- ADC Interface
- ADC_BI_A => DIG_A,
- ADC_BI_B => DIG_B,
- ADC_BI_A_CLK => DCLK_AB,
- ADC_BI_A_CLK_RST => DCLK_RST_AB,
- ADC_BI_C => DIG_C,
- ADC_BI_D => DIG_D,
- ADC_BI_D_CLK => DCLK_CD,
- ADC_BI_D_CLK_RST => DCLK_RST_CD,
-
- ADC_AB_SCL => ADC_AB_SCL,
- ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL,
- ADC_CD_SDA => ADC_CD_SDA
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ -- BN capture specific
+ g_bn_capture => c_bn_capture,
+ -- Use PHY Interface
+ g_use_phy => g_use_phy,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux,
+ -- ADC Interface
+ g_ai => c_ai
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+
+ ext_clk => ext_clk,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM registers [0,1,2,3] for wideband waveform generators [A,B,C,D]
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM registers [0,1] for I2C access with ADU AB and with ADU CD
+ reg_commander_mosi_arr => reg_commander_mosi_arr,
+ reg_commander_miso_arr => reg_commander_miso_arr,
+ ram_protocol_mosi_arr => ram_protocol_mosi_arr,
+ ram_protocol_miso_arr => ram_protocol_miso_arr,
+ ram_result_mosi_arr => ram_result_mosi_arr,
+ ram_result_miso_arr => ram_result_miso_arr,
+
+ -- MM registers to enable and disable signal path
+ reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
+ reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
+ reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
+ reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
+
+ -- ADC Interface
+ ADC_BI_A => DIG_A,
+ ADC_BI_B => DIG_B,
+ ADC_BI_A_CLK => DCLK_AB,
+ ADC_BI_A_CLK_RST => DCLK_RST_AB,
+ ADC_BI_C => DIG_C,
+ ADC_BI_D => DIG_D,
+ ADC_BI_D_CLK => DCLK_CD,
+ ADC_BI_D_CLK_RST => DCLK_RST_CD,
+
+ ADC_AB_SCL => ADC_AB_SCL,
+ ADC_AB_SDA => ADC_AB_SDA,
+ ADC_CD_SCL => ADC_CD_SCL,
+ ADC_CD_SDA => ADC_CD_SDA
+ );
-----------------------------------------------------------------------------
@@ -536,36 +538,36 @@ begin
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_A),
- AQ => TO_SINT(ANA_B),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_AB,
- DCLK_RST => DCLK_RST_AB,
- DI => DIG_A,
- DQ => DIG_B,
- OVR => DIG_OVR_AB,
- SCL => ADC_AB_SCL,
- SDA => ADC_AB_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_A),
+ AQ => TO_SINT(ANA_B),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_AB,
+ DCLK_RST => DCLK_RST_AB,
+ DI => DIG_A,
+ DQ => DIG_B,
+ OVR => DIG_OVR_AB,
+ SCL => ADC_AB_SCL,
+ SDA => ADC_AB_SDA,
+ test_pattern_en => test_pattern_en
+ );
u_adc_CD : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_C),
- AQ => TO_SINT(ANA_D),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_CD,
- DCLK_RST => DCLK_RST_CD,
- DI => DIG_C,
- DQ => DIG_D,
- OVR => DIG_OVR_CD,
- SCL => ADC_CD_SCL,
- SDA => ADC_CD_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_C),
+ AQ => TO_SINT(ANA_D),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_CD,
+ DCLK_RST => DCLK_RST_CD,
+ DI => DIG_C,
+ DQ => DIG_D,
+ OVR => DIG_OVR_CD,
+ SCL => ADC_CD_SCL,
+ SDA => ADC_CD_SDA,
+ test_pattern_en => test_pattern_en
+ );
------------------------------------------------------------------------------
-- 1GbE Loopback model
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
index 2c11bf9501..5bc0f5c08c 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
@@ -36,20 +36,20 @@
library IEEE, common_lib, dp_lib, i2c_lib, unb1_board_lib, diag_lib, aduh_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
-use i2c_lib.i2c_dev_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
+ use i2c_lib.i2c_dev_unb_pkg.all;
entity tb_bn_capture is
@@ -77,9 +77,11 @@ architecture tb of tb_bn_capture is
constant c_fw_version : t_unb_fw_version := (1, 0);
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 1024 * 1024, 1024, true); -- 800 MSps, block size 1024 samples, nof blocks per sync interval, monitor buffer nof samples using sync
- constant c_bn_capture : t_c_bn_capture := (c_unb_mm_clk_freq_50M,
- c_unb_ext_clk_freq_200M,
- c_bn_capture_sp_sim);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb_mm_clk_freq_50M,
+ c_unb_ext_clk_freq_200M,
+ c_bn_capture_sp_sim
+ );
constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g; -- use c_ddr3_phy_4g or c_ddr3_phy_1g dependent on what was generated with the MegaWizard
@@ -176,14 +178,14 @@ begin
sens_sda <= 'H'; -- pull up
u_sens_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_max1618_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_max1618_temp
- );
+ generic map (
+ g_address => c_max1618_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_max1618_temp
+ );
VERSION <= c_version;
ID <= c_id_bn0;
@@ -193,69 +195,69 @@ begin
------------------------------------------------------------------------------
dut : entity work.bn_capture
- generic map (
- -- General
- g_sim => c_sim,
- g_fw_version => c_fw_version,
- -- BN capture specific
- g_bn_capture => c_bn_capture,
- -- Use PHY Interface
- g_use_phy => g_use_phy,
- -- Auxiliary Interface
- g_aux => c_unb_aux,
- -- DDR3 Interface
- g_ddr => c_ddr,
- -- ADC Interface
- g_nof_dp_phs_clk => c_nof_dp_phs_clk,
- g_ai => c_ai
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_IN => MB_I_in,
- MB_I_IO => MB_I_io,
- MB_I_OU => MB_I_ou,
-
- -- SO-DIMM Memory Bank II = ddr3_II
- MB_II_IN => MB_II_in,
- MB_II_IO => MB_II_io,
- MB_II_OU => MB_II_ou,
-
- -- ADC Interface
- ADC_BI_A => DIG_A,
- ADC_BI_B => DIG_B,
- ADC_BI_A_CLK => DCLK_AB,
- ADC_BI_A_CLK_RST => DCLK_RST_AB,
- ADC_BI_C => DIG_C,
- ADC_BI_D => DIG_D,
- ADC_BI_D_CLK => DCLK_CD,
- ADC_BI_D_CLK_RST => DCLK_RST_CD,
-
- ADC_AB_SCL => ADC_AB_SCL,
- ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL,
- ADC_CD_SDA => ADC_CD_SDA
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_fw_version => c_fw_version,
+ -- BN capture specific
+ g_bn_capture => c_bn_capture,
+ -- Use PHY Interface
+ g_use_phy => g_use_phy,
+ -- Auxiliary Interface
+ g_aux => c_unb_aux,
+ -- DDR3 Interface
+ g_ddr => c_ddr,
+ -- ADC Interface
+ g_nof_dp_phs_clk => c_nof_dp_phs_clk,
+ g_ai => c_ai
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_IN => MB_I_in,
+ MB_I_IO => MB_I_io,
+ MB_I_OU => MB_I_ou,
+
+ -- SO-DIMM Memory Bank II = ddr3_II
+ MB_II_IN => MB_II_in,
+ MB_II_IO => MB_II_io,
+ MB_II_OU => MB_II_ou,
+
+ -- ADC Interface
+ ADC_BI_A => DIG_A,
+ ADC_BI_B => DIG_B,
+ ADC_BI_A_CLK => DCLK_AB,
+ ADC_BI_A_CLK_RST => DCLK_RST_AB,
+ ADC_BI_C => DIG_C,
+ ADC_BI_D => DIG_D,
+ ADC_BI_D_CLK => DCLK_CD,
+ ADC_BI_D_CLK_RST => DCLK_RST_CD,
+
+ ADC_AB_SCL => ADC_AB_SCL,
+ ADC_AB_SDA => ADC_AB_SDA,
+ ADC_CD_SCL => ADC_CD_SCL,
+ ADC_CD_SDA => ADC_CD_SDA
+ );
-----------------------------------------------------------------------------
@@ -278,36 +280,36 @@ begin
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_A),
- AQ => TO_SINT(ANA_B),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_AB,
- DCLK_RST => DCLK_RST_AB,
- DI => DIG_A,
- DQ => DIG_B,
- OVR => DIG_OVR_AB,
- SCL => ADC_AB_SCL,
- SDA => ADC_AB_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_A),
+ AQ => TO_SINT(ANA_B),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_AB,
+ DCLK_RST => DCLK_RST_AB,
+ DI => DIG_A,
+ DQ => DIG_B,
+ OVR => DIG_OVR_AB,
+ SCL => ADC_AB_SCL,
+ SDA => ADC_AB_SDA,
+ test_pattern_en => test_pattern_en
+ );
u_adc_CD : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_C),
- AQ => TO_SINT(ANA_D),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_CD,
- DCLK_RST => DCLK_RST_CD,
- DI => DIG_C,
- DQ => DIG_D,
- OVR => DIG_OVR_CD,
- SCL => ADC_CD_SCL,
- SDA => ADC_CD_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_C),
+ AQ => TO_SINT(ANA_D),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_CD,
+ DCLK_RST => DCLK_RST_CD,
+ DI => DIG_C,
+ DQ => DIG_D,
+ OVR => DIG_OVR_CD,
+ SCL => ADC_CD_SCL,
+ SDA => ADC_CD_SDA,
+ test_pattern_en => test_pattern_en
+ );
------------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
index a2a8d46e47..bf5d27c553 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
@@ -49,19 +49,19 @@
-- that the tb has run.
library IEEE, common_lib, dp_lib, diag_lib, aduh_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity tb_unb1_bn_capture_input is
end tb_unb1_bn_capture_input;
@@ -71,9 +71,11 @@ architecture tb of tb_unb1_bn_capture_input is
constant c_sim : boolean := true;
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true); -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M,
- c_unb1_board_ext_clk_freq_200M,
- c_bn_capture_sp_sim);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb1_board_mm_clk_freq_50M,
+ c_unb1_board_ext_clk_freq_200M,
+ c_bn_capture_sp_sim
+ );
constant c_ram_wg_dat_w : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
constant c_ram_wg_size : natural := 2**c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
@@ -462,7 +464,7 @@ begin
-- Read ADUH monitor buffer at BSN
for K in 0 to c_bsn_schedule_nof_events - 1 loop
while unsigned(current_bsn) < c_bsn_schedule_aduh_monitor + K * c_nof_block_per_sync loop
- proc_common_wait_some_cycles(mm_clk, 1);
+ proc_common_wait_some_cycles(mm_clk, 1);
end loop;
-- Read the RAM waveform buffer for all 4 wideband waveform generators
@@ -520,95 +522,95 @@ begin
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_A),
- AQ => TO_SINT(ANA_B),
- CLK => SCLK,
- DCLK => DCLK_AB,
- DCLK_RST => DCLK_RST_AB,
- DI => DIG_A,
- DQ => DIG_B,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_A),
+ AQ => TO_SINT(ANA_B),
+ CLK => SCLK,
+ DCLK => DCLK_AB,
+ DCLK_RST => DCLK_RST_AB,
+ DI => DIG_A,
+ DQ => DIG_B,
+ test_pattern_en => test_pattern_en
+ );
u_adc_CD : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_C),
- AQ => TO_SINT(ANA_D),
- CLK => SCLK,
- DCLK => DCLK_CD,
- DCLK_RST => DCLK_RST_CD,
- DI => DIG_C,
- DQ => DIG_D,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_C),
+ AQ => TO_SINT(ANA_D),
+ CLK => SCLK,
+ DCLK => DCLK_CD,
+ DCLK_RST => DCLK_RST_CD,
+ DI => DIG_C,
+ DQ => DIG_D,
+ test_pattern_en => test_pattern_en
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
dut : entity work.unb1_bn_capture_input
- generic map (
- g_sim => c_sim,
- g_bn_capture => c_bn_capture,
- g_nof_dp_phs_clk => dp_phs_clk_vec'LENGTH,
- g_ai => c_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => DIG_A,
- ADC_BI_B => DIG_B,
- ADC_BI_A_CLK => DCLK_AB,
- ADC_BI_A_CLK_RST => DCLK_RST_AB,
-
- -- . ADU_CD
- ADC_BI_C => DIG_C,
- ADC_BI_D => DIG_D,
- ADC_BI_D_CLK => DCLK_CD,
- ADC_BI_D_CLK_RST => DCLK_RST_CD,
-
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM waveform generators
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM signal path monitors
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- Streaming output (can be from ADU or from internal WG)
- sp_sosi_arr => sp_sosi_arr,
- sp_siso_arr => sp_siso_arr
- );
-
- ------------------------------------------------------------------------------
- -- Verify
- ------------------------------------------------------------------------------
-
- -- View sp_sosi_arr in Wave Window with aduh_quad_scope in unb1_bn_capture_input
+ generic map (
+ g_sim => c_sim,
+ g_bn_capture => c_bn_capture,
+ g_nof_dp_phs_clk => dp_phs_clk_vec'LENGTH,
+ g_ai => c_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => DIG_A,
+ ADC_BI_B => DIG_B,
+ ADC_BI_A_CLK => DCLK_AB,
+ ADC_BI_A_CLK_RST => DCLK_RST_AB,
+
+ -- . ADU_CD
+ ADC_BI_C => DIG_C,
+ ADC_BI_D => DIG_D,
+ ADC_BI_D_CLK => DCLK_CD,
+ ADC_BI_D_CLK_RST => DCLK_RST_CD,
+
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM waveform generators
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM signal path monitors
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- Streaming output (can be from ADU or from internal WG)
+ sp_sosi_arr => sp_sosi_arr,
+ sp_siso_arr => sp_siso_arr
+ );
+
+------------------------------------------------------------------------------
+-- Verify
+------------------------------------------------------------------------------
+
+-- View sp_sosi_arr in Wave Window with aduh_quad_scope in unb1_bn_capture_input
end tb;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
index 6835c5e073..ad9600822b 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity node_unb1_bn_terminal_bg is
generic(
@@ -136,28 +136,28 @@ begin
-----------------------------------------------------------------------------
gen_bg : if g_use_bg = true generate
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_usr_nof_streams,
- g_buf_dat_w => g_usr_data_w,
- g_buf_addr_w => ceil_log2(g_usr_block_len),
- g_file_name_prefix => "UNUSED"
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_usr_nof_streams,
+ g_buf_dat_w => g_usr_data_w,
+ g_buf_addr_w => ceil_log2(g_usr_block_len),
+ g_file_name_prefix => "UNUSED"
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
end generate;
no_bg : if g_use_bg = false generate
@@ -194,55 +194,55 @@ begin
back_tx_usr_sosi_2arr <= bg_sosi_2arr;
u_terminals_back: entity unb1_board_lib.unb1_board_terminals_back
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_nof_bus => c_unb1_board_nof_uniboard, -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_mesh_usr_nof_input,
- -- Phy
- g_phy_nof_serial => g_back_nof_serial,
- g_phy_gx_mbps => g_back_gx_mbps,
- g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
- -- Tx
- g_tx_input_use_fifo => true,
- -- Rx
- g_rx_output_use_fifo => false, -- no need for Rx output FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_timeout_w => c_rx_timeout_w
- )
- port map (
- bck_id => bck_id,
-
- tr_clk => tr_back_clk,
- cal_clk => cal_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- User I/O side (4 uniboards)(4 i/o streams)
- tx_usr_siso_2arr => back_tx_usr_siso_2arr,
- tx_usr_sosi_2arr => back_tx_usr_sosi_2arr,
- rx_usr_siso_2arr => back_rx_usr_siso_2arr,
- rx_usr_sosi_2arr => back_rx_usr_sosi_2arr,
-
- -- Serial (tr_nonbonded)
- tx_serial_2arr => back_tx_serial_2arr, -- Tx
- rx_serial_2arr => back_rx_serial_2arr, -- Rx
-
- -- MM Control
- reg_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
-
- reg_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_diagnostics_miso => reg_back_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_nof_bus => c_unb1_board_nof_uniboard, -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_mesh_usr_nof_input,
+ -- Phy
+ g_phy_nof_serial => g_back_nof_serial,
+ g_phy_gx_mbps => g_back_gx_mbps,
+ g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
+ -- Tx
+ g_tx_input_use_fifo => true,
+ -- Rx
+ g_rx_output_use_fifo => false, -- no need for Rx output FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_timeout_w => c_rx_timeout_w
+ )
+ port map (
+ bck_id => bck_id,
+
+ tr_clk => tr_back_clk,
+ cal_clk => cal_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- User I/O side (4 uniboards)(4 i/o streams)
+ tx_usr_siso_2arr => back_tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => back_tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => back_rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => back_rx_usr_sosi_2arr,
+
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr => back_tx_serial_2arr, -- Tx
+ rx_serial_2arr => back_rx_serial_2arr, -- Rx
+
+ -- MM Control
+ reg_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+
+ reg_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_diagnostics_miso => reg_back_diagnostics_miso
+ );
-----------------------------------------------------------------------------
-- Back terminals -> transpose -> mesh terminals
@@ -258,63 +258,63 @@ begin
gen_mesh: if g_use_mesh = true generate
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_bn,
- g_nof_bus => c_unb1_board_nof_fn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_mesh_usr_nof_input,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => true, -- user Tx must be TRUE for BG in BN,
- g_tx_input_use_fifo => true, -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- -- Rx
- g_use_rx => g_mesh_use_rx, -- optionally do support diag Rx
- g_rx_output_use_fifo => false, -- no user Rx
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => mesh_tx_usr_siso_2arr,
- tx_usr_sosi_2arr => mesh_tx_usr_sosi_2arr, -- Tx (user Rx from FN to BN is unused)
-
- -- Serial mesh interface (tr_nonbonded)
- tx_serial_2arr => mesh_tx_serial_2arr, -- Tx
- rx_serial_2arr => mesh_rx_serial_2arr, -- Rx
-
- -- MM Control
- reg_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
-
- reg_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_bn,
+ g_nof_bus => c_unb1_board_nof_fn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_mesh_usr_nof_input,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => true, -- user Tx must be TRUE for BG in BN,
+ g_tx_input_use_fifo => true, -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ -- Rx
+ g_use_rx => g_mesh_use_rx, -- optionally do support diag Rx
+ g_rx_output_use_fifo => false, -- no user Rx
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => mesh_tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => mesh_tx_usr_sosi_2arr, -- Tx (user Rx from FN to BN is unused)
+
+ -- Serial mesh interface (tr_nonbonded)
+ tx_serial_2arr => mesh_tx_serial_2arr, -- Tx
+ rx_serial_2arr => mesh_rx_serial_2arr, -- Rx
+
+ -- MM Control
+ reg_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+
+ reg_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
end generate;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
index 295d507e43..d3dc4e71ba 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb1_bn_terminal_bg is
generic (
@@ -40,7 +40,7 @@ entity unb1_bn_terminal_bg is
g_stamp_svn : natural := 0 -- SVN revision
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -88,17 +88,17 @@ end unb1_bn_terminal_bg;
architecture str of unb1_bn_terminal_bg is
constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
- -- Use PHY Interface
- -- TYPE t_c_unb_use_phy IS RECORD
- -- eth1g : NATURAL;
- -- tr_front: NATURAL;
- -- tr_mesh : NATURAL;
- -- tr_back : NATURAL;
- -- ddr3_I : NATURAL;
- -- ddr3_II : NATURAL;
- -- adc : NATURAL;
- -- wdi : NATURAL;
- -- END RECORD;
+ -- Use PHY Interface
+ -- TYPE t_c_unb_use_phy IS RECORD
+ -- eth1g : NATURAL;
+ -- tr_front: NATURAL;
+ -- tr_mesh : NATURAL;
+ -- tr_back : NATURAL;
+ -- ddr3_I : NATURAL;
+ -- ddr3_II : NATURAL;
+ -- adc : NATURAL;
+ -- wdi : NATURAL;
+ -- END RECORD;
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 1, 0, 0, 0, 1);
-- Transceivers Interface
constant c_tr_mesh : t_c_unb1_board_tr := c_unb1_board_tr_mesh;
@@ -149,7 +149,7 @@ architecture str of unb1_bn_terminal_bg is
signal rom_unb_system_info_mosi : t_mem_mosi;
signal rom_unb_system_info_miso : t_mem_miso;
- -- WDI override
+ -- WDI override
signal reg_wdi_mosi : t_mem_mosi;
signal reg_wdi_miso : t_mem_miso;
@@ -209,232 +209,232 @@ begin
-----------------------------------------------------------------------------
u_sopc : entity work.sopc_unb1_bn_terminal_bg
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_mesh
- coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_mesh
- coe_address_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_read_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_mesh => reg_mesh_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_write_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_back
- coe_address_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_back => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_back => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_back
- coe_address_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_back => OPEN,
- coe_read_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_back => reg_back_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_back => OPEN,
- coe_write_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- in_port_to_the_pio_pps => pin_pps,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_mesh
+ coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_mesh
+ coe_address_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_read_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_mesh => reg_mesh_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_write_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_back
+ coe_address_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_back => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_back => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_back
+ coe_address_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_back => OPEN,
+ coe_read_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_back => reg_back_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_back => OPEN,
+ coe_write_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ in_port_to_the_pio_pps => pin_pps,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
@@ -443,72 +443,72 @@ begin
-----------------------------------------------------------------------------
u_node_bn_terminal_bg : entity work.node_unb1_bn_terminal_bg
- generic map(
- g_sim => g_sim,
- -- Application interface
- g_use_bg => true,
- g_usr_nof_streams => c_usr_nof_streams,
- g_usr_block_len => c_usr_block_len,
- -- Terminals interface
- g_use_mesh => c_use_mesh,
- g_use_back => g_rev_multi_unb,
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_rx,
- g_mesh_gx_mbps => c_mesh_gx_mbps,
- g_mesh_mon_select => c_mesh_mon_select,
- g_mesh_mon_nof_words => c_mesh_mon_nof_words,
- g_mesh_mon_use_sync => c_mesh_mon_use_sync,
- g_mesh_ena_reorder => true,
- -- Auxiliary Interface
- g_aux => c_aux
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- tr_back_clk => SA_CLK,
- cal_clk => cal_clk,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id,
-
- in_sosi_arr => in_sosi_arr,
- in_siso_arr => in_siso_arr,
-
- -- MM interface
- -- . block generator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- -- . tr_nonbonded mesh
- reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
- reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- -- . tr_nonbonded back
- reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
- reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_back_diagnostics_miso => reg_back_diagnostics_miso,
-
- -- . diag_data_buffer mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- Mesh interface
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Back interface
- back_tx_serial_2arr => back_tx_serial_2arr,
- back_rx_serial_2arr => back_rx_serial_2arr
- );
+ generic map(
+ g_sim => g_sim,
+ -- Application interface
+ g_use_bg => true,
+ g_usr_nof_streams => c_usr_nof_streams,
+ g_usr_block_len => c_usr_block_len,
+ -- Terminals interface
+ g_use_mesh => c_use_mesh,
+ g_use_back => g_rev_multi_unb,
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_rx,
+ g_mesh_gx_mbps => c_mesh_gx_mbps,
+ g_mesh_mon_select => c_mesh_mon_select,
+ g_mesh_mon_nof_words => c_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => c_mesh_mon_use_sync,
+ g_mesh_ena_reorder => true,
+ -- Auxiliary Interface
+ g_aux => c_aux
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ tr_back_clk => SA_CLK,
+ cal_clk => cal_clk,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id,
+
+ in_sosi_arr => in_sosi_arr,
+ in_siso_arr => in_siso_arr,
+
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ -- . tr_nonbonded mesh
+ reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+ reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ -- . tr_nonbonded back
+ reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+ reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_back_diagnostics_miso => reg_back_diagnostics_miso,
+
+ -- . diag_data_buffer mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- Mesh interface
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Back interface
+ back_tx_serial_2arr => back_tx_serial_2arr,
+ back_rx_serial_2arr => back_rx_serial_2arr
+ );
-----------------------------------------------------------------------------
@@ -521,42 +521,42 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => mesh_tx_serial_2arr,
- rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => mesh_tx_serial_2arr,
+ rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
gen_tr_back : if c_use_phy.tr_back /= 0 generate
u_back_io : entity unb1_board_lib.unb1_board_back_io
- generic map (
- g_bus_w => c_tr_back.bus_w
- )
- port map (
- tx_serial_2arr => back_tx_serial_2arr,
- rx_serial_2arr => back_rx_serial_2arr,
-
- -- Serial I/O
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX
- );
+ generic map (
+ g_bus_w => c_tr_back.bus_w
+ )
+ port map (
+ tx_serial_2arr => back_tx_serial_2arr,
+ rx_serial_2arr => back_rx_serial_2arr,
+
+ -- Serial I/O
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX
+ );
end generate;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
index fc2e86fa11..ccfac622e9 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
@@ -28,17 +28,17 @@
-- behaviour in the Wave window.
library IEEE, common_lib, dp_lib, diag_lib, bf_lib, unb1_board_lib, diagnostics_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use bf_lib.bf_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use diagnostics_lib.tb_diagnostics_trnb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use diagnostics_lib.tb_diagnostics_trnb_pkg.all;
entity tb_node_unb1_bn_terminal_bg is
generic (
@@ -218,27 +218,27 @@ begin
-- GENERATE BLOCK GENERATOR FOR STIMULI ON SOSI PORT
---------------------------------------------------------------
u_block_generator : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_bf.nof_input_streams,
- g_buf_dat_w => c_nof_complex * g_bf.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_index_arr => g_bg_data_file_index_arr,
- g_file_name_prefix => g_bg_data_file_name
- )
- port map(
- -- Clocks and Reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => '1',
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => open,
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => open,
- out_siso_arr => in_siso_arr,
- out_sosi_arr => in_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_bf.nof_input_streams,
+ g_buf_dat_w => c_nof_complex * g_bf.in_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_index_arr => g_bg_data_file_index_arr,
+ g_file_name_prefix => g_bg_data_file_name
+ )
+ port map(
+ -- Clocks and Reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => '1',
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => open,
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => open,
+ out_siso_arr => in_siso_arr,
+ out_sosi_arr => in_sosi_arr
+ );
----------------------------------------------------------------------------
-- Stimuli for TRNB diagnostics
@@ -282,75 +282,75 @@ begin
------------------------------------------------------------------------------
u_dut : entity work.node_unb1_bn_terminal_bg
- generic map (
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- -- Application interface
- g_use_bg => g_use_bg,
--- g_bg_data_file_index_arr => g_bg_data_file_index_arr,
--- g_bg_data_file_prefix => g_bg_data_file_name,
- g_use_back => g_use_back,
-
- -- Terminals interface
- g_mesh_nof_serial => g_mesh_nof_serial,
- g_mesh_use_rx => g_mesh_use_rx,
- g_mesh_gx_mbps => g_mesh_gx_mbps,
- g_mesh_mon_select => g_mesh_mon_select,
- g_mesh_mon_nof_words => g_mesh_mon_nof_words,
- g_mesh_mon_use_sync => g_mesh_mon_use_sync,
- g_mesh_ena_reorder => g_mesh_ena_reorder,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux
- )
- port map (
- -- System
- chip_id => TO_UVEC(g_chip_id, c_unb1_board_nof_chip_w), -- BN chip ID 4, 5, 6, 7
- bck_id => TO_UVEC(g_bck_id, c_unb1_board_nof_uniboard_w), -- Backplane ID 0,1,2,3
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_clk,
- tr_back_clk => tr_clk,
- cal_clk => cal_clk,
-
- -- Streaming data input
- in_sosi_arr => in_sosi_arr,
- in_siso_arr => in_siso_arr,
-
- -- MM registers
- -- . block generator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- -- . tr_nonbonded
- reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
- reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
- reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_back_diagnostics_miso => reg_back_diagnostics_miso,
-
- -- . rx terminals monitor buffers
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Back interface level
- -- . Serial (tr_nonbonded)
- back_tx_serial_2arr => back_tx_serial_2arr,
- back_rx_serial_2arr => back_rx_serial_2arr
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ -- Application interface
+ g_use_bg => g_use_bg,
+ -- g_bg_data_file_index_arr => g_bg_data_file_index_arr,
+ -- g_bg_data_file_prefix => g_bg_data_file_name,
+ g_use_back => g_use_back,
+
+ -- Terminals interface
+ g_mesh_nof_serial => g_mesh_nof_serial,
+ g_mesh_use_rx => g_mesh_use_rx,
+ g_mesh_gx_mbps => g_mesh_gx_mbps,
+ g_mesh_mon_select => g_mesh_mon_select,
+ g_mesh_mon_nof_words => g_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => g_mesh_mon_use_sync,
+ g_mesh_ena_reorder => g_mesh_ena_reorder,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- System
+ chip_id => TO_UVEC(g_chip_id, c_unb1_board_nof_chip_w), -- BN chip ID 4, 5, 6, 7
+ bck_id => TO_UVEC(g_bck_id, c_unb1_board_nof_uniboard_w), -- Backplane ID 0,1,2,3
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_clk,
+ tr_back_clk => tr_clk,
+ cal_clk => cal_clk,
+
+ -- Streaming data input
+ in_sosi_arr => in_sosi_arr,
+ in_siso_arr => in_siso_arr,
+
+ -- MM registers
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ -- . tr_nonbonded
+ reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+ reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+ reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_back_diagnostics_miso => reg_back_diagnostics_miso,
+
+ -- . rx terminals monitor buffers
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Back interface level
+ -- . Serial (tr_nonbonded)
+ back_tx_serial_2arr => back_tx_serial_2arr,
+ back_rx_serial_2arr => back_rx_serial_2arr
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
index 5c5218d842..72e5e41c73 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
@@ -33,12 +33,12 @@
library IEEE, common_lib, dp_lib, bf_lib, unb_common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use bf_lib.bf_pkg.all;
-use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use unb_common_lib.unb_common_pkg.all;
entity tb_tb_node_bn_terminal_bg is
generic (
@@ -67,33 +67,33 @@ architecture tb of tb_tb_node_bn_terminal_bg is
begin
u_tb_node_bn_terminal_bg : entity work.tb_node_bn_terminal_bg
- generic map (
- -- Tb
- g_sim_level => 1, -- 0 = simulate GX IP, 1 = use fast serial behavioural model
- g_nof_sync => g_nof_sync,
- g_chip_id => 4,
- -- Application
- g_bf => c_bf,
- g_bg_data_file_index_arr => array_init(0, 16, 1),
- g_bg_data_file_name => "../../../../../../modules/Lofar/diag/src/data/bf_in_data",
- -- Diagnostics - TRNB
- g_diagnostics_en => g_diagnostics_en,
- -- Terminals interface
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_rx,
- g_mesh_ena_reorder => c_mesh_ena_reorder
- )
- port map (
- tb_clk => tb_clk,
- tb_end => tb_end,
-
- -- Timing
- dp_pps => dp_pps,
-
- -- Serial (tr_nonbonded)
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr
- );
+ generic map (
+ -- Tb
+ g_sim_level => 1, -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ g_nof_sync => g_nof_sync,
+ g_chip_id => 4,
+ -- Application
+ g_bf => c_bf,
+ g_bg_data_file_index_arr => array_init(0, 16, 1),
+ g_bg_data_file_name => "../../../../../../modules/Lofar/diag/src/data/bf_in_data",
+ -- Diagnostics - TRNB
+ g_diagnostics_en => g_diagnostics_en,
+ -- Terminals interface
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_rx,
+ g_mesh_ena_reorder => c_mesh_ena_reorder
+ )
+ port map (
+ tb_clk => tb_clk,
+ tb_end => tb_end,
+
+ -- Timing
+ dp_pps => dp_pps,
+
+ -- Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr
+ );
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index db070b1f80..a7627ae41c 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -20,19 +20,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
entity mmm_unb1_ddr3 is
generic (
@@ -173,40 +173,40 @@ begin
i_cal_clk <= not i_cal_clk after c_cal_clk_period / 2;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso );
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso );
u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
u_mm_file_reg_diag_bg_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_CTRL")
- port map(mm_rst, i_mm_clk, reg_diag_bg_ctrl_mosi, reg_diag_bg_ctrl_miso );
+ port map(mm_rst, i_mm_clk, reg_diag_bg_ctrl_mosi, reg_diag_bg_ctrl_miso );
u_mm_file_ram_diag_bg_data : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DATA")
- port map(mm_rst, i_mm_clk, ram_diag_bg_data_mosi, ram_diag_bg_data_miso );
+ port map(mm_rst, i_mm_clk, ram_diag_bg_data_mosi, ram_diag_bg_data_miso );
u_mm_file_reg_diag_tx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
+ port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
u_mm_file_reg_diag_rx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
+ port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
----------------------------------------------------------------------------
@@ -250,153 +250,153 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_ddr3
- port map (
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_io_ddr
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg_data
- coe_clk_export_from_the_ram_diag_bg_data => OPEN,
- coe_reset_export_from_the_ram_diag_bg_data => OPEN,
- coe_address_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.address(c_mm_ram_diag_bg_data_addr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg_data => ram_diag_bg_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf
- coe_clk_export_from_the_ram_diag_data_buf => OPEN,
- coe_reset_export_from_the_ram_diag_data_buf => OPEN,
- coe_address_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.address(c_mm_ram_diag_data_buf_addr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buf => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg_ctrl
- coe_clk_export_from_the_reg_diag_bg_ctrl => OPEN,
- coe_reset_export_from_the_reg_diag_bg_ctrl => OPEN,
- coe_address_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.address(c_mm_reg_diag_bg_ctrl_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf
- coe_clk_export_from_the_reg_diag_data_buf => OPEN,
- coe_reset_export_from_the_reg_diag_data_buf => OPEN,
- coe_address_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.address(c_mm_reg_diag_data_buf_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buf => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_rx_seq
- coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
- coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_mm_reg_diag_rx_seq_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_tx_seq
- coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
- coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_mm_reg_diag_tx_seq_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_io_ddr
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg_data
+ coe_clk_export_from_the_ram_diag_bg_data => OPEN,
+ coe_reset_export_from_the_ram_diag_bg_data => OPEN,
+ coe_address_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.address(c_mm_ram_diag_bg_data_addr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg_data => ram_diag_bg_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf
+ coe_clk_export_from_the_ram_diag_data_buf => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buf => OPEN,
+ coe_address_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.address(c_mm_ram_diag_data_buf_addr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buf => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg_ctrl
+ coe_clk_export_from_the_reg_diag_bg_ctrl => OPEN,
+ coe_reset_export_from_the_reg_diag_bg_ctrl => OPEN,
+ coe_address_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.address(c_mm_reg_diag_bg_ctrl_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf
+ coe_clk_export_from_the_reg_diag_data_buf => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buf => OPEN,
+ coe_address_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.address(c_mm_reg_diag_data_buf_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buf => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_rx_seq
+ coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_mm_reg_diag_rx_seq_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_tx_seq
+ coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_mm_reg_diag_tx_seq_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
index aa082048a3..d6da0849d3 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diagnostics_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity node_unb1_ddr3 is
generic (
@@ -115,78 +115,78 @@ architecture str of node_unb1_ddr3 is
begin
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => g_st_dat_w,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => g_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => ddr_ref_clk,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk,
- ctlr_rst_out => ddr_out_rst,
-
- ctlr_clk_in => dp_clk,
- ctlr_rst_in => dp_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on termination control from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_I_in,
- phy3_io => MB_I_io,
- phy3_ou => MB_I_ou,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso
- );
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => g_st_dat_w,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => g_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => ddr_ref_clk,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_out_clk,
+ ctlr_rst_out => ddr_out_rst,
+
+ ctlr_clk_in => dp_clk,
+ ctlr_rst_in => dp_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_I_in,
+ phy3_io => MB_I_io,
+ phy3_ou => MB_I_ou,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
index 0078bdb463..8ce0691833 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3 is
generic (
@@ -77,17 +77,17 @@ architecture str of unb1_ddr3 is
constant c_design_name : string := "unb1_ddr3";
constant c_design_note : string := "DDR3 reference design";
constant c_fw_version : t_unb1_board_fw_version := (0, 3); -- firmware version x.y
- -- Use PHY Interface
- -- TYPE t_c_unb_use_phy IS RECORD
- -- eth1g : NATURAL;
- -- tr_front: NATURAL;
- -- tr_mesh : NATURAL;
- -- tr_back : NATURAL;
- -- ddr3_I : NATURAL;
- -- ddr3_II : NATURAL;
- -- adc : NATURAL;
- -- wdi : NATURAL;
- -- END RECORD;
+ -- Use PHY Interface
+ -- TYPE t_c_unb_use_phy IS RECORD
+ -- eth1g : NATURAL;
+ -- tr_front: NATURAL;
+ -- tr_mesh : NATURAL;
+ -- tr_back : NATURAL;
+ -- ddr3_I : NATURAL;
+ -- ddr3_II : NATURAL;
+ -- adc : NATURAL;
+ -- wdi : NATURAL;
+ -- END RECORD;
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
constant c_aux : t_c_unb1_board_aux := c_unb1_board_aux;
constant c_app_led_en : boolean := true;
@@ -143,9 +143,9 @@ architecture str of unb1_ddr3 is
signal eth1g_reg_interrupt : std_logic; -- Interrupt
signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
signal eth1g_ram_miso : t_mem_miso;
--- SIGNAL eth1g_led : t_tech_tse_led;
+ -- SIGNAL eth1g_led : t_tech_tse_led;
- -- . UniBoard I2C sens
+ -- . UniBoard I2C sens
signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
@@ -178,244 +178,244 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- -- General
- g_sim => g_sim,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_name => c_design_name,
- g_design_note => c_design_note,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_use_pll => false,
- g_app_led_red => c_app_led_en,
- g_app_led_green => c_app_led_en,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN,
- dp_clk => OPEN,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => OPEN,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- --
- -- >>> Ctrl FPGA pins
- --
- -- General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_name => c_design_name,
+ g_design_note => c_design_note,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_use_pll => false,
+ g_app_led_red => c_app_led_en,
+ g_app_led_green => c_app_led_en,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN,
+ dp_clk => OPEN,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => OPEN,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ --
+ -- >>> Ctrl FPGA pins
+ --
+ -- General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
u_mmm : entity work.mmm_unb1_ddr3
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map (
- -- GENERAL
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- DDR3
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Block Generator Control
- reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
- reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
-
- -- Block Generator Data
- ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
- ram_diag_bg_data_miso => ram_diag_bg_data_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map (
+ -- GENERAL
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- DDR3
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Block Generator Control
+ reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
+ reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
+
+ -- Block Generator Data
+ ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
+ ram_diag_bg_data_miso => ram_diag_bg_data_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso
+ );
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
u_node : entity work.node_unb1_ddr3
- generic map (
- g_sim => g_sim,
- g_technology => c_technology,
- g_tech_ddr => c_tech_ddr,
- g_st_dat_w => g_st_dat_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ddr_ref_clk => CLK,
- ddr_ref_rst => ddr_ref_rst,
-
- -- Clock outputs
- ddr_out_clk => dp_clk,
- ddr_out_rst => dp_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Block Generator Control
- reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
- reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
-
- -- Block Generator Data
- ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
- ram_diag_bg_data_miso => ram_diag_bg_data_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => c_technology,
+ g_tech_ddr => c_tech_ddr,
+ g_st_dat_w => g_st_dat_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Block Generator Control
+ reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
+ reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
+
+ -- Block Generator Data
+ ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
+ ram_diag_bg_data_miso => ram_diag_bg_data_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
index 9bcdac9295..5de437da71 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
@@ -31,20 +31,20 @@
-- > python tc_unb1_ddr3_seq.py --sim --unb 0 --fn 3 --rep 3
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, tech_ddr_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_unb1_ddr3 is
@@ -73,7 +73,7 @@ architecture tb of tb_unb1_ddr3 is
constant c_ext_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
- -- SO-DIMM Memory Bank I = ddr3_I
+ -- SO-DIMM Memory Bank I = ddr3_I
signal MB_I_in : t_tech_ddr3_phy_in;
signal MB_I_io : t_tech_ddr3_phy_io;
signal MB_I_ou : t_tech_ddr3_phy_ou;
@@ -100,7 +100,7 @@ architecture tb of tb_unb1_ddr3 is
begin
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
clk <= not clk after c_ext_clk_period / 2; -- External clock (200 MHz)
@@ -127,53 +127,53 @@ begin
------------------------------------------------------------------------------
dut : entity work.unb1_ddr3
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_st_dat_w => c_st_dat_w
-
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_IN => MB_I_in,
- MB_I_IO => MB_I_io,
- MB_I_OU => MB_I_ou
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
+ g_st_dat_w => c_st_dat_w
+
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_IN => MB_I_in,
+ MB_I_IO => MB_I_io,
+ MB_I_OU => MB_I_ou
+ );
------------------------------------------------------------------------------
-- DDR3 memory model
------------------------------------------------------------------------------
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr
- )
- port map (
- mem3_in => MB_I_ou,
- mem3_io => MB_I_io,
- mem3_ou => MB_I_in
- );
+ generic map (
+ g_tech_ddr => c_ddr
+ )
+ port map (
+ mem3_in => MB_I_ou,
+ mem3_io => MB_I_io,
+ mem3_ou => MB_I_in
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
index 8027e6e0dd..8cbf8b875d 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
@@ -20,20 +20,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb1_ddr3_reorder_dual_rank is
- generic (
- g_design_name : string := "unb1_ddr3_reorder_dual_rank";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder_dual_rank";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master
+ );
end tb_unb1_ddr3_reorder_dual_rank;
architecture tb of tb_unb1_ddr3_reorder_dual_rank is
@@ -46,6 +46,6 @@ begin
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_tech_ddr => g_tech_ddr
- );
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
index 0974f466bf..e4a72852b4 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3_reorder_dual_rank is
generic (
@@ -75,37 +75,37 @@ architecture str of unb1_ddr3_reorder_dual_rank is
begin
u_revision : entity work.unb1_ddr3_reorder
- generic map(
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_aux => g_aux
- )
- port map(
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map(
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_aux => g_aux
+ )
+ port map(
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
index e9092a7f9c..364ee94a00 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
@@ -20,20 +20,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb1_ddr3_reorder_single_rank is
- generic (
- g_design_name : string := "unb1_ddr3_reorder_single_rank";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder_single_rank";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
+ );
end tb_unb1_ddr3_reorder_single_rank;
architecture tb of tb_unb1_ddr3_reorder_single_rank is
@@ -46,6 +46,6 @@ begin
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_tech_ddr => g_tech_ddr
- );
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
index 008e30d017..817b0d81ed 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3_reorder_single_rank is
generic (
@@ -75,37 +75,37 @@ architecture str of unb1_ddr3_reorder_single_rank is
begin
u_revision : entity work.unb1_ddr3_reorder
- generic map(
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_aux => g_aux
- )
- port map(
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map(
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_aux => g_aux
+ )
+ port map(
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index e68a8ec5d0..74f8241810 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, reorder_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use reorder_lib.reorder_pkg.all;
-use technology_lib.technology_select_pkg.all;
---USE tech_ddr_lib.tech_ddr_pkg.ALL;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use reorder_lib.reorder_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ --USE tech_ddr_lib.tech_ddr_pkg.ALL;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity mmm_unb1_ddr3_reorder is
generic (
@@ -46,7 +46,7 @@ entity mmm_unb1_ddr3_reorder is
g_sim_node_nr : natural := 0;
g_nof_streams : natural := 4;
g_reorder_seq : t_reorder_seq := c_reorder_seq
- );
+ );
port (
-- GENERAL
xo_clk : in std_logic;
@@ -180,46 +180,46 @@ begin
i_cal_clk <= not i_cal_clk after c_cal_clk_period / 2;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_reg_diag_tx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
+ port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
u_mm_file_reg_diag_rx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
+ port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
u_mm_file_ram_ss_ss_transp : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso);
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso);
u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -243,10 +243,10 @@ begin
p_switch : process(mm_bus_switch, eth1g_reg_proc_mosi, i_eth1g_reg_mosi)
begin
if mm_bus_switch = '1' then
- eth1g_reg_mosi <= eth1g_reg_proc_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= eth1g_reg_proc_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -262,170 +262,170 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_ddr3_reorder
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => i_tse_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg: entry for the register space of the block generator
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_rx_seq: entry for the register space of the rx sequencer
- coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
- coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_reg_diag_rx_seq_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_tx_seq: entry for the register space of the tx sequencer
- coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
- coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_reg_diag_tx_seq_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg: entry for the ram space of the block generator
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf: register space for the databuffer
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_data_buf_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf: ram space for the databuffer
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_ram_diag_data_buf_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_ss_ss_transp: ram space for the subband select unit
- coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
- coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
- coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
- coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
- coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(3 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => i_tse_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg: entry for the register space of the block generator
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_rx_seq: entry for the register space of the rx sequencer
+ coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_reg_diag_rx_seq_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_tx_seq: entry for the register space of the tx sequencer
+ coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_reg_diag_tx_seq_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg: entry for the ram space of the block generator
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf: register space for the databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_data_buf_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf: ram space for the databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_ram_diag_data_buf_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_ss_ss_transp: ram space for the subband select unit
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(3 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
index 2e3956bcd0..e2e286368e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity node_unb1_ddr3_reorder is
generic (
@@ -43,7 +43,7 @@ entity node_unb1_ddr3_reorder is
g_frame_size_out : natural := 176;
g_reorder_seq : t_reorder_seq := c_reorder_seq
);
-port (
+ port (
-- System
mm_rst : in std_logic;
mm_clk : in std_logic;
@@ -143,27 +143,27 @@ architecture str of node_unb1_ddr3_reorder is
begin
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_nof_bsn_streams, -- Check one input and one output stream
- g_cross_clock_domain => true,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => bsn_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_bsn_streams, -- Check one input and one output stream
+ g_cross_clock_domain => true,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => bsn_sosi_arr
+ );
bsn_sosi_arr(0) <= bg_sosi_arr(0);
bsn_sosi_arr(1) <= to_mem_sosi;
@@ -174,113 +174,113 @@ begin
-- TRANSPOSE UNIT
------------------------------------------------------------------------------
u_transpose: entity reorder_lib.reorder_transpose
- generic map(
- g_nof_streams => g_nof_streams,
- g_in_dat_w => g_in_dat_w,
- g_frame_size_in => g_frame_size_in,
- g_frame_size_out => g_frame_size_out,
- g_use_complex => c_use_complex,
- g_ena_pre_transp => g_ena_pre_transp,
- g_reorder_seq => g_reorder_seq
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
-
- -- ST sink
- snk_out_arr => bg_siso_arr,
- snk_in_arr => bg_sosi_arr,
-
- -- ST source
- src_in_arr => db_siso_arr,
- src_out_arr => db_sosi_arr,
-
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- Control interface to the external memory
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Data interface to the external memory
- to_mem_src_out => to_mem_sosi,
- to_mem_src_in => to_mem_siso,
-
- from_mem_snk_in => from_mem_sosi,
- from_mem_snk_out => from_mem_siso
-
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_in_dat_w => g_in_dat_w,
+ g_frame_size_in => g_frame_size_in,
+ g_frame_size_out => g_frame_size_out,
+ g_use_complex => c_use_complex,
+ g_ena_pre_transp => g_ena_pre_transp,
+ g_reorder_seq => g_reorder_seq
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+
+ -- ST sink
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+
+ -- ST source
+ src_in_arr => db_siso_arr,
+ src_out_arr => db_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- Control interface to the external memory
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Data interface to the external memory
+ to_mem_src_out => to_mem_sosi,
+ to_mem_src_in => to_mem_siso,
+
+ from_mem_snk_in => from_mem_sosi,
+ from_mem_snk_out => from_mem_siso
+
+ );
------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------
u_ddr_mem_ctrl : entity io_ddr_lib.io_ddr
- generic map(
- g_technology => g_tech_select_default,
- g_tech_ddr => g_tech_ddr,
- g_cross_domain_dvr_ctlr => false,
- g_wr_data_w => c_data_w,
- g_wr_fifo_depth => c_fifo_depth,
- g_rd_fifo_depth => c_fifo_depth,
- g_rd_data_w => c_data_w,
- g_wr_flush_mode => "SYN",
- g_wr_flush_use_channel => false,
- g_wr_flush_start_channel => 0,
- g_wr_flush_nof_channels => 1
- )
- port map (
- -- DDR reference clock
- ctlr_ref_clk => ddr_ref_clk,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk_i, -- output clock of the ddr controller is used as DP clk.
- ctlr_rst_out => ddr_out_rst_i,
-
- ctlr_clk_in => ddr_out_clk_i,
- ctlr_rst_in => ddr_out_rst_i,
-
- -- MM clock + reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM register map for DDR controller status info
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Driver clock domain
- dvr_clk => ddr_out_clk_i,
- dvr_rst => ddr_out_rst_i,
-
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Write FIFO clock domain
- wr_clk => ddr_out_clk_i,
- wr_rst => ddr_out_rst_i,
-
- wr_fifo_usedw => OPEN,
- wr_sosi => to_mem_sosi,
- wr_siso => to_mem_siso,
-
- -- Read FIFO clock domain
- rd_clk => ddr_out_clk_i,
- rd_rst => ddr_out_rst_i,
-
- rd_fifo_usedw => OPEN,
- rd_sosi => from_mem_sosi,
- rd_siso => from_mem_siso,
-
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- phy3_in => MB_I_IN,
- phy3_io => MB_I_IO,
- phy3_ou => MB_I_OU
- );
+ generic map(
+ g_technology => g_tech_select_default,
+ g_tech_ddr => g_tech_ddr,
+ g_cross_domain_dvr_ctlr => false,
+ g_wr_data_w => c_data_w,
+ g_wr_fifo_depth => c_fifo_depth,
+ g_rd_fifo_depth => c_fifo_depth,
+ g_rd_data_w => c_data_w,
+ g_wr_flush_mode => "SYN",
+ g_wr_flush_use_channel => false,
+ g_wr_flush_start_channel => 0,
+ g_wr_flush_nof_channels => 1
+ )
+ port map (
+ -- DDR reference clock
+ ctlr_ref_clk => ddr_ref_clk,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_out_clk_i, -- output clock of the ddr controller is used as DP clk.
+ ctlr_rst_out => ddr_out_rst_i,
+
+ ctlr_clk_in => ddr_out_clk_i,
+ ctlr_rst_in => ddr_out_rst_i,
+
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM register map for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Driver clock domain
+ dvr_clk => ddr_out_clk_i,
+ dvr_rst => ddr_out_rst_i,
+
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Write FIFO clock domain
+ wr_clk => ddr_out_clk_i,
+ wr_rst => ddr_out_rst_i,
+
+ wr_fifo_usedw => OPEN,
+ wr_sosi => to_mem_sosi,
+ wr_siso => to_mem_siso,
+
+ -- Read FIFO clock domain
+ rd_clk => ddr_out_clk_i,
+ rd_rst => ddr_out_rst_i,
+
+ rd_fifo_usedw => OPEN,
+ rd_sosi => from_mem_sosi,
+ rd_siso => from_mem_siso,
+
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ phy3_in => MB_I_IN,
+ phy3_io => MB_I_IO,
+ phy3_ou => MB_I_OU
+ );
ddr_out_clk <= ddr_out_clk_i;
ddr_out_rst <= ddr_out_rst_i;
@@ -289,70 +289,70 @@ begin
-- DIAG Block Generator
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- -- Generate configurations
- g_use_usr_input => false,
- g_use_bg => true,
- g_use_tx_seq => true,
- -- General
- g_nof_streams => g_nof_streams,
- -- BG settings
- g_use_bg_buffer_ram => false,
- -- Tx_seq
- g_seq_dat_w => c_data_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map (
+ -- Generate configurations
+ g_use_usr_input => false,
+ g_use_bg => true,
+ g_use_tx_seq => true,
+ -- General
+ g_nof_streams => g_nof_streams,
+ -- BG settings
+ g_use_bg_buffer_ram => false,
+ -- Tx_seq
+ g_seq_dat_w => c_data_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
-----------------------------------------------------------------------------
-- DIAG Rx seq with optional Data Buffer
-----------------------------------------------------------------------------
u_mms_diag_data_buffer: entity diag_lib.mms_diag_data_buffer
- generic map (
- -- Generate configurations
- g_use_db => c_use_db,
- g_use_rx_seq => c_use_rx_seq,
- -- General
- g_nof_streams => g_nof_streams,
- -- DB settings
- g_data_type => e_data, -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
- g_data_w => c_data_w,
- g_buf_nof_data => c_buf_nof_data,
- g_buf_use_sync => c_buf_use_sync, -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
- -- Rx_seq
- g_use_steps => c_use_steps,
- g_seq_dat_w => c_data_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- ST interface
- in_sosi_arr => db_sosi_arr
- );
+ generic map (
+ -- Generate configurations
+ g_use_db => c_use_db,
+ g_use_rx_seq => c_use_rx_seq,
+ -- General
+ g_nof_streams => g_nof_streams,
+ -- DB settings
+ g_data_type => e_data, -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
+ g_data_w => c_data_w,
+ g_buf_nof_data => c_buf_nof_data,
+ g_buf_use_sync => c_buf_use_sync, -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
+ -- Rx_seq
+ g_use_steps => c_use_steps,
+ g_seq_dat_w => c_data_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- ST interface
+ in_sosi_arr => db_sosi_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
index 07190743fb..10317ab1ea 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, technology_lib, tech_ddr_lib, diag_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity unb1_ddr3_reorder is
generic (
@@ -97,12 +97,14 @@ architecture str of unb1_ddr3_reorder is
constant c_nof_blocks : natural := sel_a_b(g_sim, 16, 800000);
constant c_nof_streams : natural := 1;
constant c_in_dat_w : natural := 64;
- constant c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,
- c_rd_chunksize,
- c_rd_nof_chunks,
- c_rd_interval,
- c_gapsize,
- c_nof_blocks);
+ constant c_reorder_seq_conf : t_reorder_seq := (
+ c_wr_chunksize,
+ c_rd_chunksize,
+ c_rd_nof_chunks,
+ c_rd_interval,
+ c_gapsize,
+ c_nof_blocks
+ );
-- System
signal cs_sim : std_logic;
@@ -175,7 +177,7 @@ architecture str of unb1_ddr3_reorder is
signal reg_io_ddr_mosi : t_mem_mosi;
signal reg_io_ddr_miso : t_mem_miso;
- -- . UniBoard I2C sens
+ -- . UniBoard I2C sens
signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
@@ -196,264 +198,264 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- -- General
- g_sim => g_sim,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_use_pll => false,
- g_app_led_red => c_app_led_en,
- g_app_led_green => c_app_led_en,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN, -- dp_rst,
- dp_clk => OPEN, -- dp_clk, -- dp_clk is now generated in the DDR controller
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => OPEN,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_use_pll => false,
+ g_app_led_red => c_app_led_en,
+ g_app_led_green => c_app_led_en,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN, -- dp_rst,
+ dp_clk => OPEN, -- dp_clk, -- dp_clk is now generated in the DDR controller
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => OPEN,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
u_mmm : entity work.mmm_unb1_ddr3_reorder
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams => c_nof_streams,
- g_reorder_seq => c_reorder_seq_conf
- )
- port map (
- -- GENERAL
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- Blockgenerator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- DDR3 transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- Databuffers
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- IO DDR register map
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso
-
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams => c_nof_streams,
+ g_reorder_seq => c_reorder_seq_conf
+ )
+ port map (
+ -- GENERAL
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- Blockgenerator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- DDR3 transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Databuffers
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso
+
+ );
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => '0',
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => '0',
+ out_rst => ddr_ref_rst
+ );
u_node : entity work.node_unb1_ddr3_reorder
- generic map(
- g_sim => g_sim,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_nof_streams => c_nof_streams,
- g_in_dat_w => c_in_dat_w,
- g_ena_pre_transp => c_ena_pre_transp,
- g_frame_size_in => c_frame_size_in,
- g_frame_size_out => c_frame_size_out,
- g_reorder_seq => c_reorder_seq_conf
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ddr_ref_clk => CLK, -- Provide external 200 MHZ clk to DDR controller
- ddr_ref_rst => ddr_ref_rst,
-
- -- Clock outputs
- ddr_out_clk => dp_clk,
- ddr_out_rst => dp_rst, -- dp_clk is generated by DDR controller
-
- -- IO DDR register map
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Reorder transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Blockgenerator Control
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
-
- -- Blockgenerator Data
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_in => MB_I_IN,
- MB_I_io => MB_I_IO,
- MB_I_ou => MB_I_OU
- );
+ generic map(
+ g_sim => g_sim,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_nof_streams => c_nof_streams,
+ g_in_dat_w => c_in_dat_w,
+ g_ena_pre_transp => c_ena_pre_transp,
+ g_frame_size_in => c_frame_size_in,
+ g_frame_size_out => c_frame_size_out,
+ g_reorder_seq => c_reorder_seq_conf
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK, -- Provide external 200 MHZ clk to DDR controller
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst, -- dp_clk is generated by DDR controller
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Reorder transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Blockgenerator Control
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+
+ -- Blockgenerator Data
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_in => MB_I_IN,
+ MB_I_io => MB_I_IO,
+ MB_I_ou => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
index 89a57d08b4..56ab74b0a3 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
@@ -27,29 +27,29 @@
library ip_stratixiv_ddr3_mem_model_lib;
library IEEE, common_lib, unb1_board_lib, i2c_lib, dp_lib, io_ddr_lib, eth_lib, technology_lib, tech_ddr_lib, diag_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity tb_unb1_ddr3_reorder is
- generic (
- g_design_name : string := "unb1_ddr3_reorder";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
+ );
end tb_unb1_ddr3_reorder;
architecture tb of tb_unb1_ddr3_reorder is
@@ -126,7 +126,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
-- 1GbE Loopback model
------------------------------------------------------------------------------
eth_rxp <= transport eth_txp after c_cable_delay;
@@ -174,51 +174,51 @@ begin
-- DDR3 memory model
------------------------------------------------------------------------------
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => g_tech_ddr
- )
- port map (
- mem3_in => phy_ou,
- mem3_io => phy_io,
- mem3_ou => phy_in
- );
+ generic map (
+ g_tech_ddr => g_tech_ddr
+ )
+ port map (
+ mem3_in => phy_ou,
+ mem3_io => phy_io,
+ mem3_ou => phy_in
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 7d0c3aabe1..7c6a3c70fb 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_field_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity mmm_unb_ddr3_transpose is
@@ -141,50 +141,50 @@ begin
mm_locked <= '0', '1' after c_mm_clk_period * 5;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_RE")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_RE")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_IM")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_IM")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
u_mm_file_ram_ss_ss_transp : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -199,169 +199,169 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb_ddr3_transpose
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg: entry for the register space of the block generator
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg: entry for the ram space of the block generator
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf_im: register space for the imaginary databuffer
- coe_clk_export_from_the_reg_diag_data_buffer_im => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer_im => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.address(c_reg_diag_data_buf_im_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf_im: ram space for the imaginary databuffer
- coe_clk_export_from_the_ram_diag_data_buffer_im => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer_im => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.address(c_ram_diag_data_buf_im_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf_re: register space for the real databuffer
- coe_clk_export_from_the_reg_diag_data_buffer_re => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer_re => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.address(c_reg_diag_data_buf_re_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf_re: ram space for the real databuffer
- coe_clk_export_from_the_ram_diag_data_buffer_re => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer_re => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.address(c_ram_diag_data_buf_re_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_ss_ss_transp: ram space for the subband select unit
- coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
- coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
- coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
- coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
- coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_io_ddr
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(1 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg: entry for the register space of the block generator
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg: entry for the ram space of the block generator
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf_im: register space for the imaginary databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer_im => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer_im => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.address(c_reg_diag_data_buf_im_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf_im: ram space for the imaginary databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer_im => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer_im => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.address(c_ram_diag_data_buf_im_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf_re: register space for the real databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer_re => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer_re => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.address(c_reg_diag_data_buf_re_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf_re: ram space for the real databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer_re => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer_re => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.address(c_ram_diag_data_buf_re_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_ss_ss_transp: ram space for the subband select unit
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_io_ddr
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(1 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index 9c38d3a1e3..ce5f0d1801 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, eth_lib, diag_lib, dp_lib, ddr3_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity unb1_ddr3_transpose is
generic (
@@ -90,12 +90,14 @@ architecture str of unb1_ddr3_transpose is
constant c_gapsize : natural := sel_a_b(g_sim, 0, 0); -- 0);
constant c_nof_blocks : positive := sel_a_b(g_sim, 4, 4); -- 16);
- constant c_ddr3_seq_conf : t_ddr3_seq := (c_wr_chunksize,
- c_wr_nof_chunks,
- c_rd_chunksize,
- c_rd_nof_chunks,
- c_gapsize,
- c_nof_blocks);
+ constant c_ddr3_seq_conf : t_ddr3_seq := (
+ c_wr_chunksize,
+ c_wr_nof_chunks,
+ c_rd_chunksize,
+ c_rd_nof_chunks,
+ c_gapsize,
+ c_nof_blocks
+ );
constant c_blocksize : positive := c_wr_nof_chunks * c_wr_chunksize;
@@ -220,337 +222,337 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_dp_clk_use_pll => false,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN, -- dp_rst,
- dp_clk => OPEN, -- dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- -- . system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_dp_clk_use_pll => false,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN, -- dp_rst,
+ dp_clk => OPEN, -- dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ -- . system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb_ddr3_transpose
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_frame_size_in => c_frame_size_in,
- g_nof_streams => c_nof_streams,
- g_ddr3_seq => c_ddr3_seq_conf
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- Blockgenerator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- DDR3 transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- Databuffers
- ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
- ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
- reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
- reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
- ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
- ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
- reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
- reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso
-
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_frame_size_in => c_frame_size_in,
+ g_nof_streams => c_nof_streams,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Blockgenerator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- DDR3 transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- Databuffers
+ ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
+ ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
+ reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
+ reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
+ ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
+ ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
+ reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
+ reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso
+
+ );
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 2, -- Check one input and one output stream
- g_cross_clock_domain => true,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => bsn_sosi_arr
- );
+ generic map (
+ g_nof_streams => 2, -- Check one input and one output stream
+ g_cross_clock_domain => true,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => bsn_sosi_arr
+ );
bsn_sosi_arr(0) <= bg_sosi_arr(0);
bsn_sosi_arr(1) <= out_sosi_arr(0);
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
u_ddr3_T: entity ddr3_lib.ddr3_transpose
- generic map(
- g_sim => g_sim,
- g_nof_streams => c_nof_streams,
- g_in_dat_w => c_bg_buf_dat_w / c_nof_complex,
- g_frame_size_in => c_frame_size_in,
- g_frame_size_out => c_frame_size_out,
- g_nof_blk_per_sync => c_nof_blk_per_sync,
- g_use_complex => true,
- g_ena_pre_transp => c_ena_pre_transpose,
- g_phy => c_phy,
- g_mts => c_mts,
- g_ddr3_seq => c_ddr3_seq_conf
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_ref_clk => CLK,
- dp_ref_rst => ddr_ref_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- dp_out_clk => dp_clk,
- dp_out_rst => dp_rst,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- snk_out_arr => bg_siso_arr,
- snk_in_arr => bg_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr,
-
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- ser_term_ctrl_out => OPEN,
- par_term_ctrl_out => OPEN,
-
- ser_term_ctrl_in => OPEN,
- par_term_ctrl_in => OPEN,
-
- phy_in => MB_I_in,
- phy_io => MB_I_io,
- phy_ou => MB_I_ou
- );
+ generic map(
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams,
+ g_in_dat_w => c_bg_buf_dat_w / c_nof_complex,
+ g_frame_size_in => c_frame_size_in,
+ g_frame_size_out => c_frame_size_out,
+ g_nof_blk_per_sync => c_nof_blk_per_sync,
+ g_use_complex => true,
+ g_ena_pre_transp => c_ena_pre_transpose,
+ g_phy => c_phy,
+ g_mts => c_mts,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_ref_clk => CLK,
+ dp_ref_rst => ddr_ref_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ dp_out_clk => dp_clk,
+ dp_out_rst => dp_rst,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ ser_term_ctrl_out => OPEN,
+ par_term_ctrl_out => OPEN,
+
+ ser_term_ctrl_in => OPEN,
+ par_term_ctrl_in => OPEN,
+
+ phy_in => MB_I_in,
+ phy_io => MB_I_io,
+ phy_ou => MB_I_ou
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
index d0e39f72ac..607e008d9f 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
@@ -26,13 +26,13 @@
library IEEE, tech_ddr_lib, common_lib, unb1_board_lib, i2c_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity tb_unb1_ddr3_transpose is
end tb_unb1_ddr3_transpose;
@@ -75,7 +75,7 @@ architecture tb of tb_unb1_ddr3_transpose is
signal sens_scl : std_logic;
signal sens_sda : std_logic;
- -- Signals to interface with the DDR3 memory model.
+ -- Signals to interface with the DDR3 memory model.
signal phy_in : t_tech_ddr3_phy_in;
signal phy_io : t_tech_ddr3_phy_io;
signal phy_ou : t_tech_ddr3_phy_ou;
@@ -157,48 +157,48 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
-- DDR3 Model
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_tech_ddr
- )
- port map (
- -- DDR3 PHY interface
- mem3_in => phy_ou,
- mem3_io => phy_io
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr
+ )
+ port map (
+ -- DDR3 PHY interface
+ mem3_in => phy_ou,
+ mem3_io => phy_io
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index ef7d86f390..3be2fb96ad 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_fn_terminal_db is
generic (
@@ -108,7 +108,7 @@ end mmm_unb1_fn_terminal_db;
architecture str of mmm_unb1_fn_terminal_db is
- -- Simulation
+ -- Simulation
constant c_mm_clk_period : time := 100 ps;
constant c_tse_clk_period : time := 8 ns;
@@ -157,37 +157,37 @@ begin
eth1g_mm_rst <= '1', '0' after c_tse_clk_period * 5;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_reg_tr_nonbonded : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
- port map(mm_rst, i_mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+ port map(mm_rst, i_mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
u_mm_file_reg_diagnostics : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
- port map(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+ port map(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
u_mm_file_ram_diag_data_buf_mesh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_MESH")
- port map(mm_rst, i_mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso);
+ port map(mm_rst, i_mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso);
u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -212,10 +212,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -234,139 +234,139 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_fn_terminal_db
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_mesh
- coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_mesh
- coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buffer
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer_mesh
- coe_address_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer_mesh => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer_mesh => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- in_port_to_the_pio_pps => pin_pps,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_mesh
+ coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_mesh
+ coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buffer
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer_mesh
+ coe_address_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer_mesh => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer_mesh => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ in_port_to_the_pio_pps => pin_pps,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
index 08fd646a24..dd25e17788 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -124,13 +124,13 @@
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_fn_terminal_db is
@@ -241,7 +241,7 @@ architecture str of node_unb1_fn_terminal_db is
signal rx_usr_siso_arr : t_dp_siso_arr(g_usr_nof_streams - 1 downto 0);
signal rx_usr_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Data buffer
-----------------------------------------------------------------------------
signal db_in_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
@@ -254,67 +254,67 @@ begin
-----------------------------------------------------------------------------
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_fn,
- g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_usr_nof_streams_per_bus,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
- g_tx_input_use_fifo => false, -- no user Tx
- -- Rx
- g_use_rx => true, -- user Rx must be TRUE for DB in FN,
- g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
-
- -- Mesh interface level (4 nodes)(4 lanes)
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr, -- Tx
- rx_serial_2arr => rx_serial_2arr, -- Rx
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_fn,
+ g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_usr_nof_streams_per_bus,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
+ g_tx_input_use_fifo => false, -- no user Tx
+ -- Rx
+ g_use_rx => true, -- user Rx must be TRUE for DB in FN,
+ g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
+
+ -- Mesh interface level (4 nodes)(4 lanes)
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr, -- Tx
+ rx_serial_2arr => rx_serial_2arr, -- Rx
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- Forward the received streams, rewire for single or multi UniBoard use
@@ -350,51 +350,51 @@ begin
gen_align : if g_use_bsn_align = true generate
u_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => g_usr_block_len,
- g_nof_input => g_usr_nof_streams,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => c_burst_bsn_latency,
- g_bsn_request_pipeline => c_bsn_request_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => rx_usr_siso_arr,
- snk_in_arr => rx_usr_sosi_arr,
- -- ST source
- src_in_arr => dp_out_siso_arr,
- src_out_arr => db_in_sosi_arr,
- -- MM
- in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr => (others => '1') -- default all user inputs are enabled
- );
+ generic map (
+ g_block_size => g_usr_block_len,
+ g_nof_input => g_usr_nof_streams,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => c_burst_bsn_latency,
+ g_bsn_request_pipeline => c_bsn_request_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => rx_usr_siso_arr,
+ snk_in_arr => rx_usr_sosi_arr,
+ -- ST source
+ src_in_arr => dp_out_siso_arr,
+ src_out_arr => db_in_sosi_arr,
+ -- MM
+ in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_arr => (others => '1') -- default all user inputs are enabled
+ );
u_bsn_monitor_align : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
- g_cross_clock_domain => true,
- g_sync_timeout => g_mesh_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => db_in_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_mesh_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => db_in_sosi_arr(0 downto 0)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -407,27 +407,27 @@ begin
gen_data_buf : if g_use_data_buf = true generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_usr_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => db_in_sosi_arr(0).sync,
- in_sosi_arr => db_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_usr_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => db_in_sosi_arr(0).sync,
+ in_sosi_arr => db_in_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
index fc36990364..c9501bb0e3 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity unb1_fn_terminal_db is
generic (
@@ -47,7 +47,7 @@ entity unb1_fn_terminal_db is
g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -176,204 +176,204 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
- pin_pps => pin_pps,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+ pin_pps => pin_pps,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_fn_terminal_db
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
-
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
- pin_pps => pin_pps,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- . bsn_monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
- );
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+ pin_pps => pin_pps,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+
+ );
-----------------------------------------------------------------------------
-- Node functioon: Terminals and data buffer
-----------------------------------------------------------------------------
u_node_unb1_fn_terminal_db : entity unb1_board_lib.node_unb1_fn_terminal_db
- generic map(
- g_multi_unb => g_rev_multi_unb,
- -- Terminals interface
- g_use_mesh => c_use_mesh,
- g_mesh_mon_select => c_mesh_mon_select,
- g_mesh_mon_nof_words => c_mesh_mon_nof_words,
- g_mesh_mon_use_sync => c_mesh_mon_use_sync,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- cal_clk => cal_clk,
-
- chip_id => this_chip_id,
-
- -- MM interface
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- -- . bsn_monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Mesh interface
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr
- );
+ generic map(
+ g_multi_unb => g_rev_multi_unb,
+ -- Terminals interface
+ g_use_mesh => c_use_mesh,
+ g_mesh_mon_select => c_mesh_mon_select,
+ g_mesh_mon_nof_words => c_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => c_mesh_mon_use_sync,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ cal_clk => cal_clk,
+
+ chip_id => this_chip_id,
+
+ -- MM interface
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Mesh interface
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr
+ );
-----------------------------------------------------------------------------
-- Mesh I/O
@@ -384,23 +384,23 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
end;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index 759135578c..5ecf664119 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -73,17 +73,17 @@
--
library IEEE, common_lib, unb_common_lib, bn_terminal_bg_lib, mm_lib, bf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb_common_lib.unb_common_pkg.all;
-use unb_common_lib.tb_unb_common_pkg.all;
-use bf_lib.bf_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use unb_common_lib.tb_unb_common_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
entity tb_mmf_node_fn_terminal_db is
generic (
@@ -97,7 +97,7 @@ architecture tb of tb_mmf_node_fn_terminal_db is
constant c_sim : boolean := true;
constant c_use_back : boolean := sel_a_b(g_unb_sys.nof_unb = 4, true, false); -- To interconnect multiple boards via the backplane when g_unb_sys.nof_unb=4 else when g_unb_sys.nof_unb=1
- -- this loops back each back node's BN_BI_TX to BN_BI_RX.
+ -- this loops back each back node's BN_BI_TX to BN_BI_RX.
constant c_ena_mesh_reorder : boolean := true;
constant c_mesh_use_bidir : boolean := false;
constant c_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
@@ -231,10 +231,10 @@ begin
-- PORT MAP(mm_rst, mm_clk, bn_reg_diagnostics_back_mosi_2arr(UNB)(BN), bn_reg_diagnostics_back_miso_2arr(UNB)(BN) );
u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, bn_reg_diag_bg_mosi_2arr(UNB)(BN), bn_reg_diag_bg_miso_2arr(UNB)(BN) );
+ port map(mm_rst, mm_clk, bn_reg_diag_bg_mosi_2arr(UNB)(BN), bn_reg_diag_bg_miso_2arr(UNB)(BN) );
u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, bn_ram_diag_bg_mosi_2arr(UNB)(BN), bn_ram_diag_bg_miso_2arr(UNB)(BN) );
+ port map(mm_rst, mm_clk, bn_ram_diag_bg_mosi_2arr(UNB)(BN), bn_ram_diag_bg_miso_2arr(UNB)(BN) );
--u_mm_file_reg_tr_nonbonded_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_TR_NONBONDED_MESH")
-- PORT MAP(mm_rst, mm_clk, bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN), bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN) );
@@ -255,58 +255,58 @@ begin
-- bn_terminal_bg: Node function: block generator & terminals
----------------------------------------------------------------------------
u_node_bn_terminal_bg : entity bn_terminal_bg_lib.node_bn_terminal_bg
- generic map(
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- g_use_back => c_use_back,
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_bidir,
- g_mesh_ena_reorder => c_ena_mesh_reorder
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_CLK,
- tr_back_clk => tr_CLK,
- cal_clk => cal_rec_clk,
-
- chip_id => TO_UVEC(BN + 4, c_unb_nof_chip_w), -- BN chip ID 4,5,6,7
- bck_id => TO_UVEC(UNB, c_unb_nof_uniboard_w), -- Backplane ID 0,1,2,3
-
- -- MM interface
- -- . block generator
- reg_diag_bg_mosi => bn_reg_diag_bg_mosi_2arr(UNB)(BN),
- reg_diag_bg_miso => bn_reg_diag_bg_miso_2arr(UNB)(BN),
- ram_diag_bg_mosi => bn_ram_diag_bg_mosi_2arr(UNB)(BN),
- ram_diag_bg_miso => bn_ram_diag_bg_miso_2arr(UNB)(BN),
- -- . tr_nonbonded mesh
- reg_mesh_tr_nonbonded_mosi => bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN),
- reg_mesh_tr_nonbonded_miso => bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN),
- reg_mesh_diagnostics_mosi => bn_reg_diagnostics_mesh_mosi_2arr(UNB)(BN),
- reg_mesh_diagnostics_miso => bn_reg_diagnostics_mesh_miso_2arr(UNB)(BN),
- -- . tr_nonbonded back
- reg_back_tr_nonbonded_mosi => bn_reg_tr_nonbonded_back_mosi_2arr(UNB)(BN),
- reg_back_tr_nonbonded_miso => bn_reg_tr_nonbonded_back_miso_2arr(UNB)(BN),
- reg_back_diagnostics_mosi => bn_reg_diagnostics_back_mosi_2arr(UNB)(BN),
- reg_back_diagnostics_miso => bn_reg_diagnostics_back_miso_2arr(UNB)(BN),
- -- . diag_data_buffer mesh
- ram_mesh_diag_data_buf_mosi => bn_ram_diag_data_buf_mesh_mosi_2arr(UNB)(BN),
- ram_mesh_diag_data_buf_miso => bn_ram_diag_data_buf_mesh_miso_2arr(UNB)(BN),
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- mesh_tx_serial_2arr => bn_out_mesh_serial_4arr(UNB)(BN),
- mesh_rx_serial_2arr => bn_in_mesh_serial_4arr(UNB)(BN),
-
- -- Back interface level
- -- . Serial (tr_nonbonded)
- back_tx_serial_2arr => bn_out_back_serial_4arr(UNB)(BN),
- back_rx_serial_2arr => bn_in_back_serial_4arr(UNB)(BN)
- );
+ generic map(
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ g_use_back => c_use_back,
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_bidir,
+ g_mesh_ena_reorder => c_ena_mesh_reorder
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_CLK,
+ tr_back_clk => tr_CLK,
+ cal_clk => cal_rec_clk,
+
+ chip_id => TO_UVEC(BN + 4, c_unb_nof_chip_w), -- BN chip ID 4,5,6,7
+ bck_id => TO_UVEC(UNB, c_unb_nof_uniboard_w), -- Backplane ID 0,1,2,3
+
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi => bn_reg_diag_bg_mosi_2arr(UNB)(BN),
+ reg_diag_bg_miso => bn_reg_diag_bg_miso_2arr(UNB)(BN),
+ ram_diag_bg_mosi => bn_ram_diag_bg_mosi_2arr(UNB)(BN),
+ ram_diag_bg_miso => bn_ram_diag_bg_miso_2arr(UNB)(BN),
+ -- . tr_nonbonded mesh
+ reg_mesh_tr_nonbonded_mosi => bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN),
+ reg_mesh_tr_nonbonded_miso => bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN),
+ reg_mesh_diagnostics_mosi => bn_reg_diagnostics_mesh_mosi_2arr(UNB)(BN),
+ reg_mesh_diagnostics_miso => bn_reg_diagnostics_mesh_miso_2arr(UNB)(BN),
+ -- . tr_nonbonded back
+ reg_back_tr_nonbonded_mosi => bn_reg_tr_nonbonded_back_mosi_2arr(UNB)(BN),
+ reg_back_tr_nonbonded_miso => bn_reg_tr_nonbonded_back_miso_2arr(UNB)(BN),
+ reg_back_diagnostics_mosi => bn_reg_diagnostics_back_mosi_2arr(UNB)(BN),
+ reg_back_diagnostics_miso => bn_reg_diagnostics_back_miso_2arr(UNB)(BN),
+ -- . diag_data_buffer mesh
+ ram_mesh_diag_data_buf_mosi => bn_ram_diag_data_buf_mesh_mosi_2arr(UNB)(BN),
+ ram_mesh_diag_data_buf_miso => bn_ram_diag_data_buf_mesh_miso_2arr(UNB)(BN),
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => bn_out_mesh_serial_4arr(UNB)(BN),
+ mesh_rx_serial_2arr => bn_in_mesh_serial_4arr(UNB)(BN),
+
+ -- Back interface level
+ -- . Serial (tr_nonbonded)
+ back_tx_serial_2arr => bn_out_back_serial_4arr(UNB)(BN),
+ back_rx_serial_2arr => bn_in_back_serial_4arr(UNB)(BN)
+ );
end generate;
@@ -321,10 +321,10 @@ begin
-- PORT MAP(mm_rst, mm_clk, fn_reg_diagnostics_mosi_2arr(UNB)(FN), fn_reg_diagnostics_miso_2arr(UNB)(FN) );
u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, fn_ram_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_diag_data_buf_miso_2arr(UNB)(FN) );
+ port map(mm_rst, mm_clk, fn_ram_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_diag_data_buf_miso_2arr(UNB)(FN) );
u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, fn_reg_diag_data_buf_mosi_2arr(UNB)(FN), fn_reg_diag_data_buf_miso_2arr(UNB)(FN) );
+ port map(mm_rst, mm_clk, fn_reg_diag_data_buf_mosi_2arr(UNB)(FN), fn_reg_diag_data_buf_miso_2arr(UNB)(FN) );
--u_mm_file_ram_diag_data_buf_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, FN, "FN") & "RAM_DIAG_DATA_BUFFER_MESH")
-- PORT MAP(mm_rst, mm_clk, fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN) );
@@ -339,52 +339,52 @@ begin
-- Node function: Terminals and data buffer
-----------------------------------------------------------------------------
u_node_fn_terminal_db : entity work.node_unb1_fn_terminal_db
- generic map(
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- g_use_bsn_align => true,
- g_use_data_buf => true,
- -- Terminals interface
- g_multi_unb => sel_a_b(g_unb_sys.nof_unb > 1, true, false),
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_tx => c_mesh_use_bidir,
- g_mesh_ena_reorder => c_ena_mesh_reorder
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_clk,
- cal_clk => cal_rec_clk,
-
- chip_id => TO_UVEC(FN, c_unb_nof_chip_w), -- FN chip ID 0,1,2,3
-
- -- MM interface
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => fn_reg_tr_nonbonded_mosi_2arr(UNB)(FN),
- reg_tr_nonbonded_miso => fn_reg_tr_nonbonded_miso_2arr(UNB)(FN),
- reg_diagnostics_mosi => fn_reg_diagnostics_mosi_2arr(UNB)(FN),
- reg_diagnostics_miso => fn_reg_diagnostics_miso_2arr(UNB)(FN),
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => fn_ram_diag_data_buf_mosi_2arr(UNB)(FN),
- ram_diag_data_buf_miso => fn_ram_diag_data_buf_miso_2arr(UNB)(FN),
- reg_diag_data_buf_mosi => fn_reg_diag_data_buf_mosi_2arr(UNB)(FN),
- reg_diag_data_buf_miso => fn_reg_diag_data_buf_miso_2arr(UNB)(FN),
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN),
- ram_mesh_diag_data_buf_miso => fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN),
- -- . bsn_monitor
- reg_bsn_monitor_mosi => fn_reg_bsn_monitor_mosi_2arr(UNB)(FN),
- reg_bsn_monitor_miso => fn_reg_bsn_monitor_miso_2arr(UNB)(FN),
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN), -- Tx support for diagnostics
- rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN) -- Rx
- );
+ generic map(
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ g_use_bsn_align => true,
+ g_use_data_buf => true,
+ -- Terminals interface
+ g_multi_unb => sel_a_b(g_unb_sys.nof_unb > 1, true, false),
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_tx => c_mesh_use_bidir,
+ g_mesh_ena_reorder => c_ena_mesh_reorder
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_clk,
+ cal_clk => cal_rec_clk,
+
+ chip_id => TO_UVEC(FN, c_unb_nof_chip_w), -- FN chip ID 0,1,2,3
+
+ -- MM interface
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => fn_reg_tr_nonbonded_mosi_2arr(UNB)(FN),
+ reg_tr_nonbonded_miso => fn_reg_tr_nonbonded_miso_2arr(UNB)(FN),
+ reg_diagnostics_mosi => fn_reg_diagnostics_mosi_2arr(UNB)(FN),
+ reg_diagnostics_miso => fn_reg_diagnostics_miso_2arr(UNB)(FN),
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => fn_ram_diag_data_buf_mosi_2arr(UNB)(FN),
+ ram_diag_data_buf_miso => fn_ram_diag_data_buf_miso_2arr(UNB)(FN),
+ reg_diag_data_buf_mosi => fn_reg_diag_data_buf_mosi_2arr(UNB)(FN),
+ reg_diag_data_buf_miso => fn_reg_diag_data_buf_miso_2arr(UNB)(FN),
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN),
+ ram_mesh_diag_data_buf_miso => fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN),
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => fn_reg_bsn_monitor_mosi_2arr(UNB)(FN),
+ reg_bsn_monitor_miso => fn_reg_bsn_monitor_miso_2arr(UNB)(FN),
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN), -- Tx support for diagnostics
+ rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN) -- Rx
+ );
end generate;
@@ -404,36 +404,36 @@ begin
-- Mesh model
gen_mesh : if g_unb_sys.nof_bn > 1 or g_unb_sys.nof_fn > 1 generate
u_mesh_model_serial : entity unb_common_lib.unb_mesh_model_sl
- generic map(
- g_reorder => c_ena_mesh_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_out_mesh_serial_4arr(UNB),
- bn_rx_sl_3arr => bn_in_mesh_serial_4arr(UNB),
-
- -- BN to FN
- bn_tx_sl_3arr => bn_out_mesh_serial_4arr(UNB),
- fn_rx_sl_3arr => fn_in_mesh_serial_4arr(UNB)
- );
+ generic map(
+ g_reorder => c_ena_mesh_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_out_mesh_serial_4arr(UNB),
+ bn_rx_sl_3arr => bn_in_mesh_serial_4arr(UNB),
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_out_mesh_serial_4arr(UNB),
+ fn_rx_sl_3arr => fn_in_mesh_serial_4arr(UNB)
+ );
end generate;
end generate;
- ------------------------------------------------------------------------------
- -- Instantiate a backplane model that interconnects all UniBoards...
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- Instantiate a backplane model that interconnects all UniBoards...
+ ------------------------------------------------------------------------------
gen_backplane : if c_use_back = true generate
gen_model : entity unb_common_lib.unb_back_model_sl
- port map (
- backplane_in_serial_4arr => bn_out_back_serial_4arr,
- backplane_out_serial_4arr => bn_in_back_serial_4arr
- );
+ port map (
+ backplane_in_serial_4arr => bn_out_back_serial_4arr,
+ backplane_out_serial_4arr => bn_in_back_serial_4arr
+ );
end generate;
- ------------------------------------------------------------------------------
- -- ...or loop back serial TX to RX in case of a single UniBoard.
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- ...or loop back serial TX to RX in case of a single UniBoard.
+ ------------------------------------------------------------------------------
no_backplane: if c_use_back = false generate
bn_in_back_serial_4arr <= bn_out_back_serial_4arr;
end generate;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index 5299c66504..558a839d12 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb1_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb1_heater_pkg.all;
entity mmm_unb1_heater is
@@ -133,30 +133,30 @@ begin
eth1g_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, i_mm_clk, reg_heater_mosi, reg_heater_miso );
+ port map(mm_rst, i_mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -171,150 +171,150 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb1_heater
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- reg_heater
- reg_heater_clk_export => OPEN,
- reg_heater_reset_export => OPEN,
- reg_heater_address_export => reg_heater_mosi.address(3 downto 0),
- reg_heater_read_export => reg_heater_mosi.rd,
- reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
- reg_heater_write_export => reg_heater_mosi.wr,
- reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- reg_heater
+ reg_heater_clk_export => OPEN,
+ reg_heater_reset_export => OPEN,
+ reg_heater_address_export => reg_heater_mosi.address(3 downto 0),
+ reg_heater_read_export => reg_heater_mosi.rd,
+ reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
+ reg_heater_write_export => reg_heater_mosi.wr,
+ reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
index 1e491f25b3..baf53f5d5a 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
@@ -20,131 +20,131 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb1_heater is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(3 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_reset_export : out std_logic -- export
- );
- end component qsys_unb1_heater;
+ component qsys_unb1_heater is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ mm_clk : out std_logic; -- clk
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ coe_read_export_from_the_reg_remu : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_reset_export : out std_logic -- export
+ );
+ end component qsys_unb1_heater;
end qsys_unb1_heater_pkg;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
index 0012749a73..2d16e8b7be 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb1_heater is
generic (
@@ -152,202 +152,202 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- epcs_clk => epcs_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ epcs_clk => epcs_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- epcs_clk => epcs_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ epcs_clk => epcs_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- g_nof_mac4 => 315
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_mac4 => 315
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
index 35c916b8e1..5e1db9b1f0 100644
--- a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_heater is
- generic (
- g_design_name : string := "unb1_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_heater;
architecture tb of tb_unb1_heater is
@@ -166,37 +166,37 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
index 6d6d6ce813..06d8eecd5b 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_mm_arbiter is
@@ -35,8 +35,8 @@ end tb_unb1_minimal_mm_arbiter;
architecture tb of tb_unb1_minimal_mm_arbiter is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_mm_arbiter",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_mm_arbiter",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
index 59b341b2ad..7e965d2a6e 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_mm_arbiter is
generic (
@@ -65,38 +65,38 @@ architecture str of unb1_minimal_mm_arbiter is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
index cdf60e088a..90f2a8a5ea 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_qsys is
@@ -35,8 +35,8 @@ end tb_unb1_minimal_qsys;
architecture tb of tb_unb1_minimal_qsys is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_qsys",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_qsys",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
index e406b3e8a3..473ba0a2f4 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
@@ -44,13 +44,13 @@
-- > run 100 us
--
library IEEE, common_lib, mm_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity tb_unb1_minimal_qsys_stimuli is
end tb_unb1_minimal_qsys_stimuli;
@@ -190,38 +190,38 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
index 031c28162d..29753d818d 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_qsys is
generic (
@@ -65,38 +65,38 @@ architecture str of unb1_minimal_qsys is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index b0b46e9cec..24120bc1dd 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_wo_pll_unb1_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_wo_pll_unb1_minimal_pkg.all;
entity mmm_unb1_minimal_qsys_wo_pll is
@@ -127,27 +127,27 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
@@ -195,133 +195,133 @@ begin
mm_rst_n <= not (mm_rst);
u_qsys : qsys_wo_pll_unb1_minimal
- port map (
- clk_0 => mm_clk,
- reset_n => mm_rst_n,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+ clk_0 => mm_clk,
+ reset_n => mm_rst_n,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
index f0f3a2a7c7..14bdb47d0b 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
@@ -20,119 +20,119 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_wo_pll_unb1_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_wo_pll_unb1_minimal is
+ component qsys_wo_pll_unb1_minimal is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic -- export
- );
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_remu : out std_logic -- export
+ );
- end component qsys_wo_pll_unb1_minimal;
+ end component qsys_wo_pll_unb1_minimal;
end qsys_wo_pll_unb1_minimal_pkg;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
index 0f750b9537..e9c24288d5 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_minimal_qsys_wo_pll is
- generic (
- g_design_name : string := "unb1_minimal_qsys_wo_pll";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_minimal_qsys_wo_pll";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_minimal_qsys_wo_pll;
architecture tb of tb_unb1_minimal_qsys_wo_pll is
@@ -166,37 +166,37 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
index d11fdcc51e..5ef80a8922 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_qsys_wo_pll is
generic (
@@ -146,190 +146,190 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_sim_flash_model => false,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_freq => c_unb1_board_ext_clk_freq_200M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_flash_model => false,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_freq => c_unb1_board_ext_clk_freq_200M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_minimal_qsys_wo_pll
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
-
- -----------------------------------------------------------------------------
- -- Node function
- -----------------------------------------------------------------------------
- -- Insert node_[design_name] here
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
+
+-----------------------------------------------------------------------------
+-- Node function
+-----------------------------------------------------------------------------
+-- Insert node_[design_name] here
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
index b7c25399bf..3df70dbc06 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_sopc is
@@ -35,8 +35,8 @@ end tb_unb1_minimal_sopc;
architecture tb of tb_unb1_minimal_sopc is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_sopc",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_sopc",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
index 5b2ca7c3f7..61a31c9c42 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_sopc is
generic (
@@ -65,37 +65,37 @@ architecture str of unb1_minimal_sopc is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index ba4b697c72..5645957223 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb1_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb1_minimal_pkg.all;
entity mmm_unb1_minimal is
@@ -162,27 +162,27 @@ begin
eth1g_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -197,280 +197,280 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false and g_use_sopc = true generate
u_sopc : entity work.sopc_unb1_minimal
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
gen_qsys : if g_sim = false and g_use_qsys = true generate
u_qsys : qsys_unb1_minimal
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
@@ -483,77 +483,77 @@ begin
-- MM master: a minimal QSYS (for now)
-----------------------------------------------------------------------------
u_qsys_unb1_minimal_mm_arbiter : qsys_unb1_minimal_mm_arbiter
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: Entangled within unb_osy code, so still required for now.
- pio_system_info_clk_export => OPEN,
- pio_system_info_reset_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- avs_common_mm export to MM arbiter
- to_mm_arbiter_clk_export => OPEN,
- to_mm_arbiter_reset_export => OPEN,
- to_mm_arbiter_address_export => master_mosi.address(11 - 1 downto 0),
- to_mm_arbiter_read_export => master_mosi.rd,
- to_mm_arbiter_readdata_export => master_miso.rddata(c_word_w - 1 downto 0),
- to_mm_arbiter_write_export => master_mosi.wr,
- to_mm_arbiter_writedata_export => master_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: Entangled within unb_osy code, so still required for now.
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- avs_common_mm export to MM arbiter
+ to_mm_arbiter_clk_export => OPEN,
+ to_mm_arbiter_reset_export => OPEN,
+ to_mm_arbiter_address_export => master_mosi.address(11 - 1 downto 0),
+ to_mm_arbiter_read_export => master_mosi.rd,
+ to_mm_arbiter_readdata_export => master_miso.rddata(c_word_w - 1 downto 0),
+ to_mm_arbiter_write_export => master_mosi.wr,
+ to_mm_arbiter_writedata_export => master_mosi.wrdata(c_word_w - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- MM arbiter
-----------------------------------------------------------------------------
u_mm_arbiter : entity mm_lib.mm_arbiter
- generic map (
- g_nof_slaves => c_nof_slaves,
- g_slave_base_arr => c_slave_base_arr,
- g_slave_high_arr => c_slave_high_arr
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => mm_rst,
-
- master_mosi => master_mosi,
- master_miso => master_miso,
-
- slave_mosi_arr => slave_mosi_arr,
- slave_miso_arr => slave_miso_arr
- );
+ generic map (
+ g_nof_slaves => c_nof_slaves,
+ g_slave_base_arr => c_slave_base_arr,
+ g_slave_high_arr => c_slave_high_arr
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => mm_rst,
+
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+
+ slave_mosi_arr => slave_mosi_arr,
+ slave_miso_arr => slave_miso_arr
+ );
-----------------------------------------------------------------------------
-- Connect slave array to individually names MM buses
@@ -565,7 +565,7 @@ begin
slave_miso_arr(1) <= rom_unb_system_info_miso;
-- pio_system_info; still needed within QSYS, so not connected here.
--- reg_unb_system_info_mosi <= slave_mosi_arr(2);
+ -- reg_unb_system_info_mosi <= slave_mosi_arr(2);
slave_miso_arr(2) <= c_mem_miso_rst;
reg_ppsh_mosi <= slave_mosi_arr(3);
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
index 0a216a48d0..53f3743db6 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
@@ -20,175 +20,175 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb1_minimal is
+ component qsys_unb1_minimal is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- coe_read_export_from_the_reg_remu : out std_logic -- export
- );
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ mm_clk : out std_logic; -- clk
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ coe_read_export_from_the_reg_remu : out std_logic -- export
+ );
- end component qsys_unb1_minimal;
+ end component qsys_unb1_minimal;
- component qsys_unb1_minimal_mm_arbiter is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- mm_clk : out std_logic; -- clk
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- to_mm_arbiter_reset_export : out std_logic; -- export
- to_mm_arbiter_clk_export : out std_logic; -- export
- to_mm_arbiter_address_export : out std_logic_vector(10 downto 0); -- export
- to_mm_arbiter_write_export : out std_logic; -- export
- to_mm_arbiter_writedata_export : out std_logic_vector(31 downto 0); -- export
- to_mm_arbiter_read_export : out std_logic; -- export
- to_mm_arbiter_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb1_minimal_mm_arbiter;
+ component qsys_unb1_minimal_mm_arbiter is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ mm_clk : out std_logic; -- clk
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ to_mm_arbiter_reset_export : out std_logic; -- export
+ to_mm_arbiter_clk_export : out std_logic; -- export
+ to_mm_arbiter_address_export : out std_logic_vector(10 downto 0); -- export
+ to_mm_arbiter_write_export : out std_logic; -- export
+ to_mm_arbiter_writedata_export : out std_logic_vector(31 downto 0); -- export
+ to_mm_arbiter_read_export : out std_logic; -- export
+ to_mm_arbiter_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb1_minimal_mm_arbiter;
end qsys_unb1_minimal_pkg;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
index 7be378fdcb..5f147bf78e 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal is
generic (
@@ -148,191 +148,191 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_epcs_protect_addr_range => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- epcs_clk => epcs_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_epcs_protect_addr_range => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ epcs_clk => epcs_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_use_qsys => c_use_qsys,
- g_use_sopc => c_use_sopc
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- epcs_clk => epcs_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
-
- -----------------------------------------------------------------------------
- -- Node function
- -----------------------------------------------------------------------------
- -- Insert node_[design_name] here
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_use_qsys => c_use_qsys,
+ g_use_sopc => c_use_sopc
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ epcs_clk => epcs_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
+
+-----------------------------------------------------------------------------
+-- Node function
+-----------------------------------------------------------------------------
+-- Insert node_[design_name] here
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
index b63da7ebd3..882d2c6cc5 100644
--- a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_minimal is
- generic (
- g_design_name : string := "unb1_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_minimal;
architecture tb of tb_unb1_minimal is
@@ -166,37 +166,37 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 794e9af242..59a05d6a71 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -66,23 +66,23 @@
-- );
--
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_terminal_bg_mesh_db is
generic (
@@ -272,37 +272,37 @@ begin
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
+ port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
+ port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
u_mm_file_reg_diagnostics : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
- port map(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+ port map(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
u_mm_file_reg_tr_nonbonded : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
- port map(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+ port map(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
u_mm_file_ram_mesh_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_MESH_DIAG_DATA_BUF")
- port map(mm_rst, mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso );
+ port map(mm_rst, mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso );
u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
@@ -344,121 +344,121 @@ begin
u_qsys_unb1_terminal_bg_mesh_db : qsys_unb1_terminal_bg_mesh_db
port map(
- clk_in_clk => mm_clk,
- eth1g_irq_export => eth1g_reg_interrupt,
- eth1g_mm_clk_export => OPEN,
- eth1g_mm_rst_export => eth1g_mm_rst,
- eth1g_ram_address_export => eth1g_ram_mosi.address(9 downto 0),
- eth1g_ram_read_export => eth1g_ram_mosi.rd,
- eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- eth1g_ram_write_export => eth1g_ram_mosi.wr,
- eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- eth1g_reg_address_export => eth1g_reg_mosi.address(3 downto 0),
- eth1g_reg_read_export => eth1g_reg_mosi.rd,
- eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- eth1g_reg_write_export => eth1g_reg_mosi.wr,
- eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- eth1g_tse_address_export => eth1g_tse_mosi.address(9 downto 0),
- eth1g_tse_read_export => eth1g_tse_mosi.rd,
- eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- eth1g_tse_write_export => eth1g_tse_mosi.wr,
- eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- out_port_from_the_pio_debug_wave => OPEN,
- out_port_from_the_pio_wdi => pout_wdi,
- pio_pps_address_export => reg_ppsh_mosi.address(0),
- pio_pps_clk_export => OPEN,
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- pio_pps_reset_export => OPEN,
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_address_export => reg_unb_system_info_mosi.address(4 downto 0),
- pio_system_info_clk_export => OPEN,
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- pio_system_info_reset_export => OPEN,
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_address_export => ram_diag_bg_mosi.address(10 downto 0),
- ram_diag_bg_clk_export => OPEN,
- ram_diag_bg_read_export => ram_diag_bg_mosi.rd,
- ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- ram_diag_bg_reset_export => OPEN,
- ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
- ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buf_address_export => ram_diag_data_buf_mosi.address(13 downto 0),
- ram_diag_data_buf_clk_export => OPEN,
- ram_diag_data_buf_read_export => ram_diag_data_buf_mosi.rd,
- ram_diag_data_buf_readdata_export => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- ram_diag_data_buf_reset_export => OPEN,
- ram_diag_data_buf_write_export => ram_diag_data_buf_mosi.wr,
- ram_diag_data_buf_writedata_export => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
- ram_mesh_diag_data_buf_address_export => ram_mesh_diag_data_buf_mosi.address(13 downto 0),
- ram_mesh_diag_data_buf_clk_export => OPEN,
- ram_mesh_diag_data_buf_read_export => ram_mesh_diag_data_buf_mosi.rd,
- ram_mesh_diag_data_buf_readdata_export => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- ram_mesh_diag_data_buf_reset_export => OPEN,
- ram_mesh_diag_data_buf_write_export => ram_mesh_diag_data_buf_mosi.wr,
- ram_mesh_diag_data_buf_writedata_export => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(6 downto 0),
- reg_bsn_monitor_clk_export => OPEN,
- reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
- reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_reset_export => OPEN,
- reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
- reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_address_export => reg_diag_bg_mosi.address(2 downto 0),
- reg_diag_bg_clk_export => OPEN,
- reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
- reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_bg_reset_export => OPEN,
- reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
- reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buf_address_export => reg_diag_data_buf_mosi.address(0),
- reg_diag_data_buf_clk_export => OPEN,
- reg_diag_data_buf_read_export => reg_diag_data_buf_mosi.rd,
- reg_diag_data_buf_readdata_export => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_data_buf_reset_export => OPEN,
- reg_diag_data_buf_write_export => reg_diag_data_buf_mosi.wr,
- reg_diag_data_buf_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diagnostics_address_export => reg_diagnostics_mosi.address(5 downto 0),
- reg_diagnostics_clk_export => OPEN,
- reg_diagnostics_read_export => reg_diagnostics_mosi.rd,
- reg_diagnostics_readdata_export => reg_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- reg_diagnostics_reset_export => OPEN,
- reg_diagnostics_write_export => reg_diagnostics_mosi.wr,
- reg_diagnostics_writedata_export => reg_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_nonbonded_address_export => reg_tr_nonbonded_mosi.address(3 downto 0),
- reg_tr_nonbonded_clk_export => OPEN,
- reg_tr_nonbonded_read_export => reg_tr_nonbonded_mosi.rd,
- reg_tr_nonbonded_readdata_export => reg_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_nonbonded_reset_export => OPEN,
- reg_tr_nonbonded_write_export => reg_tr_nonbonded_mosi.wr,
- reg_tr_nonbonded_writedata_export => reg_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(2 downto 0),
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_address_export => reg_wdi_mosi.address(0),
- reg_wdi_clk_export => OPEN,
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- reg_wdi_reset_export => OPEN,
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reset_in_reset_n => mm_rst_n,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
- rom_system_info_clk_export => OPEN,
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- rom_system_info_reset_export => OPEN,
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ clk_in_clk => mm_clk,
+ eth1g_irq_export => eth1g_reg_interrupt,
+ eth1g_mm_clk_export => OPEN,
+ eth1g_mm_rst_export => eth1g_mm_rst,
+ eth1g_ram_address_export => eth1g_ram_mosi.address(9 downto 0),
+ eth1g_ram_read_export => eth1g_ram_mosi.rd,
+ eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ eth1g_ram_write_export => eth1g_ram_mosi.wr,
+ eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ eth1g_reg_address_export => eth1g_reg_mosi.address(3 downto 0),
+ eth1g_reg_read_export => eth1g_reg_mosi.rd,
+ eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ eth1g_reg_write_export => eth1g_reg_mosi.wr,
+ eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ eth1g_tse_address_export => eth1g_tse_mosi.address(9 downto 0),
+ eth1g_tse_read_export => eth1g_tse_mosi.rd,
+ eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ eth1g_tse_write_export => eth1g_tse_mosi.wr,
+ eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ out_port_from_the_pio_debug_wave => OPEN,
+ out_port_from_the_pio_wdi => pout_wdi,
+ pio_pps_address_export => reg_ppsh_mosi.address(0),
+ pio_pps_clk_export => OPEN,
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ pio_pps_reset_export => OPEN,
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(4 downto 0),
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_address_export => ram_diag_bg_mosi.address(10 downto 0),
+ ram_diag_bg_clk_export => OPEN,
+ ram_diag_bg_read_export => ram_diag_bg_mosi.rd,
+ ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ ram_diag_bg_reset_export => OPEN,
+ ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
+ ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_address_export => ram_diag_data_buf_mosi.address(13 downto 0),
+ ram_diag_data_buf_clk_export => OPEN,
+ ram_diag_data_buf_read_export => ram_diag_data_buf_mosi.rd,
+ ram_diag_data_buf_readdata_export => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_reset_export => OPEN,
+ ram_diag_data_buf_write_export => ram_diag_data_buf_mosi.wr,
+ ram_diag_data_buf_writedata_export => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_mesh_diag_data_buf_address_export => ram_mesh_diag_data_buf_mosi.address(13 downto 0),
+ ram_mesh_diag_data_buf_clk_export => OPEN,
+ ram_mesh_diag_data_buf_read_export => ram_mesh_diag_data_buf_mosi.rd,
+ ram_mesh_diag_data_buf_readdata_export => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ ram_mesh_diag_data_buf_reset_export => OPEN,
+ ram_mesh_diag_data_buf_write_export => ram_mesh_diag_data_buf_mosi.wr,
+ ram_mesh_diag_data_buf_writedata_export => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(6 downto 0),
+ reg_bsn_monitor_clk_export => OPEN,
+ reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
+ reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_reset_export => OPEN,
+ reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
+ reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_address_export => reg_diag_bg_mosi.address(2 downto 0),
+ reg_diag_bg_clk_export => OPEN,
+ reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
+ reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_bg_reset_export => OPEN,
+ reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
+ reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_address_export => reg_diag_data_buf_mosi.address(0),
+ reg_diag_data_buf_clk_export => OPEN,
+ reg_diag_data_buf_read_export => reg_diag_data_buf_mosi.rd,
+ reg_diag_data_buf_readdata_export => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_reset_export => OPEN,
+ reg_diag_data_buf_write_export => reg_diag_data_buf_mosi.wr,
+ reg_diag_data_buf_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diagnostics_address_export => reg_diagnostics_mosi.address(5 downto 0),
+ reg_diagnostics_clk_export => OPEN,
+ reg_diagnostics_read_export => reg_diagnostics_mosi.rd,
+ reg_diagnostics_readdata_export => reg_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ reg_diagnostics_reset_export => OPEN,
+ reg_diagnostics_write_export => reg_diagnostics_mosi.wr,
+ reg_diagnostics_writedata_export => reg_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_nonbonded_address_export => reg_tr_nonbonded_mosi.address(3 downto 0),
+ reg_tr_nonbonded_clk_export => OPEN,
+ reg_tr_nonbonded_read_export => reg_tr_nonbonded_mosi.rd,
+ reg_tr_nonbonded_readdata_export => reg_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_nonbonded_reset_export => OPEN,
+ reg_tr_nonbonded_write_export => reg_tr_nonbonded_mosi.wr,
+ reg_tr_nonbonded_writedata_export => reg_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(2 downto 0),
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_address_export => reg_wdi_mosi.address(0),
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reset_in_reset_n => mm_rst_n,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
index 6c2d1dbc7b..5e015926b1 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
@@ -29,13 +29,13 @@
-- Some more remarks:
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_terminal_bg_mesh_db is
generic(
@@ -72,12 +72,12 @@ entity node_unb1_terminal_bg_mesh_db is
g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
-- Monitoring
g_mon_select : natural := 0; -- 0 = no SOSI data buffers monitor via MM
- -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
- -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
- -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
- -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
- -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
- -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
+ -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
+ -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
+ -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
+ -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
+ -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
+ -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
g_mon_nof_words : natural := 1024;
g_mon_use_sync : boolean := true;
-- UTH
@@ -210,40 +210,40 @@ begin
-- Block Generator
---------------------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- -- Generate configurations
- g_use_usr_input => c_use_usr_input,
- g_use_bg => g_use_bg,
- g_use_tx_seq => false,
- -- General
- g_nof_streams => c_bg_nof_streams,
- -- BG settings
- g_use_bg_buffer_ram => true,
- g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w,
- g_file_name_prefix => c_file_name_prefix,
- -- User input multiplexer option
- g_usr_bypass_xonoff => false
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
-
- -- ST interface
- usr_siso_arr => bg_snk_out_arr,
- usr_sosi_arr => bg_snk_in_arr,
- out_siso_arr => bg_src_in_arr,
- out_sosi_arr => bg_src_out_arr
- );
+ generic map(
+ -- Generate configurations
+ g_use_usr_input => c_use_usr_input,
+ g_use_bg => g_use_bg,
+ g_use_tx_seq => false,
+ -- General
+ g_nof_streams => c_bg_nof_streams,
+ -- BG settings
+ g_use_bg_buffer_ram => true,
+ g_buf_dat_w => c_nof_complex * c_in_dat_w,
+ g_buf_addr_w => c_bg_addr_w,
+ g_file_name_prefix => c_file_name_prefix,
+ -- User input multiplexer option
+ g_usr_bypass_xonoff => false
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+
+ -- ST interface
+ usr_siso_arr => bg_snk_out_arr,
+ usr_sosi_arr => bg_snk_in_arr,
+ out_siso_arr => bg_src_in_arr,
+ out_sosi_arr => bg_src_out_arr
+ );
---------------------------------------------------------------------------------------
-- From 1d to 2d array. Output BG to input Mesh
@@ -256,75 +256,75 @@ begin
end generate;
u_mesh_terminal : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map(
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => g_node_type,
- g_nof_bus => g_nof_bus,
- -- User
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- g_usr_nof_streams => g_usr_nof_streams,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- g_phy_gx_mbps => g_phy_gx_mbps,
- g_phy_rx_fifo_size => g_phy_rx_fifo_size,
- g_phy_ena_reorder => g_phy_ena_reorder,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
-
- -- Monitoring
- g_mon_select => g_mon_select,
- g_mon_nof_words => g_mon_nof_words,
- g_mon_use_sync => g_mon_use_sync,
-
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => bg_out_siso_2arr,
- tx_usr_sosi_2arr => bg_out_sosi_2arr, -- <== Data to the Mesh
- rx_usr_siso_2arr => rx_usr_i_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_i_sosi_2arr, -- ==> Data from the Mesh
-
- -- Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . monitor data buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => g_node_type,
+ g_nof_bus => g_nof_bus,
+ -- User
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ g_usr_nof_streams => g_usr_nof_streams,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ g_phy_gx_mbps => g_phy_gx_mbps,
+ g_phy_rx_fifo_size => g_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_phy_ena_reorder,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+
+ -- Monitoring
+ g_mon_select => g_mon_select,
+ g_mon_nof_words => g_mon_nof_words,
+ g_mon_use_sync => g_mon_use_sync,
+
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => bg_out_siso_2arr,
+ tx_usr_sosi_2arr => bg_out_sosi_2arr, -- <== Data to the Mesh
+ rx_usr_siso_2arr => rx_usr_i_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_i_sosi_2arr, -- ==> Data from the Mesh
+
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . monitor data buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- From 2d to 1d array. Input port to input BG.
@@ -341,25 +341,25 @@ begin
-----------------------------------------------------------------------------
gen_bsn_align : if g_use_bsn_align generate
u_dp_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => c_block_size,
- g_block_period => c_block_period,
- g_nof_input => c_bsn_align_nof_streams,
- g_xoff_timeout => c_bsn_align_xoff_timeout,
- g_sop_timeout => c_bsn_align_sop_timeout,
- g_bsn_latency => c_bsn_align_latency,
- g_bsn_request_pipeline => 2
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => bsn_align_snk_out_arr,
- snk_in_arr => bsn_align_snk_in_arr,
-
- src_in_arr => bsn_align_src_in_arr,
- src_out_arr => bsn_align_src_out_arr
- );
+ generic map (
+ g_block_size => c_block_size,
+ g_block_period => c_block_period,
+ g_nof_input => c_bsn_align_nof_streams,
+ g_xoff_timeout => c_bsn_align_xoff_timeout,
+ g_sop_timeout => c_bsn_align_sop_timeout,
+ g_bsn_latency => c_bsn_align_latency,
+ g_bsn_request_pipeline => 2
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => bsn_align_snk_out_arr,
+ snk_in_arr => bsn_align_snk_in_arr,
+
+ src_in_arr => bsn_align_src_in_arr,
+ src_out_arr => bsn_align_src_out_arr
+ );
end generate;
gen_no_bsn_align : if not(g_use_bsn_align) generate
@@ -371,49 +371,49 @@ begin
-- BSN monitors at the output of the BSN aligner
-----------------------------------------------------------------------------
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_bsn_mon_nof_streams,
- g_sync_timeout => c_bsn_sync_time_out,
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => bsn_mon_snk_out_arr,
- in_sosi_arr => bsn_mon_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_bsn_mon_nof_streams,
+ g_sync_timeout => c_bsn_sync_time_out,
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => bsn_mon_snk_out_arr,
+ in_sosi_arr => bsn_mon_snk_in_arr
+ );
bsn_mon_snk_in_arr <= bsn_align_src_out_arr(c_bsn_mon_nof_streams - 1 downto 0);
bsn_mon_snk_out_arr <= bsn_align_src_in_arr(c_bsn_mon_nof_streams - 1 downto 0);
gen_data_buf : if g_use_data_buf generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => c_db_nof_data,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => bsn_align_src_out_arr(0).sync,
- in_sosi_arr => bsn_align_src_out_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => c_db_nof_data,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => bsn_align_src_out_arr(0).sync,
+ in_sosi_arr => bsn_align_src_out_arr
+ );
end generate;
---------------------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
index 9202aa0cf7..d4f6ddd14b 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity unb1_terminal_bg_mesh_db is
generic (
@@ -47,7 +47,7 @@ entity unb1_terminal_bg_mesh_db is
g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -216,238 +216,238 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_sim_flash_model => not(g_sim),
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_sim_flash_model => not(g_sim),
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_inst_mmm_unb1_terminal_bg_mesh_db : entity work.mmm_unb1_terminal_bg_mesh_db
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- pout_wdi => pout_wdi,
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ pout_wdi => pout_wdi,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ );
-----------------------------------------------------------------------------
-- Node function: Terminals and data buffer
-----------------------------------------------------------------------------
u_terminal_mesh : entity work.node_unb1_terminal_bg_mesh_db
- generic map(
- g_sim => g_sim,
- g_sim_level => g_sim_level,
-
- -- BLOCK GENERATOR
- g_use_bg => c_use_bg,
-
- -- MESH TERMINAL
- -- System
- g_node_type => c_node_type,
- g_nof_bus => c_nof_bus,
- -- User
- g_usr_use_complex => c_usr_use_complex,
- g_usr_data_w => c_usr_data_w,
- g_usr_frame_len => c_usr_frame_len,
- g_usr_nof_streams => c_usr_nof_streams,
- -- Phy
- g_phy_nof_serial => c_phy_nof_serial,
- g_phy_gx_mbps => c_phy_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => c_phy_ena_reorder,
- -- Tx
- g_use_tx => c_use_tx,
- g_tx_input_use_fifo => c_tx_input_use_fifo,
- g_tx_input_fifo_size => c_tx_input_fifo_size,
- g_tx_input_fifo_fill => c_tx_input_fifo_fill,
- -- Rx
- g_use_rx => c_use_rx,
- g_rx_output_use_fifo => c_rx_output_use_fifo,
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => c_mon_select,
- g_mon_nof_words => c_mon_nof_words,
- g_mon_use_sync => c_mon_use_sync,
- -- UTH
- g_uth_len_max => c_uth_len_max,
- g_uth_typ_ofs => c_uth_typ_ofs,
-
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux,
- -- BSN ALIGNER
- g_use_bsn_align => c_use_bsn_align,
- -- DATA BUFFER
- g_use_data_buf => c_use_data_buf
- )
- port map(
- -- System
- chip_id => this_chip_id,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- cal_clk => cal_clk,
-
- -- MM interface
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Datapath User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => tx_usr_siso_2arr,
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
-
- -- Mesh serial interface (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+
+ -- BLOCK GENERATOR
+ g_use_bg => c_use_bg,
+
+ -- MESH TERMINAL
+ -- System
+ g_node_type => c_node_type,
+ g_nof_bus => c_nof_bus,
+ -- User
+ g_usr_use_complex => c_usr_use_complex,
+ g_usr_data_w => c_usr_data_w,
+ g_usr_frame_len => c_usr_frame_len,
+ g_usr_nof_streams => c_usr_nof_streams,
+ -- Phy
+ g_phy_nof_serial => c_phy_nof_serial,
+ g_phy_gx_mbps => c_phy_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => c_phy_ena_reorder,
+ -- Tx
+ g_use_tx => c_use_tx,
+ g_tx_input_use_fifo => c_tx_input_use_fifo,
+ g_tx_input_fifo_size => c_tx_input_fifo_size,
+ g_tx_input_fifo_fill => c_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => c_use_rx,
+ g_rx_output_use_fifo => c_rx_output_use_fifo,
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => c_mon_select,
+ g_mon_nof_words => c_mon_nof_words,
+ g_mon_use_sync => c_mon_use_sync,
+ -- UTH
+ g_uth_len_max => c_uth_len_max,
+ g_uth_typ_ofs => c_uth_typ_ofs,
+
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux,
+ -- BSN ALIGNER
+ g_use_bsn_align => c_use_bsn_align,
+ -- DATA BUFFER
+ g_use_data_buf => c_use_data_buf
+ )
+ port map(
+ -- System
+ chip_id => this_chip_id,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ cal_clk => cal_clk,
+
+ -- MM interface
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Datapath User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+
+ -- Mesh serial interface (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr
+ );
-----------------------------------------------------------------------------
-- Mesh I/O
@@ -458,23 +458,23 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
end;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
index 2fe9f2030e..d26eeb2ee8 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
@@ -28,12 +28,12 @@
-- > run 10 us
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.tb_unb1_board_pkg.all;
entity tb_unb1_terminal_bg_mesh_db is
end tb_unb1_terminal_bg_mesh_db;
@@ -118,134 +118,134 @@ begin
------------------------------------------------------------------------------
gen_bn: for BN in 0 to c_nof_bn - 1 generate
u_bn : entity work.unb1_terminal_bg_mesh_db
- generic map (
- -- General
- g_sim => c_sim,
- g_sim_level => c_sim_level,
- g_sim_unb_nr => c_sim_unb_nr,
- g_sim_node_nr => (BN + 4)
- )
- port map (
- -- GENERAL
- WDI => WDI,
- CLK => ext_clk,
- PPS => ext_pps,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
- ETH_SGIN => eth_rxp(BN + c_nof_fn),
- ETH_SGOUT => eth_txp(BN + c_nof_fn),
-
- -- Transceiver clocks
- SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
-
- -- Mesh serial I/O
- FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
- FN_BN_0_RX => FN_BN_0_RX_arr(BN + c_nof_fn),
- FN_BN_1_TX => FN_BN_1_TX_arr(BN + c_nof_fn),
- FN_BN_1_RX => FN_BN_1_RX_arr(BN + c_nof_fn),
- FN_BN_2_TX => FN_BN_2_TX_arr(BN + c_nof_fn),
- FN_BN_2_RX => FN_BN_2_RX_arr(BN + c_nof_fn),
- FN_BN_3_TX => FN_BN_3_TX_arr(BN + c_nof_fn),
- FN_BN_3_RX => FN_BN_3_RX_arr(BN + c_nof_fn)
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => c_sim_level,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => (BN + 4)
+ )
+ port map (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp(BN + c_nof_fn),
+ ETH_SGOUT => eth_txp(BN + c_nof_fn),
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
+ FN_BN_0_RX => FN_BN_0_RX_arr(BN + c_nof_fn),
+ FN_BN_1_TX => FN_BN_1_TX_arr(BN + c_nof_fn),
+ FN_BN_1_RX => FN_BN_1_RX_arr(BN + c_nof_fn),
+ FN_BN_2_TX => FN_BN_2_TX_arr(BN + c_nof_fn),
+ FN_BN_2_RX => FN_BN_2_RX_arr(BN + c_nof_fn),
+ FN_BN_3_TX => FN_BN_3_TX_arr(BN + c_nof_fn),
+ FN_BN_3_RX => FN_BN_3_RX_arr(BN + c_nof_fn)
+ );
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
- rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_RX_arr(BN + c_nof_fn),
- FN_BN_0_RX => FN_BN_0_TX_arr(BN + c_nof_fn),
- FN_BN_1_TX => FN_BN_1_RX_arr(BN + c_nof_fn),
- FN_BN_1_RX => FN_BN_1_TX_arr(BN + c_nof_fn),
- FN_BN_2_TX => FN_BN_2_RX_arr(BN + c_nof_fn),
- FN_BN_2_RX => FN_BN_2_TX_arr(BN + c_nof_fn),
- FN_BN_3_TX => FN_BN_3_RX_arr(BN + c_nof_fn),
- FN_BN_3_RX => FN_BN_3_TX_arr(BN + c_nof_fn)
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
+ rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_RX_arr(BN + c_nof_fn),
+ FN_BN_0_RX => FN_BN_0_TX_arr(BN + c_nof_fn),
+ FN_BN_1_TX => FN_BN_1_RX_arr(BN + c_nof_fn),
+ FN_BN_1_RX => FN_BN_1_TX_arr(BN + c_nof_fn),
+ FN_BN_2_TX => FN_BN_2_RX_arr(BN + c_nof_fn),
+ FN_BN_2_RX => FN_BN_2_TX_arr(BN + c_nof_fn),
+ FN_BN_3_TX => FN_BN_3_RX_arr(BN + c_nof_fn),
+ FN_BN_3_RX => FN_BN_3_TX_arr(BN + c_nof_fn)
+ );
end generate;
gen_fn: for FN in 0 to c_nof_fn - 1 generate
u_fn : entity work.unb1_terminal_bg_mesh_db
- generic map (
- -- General
- g_sim => c_sim,
- g_sim_level => c_sim_level,
- g_sim_unb_nr => c_sim_unb_nr,
- g_sim_node_nr => FN
- )
- port map (
- -- GENERAL
- WDI => WDI,
- CLK => ext_clk,
- PPS => ext_pps,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
- ETH_SGIN => eth_rxp(FN),
- ETH_SGOUT => eth_txp(FN),
-
- -- Transceiver clocks
- SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
-
- -- Mesh serial I/O
- FN_BN_0_TX => FN_BN_0_TX_arr(FN),
- FN_BN_0_RX => FN_BN_0_RX_arr(FN),
- FN_BN_1_TX => FN_BN_1_TX_arr(FN),
- FN_BN_1_RX => FN_BN_1_RX_arr(FN),
- FN_BN_2_TX => FN_BN_2_TX_arr(FN),
- FN_BN_2_RX => FN_BN_2_RX_arr(FN),
- FN_BN_3_TX => FN_BN_3_TX_arr(FN),
- FN_BN_3_RX => FN_BN_3_RX_arr(FN)
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => c_sim_level,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => FN
+ )
+ port map (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp(FN),
+ ETH_SGOUT => eth_txp(FN),
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX_arr(FN),
+ FN_BN_0_RX => FN_BN_0_RX_arr(FN),
+ FN_BN_1_TX => FN_BN_1_TX_arr(FN),
+ FN_BN_1_RX => FN_BN_1_RX_arr(FN),
+ FN_BN_2_TX => FN_BN_2_TX_arr(FN),
+ FN_BN_2_RX => FN_BN_2_RX_arr(FN),
+ FN_BN_3_TX => FN_BN_3_TX_arr(FN),
+ FN_BN_3_RX => FN_BN_3_RX_arr(FN)
+ );
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
- rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_RX_arr(FN),
- FN_BN_0_RX => FN_BN_0_TX_arr(FN),
- FN_BN_1_TX => FN_BN_1_RX_arr(FN),
- FN_BN_1_RX => FN_BN_1_TX_arr(FN),
- FN_BN_2_TX => FN_BN_2_RX_arr(FN),
- FN_BN_2_RX => FN_BN_2_TX_arr(FN),
- FN_BN_3_TX => FN_BN_3_RX_arr(FN),
- FN_BN_3_RX => FN_BN_3_TX_arr(FN)
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
+ rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_RX_arr(FN),
+ FN_BN_0_RX => FN_BN_0_TX_arr(FN),
+ FN_BN_1_TX => FN_BN_1_RX_arr(FN),
+ FN_BN_1_RX => FN_BN_1_TX_arr(FN),
+ FN_BN_2_TX => FN_BN_2_RX_arr(FN),
+ FN_BN_2_RX => FN_BN_2_TX_arr(FN),
+ FN_BN_3_TX => FN_BN_3_RX_arr(FN),
+ FN_BN_3_RX => FN_BN_3_TX_arr(FN)
+ );
end generate;
-- Direct interconnect BN0<->FN0.
@@ -257,18 +257,18 @@ begin
-- Mesh model
gen_mesh : if c_nof_bn > 1 or c_nof_fn > 1 generate
u_mesh_model_serial : entity unb1_board_lib.unb1_board_mesh_model_sl
- generic map(
- g_reorder => c_ena_mesh_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
- bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
-
- -- BN to FN
- bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
- fn_rx_sl_3arr => fn_in_mesh_serial_3arr
- );
+ generic map(
+ g_reorder => c_ena_mesh_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
+ bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
+ fn_rx_sl_3arr => fn_in_mesh_serial_3arr
+ );
end generate;
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
index ca717a1978..669ba05c47 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_10GbE is
@@ -35,9 +35,9 @@ end tb_unb1_test_10GbE;
architecture tb of tb_unb1_test_10GbE is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_10GbE",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_10GbE",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index 4dc4b63f76..2f7b451891 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_10GbE is
generic (
@@ -95,66 +95,66 @@ architecture str of unb1_test_10GbE is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN,
-
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX,
- BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX,
+ BN_BI_3_TX => BN_BI_3_TX,
+ BN_BI_3_RX => BN_BI_3_RX
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
index 1e2189fd17..de95eb15e2 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_10GbE_tx_only is
@@ -35,9 +35,9 @@ end tb_unb1_test_10GbE_tx_only;
architecture tb of tb_unb1_test_10GbE_tx_only is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_10GbE_tx_only",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_10GbE_tx_only",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
index bf41fa0ee4..fc17d595ab 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_10GbE_tx_only is
generic (
@@ -87,57 +87,57 @@ architecture str of unb1_test_10GbE_tx_only is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
index 1a4919e2d9..90ed584b17 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_1GbE is
@@ -35,9 +35,9 @@ end tb_unb1_test_1GbE;
architecture tb of tb_unb1_test_1GbE is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_1GbE",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_1GbE",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
index c343b9bba3..835f810cdf 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_1GbE is
generic (
@@ -67,38 +67,38 @@ architecture str of unb1_test_1GbE is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
index 95e5625c63..322fb224a1 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_all is
@@ -35,9 +35,9 @@ end tb_unb1_test_all;
architecture tb of tb_unb1_test_all is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_all",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_all",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
index 3fe8e0c0b7..91ad1862c3 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_all is
generic (
@@ -106,74 +106,74 @@ architecture str of unb1_test_all is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN,
-
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX,
- BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX,
+ BN_BI_3_TX => BN_BI_3_TX,
+ BN_BI_3_RX => BN_BI_3_RX,
+
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
index 45dee37a1e..815c85e4be 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr is
@@ -35,9 +35,9 @@ end tb_unb1_test_ddr;
architecture tb of tb_unb1_test_ddr is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
index c7999ff52f..80676f3efd 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr is
generic (
@@ -73,46 +73,46 @@ architecture str of unb1_test_ddr is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
-
--- MB_II_IN => MB_II_IN,
--- MB_II_IO => MB_II_IO,
--- MB_II_OU => MB_II_OU
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+
+ -- MB_II_IN => MB_II_IN,
+ -- MB_II_IO => MB_II_IO,
+ -- MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
index 987b652ec9..dd0a7df6b1 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_I is
@@ -35,9 +35,9 @@ end tb_unb1_test_ddr_16g_MB_I;
architecture tb of tb_unb1_test_ddr_16g_MB_I is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_I",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_I",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
index 60ce44f69d..6f29ac7c66 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_I is
generic (
@@ -73,43 +73,43 @@ architecture str of unb1_test_ddr_16g_MB_I is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
index 8563b7b429..26b2974be1 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_II is
@@ -35,9 +35,9 @@ end tb_unb1_test_ddr_16g_MB_II;
architecture tb of tb_unb1_test_ddr_16g_MB_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
index ddcbca83a0..40c5666221 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_II is
generic (
@@ -73,43 +73,43 @@ architecture str of unb1_test_ddr_16g_MB_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
index d46c182efc..360e1f656b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_I_II is
@@ -35,9 +35,9 @@ end tb_unb1_test_ddr_16g_MB_I_II;
architecture tb of tb_unb1_test_ddr_16g_MB_I_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_I_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_I_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
index 7acc74681f..f63b381509 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_I_II is
generic (
@@ -78,48 +78,48 @@ architecture str of unb1_test_ddr_16g_MB_I_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
index f6e193f507..81056d01cb 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_I is
@@ -35,9 +35,9 @@ end tb_unb1_test_ddr_MB_I;
architecture tb of tb_unb1_test_ddr_MB_I is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_I",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_I",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
index b98a4e527b..cc81973e67 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_II is
@@ -35,9 +35,9 @@ end tb_unb1_test_ddr_MB_II;
architecture tb of tb_unb1_test_ddr_MB_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
index 267bb2e42d..95e08674f9 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
@@ -25,7 +25,7 @@
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_I_II is
@@ -35,9 +35,9 @@ end tb_unb1_test_ddr_MB_I_II;
architecture tb of tb_unb1_test_ddr_MB_I_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_I_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 1 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_I_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 1 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
index 8fd5ea7484..bc05d59bd6 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_MB_I_II is
generic (
@@ -78,48 +78,48 @@ architecture str of unb1_test_ddr_MB_I_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 29dd996bfa..5b07d87a3e 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb1_test_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb1_test_pkg.all;
+ use work.unb1_test_pkg.all;
entity mmm_unb1_test is
@@ -264,102 +264,102 @@ begin
eth1g_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
u_mm_file_reg_dp_offload_tx_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
u_mm_file_reg_dp_offload_tx_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
u_mm_file_reg_dp_offload_tx_10GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_hdr_dat_mosi, reg_dp_offload_tx_10GbE_hdr_dat_miso);
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_hdr_dat_mosi, reg_dp_offload_tx_10GbE_hdr_dat_miso);
u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+ port map(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
u_mm_file_reg_dp_offload_rx_10GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_10GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso);
+ port map(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso);
u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
u_mm_file_reg_tr_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE") -- , c_mm_clk_period, FALSE, 0)
- port map(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
u_mm_file_reg_tr_xaui : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI") -- , c_mm_clk_period, FALSE, 0)
- port map(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
+ port map(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
----------------------------------------------------------------------------
@@ -385,10 +385,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
@@ -409,405 +409,405 @@ begin
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb1_test
- port map (
- clk_0 => mm_clk,
- reset_n => i_reset_n,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0 downto 0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_10GbE
- coe_clk_export_from_the_reg_tr_10GbE => OPEN,
- coe_reset_export_from_the_reg_tr_10GbE => OPEN,
- coe_address_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.rd,
- coe_readdata_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.rddata(c_word_w - 1 downto 0),
- coe_waitrequest_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.waitrequest,
- coe_write_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wr,
- coe_writedata_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_xaui
- coe_clk_export_from_the_reg_tr_xaui => OPEN,
- coe_reset_export_from_the_reg_tr_xaui => OPEN,
- coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(c_reg_tr_xaui_multi_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.rd,
- coe_readdata_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.rddata(c_word_w - 1 downto 0),
- coe_waitrequest_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.waitrequest,
- coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
- coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg_1GbE
- reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_1GbE_clk_export => OPEN,
- reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
- reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_bg_1GbE_reset_export => OPEN,
- reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
- reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- -- the_ram_diag_bg_1GbE
- ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w - 1 downto 0),
- ram_diag_bg_1GbE_clk_export => OPEN,
- ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
- ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
- ram_diag_bg_1GbE_reset_export => OPEN,
- ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
- ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg_10GbE
- reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_10GbE_clk_export => OPEN,
- reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
- reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_bg_10GbE_reset_export => OPEN,
- reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
- reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- -- the_ram_diag_bg_10GbE
- ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
- ram_diag_bg_10GbE_clk_export => OPEN,
- ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
- ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
- ram_diag_bg_10GbE_reset_export => OPEN,
- ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
- ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_tx_1GbE
- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w - 1 downto 0),
- reg_dp_offload_tx_1GbE_clk_export => OPEN,
- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_offload_tx_1GbE_reset_export => OPEN,
- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- -- the_reg_dp_offload_tx_10GbE
- reg_dp_offload_tx_10GbE_address_export => reg_dp_offload_tx_10GbE_mosi.address(c_reg_dp_offload_tx_10GbE_multi_adr_w - 1 downto 0),
- reg_dp_offload_tx_10GbE_clk_export => OPEN,
- reg_dp_offload_tx_10GbE_read_export => reg_dp_offload_tx_10GbE_mosi.rd,
- reg_dp_offload_tx_10GbE_readdata_export => reg_dp_offload_tx_10GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_offload_tx_10GbE_reset_export => OPEN,
- reg_dp_offload_tx_10GbE_write_export => reg_dp_offload_tx_10GbE_mosi.wr,
- reg_dp_offload_tx_10GbE_writedata_export => reg_dp_offload_tx_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_tx_1GbE_hdr_dat
- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w - 1 downto 0),
- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
- -- the_reg_dp_offload_tx_10GbE_hdr_dat
- reg_dp_offload_tx_10GbE_hdr_dat_address_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_10GbE_hdr_dat_multi_adr_w - 1 downto 0),
- reg_dp_offload_tx_10GbE_hdr_dat_clk_export => OPEN,
- reg_dp_offload_tx_10GbE_hdr_dat_read_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.rd,
- reg_dp_offload_tx_10GbE_hdr_dat_readdata_export => reg_dp_offload_tx_10GbE_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_offload_tx_10GbE_hdr_dat_reset_export => OPEN,
- reg_dp_offload_tx_10GbE_hdr_dat_write_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.wr,
- reg_dp_offload_tx_10GbE_hdr_dat_writedata_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_rx_1GbE_hdr_dat
- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w - 1 downto 0),
- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
- -- the_reg_dp_offload_rx_10GbE_hdr_dat
- reg_dp_offload_rx_10GbE_hdr_dat_address_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_10GbE_hdr_dat_multi_adr_w - 1 downto 0),
- reg_dp_offload_rx_10GbE_hdr_dat_clk_export => OPEN,
- reg_dp_offload_rx_10GbE_hdr_dat_read_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.rd,
- reg_dp_offload_rx_10GbE_hdr_dat_readdata_export => reg_dp_offload_rx_10GbE_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_offload_rx_10GbE_hdr_dat_reset_export => OPEN,
- reg_dp_offload_rx_10GbE_hdr_dat_write_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.wr,
- reg_dp_offload_rx_10GbE_hdr_dat_writedata_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- -- the_reg_bsn_monitor_1GbE
- reg_bsn_monitor_1GbE_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_1GbE_clk_export => OPEN,
- reg_bsn_monitor_1GbE_read_export => reg_bsn_monitor_1GbE_mosi.rd,
- reg_bsn_monitor_1GbE_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_1GbE_reset_export => OPEN,
- reg_bsn_monitor_1GbE_write_export => reg_bsn_monitor_1GbE_mosi.wr,
- reg_bsn_monitor_1GbE_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- -- the_reg_bsn_monitor_10GbE
- reg_bsn_monitor_10GbE_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_10GbE_clk_export => OPEN,
- reg_bsn_monitor_10GbE_read_export => reg_bsn_monitor_10GbE_mosi.rd,
- reg_bsn_monitor_10GbE_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_10GbE_reset_export => OPEN,
- reg_bsn_monitor_10GbE_write_export => reg_bsn_monitor_10GbE_mosi.wr,
- reg_bsn_monitor_10GbE_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer_1GbE
- ram_diag_data_buffer_1GbE_address_export => ram_diag_data_buf_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- ram_diag_data_buffer_1GbE_clk_export => OPEN,
- ram_diag_data_buffer_1GbE_read_export => ram_diag_data_buf_1GbE_mosi.rd,
- ram_diag_data_buffer_1GbE_readdata_export => ram_diag_data_buf_1GbE_miso.rddata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_1GbE_reset_export => OPEN,
- ram_diag_data_buffer_1GbE_write_export => ram_diag_data_buf_1GbE_mosi.wr,
- ram_diag_data_buffer_1GbE_writedata_export => ram_diag_data_buf_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- -- the_ram_diag_data_buffer_10GbE
- ram_diag_data_buffer_10GbE_address_export => ram_diag_data_buf_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- ram_diag_data_buffer_10GbE_clk_export => OPEN,
- ram_diag_data_buffer_10GbE_read_export => ram_diag_data_buf_10GbE_mosi.rd,
- ram_diag_data_buffer_10GbE_readdata_export => ram_diag_data_buf_10GbE_miso.rddata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_10GbE_reset_export => OPEN,
- ram_diag_data_buffer_10GbE_write_export => ram_diag_data_buf_10GbE_mosi.wr,
- ram_diag_data_buffer_10GbE_writedata_export => ram_diag_data_buf_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buffer_1GbE
- reg_diag_data_buffer_1GbE_address_export => reg_diag_data_buf_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_1GbE_clk_export => OPEN,
- reg_diag_data_buffer_1GbE_read_export => reg_diag_data_buf_1GbE_mosi.rd,
- reg_diag_data_buffer_1GbE_readdata_export => reg_diag_data_buf_1GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_1GbE_reset_export => OPEN,
- reg_diag_data_buffer_1GbE_write_export => reg_diag_data_buf_1GbE_mosi.wr,
- reg_diag_data_buffer_1GbE_writedata_export => reg_diag_data_buf_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- -- the_reg_diag_data_buffer_10GbE
- reg_diag_data_buffer_10GbE_address_export => reg_diag_data_buf_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_10GbE_clk_export => OPEN,
- reg_diag_data_buffer_10GbE_read_export => reg_diag_data_buf_10GbE_mosi.rd,
- reg_diag_data_buffer_10GbE_readdata_export => reg_diag_data_buf_10GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_10GbE_reset_export => OPEN,
- reg_diag_data_buffer_10GbE_write_export => reg_diag_data_buf_10GbE_mosi.wr,
- reg_diag_data_buffer_10GbE_writedata_export => reg_diag_data_buf_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- reg_diag_tx_seq_10GbE
- reg_diag_tx_seq_10GbE_address_export => reg_diag_tx_seq_10GbE_mosi.address(4 - 1 downto 0),
- reg_diag_tx_seq_10GbE_clk_export => OPEN,
- reg_diag_tx_seq_10GbE_read_export => reg_diag_tx_seq_10GbE_mosi.rd,
- reg_diag_tx_seq_10GbE_readdata_export => reg_diag_tx_seq_10GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_10GbE_reset_export => OPEN,
- reg_diag_tx_seq_10GbE_write_export => reg_diag_tx_seq_10GbE_mosi.wr,
- reg_diag_tx_seq_10GbE_writedata_export => reg_diag_tx_seq_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- reg_diag_rx_seq_10GbE
- reg_diag_rx_seq_10GbE_address_export => reg_diag_rx_seq_10GbE_mosi.address(5 - 1 downto 0),
- reg_diag_rx_seq_10GbE_clk_export => OPEN,
- reg_diag_rx_seq_10GbE_read_export => reg_diag_rx_seq_10GbE_mosi.rd,
- reg_diag_rx_seq_10GbE_readdata_export => reg_diag_rx_seq_10GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_10GbE_reset_export => OPEN,
- reg_diag_rx_seq_10GbE_write_export => reg_diag_rx_seq_10GbE_mosi.wr,
- reg_diag_rx_seq_10GbE_writedata_export => reg_diag_rx_seq_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- -- reg_diag_tx_seq_1GbE
- reg_diag_tx_seq_1GbE_address_export => reg_diag_tx_seq_1GbE_mosi.address(2 - 1 downto 0),
- reg_diag_tx_seq_1GbE_clk_export => OPEN,
- reg_diag_tx_seq_1GbE_read_export => reg_diag_tx_seq_1GbE_mosi.rd,
- reg_diag_tx_seq_1GbE_readdata_export => reg_diag_tx_seq_1GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_1GbE_reset_export => OPEN,
- reg_diag_tx_seq_1GbE_write_export => reg_diag_tx_seq_1GbE_mosi.wr,
- reg_diag_tx_seq_1GbE_writedata_export => reg_diag_tx_seq_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- reg_diag_rx_seq_1GbE
- reg_diag_rx_seq_1GbE_address_export => reg_diag_rx_seq_1GbE_mosi.address(3 - 1 downto 0),
- reg_diag_rx_seq_1GbE_clk_export => OPEN,
- reg_diag_rx_seq_1GbE_read_export => reg_diag_rx_seq_1GbE_mosi.rd,
- reg_diag_rx_seq_1GbE_readdata_export => reg_diag_rx_seq_1GbE_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_1GbE_reset_export => OPEN,
- reg_diag_rx_seq_1GbE_write_export => reg_diag_rx_seq_1GbE_mosi.wr,
- reg_diag_rx_seq_1GbE_writedata_export => reg_diag_rx_seq_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_I_clk_export => OPEN,
- reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
- reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_I_reset_export => OPEN,
- reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
- reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_II_clk_export => OPEN,
- reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
- reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_II_reset_export => OPEN,
- reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
- reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
- reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
- reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
- reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
- reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
- reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
- reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
- reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
- reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
- ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
- ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
- ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
- ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
+ port map (
+ clk_0 => mm_clk,
+ reset_n => i_reset_n,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0 downto 0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_10GbE
+ coe_clk_export_from_the_reg_tr_10GbE => OPEN,
+ coe_reset_export_from_the_reg_tr_10GbE => OPEN,
+ coe_address_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ coe_waitrequest_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.waitrequest,
+ coe_write_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_xaui
+ coe_clk_export_from_the_reg_tr_xaui => OPEN,
+ coe_reset_export_from_the_reg_tr_xaui => OPEN,
+ coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(c_reg_tr_xaui_multi_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.rddata(c_word_w - 1 downto 0),
+ coe_waitrequest_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.waitrequest,
+ coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg_1GbE
+ reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_1GbE_clk_export => OPEN,
+ reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
+ reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_bg_1GbE_reset_export => OPEN,
+ reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
+ reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ -- the_ram_diag_bg_1GbE
+ ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w - 1 downto 0),
+ ram_diag_bg_1GbE_clk_export => OPEN,
+ ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
+ ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
+ ram_diag_bg_1GbE_reset_export => OPEN,
+ ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
+ ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg_10GbE
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_10GbE_clk_export => OPEN,
+ reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
+ reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_bg_10GbE_reset_export => OPEN,
+ reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
+ reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ -- the_ram_diag_bg_10GbE
+ ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
+ ram_diag_bg_10GbE_clk_export => OPEN,
+ ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
+ ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ ram_diag_bg_10GbE_reset_export => OPEN,
+ ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
+ ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_tx_1GbE
+ reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w - 1 downto 0),
+ reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ -- the_reg_dp_offload_tx_10GbE
+ reg_dp_offload_tx_10GbE_address_export => reg_dp_offload_tx_10GbE_mosi.address(c_reg_dp_offload_tx_10GbE_multi_adr_w - 1 downto 0),
+ reg_dp_offload_tx_10GbE_clk_export => OPEN,
+ reg_dp_offload_tx_10GbE_read_export => reg_dp_offload_tx_10GbE_mosi.rd,
+ reg_dp_offload_tx_10GbE_readdata_export => reg_dp_offload_tx_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_offload_tx_10GbE_reset_export => OPEN,
+ reg_dp_offload_tx_10GbE_write_export => reg_dp_offload_tx_10GbE_mosi.wr,
+ reg_dp_offload_tx_10GbE_writedata_export => reg_dp_offload_tx_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w - 1 downto 0),
+ reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+ -- the_reg_dp_offload_tx_10GbE_hdr_dat
+ reg_dp_offload_tx_10GbE_hdr_dat_address_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_10GbE_hdr_dat_multi_adr_w - 1 downto 0),
+ reg_dp_offload_tx_10GbE_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_tx_10GbE_hdr_dat_read_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.rd,
+ reg_dp_offload_tx_10GbE_hdr_dat_readdata_export => reg_dp_offload_tx_10GbE_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_offload_tx_10GbE_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_tx_10GbE_hdr_dat_write_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.wr,
+ reg_dp_offload_tx_10GbE_hdr_dat_writedata_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w - 1 downto 0),
+ reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+ -- the_reg_dp_offload_rx_10GbE_hdr_dat
+ reg_dp_offload_rx_10GbE_hdr_dat_address_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_10GbE_hdr_dat_multi_adr_w - 1 downto 0),
+ reg_dp_offload_rx_10GbE_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_rx_10GbE_hdr_dat_read_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.rd,
+ reg_dp_offload_rx_10GbE_hdr_dat_readdata_export => reg_dp_offload_rx_10GbE_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_offload_rx_10GbE_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_rx_10GbE_hdr_dat_write_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.wr,
+ reg_dp_offload_rx_10GbE_hdr_dat_writedata_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ -- the_reg_bsn_monitor_1GbE
+ reg_bsn_monitor_1GbE_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_1GbE_clk_export => OPEN,
+ reg_bsn_monitor_1GbE_read_export => reg_bsn_monitor_1GbE_mosi.rd,
+ reg_bsn_monitor_1GbE_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_1GbE_reset_export => OPEN,
+ reg_bsn_monitor_1GbE_write_export => reg_bsn_monitor_1GbE_mosi.wr,
+ reg_bsn_monitor_1GbE_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ -- the_reg_bsn_monitor_10GbE
+ reg_bsn_monitor_10GbE_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_10GbE_clk_export => OPEN,
+ reg_bsn_monitor_10GbE_read_export => reg_bsn_monitor_10GbE_mosi.rd,
+ reg_bsn_monitor_10GbE_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_10GbE_reset_export => OPEN,
+ reg_bsn_monitor_10GbE_write_export => reg_bsn_monitor_10GbE_mosi.wr,
+ reg_bsn_monitor_10GbE_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer_1GbE
+ ram_diag_data_buffer_1GbE_address_export => ram_diag_data_buf_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ ram_diag_data_buffer_1GbE_clk_export => OPEN,
+ ram_diag_data_buffer_1GbE_read_export => ram_diag_data_buf_1GbE_mosi.rd,
+ ram_diag_data_buffer_1GbE_readdata_export => ram_diag_data_buf_1GbE_miso.rddata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_1GbE_reset_export => OPEN,
+ ram_diag_data_buffer_1GbE_write_export => ram_diag_data_buf_1GbE_mosi.wr,
+ ram_diag_data_buffer_1GbE_writedata_export => ram_diag_data_buf_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ -- the_ram_diag_data_buffer_10GbE
+ ram_diag_data_buffer_10GbE_address_export => ram_diag_data_buf_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ ram_diag_data_buffer_10GbE_clk_export => OPEN,
+ ram_diag_data_buffer_10GbE_read_export => ram_diag_data_buf_10GbE_mosi.rd,
+ ram_diag_data_buffer_10GbE_readdata_export => ram_diag_data_buf_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_10GbE_reset_export => OPEN,
+ ram_diag_data_buffer_10GbE_write_export => ram_diag_data_buf_10GbE_mosi.wr,
+ ram_diag_data_buffer_10GbE_writedata_export => ram_diag_data_buf_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buffer_1GbE
+ reg_diag_data_buffer_1GbE_address_export => reg_diag_data_buf_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_1GbE_clk_export => OPEN,
+ reg_diag_data_buffer_1GbE_read_export => reg_diag_data_buf_1GbE_mosi.rd,
+ reg_diag_data_buffer_1GbE_readdata_export => reg_diag_data_buf_1GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_1GbE_reset_export => OPEN,
+ reg_diag_data_buffer_1GbE_write_export => reg_diag_data_buf_1GbE_mosi.wr,
+ reg_diag_data_buffer_1GbE_writedata_export => reg_diag_data_buf_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ -- the_reg_diag_data_buffer_10GbE
+ reg_diag_data_buffer_10GbE_address_export => reg_diag_data_buf_10GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_10GbE_clk_export => OPEN,
+ reg_diag_data_buffer_10GbE_read_export => reg_diag_data_buf_10GbE_mosi.rd,
+ reg_diag_data_buffer_10GbE_readdata_export => reg_diag_data_buf_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_10GbE_reset_export => OPEN,
+ reg_diag_data_buffer_10GbE_write_export => reg_diag_data_buf_10GbE_mosi.wr,
+ reg_diag_data_buffer_10GbE_writedata_export => reg_diag_data_buf_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- reg_diag_tx_seq_10GbE
+ reg_diag_tx_seq_10GbE_address_export => reg_diag_tx_seq_10GbE_mosi.address(4 - 1 downto 0),
+ reg_diag_tx_seq_10GbE_clk_export => OPEN,
+ reg_diag_tx_seq_10GbE_read_export => reg_diag_tx_seq_10GbE_mosi.rd,
+ reg_diag_tx_seq_10GbE_readdata_export => reg_diag_tx_seq_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_10GbE_reset_export => OPEN,
+ reg_diag_tx_seq_10GbE_write_export => reg_diag_tx_seq_10GbE_mosi.wr,
+ reg_diag_tx_seq_10GbE_writedata_export => reg_diag_tx_seq_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- reg_diag_rx_seq_10GbE
+ reg_diag_rx_seq_10GbE_address_export => reg_diag_rx_seq_10GbE_mosi.address(5 - 1 downto 0),
+ reg_diag_rx_seq_10GbE_clk_export => OPEN,
+ reg_diag_rx_seq_10GbE_read_export => reg_diag_rx_seq_10GbE_mosi.rd,
+ reg_diag_rx_seq_10GbE_readdata_export => reg_diag_rx_seq_10GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_10GbE_reset_export => OPEN,
+ reg_diag_rx_seq_10GbE_write_export => reg_diag_rx_seq_10GbE_mosi.wr,
+ reg_diag_rx_seq_10GbE_writedata_export => reg_diag_rx_seq_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ -- reg_diag_tx_seq_1GbE
+ reg_diag_tx_seq_1GbE_address_export => reg_diag_tx_seq_1GbE_mosi.address(2 - 1 downto 0),
+ reg_diag_tx_seq_1GbE_clk_export => OPEN,
+ reg_diag_tx_seq_1GbE_read_export => reg_diag_tx_seq_1GbE_mosi.rd,
+ reg_diag_tx_seq_1GbE_readdata_export => reg_diag_tx_seq_1GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_1GbE_reset_export => OPEN,
+ reg_diag_tx_seq_1GbE_write_export => reg_diag_tx_seq_1GbE_mosi.wr,
+ reg_diag_tx_seq_1GbE_writedata_export => reg_diag_tx_seq_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- reg_diag_rx_seq_1GbE
+ reg_diag_rx_seq_1GbE_address_export => reg_diag_rx_seq_1GbE_mosi.address(3 - 1 downto 0),
+ reg_diag_rx_seq_1GbE_clk_export => OPEN,
+ reg_diag_rx_seq_1GbE_read_export => reg_diag_rx_seq_1GbE_mosi.rd,
+ reg_diag_rx_seq_1GbE_readdata_export => reg_diag_rx_seq_1GbE_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_1GbE_reset_export => OPEN,
+ reg_diag_rx_seq_1GbE_write_export => reg_diag_rx_seq_1GbE_mosi.wr,
+ reg_diag_rx_seq_1GbE_writedata_export => reg_diag_rx_seq_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_I_clk_export => OPEN,
+ reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
+ reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_I_reset_export => OPEN,
+ reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
+ reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_II_clk_export => OPEN,
+ reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
+ reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_II_reset_export => OPEN,
+ reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
+ reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 1589f5a61f..24dcd0a9d4 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -20,341 +20,341 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_test_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
- component qsys_unb1_test is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb1_test;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb1_test is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_remu : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb1_test;
end qsys_unb1_test_pkg;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
index e165615bf2..ef7319165c 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
@@ -21,18 +21,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb1_test_pkg.all;
entity udp_stream is
generic (
@@ -103,14 +103,28 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC(
+ g_bg_block_size,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ g_bg_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ g_bg_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ g_bg_block_size-1,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1001" & "111011111100" & "0001" & "101111111";
@@ -156,52 +170,52 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl,
- g_use_tx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_use_tx_seq => true
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
@@ -209,73 +223,73 @@ begin
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
--- reg_mosi => reg_dp_offload_tx_mosi,
--- reg_miso => reg_dp_offload_tx_miso,
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ -- reg_mosi => reg_dp_offload_tx_mosi,
+ -- reg_miso => reg_dp_offload_tx_miso,
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
@@ -300,53 +314,53 @@ begin
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 9e7bc8c9f5..c6b998c1bd 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -21,21 +21,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb1_test_pkg.all;
entity unb1_test is
generic (
@@ -118,20 +118,26 @@ architecture str of unb1_test is
-- Firmware version x.y
constant c_fw_version : t_unb1_board_fw_version := (1, 2);
- -- Select the according revision record based on the design name.
+ -- Select the according revision record based on the design name.
constant c_revision_select : t_unb1_test_config := func_unb1_test_sel_revision_rec(g_design_name);
-- ddr
constant c_nof_MB : natural := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- constant c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_revision_select.use_streaming_1GbE, 1, 0),
- c_revision_select.use_front, 0,
- c_revision_select.use_back,
- c_revision_select.use_ddr_MB_I,
- c_revision_select.use_ddr_MB_II,
- 0,
- 1);
+ constant c_use_phy : t_c_unb1_board_use_phy := (
+ sel_a_b(
+ c_revision_select.use_streaming_1GbE,
+ 1,
+ 0),
+ c_revision_select.use_front,
+ 0,
+ c_revision_select.use_back,
+ c_revision_select.use_ddr_MB_I,
+ c_revision_select.use_ddr_MB_II,
+ 0,
+ 1
+ );
constant c_nof_streams_10GbE : natural := c_revision_select.use_nof_streams_10GbE;
constant c_nof_streams_1GbE : natural := c_revision_select.use_nof_streams_1GbE;
@@ -337,7 +343,7 @@ architecture str of unb1_test is
signal reg_io_ddr_MB_II_mosi : t_mem_mosi;
signal reg_io_ddr_MB_II_miso : t_mem_miso;
- -- DDR3 pass on termination control from master to slave controller
+ -- DDR3 pass on termination control from master to slave controller
signal term_ctrl_out : t_tech_ddr3_phy_terminationcontrol;
signal term_ctrl_in : t_tech_ddr3_phy_terminationcontrol;
@@ -351,414 +357,414 @@ architecture str of unb1_test is
begin
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_udp_offload => c_revision_select.use_streaming_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_rec_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => dp_offload_tx_1GbE_src_out_arr,
- udp_tx_siso_arr => dp_offload_tx_1GbE_src_in_arr,
- udp_rx_sosi_arr => dp_offload_rx_1GbE_snk_in_arr,
- udp_rx_siso_arr => dp_offload_rx_1GbE_snk_out_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
--- END GENERATE;
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_udp_offload => c_revision_select.use_streaming_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_rec_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => dp_offload_tx_1GbE_src_out_arr,
+ udp_tx_siso_arr => dp_offload_tx_1GbE_src_in_arr,
+ udp_rx_sosi_arr => dp_offload_rx_1GbE_snk_in_arr,
+ udp_rx_siso_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+ -- END GENERATE;
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams_1GbE => c_nof_streams_1GbE,
- g_nof_streams_10GbE => 3, -- c_nof_streams_10GbE,
- g_nof_streams_ddr => 1, -- c_nof_streams_ddr,
- g_bg_block_size => c_bg_block_size
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
-
- reg_dp_offload_tx_10GbE_mosi => reg_dp_offload_tx_10GbE_mosi,
- reg_dp_offload_tx_10GbE_miso => reg_dp_offload_tx_10GbE_miso,
- reg_dp_offload_tx_10GbE_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
- reg_dp_offload_tx_10GbE_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
-
- -- dp_offload_rx
- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- reg_dp_offload_rx_10GbE_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
- reg_dp_offload_rx_10GbE_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- tr_10GbE
- reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
- reg_tr_10GbE_miso => reg_tr_10GbE_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso,
-
- -- DDR3 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
-
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
-
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR3 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
-
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
-
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
-
- gen_udp_stream_1GbE : if c_revision_select.use_streaming_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams_1GbE => c_nof_streams_1GbE,
+ g_nof_streams_10GbE => 3, -- c_nof_streams_10GbE,
+ g_nof_streams_ddr => 1, -- c_nof_streams_ddr,
+ g_bg_block_size => c_bg_block_size
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+ reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+
+ reg_dp_offload_tx_10GbE_mosi => reg_dp_offload_tx_10GbE_mosi,
+ reg_dp_offload_tx_10GbE_miso => reg_dp_offload_tx_10GbE_miso,
+ reg_dp_offload_tx_10GbE_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_10GbE_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
-- dp_offload_rx
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+
+ reg_dp_offload_rx_10GbE_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_10GbE_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- tr_10GbE
+ reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
+ reg_tr_10GbE_miso => reg_tr_10GbE_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+
+ -- DDR3 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR3 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+
+ gen_udp_stream_1GbE : if c_revision_select.use_streaming_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
gen_udp_stream_10GbE : if c_revision_select.use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_10GbE,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_def_10GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen mm
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
- reg_dp_offload_tx_mosi => reg_dp_offload_tx_10GbE_mosi,
- reg_dp_offload_tx_miso => reg_dp_offload_tx_10GbE_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- dp_offload_rx
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- -- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_10GbE,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_def_10GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen mm
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_10GbE_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_10GbE_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
end generate;
@@ -767,62 +773,62 @@ begin
-----------------------------------------------------------------------------
u_areset_sa_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map(
- clk => SA_CLK,
- in_rst => '0',
- out_rst => sa_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
gen_tr_10GbE : if c_revision_select.use_10GbE = true generate
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_streams_10GbE,
- g_use_mdio => true,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk_156 => SA_CLK,
- tr_ref_rst_156 => sa_rst,
-
- cal_rec_clk => cal_rec_clk, -- mm_clk, --cal_clk, mm_clk required by XAUI phy
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
-
- xaui_mosi => reg_tr_xaui_mosi,
- xaui_miso => reg_tr_xaui_miso,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr,
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
-
- -- Serial XAUI IO
- xaui_tx_arr => i_xaui_tx_arr,
- xaui_rx_arr => i_xaui_rx_arr,
-
- -- MDIO External clock and serial data.
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_streams_10GbE,
+ g_use_mdio => true,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ cal_rec_clk => cal_rec_clk, -- mm_clk, --cal_clk, mm_clk required by XAUI phy
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr,
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => i_xaui_tx_arr,
+ xaui_rx_arr => i_xaui_rx_arr,
+
+ -- MDIO External clock and serial data.
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
-- Wire together different types
gen_wires: for i in 0 to c_nof_streams_10GbE-1 generate
@@ -831,158 +837,158 @@ begin
end generate;
gen_tr_front : if c_revision_select.use_front = 1 generate
- u_front_io : entity unb1_board_lib.unb1_board_front_io
- generic map (
- g_nof_xaui => c_nof_streams_10GbE
- )
- port map (
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr,
-
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL
- );
+ u_front_io : entity unb1_board_lib.unb1_board_front_io
+ generic map (
+ g_nof_xaui => c_nof_streams_10GbE
+ )
+ port map (
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
end generate;
end generate;
-gen_mms_io_ddr_diag_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
- u_mms_io_ddr_diag_MB_I : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => c_data_w_64,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_revision_select.use_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- DDR reference clock
- ctlr_ref_clk => CLK,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => MB_I_ctlr_clk,
- ctlr_rst_out => MB_I_ctlr_rst,
-
- ctlr_clk_in => MB_I_ctlr_clk,
- ctlr_rst_in => MB_I_ctlr_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on signals from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_I_IN,
- phy3_io => MB_I_IO,
- phy3_ou => MB_I_OU,
-
- -- DIAG Tx seq
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- -- DIAG rx seq with optional data buffer
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ gen_mms_io_ddr_diag_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
+ u_mms_io_ddr_diag_MB_I : entity io_ddr_lib.mms_io_ddr_diag
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => c_data_w_64,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => c_revision_select.use_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- DDR reference clock
+ ctlr_ref_clk => CLK,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => MB_I_ctlr_clk,
+ ctlr_rst_out => MB_I_ctlr_rst,
+
+ ctlr_clk_in => MB_I_ctlr_clk,
+ ctlr_rst_in => MB_I_ctlr_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on signals from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_I_IN,
+ phy3_io => MB_I_IO,
+ phy3_ou => MB_I_OU,
+
+ -- DIAG Tx seq
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ -- DIAG rx seq with optional data buffer
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
-gen_mms_io_ddr_diag_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
- u_mms_io_ddr_diag_MB_II : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => c_data_w_64,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_revision_select.use_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- DDR reference clock
- ctlr_ref_clk => CLK,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => MB_II_ctlr_clk,
- ctlr_rst_out => MB_II_ctlr_rst,
-
- ctlr_clk_in => MB_II_ctlr_clk,
- ctlr_rst_in => MB_II_ctlr_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on signals from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_II_IN,
- phy3_io => MB_II_IO,
- phy3_ou => MB_II_OU,
-
- -- DIAG Tx seq
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- -- DIAG rx seq with optional data buffer
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ gen_mms_io_ddr_diag_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
+ u_mms_io_ddr_diag_MB_II : entity io_ddr_lib.mms_io_ddr_diag
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => c_data_w_64,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => c_revision_select.use_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- DDR reference clock
+ ctlr_ref_clk => CLK,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => MB_II_ctlr_clk,
+ ctlr_rst_out => MB_II_ctlr_rst,
+
+ ctlr_clk_in => MB_II_ctlr_clk,
+ ctlr_rst_in => MB_II_ctlr_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on signals from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_II_IN,
+ phy3_io => MB_II_IO,
+ phy3_ou => MB_II_OU,
+
+ -- DIAG Tx seq
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ -- DIAG rx seq with optional data buffer
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
index 61d6ce08c8..198736a3ac 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
package unb1_test_pkg is
@@ -44,37 +44,37 @@ package unb1_test_pkg is
-- dp_offload_tx
constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
-- Function to select the revision configuration.
- function func_unb1_test_sel_revision_rec(g_design_name : string) return t_unb1_test_config;
+ function func_unb1_test_sel_revision_rec (g_design_name : string) return t_unb1_test_config;
end unb1_test_pkg;
@@ -90,7 +90,7 @@ package body unb1_test_pkg is
constant c_ddr_16g_MB_II : t_unb1_test_config := ( 0, 0, false, 1, false, 0, 0, 1, 1, c_tech_ddr3_16g_dual_rank_800m);
constant c_ddr_16g_MB_I_II : t_unb1_test_config := ( 0, 0, false, 1, false, 0, 1, 1, 2, c_tech_ddr3_16g_dual_rank_800m);
- function func_unb1_test_sel_revision_rec(g_design_name : string) return t_unb1_test_config is
+ function func_unb1_test_sel_revision_rec (g_design_name : string) return t_unb1_test_config is
begin
if g_design_name = "unb1_test_all" then return c_all;
elsif g_design_name = "unb1_test_1GbE" then return c_1GbE;
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index b4c91dc640..926ab69620 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -45,22 +45,22 @@
library ip_stratixiv_ddr3_mem_model_lib;
library IEEE, common_lib, unb1_board_lib, i2c_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use work.unb1_test_pkg.all;
entity tb_unb1_test is
- generic (
- g_design_name : string := "unb1_test";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_test";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_test;
architecture tb of tb_unb1_test is
@@ -222,14 +222,14 @@ begin
------------------------------------------------------------------------------
gen_tech_ddr_memory_model_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_revision_select.use_tech_ddr
- )
- port map (
- mem3_in => phy_MB_I_ou,
- mem3_io => phy_MB_I_io,
- mem3_ou => phy_MB_I_in
- );
+ generic map (
+ g_tech_ddr => c_revision_select.use_tech_ddr
+ )
+ port map (
+ mem3_in => phy_MB_I_ou,
+ mem3_io => phy_MB_I_io,
+ mem3_ou => phy_MB_I_in
+ );
end generate;
------------------------------------------------------------------------------
@@ -237,14 +237,14 @@ begin
------------------------------------------------------------------------------
gen_tech_ddr_memory_model_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_revision_select.use_tech_ddr
- )
- port map (
- mem3_in => phy_MB_II_ou,
- mem3_io => phy_MB_II_io,
- mem3_ou => phy_MB_II_in
- );
+ generic map (
+ g_tech_ddr => c_revision_select.use_tech_ddr
+ )
+ port map (
+ mem3_in => phy_MB_II_ou,
+ mem3_io => phy_MB_II_io,
+ mem3_ou => phy_MB_II_in
+ );
end generate;
------------------------------------------------------------------------------
@@ -252,37 +252,37 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
index f458fc3070..8cc9d6d57b 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
@@ -20,23 +20,23 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_tr_10GbE is
generic (
@@ -257,137 +257,137 @@ begin
u_qsys_unb1_tr_10GbE : qsys_unb1_tr_10GbE
port map(
- clk_in_clk => mm_clk,
- eth1g_irq_export => eth1g_reg_interrupt,
- eth1g_mm_clk_export => OPEN,
- eth1g_mm_rst_export => eth1g_mm_rst,
- eth1g_ram_address_export => eth1g_ram_mosi.address(9 downto 0),
- eth1g_ram_read_export => eth1g_ram_mosi.rd,
- eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- eth1g_ram_write_export => eth1g_ram_mosi.wr,
- eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- eth1g_reg_address_export => eth1g_reg_mosi.address(3 downto 0),
- eth1g_reg_read_export => eth1g_reg_mosi.rd,
- eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- eth1g_reg_write_export => eth1g_reg_mosi.wr,
- eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- eth1g_tse_address_export => eth1g_tse_mosi.address(9 downto 0),
- eth1g_tse_read_export => eth1g_tse_mosi.rd,
- eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- eth1g_tse_write_export => eth1g_tse_mosi.wr,
- eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- out_port_from_the_pio_debug_wave => OPEN,
- out_port_from_the_pio_wdi => pout_wdi,
- pio_pps_address_export => reg_ppsh_mosi.address(0),
- pio_pps_clk_export => OPEN,
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- pio_pps_reset_export => OPEN,
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_address_export => reg_unb_system_info_mosi.address(4 downto 0),
- pio_system_info_clk_export => OPEN,
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- pio_system_info_reset_export => OPEN,
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_address_export => ram_diag_bg_mosi.address(10 downto 0),
- ram_diag_bg_clk_export => OPEN,
- ram_diag_bg_read_export => ram_diag_bg_mosi.rd,
- ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- ram_diag_bg_reset_export => OPEN,
- ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
- ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(6 downto 0),
- reg_bsn_monitor_clk_export => OPEN,
- reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
- reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_reset_export => OPEN,
- reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
- reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_address_export => reg_diag_bg_mosi.address(2 downto 0),
- reg_diag_bg_clk_export => OPEN,
- reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
- reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- reg_diag_bg_reset_export => OPEN,
- reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
- reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(6 downto 0),
- reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
- reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
- reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
- reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
- reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(5 downto 0),
- reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
- reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd,
- reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
- reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
- reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mdio_0_address_export => reg_mdio_0_mosi.address(2 downto 0),
- reg_mdio_0_clk_export => OPEN,
- reg_mdio_0_read_export => reg_mdio_0_mosi.rd,
- reg_mdio_0_readdata_export => reg_mdio_0_miso.rddata(c_word_w - 1 downto 0),
- reg_mdio_0_reset_export => OPEN,
- reg_mdio_0_write_export => reg_mdio_0_mosi.wr,
- reg_mdio_0_writedata_export => reg_mdio_0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mdio_1_address_export => reg_mdio_1_mosi.address(2 downto 0),
- reg_mdio_1_clk_export => OPEN,
- reg_mdio_1_read_export => reg_mdio_1_mosi.rd,
- reg_mdio_1_readdata_export => reg_mdio_1_miso.rddata(c_word_w - 1 downto 0),
- reg_mdio_1_reset_export => OPEN,
- reg_mdio_1_write_export => reg_mdio_1_mosi.wr,
- reg_mdio_1_writedata_export => reg_mdio_1_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mdio_2_address_export => reg_mdio_2_mosi.address(2 downto 0),
- reg_mdio_2_clk_export => OPEN,
- reg_mdio_2_read_export => reg_mdio_2_mosi.rd,
- reg_mdio_2_readdata_export => reg_mdio_2_miso.rddata(c_word_w - 1 downto 0),
- reg_mdio_2_reset_export => OPEN,
- reg_mdio_2_write_export => reg_mdio_2_mosi.wr,
- reg_mdio_2_writedata_export => reg_mdio_2_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_address_export => reg_tr_10gbe_mosi.address(14 downto 0),
- reg_tr_10gbe_clk_export => OPEN,
- reg_tr_10gbe_read_export => reg_tr_10gbe_mosi.rd,
- reg_tr_10gbe_readdata_export => reg_tr_10gbe_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_reset_export => OPEN,
- reg_tr_10gbe_waitrequest_export => reg_tr_10gbe_miso.waitrequest,
- reg_tr_10gbe_write_export => reg_tr_10gbe_mosi.wr,
- reg_tr_10gbe_writedata_export => reg_tr_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_xaui_address_export => reg_tr_xaui_mosi.address(10 downto 0),
- reg_tr_xaui_clk_export => OPEN,
- reg_tr_xaui_read_export => reg_tr_xaui_mosi.rd,
- reg_tr_xaui_readdata_export => reg_tr_xaui_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_xaui_reset_export => OPEN,
- reg_tr_xaui_waitrequest_export => reg_tr_xaui_miso.waitrequest,
- reg_tr_xaui_write_export => reg_tr_xaui_mosi.wr,
- reg_tr_xaui_writedata_export => reg_tr_xaui_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(2 downto 0),
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_address_export => reg_wdi_mosi.address(0),
- reg_wdi_clk_export => OPEN,
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- reg_wdi_reset_export => OPEN,
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reset_in_reset_n => mm_rst_n,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
- rom_system_info_clk_export => OPEN,
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- rom_system_info_reset_export => OPEN,
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ clk_in_clk => mm_clk,
+ eth1g_irq_export => eth1g_reg_interrupt,
+ eth1g_mm_clk_export => OPEN,
+ eth1g_mm_rst_export => eth1g_mm_rst,
+ eth1g_ram_address_export => eth1g_ram_mosi.address(9 downto 0),
+ eth1g_ram_read_export => eth1g_ram_mosi.rd,
+ eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ eth1g_ram_write_export => eth1g_ram_mosi.wr,
+ eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ eth1g_reg_address_export => eth1g_reg_mosi.address(3 downto 0),
+ eth1g_reg_read_export => eth1g_reg_mosi.rd,
+ eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ eth1g_reg_write_export => eth1g_reg_mosi.wr,
+ eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ eth1g_tse_address_export => eth1g_tse_mosi.address(9 downto 0),
+ eth1g_tse_read_export => eth1g_tse_mosi.rd,
+ eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ eth1g_tse_write_export => eth1g_tse_mosi.wr,
+ eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ out_port_from_the_pio_debug_wave => OPEN,
+ out_port_from_the_pio_wdi => pout_wdi,
+ pio_pps_address_export => reg_ppsh_mosi.address(0),
+ pio_pps_clk_export => OPEN,
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ pio_pps_reset_export => OPEN,
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(4 downto 0),
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_address_export => ram_diag_bg_mosi.address(10 downto 0),
+ ram_diag_bg_clk_export => OPEN,
+ ram_diag_bg_read_export => ram_diag_bg_mosi.rd,
+ ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ ram_diag_bg_reset_export => OPEN,
+ ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
+ ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(6 downto 0),
+ reg_bsn_monitor_clk_export => OPEN,
+ reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
+ reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_reset_export => OPEN,
+ reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
+ reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_address_export => reg_diag_bg_mosi.address(2 downto 0),
+ reg_diag_bg_clk_export => OPEN,
+ reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
+ reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_bg_reset_export => OPEN,
+ reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
+ reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(6 downto 0),
+ reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
+ reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
+ reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(5 downto 0),
+ reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd,
+ reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
+ reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mdio_0_address_export => reg_mdio_0_mosi.address(2 downto 0),
+ reg_mdio_0_clk_export => OPEN,
+ reg_mdio_0_read_export => reg_mdio_0_mosi.rd,
+ reg_mdio_0_readdata_export => reg_mdio_0_miso.rddata(c_word_w - 1 downto 0),
+ reg_mdio_0_reset_export => OPEN,
+ reg_mdio_0_write_export => reg_mdio_0_mosi.wr,
+ reg_mdio_0_writedata_export => reg_mdio_0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mdio_1_address_export => reg_mdio_1_mosi.address(2 downto 0),
+ reg_mdio_1_clk_export => OPEN,
+ reg_mdio_1_read_export => reg_mdio_1_mosi.rd,
+ reg_mdio_1_readdata_export => reg_mdio_1_miso.rddata(c_word_w - 1 downto 0),
+ reg_mdio_1_reset_export => OPEN,
+ reg_mdio_1_write_export => reg_mdio_1_mosi.wr,
+ reg_mdio_1_writedata_export => reg_mdio_1_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mdio_2_address_export => reg_mdio_2_mosi.address(2 downto 0),
+ reg_mdio_2_clk_export => OPEN,
+ reg_mdio_2_read_export => reg_mdio_2_mosi.rd,
+ reg_mdio_2_readdata_export => reg_mdio_2_miso.rddata(c_word_w - 1 downto 0),
+ reg_mdio_2_reset_export => OPEN,
+ reg_mdio_2_write_export => reg_mdio_2_mosi.wr,
+ reg_mdio_2_writedata_export => reg_mdio_2_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_address_export => reg_tr_10gbe_mosi.address(14 downto 0),
+ reg_tr_10gbe_clk_export => OPEN,
+ reg_tr_10gbe_read_export => reg_tr_10gbe_mosi.rd,
+ reg_tr_10gbe_readdata_export => reg_tr_10gbe_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_reset_export => OPEN,
+ reg_tr_10gbe_waitrequest_export => reg_tr_10gbe_miso.waitrequest,
+ reg_tr_10gbe_write_export => reg_tr_10gbe_mosi.wr,
+ reg_tr_10gbe_writedata_export => reg_tr_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_xaui_address_export => reg_tr_xaui_mosi.address(10 downto 0),
+ reg_tr_xaui_clk_export => OPEN,
+ reg_tr_xaui_read_export => reg_tr_xaui_mosi.rd,
+ reg_tr_xaui_readdata_export => reg_tr_xaui_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_xaui_reset_export => OPEN,
+ reg_tr_xaui_waitrequest_export => reg_tr_xaui_miso.waitrequest,
+ reg_tr_xaui_write_export => reg_tr_xaui_mosi.wr,
+ reg_tr_xaui_writedata_export => reg_tr_xaui_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(2 downto 0),
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_address_export => reg_wdi_mosi.address(0),
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reset_in_reset_n => mm_rst_n,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
index 80c8a90812..6d860cb27f 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, diag_lib, dp_lib, eth_lib, tech_tse_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
-- Purpose:
@@ -87,7 +87,7 @@ entity unb1_tr_10GbE is
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_RSTN : out std_logic := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
- -- So we need to assign a '1' to it.
+ -- So we need to assign a '1' to it.
);
end unb1_tr_10GbE;
@@ -101,14 +101,31 @@ architecture str of unb1_tr_10GbE is
constant c_bg_block_size : natural := 176;
constant c_bg_gapsize : natural := 256 - 176;
constant c_bg_blocks_per_sync : natural := 100;
- constant c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'), -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ sel_a_b(
+ g_sim,
+ '1',
+ '0'), -- enable: On by default in simulation; MM enable required on hardware.
+ '0', -- enable_sync
+ TO_UVEC(
+ c_bg_block_size,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ c_bg_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ c_bg_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ c_bg_block_size-1,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
-- System
signal cs_sim : std_logic;
signal xo_clk : std_logic;
@@ -199,25 +216,25 @@ begin
-- TX: 3 Block generators
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => c_nof_10GbE_streams,
- g_buf_dat_w => 64,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "hex/composite_signals",
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
-
- out_sosi_arr => mms_diag_block_gen_src_out_arr
- );
+ generic map (
+ g_nof_streams => c_nof_10GbE_streams,
+ g_buf_dat_w => 64,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "hex/composite_signals",
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+
+ out_sosi_arr => mms_diag_block_gen_src_out_arr
+ );
-----------------------------------------------------------------------------
@@ -230,129 +247,129 @@ begin
end generate;
u_front_io : entity unb1_board_lib.unb1_board_front_io
- generic map (
- g_nof_xaui => c_nof_10GbE_streams
- )
- port map (
- xaui_tx_arr => unb_xaui_tx_arr,
- xaui_rx_arr => unb_xaui_rx_arr,
-
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL
- );
+ generic map (
+ g_nof_xaui => c_nof_10GbE_streams
+ )
+ port map (
+ xaui_tx_arr => unb_xaui_tx_arr,
+ xaui_rx_arr => unb_xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
u_areset_sa_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map(
- clk => SA_CLK,
- in_rst => '0',
- out_rst => sa_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map(
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_streams,
- g_use_mdio => true
- )
-
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_156 => SA_CLK,
- tr_ref_rst_156 => sa_rst,
-
- -- Calibration & reconfig clock
- cal_rec_clk => mm_clk,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
-
- xaui_mosi => reg_tr_xaui_mosi,
- xaui_miso => reg_tr_xaui_miso,
-
- mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams - 1 downto 0),
- mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams - 1 downto 0),
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_snk_in_arr,
- src_in_arr => dp_offload_rx_snk_out_arr,
-
- -- Serial XAUI IO
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr,
-
- -- MDIO interface
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_streams,
+ g_use_mdio => true
+ )
+
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => mm_clk,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams - 1 downto 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams - 1 downto 0),
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ -- MDIO interface
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
--- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
--- GENERIC MAP (
--- g_nof_streams => c_nof_10GbE_streams,
--- g_data_w => c_xgmii_data_w,
--- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
--- g_remove_crc => FALSE,
--- g_crc_nof_words => 0
--- )
--- PORT MAP (
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
---
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
--- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
---
--- snk_in_arr => dp_offload_rx_snk_in_arr,
--- snk_out_arr => dp_offload_rx_snk_out_arr,
---
--- src_out_arr => dp_offload_rx_src_out_arr,
--- src_in_arr => (OTHERS=>c_dp_siso_rdy), --dp_offload_rx_src_in_arr,
---
--- hdr_fields_out_arr => hdr_fields_out_arr
--- );
---
--- gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
--- dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
--- dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
---
--- dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
--- dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
--- dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
--- dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
--- dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
--- END GENERATE;
+ -- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
+ -- GENERIC MAP (
+ -- g_nof_streams => c_nof_10GbE_streams,
+ -- g_data_w => c_xgmii_data_w,
+ -- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
+ -- g_remove_crc => FALSE,
+ -- g_crc_nof_words => 0
+ -- )
+ -- PORT MAP (
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ --
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ -- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ --
+ -- snk_in_arr => dp_offload_rx_snk_in_arr,
+ -- snk_out_arr => dp_offload_rx_snk_out_arr,
+ --
+ -- src_out_arr => dp_offload_rx_src_out_arr,
+ -- src_in_arr => (OTHERS=>c_dp_siso_rdy), --dp_offload_rx_src_in_arr,
+ --
+ -- hdr_fields_out_arr => hdr_fields_out_arr
+ -- );
+ --
+ -- gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ -- dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
+ -- dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
+ --
+ -- dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+ -- dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ -- dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ -- dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ -- dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
+ -- END GENERATE;
@@ -360,167 +377,167 @@ begin
-- RX: BSN monitors at several stages in the stream
-----------------------------------------------------------------------------
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 5,
- g_sync_timeout => 200000000,
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => dp_bsn_monitor_in_siso_arr,
- in_sosi_arr => dp_bsn_monitor_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => 5,
+ g_sync_timeout => 200000000,
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => dp_bsn_monitor_in_siso_arr,
+ in_sosi_arr => dp_bsn_monitor_in_sosi_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_sim_flash_model => false,
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_flash_model => false,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm_unb1_tr_10GbE : entity work.mmm_unb1_tr_10GbE
- generic map(
- g_sim => g_sim
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- pout_wdi => pout_wdi,
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- reg_mdio_0_mosi => reg_mdio_0_mosi,
- reg_mdio_0_miso => reg_mdio_0_miso,
- reg_mdio_1_mosi => reg_mdio_1_mosi,
- reg_mdio_1_miso => reg_mdio_1_miso,
- reg_mdio_2_mosi => reg_mdio_2_mosi,
- reg_mdio_2_miso => reg_mdio_2_miso,
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
- reg_tr_10gbe_miso => reg_tr_10gbe_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
- );
+ generic map(
+ g_sim => g_sim
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ pout_wdi => pout_wdi,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ reg_mdio_0_mosi => reg_mdio_0_mosi,
+ reg_mdio_0_miso => reg_mdio_0_miso,
+ reg_mdio_1_mosi => reg_mdio_1_mosi,
+ reg_mdio_1_miso => reg_mdio_1_miso,
+ reg_mdio_2_mosi => reg_mdio_2_mosi,
+ reg_mdio_2_miso => reg_mdio_2_miso,
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+ reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
+ reg_tr_10gbe_miso => reg_tr_10gbe_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ );
reg_mdio_mosi_arr(0) <= reg_mdio_0_mosi;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
index f03ca1a313..d537d80a13 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
@@ -25,11 +25,11 @@
-- Usage:
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_tr_10GbE is
end tb_unb1_tr_10GbE;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
index 446603b1de..2c5339f935 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
@@ -26,17 +26,17 @@
-- . node_<design_name>.vhd with the actual functionality of <design_name>
library IEEE, common_lib, mm_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb1_board is
generic (
@@ -370,31 +370,31 @@ begin
gen_pll: if g_dp_clk_use_pll = true generate
u_unb1_board_clk200_pll : entity work.unb1_board_clk200_pll
- generic map (
- g_technology => g_technology,
- g_sel => c_dp_clk_pll_sel,
- g_clk200_phase_shift => g_dp_clk_phase,
- g_clk_vec_w => g_dp_phs_clk_vec_w,
- g_clk1_phase_shift => c_dp_clk1_phase, -- dp_phs_clk_vec(0)
- g_clk2_phase_shift => c_dp_clk2_phase, -- dp_phs_clk_vec(1)
- g_clk3_phase_shift => c_dp_clk3_phase, -- dp_phs_clk_vec(2)
- g_clk4_phase_shift => c_dp_clk4_phase, -- dp_phs_clk_vec(3)
- g_clk5_phase_shift => c_dp_clk5_phase, -- dp_phs_clk_vec(4)
- g_clk6_phase_shift => c_dp_clk6_phase, -- dp_phs_clk_vec(5)
- g_clk1_divide_by => g_dp_phs_clk_divide_by,
- g_clk2_divide_by => g_dp_phs_clk_divide_by,
- g_clk3_divide_by => g_dp_phs_clk_divide_by,
- g_clk4_divide_by => g_dp_phs_clk_divide_by,
- g_clk5_divide_by => g_dp_phs_clk_divide_by,
- g_clk6_divide_by => g_dp_phs_clk_divide_by
- )
- port map (
- arst => dp_dis,
- clk200 => ext_clk,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => dp_rst,
- st_clk_vec => dp_phs_clk_vec -- PLL c6-c1
- );
+ generic map (
+ g_technology => g_technology,
+ g_sel => c_dp_clk_pll_sel,
+ g_clk200_phase_shift => g_dp_clk_phase,
+ g_clk_vec_w => g_dp_phs_clk_vec_w,
+ g_clk1_phase_shift => c_dp_clk1_phase, -- dp_phs_clk_vec(0)
+ g_clk2_phase_shift => c_dp_clk2_phase, -- dp_phs_clk_vec(1)
+ g_clk3_phase_shift => c_dp_clk3_phase, -- dp_phs_clk_vec(2)
+ g_clk4_phase_shift => c_dp_clk4_phase, -- dp_phs_clk_vec(3)
+ g_clk5_phase_shift => c_dp_clk5_phase, -- dp_phs_clk_vec(4)
+ g_clk6_phase_shift => c_dp_clk6_phase, -- dp_phs_clk_vec(5)
+ g_clk1_divide_by => g_dp_phs_clk_divide_by,
+ g_clk2_divide_by => g_dp_phs_clk_divide_by,
+ g_clk3_divide_by => g_dp_phs_clk_divide_by,
+ g_clk4_divide_by => g_dp_phs_clk_divide_by,
+ g_clk5_divide_by => g_dp_phs_clk_divide_by,
+ g_clk6_divide_by => g_dp_phs_clk_divide_by
+ )
+ port map (
+ arst => dp_dis,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => dp_rst,
+ st_clk_vec => dp_phs_clk_vec -- PLL c6-c1
+ );
end generate;
no_pll: if g_dp_clk_use_pll = false and g_dp_clk_use_xo_pll = false generate
@@ -425,75 +425,75 @@ begin
end generate;
u_unb1_board_clk25_pll : entity work.unb1_board_clk25_pll
- generic map (
- g_technology => g_technology
- )
- port map (
- arst => i_xo_rst,
- clk25 => i_xo_clk,
- c0_clk20 => clk20M,
- c1_clk40 => clk40M,
- c2_clk50 => clk50M,
- c3_clk125 => clk125M,
- c4_clk200 => clk200M,
- pll_locked => mm_locked_out
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk25 => i_xo_clk,
+ c0_clk20 => clk20M,
+ c1_clk40 => clk40M,
+ c2_clk50 => clk50M,
+ c3_clk125 => clk125M,
+ c4_clk200 => clk200M,
+ pll_locked => mm_locked_out
+ );
end generate;
u_unb1_board_node_ctrl : entity work.unb1_board_node_ctrl
- generic map (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => i_xo_clk,
- xo_rst_n => i_xo_rst_n,
- sys_clk => mm_clk,
- sys_locked => mm_locked,
- sys_rst => i_mm_rst,
- cal_clk => '0',
- cal_rst => OPEN,
- st_clk => node_ctrl_dp_clk_in,
- st_rst => node_ctrl_dp_rst_out,
- wdi_in => pout_wdi,
- wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- pulse_us => OPEN,
- pulse_ms => mm_pulse_ms,
- pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
+ generic map (
+ g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ xo_clk => i_xo_clk,
+ xo_rst_n => i_xo_rst_n,
+ sys_clk => mm_clk,
+ sys_locked => mm_locked,
+ sys_rst => i_mm_rst,
+ cal_clk => '0',
+ cal_rst => OPEN,
+ st_clk => node_ctrl_dp_clk_in,
+ st_rst => node_ctrl_dp_rst_out,
+ wdi_in => pout_wdi,
+ wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ pulse_us => OPEN,
+ pulse_ms => mm_pulse_ms,
+ pulse_s => mm_pulse_s -- could be used to toggle a LED
+ );
-- System info
cs_sim <= is_true(g_sim);
u_mms_unb1_board_system_info : entity work.mms_unb1_board_system_info
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_use_phy => g_use_phy,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version,
- g_technology => g_technology
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_use_phy => g_use_phy,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
@@ -531,12 +531,12 @@ begin
led_toggle_green <= sel_a_b(g_design_name(1 to 8) /= "unb1_min", led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
@@ -548,15 +548,15 @@ begin
WDI <= sel_a_b(g_use_phy.wdi, mm_wdi or temp_alarm or wdi_override, 'Z');
u_unb1_board_wdi_reg : entity work.unb1_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
@@ -567,15 +567,15 @@ begin
-- and reconfigure from that address.
gen_mms_remu : if c_use_flash = true generate -- enable on HW, disable to save simulation time when not used in tb
u_mms_remu : entity remu_lib.mms_remu
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
end generate;
no_remu_in_sim : if c_use_flash = false generate
@@ -588,31 +588,31 @@ begin
-----------------------------------------------------------------------------
gen_mms_epcs : if c_use_flash = true generate -- enable on HW, disable to save simulation time when not used in tb
u_mms_epcs : entity epcs_lib.mms_epcs
- generic map (
- g_sim_flash_model => g_sim_flash_model,
- g_protect_addr_range => g_epcs_protect_addr_range
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sim_flash_model => g_sim_flash_model,
+ g_protect_addr_range => g_epcs_protect_addr_range
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
end generate;
no_epcs_in_sim : if c_use_flash = false generate
@@ -627,45 +627,45 @@ begin
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => mms_ppsh_pps_sys
- );
+ generic map (
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => mms_ppsh_pps_sys
+ );
------------------------------------------------------------------------------
-- PPS delay
------------------------------------------------------------------------------
gen_mms_common_pulse_delay : if g_pps_delay_max > 0 generate
u_mms_common_pulse_delay : entity common_lib.mms_common_pulse_delay
- generic map (
- g_pulse_delay_max => g_pps_delay_max,
- g_register_out => true
- )
- port map (
- pulse_clk => dp_clk_in,
- pulse_rst => dp_rst_in,
- pulse_in => mms_ppsh_pps_sys,
- pulse_out => dp_pps,
-
- mm_clk => mm_clk,
- mm_rst => i_mm_rst,
- reg_mosi => reg_common_pulse_delay_mosi,
- reg_miso => reg_common_pulse_delay_miso
- );
+ generic map (
+ g_pulse_delay_max => g_pps_delay_max,
+ g_register_out => true
+ )
+ port map (
+ pulse_clk => dp_clk_in,
+ pulse_rst => dp_rst_in,
+ pulse_in => mms_ppsh_pps_sys,
+ pulse_out => dp_pps,
+
+ mm_clk => mm_clk,
+ mm_rst => i_mm_rst,
+ reg_mosi => reg_common_pulse_delay_mosi,
+ reg_miso => reg_common_pulse_delay_miso
+ );
end generate;
no_mms_common_pulse_delay : if g_pps_delay_max = 0 generate
@@ -679,28 +679,28 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms; -- speed up in simulation
u_mms_unb1_board_sens : entity work.mms_unb1_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_mm_clk_freq,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => sens_sc,
- sda => sens_sd,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_mm_clk_freq,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => sens_sc,
+ sda => sens_sd,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
@@ -731,44 +731,44 @@ begin
u_mac : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_sim => g_sim,
- g_sim_level => g_sim_level
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => mm_clk, -- use mm_clk direct
- eth_clk => eth1g_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT,
- eth_rxp => ETH_SGIN,
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => mm_clk, -- use mm_clk direct
+ eth_clk => eth1g_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT,
+ eth_rxp => ETH_SGIN,
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
index dc25926e50..2d6ce03029 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb1_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb1_board_sens is
@@ -68,46 +68,46 @@ architecture str of mms_unb1_board_sens is
begin
u_unb1_board_sens_reg : entity work.unb1_board_sens_reg
- generic map (
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both BN3 and all nodes implies that sens_err is only valid for BN3.
- sens_data => sens_data,
-
- -- Max temp threshold
- temp_high => temp_high
- );
+ generic map (
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both BN3 and all nodes implies that sens_err is only valid for BN3.
+ sens_data => sens_data,
+
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb1_board_sens : entity work.unb1_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => c_sens_nof_result
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => c_sens_nof_result
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
index c5a41f645f..7065f8dc56 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb1_board_system_info is
generic (
@@ -59,7 +59,7 @@ entity mms_unb1_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb1_board_system_info;
@@ -71,72 +71,74 @@ architecture str of mms_unb1_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0'
+ );
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb1_board_system_info: entity work.unb1_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb1_board_system_info_reg: entity work.unb1_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_use_phy => g_use_phy,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_use_phy => g_use_phy,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
index 08fd646a24..dd25e17788 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -124,13 +124,13 @@
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_fn_terminal_db is
@@ -241,7 +241,7 @@ architecture str of node_unb1_fn_terminal_db is
signal rx_usr_siso_arr : t_dp_siso_arr(g_usr_nof_streams - 1 downto 0);
signal rx_usr_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Data buffer
-----------------------------------------------------------------------------
signal db_in_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
@@ -254,67 +254,67 @@ begin
-----------------------------------------------------------------------------
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_fn,
- g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_usr_nof_streams_per_bus,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
- g_tx_input_use_fifo => false, -- no user Tx
- -- Rx
- g_use_rx => true, -- user Rx must be TRUE for DB in FN,
- g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
-
- -- Mesh interface level (4 nodes)(4 lanes)
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr, -- Tx
- rx_serial_2arr => rx_serial_2arr, -- Rx
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_fn,
+ g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_usr_nof_streams_per_bus,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
+ g_tx_input_use_fifo => false, -- no user Tx
+ -- Rx
+ g_use_rx => true, -- user Rx must be TRUE for DB in FN,
+ g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
+
+ -- Mesh interface level (4 nodes)(4 lanes)
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr, -- Tx
+ rx_serial_2arr => rx_serial_2arr, -- Rx
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- Forward the received streams, rewire for single or multi UniBoard use
@@ -350,51 +350,51 @@ begin
gen_align : if g_use_bsn_align = true generate
u_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => g_usr_block_len,
- g_nof_input => g_usr_nof_streams,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => c_burst_bsn_latency,
- g_bsn_request_pipeline => c_bsn_request_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => rx_usr_siso_arr,
- snk_in_arr => rx_usr_sosi_arr,
- -- ST source
- src_in_arr => dp_out_siso_arr,
- src_out_arr => db_in_sosi_arr,
- -- MM
- in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr => (others => '1') -- default all user inputs are enabled
- );
+ generic map (
+ g_block_size => g_usr_block_len,
+ g_nof_input => g_usr_nof_streams,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => c_burst_bsn_latency,
+ g_bsn_request_pipeline => c_bsn_request_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => rx_usr_siso_arr,
+ snk_in_arr => rx_usr_sosi_arr,
+ -- ST source
+ src_in_arr => dp_out_siso_arr,
+ src_out_arr => db_in_sosi_arr,
+ -- MM
+ in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_arr => (others => '1') -- default all user inputs are enabled
+ );
u_bsn_monitor_align : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
- g_cross_clock_domain => true,
- g_sync_timeout => g_mesh_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => db_in_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_mesh_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => db_in_sosi_arr(0 downto 0)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -407,27 +407,27 @@ begin
gen_data_buf : if g_use_data_buf = true generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_usr_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => db_in_sosi_arr(0).sync,
- in_sosi_arr => db_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_usr_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => db_in_sosi_arr(0).sync,
+ in_sosi_arr => db_in_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
index e7e030fc9e..131eb3b810 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_io is
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
index f5d68d2f2c..91ae17506c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
@@ -53,11 +53,11 @@
-- . See unb1_board_back_model_sl.vhd for the Apertif backplane model
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_reorder is
@@ -100,69 +100,69 @@ begin
-- Map the usr busses for the other UniBoards to the phy busses 2:0
case TO_UINT(bck_id) is
when 0 =>
- -- UniBoard 0 connects to UniBoards 3,2,1 via phy busses 0,2,1
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ -- UniBoard 0 connects to UniBoards 3,2,1 via phy busses 0,2,1
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
when 1 =>
- -- UniBoard 1 connects to UniBoards 3,2,0 via phy busses 0,1,2
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1); -- from unb 2
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ -- UniBoard 1 connects to UniBoards 3,2,0 via phy busses 0,1,2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1); -- from unb 2
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
when 2 =>
- -- UniBoard 2 connects to UniBoards 3,1,0 via phy busses 1,0,2
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0); -- from unb 1
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1); -- from unb 3
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
+ -- UniBoard 2 connects to UniBoards 3,1,0 via phy busses 1,0,2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0); -- from unb 1
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1); -- from unb 3
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
when 3 =>
- -- UniBoard 3 connects to UniBoards 2,1,0 via phy busses 2,1,0
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0); -- from unb 0
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+ -- UniBoard 3 connects to UniBoards 2,1,0 via phy busses 2,1,0
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0); -- from unb 0
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
when others => null;
end case;
end process;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
index 54e4572ae6..bb75cadd21 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
@@ -36,11 +36,11 @@
-- are ignored.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_select is
port (
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
index 8d04d02cc6..b9975ddc82 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
@@ -26,13 +26,13 @@
-- except for the SOSI entity I/O types and the monitor outputs.
library IEEE, common_lib, dp_lib, uth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use work.unb1_board_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use work.unb1_board_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_back_uth_terminals_bidir is
generic (
@@ -87,51 +87,51 @@ begin
gen_bus : for I in 0 to c_unb1_board_tr_back.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => g_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_mux_mode => c_tx_mux_mode,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- usr side interface
- tx_dp_sosi_arr => tx_dp_sosi_2arr(I),
- tx_dp_siso_arr => tx_dp_siso_2arr(I),
-
- rx_dp_sosi_arr => rx_dp_sosi_2arr(I),
- rx_dp_siso_arr => rx_dp_siso_2arr(I),
-
- -- phy side interface
- tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
-
- rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
-
- -- monitoring interface
- rx_mon_pkt_sosi_arr => OPEN,
- rx_mon_dist_sosi_arr => open
- );
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => g_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_mux_mode => c_tx_mux_mode,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- usr side interface
+ tx_dp_sosi_arr => tx_dp_sosi_2arr(I),
+ tx_dp_siso_arr => tx_dp_siso_2arr(I),
+
+ rx_dp_sosi_arr => rx_dp_sosi_2arr(I),
+ rx_dp_siso_arr => rx_dp_siso_2arr(I),
+
+ -- phy side interface
+ tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+
+ rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+
+ -- monitoring interface
+ rx_mon_pkt_sosi_arr => OPEN,
+ rx_mon_dist_sosi_arr => open
+ );
end generate;
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
index 87130a8e65..887af8b991 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -108,9 +108,9 @@ entity unb1_board_clk200_pll is
g_clk3_phase_shift : string := "313"; -- = 022.5 = st_clk_vec[3]
g_clk4_phase_shift : string := "469"; -- = 033.75 = st_clk_vec[4]
g_clk5_phase_shift : string := "625"; -- = 045 = st_clk_vec[5]
- -- "781"; -- = 056.25
+ -- "781"; -- = 056.25
g_clk6_phase_shift : string := "938"; -- = 067.5 = st_clk_vec[6]
- -- "1094"; -- = 078.75
+ -- "1094"; -- = 078.75
g_clk1_divide_by : natural := 32; -- = clk 200/32 MHz
g_clk2_divide_by : natural := 32; -- = clk 200/32 MHz
g_clk3_divide_by : natural := 32; -- = clk 200/32 MHz
@@ -167,97 +167,97 @@ begin
gen_0 : if g_sel = 0 generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_1 : if g_sel = 1 generate
i_st_clk200p <= i_st_clk_vec(0);
u_st_pll_p6 : entity tech_pll_lib.tech_pll_clk200_p6
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk0_phase_shift,
- g_clk1_used => c_clk1_used,
- g_clk2_used => c_clk2_used,
- g_clk3_used => c_clk3_used,
- g_clk4_used => c_clk4_used,
- g_clk5_used => c_clk5_used,
- g_clk6_used => c_clk6_used,
- g_clk1_divide_by => g_clk1_divide_by,
- g_clk2_divide_by => g_clk2_divide_by,
- g_clk3_divide_by => g_clk3_divide_by,
- g_clk4_divide_by => g_clk4_divide_by,
- g_clk5_divide_by => g_clk5_divide_by,
- g_clk6_divide_by => g_clk6_divide_by,
- g_clk1_phase_shift => g_clk1_phase_shift,
- g_clk2_phase_shift => g_clk2_phase_shift,
- g_clk3_phase_shift => g_clk3_phase_shift,
- g_clk4_phase_shift => g_clk4_phase_shift,
- g_clk5_phase_shift => g_clk5_phase_shift,
- g_clk6_phase_shift => g_clk6_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200,
- c0 => i_st_clk200,
- c1 => i_st_clk_vec(0),
- c2 => i_st_clk_vec(1),
- c3 => i_st_clk_vec(2),
- c4 => i_st_clk_vec(3),
- c5 => i_st_clk_vec(4),
- c6 => i_st_clk_vec(5),
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk0_phase_shift,
+ g_clk1_used => c_clk1_used,
+ g_clk2_used => c_clk2_used,
+ g_clk3_used => c_clk3_used,
+ g_clk4_used => c_clk4_used,
+ g_clk5_used => c_clk5_used,
+ g_clk6_used => c_clk6_used,
+ g_clk1_divide_by => g_clk1_divide_by,
+ g_clk2_divide_by => g_clk2_divide_by,
+ g_clk3_divide_by => g_clk3_divide_by,
+ g_clk4_divide_by => g_clk4_divide_by,
+ g_clk5_divide_by => g_clk5_divide_by,
+ g_clk6_divide_by => g_clk6_divide_by,
+ g_clk1_phase_shift => g_clk1_phase_shift,
+ g_clk2_phase_shift => g_clk2_phase_shift,
+ g_clk3_phase_shift => g_clk3_phase_shift,
+ g_clk4_phase_shift => g_clk4_phase_shift,
+ g_clk5_phase_shift => g_clk5_phase_shift,
+ g_clk6_phase_shift => g_clk6_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200,
+ c0 => i_st_clk200,
+ c1 => i_st_clk_vec(0),
+ c2 => i_st_clk_vec(1),
+ c3 => i_st_clk_vec(2),
+ c4 => i_st_clk_vec(3),
+ c5 => i_st_clk_vec(4),
+ c6 => i_st_clk_vec(5),
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end stratix4;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
index f868d0815e..c010e592c8 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -55,17 +55,17 @@ architecture stratixiv of unb1_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk40,
- c2 => c2_clk50,
- c3 => c3_clk125,
- c4 => c4_clk200,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk40,
+ c2 => c2_clk50,
+ c3 => c3_clk125,
+ c4 => c4_clk200,
+ locked => pll_locked
+ );
end stratixiv;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
index 8154e03d5b..92b302f56c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -59,28 +59,28 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
index b5d260b21b..1ea808a1f1 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_front_io is
@@ -82,48 +82,48 @@ begin
-- MDIO buffers
gen_iobuf_0 : if g_nof_xaui > 0 generate
u_iobuf_0 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(0),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(0)
- );
+ port map (
+ dat_inout => SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(0),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(0)
+ );
SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(0);
end generate;
gen_iobuf_1 : if g_nof_xaui > 1 generate
u_iobuf_1 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(1),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(1)
- );
+ port map (
+ dat_inout => SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(1),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(1)
+ );
SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(1);
end generate;
gen_iobuf_2 : if g_nof_xaui > 2 generate
u_iobuf_2 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(2),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(2)
- );
+ port map (
+ dat_inout => SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(2),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(2)
+ );
SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(2);
end generate;
gen_iobuf_3 : if g_nof_xaui > 3 generate
u_iobuf_3 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(3),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(3)
- );
+ port map (
+ dat_inout => SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(3),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(3)
+ );
SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(3);
end generate;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
index f33599ea0c..a20e4093ad 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_io is
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
index 7a5783e637..68a8a71253 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
@@ -133,11 +133,11 @@
-- unb1_board_mesh_model_sl.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_bidir is
@@ -169,32 +169,32 @@ architecture str of unb1_board_mesh_reorder_bidir is
begin
u_tx : entity work.unb1_board_mesh_reorder_tx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_reorder
- )
- port map (
- chip_id => chip_id,
- clk => tx_clk,
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- tx_phy_sosi_2arr => tx_phy_sosi_2arr,
- rx_phy_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => tx_clk,
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ tx_phy_sosi_2arr => tx_phy_sosi_2arr,
+ rx_phy_siso_2arr => rx_phy_siso_2arr
+ );
u_rx : entity work.unb1_board_mesh_reorder_rx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_reorder
- )
- port map (
- chip_id => chip_id,
- clk => rx_clk,
- rx_phy_sosi_2arr => rx_phy_sosi_2arr,
- tx_phy_siso_2arr => tx_phy_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
- tx_usr_siso_2arr => tx_usr_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => rx_clk,
+ rx_phy_sosi_2arr => rx_phy_sosi_2arr,
+ tx_phy_siso_2arr => tx_phy_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+ tx_usr_siso_2arr => tx_usr_siso_2arr
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
index 4957fde240..20073dbef5 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
@@ -31,11 +31,11 @@
-- . Indexing for *_2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_rx is
@@ -97,7 +97,7 @@ begin
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(1);
when 4 |
5 => -- this is BN0
- -- or BN1, connect phy bus 0,1,2,3 to usr bus 3,2,1,0
+ -- or BN1, connect phy bus 0,1,2,3 to usr bus 3,2,1,0
-- sosi
rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
index ef2d9e406c..ceb09e6773 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
@@ -31,11 +31,11 @@
-- . Indexing for *_2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_tx is
@@ -64,19 +64,19 @@ begin
-- Register the chip_id from FPGA pins to ease timing closure.
-- . Alternatively these registers may better be removed and pin input chip_id[] set as false path for timing closure
u_chip_id : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => c_meta_delay_len,
- g_reset_value => 0,
- g_in_dat_w => chip_id'LENGTH,
- g_out_dat_w => chip_id'length
- )
- port map (
- rst => '0',
- clk => clk,
- in_dat => chip_id,
- out_dat => chip_id_reg
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => c_meta_delay_len,
+ g_reset_value => 0,
+ g_in_dat_w => chip_id'LENGTH,
+ g_out_dat_w => chip_id'length
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ in_dat => chip_id,
+ out_dat => chip_id_reg
+ );
-- force chip_id(2) to '0' or '1' to reduce the case options in p_comb if the design will run only on a FN or only on a BN
chip_id_i <= func_unb1_board_chip_id(chip_id_reg, g_node_type);
@@ -115,7 +115,7 @@ begin
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
when 4 |
5 => -- this is BN0
- -- or BN1, connect usr bus 0,1,2,3 to phy bus 3,2,1,0
+ -- or BN1, connect usr bus 0,1,2,3 to phy bus 3,2,1,0
-- sosi
tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(0);
tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
index 23e79b3b51..e960ef79cb 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
@@ -26,13 +26,13 @@
-- except for the SOSI entity I/O types and the monitor outputs.
library IEEE, common_lib, dp_lib, uth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use work.unb1_board_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use work.unb1_board_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_mesh_uth_terminals_bidir is
generic (
@@ -94,54 +94,54 @@ begin
gen_uth_terminal_bidir : for I in 0 to c_unb1_board_tr_mesh.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => g_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_mux_mode => c_tx_mux_mode,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- usr side interface
- tx_dp_sosi_arr => tx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
- tx_dp_siso_arr => tx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
-
- rx_dp_sosi_arr => rx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
- rx_dp_siso_arr => rx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
-
- -- phy side interface
- tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
-
- rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
-
- -- monitoring interface
- rx_mon_pkt_sosi_arr => rx_mon_pkt_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_mon_dist_sosi_arr => rx_mon_dist_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0)
- );
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => g_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_mux_mode => c_tx_mux_mode,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- usr side interface
+ tx_dp_sosi_arr => tx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ tx_dp_siso_arr => tx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
+
+ rx_dp_sosi_arr => rx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ rx_dp_siso_arr => rx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
+
+ -- phy side interface
+ tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+
+ rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+
+ -- monitoring interface
+ rx_mon_pkt_sosi_arr => rx_mon_pkt_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_mon_dist_sosi_arr => rx_mon_dist_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
index 39383ca4e8..720de1a39d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Provide the basic node control along with an SOPC Builder system:
@@ -70,60 +70,60 @@ begin
pulse_ms <= i_pulse_ms;
u_unb1_board_clk_rst : entity work.unb1_board_clk_rst
- port map (
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => i_sys_rst -- release reset some clock cycles after sys_locked went high
- );
+ port map (
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => i_sys_rst -- release reset some clock cycles after sys_locked went high
+ );
u_common_areset_cal : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
- clk => cal_clk,
- out_rst => cal_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
+ clk => cal_clk,
+ out_rst => cal_rst
+ );
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
- clk => st_clk,
- out_rst => st_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
+ clk => st_clk,
+ out_rst => st_rst
+ );
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_sys_rst,
- clk => sys_clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_sys_rst,
+ clk => sys_clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => pulse_s
+ );
u_unb1_board_wdi_extend : entity work.unb1_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_sys_rst,
- clk => sys_clk,
- pulse_ms => i_pulse_ms,
- wdi_in => wdi_in,
- wdi_out => wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_sys_rst,
+ clk => sys_clk,
+ pulse_ms => i_pulse_ms,
+ wdi_in => wdi_in,
+ wdi_out => wdi_out
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
index 5cf82154fe..43a370e131 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb1_board_peripherals_pkg is
@@ -76,10 +76,10 @@ package unb1_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
index 086c5a29f0..53907db77d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb1_board_pkg is
@@ -197,7 +197,7 @@ package unb1_board_pkg is
use_lvds_clk_rst : boolean; -- = FALSE; -- When TRUE then support reset pulse to ADU to align the lvds_clk to the dp_clk, else no support
lvds_clk_phase : natural; -- = 0; -- Use PLL phase 0 for center aligned. Only for no DPA
nof_clocks : natural; -- = 2; -- 1 --> Use ADC BI clock D or dp_clk and 32 bit port ABCD
- -- 2 --> Use ADC BI clock A, D and 16 bit ports AB, CD
+ -- 2 --> Use ADC BI clock A, D and 16 bit ports AB, CD
lvds_deser_factor : natural; -- = 2; -- The ADC sampled data comes in with a DDR lvds_clk, so lvds_data_rate / 2
dp_deser_factor : natural; -- = 4; -- The Data Path clock dp_clk frequency is 200 MHz, so lvds_data_rate / 4
end record;
@@ -216,7 +216,7 @@ package unb1_board_pkg is
-- DDR3 (definitions similar as in ug_altmemphy.pdf)
type t_unb1_board_ddr_in is record
evt : std_logic;
- --nc : STD_LOGIC; -- not connect, needed to be able to initialize constant record which has to have more than one field in VHDL
+ --nc : STD_LOGIC; -- not connect, needed to be able to initialize constant record which has to have more than one field in VHDL
end record;
type t_unb1_board_ddr_inout is record
@@ -258,7 +258,7 @@ package unb1_board_pkg is
type t_c_unb1_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:3], ID part from back plane
chip_id : natural; -- = id[2:0], ID part from UniBoard
is_bn : natural; -- = id[2], 0 for Front Node, 1 for Back Node
@@ -266,35 +266,38 @@ package unb1_board_pkg is
is_bn3 : natural; -- 1 for Back Node 3, else 0.
end record;
- function func_unb1_board_system_info(VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info;
+ function func_unb1_board_system_info (
+ VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info;
- function func_unb1_board_chip_id(chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
- node_type : in t_e_unb1_board_node) return std_logic_vector;
+ function func_unb1_board_chip_id (
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
+ node_type : in t_e_unb1_board_node) return std_logic_vector;
-- Connect: out_2arr = in_2arr of different types
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr;
+ function func_unb1_board_connect_2arr (in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
+ function func_unb1_board_connect_2arr (in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr;
+ function func_unb1_board_connect_2arr (in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
+ function func_unb1_board_connect_2arr (in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr;
-- Transpose: out_2arr(J)(I) = in_2arr(I)(J) for different types
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_mesh_siso_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_back_sosi_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_back_siso_2arr;
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr;
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr;
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_mesh_siso_2arr;
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_back_sosi_2arr;
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_back_siso_2arr;
end unb1_board_pkg;
package body unb1_board_pkg is
- function func_unb1_board_system_info(VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info is
+ function func_unb1_board_system_info (
+ VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info is
variable v_system_info : t_c_unb1_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
@@ -307,8 +310,9 @@ package body unb1_board_pkg is
return v_system_info;
end;
- function func_unb1_board_chip_id(chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
- node_type : in t_e_unb1_board_node) return std_logic_vector is
+ function func_unb1_board_chip_id (
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
+ node_type : in t_e_unb1_board_node) return std_logic_vector is
variable v_chip_id : std_logic_vector(chip_id'range); -- [2:0]
begin
v_chip_id := chip_id; -- default for design that can run on either FN or BN
@@ -325,7 +329,7 @@ package body unb1_board_pkg is
-- Connect mesh 2arr - back 2arr
------------------------------------------------------------------------------
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr is
+ function func_unb1_board_connect_2arr (in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4 = c_unb1_board_tr_back_hw_nof_bus
constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4 = c_unb1_board_tr_back_hw_bus_w
@@ -339,7 +343,7 @@ package body unb1_board_pkg is
return v_out_2arr;
end;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr is
+ function func_unb1_board_connect_2arr (in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4 = c_unb1_board_tr_back_hw_nof_bus
constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4 = c_unb1_board_tr_back_hw_bus_w
@@ -353,7 +357,7 @@ package body unb1_board_pkg is
return v_out_2arr;
end;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
+ function func_unb1_board_connect_2arr (in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
@@ -367,7 +371,7 @@ package body unb1_board_pkg is
return v_out_2arr;
end;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr is
+ function func_unb1_board_connect_2arr (in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
@@ -385,7 +389,7 @@ package body unb1_board_pkg is
-- Transpose mesh 2arr - back 2arr
------------------------------------------------------------------------------
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr is
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4 = c_unb1_board_tr_back_hw_nof_bus
constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4 = c_unb1_board_tr_back_hw_bus_w
@@ -399,7 +403,7 @@ package body unb1_board_pkg is
return v_out_2arr;
end;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr is
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4 = c_unb1_board_tr_back_hw_nof_bus
constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4 = c_unb1_board_tr_back_hw_bus_w
@@ -413,7 +417,7 @@ package body unb1_board_pkg is
return v_out_2arr;
end;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
@@ -427,7 +431,7 @@ package body unb1_board_pkg is
return v_out_2arr;
end;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr is
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4 = c_unb1_board_tr_mesh_hw_nof_bus
constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4 = c_unb1_board_tr_mesh_hw_bus_w
@@ -445,7 +449,7 @@ package body unb1_board_pkg is
-- Transpose mesh 2arr -mesh 2arr
------------------------------------------------------------------------------
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_mesh_sosi_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4
constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4
@@ -459,7 +463,7 @@ package body unb1_board_pkg is
return v_out_2arr;
end;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_mesh_siso_2arr is
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_mesh_siso_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_mesh_hw_nof_bus; -- = 4
constant c_bus_w : natural := c_unb1_board_tr_mesh_hw_bus_w; -- = 4
@@ -477,7 +481,7 @@ package body unb1_board_pkg is
-- Transpose back 2arr -back 2arr
------------------------------------------------------------------------------
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_back_sosi_2arr is
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_back_sosi_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4
constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4
@@ -491,7 +495,7 @@ package body unb1_board_pkg is
return v_out_2arr;
end;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_back_siso_2arr is
+ function func_unb1_board_transpose_2arr (in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_back_siso_2arr is
constant c_nof_bus : natural := c_unb1_board_tr_back_hw_nof_bus; -- = 4
constant c_bus_w : natural := c_unb1_board_tr_back_hw_bus_w; -- = 4
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
index 572c988f6c..57db8fc69e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
entity unb1_board_sens is
@@ -52,7 +52,7 @@ architecture str of unb1_board_sens is
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
@@ -67,44 +67,44 @@ architecture str of unb1_board_sens is
begin
u_unb1_board_sens_ctrl : entity work.unb1_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_i2c_phy => c_sens_phy
+ )
+ port map (
+ gs_sim => g_sim,
+ clk => clk,
+ rst => rst,
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
+ );
end architecture;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
index 6e8d2bb9f7..8afdbcd7a3 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb1_board_sens_ctrl is
@@ -65,11 +65,23 @@ architecture rtl of unb1_board_sens_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , FPGA_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , HOTSWAP_LTC4260_ADR, LTC4260_CMD_SENSE,
- SMBUS_READ_BYTE , HOTSWAP_LTC4260_ADR, LTC4260_CMD_SOURCE,
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_READ_BYTE ,
+ FPGA_MAX1617_ADR,
+ MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE ,
+ ETH_MAX1617_ADR,
+ MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE ,
+ HOTSWAP_LTC4260_ADR,
+ LTC4260_CMD_SENSE,
+ SMBUS_READ_BYTE ,
+ HOTSWAP_LTC4260_ADR,
+ LTC4260_CMD_SOURCE,
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
index 0ef3eb536c..35be2d84d4 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb1_board_sens_reg is
generic (
@@ -94,13 +94,15 @@ architecture rtl of unb1_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
-
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ -- +1 to fit sens_err in the last address
+
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0'
+ );
signal i_temp_high : std_logic_vector(6 downto 0);
@@ -134,11 +136,11 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
-- Read access: get register value
@@ -154,7 +156,7 @@ begin
else
sla_out.rddata(6 downto 0) <= i_temp_high;
end if;
- -- else unused addresses read zero
+ -- else unused addresses read zero
end if;
end if;
end process;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
index 4a653cd776..c331aeeb7f 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
index f8bc591fea..2628406728 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_system_info_reg is
generic (
@@ -69,7 +69,7 @@ entity unb1_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb1_board_system_info_reg;
@@ -82,21 +82,23 @@ architecture rtl of unb1_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0'
+ );
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := TO_UVEC(g_use_phy.eth1g, 1) &
- TO_UVEC(g_use_phy.tr_front,1) &
- TO_UVEC(g_use_phy.tr_mesh, 1) &
- TO_UVEC(g_use_phy.tr_back, 1) &
- TO_UVEC(g_use_phy.ddr3_I, 1) &
- TO_UVEC(g_use_phy.ddr3_II, 1) &
- TO_UVEC(g_use_phy.adc, 1) &
- TO_UVEC(g_use_phy.wdi, 1);
+ TO_UVEC(g_use_phy.tr_front,1) &
+ TO_UVEC(g_use_phy.tr_mesh, 1) &
+ TO_UVEC(g_use_phy.tr_back, 1) &
+ TO_UVEC(g_use_phy.ddr3_I, 1) &
+ TO_UVEC(g_use_phy.ddr3_II, 1) &
+ TO_UVEC(g_use_phy.adc, 1) &
+ TO_UVEC(g_use_phy.wdi, 1);
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
index 5fc47736ae..98ccc6ae68 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
@@ -34,14 +34,14 @@
-- g_use_tx and g_use_rx because they are both TRUE.
library IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_terminals_back is
@@ -141,80 +141,80 @@ architecture str of unb1_board_terminals_back is
begin
u_unb1_board_back_select: entity work.unb1_board_back_select
- port map (
- bck_id => bck_id,
- clk => dp_clk,
+ port map (
+ bck_id => bck_id,
+ clk => dp_clk,
- -- User side
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- tx_usr_siso_2arr => tx_usr_siso_2arr,
+ -- User side
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ tx_usr_siso_2arr => tx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
- -- Phy side
- tx_phy_sosi_2arr => tx_sel_sosi_2arr,
- tx_phy_siso_2arr => tx_sel_siso_2arr,
+ -- Phy side
+ tx_phy_sosi_2arr => tx_sel_sosi_2arr,
+ tx_phy_siso_2arr => tx_sel_siso_2arr,
- rx_phy_sosi_2arr => rx_sel_sosi_2arr,
- rx_phy_siso_2arr => rx_sel_siso_2arr
- );
+ rx_phy_sosi_2arr => rx_sel_sosi_2arr,
+ rx_phy_siso_2arr => rx_sel_siso_2arr
+ );
u_unb1_board_back_reorder : entity work.unb1_board_back_reorder
- port map (
- bck_id => bck_id,
- clk => dp_clk,
+ port map (
+ bck_id => bck_id,
+ clk => dp_clk,
- -- User side
- tx_usr_sosi_2arr => tx_sel_sosi_2arr,
- tx_usr_siso_2arr => tx_sel_siso_2arr,
+ -- User side
+ tx_usr_sosi_2arr => tx_sel_sosi_2arr,
+ tx_usr_siso_2arr => tx_sel_siso_2arr,
- rx_usr_sosi_2arr => rx_sel_sosi_2arr,
- rx_usr_siso_2arr => rx_sel_siso_2arr,
+ rx_usr_sosi_2arr => rx_sel_sosi_2arr,
+ rx_usr_siso_2arr => rx_sel_siso_2arr,
- -- Phy side
- tx_phy_sosi_2arr => tx_term_sosi_2arr,
- tx_phy_siso_2arr => tx_term_siso_2arr,
+ -- Phy side
+ tx_phy_sosi_2arr => tx_term_sosi_2arr,
+ tx_phy_siso_2arr => tx_term_siso_2arr,
- rx_phy_sosi_2arr => rx_term_sosi_2arr,
- rx_phy_siso_2arr => rx_term_siso_2arr
- );
+ rx_phy_sosi_2arr => rx_term_sosi_2arr,
+ rx_phy_siso_2arr => rx_term_siso_2arr
+ );
u_unb1_board_back_uth_terminals_bidir : entity work.unb1_board_back_uth_terminals_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => c_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- -- Rx
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_timeout_w => g_rx_timeout_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- User
- tx_dp_sosi_2arr => tx_term_sosi_2arr,
- tx_dp_siso_2arr => tx_term_siso_2arr,
-
- rx_dp_sosi_2arr => rx_term_sosi_2arr,
- rx_dp_siso_2arr => rx_term_siso_2arr,
-
- -- Phy
- tx_uth_sosi_2arr => tx_phy_sosi_2arr,
- tx_uth_siso_2arr => tx_phy_siso_2arr,
-
- rx_uth_sosi_2arr => rx_phy_sosi_2arr,
- rx_uth_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => c_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ -- Rx
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_timeout_w => g_rx_timeout_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- User
+ tx_dp_sosi_2arr => tx_term_sosi_2arr,
+ tx_dp_siso_2arr => tx_term_siso_2arr,
+
+ rx_dp_sosi_2arr => rx_term_sosi_2arr,
+ rx_dp_siso_2arr => rx_term_siso_2arr,
+
+ -- Phy
+ tx_uth_sosi_2arr => tx_phy_sosi_2arr,
+ tx_uth_siso_2arr => tx_phy_siso_2arr,
+
+ rx_uth_sosi_2arr => rx_phy_sosi_2arr,
+ rx_uth_siso_2arr => rx_phy_siso_2arr
+ );
------------------------------------------------------------------------------
-- GX serial interface level (g_sim_level)
@@ -223,55 +223,55 @@ begin
-- Map 1-dim array on 2-dim array
gen_bus : for i in c_nof_bus_serial - 1 downto 0 generate
gen_lane : for j in g_phy_nof_serial - 1 downto 0 generate
- -- SOSI
- tx_phy_sosi_arr(i * g_phy_nof_serial + j) <= tx_phy_sosi_2arr(i)(j);
- tx_phy_siso_2arr(i)(j) <= tx_phy_siso_arr(i * g_phy_nof_serial + j);
+ -- SOSI
+ tx_phy_sosi_arr(i * g_phy_nof_serial + j) <= tx_phy_sosi_2arr(i)(j);
+ tx_phy_siso_2arr(i)(j) <= tx_phy_siso_arr(i * g_phy_nof_serial + j);
- rx_phy_sosi_2arr(i)(j) <= rx_phy_sosi_arr(i * g_phy_nof_serial + j);
- rx_phy_siso_arr(i * g_phy_nof_serial + j) <= rx_phy_siso_2arr(i)(j);
+ rx_phy_sosi_2arr(i)(j) <= rx_phy_sosi_arr(i * g_phy_nof_serial + j);
+ rx_phy_siso_arr(i * g_phy_nof_serial + j) <= rx_phy_siso_2arr(i)(j);
- -- Serial
- tx_serial_2arr(i)(j) <= tx_serial_arr(i * g_phy_nof_serial + j);
- rx_serial_arr(i * g_phy_nof_serial + j) <= rx_serial_2arr(i)(j);
+ -- Serial
+ tx_serial_2arr(i)(j) <= tx_serial_arr(i * g_phy_nof_serial + j);
+ rx_serial_arr(i * g_phy_nof_serial + j) <= rx_serial_2arr(i)(j);
end generate;
end generate;
u_tr_nonbonded : entity tr_nonbonded_lib.mms_tr_nonbonded
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_nof_gx => c_nof_gx,
- g_mbps => g_phy_gx_mbps,
- g_tx => true,
- g_rx => true,
- g_rx_fifo_depth => g_phy_rx_fifo_size
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- tr_clk => tr_clk,
- cal_rec_clk => cal_clk,
-
- --Serial data I/O
- tx_dataout => tx_serial_arr,
- rx_datain => rx_serial_arr,
-
- --Streaming I/O
- snk_out_arr => tx_phy_siso_arr,
- snk_in_arr => tx_phy_sosi_arr,
-
- src_in_arr => rx_phy_siso_arr,
- src_out_arr => rx_phy_sosi_arr,
-
- tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
- tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
-
- diagnostics_mm_mosi => reg_diagnostics_mosi,
- diagnostics_mm_miso => reg_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_gx => c_nof_gx,
+ g_mbps => g_phy_gx_mbps,
+ g_tx => true,
+ g_rx => true,
+ g_rx_fifo_depth => g_phy_rx_fifo_size
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ tr_clk => tr_clk,
+ cal_rec_clk => cal_clk,
+
+ --Serial data I/O
+ tx_dataout => tx_serial_arr,
+ rx_datain => rx_serial_arr,
+
+ --Streaming I/O
+ snk_out_arr => tx_phy_siso_arr,
+ snk_in_arr => tx_phy_sosi_arr,
+
+ src_in_arr => rx_phy_siso_arr,
+ src_out_arr => rx_phy_sosi_arr,
+
+ tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
+ tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
+
+ diagnostics_mm_mosi => reg_diagnostics_mosi,
+ diagnostics_mm_miso => reg_diagnostics_miso
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
index db68198b49..85c1c71f8d 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -50,14 +50,14 @@
library IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_terminals_mesh is
@@ -90,12 +90,12 @@ entity unb1_board_terminals_mesh is
g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
-- Monitoring
g_mon_select : natural := 0; -- 0 = no SOSI data buffers monitor via MM
- -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
- -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
- -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
- -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
- -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
- -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
+ -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
+ -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
+ -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
+ -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
+ -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
+ -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
g_mon_nof_words : natural := 1024;
g_mon_use_sync : boolean := true;
-- UTH
@@ -149,19 +149,19 @@ architecture str of unb1_board_terminals_mesh is
-- g_mon_select
constant c_usr_nof_streams : natural := g_nof_bus * g_usr_nof_streams;
constant c_mon_nof_streams : natural := sel_n(g_mon_select, c_phy_nof_gx,
- c_phy_nof_gx,
- c_phy_nof_gx,
- c_phy_nof_gx,
- c_usr_nof_streams,
- c_phy_nof_gx,
- c_phy_nof_gx);
+ c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_usr_nof_streams,
+ c_phy_nof_gx,
+ c_phy_nof_gx);
constant c_mon_data_w : natural := sel_n(g_mon_select, c_packet_data_w,
- c_packet_data_w,
- c_packet_data_w,
- c_packet_data_w,
- g_usr_data_w,
- c_packet_data_w,
- c_packet_data_w);
+ c_packet_data_w,
+ c_packet_data_w,
+ c_packet_data_w,
+ g_usr_data_w,
+ c_packet_data_w,
+ c_packet_data_w);
-- uth terminals
signal tx_term_siso_2arr : t_unb1_board_mesh_siso_2arr;
@@ -244,25 +244,25 @@ begin
gen_monitor : if g_mon_select >= 1 generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_mon_nof_streams,
- g_data_w => c_mon_data_w, -- stream data width must be <= c_word_w = 32b, the MM word width
- g_buf_nof_data => g_mon_nof_words, -- nof words per data buffer
- g_buf_use_sync => g_mon_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- -- ST interface
- in_sync => dp_sync, -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
- in_sosi_arr => mon_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_mon_nof_streams,
+ g_data_w => c_mon_data_w, -- stream data width must be <= c_word_w = 32b, the MM word width
+ g_buf_nof_data => g_mon_nof_words, -- nof words per data buffer
+ g_buf_use_sync => g_mon_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ -- ST interface
+ in_sync => dp_sync, -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ in_sosi_arr => mon_sosi_arr
+ );
end generate;
------------------------------------------------------------------------------
@@ -270,85 +270,85 @@ begin
------------------------------------------------------------------------------
u_unb1_board_mesh_uth_terminals_bidir : entity work.unb1_board_mesh_uth_terminals_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => c_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => c_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- User
- tx_dp_sosi_2arr => tx_usr_sosi_2arr,
- tx_dp_siso_2arr => tx_usr_siso_2arr,
+ -- User
+ tx_dp_sosi_2arr => tx_usr_sosi_2arr,
+ tx_dp_siso_2arr => tx_usr_siso_2arr,
- rx_dp_sosi_2arr => rx_usr_sosi_2arr,
- rx_dp_siso_2arr => rx_usr_siso_2arr,
+ rx_dp_sosi_2arr => rx_usr_sosi_2arr,
+ rx_dp_siso_2arr => rx_usr_siso_2arr,
- -- Phy
- tx_uth_sosi_2arr => tx_term_sosi_2arr,
- tx_uth_siso_2arr => tx_term_siso_2arr,
+ -- Phy
+ tx_uth_sosi_2arr => tx_term_sosi_2arr,
+ tx_uth_siso_2arr => tx_term_siso_2arr,
- rx_uth_sosi_2arr => rx_term_sosi_2arr,
- rx_uth_siso_2arr => rx_term_siso_2arr,
+ rx_uth_sosi_2arr => rx_term_sosi_2arr,
+ rx_uth_siso_2arr => rx_term_siso_2arr,
- -- Monitoring
- rx_mon_pkt_sosi_2arr => mon_rx_term_pkt_sosi_2arr,
- rx_mon_dist_sosi_2arr => mon_rx_term_dist_sosi_2arr
- );
+ -- Monitoring
+ rx_mon_pkt_sosi_2arr => mon_rx_term_pkt_sosi_2arr,
+ rx_mon_dist_sosi_2arr => mon_rx_term_dist_sosi_2arr
+ );
------------------------------------------------------------------------------
-- Compensate for mesh reorder (g_phy_ena_reorder)
------------------------------------------------------------------------------
u_tx : entity work.unb1_board_mesh_reorder_tx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_phy_ena_reorder
- )
- port map (
- chip_id => chip_id,
- clk => dp_clk,
- tx_usr_sosi_2arr => tx_term_sosi_2arr, -- g_use_tx
- rx_usr_siso_2arr => rx_term_siso_2arr, -- g_use_rx
- tx_phy_sosi_2arr => tx_phy_sosi_2arr,
- rx_phy_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_phy_ena_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => dp_clk,
+ tx_usr_sosi_2arr => tx_term_sosi_2arr, -- g_use_tx
+ rx_usr_siso_2arr => rx_term_siso_2arr, -- g_use_rx
+ tx_phy_sosi_2arr => tx_phy_sosi_2arr,
+ rx_phy_siso_2arr => rx_phy_siso_2arr
+ );
u_rx : entity work.unb1_board_mesh_reorder_rx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_phy_ena_reorder
- )
- port map (
- chip_id => chip_id,
- clk => dp_clk,
- rx_phy_sosi_2arr => rx_phy_sosi_2arr,
- tx_phy_siso_2arr => tx_phy_siso_2arr,
- rx_usr_sosi_2arr => rx_term_sosi_2arr, -- g_use_rx
- tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_phy_ena_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => dp_clk,
+ rx_phy_sosi_2arr => rx_phy_sosi_2arr,
+ tx_phy_siso_2arr => tx_phy_siso_2arr,
+ rx_usr_sosi_2arr => rx_term_sosi_2arr, -- g_use_rx
+ tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
+ );
------------------------------------------------------------------------------
@@ -358,57 +358,57 @@ begin
-- Map 1-dim array on 2-dim array
gen_bus : for I in g_nof_bus - 1 downto 0 generate
gen_lane : for J in g_phy_nof_serial - 1 downto 0 generate
- -- SOSI
- tx_phy_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
- tx_phy_siso_2arr(I)(J) <= tx_phy_siso_arr(I * g_phy_nof_serial + J);
+ -- SOSI
+ tx_phy_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
+ tx_phy_siso_2arr(I)(J) <= tx_phy_siso_arr(I * g_phy_nof_serial + J);
- rx_phy_sosi_2arr(I)(J) <= rx_phy_sosi_arr(I * g_phy_nof_serial + J);
- rx_phy_siso_arr(I * g_phy_nof_serial + J) <= rx_phy_siso_2arr(I)(J);
+ rx_phy_sosi_2arr(I)(J) <= rx_phy_sosi_arr(I * g_phy_nof_serial + J);
+ rx_phy_siso_arr(I * g_phy_nof_serial + J) <= rx_phy_siso_2arr(I)(J);
- -- Serial
- tx_serial_2arr(I)(J) <= tx_serial_arr(I * g_phy_nof_serial + J);
- rx_serial_arr(I * g_phy_nof_serial + J) <= rx_serial_2arr(I)(J);
+ -- Serial
+ tx_serial_2arr(I)(J) <= tx_serial_arr(I * g_phy_nof_serial + J);
+ rx_serial_arr(I * g_phy_nof_serial + J) <= rx_serial_2arr(I)(J);
end generate;
end generate;
u_tr_nonbonded : entity tr_nonbonded_lib.mms_tr_nonbonded
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_data_w => c_phy_data_w,
- g_nof_gx => c_phy_nof_gx,
- g_mbps => g_phy_gx_mbps,
- g_tx => g_use_tx,
- g_rx => g_use_rx,
- g_rx_fifo_depth => g_phy_rx_fifo_size
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- tr_clk => tr_clk,
- cal_rec_clk => cal_clk,
-
- --Serial data I/O
- tx_dataout => tx_serial_arr,
- rx_datain => rx_serial_arr,
-
- --Streaming I/O
- snk_out_arr => tx_phy_siso_arr,
- snk_in_arr => tx_phy_sosi_arr,
-
- src_in_arr => rx_phy_siso_arr,
- src_out_arr => rx_phy_sosi_arr,
-
- tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
- tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
-
- diagnostics_mm_mosi => reg_diagnostics_mosi,
- diagnostics_mm_miso => reg_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_data_w => c_phy_data_w,
+ g_nof_gx => c_phy_nof_gx,
+ g_mbps => g_phy_gx_mbps,
+ g_tx => g_use_tx,
+ g_rx => g_use_rx,
+ g_rx_fifo_depth => g_phy_rx_fifo_size
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ tr_clk => tr_clk,
+ cal_rec_clk => cal_clk,
+
+ --Serial data I/O
+ tx_dataout => tx_serial_arr,
+ rx_datain => rx_serial_arr,
+
+ --Streaming I/O
+ snk_out_arr => tx_phy_siso_arr,
+ snk_in_arr => tx_phy_sosi_arr,
+
+ src_in_arr => rx_phy_siso_arr,
+ src_out_arr => rx_phy_sosi_arr,
+
+ tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
+ tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
+
+ diagnostics_mm_mosi => reg_diagnostics_mosi,
+ diagnostics_mm_miso => reg_diagnostics_miso
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
index 20437a399b..644a98c601 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -72,27 +72,27 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
index d03edab58d..5a26a09146 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb1_board_wdi_reg is
port (
@@ -40,18 +40,20 @@ entity unb1_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb1_board_wdi_reg;
architecture rtl of unb1_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0'
+ );
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -64,7 +66,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
index 0de4b7a343..757b9115a9 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -32,11 +32,11 @@ entity tb_mms_unb1_board_sens is
end tb_mms_unb1_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
architecture tb of tb_mms_unb1_board_sens is
@@ -153,60 +153,60 @@ begin
-- I2C sensors master
u_mms_unb1_board_sens : entity work.mms_unb1_board_sens
- generic map (
- g_sim => c_sim,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
index 59732556ad..76652bfbdc 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
@@ -27,7 +27,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_tb_unb1_board_regression is
end tb_tb_tb_unb1_board_regression;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
index 820d767d9a..75b8bd8b95 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb1_board_clk200_pll is
@@ -74,69 +74,69 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 0, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=0 for clk200_pll.vhd
- g_clk200_phase_shift => "0",
- g_clk200p_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "0",
+ g_clk200p_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 0, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=0 for clk200_pll.vhd
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 1, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=1 for clk200_pll_p6.vhd
- g_clk200_phase_shift => "0",
- -- g_sel=1 for clk200_pll_p6.vhd
- g_clk0_phase_shift => "0",
- g_clk_vec_w => c_clk_vec_w,
- g_clk1_phase_shift => "0",
- g_clk2_phase_shift => "156",
- g_clk3_phase_shift => "313",
- g_clk4_phase_shift => "469",
- g_clk5_phase_shift => "625",
- g_clk6_phase_shift => "938",
- g_clk1_divide_by => c_clk_div,
- g_clk2_divide_by => c_clk_div,
- g_clk3_divide_by => c_clk_div,
- g_clk4_divide_by => c_clk_div,
- g_clk5_divide_by => c_clk_div,
- g_clk6_divide_by => c_clk_div
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200,
- -- . g_sel=1
- st_clk_vec => st_clk_vec
- );
+ generic map (
+ g_sel => 1, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=1 for clk200_pll_p6.vhd
+ g_clk200_phase_shift => "0",
+ -- g_sel=1 for clk200_pll_p6.vhd
+ g_clk0_phase_shift => "0",
+ g_clk_vec_w => c_clk_vec_w,
+ g_clk1_phase_shift => "0",
+ g_clk2_phase_shift => "156",
+ g_clk3_phase_shift => "313",
+ g_clk4_phase_shift => "469",
+ g_clk5_phase_shift => "625",
+ g_clk6_phase_shift => "938",
+ g_clk1_divide_by => c_clk_div,
+ g_clk2_divide_by => c_clk_div,
+ g_clk3_divide_by => c_clk_div,
+ g_clk4_divide_by => c_clk_div,
+ g_clk5_divide_by => c_clk_div,
+ g_clk6_divide_by => c_clk_div
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200,
+ -- . g_sel=1
+ st_clk_vec => st_clk_vec
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
index 050793a9a4..8535eb6aea 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -42,12 +42,12 @@
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity tb_unb1_board_mesh_reorder_bidir is
@@ -230,27 +230,27 @@ begin
gen_fn : for I in 0 to c_nof_node-1 generate
u_order : entity work.unb1_board_mesh_reorder_bidir
- generic map (
- g_node_type => e_fn,
- g_reorder => c_reorder
- )
- port map (
- chip_id => TO_UVEC(I, c_chip_id_w), -- chip id 0, 1, 2, 3
-
- -- Transmit clock domain
- tx_clk => clk,
- tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from FN user
- tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to FN user
- tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
- tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I), -- phy siso from mesh
-
- -- Receive clock domain
- rx_clk => clk,
- rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
- rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I), -- phy siso to mesh
- rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to FN user
- rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from FN user
- );
+ generic map (
+ g_node_type => e_fn,
+ g_reorder => c_reorder
+ )
+ port map (
+ chip_id => TO_UVEC(I, c_chip_id_w), -- chip id 0, 1, 2, 3
+
+ -- Transmit clock domain
+ tx_clk => clk,
+ tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from FN user
+ tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to FN user
+ tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
+ tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I), -- phy siso from mesh
+
+ -- Receive clock domain
+ rx_clk => clk,
+ rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
+ rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I), -- phy siso to mesh
+ rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to FN user
+ rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from FN user
+ );
end generate;
@@ -271,18 +271,18 @@ begin
end generate;
u_pcb_mesh_serial : entity work.unb1_board_mesh_model_sl
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_tx_phy_sl_3arr,
- bn_rx_sl_3arr => bn_rx_phy_sl_3arr,
-
- -- BN to FN
- bn_tx_sl_3arr => bn_tx_phy_sl_3arr,
- fn_rx_sl_3arr => fn_rx_phy_sl_3arr
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_tx_phy_sl_3arr,
+ bn_rx_sl_3arr => bn_rx_phy_sl_3arr,
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_tx_phy_sl_3arr,
+ fn_rx_sl_3arr => fn_rx_phy_sl_3arr
+ );
-- Use rx_phy SOSI.valid as reference output to verify output of unb1_board_mesh_model_sl
mon_rx_serial : for I in 0 to c_nof_node-1 generate
@@ -310,63 +310,63 @@ begin
-- >>> unb1_board_mesh_model_sosi
u_pcb_mesh_sosi : entity work.unb1_board_mesh_model_sosi
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn0_tx_sosi_2arr => fn_tx_phy_sosi_3arr(0),
- fn1_tx_sosi_2arr => fn_tx_phy_sosi_3arr(1),
- fn2_tx_sosi_2arr => fn_tx_phy_sosi_3arr(2),
- fn3_tx_sosi_2arr => fn_tx_phy_sosi_3arr(3),
-
- bn0_rx_sosi_2arr => bn_rx_phy_sosi_3arr(0),
- bn1_rx_sosi_2arr => bn_rx_phy_sosi_3arr(1),
- bn2_rx_sosi_2arr => bn_rx_phy_sosi_3arr(2),
- bn3_rx_sosi_2arr => bn_rx_phy_sosi_3arr(3),
-
- -- BN to FN
- bn0_tx_sosi_2arr => bn_tx_phy_sosi_3arr(0),
- bn1_tx_sosi_2arr => bn_tx_phy_sosi_3arr(1),
- bn2_tx_sosi_2arr => bn_tx_phy_sosi_3arr(2),
- bn3_tx_sosi_2arr => bn_tx_phy_sosi_3arr(3),
-
- fn0_rx_sosi_2arr => fn_rx_phy_sosi_3arr(0),
- fn1_rx_sosi_2arr => fn_rx_phy_sosi_3arr(1),
- fn2_rx_sosi_2arr => fn_rx_phy_sosi_3arr(2),
- fn3_rx_sosi_2arr => fn_rx_phy_sosi_3arr(3)
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn0_tx_sosi_2arr => fn_tx_phy_sosi_3arr(0),
+ fn1_tx_sosi_2arr => fn_tx_phy_sosi_3arr(1),
+ fn2_tx_sosi_2arr => fn_tx_phy_sosi_3arr(2),
+ fn3_tx_sosi_2arr => fn_tx_phy_sosi_3arr(3),
+
+ bn0_rx_sosi_2arr => bn_rx_phy_sosi_3arr(0),
+ bn1_rx_sosi_2arr => bn_rx_phy_sosi_3arr(1),
+ bn2_rx_sosi_2arr => bn_rx_phy_sosi_3arr(2),
+ bn3_rx_sosi_2arr => bn_rx_phy_sosi_3arr(3),
+
+ -- BN to FN
+ bn0_tx_sosi_2arr => bn_tx_phy_sosi_3arr(0),
+ bn1_tx_sosi_2arr => bn_tx_phy_sosi_3arr(1),
+ bn2_tx_sosi_2arr => bn_tx_phy_sosi_3arr(2),
+ bn3_tx_sosi_2arr => bn_tx_phy_sosi_3arr(3),
+
+ fn0_rx_sosi_2arr => fn_rx_phy_sosi_3arr(0),
+ fn1_rx_sosi_2arr => fn_rx_phy_sosi_3arr(1),
+ fn2_rx_sosi_2arr => fn_rx_phy_sosi_3arr(2),
+ fn3_rx_sosi_2arr => fn_rx_phy_sosi_3arr(3)
+ );
-- >>> unb1_board_mesh_model_siso
u_pcb_mesh_siso : entity work.unb1_board_mesh_model_siso
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn0_rx_siso_2arr => fn_rx_phy_siso_3arr(0),
- fn1_rx_siso_2arr => fn_rx_phy_siso_3arr(1),
- fn2_rx_siso_2arr => fn_rx_phy_siso_3arr(2),
- fn3_rx_siso_2arr => fn_rx_phy_siso_3arr(3),
-
- bn0_tx_siso_2arr => bn_tx_phy_siso_3arr(0),
- bn1_tx_siso_2arr => bn_tx_phy_siso_3arr(1),
- bn2_tx_siso_2arr => bn_tx_phy_siso_3arr(2),
- bn3_tx_siso_2arr => bn_tx_phy_siso_3arr(3),
-
- -- BN to FN
- bn0_rx_siso_2arr => bn_rx_phy_siso_3arr(0),
- bn1_rx_siso_2arr => bn_rx_phy_siso_3arr(1),
- bn2_rx_siso_2arr => bn_rx_phy_siso_3arr(2),
- bn3_rx_siso_2arr => bn_rx_phy_siso_3arr(3),
-
- fn0_tx_siso_2arr => fn_tx_phy_siso_3arr(0),
- fn1_tx_siso_2arr => fn_tx_phy_siso_3arr(1),
- fn2_tx_siso_2arr => fn_tx_phy_siso_3arr(2),
- fn3_tx_siso_2arr => fn_tx_phy_siso_3arr(3)
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn0_rx_siso_2arr => fn_rx_phy_siso_3arr(0),
+ fn1_rx_siso_2arr => fn_rx_phy_siso_3arr(1),
+ fn2_rx_siso_2arr => fn_rx_phy_siso_3arr(2),
+ fn3_rx_siso_2arr => fn_rx_phy_siso_3arr(3),
+
+ bn0_tx_siso_2arr => bn_tx_phy_siso_3arr(0),
+ bn1_tx_siso_2arr => bn_tx_phy_siso_3arr(1),
+ bn2_tx_siso_2arr => bn_tx_phy_siso_3arr(2),
+ bn3_tx_siso_2arr => bn_tx_phy_siso_3arr(3),
+
+ -- BN to FN
+ bn0_rx_siso_2arr => bn_rx_phy_siso_3arr(0),
+ bn1_rx_siso_2arr => bn_rx_phy_siso_3arr(1),
+ bn2_rx_siso_2arr => bn_rx_phy_siso_3arr(2),
+ bn3_rx_siso_2arr => bn_rx_phy_siso_3arr(3),
+
+ fn0_tx_siso_2arr => fn_tx_phy_siso_3arr(0),
+ fn1_tx_siso_2arr => fn_tx_phy_siso_3arr(1),
+ fn2_tx_siso_2arr => fn_tx_phy_siso_3arr(2),
+ fn3_tx_siso_2arr => fn_tx_phy_siso_3arr(3)
+ );
------------------------------------------------------------------------------
@@ -375,27 +375,27 @@ begin
gen_bn : for I in 0 to c_nof_node-1 generate
u_order : entity work.unb1_board_mesh_reorder_bidir
- generic map (
- g_node_type => e_bn,
- g_reorder => c_reorder
- )
- port map (
- chip_id => TO_UVEC(c_nof_node + I, c_chip_id_w), -- chip id 4, 5, 6, 7
-
- -- Transmit clock domain
- tx_clk => clk,
- tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from BN user
- tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to BN user
- tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
- tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I), -- phy siso from mesh
-
- -- Receive clock domain
- rx_clk => clk,
- rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
- rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I), -- phy siso to mesh
- rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to BN user
- rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from BN user
- );
+ generic map (
+ g_node_type => e_bn,
+ g_reorder => c_reorder
+ )
+ port map (
+ chip_id => TO_UVEC(c_nof_node + I, c_chip_id_w), -- chip id 4, 5, 6, 7
+
+ -- Transmit clock domain
+ tx_clk => clk,
+ tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from BN user
+ tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to BN user
+ tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
+ tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I), -- phy siso from mesh
+
+ -- Receive clock domain
+ rx_clk => clk,
+ rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
+ rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I), -- phy siso to mesh
+ rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to BN user
+ rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from BN user
+ );
end generate;
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
index 5b8ebe20f3..50f317e6d0 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb1_board_node_ctrl is
@@ -81,23 +81,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb1_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => sys_rst,
- wdi_in => wdi_in,
- wdi_out => wdi_out,
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => sys_rst,
+ wdi_in => wdi_in,
+ wdi_out => wdi_out,
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
index 2b119ed295..f6f49f060f 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
package tb_unb1_board_pkg is
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
index 195d05a17d..a5791b1e0e 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
@@ -35,11 +35,11 @@
-- . Phy bus 3 is not used and left not connected on the backplane.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_back_model_sl is
port (
@@ -74,12 +74,12 @@ begin
backplane_out_serial_4arr(3)(BN)(0) <= backplane_in_serial_4arr(0)(BN)(0);
backplane_out_serial_4arr(3)(BN)(1) <= backplane_in_serial_4arr(1)(BN)(0);
backplane_out_serial_4arr(3)(BN)(2) <= backplane_in_serial_4arr(2)(BN)(1);
- -- ^ ^ ^ ^ ^
- -- | | | | |
- -- | | BN_BI RX phy bus | BN_BI TX phy bus
- -- | | Transmitting UniBoard
- -- | Same scheme applies to all back nodes
- -- Receiving UniBoard
+ -- ^ ^ ^ ^ ^
+ -- | | | | |
+ -- | | BN_BI RX phy bus | BN_BI TX phy bus
+ -- | | Transmitting UniBoard
+ -- | Same scheme applies to all back nodes
+ -- Receiving UniBoard
end generate;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
index bfd7635362..e7908399e1 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
@@ -26,11 +26,11 @@
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_back_model_sosi is
port (
@@ -65,12 +65,12 @@ begin
backplane_out_sosi_4arr(3)(BN)(0) <= backplane_in_sosi_4arr(0)(BN)(0);
backplane_out_sosi_4arr(3)(BN)(1) <= backplane_in_sosi_4arr(1)(BN)(0);
backplane_out_sosi_4arr(3)(BN)(2) <= backplane_in_sosi_4arr(2)(BN)(1);
- -- ^ ^ ^ ^ ^
- -- | | | | |
- -- | | BN_BI RX phy bu | BN_BI TX phy bus
- -- | | Transmitting UniBoard
- -- | Same scheme applies to all back nodes
- -- Receiving UniBoard
+ -- ^ ^ ^ ^ ^
+ -- | | | | |
+ -- | | BN_BI RX phy bu | BN_BI TX phy bus
+ -- | | Transmitting UniBoard
+ -- | Same scheme applies to all back nodes
+ -- Receiving UniBoard
end generate;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
index b7a65aa7a5..94c3134db2 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
@@ -24,11 +24,11 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_model_siso is
@@ -111,7 +111,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn0_tx_siso_2arr(0) <= fn3_rx_siso_2arr(1); -- 0,0 <= 3,1
bn0_tx_siso_2arr(1) <= fn2_rx_siso_2arr(0); -- 0,1 <= 2,0
bn0_tx_siso_2arr(2) <= fn1_rx_siso_2arr(0); -- 0,2 <= 1,0
@@ -132,7 +132,7 @@ begin
bn3_tx_siso_2arr(2) <= fn2_rx_siso_2arr(3); -- 3,2 <= 2,3
bn3_tx_siso_2arr(3) <= fn1_rx_siso_2arr(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn0_tx_siso_2arr(0) <= bn0_rx_siso_2arr(3); -- 0,0 <= 0,3
fn0_tx_siso_2arr(1) <= bn3_rx_siso_2arr(1); -- 0,1 <= 3,1
fn0_tx_siso_2arr(2) <= bn2_rx_siso_2arr(2); -- 0,2 <= 2,2
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
index 1eb7f377b5..b78c285ac0 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
@@ -25,12 +25,12 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_mesh_model_sl is
@@ -66,7 +66,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn_rx_sl_3arr(0)(0) <= fn_tx_sl_3arr(3)(1); -- 0,0 <= 3,1
bn_rx_sl_3arr(0)(1) <= fn_tx_sl_3arr(2)(0); -- 0,1 <= 2,0
bn_rx_sl_3arr(0)(2) <= fn_tx_sl_3arr(1)(0); -- 0,2 <= 1,0
@@ -87,7 +87,7 @@ begin
bn_rx_sl_3arr(3)(2) <= fn_tx_sl_3arr(2)(3); -- 3,2 <= 2,3
bn_rx_sl_3arr(3)(3) <= fn_tx_sl_3arr(1)(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn_rx_sl_3arr(0)(0) <= bn_tx_sl_3arr(0)(3); -- 0,0 <= 0,3
fn_rx_sl_3arr(0)(1) <= bn_tx_sl_3arr(3)(1); -- 0,1 <= 3,1
fn_rx_sl_3arr(0)(2) <= bn_tx_sl_3arr(2)(2); -- 0,2 <= 2,2
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
index 16a1b0166e..fbde813873 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
@@ -24,11 +24,11 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_model_sosi is
@@ -111,7 +111,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn0_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(1); -- 0,0 <= 3,1
bn0_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(0); -- 0,1 <= 2,0
bn0_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(0); -- 0,2 <= 1,0
@@ -132,7 +132,7 @@ begin
bn3_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(3); -- 3,2 <= 2,3
bn3_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn0_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(3); -- 0,0 <= 0,3
fn0_rx_sosi_2arr(1) <= bn3_tx_sosi_2arr(1); -- 0,1 <= 3,1
fn0_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(2); -- 0,2 <= 2,2
diff --git a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
index 8974e7b86e..73a3b0bcab 100644
--- a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
entity unb2_led is
generic (
@@ -102,15 +102,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- mm_clk
@@ -121,40 +121,40 @@ begin
i_mm_clk <= clk50;
gen_mm_clk_sim: if g_sim = true generate
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- mm_locked <= '0', '1' after 70 ns;
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity unb2_board_lib.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity unb2_board_lib.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity unb2_board_lib.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
------------------------------------------------------------------------------
-- Toggle red LED when unb2_minimal is running, green LED for other designs.
@@ -164,15 +164,15 @@ begin
u_extend : common_lib.common_pulse_extend
- generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- p_in => mm_pulse_s,
- ep_out => led_flash
- );
+ generic map (
+ g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ p_in => mm_pulse_s,
+ ep_out => led_flash
+ );
@@ -186,36 +186,36 @@ begin
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : common_lib.common_pulse_extend
- generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- p_in => pulse_10Hz,
- ep_out => pulse_10Hz_extended
- );
+ generic map (
+ g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ p_in => pulse_10Hz,
+ ep_out => pulse_10Hz_extended
+ );
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
QSFP_LED(6) <= led_toggle;
diff --git a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
index 26d6ca1ef6..0db2dfb363 100644
--- a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
@@ -40,17 +40,17 @@
library IEEE, common_lib, unb2_board_lib, ;
use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2_led is
- generic (
- g_design_name : string := "unb2_led";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2_led";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2_led;
architecture tb of tb_unb2_led is
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index 3e498fbde5..b4065c7dfb 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use unb2_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use unb2_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2_minimal_pkg.all;
entity mmm_unb2_minimal is
@@ -116,32 +116,32 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -158,145 +158,145 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2_minimal
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
index 7f2a14415b..8958182068 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
@@ -20,137 +20,137 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb2_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(4 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2_minimal;
+ component qsys_unb2_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2_minimal;
end qsys_unb2_minimal_pkg;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index 3671e774db..3c4c14e227 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
entity unb2_minimal is
generic (
@@ -160,197 +160,197 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
-- u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
-- GENERIC MAP (
diff --git a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
index f4bc5b2a06..36c52b4977 100644
--- a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2_minimal is
- generic (
- g_design_name : string := "unb2_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2_minimal;
architecture tb of tb_unb2_minimal is
@@ -184,37 +184,37 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 9fa20f22f2..e99dfa9b49 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, unb_common_lib;
-use unb_common_lib.unb_common_pkg.all;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity unb2_pinning is
@@ -132,8 +132,8 @@ entity unb2_pinning is
-- I2C Interface to Sensors
SENS_SC : inout std_logic;
SENS_SD : inout std_logic;
- -- Others
--- CFG_DATA : inout std_logic_vector (3 downto 0);
+ -- Others
+ -- CFG_DATA : inout std_logic_vector (3 downto 0);
VERSION : in std_logic_vector(1 downto 0);
ID : in std_logic_vector(7 downto 0);
TESTIO : inout std_logic_vector(5 downto 0);
@@ -145,185 +145,185 @@ end unb2_pinning;
architecture str of unb2_pinning is
- component ddr4 is
- port (
- global_reset_n : in std_logic := 'X'; -- reset_n
- pll_ref_clk : in std_logic := 'X'; -- clk
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_alert_n : in std_logic_vector(0 downto 0); -- mem_alert_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par ** new in 14.0 **
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic; -- local_cal_fail
- emif_usr_reset_n : out std_logic; -- reset_n
- emif_usr_clk : out std_logic; -- clk
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address ** chg from 23 bits in 14.0 **
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount ** chg from 8 bits in 14.0 **
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic -- readdatavalid
- );
- end component ddr4;
-
- component transceiver_phy is
- port (
- tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_analogreset
- tx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_digitalreset
- rx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_analogreset
- rx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_digitalreset
- tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy
- rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy
- rx_is_lockedtodata : out std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data
- rx_serial_data : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_serial_data
- tx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- rx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- tx_clkout : out std_logic_vector(47 downto 0); -- clk
- rx_clkout : out std_logic_vector(47 downto 0); -- clk
- tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_enh_data_valid
- rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid
- rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock
- tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_control : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_control
- tx_err_ins : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(431 downto 0) := (others => 'X'); -- unused_tx_control
- rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data
- rx_control : out std_logic_vector(383 downto 0); -- rx_control
- unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(575 downto 0) -- unused_rx_control
- );
- end component transceiver_phy;
-
- component transceiver_phy_24channel is
- port (
- tx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_analogreset
- tx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_digitalreset
- rx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_analogreset
- rx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_digitalreset
- tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy
- rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy
- rx_is_lockedtodata : out std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data
- rx_serial_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_serial_data
- tx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- rx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- tx_clkout : out std_logic_vector(23 downto 0); -- clk
- rx_clkout : out std_logic_vector(23 downto 0); -- clk
- tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_enh_data_valid
- rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid
- rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock
- tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_control : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_control
- tx_err_ins : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(215 downto 0) := (others => 'X'); -- unused_tx_control
- rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data
- rx_control : out std_logic_vector(191 downto 0); -- rx_control
- unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(287 downto 0) -- unused_rx_control
- );
- end component transceiver_phy_24channel;
-
- component transceiver_reset_controller is
- port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset
- tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(47 downto 0); -- tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- tx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_cal_busy
- rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset
- rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset
- rx_ready : out std_logic_vector(47 downto 0); -- rx_ready
- rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy
- );
- end component transceiver_reset_controller;
-
- component transceiver_reset_controller_24 is
- port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset
- tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(23 downto 0); -- tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- tx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_cal_busy
- rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset
- rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset
- rx_ready : out std_logic_vector(23 downto 0); -- rx_ready
- rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X') -- rx_cal_busy
- );
- end component transceiver_reset_controller_24;
-
- component transceiver_pll is
- port (
- pll_powerdown : in std_logic := 'X'; -- pll_powerdown
- pll_refclk0 : in std_logic := 'X'; -- clk
- pll_locked : out std_logic; -- pll_locked
- pll_cal_busy : out std_logic; -- pll_cal_busy
- mcgb_rst : in std_logic := 'X'; -- mcgb_rst
- mcgb_serial_clk : out std_logic -- clk
- );
- end component transceiver_pll;
-
- component sys_clkctrl is
- port (
- inclk : in std_logic := 'X'; -- inclk
- outclk : out std_logic -- outclk
- );
- end component sys_clkctrl;
-
-
- component system_pll is
- port (
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X';
- locked : out std_logic;
- outclk_0 : out std_logic; -- outclk0
- outclk_1 : out std_logic; -- outclk1
- outclk_2 : out std_logic -- outclk2
- );
+ component ddr4 is
+ port (
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_alert_n : in std_logic_vector(0 downto 0); -- mem_alert_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par ** new in 14.0 **
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic; -- local_cal_fail
+ emif_usr_reset_n : out std_logic; -- reset_n
+ emif_usr_clk : out std_logic; -- clk
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address ** chg from 23 bits in 14.0 **
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount ** chg from 8 bits in 14.0 **
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic -- readdatavalid
+ );
+ end component ddr4;
+
+ component transceiver_phy is
+ port (
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_digitalreset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_digitalreset
+ tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy
+ rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_serial_data
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ tx_clkout : out std_logic_vector(47 downto 0); -- clk
+ rx_clkout : out std_logic_vector(47 downto 0); -- clk
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- tx_parallel_data
+ tx_control : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_control
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_err_ins
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => 'X'); -- unused_tx_control
+ rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data
+ rx_control : out std_logic_vector(383 downto 0); -- rx_control
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data
+ unused_rx_control : out std_logic_vector(575 downto 0) -- unused_rx_control
+ );
+ end component transceiver_phy;
+
+ component transceiver_phy_24channel is
+ port (
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_digitalreset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_digitalreset
+ tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy
+ rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_serial_data
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ tx_clkout : out std_logic_vector(23 downto 0); -- clk
+ rx_clkout : out std_logic_vector(23 downto 0); -- clk
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- tx_parallel_data
+ tx_control : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_control
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_err_ins
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => 'X'); -- unused_tx_control
+ rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data
+ rx_control : out std_logic_vector(191 downto 0); -- rx_control
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data
+ unused_rx_control : out std_logic_vector(287 downto 0) -- unused_rx_control
+ );
+ end component transceiver_phy_24channel;
+
+ component transceiver_reset_controller is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset
+ tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(47 downto 0); -- tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_cal_busy
+ rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset
+ rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset
+ rx_ready : out std_logic_vector(47 downto 0); -- rx_ready
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy
+ );
+ end component transceiver_reset_controller;
+
+ component transceiver_reset_controller_24 is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset
+ tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(23 downto 0); -- tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_cal_busy
+ rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset
+ rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset
+ rx_ready : out std_logic_vector(23 downto 0); -- rx_ready
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X') -- rx_cal_busy
+ );
+ end component transceiver_reset_controller_24;
+
+ component transceiver_pll is
+ port (
+ pll_powerdown : in std_logic := 'X'; -- pll_powerdown
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ pll_locked : out std_logic; -- pll_locked
+ pll_cal_busy : out std_logic; -- pll_cal_busy
+ mcgb_rst : in std_logic := 'X'; -- mcgb_rst
+ mcgb_serial_clk : out std_logic -- clk
+ );
+ end component transceiver_pll;
+
+ component sys_clkctrl is
+ port (
+ inclk : in std_logic := 'X'; -- inclk
+ outclk : out std_logic -- outclk
+ );
+ end component sys_clkctrl;
+
+
+ component system_pll is
+ port (
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X';
+ locked : out std_logic;
+ outclk_0 : out std_logic; -- outclk0
+ outclk_1 : out std_logic; -- outclk1
+ outclk_2 : out std_logic -- outclk2
+ );
end component system_pll;
- component system_fpll is
- port (
- pll_refclk0 : in std_logic := 'X'; -- clk
- pll_powerdown : in std_logic := 'X';
- pll_locked : out std_logic;
- pll_cal_busy : out std_logic;
- outclk0 : out std_logic; -- outclk0
- outclk1 : out std_logic; -- outclk1
- outclk2 : out std_logic -- outclk2
- );
+ component system_fpll is
+ port (
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ pll_powerdown : in std_logic := 'X';
+ pll_locked : out std_logic;
+ pll_cal_busy : out std_logic;
+ outclk0 : out std_logic; -- outclk0
+ outclk1 : out std_logic; -- outclk1
+ outclk2 : out std_logic -- outclk2
+ );
end component system_fpll;
component unb2_pinning_qsys is
@@ -386,616 +386,616 @@ architecture str of unb2_pinning is
eth_tse_1_serial_connection_txp_0 : out std_logic; -- txp
pio_0_external_connection_export : in std_logic_vector(11 downto 0) := (others => 'X') -- export
- );
+ );
end component unb2_pinning_qsys;
- -- constants
- constant cs_sim : std_logic := '0';
- constant cs_sync : std_logic := '1';
-
- -- general reset and clock signals
- signal reset_n : std_logic;
- signal reset_p : std_logic;
- signal pout_wdi : std_logic := '0';
- signal sys_clk : std_logic := '0';
- signal sys_locked : std_logic := '0';
- signal mm_clk : std_logic := '0';
- signal clk_125 : std_logic := '0';
- signal CLK_buffered : std_logic := '0';
-
- -- signals for the ddr4 controllers
- signal local_i_cal_success : std_logic;
- signal local_i_cal_fail : std_logic;
- signal local_i_reset_n : std_logic;
- signal local_i_clk : std_logic;
- signal local_i_ready : std_logic;
- signal local_i_read : std_logic;
- signal local_i_write : std_logic;
- signal local_i_address : std_logic_vector(26 downto 0);
- signal local_i_readdata : std_logic_vector(575 downto 0);
- signal local_i_writedata : std_logic_vector(575 downto 0);
- signal local_i_burstcount : std_logic_vector(6 downto 0);
- signal local_i_be : std_logic_vector(71 downto 0);
- signal local_i_read_data_valid : std_logic;
- signal mb_i_a_internal : std_logic_vector(16 downto 0);
- signal local_ii_cal_success : std_logic;
- signal local_ii_cal_fail : std_logic;
- signal local_ii_reset_n : std_logic;
- signal local_ii_clk : std_logic;
- signal local_ii_ready : std_logic;
- signal local_ii_read : std_logic;
- signal local_ii_write : std_logic;
- signal local_ii_address : std_logic_vector(26 downto 0);
- signal local_ii_readdata : std_logic_vector(575 downto 0);
- signal local_ii_writedata : std_logic_vector(575 downto 0);
- signal local_ii_burstcount : std_logic_vector(6 downto 0);
- signal local_ii_be : std_logic_vector(71 downto 0);
- signal local_ii_read_data_valid: std_logic;
- signal mb_ii_a_internal : std_logic_vector(16 downto 0);
-
- -- signals for the transceivers
- signal tx_serial_data_front : std_logic_vector(47 downto 0);
- signal rx_serial_data_front : std_logic_vector(47 downto 0);
- signal dataloopback_front : std_logic_vector(3071 downto 0);
- signal controlloopback_front : std_logic_vector(383 downto 0);
- signal tx_serdesclk_front : std_logic_vector(47 downto 0);
- signal validloopback_front : std_logic_vector(47 downto 0);
- signal tx_analogreset_front : std_logic_vector(47 downto 0);
- signal tx_digitalreset_front : std_logic_vector(47 downto 0);
- signal rx_analogreset_front : std_logic_vector(47 downto 0);
- signal rx_digitalreset_front : std_logic_vector(47 downto 0);
- signal tx_cal_busy_front : std_logic_vector(47 downto 0);
- signal rx_cal_busy_front : std_logic_vector(47 downto 0);
- signal txpll_cal_busy_front : std_logic_vector(47 downto 0);
- signal pll_cal_busy_front : std_logic;
- signal rx_is_lockedtodata_front: std_logic_vector(47 downto 0);
- signal pll_powerdown_front : std_logic_vector(0 downto 0);
- signal pll_locked_front : std_logic_vector(0 downto 0);
- signal tx_serial_clk_front : std_logic_vector(47 downto 0);
- signal mcgb_serial_clk_front : std_logic;
-
- signal tx_serial_data_back : std_logic_vector(47 downto 0);
- signal rx_serial_data_back : std_logic_vector(47 downto 0);
- signal dataloopback_back : std_logic_vector(3071 downto 0);
- signal controlloopback_back : std_logic_vector(383 downto 0);
- signal dataloopback_test : std_logic_vector(1535 downto 0);
- signal controlloopback_test : std_logic_vector(191 downto 0);
- signal tx_serdesclk_back : std_logic_vector(47 downto 0);
- signal validloopback_back : std_logic_vector(47 downto 0);
- signal tx_analogreset_back : std_logic_vector(47 downto 0);
- signal tx_digitalreset_back : std_logic_vector(47 downto 0);
- signal rx_analogreset_back : std_logic_vector(47 downto 0);
- signal rx_digitalreset_back : std_logic_vector(47 downto 0);
- signal tx_cal_busy_back : std_logic_vector(47 downto 0);
- signal rx_cal_busy_back : std_logic_vector(47 downto 0);
- signal txpll_cal_busy_back : std_logic_vector(47 downto 0);
- signal pll_cal_busy_back_upper : std_logic;
- signal pll_cal_busy_back_lower : std_logic;
- signal rx_is_lockedtodata_back: std_logic_vector(47 downto 0);
- signal pll_powerdown_back_upper : std_logic_vector(0 downto 0);
- signal pll_powerdown_back_lower : std_logic_vector(0 downto 0);
- signal pll_locked_back_upper : std_logic_vector(0 downto 0);
- signal pll_locked_back_lower : std_logic_vector(0 downto 0);
- signal tx_serial_clk_back : std_logic_vector(47 downto 0);
- signal mcgb_serial_clk_back_upper : std_logic;
- signal mcgb_serial_clk_back_lower : std_logic;
-
- -- signals for the bidirectional and misc ios
- signal inta_in : std_logic;
- signal intb_in : std_logic;
- signal testio_in : std_logic_vector(5 downto 0);
- signal qsfp_led_in : std_logic_vector(11 downto 0);
- signal bck_err_in : std_logic_vector(2 downto 0);
- signal inta_out : std_logic;
- signal intb_out : std_logic;
- signal testio_out : std_logic_vector(5 downto 0);
- signal qsfp_led_out : std_logic_vector(11 downto 0);
- signal bck_err_out : std_logic_vector(2 downto 0);
- signal ver_id_pmbusalert : std_logic_vector(11 downto 0);
+ -- constants
+ constant cs_sim : std_logic := '0';
+ constant cs_sync : std_logic := '1';
+
+ -- general reset and clock signals
+ signal reset_n : std_logic;
+ signal reset_p : std_logic;
+ signal pout_wdi : std_logic := '0';
+ signal sys_clk : std_logic := '0';
+ signal sys_locked : std_logic := '0';
+ signal mm_clk : std_logic := '0';
+ signal clk_125 : std_logic := '0';
+ signal CLK_buffered : std_logic := '0';
+
+ -- signals for the ddr4 controllers
+ signal local_i_cal_success : std_logic;
+ signal local_i_cal_fail : std_logic;
+ signal local_i_reset_n : std_logic;
+ signal local_i_clk : std_logic;
+ signal local_i_ready : std_logic;
+ signal local_i_read : std_logic;
+ signal local_i_write : std_logic;
+ signal local_i_address : std_logic_vector(26 downto 0);
+ signal local_i_readdata : std_logic_vector(575 downto 0);
+ signal local_i_writedata : std_logic_vector(575 downto 0);
+ signal local_i_burstcount : std_logic_vector(6 downto 0);
+ signal local_i_be : std_logic_vector(71 downto 0);
+ signal local_i_read_data_valid : std_logic;
+ signal mb_i_a_internal : std_logic_vector(16 downto 0);
+ signal local_ii_cal_success : std_logic;
+ signal local_ii_cal_fail : std_logic;
+ signal local_ii_reset_n : std_logic;
+ signal local_ii_clk : std_logic;
+ signal local_ii_ready : std_logic;
+ signal local_ii_read : std_logic;
+ signal local_ii_write : std_logic;
+ signal local_ii_address : std_logic_vector(26 downto 0);
+ signal local_ii_readdata : std_logic_vector(575 downto 0);
+ signal local_ii_writedata : std_logic_vector(575 downto 0);
+ signal local_ii_burstcount : std_logic_vector(6 downto 0);
+ signal local_ii_be : std_logic_vector(71 downto 0);
+ signal local_ii_read_data_valid: std_logic;
+ signal mb_ii_a_internal : std_logic_vector(16 downto 0);
+
+ -- signals for the transceivers
+ signal tx_serial_data_front : std_logic_vector(47 downto 0);
+ signal rx_serial_data_front : std_logic_vector(47 downto 0);
+ signal dataloopback_front : std_logic_vector(3071 downto 0);
+ signal controlloopback_front : std_logic_vector(383 downto 0);
+ signal tx_serdesclk_front : std_logic_vector(47 downto 0);
+ signal validloopback_front : std_logic_vector(47 downto 0);
+ signal tx_analogreset_front : std_logic_vector(47 downto 0);
+ signal tx_digitalreset_front : std_logic_vector(47 downto 0);
+ signal rx_analogreset_front : std_logic_vector(47 downto 0);
+ signal rx_digitalreset_front : std_logic_vector(47 downto 0);
+ signal tx_cal_busy_front : std_logic_vector(47 downto 0);
+ signal rx_cal_busy_front : std_logic_vector(47 downto 0);
+ signal txpll_cal_busy_front : std_logic_vector(47 downto 0);
+ signal pll_cal_busy_front : std_logic;
+ signal rx_is_lockedtodata_front: std_logic_vector(47 downto 0);
+ signal pll_powerdown_front : std_logic_vector(0 downto 0);
+ signal pll_locked_front : std_logic_vector(0 downto 0);
+ signal tx_serial_clk_front : std_logic_vector(47 downto 0);
+ signal mcgb_serial_clk_front : std_logic;
+
+ signal tx_serial_data_back : std_logic_vector(47 downto 0);
+ signal rx_serial_data_back : std_logic_vector(47 downto 0);
+ signal dataloopback_back : std_logic_vector(3071 downto 0);
+ signal controlloopback_back : std_logic_vector(383 downto 0);
+ signal dataloopback_test : std_logic_vector(1535 downto 0);
+ signal controlloopback_test : std_logic_vector(191 downto 0);
+ signal tx_serdesclk_back : std_logic_vector(47 downto 0);
+ signal validloopback_back : std_logic_vector(47 downto 0);
+ signal tx_analogreset_back : std_logic_vector(47 downto 0);
+ signal tx_digitalreset_back : std_logic_vector(47 downto 0);
+ signal rx_analogreset_back : std_logic_vector(47 downto 0);
+ signal rx_digitalreset_back : std_logic_vector(47 downto 0);
+ signal tx_cal_busy_back : std_logic_vector(47 downto 0);
+ signal rx_cal_busy_back : std_logic_vector(47 downto 0);
+ signal txpll_cal_busy_back : std_logic_vector(47 downto 0);
+ signal pll_cal_busy_back_upper : std_logic;
+ signal pll_cal_busy_back_lower : std_logic;
+ signal rx_is_lockedtodata_back: std_logic_vector(47 downto 0);
+ signal pll_powerdown_back_upper : std_logic_vector(0 downto 0);
+ signal pll_powerdown_back_lower : std_logic_vector(0 downto 0);
+ signal pll_locked_back_upper : std_logic_vector(0 downto 0);
+ signal pll_locked_back_lower : std_logic_vector(0 downto 0);
+ signal tx_serial_clk_back : std_logic_vector(47 downto 0);
+ signal mcgb_serial_clk_back_upper : std_logic;
+ signal mcgb_serial_clk_back_lower : std_logic;
+
+ -- signals for the bidirectional and misc ios
+ signal inta_in : std_logic;
+ signal intb_in : std_logic;
+ signal testio_in : std_logic_vector(5 downto 0);
+ signal qsfp_led_in : std_logic_vector(11 downto 0);
+ signal bck_err_in : std_logic_vector(2 downto 0);
+ signal inta_out : std_logic;
+ signal intb_out : std_logic;
+ signal testio_out : std_logic_vector(5 downto 0);
+ signal qsfp_led_out : std_logic_vector(11 downto 0);
+ signal bck_err_out : std_logic_vector(2 downto 0);
+ signal ver_id_pmbusalert : std_logic_vector(11 downto 0);
begin
- WDI <= 'Z';
-
- -- ****** DDR4 memory controllers ******
-
- mb_i_a <= mb_i_a_internal(13 downto 0);
- mb_i_we_a14 <= mb_i_a_internal(14);
- mb_i_cas_a15 <= mb_i_a_internal(15);
- mb_i_ras_a16 <= mb_i_a_internal(16);
-
- local_i_proc : process(local_i_clk, local_i_reset_n)
- begin
- if local_i_reset_n = '0' then
- local_i_read <= '0';
- local_i_write <= '0';
- local_i_address <= (others => '0');
- local_i_writedata <= (others => '0');
- local_i_burstcount <= (others => '0');
- local_i_be <= (others => '0');
- else
- if local_i_clk'event and local_i_clk = '1' then
- local_i_be <= (others => '1');
- if local_i_ready = '1' then
- local_i_read <= not local_i_read;
- local_i_write <= local_i_read_data_valid;
- local_i_address <= local_i_address + 1;
- if local_i_read_data_valid = '1' then
- local_i_writedata <= not local_i_readdata;
- else
- local_i_writedata <= (others => '1');
- end if;
+ WDI <= 'Z';
+
+ -- ****** DDR4 memory controllers ******
+
+ mb_i_a <= mb_i_a_internal(13 downto 0);
+ mb_i_we_a14 <= mb_i_a_internal(14);
+ mb_i_cas_a15 <= mb_i_a_internal(15);
+ mb_i_ras_a16 <= mb_i_a_internal(16);
+
+ local_i_proc : process(local_i_clk, local_i_reset_n)
+ begin
+ if local_i_reset_n = '0' then
+ local_i_read <= '0';
+ local_i_write <= '0';
+ local_i_address <= (others => '0');
+ local_i_writedata <= (others => '0');
+ local_i_burstcount <= (others => '0');
+ local_i_be <= (others => '0');
+ else
+ if local_i_clk'event and local_i_clk = '1' then
+ local_i_be <= (others => '1');
+ if local_i_ready = '1' then
+ local_i_read <= not local_i_read;
+ local_i_write <= local_i_read_data_valid;
+ local_i_address <= local_i_address + 1;
+ if local_i_read_data_valid = '1' then
+ local_i_writedata <= not local_i_readdata;
+ else
+ local_i_writedata <= (others => '1');
end if;
- end if;
+ end if;
end if;
- end process;
-
- u_ddr4_i : ddr4
- port map (
- global_reset_n => reset_n,
- pll_ref_clk => MB_I_REF_CLK,
- oct_rzqin => MB_I_RZQ,
- mem_ck => mb_i_ck,
- mem_ck_n => mb_i_ck_n,
- mem_a => mb_i_a_internal,
- mem_act_n => mb_i_act_n,
- mem_ba => mb_i_ba,
- mem_bg => mb_i_bg,
- mem_cke => mb_i_cke,
- mem_cs_n => mb_i_cs,
- mem_odt => mb_i_odt,
- mem_reset_n => mb_i_reset_n,
- mem_alert_n => mb_i_alert_n,
- mem_par => mb_i_parity,
- mem_dqs => mb_i_dqs,
- mem_dqs_n => mb_i_dqs_n,
- mem_dq(63 downto 0) => mb_i_dq,
- mem_dq(71 downto 64) => mb_i_cb,
- mem_dbi_n => mb_i_dm,
- local_cal_success => local_i_cal_success,
- local_cal_fail => local_i_cal_fail,
- emif_usr_reset_n => local_i_reset_n,
- emif_usr_clk => local_i_clk,
- amm_ready_0 => local_i_ready,
- amm_read_0 => local_i_read,
- amm_write_0 => local_i_write,
- amm_address_0 => local_i_address,
- amm_readdata_0 => local_i_readdata,
- amm_writedata_0 => local_i_writedata,
- amm_burstcount_0 => local_i_burstcount,
- amm_byteenable_0 => local_i_be,
- amm_readdatavalid_0 => local_i_read_data_valid
- );
-
- mb_ii_a <= mb_ii_a_internal(13 downto 0);
- mb_ii_we_a14 <= mb_ii_a_internal(14);
- mb_ii_cas_a15 <= mb_ii_a_internal(15);
- mb_ii_ras_a16 <= mb_ii_a_internal(16);
-
- local_ii_proc : process(local_ii_clk, local_ii_reset_n)
- begin
- if local_ii_reset_n = '0' then
- local_ii_read <= '0';
- local_ii_write <= '0';
- local_ii_address <= (others => '0');
- local_ii_writedata <= (others => '0');
- local_ii_burstcount <= (others => '0');
- local_ii_be <= (others => '0');
- else
- if local_ii_clk'event and local_ii_clk = '1' then
- local_ii_be <= (others => '1');
- if local_ii_ready = '1' then
- local_ii_read <= not local_ii_read;
- local_ii_write <= local_ii_read_data_valid;
- local_ii_address <= local_ii_address + 1;
- if local_ii_read_data_valid = '1' then
- local_ii_writedata <= not local_ii_readdata;
- else
- local_ii_writedata <= (others => '1');
- end if;
+ end if;
+ end process;
+
+ u_ddr4_i : ddr4
+ port map (
+ global_reset_n => reset_n,
+ pll_ref_clk => MB_I_REF_CLK,
+ oct_rzqin => MB_I_RZQ,
+ mem_ck => mb_i_ck,
+ mem_ck_n => mb_i_ck_n,
+ mem_a => mb_i_a_internal,
+ mem_act_n => mb_i_act_n,
+ mem_ba => mb_i_ba,
+ mem_bg => mb_i_bg,
+ mem_cke => mb_i_cke,
+ mem_cs_n => mb_i_cs,
+ mem_odt => mb_i_odt,
+ mem_reset_n => mb_i_reset_n,
+ mem_alert_n => mb_i_alert_n,
+ mem_par => mb_i_parity,
+ mem_dqs => mb_i_dqs,
+ mem_dqs_n => mb_i_dqs_n,
+ mem_dq(63 downto 0) => mb_i_dq,
+ mem_dq(71 downto 64) => mb_i_cb,
+ mem_dbi_n => mb_i_dm,
+ local_cal_success => local_i_cal_success,
+ local_cal_fail => local_i_cal_fail,
+ emif_usr_reset_n => local_i_reset_n,
+ emif_usr_clk => local_i_clk,
+ amm_ready_0 => local_i_ready,
+ amm_read_0 => local_i_read,
+ amm_write_0 => local_i_write,
+ amm_address_0 => local_i_address,
+ amm_readdata_0 => local_i_readdata,
+ amm_writedata_0 => local_i_writedata,
+ amm_burstcount_0 => local_i_burstcount,
+ amm_byteenable_0 => local_i_be,
+ amm_readdatavalid_0 => local_i_read_data_valid
+ );
+
+ mb_ii_a <= mb_ii_a_internal(13 downto 0);
+ mb_ii_we_a14 <= mb_ii_a_internal(14);
+ mb_ii_cas_a15 <= mb_ii_a_internal(15);
+ mb_ii_ras_a16 <= mb_ii_a_internal(16);
+
+ local_ii_proc : process(local_ii_clk, local_ii_reset_n)
+ begin
+ if local_ii_reset_n = '0' then
+ local_ii_read <= '0';
+ local_ii_write <= '0';
+ local_ii_address <= (others => '0');
+ local_ii_writedata <= (others => '0');
+ local_ii_burstcount <= (others => '0');
+ local_ii_be <= (others => '0');
+ else
+ if local_ii_clk'event and local_ii_clk = '1' then
+ local_ii_be <= (others => '1');
+ if local_ii_ready = '1' then
+ local_ii_read <= not local_ii_read;
+ local_ii_write <= local_ii_read_data_valid;
+ local_ii_address <= local_ii_address + 1;
+ if local_ii_read_data_valid = '1' then
+ local_ii_writedata <= not local_ii_readdata;
+ else
+ local_ii_writedata <= (others => '1');
end if;
- end if;
+ end if;
end if;
- end process;
-
- u_ddr4_ii : ddr4
- port map (
- global_reset_n => reset_n,
- pll_ref_clk => MB_II_REF_CLK,
- oct_rzqin => MB_II_RZQ,
- mem_ck => mb_ii_ck,
- mem_ck_n => mb_ii_ck_n,
- mem_a => mb_ii_a_internal,
- mem_act_n => mb_ii_act_n,
- mem_ba => mb_ii_ba,
- mem_bg => mb_ii_bg,
- mem_cke => mb_ii_cke,
- mem_cs_n => mb_ii_cs,
- mem_odt => mb_ii_odt,
- mem_reset_n => mb_ii_reset_n,
- mem_alert_n => mb_ii_alert_n,
- mem_par => mb_ii_parity,
- mem_dqs => mb_ii_dqs,
- mem_dqs_n => mb_ii_dqs_n,
- mem_dq(63 downto 0) => mb_ii_dq,
- mem_dq(71 downto 64) => mb_ii_cb,
- mem_dbi_n => mb_ii_dm,
- local_cal_success => local_ii_cal_success,
- local_cal_fail => local_ii_cal_fail,
- emif_usr_reset_n => local_ii_reset_n,
- emif_usr_clk => local_ii_clk,
- amm_ready_0 => local_ii_ready,
- amm_read_0 => local_ii_read,
- amm_write_0 => local_ii_write,
- amm_address_0 => local_ii_address,
- amm_readdata_0 => local_ii_readdata,
- amm_writedata_0 => local_ii_writedata,
- amm_burstcount_0 => local_ii_burstcount,
- amm_byteenable_0 => local_ii_be,
- amm_readdatavalid_0 => local_ii_read_data_valid
- );
-
-
--- -- ****** Front side transceivers ******
---
- RING_0_TX <= tx_serial_data_front(47 downto 36);
- QSFP_0_TX <= tx_serial_data_front(35 downto 32);
- QSFP_1_TX <= tx_serial_data_front(31 downto 28);
- QSFP_2_TX <= tx_serial_data_front(27 downto 24);
- QSFP_3_TX <= tx_serial_data_front(23 downto 20);
- QSFP_4_TX <= tx_serial_data_front(19 downto 16);
- QSFP_5_TX <= tx_serial_data_front(15 downto 12);
- RING_1_TX <= tx_serial_data_front(11 downto 0);
-
- rx_serial_data_front <= RING_0_RX
+ end if;
+ end process;
+
+ u_ddr4_ii : ddr4
+ port map (
+ global_reset_n => reset_n,
+ pll_ref_clk => MB_II_REF_CLK,
+ oct_rzqin => MB_II_RZQ,
+ mem_ck => mb_ii_ck,
+ mem_ck_n => mb_ii_ck_n,
+ mem_a => mb_ii_a_internal,
+ mem_act_n => mb_ii_act_n,
+ mem_ba => mb_ii_ba,
+ mem_bg => mb_ii_bg,
+ mem_cke => mb_ii_cke,
+ mem_cs_n => mb_ii_cs,
+ mem_odt => mb_ii_odt,
+ mem_reset_n => mb_ii_reset_n,
+ mem_alert_n => mb_ii_alert_n,
+ mem_par => mb_ii_parity,
+ mem_dqs => mb_ii_dqs,
+ mem_dqs_n => mb_ii_dqs_n,
+ mem_dq(63 downto 0) => mb_ii_dq,
+ mem_dq(71 downto 64) => mb_ii_cb,
+ mem_dbi_n => mb_ii_dm,
+ local_cal_success => local_ii_cal_success,
+ local_cal_fail => local_ii_cal_fail,
+ emif_usr_reset_n => local_ii_reset_n,
+ emif_usr_clk => local_ii_clk,
+ amm_ready_0 => local_ii_ready,
+ amm_read_0 => local_ii_read,
+ amm_write_0 => local_ii_write,
+ amm_address_0 => local_ii_address,
+ amm_readdata_0 => local_ii_readdata,
+ amm_writedata_0 => local_ii_writedata,
+ amm_burstcount_0 => local_ii_burstcount,
+ amm_byteenable_0 => local_ii_be,
+ amm_readdatavalid_0 => local_ii_read_data_valid
+ );
+
+
+ -- -- ****** Front side transceivers ******
+ --
+ RING_0_TX <= tx_serial_data_front(47 downto 36);
+ QSFP_0_TX <= tx_serial_data_front(35 downto 32);
+ QSFP_1_TX <= tx_serial_data_front(31 downto 28);
+ QSFP_2_TX <= tx_serial_data_front(27 downto 24);
+ QSFP_3_TX <= tx_serial_data_front(23 downto 20);
+ QSFP_4_TX <= tx_serial_data_front(19 downto 16);
+ QSFP_5_TX <= tx_serial_data_front(15 downto 12);
+ RING_1_TX <= tx_serial_data_front(11 downto 0);
+
+ rx_serial_data_front <= RING_0_RX
& QSFP_0_RX & QSFP_1_RX & QSFP_2_RX & QSFP_3_RX & QSFP_4_RX & QSFP_5_RX
& RING_1_RX ;
- transceiver_phy_front : transceiver_phy
- port map (
- tx_analogreset => tx_analogreset_front,
- tx_digitalreset => tx_digitalreset_front,
- rx_analogreset => rx_analogreset_front,
- rx_digitalreset => rx_digitalreset_front,
- tx_cal_busy => tx_cal_busy_front,
- rx_cal_busy => rx_cal_busy_front,
- rx_is_lockedtodata => rx_is_lockedtodata_front,
- tx_serial_clk0 => tx_serial_clk_front,
- rx_cdr_refclk0 => sa_clk,
- tx_serial_data => tx_serial_data_front,
- rx_serial_data => rx_serial_data_front,
- tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_front,
- tx_clkout => tx_serdesclk_front,
- rx_clkout => open,
- tx_enh_data_valid => validloopback_front,
- rx_enh_data_valid => validloopback_front,
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_front,
- tx_control => controlloopback_front,
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_front,
- rx_control => controlloopback_front,
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_front : transceiver_reset_controller
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_front,
- tx_analogreset => tx_analogreset_front,
- tx_digitalreset => tx_digitalreset_front,
- tx_ready => open,
- pll_locked => pll_locked_front,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_front,
- rx_analogreset => rx_analogreset_front,
- rx_digitalreset => rx_digitalreset_front,
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_front,
- rx_cal_busy => rx_cal_busy_front
- );
-
- transceiver_pll_front : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_front(0),
- pll_refclk0 => sa_clk,
- pll_locked => pll_locked_front(0),
- pll_cal_busy => pll_cal_busy_front,
- mcgb_rst => pll_powerdown_front(0),
- mcgb_serial_clk => mcgb_serial_clk_front
- );
-
- tx_serial_clk_front <= (others => mcgb_serial_clk_front);
- txpll_cal_busy_front <= tx_cal_busy_front when pll_cal_busy_front = '0' else (others => '1');
-
- -- ****** Back side transceivers ******
- -- upper 24 transceivers use sb_clk
- -- Nov 4 - temporarily disconnect BCK_TX/RX(47) to see what gets synthesised away
-
- BCK_TX(47 downto 0) <= tx_serial_data_back(47 downto 0);
--- BCK_TX(47) <= '0';
-
- rx_serial_data_back(47 downto 0) <= BCK_RX(47 downto 0);
--- dataloopback_test <= X"0000000000000000" & dataloopback_back(3007 downto 1536);
--- controlloopback_test <= X"00" & controlloopback_back(375 downto 192);
-
- transceiver_phy_back_upper : transceiver_phy_24channel
- port map (
- tx_analogreset => tx_analogreset_back(47 downto 24),
- tx_digitalreset => tx_digitalreset_back(47 downto 24),
- rx_analogreset => rx_analogreset_back(47 downto 24),
- rx_digitalreset => rx_digitalreset_back(47 downto 24),
- tx_cal_busy => tx_cal_busy_back(47 downto 24),
- rx_cal_busy => rx_cal_busy_back(47 downto 24),
- rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
- tx_serial_clk0 => tx_serial_clk_back(47 downto 24),
- rx_cdr_refclk0 => sb_clk,
- tx_serial_data => tx_serial_data_back(47 downto 24),
- rx_serial_data => rx_serial_data_back(47 downto 24),
- tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_back(47 downto 24),
- tx_clkout => tx_serdesclk_back(47 downto 24),
- rx_clkout => open,
- tx_enh_data_valid => validloopback_back(47 downto 24),
- rx_enh_data_valid => validloopback_back(47 downto 24),
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_back(3071 downto 1536),
- tx_control => controlloopback_back(383 downto 192),
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_back(3071 downto 1536),
- rx_control => controlloopback_back(383 downto 192),
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_back_upper : transceiver_reset_controller_24
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_back_upper,
- tx_analogreset => tx_analogreset_back(47 downto 24),
- tx_digitalreset => tx_digitalreset_back(47 downto 24),
- tx_ready => open,
- pll_locked => pll_locked_back_upper,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_back(47 downto 24),
- rx_analogreset => rx_analogreset_back(47 downto 24),
- rx_digitalreset => rx_digitalreset_back(47 downto 24),
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
- rx_cal_busy => rx_cal_busy_back(47 downto 24)
- );
-
- transceiver_pll_back_upper : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_back_upper(0),
- pll_refclk0 => sb_clk,
- pll_locked => pll_locked_back_upper(0),
- pll_cal_busy => pll_cal_busy_back_upper,
- mcgb_rst => pll_powerdown_back_upper(0),
- mcgb_serial_clk => mcgb_serial_clk_back_upper
- );
-
- tx_serial_clk_back(47 downto 24) <= (others => mcgb_serial_clk_back_upper);
- txpll_cal_busy_back(47 downto 24) <= tx_cal_busy_back(47 downto 24) when pll_cal_busy_back_upper = '0' else (others => '1');
-
- -- lower 24 transceivers use sb_clk
-
-
- transceiver_phy_back_lower : transceiver_phy_24channel
- port map (
- tx_analogreset => tx_analogreset_back(23 downto 0),
- tx_digitalreset => tx_digitalreset_back(23 downto 0),
- rx_analogreset => rx_analogreset_back(23 downto 0),
- rx_digitalreset => rx_digitalreset_back(23 downto 0),
- tx_cal_busy => tx_cal_busy_back(23 downto 0),
- rx_cal_busy => rx_cal_busy_back(23 downto 0),
- rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
- tx_serial_clk0 => tx_serial_clk_back(23 downto 0),
- rx_cdr_refclk0 => bck_ref_clk,
- tx_serial_data => tx_serial_data_back(23 downto 0),
- rx_serial_data => rx_serial_data_back(23 downto 0),
- tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_back(23 downto 0),
- tx_clkout => tx_serdesclk_back(23 downto 0),
- rx_clkout => open,
- tx_enh_data_valid => validloopback_back(23 downto 0),
- rx_enh_data_valid => validloopback_back(23 downto 0),
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_back(1535 downto 0),
- tx_control => controlloopback_back(191 downto 0),
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_back(1535 downto 0),
- rx_control => controlloopback_back(191 downto 0),
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_back_lower : transceiver_reset_controller_24
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_back_lower,
- tx_analogreset => tx_analogreset_back(23 downto 0),
- tx_digitalreset => tx_digitalreset_back(23 downto 0),
- tx_ready => open,
- pll_locked => pll_locked_back_lower,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_back(23 downto 0),
- rx_analogreset => rx_analogreset_back(23 downto 0),
- rx_digitalreset => rx_digitalreset_back(23 downto 0),
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
- rx_cal_busy => rx_cal_busy_back(23 downto 0)
- );
-
- transceiver_pll_back_lower : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_back_lower(0),
- pll_refclk0 => bck_ref_clk,
- pll_locked => pll_locked_back_lower(0),
- pll_cal_busy => pll_cal_busy_back_lower,
- mcgb_rst => pll_powerdown_back_lower(0),
- mcgb_serial_clk => mcgb_serial_clk_back_lower
- );
-
- tx_serial_clk_back(23 downto 0) <= (others => mcgb_serial_clk_back_lower);
- txpll_cal_busy_back(23 downto 0) <= tx_cal_busy_back(23 downto 0) when pll_cal_busy_back_lower = '0' else (others => '1');
-
- -- ****** node control for resets and wdi
-
- u_node_ctrl : entity unb_common_lib.unb_node_ctrl
- generic map (
- g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => ETH_clk,
- xo_rst_n => reset_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => open,
- st_clk => clk,
- st_rst => open,
- wdi_in => pout_wdi,
- wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
- pulse_us => open,
- pulse_ms => open,
- pulse_s => open -- could be used to toggle a LED
- );
-
- reset_p <= not reset_n;
-
- u0 : component sys_clkctrl
- port map (
- inclk => CLK, -- altclkctrl_input.inclk
- outclk => CLK_buffered -- altclkctrl_output.outclk
+ transceiver_phy_front : transceiver_phy
+ port map (
+ tx_analogreset => tx_analogreset_front,
+ tx_digitalreset => tx_digitalreset_front,
+ rx_analogreset => rx_analogreset_front,
+ rx_digitalreset => rx_digitalreset_front,
+ tx_cal_busy => tx_cal_busy_front,
+ rx_cal_busy => rx_cal_busy_front,
+ rx_is_lockedtodata => rx_is_lockedtodata_front,
+ tx_serial_clk0 => tx_serial_clk_front,
+ rx_cdr_refclk0 => sa_clk,
+ tx_serial_data => tx_serial_data_front,
+ rx_serial_data => rx_serial_data_front,
+ tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_front,
+ tx_clkout => tx_serdesclk_front,
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_front,
+ rx_enh_data_valid => validloopback_front,
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_front,
+ tx_control => controlloopback_front,
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_front,
+ rx_control => controlloopback_front,
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_front : transceiver_reset_controller
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_front,
+ tx_analogreset => tx_analogreset_front,
+ tx_digitalreset => tx_digitalreset_front,
+ tx_ready => open,
+ pll_locked => pll_locked_front,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_front,
+ rx_analogreset => rx_analogreset_front,
+ rx_digitalreset => rx_digitalreset_front,
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_front,
+ rx_cal_busy => rx_cal_busy_front
+ );
+
+ transceiver_pll_front : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_front(0),
+ pll_refclk0 => sa_clk,
+ pll_locked => pll_locked_front(0),
+ pll_cal_busy => pll_cal_busy_front,
+ mcgb_rst => pll_powerdown_front(0),
+ mcgb_serial_clk => mcgb_serial_clk_front
);
+ tx_serial_clk_front <= (others => mcgb_serial_clk_front);
+ txpll_cal_busy_front <= tx_cal_busy_front when pll_cal_busy_front = '0' else (others => '1');
+
+ -- ****** Back side transceivers ******
+ -- upper 24 transceivers use sb_clk
+ -- Nov 4 - temporarily disconnect BCK_TX/RX(47) to see what gets synthesised away
+
+ BCK_TX(47 downto 0) <= tx_serial_data_back(47 downto 0);
+ -- BCK_TX(47) <= '0';
+
+ rx_serial_data_back(47 downto 0) <= BCK_RX(47 downto 0);
+ -- dataloopback_test <= X"0000000000000000" & dataloopback_back(3007 downto 1536);
+ -- controlloopback_test <= X"00" & controlloopback_back(375 downto 192);
+
+ transceiver_phy_back_upper : transceiver_phy_24channel
+ port map (
+ tx_analogreset => tx_analogreset_back(47 downto 24),
+ tx_digitalreset => tx_digitalreset_back(47 downto 24),
+ rx_analogreset => rx_analogreset_back(47 downto 24),
+ rx_digitalreset => rx_digitalreset_back(47 downto 24),
+ tx_cal_busy => tx_cal_busy_back(47 downto 24),
+ rx_cal_busy => rx_cal_busy_back(47 downto 24),
+ rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
+ tx_serial_clk0 => tx_serial_clk_back(47 downto 24),
+ rx_cdr_refclk0 => sb_clk,
+ tx_serial_data => tx_serial_data_back(47 downto 24),
+ rx_serial_data => rx_serial_data_back(47 downto 24),
+ tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_back(47 downto 24),
+ tx_clkout => tx_serdesclk_back(47 downto 24),
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_back(47 downto 24),
+ rx_enh_data_valid => validloopback_back(47 downto 24),
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_back(3071 downto 1536),
+ tx_control => controlloopback_back(383 downto 192),
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_back(3071 downto 1536),
+ rx_control => controlloopback_back(383 downto 192),
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_back_upper : transceiver_reset_controller_24
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_back_upper,
+ tx_analogreset => tx_analogreset_back(47 downto 24),
+ tx_digitalreset => tx_digitalreset_back(47 downto 24),
+ tx_ready => open,
+ pll_locked => pll_locked_back_upper,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_back(47 downto 24),
+ rx_analogreset => rx_analogreset_back(47 downto 24),
+ rx_digitalreset => rx_digitalreset_back(47 downto 24),
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
+ rx_cal_busy => rx_cal_busy_back(47 downto 24)
+ );
+
+ transceiver_pll_back_upper : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_back_upper(0),
+ pll_refclk0 => sb_clk,
+ pll_locked => pll_locked_back_upper(0),
+ pll_cal_busy => pll_cal_busy_back_upper,
+ mcgb_rst => pll_powerdown_back_upper(0),
+ mcgb_serial_clk => mcgb_serial_clk_back_upper
+ );
+
+ tx_serial_clk_back(47 downto 24) <= (others => mcgb_serial_clk_back_upper);
+ txpll_cal_busy_back(47 downto 24) <= tx_cal_busy_back(47 downto 24) when pll_cal_busy_back_upper = '0' else (others => '1');
+
+ -- lower 24 transceivers use sb_clk
+
+
+ transceiver_phy_back_lower : transceiver_phy_24channel
+ port map (
+ tx_analogreset => tx_analogreset_back(23 downto 0),
+ tx_digitalreset => tx_digitalreset_back(23 downto 0),
+ rx_analogreset => rx_analogreset_back(23 downto 0),
+ rx_digitalreset => rx_digitalreset_back(23 downto 0),
+ tx_cal_busy => tx_cal_busy_back(23 downto 0),
+ rx_cal_busy => rx_cal_busy_back(23 downto 0),
+ rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
+ tx_serial_clk0 => tx_serial_clk_back(23 downto 0),
+ rx_cdr_refclk0 => bck_ref_clk,
+ tx_serial_data => tx_serial_data_back(23 downto 0),
+ rx_serial_data => rx_serial_data_back(23 downto 0),
+ tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_back(23 downto 0),
+ tx_clkout => tx_serdesclk_back(23 downto 0),
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_back(23 downto 0),
+ rx_enh_data_valid => validloopback_back(23 downto 0),
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_back(1535 downto 0),
+ tx_control => controlloopback_back(191 downto 0),
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_back(1535 downto 0),
+ rx_control => controlloopback_back(191 downto 0),
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_back_lower : transceiver_reset_controller_24
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_back_lower,
+ tx_analogreset => tx_analogreset_back(23 downto 0),
+ tx_digitalreset => tx_digitalreset_back(23 downto 0),
+ tx_ready => open,
+ pll_locked => pll_locked_back_lower,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_back(23 downto 0),
+ rx_analogreset => rx_analogreset_back(23 downto 0),
+ rx_digitalreset => rx_digitalreset_back(23 downto 0),
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
+ rx_cal_busy => rx_cal_busy_back(23 downto 0)
+ );
+
+ transceiver_pll_back_lower : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_back_lower(0),
+ pll_refclk0 => bck_ref_clk,
+ pll_locked => pll_locked_back_lower(0),
+ pll_cal_busy => pll_cal_busy_back_lower,
+ mcgb_rst => pll_powerdown_back_lower(0),
+ mcgb_serial_clk => mcgb_serial_clk_back_lower
+ );
+
+ tx_serial_clk_back(23 downto 0) <= (others => mcgb_serial_clk_back_lower);
+ txpll_cal_busy_back(23 downto 0) <= tx_cal_busy_back(23 downto 0) when pll_cal_busy_back_lower = '0' else (others => '1');
+
+ -- ****** node control for resets and wdi
+
+ u_node_ctrl : entity unb_common_lib.unb_node_ctrl
+ generic map (
+ g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ xo_clk => ETH_clk,
+ xo_rst_n => reset_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => open,
+ st_clk => clk,
+ st_rst => open,
+ wdi_in => pout_wdi,
+ wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ pulse_us => open,
+ pulse_ms => open,
+ pulse_s => open -- could be used to toggle a LED
+ );
+
+ reset_p <= not reset_n;
+
+ u0 : component sys_clkctrl
+ port map (
+ inclk => CLK, -- altclkctrl_input.inclk
+ outclk => CLK_buffered -- altclkctrl_output.outclk
+ );
+
+
+ u_system_pll : system_pll
+ port map(
+ -- refclk => ETH_CLK,
+ refclk => CLK_buffered,
+ -- refclk => INTB,
+ rst => reset_p,
+ locked => sys_locked,
+ outclk_0 => mm_clk, -- 100MHz
+ outclk_1 => sys_clk, -- 300MHz
+ outclk_2 => clk_125 -- 125MHz for 1ge
+ );
+
+ -- u_system_pll : system_fpll
+ -- port map(
+ -- pll_refclk0 => INTB,
+ -- pll_powerdown => reset_p,
+ -- pll_locked => sys_locked,
+ -- pll_cal_busy => open,
+ -- outclk0 => mm_clk, -- 100MHz
+ -- outclk1 => sys_clk, -- 300MHz
+ -- outclk2 => clk_125 -- 125MHz for 1ge
+ -- );
+
+
+ -- ****** i2c interfaces ******
+
+ u_qsys : unb2_pinning_qsys
+ port map (
+ clk_clk => mm_clk,
+ reset_reset_n => reset_n,
+ avs_i2c_master_0_gs_sim_export => cs_sim,
+ avs_i2c_master_0_sync_export => cs_sync,
+ avs_i2c_master_0_i2c_scl_export => sens_sc,
+ avs_i2c_master_0_i2c_sda_export => sens_sd,
+ avs_i2c_master_1_gs_sim_export => cs_sim,
+ avs_i2c_master_1_sync_export => cs_sync,
+ avs_i2c_master_1_i2c_scl_export => pmbus_sc,
+ avs_i2c_master_1_i2c_sda_export => pmbus_sd,
+ avs_i2c_master_2_gs_sim_export => cs_sim,
+ avs_i2c_master_2_sync_export => cs_sync,
+ avs_i2c_master_2_i2c_scl_export => bck_scl(0),
+ avs_i2c_master_2_i2c_sda_export => bck_sda(0),
+ avs_i2c_master_3_gs_sim_export => cs_sim,
+ avs_i2c_master_3_sync_export => cs_sync,
+ avs_i2c_master_3_i2c_scl_export => bck_scl(1),
+ avs_i2c_master_3_i2c_sda_export => bck_sda(1),
+ avs_i2c_master_4_sync_export => cs_sync,
+ avs_i2c_master_4_gs_sim_export => cs_sim,
+ avs_i2c_master_4_i2c_scl_export => bck_scl(2),
+ avs_i2c_master_4_i2c_sda_export => bck_sda(2),
+ avs_i2c_master_5_sync_export => cs_sync,
+ avs_i2c_master_5_gs_sim_export => cs_sim,
+ avs_i2c_master_5_i2c_sda_export => qsfp_sda(0),
+ avs_i2c_master_5_i2c_scl_export => qsfp_scl(0),
+ avs_i2c_master_6_sync_export => cs_sync,
+ avs_i2c_master_6_gs_sim_export => cs_sim,
+ avs_i2c_master_6_i2c_sda_export => qsfp_sda(1),
+ avs_i2c_master_6_i2c_scl_export => qsfp_scl(1),
+ avs_i2c_master_7_sync_export => cs_sync,
+ avs_i2c_master_7_gs_sim_export => cs_sim,
+ avs_i2c_master_7_i2c_sda_export => qsfp_sda(2),
+ avs_i2c_master_7_i2c_scl_export => qsfp_scl(2),
+ avs_i2c_master_8_sync_export => cs_sync,
+ avs_i2c_master_8_gs_sim_export => cs_sim,
+ avs_i2c_master_8_i2c_sda_export => qsfp_sda(3),
+ avs_i2c_master_8_i2c_scl_export => qsfp_scl(3),
+ avs_i2c_master_9_sync_export => cs_sync,
+ avs_i2c_master_9_gs_sim_export => cs_sim,
+ avs_i2c_master_9_i2c_sda_export => qsfp_sda(4),
+ avs_i2c_master_9_i2c_scl_export => qsfp_scl(4),
+ avs_i2c_master_10_sync_export => cs_sync,
+ avs_i2c_master_10_gs_sim_export => cs_sim,
+ avs_i2c_master_10_i2c_sda_export => qsfp_sda(5),
+ avs_i2c_master_10_i2c_scl_export => qsfp_scl(5),
+ avs_i2c_master_11_sync_export => cs_sync,
+ avs_i2c_master_11_gs_sim_export => cs_sim,
+ avs_i2c_master_11_i2c_sda_export => mb_sda,
+ avs_i2c_master_11_i2c_scl_export => mb_scl,
+ eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
+ eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
+ --eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
+ eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ --eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
+ eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
+ eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
+ pio_0_external_connection_export => ver_id_pmbusalert
+ );
- u_system_pll : system_pll
- port map(
--- refclk => ETH_CLK,
- refclk => CLK_buffered,
--- refclk => INTB,
- rst => reset_p,
- locked => sys_locked,
- outclk_0 => mm_clk, -- 100MHz
- outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
- );
-
--- u_system_pll : system_fpll
--- port map(
--- pll_refclk0 => INTB,
--- pll_powerdown => reset_p,
--- pll_locked => sys_locked,
--- pll_cal_busy => open,
--- outclk0 => mm_clk, -- 100MHz
--- outclk1 => sys_clk, -- 300MHz
--- outclk2 => clk_125 -- 125MHz for 1ge
--- );
-
-
- -- ****** i2c interfaces ******
-
- u_qsys : unb2_pinning_qsys
- port map (
- clk_clk => mm_clk,
- reset_reset_n => reset_n,
- avs_i2c_master_0_gs_sim_export => cs_sim,
- avs_i2c_master_0_sync_export => cs_sync,
- avs_i2c_master_0_i2c_scl_export => sens_sc,
- avs_i2c_master_0_i2c_sda_export => sens_sd,
- avs_i2c_master_1_gs_sim_export => cs_sim,
- avs_i2c_master_1_sync_export => cs_sync,
- avs_i2c_master_1_i2c_scl_export => pmbus_sc,
- avs_i2c_master_1_i2c_sda_export => pmbus_sd,
- avs_i2c_master_2_gs_sim_export => cs_sim,
- avs_i2c_master_2_sync_export => cs_sync,
- avs_i2c_master_2_i2c_scl_export => bck_scl(0),
- avs_i2c_master_2_i2c_sda_export => bck_sda(0),
- avs_i2c_master_3_gs_sim_export => cs_sim,
- avs_i2c_master_3_sync_export => cs_sync,
- avs_i2c_master_3_i2c_scl_export => bck_scl(1),
- avs_i2c_master_3_i2c_sda_export => bck_sda(1),
- avs_i2c_master_4_sync_export => cs_sync,
- avs_i2c_master_4_gs_sim_export => cs_sim,
- avs_i2c_master_4_i2c_scl_export => bck_scl(2),
- avs_i2c_master_4_i2c_sda_export => bck_sda(2),
- avs_i2c_master_5_sync_export => cs_sync,
- avs_i2c_master_5_gs_sim_export => cs_sim,
- avs_i2c_master_5_i2c_sda_export => qsfp_sda(0),
- avs_i2c_master_5_i2c_scl_export => qsfp_scl(0),
- avs_i2c_master_6_sync_export => cs_sync,
- avs_i2c_master_6_gs_sim_export => cs_sim,
- avs_i2c_master_6_i2c_sda_export => qsfp_sda(1),
- avs_i2c_master_6_i2c_scl_export => qsfp_scl(1),
- avs_i2c_master_7_sync_export => cs_sync,
- avs_i2c_master_7_gs_sim_export => cs_sim,
- avs_i2c_master_7_i2c_sda_export => qsfp_sda(2),
- avs_i2c_master_7_i2c_scl_export => qsfp_scl(2),
- avs_i2c_master_8_sync_export => cs_sync,
- avs_i2c_master_8_gs_sim_export => cs_sim,
- avs_i2c_master_8_i2c_sda_export => qsfp_sda(3),
- avs_i2c_master_8_i2c_scl_export => qsfp_scl(3),
- avs_i2c_master_9_sync_export => cs_sync,
- avs_i2c_master_9_gs_sim_export => cs_sim,
- avs_i2c_master_9_i2c_sda_export => qsfp_sda(4),
- avs_i2c_master_9_i2c_scl_export => qsfp_scl(4),
- avs_i2c_master_10_sync_export => cs_sync,
- avs_i2c_master_10_gs_sim_export => cs_sim,
- avs_i2c_master_10_i2c_sda_export => qsfp_sda(5),
- avs_i2c_master_10_i2c_scl_export => qsfp_scl(5),
- avs_i2c_master_11_sync_export => cs_sync,
- avs_i2c_master_11_gs_sim_export => cs_sim,
- avs_i2c_master_11_i2c_sda_export => mb_sda,
- avs_i2c_master_11_i2c_scl_export => mb_scl,
- eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
- eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
- --eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
- eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
- --eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
- eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
- eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
- eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
- pio_0_external_connection_export => ver_id_pmbusalert
- );
-
--- bidirectional and misc
--- use PPS as output enable
-
- INTA <= inta_out when PPS = '1' else 'Z';
- INTB <= intb_out when PPS = '1' else 'Z';
- TESTIO(5 downto 0) <= testio_out(5 downto 0) when PPS = '1' else "ZZZZZZ";
- QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
- BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
-
- inta_in <= INTA;
- intb_in <= INTB;
- testio_in(5 downto 0) <= TESTIO(5 downto 0);
- qsfp_led_in <= QSFP_LED;
- bck_err_in <= BCK_ERR;
-
- inta_out <= intb_in;
- intb_out <= inta_in;
- testio_out(5 downto 3) <= testio_in(2 downto 0);
- testio_out(2 downto 0) <= testio_in(5 downto 3);
- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
- bck_err_out(2) <= bck_err_in(1);
- bck_err_out(1) <= bck_err_in(0);
- bck_err_out(0) <= bck_err_in(2);
-
- ver_id_pmbusalert <= version & id & pmbus_alert & mb_event;
+ -- bidirectional and misc
+ -- use PPS as output enable
+
+ INTA <= inta_out when PPS = '1' else 'Z';
+ INTB <= intb_out when PPS = '1' else 'Z';
+ TESTIO(5 downto 0) <= testio_out(5 downto 0) when PPS = '1' else "ZZZZZZ";
+ QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
+ BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
+
+ inta_in <= INTA;
+ intb_in <= INTB;
+ testio_in(5 downto 0) <= TESTIO(5 downto 0);
+ qsfp_led_in <= QSFP_LED;
+ bck_err_in <= BCK_ERR;
+
+ inta_out <= intb_in;
+ intb_out <= inta_in;
+ testio_out(5 downto 3) <= testio_in(2 downto 0);
+ testio_out(2 downto 0) <= testio_in(5 downto 3);
+ qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
+ qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
+ bck_err_out(2) <= bck_err_in(1);
+ bck_err_out(1) <= bck_err_in(0);
+ bck_err_out(0) <= bck_err_in(2);
+
+ ver_id_pmbusalert <= version & id & pmbus_alert & mb_event;
end str;
diff --git a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
index fb173d75ba..e70e6ebfc5 100644
--- a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
+++ b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, unb_common_lib;
-use unb_common_lib.unb_common_pkg.all;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity unb2_singlemac is
@@ -48,54 +48,54 @@ entity unb2_singlemac is
BCK_REF_CLK : in std_logic; -- SerDes reference clock back
-- SO-DIMM DDR4 Memory Bank i2c (common)
--- MB_SCL : inout std_logic;
--- MB_SDA : inout std_logic;
+ -- MB_SCL : inout std_logic;
+ -- MB_SDA : inout std_logic;
-- SO-DIMM DDR4 Memory Bank I
--- MB_I_RZQ : in STD_LOGIC;
--- MB_I_REF_CLK : in STD_LOGIC; -- External reference clock
--- MB_I_A : out std_logic_vector (13 downto 0);
--- MB_I_ACT_N : out std_logic_vector(0 downto 0);
--- MB_I_BA : out std_logic_vector (1 downto 0);
--- MB_I_BG : out std_logic_vector (1 downto 0);
--- MB_I_CAS_A15 : out std_logic;
--- MB_I_CB : inout std_logic_vector (7 downto 0);
--- MB_I_CK : out std_logic_vector (1 downto 0);
--- MB_I_CK_n : out std_logic_vector (1 downto 0);
--- MB_I_CKE : out std_logic_vector (1 downto 0);
--- MB_I_CS : out std_logic_vector (1 downto 0);
--- MB_I_DM : inout std_logic_vector (8 downto 0);
--- MB_I_DQ : inout std_logic_vector (63 downto 0);
--- MB_I_DQS : inout std_logic_vector (8 downto 0);
--- MB_I_DQS_n : inout std_logic_vector (8 downto 0);
--- MB_I_ODT : out std_logic_vector (1 downto 0);
--- MB_I_PARITY : out std_logic_vector(0 downto 0);
--- MB_I_RAS_A16 : out std_logic;
--- MB_I_WE_A14 : out std_logic;
--- MB_I_RESET_N : out std_logic_vector(0 downto 0);
--- MB_I_ALERT_N : in std_logic_vector(0 downto 0);
+ -- MB_I_RZQ : in STD_LOGIC;
+ -- MB_I_REF_CLK : in STD_LOGIC; -- External reference clock
+ -- MB_I_A : out std_logic_vector (13 downto 0);
+ -- MB_I_ACT_N : out std_logic_vector(0 downto 0);
+ -- MB_I_BA : out std_logic_vector (1 downto 0);
+ -- MB_I_BG : out std_logic_vector (1 downto 0);
+ -- MB_I_CAS_A15 : out std_logic;
+ -- MB_I_CB : inout std_logic_vector (7 downto 0);
+ -- MB_I_CK : out std_logic_vector (1 downto 0);
+ -- MB_I_CK_n : out std_logic_vector (1 downto 0);
+ -- MB_I_CKE : out std_logic_vector (1 downto 0);
+ -- MB_I_CS : out std_logic_vector (1 downto 0);
+ -- MB_I_DM : inout std_logic_vector (8 downto 0);
+ -- MB_I_DQ : inout std_logic_vector (63 downto 0);
+ -- MB_I_DQS : inout std_logic_vector (8 downto 0);
+ -- MB_I_DQS_n : inout std_logic_vector (8 downto 0);
+ -- MB_I_ODT : out std_logic_vector (1 downto 0);
+ -- MB_I_PARITY : out std_logic_vector(0 downto 0);
+ -- MB_I_RAS_A16 : out std_logic;
+ -- MB_I_WE_A14 : out std_logic;
+ -- MB_I_RESET_N : out std_logic_vector(0 downto 0);
+ -- MB_I_ALERT_N : in std_logic_vector(0 downto 0);
-- SO-DIMM DDR4 Memory Bank II
--- MB_II_RZQ : in STD_LOGIC;
--- MB_II_REF_CLK : in STD_LOGIC; -- External reference clock
--- MB_II_A : out std_logic_vector (13 downto 0);
--- MB_II_ACT_N : out std_logic_vector(0 downto 0);
--- MB_II_BA : out std_logic_vector (1 downto 0);
--- MB_II_BG : out std_logic_vector (1 downto 0);
--- MB_II_CAS_A15 : out std_logic;
--- MB_II_CB : inout std_logic_vector (7 downto 0);
--- MB_II_CK : out std_logic_vector (1 downto 0);
--- MB_II_CK_n : out std_logic_vector (1 downto 0);
--- MB_II_CKE : out std_logic_vector (1 downto 0);
--- MB_II_CS : out std_logic_vector (1 downto 0);
--- MB_II_DM : inout std_logic_vector (8 downto 0);
--- MB_II_DQ : inout std_logic_vector (63 downto 0);
--- MB_II_DQS : inout std_logic_vector (8 downto 0);
--- MB_II_DQS_n : inout std_logic_vector (8 downto 0);
--- MB_II_ODT : out std_logic_vector (1 downto 0);
--- MB_II_PARITY : out std_logic_vector(0 downto 0);
--- MB_II_RAS_A16 : out std_logic;
--- MB_II_WE_A14 : out std_logic;
--- MB_II_RESET_N : out std_logic_vector(0 downto 0);
--- MB_II_ALERT_N : in std_logic_vector(0 downto 0);
+ -- MB_II_RZQ : in STD_LOGIC;
+ -- MB_II_REF_CLK : in STD_LOGIC; -- External reference clock
+ -- MB_II_A : out std_logic_vector (13 downto 0);
+ -- MB_II_ACT_N : out std_logic_vector(0 downto 0);
+ -- MB_II_BA : out std_logic_vector (1 downto 0);
+ -- MB_II_BG : out std_logic_vector (1 downto 0);
+ -- MB_II_CAS_A15 : out std_logic;
+ -- MB_II_CB : inout std_logic_vector (7 downto 0);
+ -- MB_II_CK : out std_logic_vector (1 downto 0);
+ -- MB_II_CK_n : out std_logic_vector (1 downto 0);
+ -- MB_II_CKE : out std_logic_vector (1 downto 0);
+ -- MB_II_CS : out std_logic_vector (1 downto 0);
+ -- MB_II_DM : inout std_logic_vector (8 downto 0);
+ -- MB_II_DQ : inout std_logic_vector (63 downto 0);
+ -- MB_II_DQS : inout std_logic_vector (8 downto 0);
+ -- MB_II_DQS_n : inout std_logic_vector (8 downto 0);
+ -- MB_II_ODT : out std_logic_vector (1 downto 0);
+ -- MB_II_PARITY : out std_logic_vector(0 downto 0);
+ -- MB_II_RAS_A16 : out std_logic;
+ -- MB_II_WE_A14 : out std_logic;
+ -- MB_II_RESET_N : out std_logic_vector(0 downto 0);
+ -- MB_II_ALERT_N : in std_logic_vector(0 downto 0);
-- back transceivers
BCK_SDA : inout std_logic_vector(2 downto 0);
@@ -114,8 +114,8 @@ entity unb2_singlemac is
-- I2C Interface to Sensors
SENS_SC : inout std_logic;
SENS_SD : inout std_logic;
- -- Others
--- CFG_DATA : inout std_logic_vector (3 downto 0);
+ -- Others
+ -- CFG_DATA : inout std_logic_vector (3 downto 0);
VERSION : in std_logic_vector(1 downto 0);
ID : in std_logic_vector(7 downto 0);
TESTIO : inout std_logic_vector(5 downto 0);
@@ -129,15 +129,15 @@ architecture str of unb2_singlemac is
- component system_iopll is
- port (
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X';
- locked : out std_logic;
- outclk_0 : out std_logic; -- outclk0
- outclk_1 : out std_logic; -- outclk1
- outclk_2 : out std_logic -- outclk2
- );
+ component system_iopll is
+ port (
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X';
+ locked : out std_logic;
+ outclk_0 : out std_logic; -- outclk0
+ outclk_1 : out std_logic; -- outclk1
+ outclk_2 : out std_logic -- outclk2
+ );
end component system_iopll;
component tech_transceiver_arria10_1 is
@@ -203,73 +203,73 @@ architecture str of unb2_singlemac is
);
end component ip_arria10_mac_10g;
- -- constants
- constant cs_sim : std_logic := '0';
- constant cs_sync : std_logic := '1';
- --CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
- constant c_block_len : natural := 1118; -- = 8944 user bytes. Including packetizing: 9012 bytes.
-
- -- general reset and clock signals
- signal reset_n : std_logic := '0';
- signal reset_p : std_logic := '0';
- signal pout_wdi : std_logic := '0';
- signal sys_clk : std_logic := '0';
- signal sys_locked : std_logic := '0';
- signal mm_clk : std_logic := '0';
- signal clk_125 : std_logic := '0';
-
-
- -- signals for the transceivers
- signal tx_serial_data_front : std_logic_vector(0 downto 0);
- signal rx_serial_data_front : std_logic_vector(0 downto 0);
- signal xgmii_tx : std_logic_vector(71 downto 0);
- signal xgmii_rx : std_logic_vector(71 downto 0);
- signal clk_156 : std_logic_vector(0 downto 0);
- signal clk_312 : std_logic_vector(0 downto 0);
-
- -- signals for the MAC
- signal mac_10g_loopback_sop : std_logic;
- signal mac_10g_loopback_eop : std_logic;
- signal mac_10g_loopback_valid : std_logic;
- signal mac_10g_loopback_ready : std_logic;
- signal mac_10g_loopback_data : std_logic_vector(63 downto 0);
- signal mac_10g_loopback_empty : std_logic_vector(2 downto 0);
- signal mac_10g_loopback_err : std_logic_vector(5 downto 0);
-
- signal reg_mac_rd : std_logic;
- signal reg_mac_wr : std_logic;
- signal reg_mac_waitrequest : std_logic;
- signal reg_mac_rddata : std_logic_vector(31 downto 0);
- signal reg_mac_wrdata : std_logic_vector(31 downto 0);
- signal reg_mac_address : std_logic_vector(12 downto 0);
-
-
- -- signals for the bidirectional and misc ios
- signal inta_in : std_logic;
- signal intb_in : std_logic;
- signal testio_in : std_logic_vector(5 downto 0);
- signal qsfp_led_in : std_logic_vector(11 downto 0);
- signal bck_err_in : std_logic_vector(2 downto 0);
- signal inta_out : std_logic;
- signal intb_out : std_logic;
- signal testio_out : std_logic_vector(5 downto 0);
- signal qsfp_led_out : std_logic_vector(11 downto 0);
- signal bck_err_out : std_logic_vector(2 downto 0);
- signal ver_id_pmbusalert : std_logic_vector(10 downto 0);
- signal toggle_count : std_logic_vector(31 downto 0);
- signal toggle_count1 : std_logic_vector(31 downto 0);
- signal led_state : std_logic;
+ -- constants
+ constant cs_sim : std_logic := '0';
+ constant cs_sync : std_logic := '1';
+ --CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
+ constant c_block_len : natural := 1118; -- = 8944 user bytes. Including packetizing: 9012 bytes.
+
+ -- general reset and clock signals
+ signal reset_n : std_logic := '0';
+ signal reset_p : std_logic := '0';
+ signal pout_wdi : std_logic := '0';
+ signal sys_clk : std_logic := '0';
+ signal sys_locked : std_logic := '0';
+ signal mm_clk : std_logic := '0';
+ signal clk_125 : std_logic := '0';
+
+
+ -- signals for the transceivers
+ signal tx_serial_data_front : std_logic_vector(0 downto 0);
+ signal rx_serial_data_front : std_logic_vector(0 downto 0);
+ signal xgmii_tx : std_logic_vector(71 downto 0);
+ signal xgmii_rx : std_logic_vector(71 downto 0);
+ signal clk_156 : std_logic_vector(0 downto 0);
+ signal clk_312 : std_logic_vector(0 downto 0);
+
+ -- signals for the MAC
+ signal mac_10g_loopback_sop : std_logic;
+ signal mac_10g_loopback_eop : std_logic;
+ signal mac_10g_loopback_valid : std_logic;
+ signal mac_10g_loopback_ready : std_logic;
+ signal mac_10g_loopback_data : std_logic_vector(63 downto 0);
+ signal mac_10g_loopback_empty : std_logic_vector(2 downto 0);
+ signal mac_10g_loopback_err : std_logic_vector(5 downto 0);
+
+ signal reg_mac_rd : std_logic;
+ signal reg_mac_wr : std_logic;
+ signal reg_mac_waitrequest : std_logic;
+ signal reg_mac_rddata : std_logic_vector(31 downto 0);
+ signal reg_mac_wrdata : std_logic_vector(31 downto 0);
+ signal reg_mac_address : std_logic_vector(12 downto 0);
+
+
+ -- signals for the bidirectional and misc ios
+ signal inta_in : std_logic;
+ signal intb_in : std_logic;
+ signal testio_in : std_logic_vector(5 downto 0);
+ signal qsfp_led_in : std_logic_vector(11 downto 0);
+ signal bck_err_in : std_logic_vector(2 downto 0);
+ signal inta_out : std_logic;
+ signal intb_out : std_logic;
+ signal testio_out : std_logic_vector(5 downto 0);
+ signal qsfp_led_out : std_logic_vector(11 downto 0);
+ signal bck_err_out : std_logic_vector(2 downto 0);
+ signal ver_id_pmbusalert : std_logic_vector(10 downto 0);
+ signal toggle_count : std_logic_vector(31 downto 0);
+ signal toggle_count1 : std_logic_vector(31 downto 0);
+ signal led_state : std_logic;
begin
- WDI <= 'Z';
+ WDI <= 'Z';
--- -- ****** Front side transceivers and MAC ******
---
- QSFP_0_TX <= tx_serial_data_front;
- rx_serial_data_front <= QSFP_0_RX;
+ -- -- ****** Front side transceivers and MAC ******
+ --
+ QSFP_0_TX <= tx_serial_data_front;
+ rx_serial_data_front <= QSFP_0_RX;
- u_transceiver: tech_transceiver_arria10_1
+ u_transceiver: tech_transceiver_arria10_1
generic map (
g_nof_channels => 1
)
@@ -285,144 +285,144 @@ begin
rx_parallel_data => xgmii_rx(63 downto 0),
tx_control => xgmii_tx(71 downto 64),
rx_control => xgmii_rx(71 downto 64)
- );
+ );
u0 : ip_arria10_mac_10g
- port map (
- csr_read => reg_mac_rd,
- csr_write => reg_mac_wr,
- csr_writedata => reg_mac_wrdata(31 downto 0),
- csr_readdata => reg_mac_rddata(31 downto 0),
- csr_waitrequest => reg_mac_waitrequest,
- csr_address => reg_mac_address(12 downto 0),
- tx_312_5_clk => clk_312(0),
- tx_156_25_clk => clk_156(0),
- rx_312_5_clk => clk_312(0),
- rx_156_25_clk => clk_156(0),
- csr_clk => mm_clk,
- csr_rst_n => reset_n,
- tx_rst_n => reset_n,
- rx_rst_n => reset_n,
- avalon_st_tx_startofpacket => mac_10g_loopback_sop,
- avalon_st_tx_endofpacket => mac_10g_loopback_eop,
- avalon_st_tx_valid => mac_10g_loopback_valid,
- avalon_st_tx_data => mac_10g_loopback_data,
- avalon_st_tx_empty => mac_10g_loopback_empty,
- avalon_st_tx_error => mac_10g_loopback_err(0),
- avalon_st_tx_ready => mac_10g_loopback_ready,
- avalon_st_pause_data => (others => '0'),
- xgmii_tx => xgmii_tx,
- avalon_st_txstatus_valid => open,
- avalon_st_txstatus_data => open,
- avalon_st_txstatus_error => open,
- xgmii_rx => xgmii_rx,
- link_fault_status_xgmii_rx_data => open,
- avalon_st_rx_data => mac_10g_loopback_data,
- avalon_st_rx_startofpacket => mac_10g_loopback_sop,
- avalon_st_rx_valid => mac_10g_loopback_valid,
- avalon_st_rx_empty => mac_10g_loopback_empty(2 downto 0),
- avalon_st_rx_error => mac_10g_loopback_err(5 downto 0),
- avalon_st_rx_ready => mac_10g_loopback_ready,
- avalon_st_rx_endofpacket => mac_10g_loopback_eop,
- avalon_st_rxstatus_valid => open,
- avalon_st_rxstatus_data => open,
- avalon_st_rxstatus_error => open
- );
+ port map (
+ csr_read => reg_mac_rd,
+ csr_write => reg_mac_wr,
+ csr_writedata => reg_mac_wrdata(31 downto 0),
+ csr_readdata => reg_mac_rddata(31 downto 0),
+ csr_waitrequest => reg_mac_waitrequest,
+ csr_address => reg_mac_address(12 downto 0),
+ tx_312_5_clk => clk_312(0),
+ tx_156_25_clk => clk_156(0),
+ rx_312_5_clk => clk_312(0),
+ rx_156_25_clk => clk_156(0),
+ csr_clk => mm_clk,
+ csr_rst_n => reset_n,
+ tx_rst_n => reset_n,
+ rx_rst_n => reset_n,
+ avalon_st_tx_startofpacket => mac_10g_loopback_sop,
+ avalon_st_tx_endofpacket => mac_10g_loopback_eop,
+ avalon_st_tx_valid => mac_10g_loopback_valid,
+ avalon_st_tx_data => mac_10g_loopback_data,
+ avalon_st_tx_empty => mac_10g_loopback_empty,
+ avalon_st_tx_error => mac_10g_loopback_err(0),
+ avalon_st_tx_ready => mac_10g_loopback_ready,
+ avalon_st_pause_data => (others => '0'),
+ xgmii_tx => xgmii_tx,
+ avalon_st_txstatus_valid => open,
+ avalon_st_txstatus_data => open,
+ avalon_st_txstatus_error => open,
+ xgmii_rx => xgmii_rx,
+ link_fault_status_xgmii_rx_data => open,
+ avalon_st_rx_data => mac_10g_loopback_data,
+ avalon_st_rx_startofpacket => mac_10g_loopback_sop,
+ avalon_st_rx_valid => mac_10g_loopback_valid,
+ avalon_st_rx_empty => mac_10g_loopback_empty(2 downto 0),
+ avalon_st_rx_error => mac_10g_loopback_err(5 downto 0),
+ avalon_st_rx_ready => mac_10g_loopback_ready,
+ avalon_st_rx_endofpacket => mac_10g_loopback_eop,
+ avalon_st_rxstatus_valid => open,
+ avalon_st_rxstatus_data => open,
+ avalon_st_rxstatus_error => open
+ );
- -- ****** node control for resets and wdi
-
- u_node_ctrl : entity unb_common_lib.unb_node_ctrl
- generic map (
- g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => ETH_clk,
- xo_rst_n => reset_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => open,
- st_clk => clk,
- st_rst => open,
- wdi_in => pout_wdi,
- wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
- pulse_us => open,
- pulse_ms => open,
- pulse_s => open -- could be used to toggle a LED
- );
-
- reset_p <= not reset_n;
-
- u_system_pll : system_iopll
- port map(
- refclk => ETH_CLK,
- rst => reset_p,
- locked => sys_locked,
- outclk_0 => mm_clk, -- 100MHz
- outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
- );
-
-
--- bidirectional and misc
--- use PPS as output enable
-
- INTA <= inta_out when PPS = '1' else 'Z';
- INTB <= intb_out when PPS = '1' else 'Z';
- TESTIO <= testio_out;
- QSFP_LED <= qsfp_led_out;
- BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
-
- inta_in <= INTA;
- intb_in <= INTB;
- testio_in <= TESTIO;
- qsfp_led_in <= QSFP_LED;
- bck_err_in <= BCK_ERR;
-
- inta_out <= intb_in;
- intb_out <= inta_in;
- testio_out(5 downto 3) <= (others => '0');
- testio_out(0) <= CLK;
- testio_out(1) <= mm_clk;
--- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
--- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
- qsfp_led_out(11 downto 6) <= (others => led_state);
- qsfp_led_out(5 downto 0) <= (others => not led_state);
- bck_err_out(2) <= bck_err_in(1);
- bck_err_out(1) <= bck_err_in(0);
- bck_err_out(0) <= bck_err_in(2);
-
-
- ver_id_pmbusalert <= version & id & pmbus_alert;
-
- toggle_led_proc: process(mm_clk, reset_p)
- begin
- if reset_p = '1' then
- toggle_count <= (others => '0');
- led_state <= '0';
- else
- if mm_clk'event and mm_clk = '1' then
- if (toggle_count < 100000000) then
- toggle_count <= toggle_count + 1;
- else
- toggle_count <= (others => '0');
- led_state <= not led_state;
- end if;
- end if;
- end if;
- end process;
+ -- ****** node control for resets and wdi
+
+ u_node_ctrl : entity unb_common_lib.unb_node_ctrl
+ generic map (
+ g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ xo_clk => ETH_clk,
+ xo_rst_n => reset_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => open,
+ st_clk => clk,
+ st_rst => open,
+ wdi_in => pout_wdi,
+ wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ pulse_us => open,
+ pulse_ms => open,
+ pulse_s => open -- could be used to toggle a LED
+ );
+
+ reset_p <= not reset_n;
+
+ u_system_pll : system_iopll
+ port map(
+ refclk => ETH_CLK,
+ rst => reset_p,
+ locked => sys_locked,
+ outclk_0 => mm_clk, -- 100MHz
+ outclk_1 => sys_clk, -- 300MHz
+ outclk_2 => clk_125 -- 125MHz for 1ge
+ );
+
- toggle_led_proc1: process(clk)
- begin
- if clk'event and clk = '1' then
- if (toggle_count1 < 100000000) then
- toggle_count1 <= toggle_count1 + 1;
+ -- bidirectional and misc
+ -- use PPS as output enable
+
+ INTA <= inta_out when PPS = '1' else 'Z';
+ INTB <= intb_out when PPS = '1' else 'Z';
+ TESTIO <= testio_out;
+ QSFP_LED <= qsfp_led_out;
+ BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
+
+ inta_in <= INTA;
+ intb_in <= INTB;
+ testio_in <= TESTIO;
+ qsfp_led_in <= QSFP_LED;
+ bck_err_in <= BCK_ERR;
+
+ inta_out <= intb_in;
+ intb_out <= inta_in;
+ testio_out(5 downto 3) <= (others => '0');
+ testio_out(0) <= CLK;
+ testio_out(1) <= mm_clk;
+ -- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
+ -- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
+ qsfp_led_out(11 downto 6) <= (others => led_state);
+ qsfp_led_out(5 downto 0) <= (others => not led_state);
+ bck_err_out(2) <= bck_err_in(1);
+ bck_err_out(1) <= bck_err_in(0);
+ bck_err_out(0) <= bck_err_in(2);
+
+
+ ver_id_pmbusalert <= version & id & pmbus_alert;
+
+ toggle_led_proc: process(mm_clk, reset_p)
+ begin
+ if reset_p = '1' then
+ toggle_count <= (others => '0');
+ led_state <= '0';
+ else
+ if mm_clk'event and mm_clk = '1' then
+ if (toggle_count < 100000000) then
+ toggle_count <= toggle_count + 1;
else
- toggle_count1 <= (others => '0');
- testio_out(2) <= not testio_out(2);
- pout_wdi <= not pout_wdi;
+ toggle_count <= (others => '0');
+ led_state <= not led_state;
end if;
end if;
- end process;
+ end if;
+ end process;
+
+ toggle_led_proc1: process(clk)
+ begin
+ if clk'event and clk = '1' then
+ if (toggle_count1 < 100000000) then
+ toggle_count1 <= toggle_count1 + 1;
+ else
+ toggle_count1 <= (others => '0');
+ testio_out(2) <= not testio_out(2);
+ pout_wdi <= not pout_wdi;
+ end if;
+ end if;
+ end process;
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
index f036f26b7d..f5fe591e7d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_10GbE is
@@ -31,8 +31,8 @@ end tb_unb2_test_10GbE;
architecture tb of tb_unb2_test_10GbE is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index 0ece6a1e7b..d0bfd88ee1 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_test_10GbE is
@@ -67,20 +67,20 @@ entity unb2_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -112,78 +112,78 @@ architecture str of unb2_test_10GbE is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
index 91c249b522..c768c281d0 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_1GbE is
@@ -33,8 +33,8 @@ end tb_unb2_test_1GbE;
architecture tb of tb_unb2_test_1GbE is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_1GbE"
- );
+ generic map (
+ g_design_name => "unb2_test_1GbE"
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
index 8cd5538d0d..a73ba10bb2 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_test_1GbE is
@@ -75,43 +75,43 @@ architecture str of unb2_test_1GbE is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
index 681063440d..3849f4fdbe 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_all is
@@ -33,9 +33,9 @@ end tb_unb2_test_all;
architecture tb of tb_unb2_test_all is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_all",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_all",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
index 55b937b124..43e594d402 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_all is
@@ -72,17 +72,17 @@ entity unb2_test_all is
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
--- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -123,91 +123,91 @@ architecture str of unb2_test_all is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
index c9175b51bc..4d6726e45d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_I is
@@ -33,9 +33,9 @@ end tb_unb2_test_ddr_MB_I;
architecture tb of tb_unb2_test_ddr_MB_I is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_I",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_I",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
index 1fab918053..cd1f5f4556 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_I is
@@ -83,50 +83,50 @@ architecture str of unb2_test_ddr_MB_I is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
index a9491c8a67..210f1ed1a4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_II is
@@ -33,9 +33,9 @@ end tb_unb2_test_ddr_MB_II;
architecture tb of tb_unb2_test_ddr_MB_II is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
index f0c4966ae1..cc420b149a 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_II is
@@ -83,50 +83,50 @@ architecture str of unb2_test_ddr_MB_II is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
index bc45cff61e..d0b8e572dd 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_I_II is
@@ -33,9 +33,9 @@ end tb_unb2_test_ddr_MB_I_II;
architecture tb of tb_unb2_test_ddr_MB_I_II is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
index 7979e41ada..0939148edc 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_I_II is
@@ -89,56 +89,56 @@ architecture str of unb2_test_ddr_MB_I_II is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 2d556761d4..a28120bffe 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use unb2_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use unb2_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2_test_pkg.all;
@@ -238,16 +238,16 @@ architecture str of mmm_unb2_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -292,109 +292,109 @@ begin
eth1g_eth1_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_SENS")
- port map(mm_rst, mm_clk, reg_fpga_sens_mosi, reg_fpga_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_sens_mosi, reg_fpga_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -419,10 +419,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
@@ -441,397 +441,397 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2_test
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_eth0_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
-
- avs_eth_1_reset_export => eth1g_eth1_mm_rst,
- avs_eth_1_clk_export => OPEN,
- avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
- avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
- avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
- avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
- avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
- avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
- avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
- avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_irq_export => eth1g_eth1_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_sens_reset_export => OPEN,
- reg_fpga_sens_clk_export => OPEN,
- reg_fpga_sens_address_export => reg_fpga_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_sens_write_export => reg_fpga_sens_mosi.wr,
- reg_fpga_sens_writedata_export => reg_fpga_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_sens_read_export => reg_fpga_sens_mosi.rd,
- reg_fpga_sens_readdata_export => reg_fpga_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
- reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
- reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
- reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
- reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
-
- reg_tr_10gbe_back0_reset_export => OPEN,
- reg_tr_10gbe_back0_clk_export => OPEN,
- reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
- reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
- reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
-
- reg_tr_10gbe_back1_reset_export => OPEN,
- reg_tr_10gbe_back1_clk_export => OPEN,
- reg_tr_10gbe_back1_address_export => reg_tr_10GbE_back1_mosi.address(c_reg_tr_10GbE_back1_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_back1_write_export => reg_tr_10GbE_back1_mosi.wr,
- reg_tr_10gbe_back1_writedata_export => reg_tr_10GbE_back1_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back1_read_export => reg_tr_10GbE_back1_mosi.rd,
- reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
-
- reg_eth10g_qsfp_ring_reset_export => OPEN,
- reg_eth10g_qsfp_ring_clk_export => OPEN,
- reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w - 1 downto 0),
- reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
- reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
- reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
-
- reg_eth10g_back0_reset_export => OPEN,
- reg_eth10g_back0_clk_export => OPEN,
- reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w - 1 downto 0),
- reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
- reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
- reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w - 1 downto 0),
-
- reg_eth10g_back1_reset_export => OPEN,
- reg_eth10g_back1_clk_export => OPEN,
- reg_eth10g_back1_address_export => reg_eth10g_back1_mosi.address(c_reg_eth10g_back1_multi_adr_w - 1 downto 0),
- reg_eth10g_back1_write_export => reg_eth10g_back1_mosi.wr,
- reg_eth10g_back1_writedata_export => reg_eth10g_back1_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
- reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
-
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
- reg_bsn_monitor_1gbe_reset_export => OPEN,
- reg_bsn_monitor_1gbe_clk_export => OPEN,
- reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_1gbe_write_export => reg_bsn_monitor_1GbE_mosi.wr,
- reg_bsn_monitor_1gbe_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_1gbe_read_export => reg_bsn_monitor_1GbE_mosi.rd,
- reg_bsn_monitor_1gbe_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_10gbe_reset_export => OPEN,
- reg_bsn_monitor_10gbe_clk_export => OPEN,
- reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
- reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
- reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_1gbe_reset_export => OPEN,
- reg_diag_data_buffer_1gbe_clk_export => OPEN,
- reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_1gbe_write_export => reg_diag_data_buf_1gbe_mosi.wr,
- reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
- reg_diag_data_buffer_1gbe_readdata_export => reg_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_10gbe_reset_export => OPEN,
- reg_diag_data_buffer_10gbe_clk_export => OPEN,
- reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
- reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
- reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_1gbe_clk_export => OPEN,
- ram_diag_data_buffer_1gbe_reset_export => OPEN,
- ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w - 1 downto 0),
- ram_diag_data_buffer_1gbe_write_export => ram_diag_data_buf_1gbe_mosi.wr,
- ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
- ram_diag_data_buffer_1gbe_readdata_export => ram_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_10gbe_clk_export => OPEN,
- ram_diag_data_buffer_10gbe_reset_export => OPEN,
- ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w - 1 downto 0),
- ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
- ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
- ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_1GbE_reset_export => OPEN,
- reg_diag_bg_1GbE_clk_export => OPEN,
- reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
- reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
- reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_10GbE_reset_export => OPEN,
- reg_diag_bg_10GbE_clk_export => OPEN,
- reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
- reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
- reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_bg_1GbE_reset_export => OPEN,
- ram_diag_bg_1GbE_clk_export => OPEN,
- ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w - 1 downto 0),
- ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
- ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
- ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_bg_10GbE_reset_export => OPEN,
- ram_diag_bg_10GbE_clk_export => OPEN,
- ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
- ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
- ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
- ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_I_clk_export => OPEN,
- reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
- reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_I_reset_export => OPEN,
- reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
- reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_II_clk_export => OPEN,
- reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
- reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_II_reset_export => OPEN,
- reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
- reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
- reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
- reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
- reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
- reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
- reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
- reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
- reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
- reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
- ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
- ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
- ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
- ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_eth0_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
+
+ avs_eth_1_reset_export => eth1g_eth1_mm_rst,
+ avs_eth_1_clk_export => OPEN,
+ avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
+ avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
+ avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
+ avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
+ avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
+ avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
+ avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
+ avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_irq_export => eth1g_eth1_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_sens_reset_export => OPEN,
+ reg_fpga_sens_clk_export => OPEN,
+ reg_fpga_sens_address_export => reg_fpga_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_sens_write_export => reg_fpga_sens_mosi.wr,
+ reg_fpga_sens_writedata_export => reg_fpga_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_sens_read_export => reg_fpga_sens_mosi.rd,
+ reg_fpga_sens_readdata_export => reg_fpga_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
+ reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
+ reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
+
+ reg_tr_10gbe_back0_reset_export => OPEN,
+ reg_tr_10gbe_back0_clk_export => OPEN,
+ reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
+ reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
+ reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
+
+ reg_tr_10gbe_back1_reset_export => OPEN,
+ reg_tr_10gbe_back1_clk_export => OPEN,
+ reg_tr_10gbe_back1_address_export => reg_tr_10GbE_back1_mosi.address(c_reg_tr_10GbE_back1_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_back1_write_export => reg_tr_10GbE_back1_mosi.wr,
+ reg_tr_10gbe_back1_writedata_export => reg_tr_10GbE_back1_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back1_read_export => reg_tr_10GbE_back1_mosi.rd,
+ reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
+
+ reg_eth10g_qsfp_ring_reset_export => OPEN,
+ reg_eth10g_qsfp_ring_clk_export => OPEN,
+ reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w - 1 downto 0),
+ reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
+ reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
+ reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_eth10g_back0_reset_export => OPEN,
+ reg_eth10g_back0_clk_export => OPEN,
+ reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w - 1 downto 0),
+ reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
+ reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
+ reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_eth10g_back1_reset_export => OPEN,
+ reg_eth10g_back1_clk_export => OPEN,
+ reg_eth10g_back1_address_export => reg_eth10g_back1_mosi.address(c_reg_eth10g_back1_multi_adr_w - 1 downto 0),
+ reg_eth10g_back1_write_export => reg_eth10g_back1_mosi.wr,
+ reg_eth10g_back1_writedata_export => reg_eth10g_back1_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
+ reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
+
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ reg_bsn_monitor_1gbe_reset_export => OPEN,
+ reg_bsn_monitor_1gbe_clk_export => OPEN,
+ reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_1gbe_write_export => reg_bsn_monitor_1GbE_mosi.wr,
+ reg_bsn_monitor_1gbe_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_1gbe_read_export => reg_bsn_monitor_1GbE_mosi.rd,
+ reg_bsn_monitor_1gbe_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_10gbe_reset_export => OPEN,
+ reg_bsn_monitor_10gbe_clk_export => OPEN,
+ reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
+ reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
+ reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_1gbe_reset_export => OPEN,
+ reg_diag_data_buffer_1gbe_clk_export => OPEN,
+ reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_1gbe_write_export => reg_diag_data_buf_1gbe_mosi.wr,
+ reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
+ reg_diag_data_buffer_1gbe_readdata_export => reg_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_10gbe_reset_export => OPEN,
+ reg_diag_data_buffer_10gbe_clk_export => OPEN,
+ reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
+ reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
+ reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_1gbe_clk_export => OPEN,
+ ram_diag_data_buffer_1gbe_reset_export => OPEN,
+ ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w - 1 downto 0),
+ ram_diag_data_buffer_1gbe_write_export => ram_diag_data_buf_1gbe_mosi.wr,
+ ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
+ ram_diag_data_buffer_1gbe_readdata_export => ram_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_10gbe_clk_export => OPEN,
+ ram_diag_data_buffer_10gbe_reset_export => OPEN,
+ ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w - 1 downto 0),
+ ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
+ ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
+ ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_1GbE_reset_export => OPEN,
+ reg_diag_bg_1GbE_clk_export => OPEN,
+ reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
+ reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
+ reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_10GbE_reset_export => OPEN,
+ reg_diag_bg_10GbE_clk_export => OPEN,
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
+ reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
+ reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_1GbE_reset_export => OPEN,
+ ram_diag_bg_1GbE_clk_export => OPEN,
+ ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w - 1 downto 0),
+ ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
+ ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
+ ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_10GbE_reset_export => OPEN,
+ ram_diag_bg_10GbE_clk_export => OPEN,
+ ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
+ ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
+ ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
+ ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_I_clk_export => OPEN,
+ reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
+ reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_I_reset_export => OPEN,
+ reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
+ reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_II_clk_export => OPEN,
+ reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
+ reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_II_reset_export => OPEN,
+ reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
+ reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index f9f6483e8e..27c4302907 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2_test_pkg is
@@ -29,355 +29,355 @@ package qsys_unb2_test_pkg is
-- $HDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_sens_clk_export : out std_logic; -- export
- reg_fpga_sens_read_export : out std_logic; -- export
- reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_sens_reset_export : out std_logic; -- export
- reg_fpga_sens_write_export : out std_logic; -- export
- reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2_test;
+ component qsys_unb2_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_sens_clk_export : out std_logic; -- export
+ reg_fpga_sens_read_export : out std_logic; -- export
+ reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_sens_reset_export : out std_logic; -- export
+ reg_fpga_sens_write_export : out std_logic; -- export
+ reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2_test;
end qsys_unb2_test_pkg;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
index 0f6da4d454..69ff66b3ce 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2_test_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2_test_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity udp_stream is
generic (
@@ -105,14 +105,28 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC(
+ g_bg_block_size,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ g_bg_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ g_bg_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ g_bg_block_size-1,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
constant c_nof_crc_words : natural := 1;
@@ -157,54 +171,54 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl,
- g_use_tx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_use_tx_seq => true
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
@@ -212,74 +226,74 @@ begin
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
@@ -304,54 +318,54 @@ begin
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index ce367aa640..90eefef7be 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2_test_pkg.all;
entity unb2_test is
generic (
@@ -318,10 +318,10 @@ architecture str of unb2_test is
signal i_QSFP_TX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -354,13 +354,13 @@ architecture str of unb2_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -438,383 +438,383 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- --g_tse_clk_buf => TRUE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ --g_tse_clk_buf => TRUE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2_board_nof_eth,
- g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_sens_miso => reg_fpga_temp_sens_miso, -- FIXME:
- --reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- --reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- --reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- --reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_sens_miso => reg_fpga_temp_sens_miso, -- FIXME:
+ --reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ --reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ --reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ --reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
@@ -834,81 +834,81 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
-
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -930,165 +930,165 @@ begin
u_front_io : entity unb2_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
-
--- u_tr_10GbE_back: ENTITY unb2_board_10gbe_lib.unb2_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+
+ -- u_tr_10GbE_back: ENTITY unb2_board_10gbe_lib.unb2_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
--green_led_arr => qsfp_green_led_arr(2-1 DOWNTO 0),
--red_led_arr => qsfp_red_led_arr(2-1 DOWNTO 0)
- );
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
@@ -1101,156 +1101,156 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
index 19dc929de3..cce87fb1fb 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2_test_pkg is
@@ -31,27 +31,27 @@ package unb2_test_pkg is
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index 2893054f64..7113ba43f4 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2_test is
generic (
@@ -187,143 +187,143 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2_test : entity work.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- QSFP_0_TX => si_lpbk_0,
- QSFP_0_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_1,
- QSFP_1_RX => si_lpbk_1,
- QSFP_2_TX => si_lpbk_2,
- QSFP_2_RX => si_lpbk_2,
- QSFP_3_TX => si_lpbk_3,
- QSFP_3_RX => si_lpbk_3,
- QSFP_4_TX => si_lpbk_4,
- QSFP_4_RX => si_lpbk_4,
- QSFP_5_TX => si_lpbk_5,
- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ QSFP_0_TX => si_lpbk_0,
+ QSFP_0_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_1,
+ QSFP_1_RX => si_lpbk_1,
+ QSFP_2_TX => si_lpbk_2,
+ QSFP_2_RX => si_lpbk_2,
+ QSFP_3_TX => si_lpbk_3,
+ QSFP_3_RX => si_lpbk_3,
+ QSFP_4_TX => si_lpbk_4,
+ QSFP_4_RX => si_lpbk_4,
+ QSFP_5_TX => si_lpbk_5,
+ QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index b90b45a0f5..7dab9af04a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2_board is
generic (
@@ -319,15 +319,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -336,15 +336,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
@@ -353,26 +353,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk
@@ -383,46 +383,46 @@ begin
dp_clk <= i_ext_clk200;
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
end generate;
gen_dp_clk_hardware: if g_sim = false generate
gen_pll: if g_dp_clk_use_pll = true generate
u_unb2_board_clk200_pll : entity work.unb2_board_clk200_pll
- generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
- )
- port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => dp_rst
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => dp_rst
+ );
end generate;
no_pll: if g_dp_clk_use_pll = false generate
dp_clk <= i_ext_clk200;
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
end generate;
end generate;
@@ -440,48 +440,48 @@ begin
clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity work.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
@@ -490,33 +490,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2_board_system_info : entity work.mms_unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
@@ -554,12 +554,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
@@ -571,15 +571,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2_board_wdi_reg : entity work.unb2_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
@@ -589,73 +589,73 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
@@ -665,69 +665,69 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms; -- speed up in simulation
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_mm_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_mm_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2_board_pmbus : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_pmbus => true,
- g_clk_freq => 8 * 10**6 -- I2C bus run at ~300kHz @ mm_clk=50MHz
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_pmbus => true,
+ g_clk_freq => 8 * 10**6 -- I2C bus run at ~300kHz @ mm_clk=50MHz
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2_fpga_sens : entity work.mms_unb2_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
@@ -737,18 +737,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
@@ -775,43 +775,43 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
index 088f538a7a..49102655d0 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2_board_sens is
@@ -69,47 +69,47 @@ architecture str of mms_unb2_board_sens is
begin
u_unb2_board_sens_reg : entity work.unb2_board_sens_reg
- generic map (
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
-
- -- Max temp threshold
- temp_high => temp_high
- );
+ generic map (
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
+
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2_board_sens : entity work.unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_pmbus => g_pmbus,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => c_sens_nof_result
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_pmbus => g_pmbus,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => c_sens_nof_result
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index 75ff5e6a7c..d4f6ede587 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2_board_system_info;
@@ -70,72 +70,74 @@ architecture str of mms_unb2_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0'
+ );
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2_board_system_info: entity work.unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2_board_system_info_reg: entity work.unb2_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index e619ec2ef2..4b3d863e8c 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2_fpga_sens.vhd
library IEEE, technology_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_fpga_sens is
@@ -67,51 +67,51 @@ architecture str of mms_unb2_fpga_sens is
begin
u_unb2_fpga_sens_reg : entity work.unb2_fpga_sens_reg
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start => mm_start,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_temp_in => reg_temp_mosi,
- sla_temp_out => reg_temp_miso,
- sla_voltage_in => reg_voltage_mosi,
- sla_voltage_out => reg_voltage_miso,
-
- -- MM registers
- --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- --sens_data => sens_data,
-
- -- Max temp threshold
- temp_high => temp_high
- );
-
--- u_unb2_board_sens : ENTITY work.unb2_board_sens
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_clk_freq => g_clk_freq,
--- g_temp_high => g_temp_high,
--- g_sens_nof_result => c_sens_nof_result
--- )
--- PORT MAP (
--- clk => mm_clk,
--- rst => mm_rst,
--- start => mm_start,
--- -- i2c bus
--- scl => scl,
--- sda => sda,
--- -- read results
--- sens_evt => OPEN,
--- sens_err => sens_err,
--- sens_data => sens_data
--- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start => mm_start,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_temp_in => reg_temp_mosi,
+ sla_temp_out => reg_temp_miso,
+ sla_voltage_in => reg_voltage_mosi,
+ sla_voltage_out => reg_voltage_miso,
+
+ -- MM registers
+ --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ --sens_data => sens_data,
+
+ -- Max temp threshold
+ temp_high => temp_high
+ );
+
+ -- u_unb2_board_sens : ENTITY work.unb2_board_sens
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_clk_freq => g_clk_freq,
+ -- g_temp_high => g_temp_high,
+ -- g_sens_nof_result => c_sens_nof_result
+ -- )
+ -- PORT MAP (
+ -- clk => mm_clk,
+ -- rst => mm_rst,
+ -- start => mm_start,
+ -- -- i2c bus
+ -- scl => scl,
+ -- sda => sda,
+ -- -- read results
+ -- sens_evt => OPEN,
+ -- sens_err => sens_err,
+ -- sens_data => sens_data
+ -- );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
index a0060fe1cb..7bd6fed35f 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_back_io is
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
index bf66c9ae6a..9c7c2ec1c4 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
-- Description:
@@ -64,47 +64,47 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
index 6bedd749d7..ac18a564ff 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -140,83 +140,83 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
index eef6905655..6b8f6093af 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -54,16 +54,16 @@ architecture arria10 of unb2_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
index 9d4d3c1bd3..769f2630a6 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -59,28 +59,28 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
index 2bbb9e4613..fdf61eff24 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_front_io is
@@ -69,8 +69,8 @@ begin
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
index 32c9cd53ff..fd68d6ee22 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
-- Description:
@@ -71,44 +71,44 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2_board_wdi_extend : entity work.unb2_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index 24ed076f79..c8028d0ebc 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2_board_peripherals_pkg is
@@ -76,10 +76,10 @@ package unb2_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index 00bdd220d7..fd36a9f6fc 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
@@ -139,23 +139,25 @@ package unb2_board_pkg is
type t_c_unb2_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
+ function func_unb2_board_system_info (
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
end unb2_board_pkg;
package body unb2_board_pkg is
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
+ function func_unb2_board_system_info (
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
variable v_system_info : t_c_unb2_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index 4baacf00df..ae7f3f6813 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_pmbus_ctrl is
@@ -75,40 +75,52 @@ architecture rtl of unb2_board_pmbus_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
--- SMBUS_READ_BYTE , LOC_POWER_CORE, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_TEMP,
+ -- SMBUS_READ_BYTE , LOC_POWER_CORE, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_TEMP,
--SMBUS_READ_BYTE , LOC_POWER_ERAM, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_TEMP,
---
- SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
- SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
- SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
- SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_TEMP,
+ --
+ SMBUS_READ_BYTE ,
+ LOC_POWER_TR_R,
+ LP_VOUT_MODE,
+ SMBUS_READ_BYTE ,
+ LOC_POWER_TR_R,
+ LP_VOUT_MODE,
+ SMBUS_READ_BYTE ,
+ LOC_POWER_TR_R,
+ LP_VOUT_MODE,
+ SMBUS_READ_BYTE ,
+ LOC_POWER_TR_R,
+ LP_VOUT_MODE,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_VOUT,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_IOUT,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_TR_T, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_BAT, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_IO, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_TEMP,
-
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_TR_T, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_TEMP,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_BAT, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_TEMP,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_IO, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_TEMP,
+
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
index 80e8ae543f..e654c43ac5 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
-- Description:
@@ -111,43 +111,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -166,20 +166,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
index fba74d7787..9f5f981f00 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_ring_io is
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
index 22bb96c97f..e0c2696ce9 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
entity unb2_board_sens is
@@ -53,7 +53,7 @@ architecture str of unb2_board_sens is
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
@@ -69,70 +69,70 @@ begin
gen_unb2_board_sens_ctrl : if g_pmbus = false generate
u_unb2_board_sens_ctrl : entity work.unb2_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_pmbus_ctrl : if g_pmbus = true generate
u_unb2_board_pmbus_ctrl : entity work.unb2_board_pmbus_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
end architecture;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 409b1bde30..542ec5ea7e 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_sens_ctrl is
@@ -64,12 +64,24 @@ architecture rtl of unb2_board_sens_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
-
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_READ_BYTE ,
+ ETH_MAX1617_ADR,
+ MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE ,
+ ETH_MAX1617_ADR,
+ MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE ,
+ ETH_MAX1617_ADR,
+ MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE ,
+ ETH_MAX1617_ADR,
+ MAX1617_CMD_READ_REMOTE_TEMP,
+
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
index 1ff3381d0d..0b886f7070 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_sens_reg is
generic (
@@ -94,13 +94,15 @@ architecture rtl of unb2_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
-
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ -- +1 to fit sens_err in the last address
+
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0'
+ );
signal i_temp_high : std_logic_vector(6 downto 0);
@@ -134,11 +136,11 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
-- Read access: get register value
@@ -154,7 +156,7 @@ begin
else
sla_out.rddata(6 downto 0) <= i_temp_high;
end if;
- -- else unused addresses read zero
+ -- else unused addresses read zero
end if;
end if;
end process;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
index 3ef429a1f9..d7ad980739 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
index 138a1de924..47d5de686b 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2_board_system_info_reg;
@@ -81,11 +81,13 @@ architecture rtl of unb2_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0'
+ );
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
index d474968663..dac90aed3e 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -72,27 +72,27 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
index 365e280976..67005e4aa5 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_wdi_reg is
port (
@@ -40,18 +40,20 @@ entity unb2_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2_board_wdi_reg;
architecture rtl of unb2_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0'
+ );
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -64,7 +66,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
index c8474454b2..86c6e335a0 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -23,11 +23,11 @@
--
library IEEE, common_lib, technology_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_fpga_sens_reg is
@@ -62,28 +62,28 @@ end unb2_fpga_sens_reg;
architecture str of unb2_fpga_sens_reg is
- --SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
+--SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
temp_high <= (others => '0'); -- i_temp_high;
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- start_sense => start,
-
- reg_temp_mosi => sla_temp_in,
- reg_temp_miso => sla_temp_out,
-
- reg_voltage_store_mosi => sla_voltage_in,
- reg_voltage_store_miso => sla_voltage_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ start_sense => start,
+
+ reg_temp_mosi => sla_temp_in,
+ reg_temp_miso => sla_temp_out,
+
+ reg_voltage_store_mosi => sla_voltage_in,
+ reg_voltage_store_miso => sla_voltage_out
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index a8f6688098..3160e7b98d 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -32,11 +32,11 @@ entity tb_mms_unb2_board_sens is
end tb_mms_unb2_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
@@ -153,60 +153,60 @@ begin
-- I2C sensors master
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => c_sim,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index 3e7d5fa1b9..504a012a6d 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk125_pll is
@@ -57,15 +57,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index 01c62f46e1..727a80bf1d 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk200_pll is
@@ -72,45 +72,45 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b460c275ce..927b5c353b 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk25_pll is
@@ -57,15 +57,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 35e015a38b..d601882160 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_node_ctrl is
@@ -76,24 +76,24 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 86668b2331..0b8a946bc8 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -37,10 +37,10 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2_board_qsfp_leds is
end tb_unb2_board_qsfp_leds;
@@ -142,49 +142,49 @@ begin
end process;
u_unb2_factory_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2_user_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 0fe7b9e242..f9395bd347 100644
--- a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_10gbe is
@@ -78,17 +78,17 @@ architecture str of unb2_board_10gbe is
begin
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
index ff6593f3fe..d152b04031 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
@@ -1,4 +1,4 @@
- component ddr4_micron46_mbIIskew is
+ component ddr4_micron46_mbIIskew is
port (
amm_ready_0 : out std_logic; -- waitrequest_n
amm_read_0 : in std_logic := 'X'; -- read
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
index 6f46a0519f..40067ba354 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
@@ -1,4 +1,4 @@
- component ddr4_micron46_mbIskew is
+ component ddr4_micron46_mbIskew is
port (
amm_ready_0 : out std_logic; -- waitrequest_n
amm_read_0 : in std_logic := 'X'; -- read
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index 0d95ca2ee8..66620d36d2 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2a_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2a_heater_pkg.all;
entity mmm_unb2a_heater is
@@ -120,35 +120,35 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -165,153 +165,153 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2a_heater
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_heater_reset_export => OPEN,
- reg_heater_clk_export => OPEN,
- reg_heater_address_export => reg_heater_mosi.address(4 downto 0),
- reg_heater_read_export => reg_heater_mosi.rd,
- reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
- reg_heater_write_export => reg_heater_mosi.wr,
- reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_heater_reset_export => OPEN,
+ reg_heater_clk_export => OPEN,
+ reg_heater_address_export => reg_heater_mosi.address(4 downto 0),
+ reg_heater_read_export => reg_heater_mosi.rd,
+ reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
+ reg_heater_write_export => reg_heater_mosi.wr,
+ reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
index 7229f0b80c..0ebecfcc5a 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
@@ -20,144 +20,144 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v15.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v15.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb2a_heater is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_reset_export : out std_logic -- export
- );
- end component qsys_unb2a_heater;
+ component qsys_unb2a_heater is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2a_heater;
end qsys_unb2a_heater_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
index 1d6e8e0086..747e5d6c1e 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2a_heater is
generic (
@@ -165,242 +165,242 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_tse_clk_buf => false, -- TRUE,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_tse_clk_buf => false, -- TRUE,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
- g_nof_mac4 => 736 -- 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
+ g_nof_mac4 => 736 -- 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
index 5618e365de..5dc5d0b127 100644
--- a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2a_heater is
- generic (
- g_design_name : string := "unb2a_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_heater;
architecture tb of tb_unb2a_heater is
@@ -184,37 +184,37 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
index a175b4e2e2..86dffd84c6 100644
--- a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
entity unb2a_led is
generic (
@@ -102,15 +102,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- mm_clk
@@ -121,40 +121,40 @@ begin
i_mm_clk <= clk50;
gen_mm_clk_sim: if g_sim = true generate
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- mm_locked <= '0', '1' after 70 ns;
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2a_board_clk125_pll : entity unb2a_board_lib.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2a_board_node_ctrl : entity unb2a_board_lib.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2a_board_node_ctrl : entity unb2a_board_lib.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
------------------------------------------------------------------------------
-- Toggle red LED when unb2a_minimal is running, green LED for other designs.
@@ -164,15 +164,15 @@ begin
u_extend : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- p_in => mm_pulse_s,
- ep_out => led_flash
- );
+ generic map (
+ g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ p_in => mm_pulse_s,
+ ep_out => led_flash
+ );
@@ -186,36 +186,36 @@ begin
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- p_in => pulse_10Hz,
- ep_out => pulse_10Hz_extended
- );
+ generic map (
+ g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ p_in => pulse_10Hz,
+ ep_out => pulse_10Hz_extended
+ );
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
QSFP_LED(6) <= led_toggle;
diff --git a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
index ae2986db69..22e5697031 100644
--- a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
@@ -39,18 +39,18 @@
--
library IEEE, common_lib, unb2a_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2a_led is
- generic (
- g_design_name : string := "unb2a_led";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_led";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_led;
architecture tb of tb_unb2a_led is
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 9508f28879..d0228ca492 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2a_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2a_minimal_pkg.all;
entity mmm_unb2a_minimal is
@@ -116,32 +116,32 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -158,145 +158,145 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2a_minimal
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
index 5d8ec0f7e9..567a232ec0 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
@@ -20,137 +20,137 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb2a_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2a_minimal;
+ component qsys_unb2a_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2a_minimal;
end qsys_unb2a_minimal_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
index f9fd13d39a..f966a04c90 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
entity unb2a_minimal is
generic (
@@ -160,219 +160,219 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
index 229e507f6a..d018d459c3 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2a_minimal is
- generic (
- g_design_name : string := "unb2a_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_minimal;
architecture tb of tb_unb2a_minimal is
@@ -188,51 +188,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
index d810f5c1e5..03a96ab7f6 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_10GbE is
@@ -31,8 +31,8 @@ end tb_unb2a_test_10GbE;
architecture tb of tb_unb2a_test_10GbE is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2a_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
index e287fb3c66..1963b65480 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2a_test_10GbE is
@@ -67,20 +67,20 @@ entity unb2a_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -112,78 +112,78 @@ architecture str of unb2a_test_10GbE is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
index 4235e78702..058dcc891a 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_1GbE is
@@ -33,8 +33,8 @@ end tb_unb2a_test_1GbE;
architecture tb of tb_unb2a_test_1GbE is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_1GbE"
- );
+ generic map (
+ g_design_name => "unb2a_test_1GbE"
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
index d397d48345..69ac9a37c2 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2a_test_1GbE is
@@ -75,43 +75,43 @@ architecture str of unb2a_test_1GbE is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
index fe6292e768..43677dd462 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_all is
@@ -33,9 +33,9 @@ end tb_unb2a_test_all;
architecture tb of tb_unb2a_test_all is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_all",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_all",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
index 2243b164a7..8a14e60565 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_all is
@@ -72,17 +72,17 @@ entity unb2a_test_all is
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
--- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -123,91 +123,91 @@ architecture str of unb2a_test_all is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
index c4f4c2fc74..9882804d0d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_I is
@@ -33,9 +33,9 @@ end tb_unb2a_test_ddr_MB_I;
architecture tb of tb_unb2a_test_ddr_MB_I is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_I",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_I",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
index a510857612..8b0de74f90 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_I is
@@ -83,50 +83,50 @@ architecture str of unb2a_test_ddr_MB_I is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
index 94c31dfa59..cf7cb947ff 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_II is
@@ -33,9 +33,9 @@ end tb_unb2a_test_ddr_MB_II;
architecture tb of tb_unb2a_test_ddr_MB_II is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
index 96168f2b76..7cd258eab1 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_II is
@@ -83,50 +83,50 @@ architecture str of unb2a_test_ddr_MB_II is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
index 3502dfe0dd..413ee22088 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_I_II is
@@ -33,9 +33,9 @@ end tb_unb2a_test_ddr_MB_I_II;
architecture tb of tb_unb2a_test_ddr_MB_I_II is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
index 4f5fd33af0..f22fb8191f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_I_II is
@@ -89,56 +89,56 @@ architecture str of unb2a_test_ddr_MB_I_II is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 2008c4a831..1330d6e751 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2a_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2a_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2a_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2a_test_pkg.all;
@@ -241,16 +241,16 @@ architecture str of mmm_unb2a_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -295,115 +295,115 @@ begin
eth1g_eth1_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
u_mm_file_reg_10gbase_r_24 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_10GBASE_R_24")
- port map(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
+ port map(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -428,10 +428,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
@@ -450,415 +450,415 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2a_test
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_eth0_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
-
- avs_eth_1_reset_export => eth1g_eth1_mm_rst,
- avs_eth_1_clk_export => OPEN,
- avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
- avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
- avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
- avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
- avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
- avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
- avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
- avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_irq_export => eth1g_eth1_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_10gbase_r_24_reset_export => OPEN,
- reg_10gbase_r_24_clk_export => OPEN,
- reg_10gbase_r_24_address_export => reg_10gbase_r_24_mosi.address(14 downto 0),
- reg_10gbase_r_24_write_export => reg_10gbase_r_24_mosi.wr,
- reg_10gbase_r_24_writedata_export => reg_10gbase_r_24_mosi.wrdata(c_word_w - 1 downto 0),
- reg_10gbase_r_24_read_export => reg_10gbase_r_24_mosi.rd,
- reg_10gbase_r_24_readdata_export => reg_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0),
- reg_10gbase_r_24_waitrequest_export => reg_10gbase_r_24_miso.waitrequest,
-
-
- reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
- reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
- reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
- reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
- reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
-
- reg_tr_10gbe_back0_reset_export => OPEN,
- reg_tr_10gbe_back0_clk_export => OPEN,
- reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
- reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
- reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
-
- reg_tr_10gbe_back1_reset_export => OPEN,
- reg_tr_10gbe_back1_clk_export => OPEN,
- reg_tr_10gbe_back1_address_export => reg_tr_10GbE_back1_mosi.address(c_reg_tr_10GbE_back1_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_back1_write_export => reg_tr_10GbE_back1_mosi.wr,
- reg_tr_10gbe_back1_writedata_export => reg_tr_10GbE_back1_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back1_read_export => reg_tr_10GbE_back1_mosi.rd,
- reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
-
- reg_eth10g_qsfp_ring_reset_export => OPEN,
- reg_eth10g_qsfp_ring_clk_export => OPEN,
- reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w - 1 downto 0),
- reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
- reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
- reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
-
- reg_eth10g_back0_reset_export => OPEN,
- reg_eth10g_back0_clk_export => OPEN,
- reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w - 1 downto 0),
- reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
- reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
- reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w - 1 downto 0),
-
- reg_eth10g_back1_reset_export => OPEN,
- reg_eth10g_back1_clk_export => OPEN,
- reg_eth10g_back1_address_export => reg_eth10g_back1_mosi.address(c_reg_eth10g_back1_multi_adr_w - 1 downto 0),
- reg_eth10g_back1_write_export => reg_eth10g_back1_mosi.wr,
- reg_eth10g_back1_writedata_export => reg_eth10g_back1_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
- reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
-
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
- reg_bsn_monitor_1gbe_reset_export => OPEN,
- reg_bsn_monitor_1gbe_clk_export => OPEN,
- reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_1gbe_write_export => reg_bsn_monitor_1GbE_mosi.wr,
- reg_bsn_monitor_1gbe_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_1gbe_read_export => reg_bsn_monitor_1GbE_mosi.rd,
- reg_bsn_monitor_1gbe_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_10gbe_reset_export => OPEN,
- reg_bsn_monitor_10gbe_clk_export => OPEN,
- reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
- reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
- reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_1gbe_reset_export => OPEN,
- reg_diag_data_buffer_1gbe_clk_export => OPEN,
- reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_1gbe_write_export => reg_diag_data_buf_1gbe_mosi.wr,
- reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
- reg_diag_data_buffer_1gbe_readdata_export => reg_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_10gbe_reset_export => OPEN,
- reg_diag_data_buffer_10gbe_clk_export => OPEN,
- reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(5 downto 0),
- reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
- reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
- reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_1gbe_clk_export => OPEN,
- ram_diag_data_buffer_1gbe_reset_export => OPEN,
- ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w - 1 downto 0),
- ram_diag_data_buffer_1gbe_write_export => ram_diag_data_buf_1gbe_mosi.wr,
- ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
- ram_diag_data_buffer_1gbe_readdata_export => ram_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_10gbe_clk_export => OPEN,
- ram_diag_data_buffer_10gbe_reset_export => OPEN,
- ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w - 1 downto 0),
- ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
- ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
- ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_1GbE_reset_export => OPEN,
- reg_diag_bg_1GbE_clk_export => OPEN,
- reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
- reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
- reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_10GbE_reset_export => OPEN,
- reg_diag_bg_10GbE_clk_export => OPEN,
- reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
- reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
- reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_bg_1GbE_reset_export => OPEN,
- ram_diag_bg_1GbE_clk_export => OPEN,
- ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w - 1 downto 0),
- ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
- ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
- ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_bg_10GbE_reset_export => OPEN,
- ram_diag_bg_10GbE_clk_export => OPEN,
- ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
- ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
- ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
- ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_I_clk_export => OPEN,
- reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
- reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_I_reset_export => OPEN,
- reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
- reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_II_clk_export => OPEN,
- reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
- reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_II_reset_export => OPEN,
- reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
- reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
- reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
- reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
- reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
- reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
- reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
- reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
- reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
- reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
- ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
- ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
- ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
- ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_eth0_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
+
+ avs_eth_1_reset_export => eth1g_eth1_mm_rst,
+ avs_eth_1_clk_export => OPEN,
+ avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
+ avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
+ avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
+ avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
+ avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
+ avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
+ avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
+ avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_irq_export => eth1g_eth1_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_10gbase_r_24_reset_export => OPEN,
+ reg_10gbase_r_24_clk_export => OPEN,
+ reg_10gbase_r_24_address_export => reg_10gbase_r_24_mosi.address(14 downto 0),
+ reg_10gbase_r_24_write_export => reg_10gbase_r_24_mosi.wr,
+ reg_10gbase_r_24_writedata_export => reg_10gbase_r_24_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_10gbase_r_24_read_export => reg_10gbase_r_24_mosi.rd,
+ reg_10gbase_r_24_readdata_export => reg_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0),
+ reg_10gbase_r_24_waitrequest_export => reg_10gbase_r_24_miso.waitrequest,
+
+
+ reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
+ reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
+ reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
+
+ reg_tr_10gbe_back0_reset_export => OPEN,
+ reg_tr_10gbe_back0_clk_export => OPEN,
+ reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
+ reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
+ reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
+
+ reg_tr_10gbe_back1_reset_export => OPEN,
+ reg_tr_10gbe_back1_clk_export => OPEN,
+ reg_tr_10gbe_back1_address_export => reg_tr_10GbE_back1_mosi.address(c_reg_tr_10GbE_back1_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_back1_write_export => reg_tr_10GbE_back1_mosi.wr,
+ reg_tr_10gbe_back1_writedata_export => reg_tr_10GbE_back1_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back1_read_export => reg_tr_10GbE_back1_mosi.rd,
+ reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
+
+ reg_eth10g_qsfp_ring_reset_export => OPEN,
+ reg_eth10g_qsfp_ring_clk_export => OPEN,
+ reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w - 1 downto 0),
+ reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
+ reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
+ reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_eth10g_back0_reset_export => OPEN,
+ reg_eth10g_back0_clk_export => OPEN,
+ reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w - 1 downto 0),
+ reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
+ reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
+ reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_eth10g_back1_reset_export => OPEN,
+ reg_eth10g_back1_clk_export => OPEN,
+ reg_eth10g_back1_address_export => reg_eth10g_back1_mosi.address(c_reg_eth10g_back1_multi_adr_w - 1 downto 0),
+ reg_eth10g_back1_write_export => reg_eth10g_back1_mosi.wr,
+ reg_eth10g_back1_writedata_export => reg_eth10g_back1_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
+ reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
+
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ reg_bsn_monitor_1gbe_reset_export => OPEN,
+ reg_bsn_monitor_1gbe_clk_export => OPEN,
+ reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_1gbe_write_export => reg_bsn_monitor_1GbE_mosi.wr,
+ reg_bsn_monitor_1gbe_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_1gbe_read_export => reg_bsn_monitor_1GbE_mosi.rd,
+ reg_bsn_monitor_1gbe_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_10gbe_reset_export => OPEN,
+ reg_bsn_monitor_10gbe_clk_export => OPEN,
+ reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
+ reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
+ reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_1gbe_reset_export => OPEN,
+ reg_diag_data_buffer_1gbe_clk_export => OPEN,
+ reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_1gbe_write_export => reg_diag_data_buf_1gbe_mosi.wr,
+ reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
+ reg_diag_data_buffer_1gbe_readdata_export => reg_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_10gbe_reset_export => OPEN,
+ reg_diag_data_buffer_10gbe_clk_export => OPEN,
+ reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(5 downto 0),
+ reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
+ reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
+ reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_1gbe_clk_export => OPEN,
+ ram_diag_data_buffer_1gbe_reset_export => OPEN,
+ ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w - 1 downto 0),
+ ram_diag_data_buffer_1gbe_write_export => ram_diag_data_buf_1gbe_mosi.wr,
+ ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
+ ram_diag_data_buffer_1gbe_readdata_export => ram_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_10gbe_clk_export => OPEN,
+ ram_diag_data_buffer_10gbe_reset_export => OPEN,
+ ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w - 1 downto 0),
+ ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
+ ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
+ ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_1GbE_reset_export => OPEN,
+ reg_diag_bg_1GbE_clk_export => OPEN,
+ reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
+ reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
+ reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_10GbE_reset_export => OPEN,
+ reg_diag_bg_10GbE_clk_export => OPEN,
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
+ reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
+ reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_1GbE_reset_export => OPEN,
+ ram_diag_bg_1GbE_clk_export => OPEN,
+ ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w - 1 downto 0),
+ ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
+ ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
+ ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_10GbE_reset_export => OPEN,
+ ram_diag_bg_10GbE_clk_export => OPEN,
+ ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
+ ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
+ ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
+ ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_I_clk_export => OPEN,
+ reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
+ reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_I_reset_export => OPEN,
+ reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
+ reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_II_clk_export => OPEN,
+ reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
+ reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_II_reset_export => OPEN,
+ reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
+ reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index 3722b4a589..1b6a111e56 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_test_pkg is
@@ -29,370 +29,370 @@ package qsys_unb2a_test_pkg is
-- $HDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2a_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
- reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
- reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
- reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
- reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
- reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
- reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
- reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
- reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
- reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
- reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
- reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
- reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
- reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
- reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0); -- reg_10gbase_r_24_address.export
- reg_10gbase_r_24_clk_export : out std_logic; -- reg_10gbase_r_24_clk.export
- reg_10gbase_r_24_read_export : out std_logic; -- reg_10gbase_r_24_read.export
- reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_10gbase_r_24_readdata.export
- reg_10gbase_r_24_reset_export : out std_logic; -- reg_10gbase_r_24_reset.export
- reg_10gbase_r_24_waitrequest_export : in std_logic := '0'; -- reg_10gbase_r_24_waitrequest.export
- reg_10gbase_r_24_write_export : out std_logic; -- reg_10gbase_r_24_write.export
- reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0); -- reg_10gbase_r_24_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
- reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
- reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
- reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
- reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
- );
- end component qsys_unb2a_test;
+ component qsys_unb2a_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
+ avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
+ avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
+ avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
+ avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
+ avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
+ avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
+ avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
+ avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
+ avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
+ avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
+ avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
+ avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
+ avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
+ avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
+ avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
+ avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
+ avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
+ clk_clk : in std_logic := '0'; -- clk.clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
+ pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
+ pio_pps_read_export : out std_logic; -- pio_pps_read.export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
+ pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
+ pio_pps_write_export : out std_logic; -- pio_pps_write.export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
+ pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
+ pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
+ pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
+ pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
+ pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
+ reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
+ reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
+ reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
+ reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
+ reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
+ reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
+ reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
+ reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
+ reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
+ reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
+ reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
+ reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
+ reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
+ reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
+ reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
+ reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
+ reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
+ reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
+ reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
+ reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
+ reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0); -- reg_10gbase_r_24_address.export
+ reg_10gbase_r_24_clk_export : out std_logic; -- reg_10gbase_r_24_clk.export
+ reg_10gbase_r_24_read_export : out std_logic; -- reg_10gbase_r_24_read.export
+ reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_10gbase_r_24_readdata.export
+ reg_10gbase_r_24_reset_export : out std_logic; -- reg_10gbase_r_24_reset.export
+ reg_10gbase_r_24_waitrequest_export : in std_logic := '0'; -- reg_10gbase_r_24_waitrequest.export
+ reg_10gbase_r_24_write_export : out std_logic; -- reg_10gbase_r_24_write.export
+ reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0); -- reg_10gbase_r_24_writedata.export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
+ reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
+ reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
+ reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
+ reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
+ reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
+ reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
+ reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
+ reg_remu_read_export : out std_logic; -- reg_remu_read.export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
+ reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
+ reg_remu_write_export : out std_logic; -- reg_remu_write.export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
+ reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
+ reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
+ reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
+ reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
+ reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
+ reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
+ reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
+ reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
+ reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
+ reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
+ reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
+ reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
+ reset_reset_n : in std_logic := '0'; -- reset.reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
+ rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
+ rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
+ rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
+ rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
+ );
+ end component qsys_unb2a_test;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
index 6c98ef16b9..5579e4e815 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2a_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2a_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2a_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -105,14 +105,28 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC(
+ g_bg_block_size,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ g_bg_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ g_bg_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ g_bg_block_size-1,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
constant c_nof_crc_words : natural := 1;
@@ -157,54 +171,54 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
@@ -212,74 +226,74 @@ begin
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
@@ -304,55 +318,55 @@ begin
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index 956661fc96..fc51f1a668 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2a_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2a_test_pkg.all;
entity unb2a_test is
generic (
@@ -320,10 +320,10 @@ architecture str of unb2a_test is
signal i_QSFP_TX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -359,13 +359,13 @@ architecture str of unb2a_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -444,384 +444,384 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2_board_nof_eth,
- g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
@@ -841,92 +841,92 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2a_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -948,163 +948,163 @@ begin
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2a_board_lib.unb2_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
-
--- u_tr_10GbE_back: ENTITY unb2a_board_10gbe_lib.unb2_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2a_board_lib.unb2_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2a_board_lib.unb2_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+
+ -- u_tr_10GbE_back: ENTITY unb2a_board_10gbe_lib.unb2_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2a_board_lib.unb2_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
@@ -1117,156 +1117,156 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
index 86fbfc91d6..de1b1c2fc6 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2a_test_pkg is
@@ -31,27 +31,27 @@ package unb2a_test_pkg is
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
index 27189108a8..7f24df1a84 100644
--- a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2a_test is
generic (
@@ -187,143 +187,143 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2a_test : entity work.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- -- QSFP_0_TX => si_lpbk_0,
- -- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
index 685a1ec112..f31d81c635 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2_board is
generic (
@@ -332,15 +332,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -349,15 +349,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
@@ -366,26 +366,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -399,29 +399,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2_board_clk200_pll : entity work.unb2_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -436,48 +436,48 @@ begin
clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity work.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -485,33 +485,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2_board_system_info : entity work.mms_unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
@@ -549,12 +549,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
@@ -566,15 +566,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2_board_wdi_reg : entity work.unb2_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
@@ -584,75 +584,75 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
@@ -662,74 +662,74 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s; -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2_board_pmbus : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_pmbus,
- g_sens_nof_result => 42,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_pmbus,
+ g_sens_nof_result => 42,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2_fpga_sens : entity work.mms_unb2_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
@@ -739,18 +739,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
@@ -777,43 +777,43 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
index 1f6e0b05ad..c8949d07d5 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2_board_sens is
@@ -70,48 +70,48 @@ architecture str of mms_unb2_board_sens is
begin
u_unb2_board_sens_reg : entity work.unb2_board_sens_reg
- generic map (
- g_sens_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
-
- -- Max temp threshold
- temp_high => temp_high
- );
+ generic map (
+ g_sens_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
+
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2_board_sens : entity work.unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => g_i2c_peripheral,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => g_sens_nof_result,
- g_comma_w => g_comma_w
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => g_i2c_peripheral,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => g_sens_nof_result,
+ g_comma_w => g_comma_w
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
index 75ff5e6a7c..d4f6ede587 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2_board_system_info;
@@ -70,72 +70,74 @@ architecture str of mms_unb2_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0'
+ );
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2_board_system_info: entity work.unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2_board_system_info_reg: entity work.unb2_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
index e619ec2ef2..4b3d863e8c 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2_fpga_sens.vhd
library IEEE, technology_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_fpga_sens is
@@ -67,51 +67,51 @@ architecture str of mms_unb2_fpga_sens is
begin
u_unb2_fpga_sens_reg : entity work.unb2_fpga_sens_reg
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start => mm_start,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_temp_in => reg_temp_mosi,
- sla_temp_out => reg_temp_miso,
- sla_voltage_in => reg_voltage_mosi,
- sla_voltage_out => reg_voltage_miso,
-
- -- MM registers
- --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- --sens_data => sens_data,
-
- -- Max temp threshold
- temp_high => temp_high
- );
-
--- u_unb2_board_sens : ENTITY work.unb2_board_sens
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_clk_freq => g_clk_freq,
--- g_temp_high => g_temp_high,
--- g_sens_nof_result => c_sens_nof_result
--- )
--- PORT MAP (
--- clk => mm_clk,
--- rst => mm_rst,
--- start => mm_start,
--- -- i2c bus
--- scl => scl,
--- sda => sda,
--- -- read results
--- sens_evt => OPEN,
--- sens_err => sens_err,
--- sens_data => sens_data
--- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start => mm_start,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_temp_in => reg_temp_mosi,
+ sla_temp_out => reg_temp_miso,
+ sla_voltage_in => reg_voltage_mosi,
+ sla_voltage_out => reg_voltage_miso,
+
+ -- MM registers
+ --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ --sens_data => sens_data,
+
+ -- Max temp threshold
+ temp_high => temp_high
+ );
+
+ -- u_unb2_board_sens : ENTITY work.unb2_board_sens
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_clk_freq => g_clk_freq,
+ -- g_temp_high => g_temp_high,
+ -- g_sens_nof_result => c_sens_nof_result
+ -- )
+ -- PORT MAP (
+ -- clk => mm_clk,
+ -- rst => mm_rst,
+ -- start => mm_start,
+ -- -- i2c bus
+ -- scl => scl,
+ -- sda => sda,
+ -- -- read results
+ -- sens_evt => OPEN,
+ -- sens_err => sens_err,
+ -- sens_data => sens_data
+ -- );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
index a0060fe1cb..7bd6fed35f 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_back_io is
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
index bf66c9ae6a..9c7c2ec1c4 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
-- Description:
@@ -64,47 +64,47 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
index 6bedd749d7..ac18a564ff 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -140,83 +140,83 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
index eef6905655..6b8f6093af 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -54,16 +54,16 @@ architecture arria10 of unb2_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
index 9d4d3c1bd3..769f2630a6 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -59,28 +59,28 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
index 2bbb9e4613..fdf61eff24 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_front_io is
@@ -69,8 +69,8 @@ begin
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
index 284c10f68e..c1d4b0fcfd 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_hmc_ctrl is
@@ -59,37 +59,89 @@ architecture rtl of unb2_board_hmc_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
index 32c9cd53ff..fd68d6ee22 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
-- Description:
@@ -71,44 +71,44 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2_board_wdi_extend : entity work.unb2_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index 9417764144..33d6eed969 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2_board_peripherals_pkg is
@@ -76,10 +76,10 @@ package unb2_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
index 5a80929f83..710038fdd9 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
@@ -144,23 +144,25 @@ package unb2_board_pkg is
type t_c_unb2_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
+ function func_unb2_board_system_info (
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
end unb2_board_pkg;
package body unb2_board_pkg is
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
+ function func_unb2_board_system_info (
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
variable v_system_info : t_c_unb2_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index 14226a8a74..4453463c71 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_pmbus_ctrl is
@@ -59,37 +59,89 @@ architecture rtl of unb2_board_pmbus_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
index 80e8ae543f..e654c43ac5 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
-- Description:
@@ -111,43 +111,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -166,20 +166,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
index fba74d7787..9f5f981f00 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_ring_io is
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
index 0975230402..d81adac051 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_sens is
generic (
@@ -54,18 +54,18 @@ architecture str of unb2_board_sens is
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
--- octave:4> t=1/50e6
--- t = 2.0000e-08
--- octave:5> delay=2^13 * t
--- delay = 1.6384e-04
--- octave:6> delay/t
--- ans = 8192
--- octave:7> log2(ans)
--- ans = 13
--- octave:8> log2(delay/t)
--- ans = 13
+ -- octave:4> t=1/50e6
+ -- t = 2.0000e-08
+ -- octave:5> delay=2^13 * t
+ -- delay = 1.6384e-04
+ -- octave:6> delay/t
+ -- ans = 8192
+ -- octave:7> log2(ans)
+ -- ans = 13
+ -- octave:8> log2(delay/t)
+ -- ans = 13
--CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
@@ -83,94 +83,94 @@ begin
gen_unb2_board_sens_ctrl : if g_i2c_peripheral = c_i2c_peripheral_sens generate
u_unb2_board_sens_ctrl : entity work.unb2_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_pmbus_ctrl : if g_i2c_peripheral = c_i2c_peripheral_pmbus generate
u_unb2_board_pmbus_ctrl : entity work.unb2_board_pmbus_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_hmc_ctrl : if g_i2c_peripheral = c_i2c_peripheral_hmc generate
u_unb2_board_hmc_ctrl : entity work.unb2_board_hmc_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy,
+ g_clock_stretch_sense_scl => true
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy,
- g_clock_stretch_sense_scl => true
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
end architecture;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 32d5602655..1e1eee824c 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_sens_ctrl is
@@ -73,39 +73,93 @@ architecture rtl of unb2_board_sens_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_SENS_EEPROM_CAT24C02_ADR, CAT24C02_ADR_00,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_HI,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_LO,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_HI,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_LO,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_EEPROM_CAT24C02_ADR,
+ CAT24C02_ADR_00,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_TEMP_TMP451_ADR,
+ TMP451_LOC_HI,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_TEMP_TMP451_ADR,
+ TMP451_LOC_LO,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_TEMP_TMP451_ADR,
+ TMP451_REM_HI,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_TEMP_TMP451_ADR,
+ TMP451_REM_LO,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_QSFP0_BMR464_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP0_BMR464_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP0_BMR464_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP0_BMR464_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_QSFP1_BMR464_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP1_BMR464_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP1_BMR464_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP1_BMR464_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_CLK_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_CLK_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_CLK_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_CLK_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_3V3_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_3V3_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_3V3_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_3V3_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_1V2_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_1V2_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_1V2_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_1V2_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
index 1ff3381d0d..0b886f7070 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_sens_reg is
generic (
@@ -94,13 +94,15 @@ architecture rtl of unb2_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
-
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ -- +1 to fit sens_err in the last address
+
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0'
+ );
signal i_temp_high : std_logic_vector(6 downto 0);
@@ -134,11 +136,11 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
-- Read access: get register value
@@ -154,7 +156,7 @@ begin
else
sla_out.rddata(6 downto 0) <= i_temp_high;
end if;
- -- else unused addresses read zero
+ -- else unused addresses read zero
end if;
end if;
end process;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
index 3ef429a1f9..d7ad980739 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
index 138a1de924..47d5de686b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2_board_system_info_reg;
@@ -81,11 +81,13 @@ architecture rtl of unb2_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0'
+ );
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
index d474968663..dac90aed3e 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -72,27 +72,27 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
index 365e280976..67005e4aa5 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_wdi_reg is
port (
@@ -40,18 +40,20 @@ entity unb2_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2_board_wdi_reg;
architecture rtl of unb2_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0'
+ );
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -64,7 +66,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
index c8474454b2..86c6e335a0 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -23,11 +23,11 @@
--
library IEEE, common_lib, technology_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_fpga_sens_reg is
@@ -62,28 +62,28 @@ end unb2_fpga_sens_reg;
architecture str of unb2_fpga_sens_reg is
- --SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
+--SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
temp_high <= (others => '0'); -- i_temp_high;
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- start_sense => start,
-
- reg_temp_mosi => sla_temp_in,
- reg_temp_miso => sla_temp_out,
-
- reg_voltage_store_mosi => sla_voltage_in,
- reg_voltage_store_miso => sla_voltage_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ start_sense => start,
+
+ reg_temp_mosi => sla_temp_in,
+ reg_temp_miso => sla_temp_out,
+
+ reg_voltage_store_mosi => sla_voltage_in,
+ reg_voltage_store_miso => sla_voltage_out
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index 3128953b34..5a2a2e0f54 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -32,12 +32,12 @@ entity tb_mms_unb2_board_sens is
end tb_mms_unb2_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
@@ -153,63 +153,63 @@ begin
-- I2C sensors master
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => c_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index 3e7d5fa1b9..504a012a6d 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk125_pll is
@@ -57,15 +57,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index 01c62f46e1..727a80bf1d 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk200_pll is
@@ -72,45 +72,45 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b460c275ce..927b5c353b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk25_pll is
@@ -57,15 +57,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 35e015a38b..d601882160 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_node_ctrl is
@@ -76,24 +76,24 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 86668b2331..0b8a946bc8 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -37,10 +37,10 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2_board_qsfp_leds is
end tb_unb2_board_qsfp_leds;
@@ -142,49 +142,49 @@ begin
end process;
u_unb2_factory_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2_user_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 62b69dadc3..0124aee774 100644
--- a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_board_10gbe is
@@ -80,17 +80,17 @@ architecture str of unb2_board_10gbe is
begin
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
index 0b79a074c6..dba45b9957 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
@@ -27,16 +27,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, eth_lib, eth1g_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_arp_ping is
generic (
@@ -190,130 +190,130 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_technology => g_technology,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_udp_offload => g_sim, -- use g_udp_offload to enable ETH instance in simulation
- g_udp_offload_nof_streams => 3, -- use g_udp_offload, but no UDP offload streams
- g_protect_addr_range => g_protect_addr_range,
- g_app_led_red => true,
- g_app_led_green => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_technology => g_technology,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_udp_offload => g_sim, -- use g_udp_offload to enable ETH instance in simulation
+ g_udp_offload_nof_streams => 3, -- use g_udp_offload, but no UDP offload streams
+ g_protect_addr_range => g_protect_addr_range,
+ g_app_led_red => true,
+ g_app_led_green => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-- normaly done by unb_os
p_wdi : process(mm_clk)
@@ -343,49 +343,49 @@ begin
--u_eth1g_master : ENTITY eth1g_lib.eth1g_master(beh)
u_eth1g_master : entity eth1g_lib.eth1g_master(rtl)
- generic map (
- g_sim => g_sim
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- tse_mosi => eth1g_tse_mosi,
- tse_miso => eth1g_tse_miso,
- reg_interrupt => eth1g_reg_interrupt,
- reg_mosi => eth1g_reg_mosi,
- reg_miso => eth1g_reg_miso,
- ram_mosi => eth1g_ram_mosi,
- ram_miso => eth1g_ram_miso,
-
- src_mac => src_mac,
- src_ip => src_ip
- );
+ generic map (
+ g_sim => g_sim
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ tse_mosi => eth1g_tse_mosi,
+ tse_miso => eth1g_tse_miso,
+ reg_interrupt => eth1g_reg_interrupt,
+ reg_mosi => eth1g_reg_mosi,
+ reg_miso => eth1g_reg_miso,
+ ram_mosi => eth1g_ram_mosi,
+ ram_miso => eth1g_ram_miso,
+
+ src_mac => src_mac,
+ src_ip => src_ip
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
index 4ca8b24be4..5cb232a10c 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
@@ -41,19 +41,19 @@
library IEEE, common_lib, dp_lib, technology_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity tb_eth1g is
@@ -94,7 +94,7 @@ architecture tb of tb_eth1g is
-- Payload user data
constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
- -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
+ -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
-- Packet headers
@@ -107,15 +107,21 @@ architecture tb of tb_eth1g is
-- symbols counter ARP=0x806 IP=0x800 IP=0x800
constant c_dut_ethertype : natural := sel_n(g_data_type, 16#07F0#, 16#07F1#, c_network_eth_type_arp, c_network_eth_type_ip, c_network_eth_type_ip);
- constant c_tx_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
- constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
+ constant c_tx_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w)
+ );
+ constant c_discard_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w)
+ );
+ constant c_exp_eth_header : t_network_eth_header := (
+ dst_mac => c_tx_eth_header.src_mac, -- \/
+ src_mac => c_tx_eth_header.dst_mac, -- /\
+ eth_type => c_tx_eth_header.eth_type
+ ); -- =
-- . IP header
constant c_lcu_ip_addr : natural := 16#05060708#; -- = 05:06:07:08
@@ -126,64 +132,76 @@ architecture tb of tb_eth1g is
-- symbols counter ARP ping=1 UDP=17
constant c_tb_ip_protocol : natural := sel_n(g_data_type, 13, 14, 15, c_network_ip_protocol_icmp, c_network_ip_protocol_udp);
- constant c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
- header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
- services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
- total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
- identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
- flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
- fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
- time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
- protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
- src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
- dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
-
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+ constant c_tx_ip_header : t_network_ip_header := (
+ version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
+ header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
+ services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
+ total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
+ identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
+ flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
+ fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
+ time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
+ protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
+ dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w)
+ );
+
+ constant c_exp_ip_header : t_network_ip_header := (
+ version => c_tx_ip_header.version, -- =
+ header_length => c_tx_ip_header.header_length, -- =
+ services => c_tx_ip_header.services, -- =
+ total_length => c_tx_ip_header.total_length, -- =
+ identification => c_tx_ip_header.identification, -- =
+ flags => c_tx_ip_header.flags, -- =
+ fragment_offset => c_tx_ip_header.fragment_offset, -- =
+ time_to_live => c_tx_ip_header.time_to_live, -- =
+ protocol => c_tx_ip_header.protocol, -- =
+ header_checksum => c_tx_ip_header.header_checksum, -- init value
+ src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
+ dst_ip_addr => c_tx_ip_header.src_ip_addr
+ ); -- /\
-- . ARP packet
- constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
- ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
- hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
- plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
- oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
- sha => c_lcu_src_mac,
- spa => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
- tha => c_dut_src_mac,
- tpa => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
-
- constant c_exp_arp_packet : t_network_arp_packet := (htype => c_tx_arp_packet.htype,
- ptype => c_tx_arp_packet.ptype,
- hlen => c_tx_arp_packet.hlen,
- plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
+ constant c_tx_arp_packet : t_network_arp_packet := (
+ htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
+ ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
+ hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
+ plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
+ oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
+ sha => c_lcu_src_mac,
+ spa => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
+ tha => c_dut_src_mac,
+ tpa => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w)
+ );
+
+ constant c_exp_arp_packet : t_network_arp_packet := (
+ htype => c_tx_arp_packet.htype,
+ ptype => c_tx_arp_packet.ptype,
+ hlen => c_tx_arp_packet.hlen,
+ plen => c_tx_arp_packet.plen,
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
+ sha => c_tx_arp_packet.tha, -- \/
+ spa => c_tx_arp_packet.tpa, -- /\ \/
+ tha => c_tx_arp_packet.sha, -- / \ /\
+ tpa => c_tx_arp_packet.spa
+ ); -- / \
-- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
- code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
- id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
- sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
- code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
- id => c_tx_icmp_header.id,
- sequence => c_tx_icmp_header.sequence);
+ constant c_tx_icmp_header : t_network_icmp_header := (
+ msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
+ code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
+ sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w)
+ );
+ constant c_exp_icmp_header : t_network_icmp_header := (
+ msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
+ code => c_tx_icmp_header.code,
+ checksum => c_tx_icmp_header.checksum, -- init value
+ id => c_tx_icmp_header.id,
+ sequence => c_tx_icmp_header.sequence
+ );
-- . UDP header
constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
@@ -194,15 +212,19 @@ architecture tb of tb_eth1g is
constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
constant c_dut_udp_port_st : natural := c_dut_udp_port_st0; -- UDP port used for dst_port
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
- constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
- total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
-
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
+ constant c_tx_udp_header : t_network_udp_header := (
+ src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)
+ ); -- init value
+
+ constant c_exp_udp_header : t_network_udp_header := (
+ src_port => c_tx_udp_header.dst_port, -- \/
+ dst_port => c_tx_udp_header.src_port, -- /\
+ total_length => c_tx_udp_header.total_length, -- =
+ checksum => c_tx_udp_header.checksum
+ ); -- init value
signal tx_total_header : t_network_total_header; -- transmitted packet header
signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
@@ -405,7 +427,7 @@ begin
proc_mem_mm_bus_wr(c_eth_ram_tx_offset + I, TO_SINT(eth_ram_miso.rddata(c_word_w - 1 downto 0)), mm_clk, eth_ram_miso, eth_ram_mosi);
end loop;
--ELSE
- -- . only reply header
+ -- . only reply header
end if;
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
proc_mem_mm_bus_wr(c_eth_reg_control_wi + 0, TO_UINT(v_eth_control_word), mm_clk, eth_reg_miso, eth_reg_mosi);
@@ -456,7 +478,7 @@ begin
for I in 0 to 40 loop
proc_tech_tse_tx_packet(tx_total_header, I, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
- --FOR J IN 0 TO 9 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
+ --FOR J IN 0 TO 9 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
end loop;
if g_frm_discard_en = true then
@@ -486,17 +508,17 @@ begin
proc_tech_tse_tx_packet(tx_total_header, 2, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
end if;
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
tx_end <= '1';
wait;
@@ -532,77 +554,77 @@ begin
end generate;
dut : entity eth_lib.eth
- generic map (
- g_technology => g_technology_dut,
- g_cross_clock_domain => c_cross_clock_domain,
- g_frm_discard_en => g_frm_discard_en
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => eth_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- -- UDP transmit interfaceg_frm_discard_en
- -- . ST sink
- udp_tx_snk_in_arr => udp_tx_sosi_arr,
- udp_tx_snk_out_arr => udp_tx_siso_arr,
- -- UDP receive interface
- -- . ST source
- udp_rx_src_in_arr => udp_rx_siso_arr,
- udp_rx_src_out_arr => udp_rx_sosi_arr,
- -- Control Memory Mapped Slaves
- tse_sla_in => eth_tse_mosi,
- tse_sla_out => eth_tse_miso,
- reg_sla_in => eth_reg_mosi,
- reg_sla_out => eth_reg_miso,
- reg_sla_interrupt => eth_reg_interrupt,
- ram_sla_in => eth_ram_mosi,
- ram_sla_out => eth_ram_miso,
- -- Monitoring
- rx_flushed_frm_cnt => rx_pkt_flushed_cnt,
- -- PHY interface
- eth_txp => eth_txp,
- eth_rxp => eth_rxp,
- -- LED interface
- tse_led => eth_led
- );
+ generic map (
+ g_technology => g_technology_dut,
+ g_cross_clock_domain => c_cross_clock_domain,
+ g_frm_discard_en => g_frm_discard_en
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => eth_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ -- UDP transmit interfaceg_frm_discard_en
+ -- . ST sink
+ udp_tx_snk_in_arr => udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => udp_tx_siso_arr,
+ -- UDP receive interface
+ -- . ST source
+ udp_rx_src_in_arr => udp_rx_siso_arr,
+ udp_rx_src_out_arr => udp_rx_sosi_arr,
+ -- Control Memory Mapped Slaves
+ tse_sla_in => eth_tse_mosi,
+ tse_sla_out => eth_tse_miso,
+ reg_sla_in => eth_reg_mosi,
+ reg_sla_out => eth_reg_miso,
+ reg_sla_interrupt => eth_reg_interrupt,
+ ram_sla_in => eth_ram_mosi,
+ ram_sla_out => eth_ram_miso,
+ -- Monitoring
+ rx_flushed_frm_cnt => rx_pkt_flushed_cnt,
+ -- PHY interface
+ eth_txp => eth_txp,
+ eth_rxp => eth_rxp,
+ -- LED interface
+ tse_led => eth_led
+ );
lcu : entity tech_tse_lib.tech_tse
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => eth_clk,
- tx_snk_clk => st_clk,
- rx_src_clk => st_clk,
-
- -- Memory Mapped Slave
- mm_sla_in => lcu_tse_mosi,
- mm_sla_out => lcu_tse_miso,
-
- -- MAC transmit interface
- -- . ST sink
- tx_snk_in => lcu_tx_sosi,
- tx_snk_out => lcu_tx_siso,
- -- . MAC specific
- tx_mac_in => lcu_tx_mac_in,
- tx_mac_out => lcu_tx_mac_out,
-
- -- MAC receive interface
- -- . ST Source
- rx_src_in => lcu_rx_siso,
- rx_src_out => lcu_rx_sosi,
- -- . MAC specific
- rx_mac_out => lcu_rx_mac_out,
-
- -- PHY interface
- eth_txp => lcu_txp,
- eth_rxp => lcu_rxp,
-
- tse_led => lcu_led
- );
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => eth_clk,
+ tx_snk_clk => st_clk,
+ rx_src_clk => st_clk,
+
+ -- Memory Mapped Slave
+ mm_sla_in => lcu_tse_mosi,
+ mm_sla_out => lcu_tse_miso,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => lcu_tx_sosi,
+ tx_snk_out => lcu_tx_siso,
+ -- . MAC specific
+ tx_mac_in => lcu_tx_mac_in,
+ tx_mac_out => lcu_tx_mac_out,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => lcu_rx_siso,
+ rx_src_out => lcu_rx_sosi,
+ -- . MAC specific
+ rx_mac_out => lcu_rx_mac_out,
+
+ -- PHY interface
+ eth_txp => lcu_txp,
+ eth_rxp => lcu_rxp,
+
+ tse_led => lcu_led
+ );
-- Verification
tx_pkt_cnt <= tx_pkt_cnt + 1 when lcu_tx_sosi.sop = '1' and rising_edge(st_clk);
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
index cbae477513..7f09235dcc 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
@@ -28,10 +28,10 @@
-- > run -all
library IEEE, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity tb_tb_eth1g is
@@ -51,24 +51,24 @@ architecture tb of tb_tb_eth1g is
begin
--- g_technology_dut : NATURAL := c_tech_select_default;
--- g_technology_lcu : NATURAL := c_tech_select_default;
--- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
--- g_flush_test_en : BOOLEAN := FALSE; -- when TRUE send many large frames to enforce flush in eth_buffer
--- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
--- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
--- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
--- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
--- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
--- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
--- g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
+ -- g_technology_dut : NATURAL := c_tech_select_default;
+ -- g_technology_lcu : NATURAL := c_tech_select_default;
+ -- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ -- g_flush_test_en : BOOLEAN := FALSE; -- when TRUE send many large frames to enforce flush in eth_buffer
+ -- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+ -- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+ -- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
+ -- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
+ -- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
+ -- g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
--- u_use_symbols : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
--- u_use_counter : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
--- u_use_arp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
+ -- u_use_symbols : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
+ -- u_use_counter : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
+ -- u_use_arp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
u_use_ping : entity work.tb_eth1g generic map (g_technology_dut, c_technology_lcu, true, false, false, c_tb_tech_tse_data_type_ping ) port map (tb_end_vec(3));
--- u_use_udp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
--- u_use_udp_flush : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
+ -- u_use_udp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
+ -- u_use_udp_flush : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
tb_end <= '1' when tb_end_vec = c_tb_end_vec else '0';
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
index 9ef33d30ab..545f79059b 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
@@ -43,32 +43,32 @@
--
library IEEE, common_lib, technology_lib, unb2b_board_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.tb_common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_unb2b_arp_ping is
- generic (
- g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
- g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
- g_data_type : natural := c_tb_tech_tse_data_type_ping;
- g_tb_end : boolean := true -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- );
+ generic (
+ g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
+ -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+ -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+ -- g_data_type = c_tb_tech_tse_data_type_arp = 2
+ -- g_data_type = c_tb_tech_tse_data_type_ping = 3
+ -- g_data_type = c_tb_tech_tse_data_type_udp = 4
+ g_data_type : natural := c_tb_tech_tse_data_type_ping;
+ g_tb_end : boolean := true -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ );
port (
tb_end : out std_logic
);
@@ -189,7 +189,7 @@ architecture tb of tb_unb2b_arp_ping is
-- Payload user data
constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
- -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
+ -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
-- Packet headers
@@ -197,15 +197,21 @@ architecture tb of tb_unb2b_arp_ping is
-- symbols counter ARP=0x806 IP=0x800 IP=0x800
constant c_dut_ethertype : natural := sel_n(g_data_type, 16#07F0#, 16#07F1#, c_network_eth_type_arp, c_network_eth_type_ip, c_network_eth_type_ip);
- constant c_tx_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
- constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
+ constant c_tx_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w)
+ );
+ constant c_discard_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w)
+ );
+ constant c_exp_eth_header : t_network_eth_header := (
+ dst_mac => c_tx_eth_header.src_mac, -- \/
+ src_mac => c_tx_eth_header.dst_mac, -- /\
+ eth_type => c_tx_eth_header.eth_type
+ ); -- =
-- . IP header
constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
@@ -214,64 +220,76 @@ architecture tb of tb_unb2b_arp_ping is
-- symbols counter ARP ping=1 UDP=17
constant c_tb_ip_protocol : natural := sel_n(g_data_type, 13, 14, 15, c_network_ip_protocol_icmp, c_network_ip_protocol_udp);
- constant c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
- header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
- services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
- total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
- identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
- flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
- fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
- time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
- protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
- src_ip_addr => c_lcu_src_ip,
- dst_ip_addr => c_dut_src_ip);
-
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+ constant c_tx_ip_header : t_network_ip_header := (
+ version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
+ header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
+ services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
+ total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
+ identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
+ flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
+ fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
+ time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
+ protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ src_ip_addr => c_lcu_src_ip,
+ dst_ip_addr => c_dut_src_ip
+ );
+
+ constant c_exp_ip_header : t_network_ip_header := (
+ version => c_tx_ip_header.version, -- =
+ header_length => c_tx_ip_header.header_length, -- =
+ services => c_tx_ip_header.services, -- =
+ total_length => c_tx_ip_header.total_length, -- =
+ identification => c_tx_ip_header.identification, -- =
+ flags => c_tx_ip_header.flags, -- =
+ fragment_offset => c_tx_ip_header.fragment_offset, -- =
+ time_to_live => c_tx_ip_header.time_to_live, -- =
+ protocol => c_tx_ip_header.protocol, -- =
+ header_checksum => c_tx_ip_header.header_checksum, -- init value
+ src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
+ dst_ip_addr => c_tx_ip_header.src_ip_addr
+ ); -- /\
-- . ARP packet
- constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
- ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
- hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
- plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
- oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
- sha => c_lcu_src_mac,
- spa => c_lcu_src_ip,
- tha => c_dut_src_mac,
- tpa => c_dut_src_ip);
-
- constant c_exp_arp_packet : t_network_arp_packet := (htype => c_tx_arp_packet.htype,
- ptype => c_tx_arp_packet.ptype,
- hlen => c_tx_arp_packet.hlen,
- plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
+ constant c_tx_arp_packet : t_network_arp_packet := (
+ htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
+ ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
+ hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
+ plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
+ oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
+ sha => c_lcu_src_mac,
+ spa => c_lcu_src_ip,
+ tha => c_dut_src_mac,
+ tpa => c_dut_src_ip
+ );
+
+ constant c_exp_arp_packet : t_network_arp_packet := (
+ htype => c_tx_arp_packet.htype,
+ ptype => c_tx_arp_packet.ptype,
+ hlen => c_tx_arp_packet.hlen,
+ plen => c_tx_arp_packet.plen,
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
+ sha => c_tx_arp_packet.tha, -- \/
+ spa => c_tx_arp_packet.tpa, -- /\ \/
+ tha => c_tx_arp_packet.sha, -- / \ /\
+ tpa => c_tx_arp_packet.spa
+ ); -- / \
-- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
- code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
- id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
- sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
- code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
- id => c_tx_icmp_header.id,
- sequence => c_tx_icmp_header.sequence);
+ constant c_tx_icmp_header : t_network_icmp_header := (
+ msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
+ code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
+ sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w)
+ );
+ constant c_exp_icmp_header : t_network_icmp_header := (
+ msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
+ code => c_tx_icmp_header.code,
+ checksum => c_tx_icmp_header.checksum, -- init value
+ id => c_tx_icmp_header.id,
+ sequence => c_tx_icmp_header.sequence
+ );
-- . UDP header
constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
@@ -279,15 +297,19 @@ architecture tb of tb_unb2b_arp_ping is
constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
- constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
- total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
+ constant c_tx_udp_header : t_network_udp_header := (
+ src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)
+ ); -- init value
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
+ constant c_exp_udp_header : t_network_udp_header := (
+ src_port => c_tx_udp_header.dst_port, -- \/
+ dst_port => c_tx_udp_header.src_port, -- /\
+ total_length => c_tx_udp_header.total_length, -- =
+ checksum => c_tx_udp_header.checksum
+ ); -- init value
signal tx_total_header : t_network_total_header; -- transmitted packet header
signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
@@ -315,37 +337,37 @@ begin
PMBUS_SD <= 'H'; -- pull up
u_dut : entity work.unb2b_arp_ping
- generic map (
- g_sim => c_sim,
- g_sim_level => c_sim_level
- )
- port map (
- -- GENERAL
- CLK => sys_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp_arr,
- ETH_SGOUT => eth_txp_arr,
-
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => c_sim_level
+ )
+ port map (
+ -- GENERAL
+ CLK => sys_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp_arr,
+ ETH_SGOUT => eth_txp_arr,
+
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- Ethernet cable between LCU and DUT
@@ -383,43 +405,43 @@ begin
end process;
u_lcu : entity tech_tse_lib.tech_tse
- generic map (
- g_sim => c_sim,
- g_sim_level => c_sim_level
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => tse_clk,
- tx_snk_clk => st_clk,
- rx_src_clk => st_clk,
-
- -- Memory Mapped Slave
- mm_sla_in => lcu_tse_mosi,
- mm_sla_out => lcu_tse_miso,
-
- -- MAC transmit interface
- -- . ST sink
- tx_snk_in => lcu_tx_sosi,
- tx_snk_out => lcu_tx_siso,
- -- . MAC specific
- tx_mac_in => lcu_tx_mac_in,
- tx_mac_out => lcu_tx_mac_out,
-
- -- MAC receive interface
- -- . ST Source
- rx_src_in => lcu_rx_siso,
- rx_src_out => lcu_rx_sosi,
- -- . MAC specific
- rx_mac_out => lcu_rx_mac_out,
-
- -- PHY interface
- eth_txp => lcu_txp,
- eth_rxp => lcu_rxp,
-
- tse_led => lcu_led
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => c_sim_level
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => tse_clk,
+ tx_snk_clk => st_clk,
+ rx_src_clk => st_clk,
+
+ -- Memory Mapped Slave
+ mm_sla_in => lcu_tse_mosi,
+ mm_sla_out => lcu_tse_miso,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => lcu_tx_sosi,
+ tx_snk_out => lcu_tx_siso,
+ -- . MAC specific
+ tx_mac_in => lcu_tx_mac_in,
+ tx_mac_out => lcu_tx_mac_out,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => lcu_rx_siso,
+ rx_src_out => lcu_rx_sosi,
+ -- . MAC specific
+ rx_mac_out => lcu_rx_mac_out,
+
+ -- PHY interface
+ eth_txp => lcu_txp,
+ eth_rxp => lcu_rxp,
+
+ tse_led => lcu_led
+ );
------------------------------------------------------------------------------
-- LCU transmit and receive packets
@@ -489,17 +511,17 @@ begin
proc_tech_tse_tx_packet(tx_total_header, 2, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
end if;
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
tx_end <= '1';
wait;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index 8c7247cb87..cc25b86675 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_heater_pkg.all;
entity mmm_unb2b_heater is
@@ -120,35 +120,35 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -165,155 +165,155 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2b_heater
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
---c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
---c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_heater_reset_export => OPEN,
- reg_heater_clk_export => OPEN,
- reg_heater_address_export => reg_heater_mosi.address(4 downto 0),
- reg_heater_read_export => reg_heater_mosi.rd,
- reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
- reg_heater_write_export => reg_heater_mosi.wr,
- reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
+ --c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
+ --c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_heater_reset_export => OPEN,
+ reg_heater_clk_export => OPEN,
+ reg_heater_address_export => reg_heater_mosi.address(4 downto 0),
+ reg_heater_read_export => reg_heater_mosi.rd,
+ reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
+ reg_heater_write_export => reg_heater_mosi.wr,
+ reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
index 831de95afb..57b881cc0a 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
@@ -20,144 +20,144 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v17 QSYS builder
- -----------------------------------------------------------------------------
- component qsys_unb2b_heater is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_heater;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v17 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb2b_heater is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_unb2b_heater;
end qsys_unb2b_heater_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
index 9c548cd558..e904879d61 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2b_heater is
generic (
@@ -56,12 +56,12 @@ entity unb2b_heater is
TESTIO : inout std_logic_vector(c_unb2b_board_aux.testio_w - 1 downto 0);
-- I2C Interface to Sensors
--- SENS_SC : INOUT STD_LOGIC;
--- SENS_SD : INOUT STD_LOGIC;
---
--- PMBUS_SC : INOUT STD_LOGIC;
--- PMBUS_SD : INOUT STD_LOGIC;
--- PMBUS_ALERT : IN STD_LOGIC := '0';
+ -- SENS_SC : INOUT STD_LOGIC;
+ -- SENS_SD : INOUT STD_LOGIC;
+ --
+ -- PMBUS_SC : INOUT STD_LOGIC;
+ -- PMBUS_SD : INOUT STD_LOGIC;
+ -- PMBUS_ALERT : IN STD_LOGIC := '0';
-- 1GbE Control Interface
ETH_CLK : in std_logic;
@@ -165,246 +165,246 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_dp_clk_use_pll => true,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_tse_clk_buf => false, -- TRUE,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
--- SENS_SC => 'Z', --SENS_SC,
--- SENS_SD => 'Z', --SENS_SD,
--- -- PM bus
--- PMBUS_SC => 'Z', --PMBUS_SC,
--- PMBUS_SD => 'Z', --PMBUS_SD,
--- PMBUS_ALERT => 'Z', --PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_dp_clk_use_pll => true,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_tse_clk_buf => false, -- TRUE,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ -- SENS_SC => 'Z', --SENS_SC,
+ -- SENS_SD => 'Z', --SENS_SD,
+ -- -- PM bus
+ -- PMBUS_SC => 'Z', --PMBUS_SC,
+ -- PMBUS_SD => 'Z', --PMBUS_SD,
+ -- PMBUS_ALERT => 'Z', --PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
- g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- g_pipeline => 72, -- max 72
- g_nof_ram => 4, -- max 4
- g_nof_logic => 24 -- max 24
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
+ g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_pipeline => 72, -- max 72
+ g_nof_ram => 4, -- max 4
+ g_nof_logic => 24 -- max 24
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
index 0d2dfea153..582df5ad00 100644
--- a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2b_heater is
- generic (
- g_design_name : string := "unb2b_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_heater;
architecture tb of tb_unb2b_heater is
@@ -184,37 +184,37 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 7d7bea513e..951e9fa4ac 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_corepll is
+ component altjesd_ss_RX_corepll is
port (
locked : out std_logic; -- export
outclk_0 : out std_logic; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 1bc0ee7c56..50d5bb6b90 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_frame_reset is
+ component altjesd_ss_RX_frame_reset is
port (
clk : in std_logic := 'X'; -- clk
in_reset_n : in std_logic := 'X'; -- reset_n
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index e6c8fc658b..77367eabe2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_link_reset is
+ component altjesd_ss_RX_link_reset is
port (
clk : in std_logic := 'X'; -- clk
in_reset_n : in std_logic := 'X'; -- reset_n
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index 46793b217e..c634e00746 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_reset_seq is
+ component altjesd_ss_RX_reset_seq is
generic (
NUM_OUTPUTS : integer := 3;
ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index 4aa29f21f8..8dff895996 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_xcvr_reset_control is
+ component altjesd_ss_RX_xcvr_reset_control is
port (
clock : in std_logic := 'X'; -- clk
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index bfd91a8bfa..7d0eb498ea 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,4 +1,4 @@
- component device_clk is
+ component device_clk is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 342b6062c1..124a3b18ef 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,4 +1,4 @@
- component frame_clk is
+ component frame_clk is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 9868df2cdd..ff194b2a69 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,4 +1,4 @@
- component jesd is
+ component jesd is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index 7da9be04fe..2017afa101 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,4 +1,4 @@
- component link_clk is
+ component link_clk is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index c97253ac79..5a858a60f9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_avs_common_mm_0 is
+ component qsys_unb2b_minimal_avs_common_mm_0 is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index b57aa7daff..75fab6c120 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_avs_common_mm_1 is
+ component qsys_unb2b_minimal_avs_common_mm_1 is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index 3c94c1901f..274d14a577 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index 3fc6ebb7a2..d49ba9d9fb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
@@ -86,9 +86,11 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -135,13 +137,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
c_network_ip_identification_len + c_network_ip_flags_fragment_len +
c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
c_network_ip_addr_len +
c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -175,11 +177,20 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001",
+ "0001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "001",
+ "0000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ARP Packet
@@ -216,12 +227,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -247,12 +258,17 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001",
+ "0000000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -301,8 +317,13 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- UDP Packet
@@ -327,7 +348,7 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
@@ -348,8 +369,12 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 9469fd2656..cfde8ebf26 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
@@ -165,315 +165,318 @@ package common_pkg is
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ function pow2 (n : natural) return natural; -- = 2**n
+ function ceil_pow2 (n : integer) return natural; -- = 2**n, returns 1 for n<0
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function true_log2 (n : natural) return natural; -- true_log2(n) = log2(n)
+ function ceil_log2 (n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
- function floor_log10(n : natural) return natural;
+ function floor_log10 (n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
+ function is_pow2 (n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function true_log_pow2 (n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio ( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio2 (n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
- function ceil_div( n : unsigned; d: natural) return unsigned;
- function ceil_value( n : unsigned; d: natural) return unsigned;
- function floor_value(n : unsigned; d: natural) return unsigned;
+ function ceil_div ( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_value ( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
+ function floor_value (n, d : natural) return natural; -- floor_value = (n/d) * d
+ function ceil_div ( n : unsigned; d: natural) return unsigned;
+ function ceil_value ( n : unsigned; d: natural) return unsigned;
+ function floor_value (n : unsigned; d: natural) return unsigned;
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+ function slv (n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
+ function sl ( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
- function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
- function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr;
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr;
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr;
+ function to_slv_32_arr ( n : t_integer_arr) return t_slv_32_arr;
+ function to_slv_32_arr ( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_and (slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
+ function vector_or ( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
+ function vector_xor (slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
+ function andv (slv : std_logic_vector) return std_logic; -- alias of vector_and
+ function orv ( slv : std_logic_vector) return std_logic; -- alias of vector_or
+ function xorv (slv : std_logic_vector) return std_logic; -- alias of vector_xor
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
+ function matrix_or ( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
- function smallest(n, m : integer) return integer;
- function smallest(n, m, l : integer) return integer;
- function smallest(n : t_natural_arr) return natural;
+ function smallest (n, m : integer) return integer;
+ function smallest (n, m, l : integer) return integer;
+ function smallest (n : t_natural_arr) return natural;
- function largest(n, m : integer) return integer;
- function largest(n : t_natural_arr) return natural;
+ function largest (n, m : integer) return integer;
+ function largest (n : t_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
- function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
- function func_product(n : t_nat_natural_arr) return natural;
+ function func_sum ( n : t_natural_arr) return natural; -- sum of all elements in array
+ function func_sum ( n : t_nat_natural_arr) return natural;
+ function func_product (n : t_natural_arr) return natural; -- product of all elements in array
+ function func_product (n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
-
- function is_true(a : std_logic) return boolean;
- function is_true(a : std_logic) return natural;
- function is_true(a : boolean) return std_logic;
- function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
-
- function sel_a_b(sel, a, b : boolean) return boolean;
- function sel_a_b(sel, a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : real) return real;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : signed) return signed;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
- function sel_a_b(sel : boolean; a, b : string) return string;
- function sel_a_b(sel : integer; a, b : string) return string;
- function sel_a_b(sel : boolean; a, b : time) return time;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+
+ function is_true (a : std_logic) return boolean;
+ function is_true (a : std_logic) return natural;
+ function is_true (a : boolean) return std_logic;
+ function is_true (a : boolean) return natural;
+ function is_true (a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true (a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+
+ function sel_a_b (sel, a, b : boolean) return boolean;
+ function sel_a_b (sel, a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : real) return real;
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : signed) return signed;
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned;
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
+ function sel_a_b (sel : boolean; a, b : string) return string;
+ function sel_a_b (sel : integer; a, b : string) return string;
+ function sel_a_b (sel : boolean; a, b : time) return time;
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
- function array_init(init, nof, incr : natural) return t_nat_natural_arr;
- function array_init(init, nof, incr : integer) return t_slv_16_arr;
- function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
-
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ function sel_n (sel : natural; a, b, c : boolean) return boolean; -- 3
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
+
+ function sel_n (sel : natural; a, b, c : integer) return integer; -- 3
+ function sel_n (sel : natural; a, b, c, d : integer) return integer; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
+
+ function sel_n (sel : natural; a, b : string) return string; -- 2
+ function sel_n (sel : natural; a, b, c : string) return string; -- 3
+ function sel_n (sel : natural; a, b, c, d : string) return string; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : string) return string; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr;
+ function array_init (init, nof, incr : integer) return t_slv_16_arr;
+ function array_init (init, nof, incr : integer) return t_slv_32_arr;
+ function array_init (init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init (init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_sinit (init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
-
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
- function TO_SINT(vec : std_logic_vector) return integer;
-
- function TO_UVEC(dec, w : natural) return std_logic_vector;
- function TO_SVEC(dec, w : integer) return std_logic_vector;
-
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
-
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+
+ function TO_UINT (vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_SINT (vec : std_logic_vector) return integer;
+
+ function TO_UVEC (dec, w : natural) return std_logic_vector;
+ function TO_SVEC (dec, w : integer) return std_logic_vector;
+
+ function TO_SVEC_32 (dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
-- happens for RESIZE of UNSIGNED. Therefor this is what the RESIZE_NUM for SIGNED and the RESIZE_SVEC do
-- and better not use RESIZE for SIGNED anymore.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
-
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
-
- function offset_binary(a : std_logic_vector) return std_logic_vector;
-
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
- function flip(a : t_slv_32_arr) return t_slv_32_arr;
- function flip(a : t_integer_arr) return t_integer_arr;
- function flip(a : t_natural_arr) return t_natural_arr;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
-
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
-
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
-
- function pad(str: string; width: natural; pad_char: character) return string;
-
- function slice_up(str: string; width: natural; i: natural) return string;
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string;
- function slice_dn(str: string; width: natural; i: natural) return string;
-
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
+ function RESIZE_NUM ( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM ( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
+ function RESIZE_UINT (u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
+ function RESIZE_SINT (s : integer; w : natural) return integer; -- extend sign bit or keep LS part
+
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector;
+ -- Used in common_add_sub.vhd
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+
+ function offset_binary (a : std_logic_vector) return std_logic_vector;
+
+ function truncate ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function scale ( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
+ function scale_and_resize_uvec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_svec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function truncate_or_resize_uvec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_svec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
+
+ function s_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round_up (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up (vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
+ function u_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
+ function u_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
+
+ function u_to_s (u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function s_to_u (s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+
+ function u_wrap (u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function s_wrap (s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+
+ function u_clip (u : natural; max : natural) return natural; -- if s < max return s, else return n
+ function s_clip (s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip (s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
+
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
+ function hton (a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh (a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+
+ function flip (a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
+ function flip (a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip (a : t_slv_32_arr) return t_slv_32_arr;
+ function flip (a : t_integer_arr) return t_integer_arr;
+ function flip (a : t_natural_arr) return t_natural_arr;
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr;
+
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
+
+ function pad (str: string; width: natural; pad_char: character) return string;
+
+ function slice_up (str: string; width: natural; i: natural) return string;
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string;
+ function slice_dn (str: string; width: natural; i: natural) return string;
+
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
------------------------------------------------------------------------------
-- Component specific functions
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
- function func_common_reorder2_is_there(I, J : natural) return boolean;
- function func_common_reorder2_is_active(I, J, N : natural) return boolean;
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer;
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural;
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
+ function func_common_reorder2_is_there (I, J : natural) return boolean;
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean;
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer;
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural;
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
- function pow2(n : natural) return natural is
+ function pow2 (n : natural) return natural is
begin
return 2**n;
end;
- function ceil_pow2(n : integer) return natural is
+ function ceil_pow2 (n : integer) return natural is
-- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
- function true_log2(n : natural) return natural is
+ function true_log2 (n : natural) return natural is
-- Purpose: For calculating extra vector width of existing vector
-- Description: Return mathematical ceil(log2(n))
-- n log2()
@@ -492,7 +495,7 @@ package body common_pkg is
return natural(integer(ceil(log2(real(n)))));
end;
- function ceil_log2(n : natural) return natural is
+ function ceil_log2 (n : natural) return natural is
-- Purpose: For calculating vector width of new vector
-- Description:
-- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
@@ -510,22 +513,22 @@ package body common_pkg is
end if;
end;
- function floor_log10(n : natural) return natural is
+ function floor_log10 (n : natural) return natural is
begin
return natural(integer(floor(log10(real(n)))));
end;
- function is_pow2(n : natural) return boolean is
+ function is_pow2 (n : natural) return boolean is
begin
return n = 2**true_log2(n);
end;
- function true_log_pow2(n : natural) return natural is
+ function true_log_pow2 (n : natural) return natural is
begin
return 2**true_log2(n);
end;
- function ratio(n, d : natural) return natural is
+ function ratio (n, d : natural) return natural is
begin
if n mod d = 0 then
return n / d;
@@ -534,32 +537,32 @@ package body common_pkg is
end if;
end;
- function ratio2(n, m : natural) return natural is
+ function ratio2 (n, m : natural) return natural is
begin
return largest(ratio(n,m), ratio(m,n));
end;
- function ceil_div(n, d : natural) return natural is
+ function ceil_div (n, d : natural) return natural is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
- function ceil_value(n, d : natural) return natural is
+ function ceil_value (n, d : natural) return natural is
begin
return ceil_div(n, d) * d;
end;
- function floor_value(n, d : natural) return natural is
+ function floor_value (n, d : natural) return natural is
begin
return (n / d) * d;
end;
- function ceil_div(n : unsigned; d: natural) return unsigned is
+ function ceil_div (n : unsigned; d: natural) return unsigned is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
end;
- function ceil_value(n : unsigned; d: natural) return unsigned is
+ function ceil_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -567,7 +570,7 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function floor_value(n : unsigned; d: natural) return unsigned is
+ function floor_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -575,21 +578,21 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function slv(n: in std_logic) return std_logic_vector is
+ function slv (n: in std_logic) return std_logic_vector is
variable r : std_logic_vector(0 downto 0);
begin
r(0) := n;
return r;
end;
- function sl(n: in std_logic_vector) return std_logic is
+ function sl (n: in std_logic_vector) return std_logic is
variable r : std_logic;
begin
r := n(n'low);
return r;
end;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr is
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -607,7 +610,7 @@ package body common_pkg is
return vR;
end;
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr is
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr is
variable vN : t_nat_natural_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -618,7 +621,7 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_integer_arr(n'length - 1 downto 0);
begin
@@ -629,14 +632,14 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return to_integer_arr(vN);
end;
- function to_slv_32_arr(n : t_integer_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_integer_arr) return t_slv_32_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -647,7 +650,7 @@ package body common_pkg is
return vR;
end;
- function to_slv_32_arr(n : t_natural_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_natural_arr) return t_slv_32_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -658,7 +661,7 @@ package body common_pkg is
return vR;
end;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic is
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic is
-- Linear loop to determine result takes combinatorial delay that is proportional to slv'LENGTH:
-- FOR I IN slv'RANGE LOOP
-- v_result := v_result OPERATION slv(I);
@@ -691,22 +694,22 @@ package body common_pkg is
return v_stage_arr(c_nof_stages - 1)(0);
end;
- function vector_and(slv : std_logic_vector) return std_logic is
+ function vector_and (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function vector_or(slv : std_logic_vector) return std_logic is
+ function vector_or (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function vector_xor(slv : std_logic_vector) return std_logic is
+ function vector_xor (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector is
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector is
variable v_one_hot : boolean := false;
variable v_zeros : std_logic_vector(slv'range) := (others => '0');
begin
@@ -725,22 +728,22 @@ package body common_pkg is
return slv;
end;
- function andv(slv : std_logic_vector) return std_logic is
+ function andv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function orv(slv : std_logic_vector) return std_logic is
+ function orv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function xorv(slv : std_logic_vector) return std_logic is
+ function xorv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '1';
begin
@@ -752,7 +755,7 @@ package body common_pkg is
return v_result;
end;
- function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_or (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '0';
begin
@@ -764,7 +767,7 @@ package body common_pkg is
return v_result;
end;
- function smallest(n, m : integer) return integer is
+ function smallest (n, m : integer) return integer is
begin
if n < m then
return n;
@@ -773,16 +776,16 @@ package body common_pkg is
end if;
end;
- function smallest(n, m, l : integer) return integer is
+ function smallest (n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
end;
- function smallest(n : t_natural_arr) return natural is
+ function smallest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -793,7 +796,7 @@ package body common_pkg is
return m;
end;
- function largest(n, m : integer) return integer is
+ function largest (n, m : integer) return integer is
begin
if n > m then
return n;
@@ -802,7 +805,7 @@ package body common_pkg is
end if;
end;
- function largest(n : t_natural_arr) return natural is
+ function largest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -813,7 +816,7 @@ package body common_pkg is
return m;
end;
- function func_sum(n : t_natural_arr) return natural is
+ function func_sum (n : t_natural_arr) return natural is
variable vS : natural;
begin
vS := 0;
@@ -823,14 +826,14 @@ package body common_pkg is
return vS;
end;
- function func_sum(n : t_nat_natural_arr) return natural is
+ function func_sum (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return func_sum(vN);
end;
- function func_product(n : t_natural_arr) return natural is
+ function func_product (n : t_natural_arr) return natural is
variable vP : natural;
begin
vP := 1;
@@ -840,7 +843,7 @@ package body common_pkg is
return vP;
end;
- function func_product(n : t_nat_natural_arr) return natural is
+ function func_product (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
@@ -999,14 +1002,14 @@ package body common_pkg is
return vP;
end;
- function is_true(a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
- function is_true(a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
- function is_true(a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
- function is_true(a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
- function is_true(a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
- function is_true(a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
+ function is_true (a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
+ function is_true (a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
+ function is_true (a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
+ function is_true (a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
+ function is_true (a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
+ function is_true (a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
- function sel_a_b(sel, a, b : integer) return integer is
+ function sel_a_b (sel, a, b : integer) return integer is
begin
if sel /= 0 then
return a;
@@ -1015,7 +1018,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel, a, b : boolean) return boolean is
+ function sel_a_b (sel, a, b : boolean) return boolean is
begin
if sel = true then
return a;
@@ -1024,7 +1027,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : integer) return integer is
+ function sel_a_b (sel : boolean; a, b : integer) return integer is
begin
if sel = true then
return a;
@@ -1033,7 +1036,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : real) return real is
+ function sel_a_b (sel : boolean; a, b : real) return real is
begin
if sel = true then
return a;
@@ -1042,7 +1045,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic is
begin
if sel = true then
return a;
@@ -1051,7 +1054,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic is
begin
if sel /= 0 then
return a;
@@ -1060,7 +1063,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector is
begin
if sel /= 0 then
return a;
@@ -1069,7 +1072,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
if sel = true then
return a;
@@ -1078,7 +1081,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : signed) return signed is
+ function sel_a_b (sel : boolean; a, b : signed) return signed is
begin
if sel = true then
return a;
@@ -1087,7 +1090,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned is
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned is
begin
if sel = true then
return a;
@@ -1096,7 +1099,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr is
begin
if sel = true then
return a;
@@ -1105,7 +1108,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr is
begin
if sel = true then
return a;
@@ -1114,7 +1117,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
begin
if sel = true then
return a;
@@ -1123,7 +1126,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
begin
if sel = true then
return a;
@@ -1132,7 +1135,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : string) return string is
+ function sel_a_b (sel : boolean; a, b : string) return string is
begin
if sel = true then
return a;
@@ -1141,7 +1144,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : string) return string is
+ function sel_a_b (sel : integer; a, b : string) return string is
begin
if sel /= 0 then
return a;
@@ -1150,7 +1153,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : time) return time is
+ function sel_a_b (sel : boolean; a, b : time) return time is
begin
if sel = true then
return a;
@@ -1159,7 +1162,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level is
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level is
begin
if sel = true then
return a;
@@ -1169,115 +1172,115 @@ package body common_pkg is
end;
-- sel_n : boolean
- function sel_n(sel : natural; a, b, c : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : integer
- function sel_n(sel : natural; a, b, c : integer) return integer is
+ function sel_n (sel : natural; a, b, c : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : string
- function sel_n(sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
- function sel_n(sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
- function sel_n(sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
- function sel_n(sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector is
+ function sel_n (sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
+ function sel_n (sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
+ function sel_n (sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector is
variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1286,7 +1289,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_natural_arr is
+ function array_init (init, nof : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1295,7 +1298,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_nat_natural_arr is
+ function array_init (init, nof : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1304,7 +1307,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_natural_arr is
+ function array_init (init, nof, incr : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1316,7 +1319,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_nat_natural_arr is
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1328,7 +1331,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_16_arr is
+ function array_init (init, nof, incr : integer) return t_slv_16_arr is
variable v_arr : t_slv_16_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1340,7 +1343,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_32_arr is
+ function array_init (init, nof, incr : integer) return t_slv_32_arr is
variable v_arr : t_slv_32_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1352,7 +1355,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width : natural) return std_logic_vector is
+ function array_init (init, nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1361,7 +1364,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width, incr : natural) return std_logic_vector is
+ function array_init (init, nof, width, incr : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
variable v_i : natural;
begin
@@ -1373,7 +1376,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
+ function array_sinit (init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1382,7 +1385,7 @@ package body common_pkg is
return v_arr;
end;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix is
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix is
variable v_mat : t_slv_64_matrix(nof_a - 1 downto 0, nof_b - 1 downto 0);
begin
for I in 0 to nof_a - 1 loop
@@ -1395,7 +1398,7 @@ package body common_pkg is
-- Support concatenation of up to 7 slv into 1 slv
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length;
variable v_res : std_logic_vector(c_max_w - 1 downto 0) := (others => '0');
variable v_len : natural := 0;
@@ -1410,32 +1413,32 @@ package body common_pkg is
return v_res(v_len - 1 downto 0);
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, false, a, b, c, d, e, f, "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, false, false, a, b, c, d, e, "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, false, false, false, a, b, c, d, "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, false, false, false, false, a, b, c, "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, false, false, false, false, false, a, b, "0", "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
variable v_len : natural := 0;
begin
if use_a = true then v_len := v_len + a_w; end if;
@@ -1448,33 +1451,33 @@ package body common_pkg is
return v_len;
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, false, a_w, b_w, c_w, d_w, e_w, f_w, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0);
end func_slv_concat_w;
-- extract slv
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
variable v_w : natural := 0;
variable v_lo : natural := 0;
begin
@@ -1520,64 +1523,64 @@ package body common_pkg is
return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, false, a_w, b_w, c_w, d_w, e_w, f_w, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function TO_UINT(vec : std_logic_vector) return natural is
+ function TO_UINT (vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
end;
- function TO_SINT(vec : std_logic_vector) return integer is
+ function TO_SINT (vec : std_logic_vector) return integer is
begin
return to_integer(signed(vec));
end;
- function TO_UVEC(dec, w : natural) return std_logic_vector is
+ function TO_UVEC (dec, w : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(dec, w));
end;
- function TO_SVEC(dec, w : integer) return std_logic_vector is
+ function TO_SVEC (dec, w : integer) return std_logic_vector is
begin
return std_logic_vector(to_signed(dec, w));
end;
- function TO_SVEC_32(dec : integer) return std_logic_vector is
+ function TO_SVEC_32 (dec : integer) return std_logic_vector is
begin
return TO_SVEC(dec, 32);
end;
- function RESIZE_NUM(u : unsigned; w : natural) return unsigned is
+ function RESIZE_NUM (u : unsigned; w : natural) return unsigned is
begin
-- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
return resize(u, w);
end;
- function RESIZE_NUM(s : signed; w : natural) return signed is
+ function RESIZE_NUM (s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
if w > s'length then
@@ -1587,47 +1590,47 @@ package body common_pkg is
end if;
end;
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector is
variable v_slv0 : std_logic_vector(w - 1 downto 1) := (others => '0');
begin
return v_slv0 & sl;
end;
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(vec), w));
end;
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(vec), w));
end;
- function RESIZE_UINT(u : integer; w : natural) return integer is
+ function RESIZE_UINT (u : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_UVEC(u, c_word_w);
return TO_UINT(v(w - 1 downto 0));
end;
- function RESIZE_SINT(s : integer; w : natural) return integer is
+ function RESIZE_SINT (s : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_SVEC(s, c_word_w);
return TO_SINT(v(w - 1 downto 0));
end;
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, 32);
end;
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, 32);
end;
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
if dec < 0 then
@@ -1639,74 +1642,74 @@ package body common_pkg is
end if;
end;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector is
begin
return std_logic_vector(unsigned(vec) + dec);
end;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
return std_logic_vector(signed(vec) + v_dec); -- uses function "+" (L : SIGNED, R : INTEGER)
end;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector is
begin
return std_logic_vector(signed(vec) + dec);
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) + signed(r_vec));
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) - signed(r_vec));
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) + unsigned(r_vec));
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_SVEC(l_vec, r_vec, l_vec'length);
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_UVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_UVEC(l_vec, r_vec, l_vec'length);
end;
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_re * b_re - a_im * b_im);
end;
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_im * b_re + a_re * b_im);
end;
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
@@ -1715,7 +1718,7 @@ package body common_pkg is
end if;
end;
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
@@ -1741,24 +1744,24 @@ package body common_pkg is
-- The offset_binary() mapping can be done and undone both ways.
-- The offset_binary() mapping to two-complement binary yields a DC offset
-- of -0.5 Lsb.
- function offset_binary(a : std_logic_vector) return std_logic_vector is
+ function offset_binary (a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
- function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function truncate (vec : std_logic_vector; n : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -1769,7 +1772,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -1780,7 +1783,7 @@ package body common_pkg is
return v_res;
end;
- function scale(vec : std_logic_vector; n: natural) return std_logic_vector is
+ function scale (vec : std_logic_vector; n: natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1789,7 +1792,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1800,7 +1803,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1811,7 +1814,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_uvec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_uvec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -1824,7 +1827,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_svec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_svec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -1856,7 +1859,7 @@ package body common_pkg is
-- maximum product is -8*-8=+64 <= 127-8, so wrapping due to rounding
-- overflow will never occur.
- function s_round(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
-- Use SIGNED to avoid NATURAL (32 bit range) overflow error
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
@@ -1884,24 +1887,24 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return s_round(vec, n, false); -- no round clip
end;
-- An alternative is to always round up, also for negative numbers (i.e. s_round_up = u_round).
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round_up (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
begin
return u_round(vec, n, clip);
end;
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round_up (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
-- Unsigned numbers are round up (almost same as s_round, but without the else on negative vec)
- function u_round(vec : std_logic_vector; n : natural; clip : boolean ) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural; clip : boolean ) return std_logic_vector is
-- Use UNSIGNED to avoid NATURAL (32 bit range) overflow error
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
@@ -1925,36 +1928,36 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
- function u_to_s(u : natural; w : natural) return integer is
+ function u_to_s (u : natural; w : natural) return integer is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
- function s_to_u(s : integer; w : natural) return natural is
+ function s_to_u (s : integer; w : natural) return natural is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
- function u_wrap(u : natural; w : natural) return natural is
+ function u_wrap (u : natural; w : natural) return natural is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
- function s_wrap(s : integer; w : natural) return integer is
+ function s_wrap (s : integer; w : natural) return integer is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
- function u_clip(u : natural; max : natural) return natural is
+ function u_clip (u : natural; max : natural) return natural is
begin
if u > max then
return max;
@@ -1963,7 +1966,7 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural; min : integer) return integer is
+ function s_clip (s : integer; max : natural; min : integer) return integer is
begin
if s < min then
return min;
@@ -1976,12 +1979,12 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural) return integer is
+ function s_clip (s : integer; max : natural) return integer is
begin
return s_clip(s, max, -max);
end;
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
variable vL : natural;
@@ -1997,28 +2000,28 @@ package body common_pkg is
return v_b;
end function;
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
end function;
- function hton(a : std_logic_vector) return std_logic_vector is
+ function hton (a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
end function;
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, sz); -- i.e. ntoh() = hton()
end function;
- function ntoh(a : std_logic_vector) return std_logic_vector is
+ function ntoh (a : std_logic_vector) return std_logic_vector is
begin
return hton(a); -- i.e. ntoh() = hton()
end function;
- function flip(a : std_logic_vector) return std_logic_vector is
+ function flip (a : std_logic_vector) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2028,12 +2031,12 @@ package body common_pkg is
return v_b;
end;
- function flip(a, w : natural) return natural is
+ function flip (a, w : natural) return natural is
begin
return TO_UINT(flip(TO_UVEC(a, w)));
end;
- function flip(a : t_slv_32_arr) return t_slv_32_arr is
+ function flip (a : t_slv_32_arr) return t_slv_32_arr is
variable v_a : t_slv_32_arr(a'length - 1 downto 0) := a;
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
@@ -2043,7 +2046,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_integer_arr) return t_integer_arr is
+ function flip (a : t_integer_arr) return t_integer_arr is
variable v_a : t_integer_arr(a'length - 1 downto 0) := a;
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
@@ -2053,7 +2056,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_natural_arr) return t_natural_arr is
+ function flip (a : t_natural_arr) return t_natural_arr is
variable v_a : t_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
@@ -2063,7 +2066,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr is
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr is
variable v_a : t_nat_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
@@ -2073,7 +2076,7 @@ package body common_pkg is
return v_b;
end;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector is
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2087,7 +2090,7 @@ package body common_pkg is
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
variable vI : natural;
variable vJ : natural;
begin
@@ -2096,7 +2099,7 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
@@ -2111,34 +2114,34 @@ package body common_pkg is
end loop;
end;
- function pad(str: string; width: natural; pad_char: character) return string is
+ function pad (str: string; width: natural; pad_char: character) return string is
variable v_str : string(1 to width) := (others => pad_char);
begin
v_str(width - str'length + 1 to width) := str;
return v_str;
end;
- function slice_up(str: string; width: natural; i: natural) return string is
+ function slice_up (str: string; width: natural; i: natural) return string is
begin
return str(i * width + 1 to (i + 1) * width);
end;
-- If the input value is not a multiple of the desired width, the return value is padded with
-- the passed pad value. E.g. if input='10' and desired width is 4, return value is '0010'.
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string is
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
- function slice_dn(str: string; width: natural; i: natural) return string is
+ function slice_dn (str: string; width: natural; i: natural) return string is
begin
return str((i + 1) * width - 1 downto i * width);
end;
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
for i in 0 to nof_elements - 1 loop
@@ -2152,16 +2155,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2174,7 +2178,7 @@ package body common_pkg is
assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
- --synthesis translate_on
+ --synthesis translate_on
end procedure proc_common_fifo_asserts;
@@ -2182,8 +2186,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2204,7 +2209,7 @@ package body common_pkg is
------------------------------------------------------------------------------
-- Determine whether the stage I and row J index refer to any (active or redundant) 2-input reorder cell instantiation
- function func_common_reorder2_is_there(I, J : natural) return boolean is
+ function func_common_reorder2_is_there (I, J : natural) return boolean is
variable v_odd : boolean;
variable v_even : boolean;
begin
@@ -2214,7 +2219,7 @@ package body common_pkg is
end func_common_reorder2_is_there;
-- Determine whether the stage I and row J index refer to an active 2-input reorder cell instantiation in a reorder network with N stages
- function func_common_reorder2_is_active(I, J, N : natural) return boolean is
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean is
variable v_inst : boolean;
variable v_act : boolean;
begin
@@ -2224,7 +2229,7 @@ package body common_pkg is
end func_common_reorder2_is_active;
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer is
constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
@@ -2246,7 +2251,7 @@ package body common_pkg is
end func_common_reorder2_get_select_index;
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -2261,7 +2266,7 @@ package body common_pkg is
end func_common_reorder2_get_select;
-- Determine the inverse of a reorder network by using two reorder networks in series
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -2287,8 +2292,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2327,9 +2332,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
@@ -2354,7 +2360,7 @@ package body common_pkg is
end if;
wait for v_speriod / 2;
SCLK <= '1';
- -- Wait for next DCLK
+ -- Wait for next DCLK
end loop;
wait;
end proc_common_dclk_generate_sclk;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 40128fea21..0fa106e866 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
@@ -121,15 +121,33 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_bsn_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ '1',
+ '1',
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_empty_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_channel_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_error_w)
+ );
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -208,30 +226,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -240,142 +262,142 @@ package dp_stream_pkg is
-- Typically the sosi data are treated as unsigned in the record field, so extended with '0'. However for interpretating
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
- function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
- function TO_DP_EMPTY( n : natural) return std_logic_vector;
- function TO_DP_CHANNEL( n : natural) return std_logic_vector;
- function TO_DP_ERROR( n : natural) return std_logic_vector;
- function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
- function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
-
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
-
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
-
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
+ function TO_DP_BSN ( n : natural) return std_logic_vector;
+ function TO_DP_DATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_SDATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
+ function TO_DP_UDATA ( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector; -- for re and im fields, signed data
+ function TO_DP_DSP_UDATA (n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_EMPTY ( n : natural) return std_logic_vector;
+ function TO_DP_CHANNEL ( n : natural) return std_logic_vector;
+ function TO_DP_ERROR ( n : natural) return std_logic_vector;
+ function RESIZE_DP_BSN ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_DATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
+ function RESIZE_DP_SDATA ( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
+ function RESIZE_DP_XDATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_EMPTY ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_CHANNEL ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_ERROR ( vec : std_logic_vector) return std_logic_vector;
+
+ function INCR_DP_DATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
+ function INCR_DP_SDATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+
+ function REPLICATE_DP_DATA ( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
-- Shift and combine part of previous data and this data, use the other sosi from prev_sosi
- function func_dp_data_shift( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
+ function func_dp_data_shift ( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
+ function func_dp_data_shift_last ( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
-- Determine resulting empty if two streams are concatenated or split
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi;
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi;
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; str : string) return std_logic;
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector;
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
-- Fix reversed buses due to connecting TO to DOWNTO range arrays.
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr;
-- Functions to combinatorially hold the data fields and to set or reset the control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_info( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_control( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_reset_control( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_info ( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_control ( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reset_control ( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
-- Reset sosi ctrl and preserve the sosi data (to avoid unnecessary data toggling and to ease data view in Wave window)
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
-- Function to copy the BSN of one valid stream to all output streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
-- Functions to combinatorially handle the BSN field
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
-- Functions to combine sosi fields
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi;
-- Functions to convert sosi fields
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
-- Functions to set the DATA, RE and IM field in a stream.
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
-
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
-
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
+
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -384,14 +406,14 @@ package dp_stream_pkg is
-- . data_order_im_re = TRUE then "COMPLEX" data = im&re
-- FALSE then "COMPLEX" data = re&im
-- ignore when data_representation /= "COMPLEX"
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
end dp_stream_pkg;
@@ -399,11 +421,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -417,20 +440,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -448,118 +473,119 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
- function TO_DP_BSN(n : natural) return std_logic_vector is
+ function TO_DP_BSN (n : natural) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_bsn_w);
end TO_DP_BSN;
- function TO_DP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_DATA;
- function TO_DP_SDATA(n : integer) return std_logic_vector is
+ function TO_DP_SDATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_SDATA;
- function TO_DP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_UDATA (n : integer) return std_logic_vector is
begin
return TO_DP_DATA(n);
end TO_DP_UDATA;
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_DATA;
- function TO_DP_DSP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_UDATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_UDATA;
- function TO_DP_EMPTY(n : natural) return std_logic_vector is
+ function TO_DP_EMPTY (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_empty_w);
end TO_DP_EMPTY;
- function TO_DP_CHANNEL(n : natural) return std_logic_vector is
+ function TO_DP_CHANNEL (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_channel_w);
end TO_DP_CHANNEL;
- function TO_DP_ERROR(n : natural) return std_logic_vector is
+ function TO_DP_ERROR (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_error_w);
end TO_DP_ERROR;
- function RESIZE_DP_BSN(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_BSN (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_bsn_w);
end RESIZE_DP_BSN;
- function RESIZE_DP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_DATA;
- function RESIZE_DP_SDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_SDATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_SDATA;
- function RESIZE_DP_XDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_XDATA (vec : std_logic_vector) return std_logic_vector is
variable v_vec : std_logic_vector(c_dp_stream_data_w - 1 downto 0) := (others => 'X');
begin
v_vec(vec'length - 1 downto 0) := vec;
return v_vec;
end RESIZE_DP_XDATA;
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_dsp_data_w);
end RESIZE_DP_DSP_DATA;
- function RESIZE_DP_EMPTY(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_EMPTY (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_empty_w);
end RESIZE_DP_EMPTY;
- function RESIZE_DP_CHANNEL(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_CHANNEL (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_channel_w);
end RESIZE_DP_CHANNEL;
- function RESIZE_DP_ERROR(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_ERROR (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_error_w);
end RESIZE_DP_ERROR;
- function INCR_DP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DATA(std_logic_vector(unsigned(vec(w - 1 downto 0)) + dec));
end INCR_DP_DATA;
- function INCR_DP_SDATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_SDATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_SDATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_SDATA;
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DSP_DATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_DSP_DATA;
- function REPLICATE_DP_DATA(seq : std_logic_vector) return std_logic_vector is
+ function REPLICATE_DP_DATA (seq : std_logic_vector) return std_logic_vector is
constant c_seq_w : natural := seq'length;
constant c_nof_replications : natural := ceil_div(c_dp_stream_data_w, c_seq_w);
constant c_vec_w : natural := ceil_value(c_dp_stream_data_w, c_seq_w);
@@ -571,7 +597,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
@@ -590,7 +616,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -608,7 +634,7 @@ package body dp_stream_pkg is
end TO_DP_SOSI_UNSIGNED;
-- Keep part of head data and combine part of tail data
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
@@ -625,7 +651,7 @@ package body dp_stream_pkg is
-- Shift and combine part of previous data and this data,
- function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
+ function func_dp_data_shift (prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
@@ -658,7 +684,7 @@ package body dp_stream_pkg is
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
+ function func_dp_data_shift_last (tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
variable vL : natural := input_empty;
variable vN : natural := nof_symbols_per_data;
@@ -688,7 +714,7 @@ package body dp_stream_pkg is
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(head_empty);
@@ -700,7 +726,7 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_concat;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(input_empty);
@@ -715,7 +741,7 @@ package body dp_stream_pkg is
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
begin
for I in dp'range loop
@@ -729,7 +755,7 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -751,7 +777,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -775,19 +801,19 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -809,7 +835,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -833,13 +859,13 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
@@ -847,7 +873,7 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -860,7 +886,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -875,19 +901,19 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -899,7 +925,7 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -915,7 +941,7 @@ package body dp_stream_pkg is
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -928,7 +954,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -941,7 +967,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -954,7 +980,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -967,7 +993,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -980,7 +1006,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -993,7 +1019,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1006,7 +1032,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1019,7 +1045,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr is
variable v_to_range : t_dp_siso_arr(0 to in_arr'high);
variable v_downto_range : t_dp_siso_arr(in_arr'high downto 0);
begin
@@ -1036,7 +1062,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_reverse_range;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_to_range : t_dp_sosi_arr(0 to in_arr'high);
variable v_downto_range : t_dp_sosi_arr(in_arr'high downto 0);
begin
@@ -1054,7 +1080,7 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reverse_range;
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
@@ -1062,7 +1088,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
- function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_info (dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi info
@@ -1074,7 +1100,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_info;
- function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_control (dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi control
@@ -1086,7 +1112,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_control;
- function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reset_control (dp : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- reset sosi control
@@ -1098,7 +1124,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_reset_control;
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp; -- hold sosi data
begin
-- reset sosi control
@@ -1110,7 +1136,7 @@ package body dp_stream_pkg is
end func_dp_stream_reset_control;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
begin
for I in dp'range loop
@@ -1123,13 +1149,13 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_max(dp, c_mask, w);
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
begin
for I in dp'range loop
@@ -1142,14 +1168,14 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_min;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_min(dp, c_mask, w);
end func_dp_stream_arr_bsn_min;
-- Function to copy the BSN number of one valid stream to all other streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
@@ -1166,14 +1192,14 @@ package body dp_stream_pkg is
-- Functions to combinatorially handle channels
- function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.channel := TO_UVEC(ch, c_dp_stream_channel_w);
return v_rec;
end func_dp_stream_channel_set;
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) /= ch then
@@ -1184,7 +1210,7 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_select;
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) = ch then
@@ -1196,7 +1222,7 @@ package body dp_stream_pkg is
end func_dp_stream_channel_remove;
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.err := TO_UVEC(n, c_dp_stream_error_w);
@@ -1204,7 +1230,7 @@ package body dp_stream_pkg is
end func_dp_stream_error_set;
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.bsn := RESIZE_DP_BSN(bsn);
@@ -1212,7 +1238,7 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
-- Combine sosi data with the sosi info fields
@@ -1225,7 +1251,7 @@ package body dp_stream_pkg is
end func_dp_stream_combine_info_and_data;
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
@@ -1242,23 +1268,23 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_slv_to_integer;
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1267,7 +1293,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1278,8 +1304,8 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_re : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1300,17 +1326,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_hi : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1333,17 +1359,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, 1, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1352,17 +1378,17 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1371,18 +1397,18 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, 1, true);
end;
-- Concatenate the data (and complex fields) from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out : t_dp_sosi := snk_in_arr(0);
begin
@@ -1397,7 +1423,7 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1407,7 +1433,7 @@ package body dp_stream_pkg is
end;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_in_w : natural := in_w / 2;
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
@@ -1445,12 +1471,12 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
begin
return func_dp_stream_reconcat(snk_in, in_w, out_w, nof_data, data_representation, true);
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_src_out_arr : t_dp_sosi_arr(snk_in_arr'range) := snk_in_arr;
begin
for i in v_src_out_arr'range loop
@@ -1459,13 +1485,13 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
begin
return func_dp_stream_reconcat(snk_in_arr, in_w, out_w, nof_data, data_representation, true);
end;
-- Deconcatenate data from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out_arr : t_dp_sosi_arr(nof_streams - 1 downto 0);
begin
@@ -1481,7 +1507,7 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
begin
return src_out_arr(0);
end;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index d1ec55fe6f..adae931402 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
@@ -46,12 +46,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -74,9 +74,17 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0',
+ '0',
+ '0',
+ '0',
+ (others => '0'),
+ '0',
+ '0',
+ (others => '0'),
+ '0'
+ );
------------------------------------------------------------------------------
-- Definitions for eth demux udp
@@ -185,16 +193,16 @@ package eth_pkg is
constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
-- Register mapping functions
- function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
- function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
- function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
- function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
- function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
- function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
- function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
- function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
+ function func_eth_mm_reg_demux ( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
+ function func_eth_mm_reg_demux ( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
+ function func_eth_mm_reg_config ( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
+ function func_eth_mm_reg_config ( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
+ function func_eth_mm_reg_control (mm_reg : std_logic_vector) return t_eth_mm_reg_control;
+ function func_eth_mm_reg_control (mm_reg : t_eth_mm_reg_control) return std_logic_vector;
+ function func_eth_mm_reg_frame ( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
+ function func_eth_mm_reg_frame ( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
+ function func_eth_mm_reg_status ( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
+ function func_eth_mm_reg_status ( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
------------------------------------------------------------------------------
-- Definitions for eth_mm_registers
@@ -223,7 +231,7 @@ end eth_pkg;
package body eth_pkg is
-- Register mapping functions
- function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
+ function func_eth_mm_reg_demux (mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
begin
-- Demux UDP MM registers
@@ -234,7 +242,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_demux;
- function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
+ function func_eth_mm_reg_demux (mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -246,7 +254,7 @@ package body eth_pkg is
end func_eth_mm_reg_demux;
-- MM config register
- function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
+ function func_eth_mm_reg_config (mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
@@ -256,7 +264,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_config;
- function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
+ function func_eth_mm_reg_config (mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -268,7 +276,7 @@ package body eth_pkg is
end func_eth_mm_reg_config;
-- MM control register
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
+ function func_eth_mm_reg_control (mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
@@ -279,7 +287,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
+ function func_eth_mm_reg_control (mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -292,7 +300,7 @@ package body eth_pkg is
end func_eth_mm_reg_control;
-- MM frame register
- function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
+ function func_eth_mm_reg_frame (mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
@@ -308,7 +316,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_frame;
- function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
+ function func_eth_mm_reg_frame (mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -326,7 +334,7 @@ package body eth_pkg is
end func_eth_mm_reg_frame;
-- MM status register
- function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
+ function func_eth_mm_reg_status (mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
@@ -337,7 +345,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
- function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
+ function func_eth_mm_reg_status (mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 2eb92cbc7d..e8bb8d4283 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index 3c94c1901f..274d14a577 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index 3fc6ebb7a2..d49ba9d9fb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
@@ -86,9 +86,11 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -135,13 +137,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
c_network_ip_identification_len + c_network_ip_flags_fragment_len +
c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
c_network_ip_addr_len +
c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -175,11 +177,20 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001",
+ "0001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "001",
+ "0000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ARP Packet
@@ -216,12 +227,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -247,12 +258,17 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001",
+ "0000000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -301,8 +317,13 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- UDP Packet
@@ -327,7 +348,7 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
@@ -348,8 +369,12 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 9469fd2656..cfde8ebf26 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
@@ -165,315 +165,318 @@ package common_pkg is
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ function pow2 (n : natural) return natural; -- = 2**n
+ function ceil_pow2 (n : integer) return natural; -- = 2**n, returns 1 for n<0
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function true_log2 (n : natural) return natural; -- true_log2(n) = log2(n)
+ function ceil_log2 (n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
- function floor_log10(n : natural) return natural;
+ function floor_log10 (n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
+ function is_pow2 (n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function true_log_pow2 (n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio ( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio2 (n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
- function ceil_div( n : unsigned; d: natural) return unsigned;
- function ceil_value( n : unsigned; d: natural) return unsigned;
- function floor_value(n : unsigned; d: natural) return unsigned;
+ function ceil_div ( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_value ( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
+ function floor_value (n, d : natural) return natural; -- floor_value = (n/d) * d
+ function ceil_div ( n : unsigned; d: natural) return unsigned;
+ function ceil_value ( n : unsigned; d: natural) return unsigned;
+ function floor_value (n : unsigned; d: natural) return unsigned;
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+ function slv (n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
+ function sl ( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
- function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
- function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr;
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr;
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr;
+ function to_slv_32_arr ( n : t_integer_arr) return t_slv_32_arr;
+ function to_slv_32_arr ( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_and (slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
+ function vector_or ( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
+ function vector_xor (slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
+ function andv (slv : std_logic_vector) return std_logic; -- alias of vector_and
+ function orv ( slv : std_logic_vector) return std_logic; -- alias of vector_or
+ function xorv (slv : std_logic_vector) return std_logic; -- alias of vector_xor
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
+ function matrix_or ( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
- function smallest(n, m : integer) return integer;
- function smallest(n, m, l : integer) return integer;
- function smallest(n : t_natural_arr) return natural;
+ function smallest (n, m : integer) return integer;
+ function smallest (n, m, l : integer) return integer;
+ function smallest (n : t_natural_arr) return natural;
- function largest(n, m : integer) return integer;
- function largest(n : t_natural_arr) return natural;
+ function largest (n, m : integer) return integer;
+ function largest (n : t_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
- function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
- function func_product(n : t_nat_natural_arr) return natural;
+ function func_sum ( n : t_natural_arr) return natural; -- sum of all elements in array
+ function func_sum ( n : t_nat_natural_arr) return natural;
+ function func_product (n : t_natural_arr) return natural; -- product of all elements in array
+ function func_product (n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
-
- function is_true(a : std_logic) return boolean;
- function is_true(a : std_logic) return natural;
- function is_true(a : boolean) return std_logic;
- function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
-
- function sel_a_b(sel, a, b : boolean) return boolean;
- function sel_a_b(sel, a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : real) return real;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : signed) return signed;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
- function sel_a_b(sel : boolean; a, b : string) return string;
- function sel_a_b(sel : integer; a, b : string) return string;
- function sel_a_b(sel : boolean; a, b : time) return time;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+
+ function is_true (a : std_logic) return boolean;
+ function is_true (a : std_logic) return natural;
+ function is_true (a : boolean) return std_logic;
+ function is_true (a : boolean) return natural;
+ function is_true (a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true (a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+
+ function sel_a_b (sel, a, b : boolean) return boolean;
+ function sel_a_b (sel, a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : real) return real;
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : signed) return signed;
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned;
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
+ function sel_a_b (sel : boolean; a, b : string) return string;
+ function sel_a_b (sel : integer; a, b : string) return string;
+ function sel_a_b (sel : boolean; a, b : time) return time;
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
- function array_init(init, nof, incr : natural) return t_nat_natural_arr;
- function array_init(init, nof, incr : integer) return t_slv_16_arr;
- function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
-
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ function sel_n (sel : natural; a, b, c : boolean) return boolean; -- 3
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
+
+ function sel_n (sel : natural; a, b, c : integer) return integer; -- 3
+ function sel_n (sel : natural; a, b, c, d : integer) return integer; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
+
+ function sel_n (sel : natural; a, b : string) return string; -- 2
+ function sel_n (sel : natural; a, b, c : string) return string; -- 3
+ function sel_n (sel : natural; a, b, c, d : string) return string; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : string) return string; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr;
+ function array_init (init, nof, incr : integer) return t_slv_16_arr;
+ function array_init (init, nof, incr : integer) return t_slv_32_arr;
+ function array_init (init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init (init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_sinit (init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
-
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
- function TO_SINT(vec : std_logic_vector) return integer;
-
- function TO_UVEC(dec, w : natural) return std_logic_vector;
- function TO_SVEC(dec, w : integer) return std_logic_vector;
-
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
-
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+
+ function TO_UINT (vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_SINT (vec : std_logic_vector) return integer;
+
+ function TO_UVEC (dec, w : natural) return std_logic_vector;
+ function TO_SVEC (dec, w : integer) return std_logic_vector;
+
+ function TO_SVEC_32 (dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
-- happens for RESIZE of UNSIGNED. Therefor this is what the RESIZE_NUM for SIGNED and the RESIZE_SVEC do
-- and better not use RESIZE for SIGNED anymore.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
-
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
-
- function offset_binary(a : std_logic_vector) return std_logic_vector;
-
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
- function flip(a : t_slv_32_arr) return t_slv_32_arr;
- function flip(a : t_integer_arr) return t_integer_arr;
- function flip(a : t_natural_arr) return t_natural_arr;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
-
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
-
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
-
- function pad(str: string; width: natural; pad_char: character) return string;
-
- function slice_up(str: string; width: natural; i: natural) return string;
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string;
- function slice_dn(str: string; width: natural; i: natural) return string;
-
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
+ function RESIZE_NUM ( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM ( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
+ function RESIZE_UINT (u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
+ function RESIZE_SINT (s : integer; w : natural) return integer; -- extend sign bit or keep LS part
+
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector;
+ -- Used in common_add_sub.vhd
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+
+ function offset_binary (a : std_logic_vector) return std_logic_vector;
+
+ function truncate ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function scale ( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
+ function scale_and_resize_uvec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_svec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function truncate_or_resize_uvec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_svec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
+
+ function s_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round_up (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up (vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
+ function u_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
+ function u_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
+
+ function u_to_s (u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function s_to_u (s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+
+ function u_wrap (u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function s_wrap (s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+
+ function u_clip (u : natural; max : natural) return natural; -- if s < max return s, else return n
+ function s_clip (s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip (s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
+
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
+ function hton (a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh (a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+
+ function flip (a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
+ function flip (a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip (a : t_slv_32_arr) return t_slv_32_arr;
+ function flip (a : t_integer_arr) return t_integer_arr;
+ function flip (a : t_natural_arr) return t_natural_arr;
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr;
+
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
+
+ function pad (str: string; width: natural; pad_char: character) return string;
+
+ function slice_up (str: string; width: natural; i: natural) return string;
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string;
+ function slice_dn (str: string; width: natural; i: natural) return string;
+
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
------------------------------------------------------------------------------
-- Component specific functions
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
- function func_common_reorder2_is_there(I, J : natural) return boolean;
- function func_common_reorder2_is_active(I, J, N : natural) return boolean;
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer;
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural;
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
+ function func_common_reorder2_is_there (I, J : natural) return boolean;
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean;
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer;
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural;
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
- function pow2(n : natural) return natural is
+ function pow2 (n : natural) return natural is
begin
return 2**n;
end;
- function ceil_pow2(n : integer) return natural is
+ function ceil_pow2 (n : integer) return natural is
-- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
- function true_log2(n : natural) return natural is
+ function true_log2 (n : natural) return natural is
-- Purpose: For calculating extra vector width of existing vector
-- Description: Return mathematical ceil(log2(n))
-- n log2()
@@ -492,7 +495,7 @@ package body common_pkg is
return natural(integer(ceil(log2(real(n)))));
end;
- function ceil_log2(n : natural) return natural is
+ function ceil_log2 (n : natural) return natural is
-- Purpose: For calculating vector width of new vector
-- Description:
-- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
@@ -510,22 +513,22 @@ package body common_pkg is
end if;
end;
- function floor_log10(n : natural) return natural is
+ function floor_log10 (n : natural) return natural is
begin
return natural(integer(floor(log10(real(n)))));
end;
- function is_pow2(n : natural) return boolean is
+ function is_pow2 (n : natural) return boolean is
begin
return n = 2**true_log2(n);
end;
- function true_log_pow2(n : natural) return natural is
+ function true_log_pow2 (n : natural) return natural is
begin
return 2**true_log2(n);
end;
- function ratio(n, d : natural) return natural is
+ function ratio (n, d : natural) return natural is
begin
if n mod d = 0 then
return n / d;
@@ -534,32 +537,32 @@ package body common_pkg is
end if;
end;
- function ratio2(n, m : natural) return natural is
+ function ratio2 (n, m : natural) return natural is
begin
return largest(ratio(n,m), ratio(m,n));
end;
- function ceil_div(n, d : natural) return natural is
+ function ceil_div (n, d : natural) return natural is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
- function ceil_value(n, d : natural) return natural is
+ function ceil_value (n, d : natural) return natural is
begin
return ceil_div(n, d) * d;
end;
- function floor_value(n, d : natural) return natural is
+ function floor_value (n, d : natural) return natural is
begin
return (n / d) * d;
end;
- function ceil_div(n : unsigned; d: natural) return unsigned is
+ function ceil_div (n : unsigned; d: natural) return unsigned is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
end;
- function ceil_value(n : unsigned; d: natural) return unsigned is
+ function ceil_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -567,7 +570,7 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function floor_value(n : unsigned; d: natural) return unsigned is
+ function floor_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -575,21 +578,21 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function slv(n: in std_logic) return std_logic_vector is
+ function slv (n: in std_logic) return std_logic_vector is
variable r : std_logic_vector(0 downto 0);
begin
r(0) := n;
return r;
end;
- function sl(n: in std_logic_vector) return std_logic is
+ function sl (n: in std_logic_vector) return std_logic is
variable r : std_logic;
begin
r := n(n'low);
return r;
end;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr is
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -607,7 +610,7 @@ package body common_pkg is
return vR;
end;
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr is
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr is
variable vN : t_nat_natural_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -618,7 +621,7 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_integer_arr(n'length - 1 downto 0);
begin
@@ -629,14 +632,14 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return to_integer_arr(vN);
end;
- function to_slv_32_arr(n : t_integer_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_integer_arr) return t_slv_32_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -647,7 +650,7 @@ package body common_pkg is
return vR;
end;
- function to_slv_32_arr(n : t_natural_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_natural_arr) return t_slv_32_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -658,7 +661,7 @@ package body common_pkg is
return vR;
end;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic is
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic is
-- Linear loop to determine result takes combinatorial delay that is proportional to slv'LENGTH:
-- FOR I IN slv'RANGE LOOP
-- v_result := v_result OPERATION slv(I);
@@ -691,22 +694,22 @@ package body common_pkg is
return v_stage_arr(c_nof_stages - 1)(0);
end;
- function vector_and(slv : std_logic_vector) return std_logic is
+ function vector_and (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function vector_or(slv : std_logic_vector) return std_logic is
+ function vector_or (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function vector_xor(slv : std_logic_vector) return std_logic is
+ function vector_xor (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector is
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector is
variable v_one_hot : boolean := false;
variable v_zeros : std_logic_vector(slv'range) := (others => '0');
begin
@@ -725,22 +728,22 @@ package body common_pkg is
return slv;
end;
- function andv(slv : std_logic_vector) return std_logic is
+ function andv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function orv(slv : std_logic_vector) return std_logic is
+ function orv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function xorv(slv : std_logic_vector) return std_logic is
+ function xorv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '1';
begin
@@ -752,7 +755,7 @@ package body common_pkg is
return v_result;
end;
- function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_or (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '0';
begin
@@ -764,7 +767,7 @@ package body common_pkg is
return v_result;
end;
- function smallest(n, m : integer) return integer is
+ function smallest (n, m : integer) return integer is
begin
if n < m then
return n;
@@ -773,16 +776,16 @@ package body common_pkg is
end if;
end;
- function smallest(n, m, l : integer) return integer is
+ function smallest (n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
end;
- function smallest(n : t_natural_arr) return natural is
+ function smallest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -793,7 +796,7 @@ package body common_pkg is
return m;
end;
- function largest(n, m : integer) return integer is
+ function largest (n, m : integer) return integer is
begin
if n > m then
return n;
@@ -802,7 +805,7 @@ package body common_pkg is
end if;
end;
- function largest(n : t_natural_arr) return natural is
+ function largest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -813,7 +816,7 @@ package body common_pkg is
return m;
end;
- function func_sum(n : t_natural_arr) return natural is
+ function func_sum (n : t_natural_arr) return natural is
variable vS : natural;
begin
vS := 0;
@@ -823,14 +826,14 @@ package body common_pkg is
return vS;
end;
- function func_sum(n : t_nat_natural_arr) return natural is
+ function func_sum (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return func_sum(vN);
end;
- function func_product(n : t_natural_arr) return natural is
+ function func_product (n : t_natural_arr) return natural is
variable vP : natural;
begin
vP := 1;
@@ -840,7 +843,7 @@ package body common_pkg is
return vP;
end;
- function func_product(n : t_nat_natural_arr) return natural is
+ function func_product (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
@@ -999,14 +1002,14 @@ package body common_pkg is
return vP;
end;
- function is_true(a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
- function is_true(a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
- function is_true(a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
- function is_true(a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
- function is_true(a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
- function is_true(a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
+ function is_true (a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
+ function is_true (a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
+ function is_true (a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
+ function is_true (a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
+ function is_true (a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
+ function is_true (a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
- function sel_a_b(sel, a, b : integer) return integer is
+ function sel_a_b (sel, a, b : integer) return integer is
begin
if sel /= 0 then
return a;
@@ -1015,7 +1018,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel, a, b : boolean) return boolean is
+ function sel_a_b (sel, a, b : boolean) return boolean is
begin
if sel = true then
return a;
@@ -1024,7 +1027,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : integer) return integer is
+ function sel_a_b (sel : boolean; a, b : integer) return integer is
begin
if sel = true then
return a;
@@ -1033,7 +1036,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : real) return real is
+ function sel_a_b (sel : boolean; a, b : real) return real is
begin
if sel = true then
return a;
@@ -1042,7 +1045,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic is
begin
if sel = true then
return a;
@@ -1051,7 +1054,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic is
begin
if sel /= 0 then
return a;
@@ -1060,7 +1063,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector is
begin
if sel /= 0 then
return a;
@@ -1069,7 +1072,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
if sel = true then
return a;
@@ -1078,7 +1081,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : signed) return signed is
+ function sel_a_b (sel : boolean; a, b : signed) return signed is
begin
if sel = true then
return a;
@@ -1087,7 +1090,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned is
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned is
begin
if sel = true then
return a;
@@ -1096,7 +1099,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr is
begin
if sel = true then
return a;
@@ -1105,7 +1108,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr is
begin
if sel = true then
return a;
@@ -1114,7 +1117,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
begin
if sel = true then
return a;
@@ -1123,7 +1126,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
begin
if sel = true then
return a;
@@ -1132,7 +1135,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : string) return string is
+ function sel_a_b (sel : boolean; a, b : string) return string is
begin
if sel = true then
return a;
@@ -1141,7 +1144,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : string) return string is
+ function sel_a_b (sel : integer; a, b : string) return string is
begin
if sel /= 0 then
return a;
@@ -1150,7 +1153,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : time) return time is
+ function sel_a_b (sel : boolean; a, b : time) return time is
begin
if sel = true then
return a;
@@ -1159,7 +1162,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level is
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level is
begin
if sel = true then
return a;
@@ -1169,115 +1172,115 @@ package body common_pkg is
end;
-- sel_n : boolean
- function sel_n(sel : natural; a, b, c : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : integer
- function sel_n(sel : natural; a, b, c : integer) return integer is
+ function sel_n (sel : natural; a, b, c : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : string
- function sel_n(sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
- function sel_n(sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
- function sel_n(sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
- function sel_n(sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector is
+ function sel_n (sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
+ function sel_n (sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
+ function sel_n (sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector is
variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1286,7 +1289,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_natural_arr is
+ function array_init (init, nof : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1295,7 +1298,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_nat_natural_arr is
+ function array_init (init, nof : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1304,7 +1307,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_natural_arr is
+ function array_init (init, nof, incr : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1316,7 +1319,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_nat_natural_arr is
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1328,7 +1331,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_16_arr is
+ function array_init (init, nof, incr : integer) return t_slv_16_arr is
variable v_arr : t_slv_16_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1340,7 +1343,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_32_arr is
+ function array_init (init, nof, incr : integer) return t_slv_32_arr is
variable v_arr : t_slv_32_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1352,7 +1355,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width : natural) return std_logic_vector is
+ function array_init (init, nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1361,7 +1364,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width, incr : natural) return std_logic_vector is
+ function array_init (init, nof, width, incr : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
variable v_i : natural;
begin
@@ -1373,7 +1376,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
+ function array_sinit (init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1382,7 +1385,7 @@ package body common_pkg is
return v_arr;
end;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix is
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix is
variable v_mat : t_slv_64_matrix(nof_a - 1 downto 0, nof_b - 1 downto 0);
begin
for I in 0 to nof_a - 1 loop
@@ -1395,7 +1398,7 @@ package body common_pkg is
-- Support concatenation of up to 7 slv into 1 slv
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length;
variable v_res : std_logic_vector(c_max_w - 1 downto 0) := (others => '0');
variable v_len : natural := 0;
@@ -1410,32 +1413,32 @@ package body common_pkg is
return v_res(v_len - 1 downto 0);
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, false, a, b, c, d, e, f, "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, false, false, a, b, c, d, e, "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, false, false, false, a, b, c, d, "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, false, false, false, false, a, b, c, "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, false, false, false, false, false, a, b, "0", "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
variable v_len : natural := 0;
begin
if use_a = true then v_len := v_len + a_w; end if;
@@ -1448,33 +1451,33 @@ package body common_pkg is
return v_len;
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, false, a_w, b_w, c_w, d_w, e_w, f_w, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0);
end func_slv_concat_w;
-- extract slv
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
variable v_w : natural := 0;
variable v_lo : natural := 0;
begin
@@ -1520,64 +1523,64 @@ package body common_pkg is
return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, false, a_w, b_w, c_w, d_w, e_w, f_w, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function TO_UINT(vec : std_logic_vector) return natural is
+ function TO_UINT (vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
end;
- function TO_SINT(vec : std_logic_vector) return integer is
+ function TO_SINT (vec : std_logic_vector) return integer is
begin
return to_integer(signed(vec));
end;
- function TO_UVEC(dec, w : natural) return std_logic_vector is
+ function TO_UVEC (dec, w : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(dec, w));
end;
- function TO_SVEC(dec, w : integer) return std_logic_vector is
+ function TO_SVEC (dec, w : integer) return std_logic_vector is
begin
return std_logic_vector(to_signed(dec, w));
end;
- function TO_SVEC_32(dec : integer) return std_logic_vector is
+ function TO_SVEC_32 (dec : integer) return std_logic_vector is
begin
return TO_SVEC(dec, 32);
end;
- function RESIZE_NUM(u : unsigned; w : natural) return unsigned is
+ function RESIZE_NUM (u : unsigned; w : natural) return unsigned is
begin
-- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
return resize(u, w);
end;
- function RESIZE_NUM(s : signed; w : natural) return signed is
+ function RESIZE_NUM (s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
if w > s'length then
@@ -1587,47 +1590,47 @@ package body common_pkg is
end if;
end;
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector is
variable v_slv0 : std_logic_vector(w - 1 downto 1) := (others => '0');
begin
return v_slv0 & sl;
end;
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(vec), w));
end;
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(vec), w));
end;
- function RESIZE_UINT(u : integer; w : natural) return integer is
+ function RESIZE_UINT (u : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_UVEC(u, c_word_w);
return TO_UINT(v(w - 1 downto 0));
end;
- function RESIZE_SINT(s : integer; w : natural) return integer is
+ function RESIZE_SINT (s : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_SVEC(s, c_word_w);
return TO_SINT(v(w - 1 downto 0));
end;
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, 32);
end;
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, 32);
end;
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
if dec < 0 then
@@ -1639,74 +1642,74 @@ package body common_pkg is
end if;
end;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector is
begin
return std_logic_vector(unsigned(vec) + dec);
end;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
return std_logic_vector(signed(vec) + v_dec); -- uses function "+" (L : SIGNED, R : INTEGER)
end;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector is
begin
return std_logic_vector(signed(vec) + dec);
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) + signed(r_vec));
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) - signed(r_vec));
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) + unsigned(r_vec));
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_SVEC(l_vec, r_vec, l_vec'length);
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_UVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_UVEC(l_vec, r_vec, l_vec'length);
end;
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_re * b_re - a_im * b_im);
end;
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_im * b_re + a_re * b_im);
end;
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
@@ -1715,7 +1718,7 @@ package body common_pkg is
end if;
end;
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
@@ -1741,24 +1744,24 @@ package body common_pkg is
-- The offset_binary() mapping can be done and undone both ways.
-- The offset_binary() mapping to two-complement binary yields a DC offset
-- of -0.5 Lsb.
- function offset_binary(a : std_logic_vector) return std_logic_vector is
+ function offset_binary (a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
- function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function truncate (vec : std_logic_vector; n : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -1769,7 +1772,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -1780,7 +1783,7 @@ package body common_pkg is
return v_res;
end;
- function scale(vec : std_logic_vector; n: natural) return std_logic_vector is
+ function scale (vec : std_logic_vector; n: natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1789,7 +1792,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1800,7 +1803,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1811,7 +1814,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_uvec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_uvec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -1824,7 +1827,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_svec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_svec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -1856,7 +1859,7 @@ package body common_pkg is
-- maximum product is -8*-8=+64 <= 127-8, so wrapping due to rounding
-- overflow will never occur.
- function s_round(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
-- Use SIGNED to avoid NATURAL (32 bit range) overflow error
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
@@ -1884,24 +1887,24 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return s_round(vec, n, false); -- no round clip
end;
-- An alternative is to always round up, also for negative numbers (i.e. s_round_up = u_round).
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round_up (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
begin
return u_round(vec, n, clip);
end;
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round_up (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
-- Unsigned numbers are round up (almost same as s_round, but without the else on negative vec)
- function u_round(vec : std_logic_vector; n : natural; clip : boolean ) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural; clip : boolean ) return std_logic_vector is
-- Use UNSIGNED to avoid NATURAL (32 bit range) overflow error
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
@@ -1925,36 +1928,36 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
- function u_to_s(u : natural; w : natural) return integer is
+ function u_to_s (u : natural; w : natural) return integer is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
- function s_to_u(s : integer; w : natural) return natural is
+ function s_to_u (s : integer; w : natural) return natural is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
- function u_wrap(u : natural; w : natural) return natural is
+ function u_wrap (u : natural; w : natural) return natural is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
- function s_wrap(s : integer; w : natural) return integer is
+ function s_wrap (s : integer; w : natural) return integer is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
- function u_clip(u : natural; max : natural) return natural is
+ function u_clip (u : natural; max : natural) return natural is
begin
if u > max then
return max;
@@ -1963,7 +1966,7 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural; min : integer) return integer is
+ function s_clip (s : integer; max : natural; min : integer) return integer is
begin
if s < min then
return min;
@@ -1976,12 +1979,12 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural) return integer is
+ function s_clip (s : integer; max : natural) return integer is
begin
return s_clip(s, max, -max);
end;
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
variable vL : natural;
@@ -1997,28 +2000,28 @@ package body common_pkg is
return v_b;
end function;
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
end function;
- function hton(a : std_logic_vector) return std_logic_vector is
+ function hton (a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
end function;
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, sz); -- i.e. ntoh() = hton()
end function;
- function ntoh(a : std_logic_vector) return std_logic_vector is
+ function ntoh (a : std_logic_vector) return std_logic_vector is
begin
return hton(a); -- i.e. ntoh() = hton()
end function;
- function flip(a : std_logic_vector) return std_logic_vector is
+ function flip (a : std_logic_vector) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2028,12 +2031,12 @@ package body common_pkg is
return v_b;
end;
- function flip(a, w : natural) return natural is
+ function flip (a, w : natural) return natural is
begin
return TO_UINT(flip(TO_UVEC(a, w)));
end;
- function flip(a : t_slv_32_arr) return t_slv_32_arr is
+ function flip (a : t_slv_32_arr) return t_slv_32_arr is
variable v_a : t_slv_32_arr(a'length - 1 downto 0) := a;
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
@@ -2043,7 +2046,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_integer_arr) return t_integer_arr is
+ function flip (a : t_integer_arr) return t_integer_arr is
variable v_a : t_integer_arr(a'length - 1 downto 0) := a;
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
@@ -2053,7 +2056,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_natural_arr) return t_natural_arr is
+ function flip (a : t_natural_arr) return t_natural_arr is
variable v_a : t_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
@@ -2063,7 +2066,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr is
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr is
variable v_a : t_nat_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
@@ -2073,7 +2076,7 @@ package body common_pkg is
return v_b;
end;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector is
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2087,7 +2090,7 @@ package body common_pkg is
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
variable vI : natural;
variable vJ : natural;
begin
@@ -2096,7 +2099,7 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
@@ -2111,34 +2114,34 @@ package body common_pkg is
end loop;
end;
- function pad(str: string; width: natural; pad_char: character) return string is
+ function pad (str: string; width: natural; pad_char: character) return string is
variable v_str : string(1 to width) := (others => pad_char);
begin
v_str(width - str'length + 1 to width) := str;
return v_str;
end;
- function slice_up(str: string; width: natural; i: natural) return string is
+ function slice_up (str: string; width: natural; i: natural) return string is
begin
return str(i * width + 1 to (i + 1) * width);
end;
-- If the input value is not a multiple of the desired width, the return value is padded with
-- the passed pad value. E.g. if input='10' and desired width is 4, return value is '0010'.
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string is
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
- function slice_dn(str: string; width: natural; i: natural) return string is
+ function slice_dn (str: string; width: natural; i: natural) return string is
begin
return str((i + 1) * width - 1 downto i * width);
end;
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
for i in 0 to nof_elements - 1 loop
@@ -2152,16 +2155,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2174,7 +2178,7 @@ package body common_pkg is
assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
- --synthesis translate_on
+ --synthesis translate_on
end procedure proc_common_fifo_asserts;
@@ -2182,8 +2186,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2204,7 +2209,7 @@ package body common_pkg is
------------------------------------------------------------------------------
-- Determine whether the stage I and row J index refer to any (active or redundant) 2-input reorder cell instantiation
- function func_common_reorder2_is_there(I, J : natural) return boolean is
+ function func_common_reorder2_is_there (I, J : natural) return boolean is
variable v_odd : boolean;
variable v_even : boolean;
begin
@@ -2214,7 +2219,7 @@ package body common_pkg is
end func_common_reorder2_is_there;
-- Determine whether the stage I and row J index refer to an active 2-input reorder cell instantiation in a reorder network with N stages
- function func_common_reorder2_is_active(I, J, N : natural) return boolean is
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean is
variable v_inst : boolean;
variable v_act : boolean;
begin
@@ -2224,7 +2229,7 @@ package body common_pkg is
end func_common_reorder2_is_active;
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer is
constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
@@ -2246,7 +2251,7 @@ package body common_pkg is
end func_common_reorder2_get_select_index;
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -2261,7 +2266,7 @@ package body common_pkg is
end func_common_reorder2_get_select;
-- Determine the inverse of a reorder network by using two reorder networks in series
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -2287,8 +2292,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2327,9 +2332,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
@@ -2354,7 +2360,7 @@ package body common_pkg is
end if;
wait for v_speriod / 2;
SCLK <= '1';
- -- Wait for next DCLK
+ -- Wait for next DCLK
end loop;
wait;
end proc_common_dclk_generate_sclk;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 40128fea21..0fa106e866 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
@@ -121,15 +121,33 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_bsn_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ '1',
+ '1',
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_empty_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_channel_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_error_w)
+ );
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -208,30 +226,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -240,142 +262,142 @@ package dp_stream_pkg is
-- Typically the sosi data are treated as unsigned in the record field, so extended with '0'. However for interpretating
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
- function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
- function TO_DP_EMPTY( n : natural) return std_logic_vector;
- function TO_DP_CHANNEL( n : natural) return std_logic_vector;
- function TO_DP_ERROR( n : natural) return std_logic_vector;
- function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
- function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
-
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
-
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
-
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
+ function TO_DP_BSN ( n : natural) return std_logic_vector;
+ function TO_DP_DATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_SDATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
+ function TO_DP_UDATA ( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector; -- for re and im fields, signed data
+ function TO_DP_DSP_UDATA (n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_EMPTY ( n : natural) return std_logic_vector;
+ function TO_DP_CHANNEL ( n : natural) return std_logic_vector;
+ function TO_DP_ERROR ( n : natural) return std_logic_vector;
+ function RESIZE_DP_BSN ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_DATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
+ function RESIZE_DP_SDATA ( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
+ function RESIZE_DP_XDATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_EMPTY ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_CHANNEL ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_ERROR ( vec : std_logic_vector) return std_logic_vector;
+
+ function INCR_DP_DATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
+ function INCR_DP_SDATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+
+ function REPLICATE_DP_DATA ( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
-- Shift and combine part of previous data and this data, use the other sosi from prev_sosi
- function func_dp_data_shift( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
+ function func_dp_data_shift ( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
+ function func_dp_data_shift_last ( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
-- Determine resulting empty if two streams are concatenated or split
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi;
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi;
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; str : string) return std_logic;
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector;
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
-- Fix reversed buses due to connecting TO to DOWNTO range arrays.
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr;
-- Functions to combinatorially hold the data fields and to set or reset the control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_info( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_control( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_reset_control( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_info ( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_control ( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reset_control ( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
-- Reset sosi ctrl and preserve the sosi data (to avoid unnecessary data toggling and to ease data view in Wave window)
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
-- Function to copy the BSN of one valid stream to all output streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
-- Functions to combinatorially handle the BSN field
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
-- Functions to combine sosi fields
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi;
-- Functions to convert sosi fields
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
-- Functions to set the DATA, RE and IM field in a stream.
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
-
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
-
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
+
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -384,14 +406,14 @@ package dp_stream_pkg is
-- . data_order_im_re = TRUE then "COMPLEX" data = im&re
-- FALSE then "COMPLEX" data = re&im
-- ignore when data_representation /= "COMPLEX"
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
end dp_stream_pkg;
@@ -399,11 +421,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -417,20 +440,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -448,118 +473,119 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
- function TO_DP_BSN(n : natural) return std_logic_vector is
+ function TO_DP_BSN (n : natural) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_bsn_w);
end TO_DP_BSN;
- function TO_DP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_DATA;
- function TO_DP_SDATA(n : integer) return std_logic_vector is
+ function TO_DP_SDATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_SDATA;
- function TO_DP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_UDATA (n : integer) return std_logic_vector is
begin
return TO_DP_DATA(n);
end TO_DP_UDATA;
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_DATA;
- function TO_DP_DSP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_UDATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_UDATA;
- function TO_DP_EMPTY(n : natural) return std_logic_vector is
+ function TO_DP_EMPTY (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_empty_w);
end TO_DP_EMPTY;
- function TO_DP_CHANNEL(n : natural) return std_logic_vector is
+ function TO_DP_CHANNEL (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_channel_w);
end TO_DP_CHANNEL;
- function TO_DP_ERROR(n : natural) return std_logic_vector is
+ function TO_DP_ERROR (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_error_w);
end TO_DP_ERROR;
- function RESIZE_DP_BSN(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_BSN (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_bsn_w);
end RESIZE_DP_BSN;
- function RESIZE_DP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_DATA;
- function RESIZE_DP_SDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_SDATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_SDATA;
- function RESIZE_DP_XDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_XDATA (vec : std_logic_vector) return std_logic_vector is
variable v_vec : std_logic_vector(c_dp_stream_data_w - 1 downto 0) := (others => 'X');
begin
v_vec(vec'length - 1 downto 0) := vec;
return v_vec;
end RESIZE_DP_XDATA;
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_dsp_data_w);
end RESIZE_DP_DSP_DATA;
- function RESIZE_DP_EMPTY(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_EMPTY (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_empty_w);
end RESIZE_DP_EMPTY;
- function RESIZE_DP_CHANNEL(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_CHANNEL (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_channel_w);
end RESIZE_DP_CHANNEL;
- function RESIZE_DP_ERROR(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_ERROR (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_error_w);
end RESIZE_DP_ERROR;
- function INCR_DP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DATA(std_logic_vector(unsigned(vec(w - 1 downto 0)) + dec));
end INCR_DP_DATA;
- function INCR_DP_SDATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_SDATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_SDATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_SDATA;
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DSP_DATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_DSP_DATA;
- function REPLICATE_DP_DATA(seq : std_logic_vector) return std_logic_vector is
+ function REPLICATE_DP_DATA (seq : std_logic_vector) return std_logic_vector is
constant c_seq_w : natural := seq'length;
constant c_nof_replications : natural := ceil_div(c_dp_stream_data_w, c_seq_w);
constant c_vec_w : natural := ceil_value(c_dp_stream_data_w, c_seq_w);
@@ -571,7 +597,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
@@ -590,7 +616,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -608,7 +634,7 @@ package body dp_stream_pkg is
end TO_DP_SOSI_UNSIGNED;
-- Keep part of head data and combine part of tail data
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
@@ -625,7 +651,7 @@ package body dp_stream_pkg is
-- Shift and combine part of previous data and this data,
- function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
+ function func_dp_data_shift (prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
@@ -658,7 +684,7 @@ package body dp_stream_pkg is
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
+ function func_dp_data_shift_last (tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
variable vL : natural := input_empty;
variable vN : natural := nof_symbols_per_data;
@@ -688,7 +714,7 @@ package body dp_stream_pkg is
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(head_empty);
@@ -700,7 +726,7 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_concat;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(input_empty);
@@ -715,7 +741,7 @@ package body dp_stream_pkg is
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
begin
for I in dp'range loop
@@ -729,7 +755,7 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -751,7 +777,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -775,19 +801,19 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -809,7 +835,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -833,13 +859,13 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
@@ -847,7 +873,7 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -860,7 +886,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -875,19 +901,19 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -899,7 +925,7 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -915,7 +941,7 @@ package body dp_stream_pkg is
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -928,7 +954,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -941,7 +967,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -954,7 +980,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -967,7 +993,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -980,7 +1006,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -993,7 +1019,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1006,7 +1032,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1019,7 +1045,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr is
variable v_to_range : t_dp_siso_arr(0 to in_arr'high);
variable v_downto_range : t_dp_siso_arr(in_arr'high downto 0);
begin
@@ -1036,7 +1062,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_reverse_range;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_to_range : t_dp_sosi_arr(0 to in_arr'high);
variable v_downto_range : t_dp_sosi_arr(in_arr'high downto 0);
begin
@@ -1054,7 +1080,7 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reverse_range;
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
@@ -1062,7 +1088,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
- function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_info (dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi info
@@ -1074,7 +1100,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_info;
- function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_control (dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi control
@@ -1086,7 +1112,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_control;
- function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reset_control (dp : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- reset sosi control
@@ -1098,7 +1124,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_reset_control;
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp; -- hold sosi data
begin
-- reset sosi control
@@ -1110,7 +1136,7 @@ package body dp_stream_pkg is
end func_dp_stream_reset_control;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
begin
for I in dp'range loop
@@ -1123,13 +1149,13 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_max(dp, c_mask, w);
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
begin
for I in dp'range loop
@@ -1142,14 +1168,14 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_min;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_min(dp, c_mask, w);
end func_dp_stream_arr_bsn_min;
-- Function to copy the BSN number of one valid stream to all other streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
@@ -1166,14 +1192,14 @@ package body dp_stream_pkg is
-- Functions to combinatorially handle channels
- function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.channel := TO_UVEC(ch, c_dp_stream_channel_w);
return v_rec;
end func_dp_stream_channel_set;
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) /= ch then
@@ -1184,7 +1210,7 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_select;
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) = ch then
@@ -1196,7 +1222,7 @@ package body dp_stream_pkg is
end func_dp_stream_channel_remove;
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.err := TO_UVEC(n, c_dp_stream_error_w);
@@ -1204,7 +1230,7 @@ package body dp_stream_pkg is
end func_dp_stream_error_set;
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.bsn := RESIZE_DP_BSN(bsn);
@@ -1212,7 +1238,7 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
-- Combine sosi data with the sosi info fields
@@ -1225,7 +1251,7 @@ package body dp_stream_pkg is
end func_dp_stream_combine_info_and_data;
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
@@ -1242,23 +1268,23 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_slv_to_integer;
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1267,7 +1293,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1278,8 +1304,8 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_re : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1300,17 +1326,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_hi : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1333,17 +1359,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, 1, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1352,17 +1378,17 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1371,18 +1397,18 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, 1, true);
end;
-- Concatenate the data (and complex fields) from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out : t_dp_sosi := snk_in_arr(0);
begin
@@ -1397,7 +1423,7 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1407,7 +1433,7 @@ package body dp_stream_pkg is
end;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_in_w : natural := in_w / 2;
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
@@ -1445,12 +1471,12 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
begin
return func_dp_stream_reconcat(snk_in, in_w, out_w, nof_data, data_representation, true);
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_src_out_arr : t_dp_sosi_arr(snk_in_arr'range) := snk_in_arr;
begin
for i in v_src_out_arr'range loop
@@ -1459,13 +1485,13 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
begin
return func_dp_stream_reconcat(snk_in_arr, in_w, out_w, nof_data, data_representation, true);
end;
-- Deconcatenate data from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out_arr : t_dp_sosi_arr(nof_streams - 1 downto 0);
begin
@@ -1481,7 +1507,7 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
begin
return src_out_arr(0);
end;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index d1ec55fe6f..adae931402 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
@@ -46,12 +46,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -74,9 +74,17 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0',
+ '0',
+ '0',
+ '0',
+ (others => '0'),
+ '0',
+ '0',
+ (others => '0'),
+ '0'
+ );
------------------------------------------------------------------------------
-- Definitions for eth demux udp
@@ -185,16 +193,16 @@ package eth_pkg is
constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
-- Register mapping functions
- function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
- function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
- function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
- function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
- function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
- function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
- function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
- function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
+ function func_eth_mm_reg_demux ( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
+ function func_eth_mm_reg_demux ( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
+ function func_eth_mm_reg_config ( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
+ function func_eth_mm_reg_config ( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
+ function func_eth_mm_reg_control (mm_reg : std_logic_vector) return t_eth_mm_reg_control;
+ function func_eth_mm_reg_control (mm_reg : t_eth_mm_reg_control) return std_logic_vector;
+ function func_eth_mm_reg_frame ( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
+ function func_eth_mm_reg_frame ( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
+ function func_eth_mm_reg_status ( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
+ function func_eth_mm_reg_status ( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
------------------------------------------------------------------------------
-- Definitions for eth_mm_registers
@@ -223,7 +231,7 @@ end eth_pkg;
package body eth_pkg is
-- Register mapping functions
- function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
+ function func_eth_mm_reg_demux (mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
begin
-- Demux UDP MM registers
@@ -234,7 +242,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_demux;
- function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
+ function func_eth_mm_reg_demux (mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -246,7 +254,7 @@ package body eth_pkg is
end func_eth_mm_reg_demux;
-- MM config register
- function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
+ function func_eth_mm_reg_config (mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
@@ -256,7 +264,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_config;
- function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
+ function func_eth_mm_reg_config (mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -268,7 +276,7 @@ package body eth_pkg is
end func_eth_mm_reg_config;
-- MM control register
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
+ function func_eth_mm_reg_control (mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
@@ -279,7 +287,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
+ function func_eth_mm_reg_control (mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -292,7 +300,7 @@ package body eth_pkg is
end func_eth_mm_reg_control;
-- MM frame register
- function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
+ function func_eth_mm_reg_frame (mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
@@ -308,7 +316,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_frame;
- function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
+ function func_eth_mm_reg_frame (mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -326,7 +334,7 @@ package body eth_pkg is
end func_eth_mm_reg_frame;
-- MM status register
- function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
+ function func_eth_mm_reg_status (mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
@@ -337,7 +345,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
- function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
+ function func_eth_mm_reg_status (mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 2eb92cbc7d..e8bb8d4283 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 5508d1789d..49cec362a2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_avs_eth_0 is
+ component qsys_unb2b_minimal_avs_eth_0 is
port (
coe_clk_export : out std_logic; -- export
ins_interrupt_irq : out std_logic; -- irq
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index 69ff39c0a0..f5f9738149 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_clk_0 is
+ component qsys_unb2b_minimal_clk_0 is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 6d24dae5a9..f0ba7ef983 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_cpu_0 is
+ component qsys_unb2b_minimal_cpu_0 is
port (
clk : in std_logic := 'X'; -- clk
dummy_ci_port : out std_logic; -- readra
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index 927069ecd1..fb2dc732db 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_jesd204 is
+ component qsys_unb2b_minimal_jesd204 is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index a169c6edeb..b2603c75cf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -16,32 +16,32 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library std;
-use std.textio.all;
+ use std.textio.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
@@ -49,25 +49,25 @@ architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_18
begin
---synthesis translate_off
- process (clk)
+ --synthesis translate_off
+ process (clk)
variable write_line : line;
- begin
- if clk'event and clk = '1' then
- if std_logic'(fifo_wr) = '1' then
- write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
- write(write_line, string'(""));
- write(output, write_line.all);
- deallocate (write_line);
- end if;
+ begin
+ if clk'event and clk = '1' then
+ if std_logic'(fifo_wr) = '1' then
+ write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
+ write(write_line, string'(""));
+ write(output, write_line.all);
+ deallocate (write_line);
end if;
+ end if;
- end process;
+ end process;
- wfifo_used <= A_REP(std_logic'('0'), 6);
- r_dat <= A_REP(std_logic'('0'), 8);
- fifo_FF <= std_logic'('0');
- wfifo_empty <= std_logic'('1');
+ wfifo_used <= A_REP(std_logic'('0'), 6);
+ r_dat <= A_REP(std_logic'('0'), 8);
+ fifo_FF <= std_logic'('0');
+ wfifo_empty <= std_logic'('1');
--synthesis translate_on
end europa;
@@ -79,85 +79,85 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_FF : std_logic;
- signal internal_r_dat : std_logic_vector(7 downto 0);
- signal internal_wfifo_empty : std_logic;
- signal internal_wfifo_used : std_logic_vector(5 downto 0);
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_FF : std_logic;
+ signal internal_r_dat : std_logic_vector(7 downto 0);
+ signal internal_wfifo_empty : std_logic;
+ signal internal_wfifo_used : std_logic_vector(5 downto 0);
begin
@@ -169,18 +169,18 @@ begin
wfifo_empty <= internal_wfifo_empty;
--vhdl renameroo for output signals
wfifo_used <= internal_wfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
- port map(
- fifo_FF => internal_fifo_FF,
- r_dat => internal_r_dat,
- wfifo_empty => internal_wfifo_empty,
- wfifo_used => internal_wfifo_used,
- clk => clk,
- fifo_wdata => fifo_wdata,
- fifo_wr => fifo_wr
- );
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
+ port map(
+ fifo_FF => internal_fifo_FF,
+ r_dat => internal_r_dat,
+ wfifo_empty => internal_wfifo_empty,
+ wfifo_used => internal_wfifo_used,
+ clk => clk,
+ fifo_wdata => fifo_wdata,
+ fifo_wr => fifo_wr
+ );
--synthesis translate_on
@@ -220,72 +220,72 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- signal bytes_left : std_logic_vector(31 downto 0);
- signal fifo_rd_d : std_logic;
- signal internal_rfifo_full1 : std_logic;
- signal new_rom : std_logic;
- signal num_bytes : std_logic_vector(31 downto 0);
- signal rfifo_entries : std_logic_vector(6 downto 0);
+ signal bytes_left : std_logic_vector(31 downto 0);
+ signal fifo_rd_d : std_logic;
+ signal internal_rfifo_full1 : std_logic;
+ signal new_rom : std_logic;
+ signal num_bytes : std_logic_vector(31 downto 0);
+ signal rfifo_entries : std_logic_vector(6 downto 0);
begin
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
---synthesis translate_off
- -- Generate rfifo_entries for simulation
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- bytes_left <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rd_d <= std_logic'('0');
- elsif clk'event and clk = '1' then
- fifo_rd_d <= fifo_rd;
- -- decrement on read
- if std_logic'(fifo_rd_d) = '1' then
- bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
- end if;
- -- catch new contents
- if std_logic'(new_rom) = '1' then
- bytes_left <= num_bytes;
- end if;
+ --synthesis translate_off
+ -- Generate rfifo_entries for simulation
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ bytes_left <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rd_d <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ fifo_rd_d <= fifo_rd;
+ -- decrement on read
+ if std_logic'(fifo_rd_d) = '1' then
+ bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
end if;
+ -- catch new contents
+ if std_logic'(new_rom) = '1' then
+ bytes_left <= num_bytes;
+ end if;
+ end if;
- end process;
+ end process;
- fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
- internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
- rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
- rfifo_used <= rfifo_entries(5 downto 0);
- new_rom <= std_logic'('0');
- num_bytes <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rdata <= std_logic_vector'("00000000");
+ fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
+ internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
+ rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
+ rfifo_used <= rfifo_entries(5 downto 0);
+ new_rom <= std_logic'('0');
+ num_bytes <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rdata <= std_logic_vector'("00000000");
--synthesis translate_on
end europa;
@@ -297,86 +297,86 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_EF : std_logic;
- signal internal_fifo_rdata : std_logic_vector(7 downto 0);
- signal internal_rfifo_full : std_logic;
- signal internal_rfifo_used : std_logic_vector(5 downto 0);
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_EF : std_logic;
+ signal internal_fifo_rdata : std_logic_vector(7 downto 0);
+ signal internal_rfifo_full : std_logic;
+ signal internal_rfifo_used : std_logic_vector(5 downto 0);
begin
@@ -388,18 +388,18 @@ begin
rfifo_full <= internal_rfifo_full;
--vhdl renameroo for output signals
rfifo_used <= internal_rfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
- port map(
- fifo_EF => internal_fifo_EF,
- fifo_rdata => internal_fifo_rdata,
- rfifo_full => internal_rfifo_full,
- rfifo_used => internal_rfifo_used,
- clk => clk,
- fifo_rd => fifo_rd,
- rst_n => rst_n
- );
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
+ port map(
+ fifo_EF => internal_fifo_EF,
+ fifo_rdata => internal_fifo_rdata,
+ rfifo_full => internal_rfifo_full,
+ rfifo_used => internal_rfifo_used,
+ clk => clk,
+ fifo_rd => fifo_rd,
+ rst_n => rst_n
+ );
--synthesis translate_on
@@ -439,136 +439,136 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
- port (
- -- inputs:
- signal av_address : in std_logic;
- signal av_chipselect : in std_logic;
- signal av_read_n : in std_logic;
- signal av_write_n : in std_logic;
- signal av_writedata : in std_logic_vector(31 downto 0);
- signal clk : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal av_irq : out std_logic;
- signal av_readdata : out std_logic_vector(31 downto 0);
- signal av_waitrequest : out std_logic;
- signal dataavailable : out std_logic;
- signal readyfordata : out std_logic
- );
-attribute ALTERA_ATTRIBUTE : string;
-attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
+ port (
+ -- inputs:
+ signal av_address : in std_logic;
+ signal av_chipselect : in std_logic;
+ signal av_read_n : in std_logic;
+ signal av_write_n : in std_logic;
+ signal av_writedata : in std_logic_vector(31 downto 0);
+ signal clk : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal av_irq : out std_logic;
+ signal av_readdata : out std_logic_vector(31 downto 0);
+ signal av_waitrequest : out std_logic;
+ signal dataavailable : out std_logic;
+ signal readyfordata : out std_logic
+ );
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
-
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
-
---synthesis read_comments_as_HDL on
--- component alt_jtag_atlantic is
---GENERIC (
--- INSTANCE_ID : NATURAL;
--- LOG2_RXFIFO_DEPTH : NATURAL;
--- LOG2_TXFIFO_DEPTH : NATURAL;
--- SLD_AUTO_INSTANCE_INDEX : STRING
--- );
--- PORT (
--- signal t_pause : OUT STD_LOGIC;
--- signal r_ena : OUT STD_LOGIC;
--- signal t_ena : OUT STD_LOGIC;
--- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal t_dav : IN STD_LOGIC;
--- signal rst_n : IN STD_LOGIC;
--- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal r_val : IN STD_LOGIC;
--- signal clk : IN STD_LOGIC
--- );
--- end component alt_jtag_atlantic;
---synthesis read_comments_as_HDL off
- signal ac : std_logic;
- signal activity : std_logic;
- signal fifo_AE : std_logic;
- signal fifo_AF : std_logic;
- signal fifo_EF : std_logic;
- signal fifo_FF : std_logic;
- signal fifo_clear : std_logic;
- signal fifo_rd : std_logic;
- signal fifo_rdata : std_logic_vector(7 downto 0);
- signal fifo_wdata : std_logic_vector(7 downto 0);
- signal fifo_wr : std_logic;
- signal ien_AE : std_logic;
- signal ien_AF : std_logic;
- signal internal_av_waitrequest : std_logic;
- signal ipen_AE : std_logic;
- signal ipen_AF : std_logic;
- signal pause_irq : std_logic;
- signal r_dat : std_logic_vector(7 downto 0);
- signal r_ena : std_logic;
- signal r_val : std_logic;
- signal rd_wfifo : std_logic;
- signal read_0 : std_logic;
- signal rfifo_full : std_logic;
- signal rfifo_used : std_logic_vector(5 downto 0);
- signal rvalid : std_logic;
- signal sim_r_ena : std_logic;
- signal sim_t_dat : std_logic;
- signal sim_t_ena : std_logic;
- signal sim_t_pause : std_logic;
- signal t_dat : std_logic_vector(7 downto 0);
- signal t_dav : std_logic;
- signal t_ena : std_logic;
- signal t_pause : std_logic;
- signal wfifo_empty : std_logic;
- signal wfifo_used : std_logic_vector(5 downto 0);
- signal woverflow : std_logic;
- signal wr_rfifo : std_logic;
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
+
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+
+ --synthesis read_comments_as_HDL on
+ -- component alt_jtag_atlantic is
+ --GENERIC (
+ -- INSTANCE_ID : NATURAL;
+ -- LOG2_RXFIFO_DEPTH : NATURAL;
+ -- LOG2_TXFIFO_DEPTH : NATURAL;
+ -- SLD_AUTO_INSTANCE_INDEX : STRING
+ -- );
+ -- PORT (
+ -- signal t_pause : OUT STD_LOGIC;
+ -- signal r_ena : OUT STD_LOGIC;
+ -- signal t_ena : OUT STD_LOGIC;
+ -- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal t_dav : IN STD_LOGIC;
+ -- signal rst_n : IN STD_LOGIC;
+ -- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal r_val : IN STD_LOGIC;
+ -- signal clk : IN STD_LOGIC
+ -- );
+ -- end component alt_jtag_atlantic;
+ --synthesis read_comments_as_HDL off
+ signal ac : std_logic;
+ signal activity : std_logic;
+ signal fifo_AE : std_logic;
+ signal fifo_AF : std_logic;
+ signal fifo_EF : std_logic;
+ signal fifo_FF : std_logic;
+ signal fifo_clear : std_logic;
+ signal fifo_rd : std_logic;
+ signal fifo_rdata : std_logic_vector(7 downto 0);
+ signal fifo_wdata : std_logic_vector(7 downto 0);
+ signal fifo_wr : std_logic;
+ signal ien_AE : std_logic;
+ signal ien_AF : std_logic;
+ signal internal_av_waitrequest : std_logic;
+ signal ipen_AE : std_logic;
+ signal ipen_AF : std_logic;
+ signal pause_irq : std_logic;
+ signal r_dat : std_logic_vector(7 downto 0);
+ signal r_ena : std_logic;
+ signal r_val : std_logic;
+ signal rd_wfifo : std_logic;
+ signal read_0 : std_logic;
+ signal rfifo_full : std_logic;
+ signal rfifo_used : std_logic_vector(5 downto 0);
+ signal rvalid : std_logic;
+ signal sim_r_ena : std_logic;
+ signal sim_t_dat : std_logic;
+ signal sim_t_ena : std_logic;
+ signal sim_t_pause : std_logic;
+ signal t_dat : std_logic_vector(7 downto 0);
+ signal t_dav : std_logic;
+ signal t_ena : std_logic;
+ signal t_pause : std_logic;
+ signal wfifo_empty : std_logic;
+ signal wfifo_used : std_logic_vector(5 downto 0);
+ signal woverflow : std_logic;
+ signal wr_rfifo : std_logic;
begin
@@ -701,28 +701,28 @@ begin
--vhdl renameroo for output signals
av_waitrequest <= internal_av_waitrequest;
---synthesis translate_off
- -- Tie off Atlantic Interface signals not used for simulation
- process (clk)
- begin
- if clk'event and clk = '1' then
- sim_t_pause <= std_logic'('0');
- sim_t_ena <= std_logic'('0');
- sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
- sim_r_ena <= std_logic'('0');
- end if;
+ --synthesis translate_off
+ -- Tie off Atlantic Interface signals not used for simulation
+ process (clk)
+ begin
+ if clk'event and clk = '1' then
+ sim_t_pause <= std_logic'('0');
+ sim_t_ena <= std_logic'('0');
+ sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
+ sim_r_ena <= std_logic'('0');
+ end if;
- end process;
+ end process;
- r_ena <= sim_r_ena;
- t_ena <= sim_t_ena;
- t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
- t_pause <= sim_t_pause;
- process (fifo_EF)
- begin
- dataavailable <= not fifo_EF;
+ r_ena <= sim_r_ena;
+ t_ena <= sim_t_ena;
+ t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
+ t_pause <= sim_t_pause;
+ process (fifo_EF)
+ begin
+ dataavailable <= not fifo_EF;
- end process;
+ end process;
--synthesis translate_on
--synthesis read_comments_as_HDL on
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index e357a3b8ab..4f7553ed71 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_jtag_uart_0 is
+ component qsys_unb2b_minimal_jtag_uart_0 is
port (
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index c400576a19..c4aec21c6b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -16,69 +16,69 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
- generic (
- INIT_FILE : string := "onchip_memory2_0.hex"
- );
- port (
- -- inputs:
- signal address : in std_logic_vector(14 downto 0);
- signal byteenable : in std_logic_vector(3 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal clken : in std_logic;
- signal freeze : in std_logic;
- signal reset : in std_logic;
- signal reset_req : in std_logic;
- signal write : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ generic (
+ INIT_FILE : string := "onchip_memory2_0.hex"
+ );
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(14 downto 0);
+ signal byteenable : in std_logic_vector(3 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal clken : in std_logic;
+ signal freeze : in std_logic;
+ signal reset : in std_logic;
+ signal reset_req : in std_logic;
+ signal write : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal readdata : out std_logic_vector(31 downto 0)
- );
+ -- outputs:
+ signal readdata : out std_logic_vector(31 downto 0)
+ );
end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
architecture europa of qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
component altsyncram is
-generic (
+ generic (
byte_size : natural;
- init_file : string;
- lpm_type : string;
- maximum_depth : natural;
- numwords_a : natural;
- operation_mode : string;
- outdata_reg_a : string;
- ram_block_type : string;
- read_during_write_mode_mixed_ports : string;
- read_during_write_mode_port_a : string;
- width_a : natural;
- width_byteena_a : natural;
- widthad_a : natural
- );
+ init_file : string;
+ lpm_type : string;
+ maximum_depth : natural;
+ numwords_a : natural;
+ operation_mode : string;
+ outdata_reg_a : string;
+ ram_block_type : string;
+ read_during_write_mode_mixed_ports : string;
+ read_during_write_mode_port_a : string;
+ width_a : natural;
+ width_byteena_a : natural;
+ widthad_a : natural
+ );
port (
- signal q_a : out std_logic_vector(31 downto 0);
- signal wren_a : in std_logic;
- signal byteena_a : in std_logic_vector(3 downto 0);
- signal clock0 : in std_logic;
- signal address_a : in std_logic_vector(14 downto 0);
- signal clocken0 : in std_logic;
- signal data_a : in std_logic_vector(31 downto 0)
- );
+ signal q_a : out std_logic_vector(31 downto 0);
+ signal wren_a : in std_logic;
+ signal byteena_a : in std_logic_vector(3 downto 0);
+ signal clock0 : in std_logic;
+ signal address_a : in std_logic_vector(14 downto 0);
+ signal clocken0 : in std_logic;
+ signal data_a : in std_logic_vector(31 downto 0)
+ );
end component altsyncram;
- signal clocken0 : std_logic;
- signal internal_readdata : std_logic_vector(31 downto 0);
- signal wren : std_logic;
+ signal clocken0 : std_logic;
+ signal internal_readdata : std_logic_vector(31 downto 0);
+ signal wren : std_logic;
begin
@@ -101,13 +101,13 @@ begin
widthad_a => 15
)
port map(
- address_a => address,
- byteena_a => byteenable,
- clock0 => clk,
- clocken0 => clocken0,
- data_a => writedata,
- q_a => internal_readdata,
- wren_a => wren
+ address_a => address,
+ byteena_a => byteenable,
+ clock0 => clk,
+ clocken0 => clocken0,
+ data_a => writedata,
+ q_a => internal_readdata,
+ wren_a => wren
);
--s1, which is an e_avalon_slave
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index 1013d9c8fe..d4fadd4056 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_onchip_memory2_0 is
+ component qsys_unb2b_minimal_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 6ac45a007b..ed5d6c9386 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_pio_pps is
+ component qsys_unb2b_minimal_pio_pps is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index 54214733fc..ce7b65f835 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_pio_system_info is
+ component qsys_unb2b_minimal_pio_system_info is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 275c472861..ad408c7815 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -16,37 +16,37 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- port (
- -- inputs:
- signal address : in std_logic_vector(1 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(1 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal out_port : out std_logic;
- signal readdata : out std_logic_vector(31 downto 0)
- );
+ -- outputs:
+ signal out_port : out std_logic;
+ signal readdata : out std_logic_vector(31 downto 0)
+ );
end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
architecture europa of qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- signal clk_en : std_logic;
- signal data_out : std_logic;
- signal read_mux_out : std_logic;
+ signal clk_en : std_logic;
+ signal data_out : std_logic;
+ signal read_mux_out : std_logic;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 7653111094..249fc3461d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_pio_wdi is
+ component qsys_unb2b_minimal_pio_wdi is
port (
clk : in std_logic := 'X'; -- clk
out_port : out std_logic; -- export
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index beaf80437e..ca0753b8f6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_dpmm_ctrl is
+ component qsys_unb2b_minimal_reg_dpmm_ctrl is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index d4d2ea56c7..cb7d6e343c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_dpmm_data is
+ component qsys_unb2b_minimal_reg_dpmm_data is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index 35a921ca9e..2b12931243 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_epcs is
+ component qsys_unb2b_minimal_reg_epcs is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 0dd4b690ec..996a19af95 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_fpga_temp_sens is
+ component qsys_unb2b_minimal_reg_fpga_temp_sens is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 391087f935..72452d8e9f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_fpga_voltage_sens is
+ component qsys_unb2b_minimal_reg_fpga_voltage_sens is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index 57e4a4c70f..cd765a360d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_mmdp_ctrl is
+ component qsys_unb2b_minimal_reg_mmdp_ctrl is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index 6ef3680e58..51873f2715 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_mmdp_data is
+ component qsys_unb2b_minimal_reg_mmdp_data is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 813521ee09..f0ecc1ba1f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_remu is
+ component qsys_unb2b_minimal_reg_remu is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index 911de6ef25..31f317ab8d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_unb_pmbus is
+ component qsys_unb2b_minimal_reg_unb_pmbus is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index bda7f7ffb4..2b7f3cd7f1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_unb_sens is
+ component qsys_unb2b_minimal_reg_unb_sens is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 2037678c58..5d57d1c5e1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_wdi is
+ component qsys_unb2b_minimal_reg_wdi is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index 24125dfe0e..026a6b8def 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_rom_system_info is
+ component qsys_unb2b_minimal_rom_system_info is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index 8b3e6b4cf8..6c59af2597 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -16,52 +16,52 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- port (
- -- inputs:
- signal address : in std_logic_vector(2 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(15 downto 0);
-
- -- outputs:
- signal irq : out std_logic;
- signal readdata : out std_logic_vector(15 downto 0)
- );
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(2 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(15 downto 0);
+
+ -- outputs:
+ signal irq : out std_logic;
+ signal readdata : out std_logic_vector(15 downto 0)
+ );
end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- signal clk_en : std_logic;
- signal control_interrupt_enable : std_logic;
- signal control_register : std_logic;
- signal control_wr_strobe : std_logic;
- signal counter_is_running : std_logic;
- signal counter_is_zero : std_logic;
- signal counter_load_value : std_logic_vector(16 downto 0);
- signal delayed_unxcounter_is_zeroxx0 : std_logic;
- signal do_start_counter : std_logic;
- signal do_stop_counter : std_logic;
- signal force_reload : std_logic;
- signal internal_counter : std_logic_vector(16 downto 0);
- signal period_h_wr_strobe : std_logic;
- signal period_l_wr_strobe : std_logic;
- signal read_mux_out : std_logic_vector(15 downto 0);
- signal status_wr_strobe : std_logic;
- signal timeout_event : std_logic;
- signal timeout_occurred : std_logic;
+ signal clk_en : std_logic;
+ signal control_interrupt_enable : std_logic;
+ signal control_register : std_logic;
+ signal control_wr_strobe : std_logic;
+ signal counter_is_running : std_logic;
+ signal counter_is_zero : std_logic;
+ signal counter_load_value : std_logic_vector(16 downto 0);
+ signal delayed_unxcounter_is_zeroxx0 : std_logic;
+ signal do_start_counter : std_logic;
+ signal do_stop_counter : std_logic;
+ signal force_reload : std_logic;
+ signal internal_counter : std_logic_vector(16 downto 0);
+ signal period_h_wr_strobe : std_logic;
+ signal period_l_wr_strobe : std_logic;
+ signal read_mux_out : std_logic_vector(15 downto 0);
+ signal status_wr_strobe : std_logic;
+ signal timeout_event : std_logic;
+ signal timeout_occurred : std_logic;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index d3f78c4dc8..476cac0f46 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_timer_0 is
+ component qsys_unb2b_minimal_timer_0 is
port (
clk : in std_logic := 'X'; -- clk
irq : out std_logic; -- irq
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
index 99377fe8a1..a2c128cc21 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, unb2b_jesd_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd_node0 is
generic (
@@ -45,7 +45,7 @@ entity unb2b_jesd_node0 is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -85,51 +85,51 @@ architecture str of unb2b_jesd_node0 is
begin
u_revision : entity unb2b_jesd_lib.unb2b_jesd
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- QSFP_LED => QSFP_LED,
-
- -- JESD signals
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_sysref => jesd204_rx_sysref,
- jesd204_device_clk => jesd204_device_clk
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED,
+
+ -- JESD signals
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_sysref => jesd204_rx_sysref,
+ jesd204_device_clk => jesd204_device_clk
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 7d7bea513e..951e9fa4ac 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_corepll is
+ component altjesd_ss_RX_corepll is
port (
locked : out std_logic; -- export
outclk_0 : out std_logic; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 1bc0ee7c56..50d5bb6b90 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_frame_reset is
+ component altjesd_ss_RX_frame_reset is
port (
clk : in std_logic := 'X'; -- clk
in_reset_n : in std_logic := 'X'; -- reset_n
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index e6c8fc658b..77367eabe2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_link_reset is
+ component altjesd_ss_RX_link_reset is
port (
clk : in std_logic := 'X'; -- clk
in_reset_n : in std_logic := 'X'; -- reset_n
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index 46793b217e..c634e00746 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_reset_seq is
+ component altjesd_ss_RX_reset_seq is
generic (
NUM_OUTPUTS : integer := 3;
ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index 4aa29f21f8..8dff895996 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,4 +1,4 @@
- component altjesd_ss_RX_xcvr_reset_control is
+ component altjesd_ss_RX_xcvr_reset_control is
port (
clock : in std_logic := 'X'; -- clk
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index bfd91a8bfa..7d0eb498ea 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,4 +1,4 @@
- component device_clk is
+ component device_clk is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 342b6062c1..124a3b18ef 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,4 +1,4 @@
- component frame_clk is
+ component frame_clk is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 9868df2cdd..ff194b2a69 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,4 +1,4 @@
- component jesd is
+ component jesd is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index 7da9be04fe..2017afa101 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,4 +1,4 @@
- component link_clk is
+ component link_clk is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index c97253ac79..5a858a60f9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_avs_common_mm_0 is
+ component qsys_unb2b_minimal_avs_common_mm_0 is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index b57aa7daff..75fab6c120 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_avs_common_mm_1 is
+ component qsys_unb2b_minimal_avs_common_mm_1 is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index 3c94c1901f..274d14a577 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index 3fc6ebb7a2..d49ba9d9fb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
@@ -86,9 +86,11 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -135,13 +137,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
c_network_ip_identification_len + c_network_ip_flags_fragment_len +
c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
c_network_ip_addr_len +
c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -175,11 +177,20 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001",
+ "0001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "001",
+ "0000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ARP Packet
@@ -216,12 +227,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -247,12 +258,17 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001",
+ "0000000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -301,8 +317,13 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- UDP Packet
@@ -327,7 +348,7 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
@@ -348,8 +369,12 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 9469fd2656..cfde8ebf26 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
@@ -165,315 +165,318 @@ package common_pkg is
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ function pow2 (n : natural) return natural; -- = 2**n
+ function ceil_pow2 (n : integer) return natural; -- = 2**n, returns 1 for n<0
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function true_log2 (n : natural) return natural; -- true_log2(n) = log2(n)
+ function ceil_log2 (n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
- function floor_log10(n : natural) return natural;
+ function floor_log10 (n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
+ function is_pow2 (n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function true_log_pow2 (n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio ( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio2 (n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
- function ceil_div( n : unsigned; d: natural) return unsigned;
- function ceil_value( n : unsigned; d: natural) return unsigned;
- function floor_value(n : unsigned; d: natural) return unsigned;
+ function ceil_div ( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_value ( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
+ function floor_value (n, d : natural) return natural; -- floor_value = (n/d) * d
+ function ceil_div ( n : unsigned; d: natural) return unsigned;
+ function ceil_value ( n : unsigned; d: natural) return unsigned;
+ function floor_value (n : unsigned; d: natural) return unsigned;
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+ function slv (n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
+ function sl ( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
- function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
- function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr;
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr;
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr;
+ function to_slv_32_arr ( n : t_integer_arr) return t_slv_32_arr;
+ function to_slv_32_arr ( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_and (slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
+ function vector_or ( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
+ function vector_xor (slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
+ function andv (slv : std_logic_vector) return std_logic; -- alias of vector_and
+ function orv ( slv : std_logic_vector) return std_logic; -- alias of vector_or
+ function xorv (slv : std_logic_vector) return std_logic; -- alias of vector_xor
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
+ function matrix_or ( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
- function smallest(n, m : integer) return integer;
- function smallest(n, m, l : integer) return integer;
- function smallest(n : t_natural_arr) return natural;
+ function smallest (n, m : integer) return integer;
+ function smallest (n, m, l : integer) return integer;
+ function smallest (n : t_natural_arr) return natural;
- function largest(n, m : integer) return integer;
- function largest(n : t_natural_arr) return natural;
+ function largest (n, m : integer) return integer;
+ function largest (n : t_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
- function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
- function func_product(n : t_nat_natural_arr) return natural;
+ function func_sum ( n : t_natural_arr) return natural; -- sum of all elements in array
+ function func_sum ( n : t_nat_natural_arr) return natural;
+ function func_product (n : t_natural_arr) return natural; -- product of all elements in array
+ function func_product (n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
-
- function is_true(a : std_logic) return boolean;
- function is_true(a : std_logic) return natural;
- function is_true(a : boolean) return std_logic;
- function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
-
- function sel_a_b(sel, a, b : boolean) return boolean;
- function sel_a_b(sel, a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : real) return real;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : signed) return signed;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
- function sel_a_b(sel : boolean; a, b : string) return string;
- function sel_a_b(sel : integer; a, b : string) return string;
- function sel_a_b(sel : boolean; a, b : time) return time;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+
+ function is_true (a : std_logic) return boolean;
+ function is_true (a : std_logic) return natural;
+ function is_true (a : boolean) return std_logic;
+ function is_true (a : boolean) return natural;
+ function is_true (a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true (a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+
+ function sel_a_b (sel, a, b : boolean) return boolean;
+ function sel_a_b (sel, a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : real) return real;
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : signed) return signed;
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned;
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
+ function sel_a_b (sel : boolean; a, b : string) return string;
+ function sel_a_b (sel : integer; a, b : string) return string;
+ function sel_a_b (sel : boolean; a, b : time) return time;
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
- function array_init(init, nof, incr : natural) return t_nat_natural_arr;
- function array_init(init, nof, incr : integer) return t_slv_16_arr;
- function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
-
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ function sel_n (sel : natural; a, b, c : boolean) return boolean; -- 3
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
+
+ function sel_n (sel : natural; a, b, c : integer) return integer; -- 3
+ function sel_n (sel : natural; a, b, c, d : integer) return integer; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
+
+ function sel_n (sel : natural; a, b : string) return string; -- 2
+ function sel_n (sel : natural; a, b, c : string) return string; -- 3
+ function sel_n (sel : natural; a, b, c, d : string) return string; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : string) return string; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr;
+ function array_init (init, nof, incr : integer) return t_slv_16_arr;
+ function array_init (init, nof, incr : integer) return t_slv_32_arr;
+ function array_init (init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init (init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_sinit (init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
-
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
- function TO_SINT(vec : std_logic_vector) return integer;
-
- function TO_UVEC(dec, w : natural) return std_logic_vector;
- function TO_SVEC(dec, w : integer) return std_logic_vector;
-
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
-
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+
+ function TO_UINT (vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_SINT (vec : std_logic_vector) return integer;
+
+ function TO_UVEC (dec, w : natural) return std_logic_vector;
+ function TO_SVEC (dec, w : integer) return std_logic_vector;
+
+ function TO_SVEC_32 (dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
-- happens for RESIZE of UNSIGNED. Therefor this is what the RESIZE_NUM for SIGNED and the RESIZE_SVEC do
-- and better not use RESIZE for SIGNED anymore.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
-
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
-
- function offset_binary(a : std_logic_vector) return std_logic_vector;
-
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
- function flip(a : t_slv_32_arr) return t_slv_32_arr;
- function flip(a : t_integer_arr) return t_integer_arr;
- function flip(a : t_natural_arr) return t_natural_arr;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
-
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
-
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
-
- function pad(str: string; width: natural; pad_char: character) return string;
-
- function slice_up(str: string; width: natural; i: natural) return string;
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string;
- function slice_dn(str: string; width: natural; i: natural) return string;
-
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
+ function RESIZE_NUM ( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM ( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
+ function RESIZE_UINT (u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
+ function RESIZE_SINT (s : integer; w : natural) return integer; -- extend sign bit or keep LS part
+
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector;
+ -- Used in common_add_sub.vhd
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+
+ function offset_binary (a : std_logic_vector) return std_logic_vector;
+
+ function truncate ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function scale ( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
+ function scale_and_resize_uvec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_svec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function truncate_or_resize_uvec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_svec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
+
+ function s_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round_up (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up (vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
+ function u_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
+ function u_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
+
+ function u_to_s (u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function s_to_u (s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+
+ function u_wrap (u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function s_wrap (s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+
+ function u_clip (u : natural; max : natural) return natural; -- if s < max return s, else return n
+ function s_clip (s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip (s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
+
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
+ function hton (a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh (a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+
+ function flip (a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
+ function flip (a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip (a : t_slv_32_arr) return t_slv_32_arr;
+ function flip (a : t_integer_arr) return t_integer_arr;
+ function flip (a : t_natural_arr) return t_natural_arr;
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr;
+
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
+
+ function pad (str: string; width: natural; pad_char: character) return string;
+
+ function slice_up (str: string; width: natural; i: natural) return string;
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string;
+ function slice_dn (str: string; width: natural; i: natural) return string;
+
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
------------------------------------------------------------------------------
-- Component specific functions
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
- function func_common_reorder2_is_there(I, J : natural) return boolean;
- function func_common_reorder2_is_active(I, J, N : natural) return boolean;
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer;
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural;
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
+ function func_common_reorder2_is_there (I, J : natural) return boolean;
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean;
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer;
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural;
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
- function pow2(n : natural) return natural is
+ function pow2 (n : natural) return natural is
begin
return 2**n;
end;
- function ceil_pow2(n : integer) return natural is
+ function ceil_pow2 (n : integer) return natural is
-- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
- function true_log2(n : natural) return natural is
+ function true_log2 (n : natural) return natural is
-- Purpose: For calculating extra vector width of existing vector
-- Description: Return mathematical ceil(log2(n))
-- n log2()
@@ -492,7 +495,7 @@ package body common_pkg is
return natural(integer(ceil(log2(real(n)))));
end;
- function ceil_log2(n : natural) return natural is
+ function ceil_log2 (n : natural) return natural is
-- Purpose: For calculating vector width of new vector
-- Description:
-- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
@@ -510,22 +513,22 @@ package body common_pkg is
end if;
end;
- function floor_log10(n : natural) return natural is
+ function floor_log10 (n : natural) return natural is
begin
return natural(integer(floor(log10(real(n)))));
end;
- function is_pow2(n : natural) return boolean is
+ function is_pow2 (n : natural) return boolean is
begin
return n = 2**true_log2(n);
end;
- function true_log_pow2(n : natural) return natural is
+ function true_log_pow2 (n : natural) return natural is
begin
return 2**true_log2(n);
end;
- function ratio(n, d : natural) return natural is
+ function ratio (n, d : natural) return natural is
begin
if n mod d = 0 then
return n / d;
@@ -534,32 +537,32 @@ package body common_pkg is
end if;
end;
- function ratio2(n, m : natural) return natural is
+ function ratio2 (n, m : natural) return natural is
begin
return largest(ratio(n,m), ratio(m,n));
end;
- function ceil_div(n, d : natural) return natural is
+ function ceil_div (n, d : natural) return natural is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
- function ceil_value(n, d : natural) return natural is
+ function ceil_value (n, d : natural) return natural is
begin
return ceil_div(n, d) * d;
end;
- function floor_value(n, d : natural) return natural is
+ function floor_value (n, d : natural) return natural is
begin
return (n / d) * d;
end;
- function ceil_div(n : unsigned; d: natural) return unsigned is
+ function ceil_div (n : unsigned; d: natural) return unsigned is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
end;
- function ceil_value(n : unsigned; d: natural) return unsigned is
+ function ceil_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -567,7 +570,7 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function floor_value(n : unsigned; d: natural) return unsigned is
+ function floor_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -575,21 +578,21 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function slv(n: in std_logic) return std_logic_vector is
+ function slv (n: in std_logic) return std_logic_vector is
variable r : std_logic_vector(0 downto 0);
begin
r(0) := n;
return r;
end;
- function sl(n: in std_logic_vector) return std_logic is
+ function sl (n: in std_logic_vector) return std_logic is
variable r : std_logic;
begin
r := n(n'low);
return r;
end;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr is
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -607,7 +610,7 @@ package body common_pkg is
return vR;
end;
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr is
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr is
variable vN : t_nat_natural_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -618,7 +621,7 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_integer_arr(n'length - 1 downto 0);
begin
@@ -629,14 +632,14 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return to_integer_arr(vN);
end;
- function to_slv_32_arr(n : t_integer_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_integer_arr) return t_slv_32_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -647,7 +650,7 @@ package body common_pkg is
return vR;
end;
- function to_slv_32_arr(n : t_natural_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_natural_arr) return t_slv_32_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -658,7 +661,7 @@ package body common_pkg is
return vR;
end;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic is
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic is
-- Linear loop to determine result takes combinatorial delay that is proportional to slv'LENGTH:
-- FOR I IN slv'RANGE LOOP
-- v_result := v_result OPERATION slv(I);
@@ -691,22 +694,22 @@ package body common_pkg is
return v_stage_arr(c_nof_stages - 1)(0);
end;
- function vector_and(slv : std_logic_vector) return std_logic is
+ function vector_and (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function vector_or(slv : std_logic_vector) return std_logic is
+ function vector_or (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function vector_xor(slv : std_logic_vector) return std_logic is
+ function vector_xor (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector is
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector is
variable v_one_hot : boolean := false;
variable v_zeros : std_logic_vector(slv'range) := (others => '0');
begin
@@ -725,22 +728,22 @@ package body common_pkg is
return slv;
end;
- function andv(slv : std_logic_vector) return std_logic is
+ function andv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function orv(slv : std_logic_vector) return std_logic is
+ function orv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function xorv(slv : std_logic_vector) return std_logic is
+ function xorv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '1';
begin
@@ -752,7 +755,7 @@ package body common_pkg is
return v_result;
end;
- function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_or (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '0';
begin
@@ -764,7 +767,7 @@ package body common_pkg is
return v_result;
end;
- function smallest(n, m : integer) return integer is
+ function smallest (n, m : integer) return integer is
begin
if n < m then
return n;
@@ -773,16 +776,16 @@ package body common_pkg is
end if;
end;
- function smallest(n, m, l : integer) return integer is
+ function smallest (n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
end;
- function smallest(n : t_natural_arr) return natural is
+ function smallest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -793,7 +796,7 @@ package body common_pkg is
return m;
end;
- function largest(n, m : integer) return integer is
+ function largest (n, m : integer) return integer is
begin
if n > m then
return n;
@@ -802,7 +805,7 @@ package body common_pkg is
end if;
end;
- function largest(n : t_natural_arr) return natural is
+ function largest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -813,7 +816,7 @@ package body common_pkg is
return m;
end;
- function func_sum(n : t_natural_arr) return natural is
+ function func_sum (n : t_natural_arr) return natural is
variable vS : natural;
begin
vS := 0;
@@ -823,14 +826,14 @@ package body common_pkg is
return vS;
end;
- function func_sum(n : t_nat_natural_arr) return natural is
+ function func_sum (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return func_sum(vN);
end;
- function func_product(n : t_natural_arr) return natural is
+ function func_product (n : t_natural_arr) return natural is
variable vP : natural;
begin
vP := 1;
@@ -840,7 +843,7 @@ package body common_pkg is
return vP;
end;
- function func_product(n : t_nat_natural_arr) return natural is
+ function func_product (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
@@ -999,14 +1002,14 @@ package body common_pkg is
return vP;
end;
- function is_true(a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
- function is_true(a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
- function is_true(a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
- function is_true(a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
- function is_true(a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
- function is_true(a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
+ function is_true (a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
+ function is_true (a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
+ function is_true (a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
+ function is_true (a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
+ function is_true (a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
+ function is_true (a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
- function sel_a_b(sel, a, b : integer) return integer is
+ function sel_a_b (sel, a, b : integer) return integer is
begin
if sel /= 0 then
return a;
@@ -1015,7 +1018,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel, a, b : boolean) return boolean is
+ function sel_a_b (sel, a, b : boolean) return boolean is
begin
if sel = true then
return a;
@@ -1024,7 +1027,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : integer) return integer is
+ function sel_a_b (sel : boolean; a, b : integer) return integer is
begin
if sel = true then
return a;
@@ -1033,7 +1036,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : real) return real is
+ function sel_a_b (sel : boolean; a, b : real) return real is
begin
if sel = true then
return a;
@@ -1042,7 +1045,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic is
begin
if sel = true then
return a;
@@ -1051,7 +1054,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic is
begin
if sel /= 0 then
return a;
@@ -1060,7 +1063,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector is
begin
if sel /= 0 then
return a;
@@ -1069,7 +1072,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
if sel = true then
return a;
@@ -1078,7 +1081,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : signed) return signed is
+ function sel_a_b (sel : boolean; a, b : signed) return signed is
begin
if sel = true then
return a;
@@ -1087,7 +1090,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned is
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned is
begin
if sel = true then
return a;
@@ -1096,7 +1099,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr is
begin
if sel = true then
return a;
@@ -1105,7 +1108,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr is
begin
if sel = true then
return a;
@@ -1114,7 +1117,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
begin
if sel = true then
return a;
@@ -1123,7 +1126,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
begin
if sel = true then
return a;
@@ -1132,7 +1135,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : string) return string is
+ function sel_a_b (sel : boolean; a, b : string) return string is
begin
if sel = true then
return a;
@@ -1141,7 +1144,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : string) return string is
+ function sel_a_b (sel : integer; a, b : string) return string is
begin
if sel /= 0 then
return a;
@@ -1150,7 +1153,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : time) return time is
+ function sel_a_b (sel : boolean; a, b : time) return time is
begin
if sel = true then
return a;
@@ -1159,7 +1162,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level is
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level is
begin
if sel = true then
return a;
@@ -1169,115 +1172,115 @@ package body common_pkg is
end;
-- sel_n : boolean
- function sel_n(sel : natural; a, b, c : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : integer
- function sel_n(sel : natural; a, b, c : integer) return integer is
+ function sel_n (sel : natural; a, b, c : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : string
- function sel_n(sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
- function sel_n(sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
- function sel_n(sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
- function sel_n(sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector is
+ function sel_n (sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
+ function sel_n (sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
+ function sel_n (sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector is
variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1286,7 +1289,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_natural_arr is
+ function array_init (init, nof : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1295,7 +1298,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_nat_natural_arr is
+ function array_init (init, nof : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1304,7 +1307,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_natural_arr is
+ function array_init (init, nof, incr : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1316,7 +1319,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_nat_natural_arr is
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1328,7 +1331,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_16_arr is
+ function array_init (init, nof, incr : integer) return t_slv_16_arr is
variable v_arr : t_slv_16_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1340,7 +1343,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_32_arr is
+ function array_init (init, nof, incr : integer) return t_slv_32_arr is
variable v_arr : t_slv_32_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1352,7 +1355,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width : natural) return std_logic_vector is
+ function array_init (init, nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1361,7 +1364,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width, incr : natural) return std_logic_vector is
+ function array_init (init, nof, width, incr : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
variable v_i : natural;
begin
@@ -1373,7 +1376,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
+ function array_sinit (init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1382,7 +1385,7 @@ package body common_pkg is
return v_arr;
end;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix is
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix is
variable v_mat : t_slv_64_matrix(nof_a - 1 downto 0, nof_b - 1 downto 0);
begin
for I in 0 to nof_a - 1 loop
@@ -1395,7 +1398,7 @@ package body common_pkg is
-- Support concatenation of up to 7 slv into 1 slv
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length;
variable v_res : std_logic_vector(c_max_w - 1 downto 0) := (others => '0');
variable v_len : natural := 0;
@@ -1410,32 +1413,32 @@ package body common_pkg is
return v_res(v_len - 1 downto 0);
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, false, a, b, c, d, e, f, "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, false, false, a, b, c, d, e, "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, false, false, false, a, b, c, d, "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, false, false, false, false, a, b, c, "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, false, false, false, false, false, a, b, "0", "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
variable v_len : natural := 0;
begin
if use_a = true then v_len := v_len + a_w; end if;
@@ -1448,33 +1451,33 @@ package body common_pkg is
return v_len;
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, false, a_w, b_w, c_w, d_w, e_w, f_w, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0);
end func_slv_concat_w;
-- extract slv
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
variable v_w : natural := 0;
variable v_lo : natural := 0;
begin
@@ -1520,64 +1523,64 @@ package body common_pkg is
return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, false, a_w, b_w, c_w, d_w, e_w, f_w, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function TO_UINT(vec : std_logic_vector) return natural is
+ function TO_UINT (vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
end;
- function TO_SINT(vec : std_logic_vector) return integer is
+ function TO_SINT (vec : std_logic_vector) return integer is
begin
return to_integer(signed(vec));
end;
- function TO_UVEC(dec, w : natural) return std_logic_vector is
+ function TO_UVEC (dec, w : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(dec, w));
end;
- function TO_SVEC(dec, w : integer) return std_logic_vector is
+ function TO_SVEC (dec, w : integer) return std_logic_vector is
begin
return std_logic_vector(to_signed(dec, w));
end;
- function TO_SVEC_32(dec : integer) return std_logic_vector is
+ function TO_SVEC_32 (dec : integer) return std_logic_vector is
begin
return TO_SVEC(dec, 32);
end;
- function RESIZE_NUM(u : unsigned; w : natural) return unsigned is
+ function RESIZE_NUM (u : unsigned; w : natural) return unsigned is
begin
-- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
return resize(u, w);
end;
- function RESIZE_NUM(s : signed; w : natural) return signed is
+ function RESIZE_NUM (s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
if w > s'length then
@@ -1587,47 +1590,47 @@ package body common_pkg is
end if;
end;
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector is
variable v_slv0 : std_logic_vector(w - 1 downto 1) := (others => '0');
begin
return v_slv0 & sl;
end;
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(vec), w));
end;
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(vec), w));
end;
- function RESIZE_UINT(u : integer; w : natural) return integer is
+ function RESIZE_UINT (u : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_UVEC(u, c_word_w);
return TO_UINT(v(w - 1 downto 0));
end;
- function RESIZE_SINT(s : integer; w : natural) return integer is
+ function RESIZE_SINT (s : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_SVEC(s, c_word_w);
return TO_SINT(v(w - 1 downto 0));
end;
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, 32);
end;
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, 32);
end;
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
if dec < 0 then
@@ -1639,74 +1642,74 @@ package body common_pkg is
end if;
end;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector is
begin
return std_logic_vector(unsigned(vec) + dec);
end;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
return std_logic_vector(signed(vec) + v_dec); -- uses function "+" (L : SIGNED, R : INTEGER)
end;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector is
begin
return std_logic_vector(signed(vec) + dec);
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) + signed(r_vec));
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) - signed(r_vec));
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) + unsigned(r_vec));
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_SVEC(l_vec, r_vec, l_vec'length);
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_UVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_UVEC(l_vec, r_vec, l_vec'length);
end;
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_re * b_re - a_im * b_im);
end;
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_im * b_re + a_re * b_im);
end;
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
@@ -1715,7 +1718,7 @@ package body common_pkg is
end if;
end;
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
@@ -1741,24 +1744,24 @@ package body common_pkg is
-- The offset_binary() mapping can be done and undone both ways.
-- The offset_binary() mapping to two-complement binary yields a DC offset
-- of -0.5 Lsb.
- function offset_binary(a : std_logic_vector) return std_logic_vector is
+ function offset_binary (a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
- function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function truncate (vec : std_logic_vector; n : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -1769,7 +1772,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -1780,7 +1783,7 @@ package body common_pkg is
return v_res;
end;
- function scale(vec : std_logic_vector; n: natural) return std_logic_vector is
+ function scale (vec : std_logic_vector; n: natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1789,7 +1792,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1800,7 +1803,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1811,7 +1814,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_uvec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_uvec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -1824,7 +1827,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_svec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_svec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -1856,7 +1859,7 @@ package body common_pkg is
-- maximum product is -8*-8=+64 <= 127-8, so wrapping due to rounding
-- overflow will never occur.
- function s_round(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
-- Use SIGNED to avoid NATURAL (32 bit range) overflow error
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
@@ -1884,24 +1887,24 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return s_round(vec, n, false); -- no round clip
end;
-- An alternative is to always round up, also for negative numbers (i.e. s_round_up = u_round).
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round_up (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
begin
return u_round(vec, n, clip);
end;
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round_up (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
-- Unsigned numbers are round up (almost same as s_round, but without the else on negative vec)
- function u_round(vec : std_logic_vector; n : natural; clip : boolean ) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural; clip : boolean ) return std_logic_vector is
-- Use UNSIGNED to avoid NATURAL (32 bit range) overflow error
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
@@ -1925,36 +1928,36 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
- function u_to_s(u : natural; w : natural) return integer is
+ function u_to_s (u : natural; w : natural) return integer is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
- function s_to_u(s : integer; w : natural) return natural is
+ function s_to_u (s : integer; w : natural) return natural is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
- function u_wrap(u : natural; w : natural) return natural is
+ function u_wrap (u : natural; w : natural) return natural is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
- function s_wrap(s : integer; w : natural) return integer is
+ function s_wrap (s : integer; w : natural) return integer is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
- function u_clip(u : natural; max : natural) return natural is
+ function u_clip (u : natural; max : natural) return natural is
begin
if u > max then
return max;
@@ -1963,7 +1966,7 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural; min : integer) return integer is
+ function s_clip (s : integer; max : natural; min : integer) return integer is
begin
if s < min then
return min;
@@ -1976,12 +1979,12 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural) return integer is
+ function s_clip (s : integer; max : natural) return integer is
begin
return s_clip(s, max, -max);
end;
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
variable vL : natural;
@@ -1997,28 +2000,28 @@ package body common_pkg is
return v_b;
end function;
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
end function;
- function hton(a : std_logic_vector) return std_logic_vector is
+ function hton (a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
end function;
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, sz); -- i.e. ntoh() = hton()
end function;
- function ntoh(a : std_logic_vector) return std_logic_vector is
+ function ntoh (a : std_logic_vector) return std_logic_vector is
begin
return hton(a); -- i.e. ntoh() = hton()
end function;
- function flip(a : std_logic_vector) return std_logic_vector is
+ function flip (a : std_logic_vector) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2028,12 +2031,12 @@ package body common_pkg is
return v_b;
end;
- function flip(a, w : natural) return natural is
+ function flip (a, w : natural) return natural is
begin
return TO_UINT(flip(TO_UVEC(a, w)));
end;
- function flip(a : t_slv_32_arr) return t_slv_32_arr is
+ function flip (a : t_slv_32_arr) return t_slv_32_arr is
variable v_a : t_slv_32_arr(a'length - 1 downto 0) := a;
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
@@ -2043,7 +2046,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_integer_arr) return t_integer_arr is
+ function flip (a : t_integer_arr) return t_integer_arr is
variable v_a : t_integer_arr(a'length - 1 downto 0) := a;
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
@@ -2053,7 +2056,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_natural_arr) return t_natural_arr is
+ function flip (a : t_natural_arr) return t_natural_arr is
variable v_a : t_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
@@ -2063,7 +2066,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr is
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr is
variable v_a : t_nat_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
@@ -2073,7 +2076,7 @@ package body common_pkg is
return v_b;
end;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector is
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2087,7 +2090,7 @@ package body common_pkg is
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
variable vI : natural;
variable vJ : natural;
begin
@@ -2096,7 +2099,7 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
@@ -2111,34 +2114,34 @@ package body common_pkg is
end loop;
end;
- function pad(str: string; width: natural; pad_char: character) return string is
+ function pad (str: string; width: natural; pad_char: character) return string is
variable v_str : string(1 to width) := (others => pad_char);
begin
v_str(width - str'length + 1 to width) := str;
return v_str;
end;
- function slice_up(str: string; width: natural; i: natural) return string is
+ function slice_up (str: string; width: natural; i: natural) return string is
begin
return str(i * width + 1 to (i + 1) * width);
end;
-- If the input value is not a multiple of the desired width, the return value is padded with
-- the passed pad value. E.g. if input='10' and desired width is 4, return value is '0010'.
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string is
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
- function slice_dn(str: string; width: natural; i: natural) return string is
+ function slice_dn (str: string; width: natural; i: natural) return string is
begin
return str((i + 1) * width - 1 downto i * width);
end;
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
for i in 0 to nof_elements - 1 loop
@@ -2152,16 +2155,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2174,7 +2178,7 @@ package body common_pkg is
assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
- --synthesis translate_on
+ --synthesis translate_on
end procedure proc_common_fifo_asserts;
@@ -2182,8 +2186,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2204,7 +2209,7 @@ package body common_pkg is
------------------------------------------------------------------------------
-- Determine whether the stage I and row J index refer to any (active or redundant) 2-input reorder cell instantiation
- function func_common_reorder2_is_there(I, J : natural) return boolean is
+ function func_common_reorder2_is_there (I, J : natural) return boolean is
variable v_odd : boolean;
variable v_even : boolean;
begin
@@ -2214,7 +2219,7 @@ package body common_pkg is
end func_common_reorder2_is_there;
-- Determine whether the stage I and row J index refer to an active 2-input reorder cell instantiation in a reorder network with N stages
- function func_common_reorder2_is_active(I, J, N : natural) return boolean is
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean is
variable v_inst : boolean;
variable v_act : boolean;
begin
@@ -2224,7 +2229,7 @@ package body common_pkg is
end func_common_reorder2_is_active;
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer is
constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
@@ -2246,7 +2251,7 @@ package body common_pkg is
end func_common_reorder2_get_select_index;
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -2261,7 +2266,7 @@ package body common_pkg is
end func_common_reorder2_get_select;
-- Determine the inverse of a reorder network by using two reorder networks in series
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -2287,8 +2292,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2327,9 +2332,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
@@ -2354,7 +2360,7 @@ package body common_pkg is
end if;
wait for v_speriod / 2;
SCLK <= '1';
- -- Wait for next DCLK
+ -- Wait for next DCLK
end loop;
wait;
end proc_common_dclk_generate_sclk;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 40128fea21..0fa106e866 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
@@ -121,15 +121,33 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_bsn_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ '1',
+ '1',
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_empty_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_channel_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_error_w)
+ );
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -208,30 +226,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -240,142 +262,142 @@ package dp_stream_pkg is
-- Typically the sosi data are treated as unsigned in the record field, so extended with '0'. However for interpretating
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
- function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
- function TO_DP_EMPTY( n : natural) return std_logic_vector;
- function TO_DP_CHANNEL( n : natural) return std_logic_vector;
- function TO_DP_ERROR( n : natural) return std_logic_vector;
- function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
- function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
-
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
-
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
-
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
+ function TO_DP_BSN ( n : natural) return std_logic_vector;
+ function TO_DP_DATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_SDATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
+ function TO_DP_UDATA ( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector; -- for re and im fields, signed data
+ function TO_DP_DSP_UDATA (n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_EMPTY ( n : natural) return std_logic_vector;
+ function TO_DP_CHANNEL ( n : natural) return std_logic_vector;
+ function TO_DP_ERROR ( n : natural) return std_logic_vector;
+ function RESIZE_DP_BSN ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_DATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
+ function RESIZE_DP_SDATA ( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
+ function RESIZE_DP_XDATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_EMPTY ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_CHANNEL ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_ERROR ( vec : std_logic_vector) return std_logic_vector;
+
+ function INCR_DP_DATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
+ function INCR_DP_SDATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+
+ function REPLICATE_DP_DATA ( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
-- Shift and combine part of previous data and this data, use the other sosi from prev_sosi
- function func_dp_data_shift( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
+ function func_dp_data_shift ( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
+ function func_dp_data_shift_last ( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
-- Determine resulting empty if two streams are concatenated or split
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi;
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi;
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; str : string) return std_logic;
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector;
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
-- Fix reversed buses due to connecting TO to DOWNTO range arrays.
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr;
-- Functions to combinatorially hold the data fields and to set or reset the control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_info( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_control( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_reset_control( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_info ( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_control ( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reset_control ( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
-- Reset sosi ctrl and preserve the sosi data (to avoid unnecessary data toggling and to ease data view in Wave window)
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
-- Function to copy the BSN of one valid stream to all output streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
-- Functions to combinatorially handle the BSN field
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
-- Functions to combine sosi fields
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi;
-- Functions to convert sosi fields
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
-- Functions to set the DATA, RE and IM field in a stream.
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
-
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
-
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
+
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -384,14 +406,14 @@ package dp_stream_pkg is
-- . data_order_im_re = TRUE then "COMPLEX" data = im&re
-- FALSE then "COMPLEX" data = re&im
-- ignore when data_representation /= "COMPLEX"
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
end dp_stream_pkg;
@@ -399,11 +421,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -417,20 +440,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -448,118 +473,119 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
- function TO_DP_BSN(n : natural) return std_logic_vector is
+ function TO_DP_BSN (n : natural) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_bsn_w);
end TO_DP_BSN;
- function TO_DP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_DATA;
- function TO_DP_SDATA(n : integer) return std_logic_vector is
+ function TO_DP_SDATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_SDATA;
- function TO_DP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_UDATA (n : integer) return std_logic_vector is
begin
return TO_DP_DATA(n);
end TO_DP_UDATA;
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_DATA;
- function TO_DP_DSP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_UDATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_UDATA;
- function TO_DP_EMPTY(n : natural) return std_logic_vector is
+ function TO_DP_EMPTY (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_empty_w);
end TO_DP_EMPTY;
- function TO_DP_CHANNEL(n : natural) return std_logic_vector is
+ function TO_DP_CHANNEL (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_channel_w);
end TO_DP_CHANNEL;
- function TO_DP_ERROR(n : natural) return std_logic_vector is
+ function TO_DP_ERROR (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_error_w);
end TO_DP_ERROR;
- function RESIZE_DP_BSN(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_BSN (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_bsn_w);
end RESIZE_DP_BSN;
- function RESIZE_DP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_DATA;
- function RESIZE_DP_SDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_SDATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_SDATA;
- function RESIZE_DP_XDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_XDATA (vec : std_logic_vector) return std_logic_vector is
variable v_vec : std_logic_vector(c_dp_stream_data_w - 1 downto 0) := (others => 'X');
begin
v_vec(vec'length - 1 downto 0) := vec;
return v_vec;
end RESIZE_DP_XDATA;
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_dsp_data_w);
end RESIZE_DP_DSP_DATA;
- function RESIZE_DP_EMPTY(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_EMPTY (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_empty_w);
end RESIZE_DP_EMPTY;
- function RESIZE_DP_CHANNEL(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_CHANNEL (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_channel_w);
end RESIZE_DP_CHANNEL;
- function RESIZE_DP_ERROR(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_ERROR (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_error_w);
end RESIZE_DP_ERROR;
- function INCR_DP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DATA(std_logic_vector(unsigned(vec(w - 1 downto 0)) + dec));
end INCR_DP_DATA;
- function INCR_DP_SDATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_SDATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_SDATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_SDATA;
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DSP_DATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_DSP_DATA;
- function REPLICATE_DP_DATA(seq : std_logic_vector) return std_logic_vector is
+ function REPLICATE_DP_DATA (seq : std_logic_vector) return std_logic_vector is
constant c_seq_w : natural := seq'length;
constant c_nof_replications : natural := ceil_div(c_dp_stream_data_w, c_seq_w);
constant c_vec_w : natural := ceil_value(c_dp_stream_data_w, c_seq_w);
@@ -571,7 +597,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
@@ -590,7 +616,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -608,7 +634,7 @@ package body dp_stream_pkg is
end TO_DP_SOSI_UNSIGNED;
-- Keep part of head data and combine part of tail data
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
@@ -625,7 +651,7 @@ package body dp_stream_pkg is
-- Shift and combine part of previous data and this data,
- function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
+ function func_dp_data_shift (prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
@@ -658,7 +684,7 @@ package body dp_stream_pkg is
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
+ function func_dp_data_shift_last (tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
variable vL : natural := input_empty;
variable vN : natural := nof_symbols_per_data;
@@ -688,7 +714,7 @@ package body dp_stream_pkg is
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(head_empty);
@@ -700,7 +726,7 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_concat;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(input_empty);
@@ -715,7 +741,7 @@ package body dp_stream_pkg is
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
begin
for I in dp'range loop
@@ -729,7 +755,7 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -751,7 +777,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -775,19 +801,19 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -809,7 +835,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -833,13 +859,13 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
@@ -847,7 +873,7 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -860,7 +886,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -875,19 +901,19 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -899,7 +925,7 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -915,7 +941,7 @@ package body dp_stream_pkg is
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -928,7 +954,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -941,7 +967,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -954,7 +980,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -967,7 +993,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -980,7 +1006,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -993,7 +1019,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1006,7 +1032,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1019,7 +1045,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr is
variable v_to_range : t_dp_siso_arr(0 to in_arr'high);
variable v_downto_range : t_dp_siso_arr(in_arr'high downto 0);
begin
@@ -1036,7 +1062,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_reverse_range;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_to_range : t_dp_sosi_arr(0 to in_arr'high);
variable v_downto_range : t_dp_sosi_arr(in_arr'high downto 0);
begin
@@ -1054,7 +1080,7 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reverse_range;
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
@@ -1062,7 +1088,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
- function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_info (dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi info
@@ -1074,7 +1100,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_info;
- function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_control (dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi control
@@ -1086,7 +1112,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_control;
- function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reset_control (dp : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- reset sosi control
@@ -1098,7 +1124,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_reset_control;
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp; -- hold sosi data
begin
-- reset sosi control
@@ -1110,7 +1136,7 @@ package body dp_stream_pkg is
end func_dp_stream_reset_control;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
begin
for I in dp'range loop
@@ -1123,13 +1149,13 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_max(dp, c_mask, w);
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
begin
for I in dp'range loop
@@ -1142,14 +1168,14 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_min;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_min(dp, c_mask, w);
end func_dp_stream_arr_bsn_min;
-- Function to copy the BSN number of one valid stream to all other streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
@@ -1166,14 +1192,14 @@ package body dp_stream_pkg is
-- Functions to combinatorially handle channels
- function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.channel := TO_UVEC(ch, c_dp_stream_channel_w);
return v_rec;
end func_dp_stream_channel_set;
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) /= ch then
@@ -1184,7 +1210,7 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_select;
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) = ch then
@@ -1196,7 +1222,7 @@ package body dp_stream_pkg is
end func_dp_stream_channel_remove;
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.err := TO_UVEC(n, c_dp_stream_error_w);
@@ -1204,7 +1230,7 @@ package body dp_stream_pkg is
end func_dp_stream_error_set;
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.bsn := RESIZE_DP_BSN(bsn);
@@ -1212,7 +1238,7 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
-- Combine sosi data with the sosi info fields
@@ -1225,7 +1251,7 @@ package body dp_stream_pkg is
end func_dp_stream_combine_info_and_data;
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
@@ -1242,23 +1268,23 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_slv_to_integer;
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1267,7 +1293,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1278,8 +1304,8 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_re : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1300,17 +1326,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_hi : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1333,17 +1359,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, 1, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1352,17 +1378,17 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1371,18 +1397,18 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, 1, true);
end;
-- Concatenate the data (and complex fields) from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out : t_dp_sosi := snk_in_arr(0);
begin
@@ -1397,7 +1423,7 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1407,7 +1433,7 @@ package body dp_stream_pkg is
end;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_in_w : natural := in_w / 2;
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
@@ -1445,12 +1471,12 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
begin
return func_dp_stream_reconcat(snk_in, in_w, out_w, nof_data, data_representation, true);
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_src_out_arr : t_dp_sosi_arr(snk_in_arr'range) := snk_in_arr;
begin
for i in v_src_out_arr'range loop
@@ -1459,13 +1485,13 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
begin
return func_dp_stream_reconcat(snk_in_arr, in_w, out_w, nof_data, data_representation, true);
end;
-- Deconcatenate data from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out_arr : t_dp_sosi_arr(nof_streams - 1 downto 0);
begin
@@ -1481,7 +1507,7 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
begin
return src_out_arr(0);
end;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index d1ec55fe6f..adae931402 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
@@ -46,12 +46,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -74,9 +74,17 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0',
+ '0',
+ '0',
+ '0',
+ (others => '0'),
+ '0',
+ '0',
+ (others => '0'),
+ '0'
+ );
------------------------------------------------------------------------------
-- Definitions for eth demux udp
@@ -185,16 +193,16 @@ package eth_pkg is
constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
-- Register mapping functions
- function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
- function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
- function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
- function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
- function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
- function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
- function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
- function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
+ function func_eth_mm_reg_demux ( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
+ function func_eth_mm_reg_demux ( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
+ function func_eth_mm_reg_config ( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
+ function func_eth_mm_reg_config ( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
+ function func_eth_mm_reg_control (mm_reg : std_logic_vector) return t_eth_mm_reg_control;
+ function func_eth_mm_reg_control (mm_reg : t_eth_mm_reg_control) return std_logic_vector;
+ function func_eth_mm_reg_frame ( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
+ function func_eth_mm_reg_frame ( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
+ function func_eth_mm_reg_status ( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
+ function func_eth_mm_reg_status ( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
------------------------------------------------------------------------------
-- Definitions for eth_mm_registers
@@ -223,7 +231,7 @@ end eth_pkg;
package body eth_pkg is
-- Register mapping functions
- function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
+ function func_eth_mm_reg_demux (mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
begin
-- Demux UDP MM registers
@@ -234,7 +242,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_demux;
- function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
+ function func_eth_mm_reg_demux (mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -246,7 +254,7 @@ package body eth_pkg is
end func_eth_mm_reg_demux;
-- MM config register
- function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
+ function func_eth_mm_reg_config (mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
@@ -256,7 +264,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_config;
- function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
+ function func_eth_mm_reg_config (mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -268,7 +276,7 @@ package body eth_pkg is
end func_eth_mm_reg_config;
-- MM control register
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
+ function func_eth_mm_reg_control (mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
@@ -279,7 +287,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
+ function func_eth_mm_reg_control (mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -292,7 +300,7 @@ package body eth_pkg is
end func_eth_mm_reg_control;
-- MM frame register
- function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
+ function func_eth_mm_reg_frame (mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
@@ -308,7 +316,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_frame;
- function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
+ function func_eth_mm_reg_frame (mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -326,7 +334,7 @@ package body eth_pkg is
end func_eth_mm_reg_frame;
-- MM status register
- function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
+ function func_eth_mm_reg_status (mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
@@ -337,7 +345,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
- function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
+ function func_eth_mm_reg_status (mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 2eb92cbc7d..e8bb8d4283 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index 3c94c1901f..274d14a577 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index 3fc6ebb7a2..d49ba9d9fb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
@@ -86,9 +86,11 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -135,13 +137,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
c_network_ip_identification_len + c_network_ip_flags_fragment_len +
c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
c_network_ip_addr_len +
c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -175,11 +177,20 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001",
+ "0001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "001",
+ "0000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ARP Packet
@@ -216,12 +227,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -247,12 +258,17 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001",
+ "0000000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -301,8 +317,13 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- UDP Packet
@@ -327,7 +348,7 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
@@ -348,8 +369,12 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 9469fd2656..cfde8ebf26 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
@@ -165,315 +165,318 @@ package common_pkg is
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ function pow2 (n : natural) return natural; -- = 2**n
+ function ceil_pow2 (n : integer) return natural; -- = 2**n, returns 1 for n<0
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function true_log2 (n : natural) return natural; -- true_log2(n) = log2(n)
+ function ceil_log2 (n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
- function floor_log10(n : natural) return natural;
+ function floor_log10 (n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
+ function is_pow2 (n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function true_log_pow2 (n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio ( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio2 (n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
- function ceil_div( n : unsigned; d: natural) return unsigned;
- function ceil_value( n : unsigned; d: natural) return unsigned;
- function floor_value(n : unsigned; d: natural) return unsigned;
+ function ceil_div ( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_value ( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
+ function floor_value (n, d : natural) return natural; -- floor_value = (n/d) * d
+ function ceil_div ( n : unsigned; d: natural) return unsigned;
+ function ceil_value ( n : unsigned; d: natural) return unsigned;
+ function floor_value (n : unsigned; d: natural) return unsigned;
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+ function slv (n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
+ function sl ( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
- function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
- function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr;
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr;
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr;
+ function to_slv_32_arr ( n : t_integer_arr) return t_slv_32_arr;
+ function to_slv_32_arr ( n : t_natural_arr) return t_slv_32_arr;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_and (slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
+ function vector_or ( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
+ function vector_xor (slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
+ function andv (slv : std_logic_vector) return std_logic; -- alias of vector_and
+ function orv ( slv : std_logic_vector) return std_logic; -- alias of vector_or
+ function xorv (slv : std_logic_vector) return std_logic; -- alias of vector_xor
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
+ function matrix_or ( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
- function smallest(n, m : integer) return integer;
- function smallest(n, m, l : integer) return integer;
- function smallest(n : t_natural_arr) return natural;
+ function smallest (n, m : integer) return integer;
+ function smallest (n, m, l : integer) return integer;
+ function smallest (n : t_natural_arr) return natural;
- function largest(n, m : integer) return integer;
- function largest(n : t_natural_arr) return natural;
+ function largest (n, m : integer) return integer;
+ function largest (n : t_natural_arr) return natural;
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
- function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
- function func_product(n : t_nat_natural_arr) return natural;
+ function func_sum ( n : t_natural_arr) return natural; -- sum of all elements in array
+ function func_sum ( n : t_nat_natural_arr) return natural;
+ function func_product (n : t_natural_arr) return natural; -- product of all elements in array
+ function func_product (n : t_nat_natural_arr) return natural;
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
+ function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
-
- function is_true(a : std_logic) return boolean;
- function is_true(a : std_logic) return natural;
- function is_true(a : boolean) return std_logic;
- function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
-
- function sel_a_b(sel, a, b : boolean) return boolean;
- function sel_a_b(sel, a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : real) return real;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : signed) return signed;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
- function sel_a_b(sel : boolean; a, b : string) return string;
- function sel_a_b(sel : integer; a, b : string) return string;
- function sel_a_b(sel : boolean; a, b : time) return time;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+
+ function is_true (a : std_logic) return boolean;
+ function is_true (a : std_logic) return natural;
+ function is_true (a : boolean) return std_logic;
+ function is_true (a : boolean) return natural;
+ function is_true (a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true (a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+
+ function sel_a_b (sel, a, b : boolean) return boolean;
+ function sel_a_b (sel, a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : real) return real;
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : signed) return signed;
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned;
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
+ function sel_a_b (sel : boolean; a, b : string) return string;
+ function sel_a_b (sel : integer; a, b : string) return string;
+ function sel_a_b (sel : boolean; a, b : time) return time;
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
- function array_init(init, nof, incr : natural) return t_nat_natural_arr;
- function array_init(init, nof, incr : integer) return t_slv_16_arr;
- function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
-
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ function sel_n (sel : natural; a, b, c : boolean) return boolean; -- 3
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
+
+ function sel_n (sel : natural; a, b, c : integer) return integer; -- 3
+ function sel_n (sel : natural; a, b, c, d : integer) return integer; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
+
+ function sel_n (sel : natural; a, b : string) return string; -- 2
+ function sel_n (sel : natural; a, b, c : string) return string; -- 3
+ function sel_n (sel : natural; a, b, c, d : string) return string; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : string) return string; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr;
+ function array_init (init, nof, incr : integer) return t_slv_16_arr;
+ function array_init (init, nof, incr : integer) return t_slv_32_arr;
+ function array_init (init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init (init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_sinit (init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
-
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
- function TO_SINT(vec : std_logic_vector) return integer;
-
- function TO_UVEC(dec, w : natural) return std_logic_vector;
- function TO_SVEC(dec, w : integer) return std_logic_vector;
-
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
-
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+
+ function TO_UINT (vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_SINT (vec : std_logic_vector) return integer;
+
+ function TO_UVEC (dec, w : natural) return std_logic_vector;
+ function TO_SVEC (dec, w : integer) return std_logic_vector;
+
+ function TO_SVEC_32 (dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
-- happens for RESIZE of UNSIGNED. Therefor this is what the RESIZE_NUM for SIGNED and the RESIZE_SVEC do
-- and better not use RESIZE for SIGNED anymore.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
-
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
-
- function offset_binary(a : std_logic_vector) return std_logic_vector;
-
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
-
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
-
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
-
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
-
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
-
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
-
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
- function flip(a : t_slv_32_arr) return t_slv_32_arr;
- function flip(a : t_integer_arr) return t_integer_arr;
- function flip(a : t_natural_arr) return t_natural_arr;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
-
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
-
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
-
- function pad(str: string; width: natural; pad_char: character) return string;
-
- function slice_up(str: string; width: natural; i: natural) return string;
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string;
- function slice_dn(str: string; width: natural; i: natural) return string;
-
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
+ function RESIZE_NUM ( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM ( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
+ function RESIZE_UINT (u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
+ function RESIZE_SINT (s : integer; w : natural) return integer; -- extend sign bit or keep LS part
+
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector;
+ -- Used in common_add_sub.vhd
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+
+ function offset_binary (a : std_logic_vector) return std_logic_vector;
+
+ function truncate ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function scale ( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
+ function scale_and_resize_uvec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_svec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function truncate_or_resize_uvec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_svec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
+
+ function s_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round_up (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
+ function s_round_up (vec : std_logic_vector; n : natural) return std_logic_vector; -- idem but round up to +infinity (s_round_up = u_round)
+ function u_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
+ function u_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
+
+ function u_to_s (u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function s_to_u (s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+
+ function u_wrap (u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function s_wrap (s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+
+ function u_clip (u : natural; max : natural) return natural; -- if s < max return s, else return n
+ function s_clip (s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip (s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
+
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
+ function hton (a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh (a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+
+ function flip (a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
+ function flip (a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip (a : t_slv_32_arr) return t_slv_32_arr;
+ function flip (a : t_integer_arr) return t_integer_arr;
+ function flip (a : t_natural_arr) return t_natural_arr;
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr;
+
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
+
+ function pad (str: string; width: natural; pad_char: character) return string;
+
+ function slice_up (str: string; width: natural; i: natural) return string;
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string;
+ function slice_dn (str: string; width: natural; i: natural) return string;
+
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
------------------------------------------------------------------------------
-- Component specific functions
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
- function func_common_reorder2_is_there(I, J : natural) return boolean;
- function func_common_reorder2_is_active(I, J, N : natural) return boolean;
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer;
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural;
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
+ function func_common_reorder2_is_there (I, J : natural) return boolean;
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean;
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer;
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural;
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
- function pow2(n : natural) return natural is
+ function pow2 (n : natural) return natural is
begin
return 2**n;
end;
- function ceil_pow2(n : integer) return natural is
+ function ceil_pow2 (n : integer) return natural is
-- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
- function true_log2(n : natural) return natural is
+ function true_log2 (n : natural) return natural is
-- Purpose: For calculating extra vector width of existing vector
-- Description: Return mathematical ceil(log2(n))
-- n log2()
@@ -492,7 +495,7 @@ package body common_pkg is
return natural(integer(ceil(log2(real(n)))));
end;
- function ceil_log2(n : natural) return natural is
+ function ceil_log2 (n : natural) return natural is
-- Purpose: For calculating vector width of new vector
-- Description:
-- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
@@ -510,22 +513,22 @@ package body common_pkg is
end if;
end;
- function floor_log10(n : natural) return natural is
+ function floor_log10 (n : natural) return natural is
begin
return natural(integer(floor(log10(real(n)))));
end;
- function is_pow2(n : natural) return boolean is
+ function is_pow2 (n : natural) return boolean is
begin
return n = 2**true_log2(n);
end;
- function true_log_pow2(n : natural) return natural is
+ function true_log_pow2 (n : natural) return natural is
begin
return 2**true_log2(n);
end;
- function ratio(n, d : natural) return natural is
+ function ratio (n, d : natural) return natural is
begin
if n mod d = 0 then
return n / d;
@@ -534,32 +537,32 @@ package body common_pkg is
end if;
end;
- function ratio2(n, m : natural) return natural is
+ function ratio2 (n, m : natural) return natural is
begin
return largest(ratio(n,m), ratio(m,n));
end;
- function ceil_div(n, d : natural) return natural is
+ function ceil_div (n, d : natural) return natural is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
- function ceil_value(n, d : natural) return natural is
+ function ceil_value (n, d : natural) return natural is
begin
return ceil_div(n, d) * d;
end;
- function floor_value(n, d : natural) return natural is
+ function floor_value (n, d : natural) return natural is
begin
return (n / d) * d;
end;
- function ceil_div(n : unsigned; d: natural) return unsigned is
+ function ceil_div (n : unsigned; d: natural) return unsigned is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
end;
- function ceil_value(n : unsigned; d: natural) return unsigned is
+ function ceil_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -567,7 +570,7 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function floor_value(n : unsigned; d: natural) return unsigned is
+ function floor_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -575,21 +578,21 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function slv(n: in std_logic) return std_logic_vector is
+ function slv (n: in std_logic) return std_logic_vector is
variable r : std_logic_vector(0 downto 0);
begin
r(0) := n;
return r;
end;
- function sl(n: in std_logic_vector) return std_logic is
+ function sl (n: in std_logic_vector) return std_logic is
variable r : std_logic;
begin
r := n(n'low);
return r;
end;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr is
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -607,7 +610,7 @@ package body common_pkg is
return vR;
end;
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr is
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr is
variable vN : t_nat_natural_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -618,7 +621,7 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_integer_arr(n'length - 1 downto 0);
begin
@@ -629,14 +632,14 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return to_integer_arr(vN);
end;
- function to_slv_32_arr(n : t_integer_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_integer_arr) return t_slv_32_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -647,7 +650,7 @@ package body common_pkg is
return vR;
end;
- function to_slv_32_arr(n : t_natural_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_natural_arr) return t_slv_32_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -658,7 +661,7 @@ package body common_pkg is
return vR;
end;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic is
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic is
-- Linear loop to determine result takes combinatorial delay that is proportional to slv'LENGTH:
-- FOR I IN slv'RANGE LOOP
-- v_result := v_result OPERATION slv(I);
@@ -691,22 +694,22 @@ package body common_pkg is
return v_stage_arr(c_nof_stages - 1)(0);
end;
- function vector_and(slv : std_logic_vector) return std_logic is
+ function vector_and (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function vector_or(slv : std_logic_vector) return std_logic is
+ function vector_or (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function vector_xor(slv : std_logic_vector) return std_logic is
+ function vector_xor (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector is
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector is
variable v_one_hot : boolean := false;
variable v_zeros : std_logic_vector(slv'range) := (others => '0');
begin
@@ -725,22 +728,22 @@ package body common_pkg is
return slv;
end;
- function andv(slv : std_logic_vector) return std_logic is
+ function andv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function orv(slv : std_logic_vector) return std_logic is
+ function orv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function xorv(slv : std_logic_vector) return std_logic is
+ function xorv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '1';
begin
@@ -752,7 +755,7 @@ package body common_pkg is
return v_result;
end;
- function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_or (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '0';
begin
@@ -764,7 +767,7 @@ package body common_pkg is
return v_result;
end;
- function smallest(n, m : integer) return integer is
+ function smallest (n, m : integer) return integer is
begin
if n < m then
return n;
@@ -773,16 +776,16 @@ package body common_pkg is
end if;
end;
- function smallest(n, m, l : integer) return integer is
+ function smallest (n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
end;
- function smallest(n : t_natural_arr) return natural is
+ function smallest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -793,7 +796,7 @@ package body common_pkg is
return m;
end;
- function largest(n, m : integer) return integer is
+ function largest (n, m : integer) return integer is
begin
if n > m then
return n;
@@ -802,7 +805,7 @@ package body common_pkg is
end if;
end;
- function largest(n : t_natural_arr) return natural is
+ function largest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -813,7 +816,7 @@ package body common_pkg is
return m;
end;
- function func_sum(n : t_natural_arr) return natural is
+ function func_sum (n : t_natural_arr) return natural is
variable vS : natural;
begin
vS := 0;
@@ -823,14 +826,14 @@ package body common_pkg is
return vS;
end;
- function func_sum(n : t_nat_natural_arr) return natural is
+ function func_sum (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return func_sum(vN);
end;
- function func_product(n : t_natural_arr) return natural is
+ function func_product (n : t_natural_arr) return natural is
variable vP : natural;
begin
vP := 1;
@@ -840,7 +843,7 @@ package body common_pkg is
return vP;
end;
- function func_product(n : t_nat_natural_arr) return natural is
+ function func_product (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
@@ -999,14 +1002,14 @@ package body common_pkg is
return vP;
end;
- function is_true(a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
- function is_true(a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
- function is_true(a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
- function is_true(a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
- function is_true(a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
- function is_true(a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
+ function is_true (a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
+ function is_true (a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
+ function is_true (a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
+ function is_true (a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
+ function is_true (a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
+ function is_true (a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
- function sel_a_b(sel, a, b : integer) return integer is
+ function sel_a_b (sel, a, b : integer) return integer is
begin
if sel /= 0 then
return a;
@@ -1015,7 +1018,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel, a, b : boolean) return boolean is
+ function sel_a_b (sel, a, b : boolean) return boolean is
begin
if sel = true then
return a;
@@ -1024,7 +1027,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : integer) return integer is
+ function sel_a_b (sel : boolean; a, b : integer) return integer is
begin
if sel = true then
return a;
@@ -1033,7 +1036,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : real) return real is
+ function sel_a_b (sel : boolean; a, b : real) return real is
begin
if sel = true then
return a;
@@ -1042,7 +1045,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic is
begin
if sel = true then
return a;
@@ -1051,7 +1054,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic is
begin
if sel /= 0 then
return a;
@@ -1060,7 +1063,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector is
begin
if sel /= 0 then
return a;
@@ -1069,7 +1072,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
if sel = true then
return a;
@@ -1078,7 +1081,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : signed) return signed is
+ function sel_a_b (sel : boolean; a, b : signed) return signed is
begin
if sel = true then
return a;
@@ -1087,7 +1090,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned is
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned is
begin
if sel = true then
return a;
@@ -1096,7 +1099,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr is
begin
if sel = true then
return a;
@@ -1105,7 +1108,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr is
begin
if sel = true then
return a;
@@ -1114,7 +1117,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
begin
if sel = true then
return a;
@@ -1123,7 +1126,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
begin
if sel = true then
return a;
@@ -1132,7 +1135,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : string) return string is
+ function sel_a_b (sel : boolean; a, b : string) return string is
begin
if sel = true then
return a;
@@ -1141,7 +1144,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : string) return string is
+ function sel_a_b (sel : integer; a, b : string) return string is
begin
if sel /= 0 then
return a;
@@ -1150,7 +1153,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : time) return time is
+ function sel_a_b (sel : boolean; a, b : time) return time is
begin
if sel = true then
return a;
@@ -1159,7 +1162,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level is
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level is
begin
if sel = true then
return a;
@@ -1169,115 +1172,115 @@ package body common_pkg is
end;
-- sel_n : boolean
- function sel_n(sel : natural; a, b, c : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : integer
- function sel_n(sel : natural; a, b, c : integer) return integer is
+ function sel_n (sel : natural; a, b, c : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : string
- function sel_n(sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
- function sel_n(sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
- function sel_n(sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
- function sel_n(sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector is
+ function sel_n (sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
+ function sel_n (sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
+ function sel_n (sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector is
variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1286,7 +1289,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_natural_arr is
+ function array_init (init, nof : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1295,7 +1298,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_nat_natural_arr is
+ function array_init (init, nof : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1304,7 +1307,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_natural_arr is
+ function array_init (init, nof, incr : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1316,7 +1319,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_nat_natural_arr is
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1328,7 +1331,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_16_arr is
+ function array_init (init, nof, incr : integer) return t_slv_16_arr is
variable v_arr : t_slv_16_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1340,7 +1343,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_32_arr is
+ function array_init (init, nof, incr : integer) return t_slv_32_arr is
variable v_arr : t_slv_32_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1352,7 +1355,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width : natural) return std_logic_vector is
+ function array_init (init, nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1361,7 +1364,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width, incr : natural) return std_logic_vector is
+ function array_init (init, nof, width, incr : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
variable v_i : natural;
begin
@@ -1373,7 +1376,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
+ function array_sinit (init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1382,7 +1385,7 @@ package body common_pkg is
return v_arr;
end;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix is
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix is
variable v_mat : t_slv_64_matrix(nof_a - 1 downto 0, nof_b - 1 downto 0);
begin
for I in 0 to nof_a - 1 loop
@@ -1395,7 +1398,7 @@ package body common_pkg is
-- Support concatenation of up to 7 slv into 1 slv
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length;
variable v_res : std_logic_vector(c_max_w - 1 downto 0) := (others => '0');
variable v_len : natural := 0;
@@ -1410,32 +1413,32 @@ package body common_pkg is
return v_res(v_len - 1 downto 0);
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, false, a, b, c, d, e, f, "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, false, false, a, b, c, d, e, "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, false, false, false, a, b, c, d, "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, false, false, false, false, a, b, c, "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, false, false, false, false, false, a, b, "0", "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
variable v_len : natural := 0;
begin
if use_a = true then v_len := v_len + a_w; end if;
@@ -1448,33 +1451,33 @@ package body common_pkg is
return v_len;
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, false, a_w, b_w, c_w, d_w, e_w, f_w, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0);
end func_slv_concat_w;
-- extract slv
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
variable v_w : natural := 0;
variable v_lo : natural := 0;
begin
@@ -1520,64 +1523,64 @@ package body common_pkg is
return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, false, a_w, b_w, c_w, d_w, e_w, f_w, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function TO_UINT(vec : std_logic_vector) return natural is
+ function TO_UINT (vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
end;
- function TO_SINT(vec : std_logic_vector) return integer is
+ function TO_SINT (vec : std_logic_vector) return integer is
begin
return to_integer(signed(vec));
end;
- function TO_UVEC(dec, w : natural) return std_logic_vector is
+ function TO_UVEC (dec, w : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(dec, w));
end;
- function TO_SVEC(dec, w : integer) return std_logic_vector is
+ function TO_SVEC (dec, w : integer) return std_logic_vector is
begin
return std_logic_vector(to_signed(dec, w));
end;
- function TO_SVEC_32(dec : integer) return std_logic_vector is
+ function TO_SVEC_32 (dec : integer) return std_logic_vector is
begin
return TO_SVEC(dec, 32);
end;
- function RESIZE_NUM(u : unsigned; w : natural) return unsigned is
+ function RESIZE_NUM (u : unsigned; w : natural) return unsigned is
begin
-- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
return resize(u, w);
end;
- function RESIZE_NUM(s : signed; w : natural) return signed is
+ function RESIZE_NUM (s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
if w > s'length then
@@ -1587,47 +1590,47 @@ package body common_pkg is
end if;
end;
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector is
variable v_slv0 : std_logic_vector(w - 1 downto 1) := (others => '0');
begin
return v_slv0 & sl;
end;
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(vec), w));
end;
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(vec), w));
end;
- function RESIZE_UINT(u : integer; w : natural) return integer is
+ function RESIZE_UINT (u : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_UVEC(u, c_word_w);
return TO_UINT(v(w - 1 downto 0));
end;
- function RESIZE_SINT(s : integer; w : natural) return integer is
+ function RESIZE_SINT (s : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_SVEC(s, c_word_w);
return TO_SINT(v(w - 1 downto 0));
end;
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, 32);
end;
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, 32);
end;
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
if dec < 0 then
@@ -1639,74 +1642,74 @@ package body common_pkg is
end if;
end;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector is
begin
return std_logic_vector(unsigned(vec) + dec);
end;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
return std_logic_vector(signed(vec) + v_dec); -- uses function "+" (L : SIGNED, R : INTEGER)
end;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector is
begin
return std_logic_vector(signed(vec) + dec);
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) + signed(r_vec));
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) - signed(r_vec));
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) + unsigned(r_vec));
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_SVEC(l_vec, r_vec, l_vec'length);
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_UVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_UVEC(l_vec, r_vec, l_vec'length);
end;
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_re * b_re - a_im * b_im);
end;
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_im * b_re + a_re * b_im);
end;
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
@@ -1715,7 +1718,7 @@ package body common_pkg is
end if;
end;
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
@@ -1741,24 +1744,24 @@ package body common_pkg is
-- The offset_binary() mapping can be done and undone both ways.
-- The offset_binary() mapping to two-complement binary yields a DC offset
-- of -0.5 Lsb.
- function offset_binary(a : std_logic_vector) return std_logic_vector is
+ function offset_binary (a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
- function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function truncate (vec : std_logic_vector; n : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -1769,7 +1772,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -1780,7 +1783,7 @@ package body common_pkg is
return v_res;
end;
- function scale(vec : std_logic_vector; n: natural) return std_logic_vector is
+ function scale (vec : std_logic_vector; n: natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1789,7 +1792,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1800,7 +1803,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -1811,7 +1814,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_uvec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_uvec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -1824,7 +1827,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_svec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_svec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -1856,7 +1859,7 @@ package body common_pkg is
-- maximum product is -8*-8=+64 <= 127-8, so wrapping due to rounding
-- overflow will never occur.
- function s_round(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
-- Use SIGNED to avoid NATURAL (32 bit range) overflow error
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
@@ -1884,24 +1887,24 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return s_round(vec, n, false); -- no round clip
end;
-- An alternative is to always round up, also for negative numbers (i.e. s_round_up = u_round).
- function s_round_up(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round_up (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
begin
return u_round(vec, n, clip);
end;
- function s_round_up(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round_up (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
-- Unsigned numbers are round up (almost same as s_round, but without the else on negative vec)
- function u_round(vec : std_logic_vector; n : natural; clip : boolean ) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural; clip : boolean ) return std_logic_vector is
-- Use UNSIGNED to avoid NATURAL (32 bit range) overflow error
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
@@ -1925,36 +1928,36 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
- function u_to_s(u : natural; w : natural) return integer is
+ function u_to_s (u : natural; w : natural) return integer is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
- function s_to_u(s : integer; w : natural) return natural is
+ function s_to_u (s : integer; w : natural) return natural is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
- function u_wrap(u : natural; w : natural) return natural is
+ function u_wrap (u : natural; w : natural) return natural is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
- function s_wrap(s : integer; w : natural) return integer is
+ function s_wrap (s : integer; w : natural) return integer is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
- function u_clip(u : natural; max : natural) return natural is
+ function u_clip (u : natural; max : natural) return natural is
begin
if u > max then
return max;
@@ -1963,7 +1966,7 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural; min : integer) return integer is
+ function s_clip (s : integer; max : natural; min : integer) return integer is
begin
if s < min then
return min;
@@ -1976,12 +1979,12 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural) return integer is
+ function s_clip (s : integer; max : natural) return integer is
begin
return s_clip(s, max, -max);
end;
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
variable vL : natural;
@@ -1997,28 +2000,28 @@ package body common_pkg is
return v_b;
end function;
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
end function;
- function hton(a : std_logic_vector) return std_logic_vector is
+ function hton (a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
end function;
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, sz); -- i.e. ntoh() = hton()
end function;
- function ntoh(a : std_logic_vector) return std_logic_vector is
+ function ntoh (a : std_logic_vector) return std_logic_vector is
begin
return hton(a); -- i.e. ntoh() = hton()
end function;
- function flip(a : std_logic_vector) return std_logic_vector is
+ function flip (a : std_logic_vector) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2028,12 +2031,12 @@ package body common_pkg is
return v_b;
end;
- function flip(a, w : natural) return natural is
+ function flip (a, w : natural) return natural is
begin
return TO_UINT(flip(TO_UVEC(a, w)));
end;
- function flip(a : t_slv_32_arr) return t_slv_32_arr is
+ function flip (a : t_slv_32_arr) return t_slv_32_arr is
variable v_a : t_slv_32_arr(a'length - 1 downto 0) := a;
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
@@ -2043,7 +2046,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_integer_arr) return t_integer_arr is
+ function flip (a : t_integer_arr) return t_integer_arr is
variable v_a : t_integer_arr(a'length - 1 downto 0) := a;
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
@@ -2053,7 +2056,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_natural_arr) return t_natural_arr is
+ function flip (a : t_natural_arr) return t_natural_arr is
variable v_a : t_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
@@ -2063,7 +2066,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr is
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr is
variable v_a : t_nat_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
@@ -2073,7 +2076,7 @@ package body common_pkg is
return v_b;
end;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector is
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2087,7 +2090,7 @@ package body common_pkg is
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
variable vI : natural;
variable vJ : natural;
begin
@@ -2096,7 +2099,7 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
@@ -2111,34 +2114,34 @@ package body common_pkg is
end loop;
end;
- function pad(str: string; width: natural; pad_char: character) return string is
+ function pad (str: string; width: natural; pad_char: character) return string is
variable v_str : string(1 to width) := (others => pad_char);
begin
v_str(width - str'length + 1 to width) := str;
return v_str;
end;
- function slice_up(str: string; width: natural; i: natural) return string is
+ function slice_up (str: string; width: natural; i: natural) return string is
begin
return str(i * width + 1 to (i + 1) * width);
end;
-- If the input value is not a multiple of the desired width, the return value is padded with
-- the passed pad value. E.g. if input='10' and desired width is 4, return value is '0010'.
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string is
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
- function slice_dn(str: string; width: natural; i: natural) return string is
+ function slice_dn (str: string; width: natural; i: natural) return string is
begin
return str((i + 1) * width - 1 downto i * width);
end;
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
for i in 0 to nof_elements - 1 loop
@@ -2152,16 +2155,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2174,7 +2178,7 @@ package body common_pkg is
assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
- --synthesis translate_on
+ --synthesis translate_on
end procedure proc_common_fifo_asserts;
@@ -2182,8 +2186,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2204,7 +2209,7 @@ package body common_pkg is
------------------------------------------------------------------------------
-- Determine whether the stage I and row J index refer to any (active or redundant) 2-input reorder cell instantiation
- function func_common_reorder2_is_there(I, J : natural) return boolean is
+ function func_common_reorder2_is_there (I, J : natural) return boolean is
variable v_odd : boolean;
variable v_even : boolean;
begin
@@ -2214,7 +2219,7 @@ package body common_pkg is
end func_common_reorder2_is_there;
-- Determine whether the stage I and row J index refer to an active 2-input reorder cell instantiation in a reorder network with N stages
- function func_common_reorder2_is_active(I, J, N : natural) return boolean is
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean is
variable v_inst : boolean;
variable v_act : boolean;
begin
@@ -2224,7 +2229,7 @@ package body common_pkg is
end func_common_reorder2_is_active;
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer is
constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
@@ -2246,7 +2251,7 @@ package body common_pkg is
end func_common_reorder2_get_select_index;
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -2261,7 +2266,7 @@ package body common_pkg is
end func_common_reorder2_get_select;
-- Determine the inverse of a reorder network by using two reorder networks in series
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -2287,8 +2292,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2327,9 +2332,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
@@ -2354,7 +2360,7 @@ package body common_pkg is
end if;
wait for v_speriod / 2;
SCLK <= '1';
- -- Wait for next DCLK
+ -- Wait for next DCLK
end loop;
wait;
end proc_common_dclk_generate_sclk;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 40128fea21..0fa106e866 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
@@ -121,15 +121,33 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_bsn_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ '1',
+ '1',
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_empty_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_channel_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_error_w)
+ );
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -208,30 +226,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -240,142 +262,142 @@ package dp_stream_pkg is
-- Typically the sosi data are treated as unsigned in the record field, so extended with '0'. However for interpretating
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
- function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
- function TO_DP_EMPTY( n : natural) return std_logic_vector;
- function TO_DP_CHANNEL( n : natural) return std_logic_vector;
- function TO_DP_ERROR( n : natural) return std_logic_vector;
- function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
- function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
-
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
-
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
-
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
+ function TO_DP_BSN ( n : natural) return std_logic_vector;
+ function TO_DP_DATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_SDATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
+ function TO_DP_UDATA ( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector; -- for re and im fields, signed data
+ function TO_DP_DSP_UDATA (n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_EMPTY ( n : natural) return std_logic_vector;
+ function TO_DP_CHANNEL ( n : natural) return std_logic_vector;
+ function TO_DP_ERROR ( n : natural) return std_logic_vector;
+ function RESIZE_DP_BSN ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_DATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
+ function RESIZE_DP_SDATA ( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
+ function RESIZE_DP_XDATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_EMPTY ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_CHANNEL ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_ERROR ( vec : std_logic_vector) return std_logic_vector;
+
+ function INCR_DP_DATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
+ function INCR_DP_SDATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+
+ function REPLICATE_DP_DATA ( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
-- Shift and combine part of previous data and this data, use the other sosi from prev_sosi
- function func_dp_data_shift( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
+ function func_dp_data_shift ( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
+ function func_dp_data_shift_last ( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
-- Determine resulting empty if two streams are concatenated or split
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi;
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi;
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; str : string) return std_logic;
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector;
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
-- Fix reversed buses due to connecting TO to DOWNTO range arrays.
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr;
-- Functions to combinatorially hold the data fields and to set or reset the control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_info( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_control( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_reset_control( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_info ( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_control ( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reset_control ( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
-- Reset sosi ctrl and preserve the sosi data (to avoid unnecessary data toggling and to ease data view in Wave window)
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
-- Function to copy the BSN of one valid stream to all output streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
-- Functions to combinatorially handle the BSN field
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
-- Functions to combine sosi fields
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi;
-- Functions to convert sosi fields
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
-- Functions to set the DATA, RE and IM field in a stream.
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
-
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
-
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
+
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -384,14 +406,14 @@ package dp_stream_pkg is
-- . data_order_im_re = TRUE then "COMPLEX" data = im&re
-- FALSE then "COMPLEX" data = re&im
-- ignore when data_representation /= "COMPLEX"
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
end dp_stream_pkg;
@@ -399,11 +421,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -417,20 +440,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -448,118 +473,119 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
- function TO_DP_BSN(n : natural) return std_logic_vector is
+ function TO_DP_BSN (n : natural) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_bsn_w);
end TO_DP_BSN;
- function TO_DP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_DATA;
- function TO_DP_SDATA(n : integer) return std_logic_vector is
+ function TO_DP_SDATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_SDATA;
- function TO_DP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_UDATA (n : integer) return std_logic_vector is
begin
return TO_DP_DATA(n);
end TO_DP_UDATA;
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_DATA;
- function TO_DP_DSP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_UDATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_UDATA;
- function TO_DP_EMPTY(n : natural) return std_logic_vector is
+ function TO_DP_EMPTY (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_empty_w);
end TO_DP_EMPTY;
- function TO_DP_CHANNEL(n : natural) return std_logic_vector is
+ function TO_DP_CHANNEL (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_channel_w);
end TO_DP_CHANNEL;
- function TO_DP_ERROR(n : natural) return std_logic_vector is
+ function TO_DP_ERROR (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_error_w);
end TO_DP_ERROR;
- function RESIZE_DP_BSN(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_BSN (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_bsn_w);
end RESIZE_DP_BSN;
- function RESIZE_DP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_DATA;
- function RESIZE_DP_SDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_SDATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_SDATA;
- function RESIZE_DP_XDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_XDATA (vec : std_logic_vector) return std_logic_vector is
variable v_vec : std_logic_vector(c_dp_stream_data_w - 1 downto 0) := (others => 'X');
begin
v_vec(vec'length - 1 downto 0) := vec;
return v_vec;
end RESIZE_DP_XDATA;
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_dsp_data_w);
end RESIZE_DP_DSP_DATA;
- function RESIZE_DP_EMPTY(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_EMPTY (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_empty_w);
end RESIZE_DP_EMPTY;
- function RESIZE_DP_CHANNEL(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_CHANNEL (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_channel_w);
end RESIZE_DP_CHANNEL;
- function RESIZE_DP_ERROR(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_ERROR (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_error_w);
end RESIZE_DP_ERROR;
- function INCR_DP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DATA(std_logic_vector(unsigned(vec(w - 1 downto 0)) + dec));
end INCR_DP_DATA;
- function INCR_DP_SDATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_SDATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_SDATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_SDATA;
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DSP_DATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_DSP_DATA;
- function REPLICATE_DP_DATA(seq : std_logic_vector) return std_logic_vector is
+ function REPLICATE_DP_DATA (seq : std_logic_vector) return std_logic_vector is
constant c_seq_w : natural := seq'length;
constant c_nof_replications : natural := ceil_div(c_dp_stream_data_w, c_seq_w);
constant c_vec_w : natural := ceil_value(c_dp_stream_data_w, c_seq_w);
@@ -571,7 +597,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
@@ -590,7 +616,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -608,7 +634,7 @@ package body dp_stream_pkg is
end TO_DP_SOSI_UNSIGNED;
-- Keep part of head data and combine part of tail data
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
@@ -625,7 +651,7 @@ package body dp_stream_pkg is
-- Shift and combine part of previous data and this data,
- function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
+ function func_dp_data_shift (prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
@@ -658,7 +684,7 @@ package body dp_stream_pkg is
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
+ function func_dp_data_shift_last (tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
variable vL : natural := input_empty;
variable vN : natural := nof_symbols_per_data;
@@ -688,7 +714,7 @@ package body dp_stream_pkg is
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(head_empty);
@@ -700,7 +726,7 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_concat;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(input_empty);
@@ -715,7 +741,7 @@ package body dp_stream_pkg is
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
begin
for I in dp'range loop
@@ -729,7 +755,7 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -751,7 +777,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -775,19 +801,19 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -809,7 +835,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -833,13 +859,13 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
@@ -847,7 +873,7 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -860,7 +886,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -875,19 +901,19 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -899,7 +925,7 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -915,7 +941,7 @@ package body dp_stream_pkg is
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -928,7 +954,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -941,7 +967,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -954,7 +980,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -967,7 +993,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -980,7 +1006,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -993,7 +1019,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1006,7 +1032,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1019,7 +1045,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr is
variable v_to_range : t_dp_siso_arr(0 to in_arr'high);
variable v_downto_range : t_dp_siso_arr(in_arr'high downto 0);
begin
@@ -1036,7 +1062,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_reverse_range;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_to_range : t_dp_sosi_arr(0 to in_arr'high);
variable v_downto_range : t_dp_sosi_arr(in_arr'high downto 0);
begin
@@ -1054,7 +1080,7 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reverse_range;
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
@@ -1062,7 +1088,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
- function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_info (dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi info
@@ -1074,7 +1100,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_info;
- function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_control (dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi control
@@ -1086,7 +1112,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_control;
- function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reset_control (dp : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- reset sosi control
@@ -1098,7 +1124,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_reset_control;
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp; -- hold sosi data
begin
-- reset sosi control
@@ -1110,7 +1136,7 @@ package body dp_stream_pkg is
end func_dp_stream_reset_control;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
begin
for I in dp'range loop
@@ -1123,13 +1149,13 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_max(dp, c_mask, w);
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
begin
for I in dp'range loop
@@ -1142,14 +1168,14 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_min;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_min(dp, c_mask, w);
end func_dp_stream_arr_bsn_min;
-- Function to copy the BSN number of one valid stream to all other streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
@@ -1166,14 +1192,14 @@ package body dp_stream_pkg is
-- Functions to combinatorially handle channels
- function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.channel := TO_UVEC(ch, c_dp_stream_channel_w);
return v_rec;
end func_dp_stream_channel_set;
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) /= ch then
@@ -1184,7 +1210,7 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_select;
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) = ch then
@@ -1196,7 +1222,7 @@ package body dp_stream_pkg is
end func_dp_stream_channel_remove;
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.err := TO_UVEC(n, c_dp_stream_error_w);
@@ -1204,7 +1230,7 @@ package body dp_stream_pkg is
end func_dp_stream_error_set;
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.bsn := RESIZE_DP_BSN(bsn);
@@ -1212,7 +1238,7 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
-- Combine sosi data with the sosi info fields
@@ -1225,7 +1251,7 @@ package body dp_stream_pkg is
end func_dp_stream_combine_info_and_data;
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
@@ -1242,23 +1268,23 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_slv_to_integer;
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1267,7 +1293,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1278,8 +1304,8 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_re : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1300,17 +1326,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_hi : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1333,17 +1359,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, 1, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1352,17 +1378,17 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1371,18 +1397,18 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, 1, true);
end;
-- Concatenate the data (and complex fields) from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out : t_dp_sosi := snk_in_arr(0);
begin
@@ -1397,7 +1423,7 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1407,7 +1433,7 @@ package body dp_stream_pkg is
end;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_in_w : natural := in_w / 2;
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
@@ -1445,12 +1471,12 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
begin
return func_dp_stream_reconcat(snk_in, in_w, out_w, nof_data, data_representation, true);
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_src_out_arr : t_dp_sosi_arr(snk_in_arr'range) := snk_in_arr;
begin
for i in v_src_out_arr'range loop
@@ -1459,13 +1485,13 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
begin
return func_dp_stream_reconcat(snk_in_arr, in_w, out_w, nof_data, data_representation, true);
end;
-- Deconcatenate data from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out_arr : t_dp_sosi_arr(nof_streams - 1 downto 0);
begin
@@ -1481,7 +1507,7 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
begin
return src_out_arr(0);
end;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index d1ec55fe6f..adae931402 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
@@ -46,12 +46,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -74,9 +74,17 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0',
+ '0',
+ '0',
+ '0',
+ (others => '0'),
+ '0',
+ '0',
+ (others => '0'),
+ '0'
+ );
------------------------------------------------------------------------------
-- Definitions for eth demux udp
@@ -185,16 +193,16 @@ package eth_pkg is
constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
-- Register mapping functions
- function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
- function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
- function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
- function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
- function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
- function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
- function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
- function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
+ function func_eth_mm_reg_demux ( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
+ function func_eth_mm_reg_demux ( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
+ function func_eth_mm_reg_config ( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
+ function func_eth_mm_reg_config ( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
+ function func_eth_mm_reg_control (mm_reg : std_logic_vector) return t_eth_mm_reg_control;
+ function func_eth_mm_reg_control (mm_reg : t_eth_mm_reg_control) return std_logic_vector;
+ function func_eth_mm_reg_frame ( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
+ function func_eth_mm_reg_frame ( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
+ function func_eth_mm_reg_status ( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
+ function func_eth_mm_reg_status ( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
------------------------------------------------------------------------------
-- Definitions for eth_mm_registers
@@ -223,7 +231,7 @@ end eth_pkg;
package body eth_pkg is
-- Register mapping functions
- function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
+ function func_eth_mm_reg_demux (mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
begin
-- Demux UDP MM registers
@@ -234,7 +242,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_demux;
- function func_eth_mm_reg_demux(mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
+ function func_eth_mm_reg_demux (mm_reg : t_eth_mm_reg_demux) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_demux_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -246,7 +254,7 @@ package body eth_pkg is
end func_eth_mm_reg_demux;
-- MM config register
- function func_eth_mm_reg_config(mm_reg : std_logic_vector) return t_eth_mm_reg_config is
+ function func_eth_mm_reg_config (mm_reg : std_logic_vector) return t_eth_mm_reg_config is
variable v_reg : t_eth_mm_reg_config;
begin
v_reg.udp_port := mm_reg(c_network_udp_port_w + 3 * c_word_w - 1 downto 3 * c_word_w); -- [15:0] = control UDP port number
@@ -256,7 +264,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_config;
- function func_eth_mm_reg_config(mm_reg : t_eth_mm_reg_config) return std_logic_vector is
+ function func_eth_mm_reg_config (mm_reg : t_eth_mm_reg_config) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_config_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -268,7 +276,7 @@ package body eth_pkg is
end func_eth_mm_reg_config;
-- MM control register
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control is
+ function func_eth_mm_reg_control (mm_reg : std_logic_vector) return t_eth_mm_reg_control is
variable v_reg : t_eth_mm_reg_control;
begin
v_reg.tx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
@@ -279,7 +287,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector is
+ function func_eth_mm_reg_control (mm_reg : t_eth_mm_reg_control) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_control_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -292,7 +300,7 @@ package body eth_pkg is
end func_eth_mm_reg_control;
-- MM frame register
- function func_eth_mm_reg_frame(mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
+ function func_eth_mm_reg_frame (mm_reg : std_logic_vector) return t_eth_mm_reg_frame is
variable v_reg : t_eth_mm_reg_frame;
begin
v_reg.is_dhcp := mm_reg( c_byte_w + 7); -- [15]
@@ -308,7 +316,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_frame;
- function func_eth_mm_reg_frame(mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
+ function func_eth_mm_reg_frame (mm_reg : t_eth_mm_reg_frame) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_frame_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
@@ -326,7 +334,7 @@ package body eth_pkg is
end func_eth_mm_reg_frame;
-- MM status register
- function func_eth_mm_reg_status(mm_reg : std_logic_vector) return t_eth_mm_reg_status is
+ function func_eth_mm_reg_status (mm_reg : std_logic_vector) return t_eth_mm_reg_status is
variable v_reg : t_eth_mm_reg_status;
begin
v_reg.rx_nof_words := mm_reg(c_eth_max_frame_nof_words_w + c_eth_empty_w + 16 - 1 downto c_eth_empty_w + 16); -- [29:18]
@@ -337,7 +345,7 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
- function func_eth_mm_reg_status(mm_reg : t_eth_mm_reg_status) return std_logic_vector is
+ function func_eth_mm_reg_status (mm_reg : t_eth_mm_reg_status) return std_logic_vector is
variable v_reg : std_logic_vector(c_eth_reg_status_nof_words * c_word_w - 1 downto 0);
begin
v_reg := (others => '0'); -- rsvd
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 2eb92cbc7d..e8bb8d4283 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 5508d1789d..49cec362a2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_avs_eth_0 is
+ component qsys_unb2b_minimal_avs_eth_0 is
port (
coe_clk_export : out std_logic; -- export
ins_interrupt_irq : out std_logic; -- irq
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index 69ff39c0a0..f5f9738149 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_clk_0 is
+ component qsys_unb2b_minimal_clk_0 is
port (
clk_out : out std_logic; -- clk
in_clk : in std_logic := 'X'; -- clk
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 6d24dae5a9..f0ba7ef983 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_cpu_0 is
+ component qsys_unb2b_minimal_cpu_0 is
port (
clk : in std_logic := 'X'; -- clk
dummy_ci_port : out std_logic; -- readra
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index 927069ecd1..fb2dc732db 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_jesd204 is
+ component qsys_unb2b_minimal_jesd204 is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index a169c6edeb..b2603c75cf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -16,32 +16,32 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library std;
-use std.textio.all;
+ use std.textio.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
@@ -49,25 +49,25 @@ architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_18
begin
---synthesis translate_off
- process (clk)
+ --synthesis translate_off
+ process (clk)
variable write_line : line;
- begin
- if clk'event and clk = '1' then
- if std_logic'(fifo_wr) = '1' then
- write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
- write(write_line, string'(""));
- write(output, write_line.all);
- deallocate (write_line);
- end if;
+ begin
+ if clk'event and clk = '1' then
+ if std_logic'(fifo_wr) = '1' then
+ write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
+ write(write_line, string'(""));
+ write(output, write_line.all);
+ deallocate (write_line);
end if;
+ end if;
- end process;
+ end process;
- wfifo_used <= A_REP(std_logic'('0'), 6);
- r_dat <= A_REP(std_logic'('0'), 8);
- fifo_FF <= std_logic'('0');
- wfifo_empty <= std_logic'('1');
+ wfifo_used <= A_REP(std_logic'('0'), 6);
+ r_dat <= A_REP(std_logic'('0'), 8);
+ fifo_FF <= std_logic'('0');
+ wfifo_empty <= std_logic'('1');
--synthesis translate_on
end europa;
@@ -79,85 +79,85 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_FF : std_logic;
- signal internal_r_dat : std_logic_vector(7 downto 0);
- signal internal_wfifo_empty : std_logic;
- signal internal_wfifo_used : std_logic_vector(5 downto 0);
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_FF : std_logic;
+ signal internal_r_dat : std_logic_vector(7 downto 0);
+ signal internal_wfifo_empty : std_logic;
+ signal internal_wfifo_used : std_logic_vector(5 downto 0);
begin
@@ -169,18 +169,18 @@ begin
wfifo_empty <= internal_wfifo_empty;
--vhdl renameroo for output signals
wfifo_used <= internal_wfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
- port map(
- fifo_FF => internal_fifo_FF,
- r_dat => internal_r_dat,
- wfifo_empty => internal_wfifo_empty,
- wfifo_used => internal_wfifo_used,
- clk => clk,
- fifo_wdata => fifo_wdata,
- fifo_wr => fifo_wr
- );
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
+ port map(
+ fifo_FF => internal_fifo_FF,
+ r_dat => internal_r_dat,
+ wfifo_empty => internal_wfifo_empty,
+ wfifo_used => internal_wfifo_used,
+ clk => clk,
+ fifo_wdata => fifo_wdata,
+ fifo_wr => fifo_wr
+ );
--synthesis translate_on
@@ -220,72 +220,72 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- signal bytes_left : std_logic_vector(31 downto 0);
- signal fifo_rd_d : std_logic;
- signal internal_rfifo_full1 : std_logic;
- signal new_rom : std_logic;
- signal num_bytes : std_logic_vector(31 downto 0);
- signal rfifo_entries : std_logic_vector(6 downto 0);
+ signal bytes_left : std_logic_vector(31 downto 0);
+ signal fifo_rd_d : std_logic;
+ signal internal_rfifo_full1 : std_logic;
+ signal new_rom : std_logic;
+ signal num_bytes : std_logic_vector(31 downto 0);
+ signal rfifo_entries : std_logic_vector(6 downto 0);
begin
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
---synthesis translate_off
- -- Generate rfifo_entries for simulation
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- bytes_left <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rd_d <= std_logic'('0');
- elsif clk'event and clk = '1' then
- fifo_rd_d <= fifo_rd;
- -- decrement on read
- if std_logic'(fifo_rd_d) = '1' then
- bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
- end if;
- -- catch new contents
- if std_logic'(new_rom) = '1' then
- bytes_left <= num_bytes;
- end if;
+ --synthesis translate_off
+ -- Generate rfifo_entries for simulation
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ bytes_left <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rd_d <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ fifo_rd_d <= fifo_rd;
+ -- decrement on read
+ if std_logic'(fifo_rd_d) = '1' then
+ bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
end if;
+ -- catch new contents
+ if std_logic'(new_rom) = '1' then
+ bytes_left <= num_bytes;
+ end if;
+ end if;
- end process;
+ end process;
- fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
- internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
- rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
- rfifo_used <= rfifo_entries(5 downto 0);
- new_rom <= std_logic'('0');
- num_bytes <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rdata <= std_logic_vector'("00000000");
+ fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
+ internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
+ rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
+ rfifo_used <= rfifo_entries(5 downto 0);
+ new_rom <= std_logic'('0');
+ num_bytes <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rdata <= std_logic_vector'("00000000");
--synthesis translate_on
end europa;
@@ -297,86 +297,86 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_EF : std_logic;
- signal internal_fifo_rdata : std_logic_vector(7 downto 0);
- signal internal_rfifo_full : std_logic;
- signal internal_rfifo_used : std_logic_vector(5 downto 0);
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_EF : std_logic;
+ signal internal_fifo_rdata : std_logic_vector(7 downto 0);
+ signal internal_rfifo_full : std_logic;
+ signal internal_rfifo_used : std_logic_vector(5 downto 0);
begin
@@ -388,18 +388,18 @@ begin
rfifo_full <= internal_rfifo_full;
--vhdl renameroo for output signals
rfifo_used <= internal_rfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
- port map(
- fifo_EF => internal_fifo_EF,
- fifo_rdata => internal_fifo_rdata,
- rfifo_full => internal_rfifo_full,
- rfifo_used => internal_rfifo_used,
- clk => clk,
- fifo_rd => fifo_rd,
- rst_n => rst_n
- );
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
+ port map(
+ fifo_EF => internal_fifo_EF,
+ fifo_rdata => internal_fifo_rdata,
+ rfifo_full => internal_rfifo_full,
+ rfifo_used => internal_rfifo_used,
+ clk => clk,
+ fifo_rd => fifo_rd,
+ rst_n => rst_n
+ );
--synthesis translate_on
@@ -439,136 +439,136 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
- port (
- -- inputs:
- signal av_address : in std_logic;
- signal av_chipselect : in std_logic;
- signal av_read_n : in std_logic;
- signal av_write_n : in std_logic;
- signal av_writedata : in std_logic_vector(31 downto 0);
- signal clk : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal av_irq : out std_logic;
- signal av_readdata : out std_logic_vector(31 downto 0);
- signal av_waitrequest : out std_logic;
- signal dataavailable : out std_logic;
- signal readyfordata : out std_logic
- );
-attribute ALTERA_ATTRIBUTE : string;
-attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
+ port (
+ -- inputs:
+ signal av_address : in std_logic;
+ signal av_chipselect : in std_logic;
+ signal av_read_n : in std_logic;
+ signal av_write_n : in std_logic;
+ signal av_writedata : in std_logic_vector(31 downto 0);
+ signal clk : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal av_irq : out std_logic;
+ signal av_readdata : out std_logic_vector(31 downto 0);
+ signal av_waitrequest : out std_logic;
+ signal dataavailable : out std_logic;
+ signal readyfordata : out std_logic
+ );
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
-
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
-
---synthesis read_comments_as_HDL on
--- component alt_jtag_atlantic is
---GENERIC (
--- INSTANCE_ID : NATURAL;
--- LOG2_RXFIFO_DEPTH : NATURAL;
--- LOG2_TXFIFO_DEPTH : NATURAL;
--- SLD_AUTO_INSTANCE_INDEX : STRING
--- );
--- PORT (
--- signal t_pause : OUT STD_LOGIC;
--- signal r_ena : OUT STD_LOGIC;
--- signal t_ena : OUT STD_LOGIC;
--- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal t_dav : IN STD_LOGIC;
--- signal rst_n : IN STD_LOGIC;
--- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal r_val : IN STD_LOGIC;
--- signal clk : IN STD_LOGIC
--- );
--- end component alt_jtag_atlantic;
---synthesis read_comments_as_HDL off
- signal ac : std_logic;
- signal activity : std_logic;
- signal fifo_AE : std_logic;
- signal fifo_AF : std_logic;
- signal fifo_EF : std_logic;
- signal fifo_FF : std_logic;
- signal fifo_clear : std_logic;
- signal fifo_rd : std_logic;
- signal fifo_rdata : std_logic_vector(7 downto 0);
- signal fifo_wdata : std_logic_vector(7 downto 0);
- signal fifo_wr : std_logic;
- signal ien_AE : std_logic;
- signal ien_AF : std_logic;
- signal internal_av_waitrequest : std_logic;
- signal ipen_AE : std_logic;
- signal ipen_AF : std_logic;
- signal pause_irq : std_logic;
- signal r_dat : std_logic_vector(7 downto 0);
- signal r_ena : std_logic;
- signal r_val : std_logic;
- signal rd_wfifo : std_logic;
- signal read_0 : std_logic;
- signal rfifo_full : std_logic;
- signal rfifo_used : std_logic_vector(5 downto 0);
- signal rvalid : std_logic;
- signal sim_r_ena : std_logic;
- signal sim_t_dat : std_logic;
- signal sim_t_ena : std_logic;
- signal sim_t_pause : std_logic;
- signal t_dat : std_logic_vector(7 downto 0);
- signal t_dav : std_logic;
- signal t_ena : std_logic;
- signal t_pause : std_logic;
- signal wfifo_empty : std_logic;
- signal wfifo_used : std_logic_vector(5 downto 0);
- signal woverflow : std_logic;
- signal wr_rfifo : std_logic;
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
+
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+
+ --synthesis read_comments_as_HDL on
+ -- component alt_jtag_atlantic is
+ --GENERIC (
+ -- INSTANCE_ID : NATURAL;
+ -- LOG2_RXFIFO_DEPTH : NATURAL;
+ -- LOG2_TXFIFO_DEPTH : NATURAL;
+ -- SLD_AUTO_INSTANCE_INDEX : STRING
+ -- );
+ -- PORT (
+ -- signal t_pause : OUT STD_LOGIC;
+ -- signal r_ena : OUT STD_LOGIC;
+ -- signal t_ena : OUT STD_LOGIC;
+ -- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal t_dav : IN STD_LOGIC;
+ -- signal rst_n : IN STD_LOGIC;
+ -- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal r_val : IN STD_LOGIC;
+ -- signal clk : IN STD_LOGIC
+ -- );
+ -- end component alt_jtag_atlantic;
+ --synthesis read_comments_as_HDL off
+ signal ac : std_logic;
+ signal activity : std_logic;
+ signal fifo_AE : std_logic;
+ signal fifo_AF : std_logic;
+ signal fifo_EF : std_logic;
+ signal fifo_FF : std_logic;
+ signal fifo_clear : std_logic;
+ signal fifo_rd : std_logic;
+ signal fifo_rdata : std_logic_vector(7 downto 0);
+ signal fifo_wdata : std_logic_vector(7 downto 0);
+ signal fifo_wr : std_logic;
+ signal ien_AE : std_logic;
+ signal ien_AF : std_logic;
+ signal internal_av_waitrequest : std_logic;
+ signal ipen_AE : std_logic;
+ signal ipen_AF : std_logic;
+ signal pause_irq : std_logic;
+ signal r_dat : std_logic_vector(7 downto 0);
+ signal r_ena : std_logic;
+ signal r_val : std_logic;
+ signal rd_wfifo : std_logic;
+ signal read_0 : std_logic;
+ signal rfifo_full : std_logic;
+ signal rfifo_used : std_logic_vector(5 downto 0);
+ signal rvalid : std_logic;
+ signal sim_r_ena : std_logic;
+ signal sim_t_dat : std_logic;
+ signal sim_t_ena : std_logic;
+ signal sim_t_pause : std_logic;
+ signal t_dat : std_logic_vector(7 downto 0);
+ signal t_dav : std_logic;
+ signal t_ena : std_logic;
+ signal t_pause : std_logic;
+ signal wfifo_empty : std_logic;
+ signal wfifo_used : std_logic_vector(5 downto 0);
+ signal woverflow : std_logic;
+ signal wr_rfifo : std_logic;
begin
@@ -701,28 +701,28 @@ begin
--vhdl renameroo for output signals
av_waitrequest <= internal_av_waitrequest;
---synthesis translate_off
- -- Tie off Atlantic Interface signals not used for simulation
- process (clk)
- begin
- if clk'event and clk = '1' then
- sim_t_pause <= std_logic'('0');
- sim_t_ena <= std_logic'('0');
- sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
- sim_r_ena <= std_logic'('0');
- end if;
+ --synthesis translate_off
+ -- Tie off Atlantic Interface signals not used for simulation
+ process (clk)
+ begin
+ if clk'event and clk = '1' then
+ sim_t_pause <= std_logic'('0');
+ sim_t_ena <= std_logic'('0');
+ sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
+ sim_r_ena <= std_logic'('0');
+ end if;
- end process;
+ end process;
- r_ena <= sim_r_ena;
- t_ena <= sim_t_ena;
- t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
- t_pause <= sim_t_pause;
- process (fifo_EF)
- begin
- dataavailable <= not fifo_EF;
+ r_ena <= sim_r_ena;
+ t_ena <= sim_t_ena;
+ t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
+ t_pause <= sim_t_pause;
+ process (fifo_EF)
+ begin
+ dataavailable <= not fifo_EF;
- end process;
+ end process;
--synthesis translate_on
--synthesis read_comments_as_HDL on
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index e357a3b8ab..4f7553ed71 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_jtag_uart_0 is
+ component qsys_unb2b_minimal_jtag_uart_0 is
port (
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index c400576a19..c4aec21c6b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -16,69 +16,69 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
- generic (
- INIT_FILE : string := "onchip_memory2_0.hex"
- );
- port (
- -- inputs:
- signal address : in std_logic_vector(14 downto 0);
- signal byteenable : in std_logic_vector(3 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal clken : in std_logic;
- signal freeze : in std_logic;
- signal reset : in std_logic;
- signal reset_req : in std_logic;
- signal write : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ generic (
+ INIT_FILE : string := "onchip_memory2_0.hex"
+ );
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(14 downto 0);
+ signal byteenable : in std_logic_vector(3 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal clken : in std_logic;
+ signal freeze : in std_logic;
+ signal reset : in std_logic;
+ signal reset_req : in std_logic;
+ signal write : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal readdata : out std_logic_vector(31 downto 0)
- );
+ -- outputs:
+ signal readdata : out std_logic_vector(31 downto 0)
+ );
end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
architecture europa of qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
component altsyncram is
-generic (
+ generic (
byte_size : natural;
- init_file : string;
- lpm_type : string;
- maximum_depth : natural;
- numwords_a : natural;
- operation_mode : string;
- outdata_reg_a : string;
- ram_block_type : string;
- read_during_write_mode_mixed_ports : string;
- read_during_write_mode_port_a : string;
- width_a : natural;
- width_byteena_a : natural;
- widthad_a : natural
- );
+ init_file : string;
+ lpm_type : string;
+ maximum_depth : natural;
+ numwords_a : natural;
+ operation_mode : string;
+ outdata_reg_a : string;
+ ram_block_type : string;
+ read_during_write_mode_mixed_ports : string;
+ read_during_write_mode_port_a : string;
+ width_a : natural;
+ width_byteena_a : natural;
+ widthad_a : natural
+ );
port (
- signal q_a : out std_logic_vector(31 downto 0);
- signal wren_a : in std_logic;
- signal byteena_a : in std_logic_vector(3 downto 0);
- signal clock0 : in std_logic;
- signal address_a : in std_logic_vector(14 downto 0);
- signal clocken0 : in std_logic;
- signal data_a : in std_logic_vector(31 downto 0)
- );
+ signal q_a : out std_logic_vector(31 downto 0);
+ signal wren_a : in std_logic;
+ signal byteena_a : in std_logic_vector(3 downto 0);
+ signal clock0 : in std_logic;
+ signal address_a : in std_logic_vector(14 downto 0);
+ signal clocken0 : in std_logic;
+ signal data_a : in std_logic_vector(31 downto 0)
+ );
end component altsyncram;
- signal clocken0 : std_logic;
- signal internal_readdata : std_logic_vector(31 downto 0);
- signal wren : std_logic;
+ signal clocken0 : std_logic;
+ signal internal_readdata : std_logic_vector(31 downto 0);
+ signal wren : std_logic;
begin
@@ -101,13 +101,13 @@ begin
widthad_a => 15
)
port map(
- address_a => address,
- byteena_a => byteenable,
- clock0 => clk,
- clocken0 => clocken0,
- data_a => writedata,
- q_a => internal_readdata,
- wren_a => wren
+ address_a => address,
+ byteena_a => byteenable,
+ clock0 => clk,
+ clocken0 => clocken0,
+ data_a => writedata,
+ q_a => internal_readdata,
+ wren_a => wren
);
--s1, which is an e_avalon_slave
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index 1013d9c8fe..d4fadd4056 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_onchip_memory2_0 is
+ component qsys_unb2b_minimal_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 6ac45a007b..ed5d6c9386 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_pio_pps is
+ component qsys_unb2b_minimal_pio_pps is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index 54214733fc..ce7b65f835 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_pio_system_info is
+ component qsys_unb2b_minimal_pio_system_info is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 275c472861..ad408c7815 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -16,37 +16,37 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- port (
- -- inputs:
- signal address : in std_logic_vector(1 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(1 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal out_port : out std_logic;
- signal readdata : out std_logic_vector(31 downto 0)
- );
+ -- outputs:
+ signal out_port : out std_logic;
+ signal readdata : out std_logic_vector(31 downto 0)
+ );
end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
architecture europa of qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- signal clk_en : std_logic;
- signal data_out : std_logic;
- signal read_mux_out : std_logic;
+ signal clk_en : std_logic;
+ signal data_out : std_logic;
+ signal read_mux_out : std_logic;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 7653111094..249fc3461d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_pio_wdi is
+ component qsys_unb2b_minimal_pio_wdi is
port (
clk : in std_logic := 'X'; -- clk
out_port : out std_logic; -- export
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index beaf80437e..ca0753b8f6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_dpmm_ctrl is
+ component qsys_unb2b_minimal_reg_dpmm_ctrl is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index d4d2ea56c7..cb7d6e343c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_dpmm_data is
+ component qsys_unb2b_minimal_reg_dpmm_data is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index 35a921ca9e..2b12931243 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_epcs is
+ component qsys_unb2b_minimal_reg_epcs is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 0dd4b690ec..996a19af95 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_fpga_temp_sens is
+ component qsys_unb2b_minimal_reg_fpga_temp_sens is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 391087f935..72452d8e9f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_fpga_voltage_sens is
+ component qsys_unb2b_minimal_reg_fpga_voltage_sens is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index 57e4a4c70f..cd765a360d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_mmdp_ctrl is
+ component qsys_unb2b_minimal_reg_mmdp_ctrl is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index 6ef3680e58..51873f2715 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_mmdp_data is
+ component qsys_unb2b_minimal_reg_mmdp_data is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 813521ee09..f0ecc1ba1f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_remu is
+ component qsys_unb2b_minimal_reg_remu is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index 911de6ef25..31f317ab8d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_unb_pmbus is
+ component qsys_unb2b_minimal_reg_unb_pmbus is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index bda7f7ffb4..2b7f3cd7f1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_unb_sens is
+ component qsys_unb2b_minimal_reg_unb_sens is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 2037678c58..5d57d1c5e1 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_reg_wdi is
+ component qsys_unb2b_minimal_reg_wdi is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index 24125dfe0e..026a6b8def 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_rom_system_info is
+ component qsys_unb2b_minimal_rom_system_info is
generic (
g_adr_w : natural := 5;
g_dat_w : natural := 32
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index 8b3e6b4cf8..6c59af2597 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -16,52 +16,52 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- port (
- -- inputs:
- signal address : in std_logic_vector(2 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(15 downto 0);
-
- -- outputs:
- signal irq : out std_logic;
- signal readdata : out std_logic_vector(15 downto 0)
- );
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(2 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(15 downto 0);
+
+ -- outputs:
+ signal irq : out std_logic;
+ signal readdata : out std_logic_vector(15 downto 0)
+ );
end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- signal clk_en : std_logic;
- signal control_interrupt_enable : std_logic;
- signal control_register : std_logic;
- signal control_wr_strobe : std_logic;
- signal counter_is_running : std_logic;
- signal counter_is_zero : std_logic;
- signal counter_load_value : std_logic_vector(16 downto 0);
- signal delayed_unxcounter_is_zeroxx0 : std_logic;
- signal do_start_counter : std_logic;
- signal do_stop_counter : std_logic;
- signal force_reload : std_logic;
- signal internal_counter : std_logic_vector(16 downto 0);
- signal period_h_wr_strobe : std_logic;
- signal period_l_wr_strobe : std_logic;
- signal read_mux_out : std_logic_vector(15 downto 0);
- signal status_wr_strobe : std_logic;
- signal timeout_event : std_logic;
- signal timeout_occurred : std_logic;
+ signal clk_en : std_logic;
+ signal control_interrupt_enable : std_logic;
+ signal control_register : std_logic;
+ signal control_wr_strobe : std_logic;
+ signal counter_is_running : std_logic;
+ signal counter_is_zero : std_logic;
+ signal counter_load_value : std_logic_vector(16 downto 0);
+ signal delayed_unxcounter_is_zeroxx0 : std_logic;
+ signal do_start_counter : std_logic;
+ signal do_stop_counter : std_logic;
+ signal force_reload : std_logic;
+ signal internal_counter : std_logic_vector(16 downto 0);
+ signal period_h_wr_strobe : std_logic;
+ signal period_l_wr_strobe : std_logic;
+ signal read_mux_out : std_logic_vector(15 downto 0);
+ signal status_wr_strobe : std_logic;
+ signal timeout_event : std_logic;
+ signal timeout_occurred : std_logic;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index d3f78c4dc8..476cac0f46 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,4 +1,4 @@
- component qsys_unb2b_minimal_timer_0 is
+ component qsys_unb2b_minimal_timer_0 is
port (
clk : in std_logic := 'X'; -- clk
irq : out std_logic; -- irq
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
index 0099aadc7d..cbe380f9e9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, unb2b_jesd_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd_node3 is
generic (
@@ -45,7 +45,7 @@ entity unb2b_jesd_node3 is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -85,51 +85,51 @@ architecture str of unb2b_jesd_node3 is
begin
u_revision : entity unb2b_jesd_lib.unb2b_jesd
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- QSFP_LED => QSFP_LED,
-
- -- JESD signals
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_sysref => jesd204_rx_sysref,
- jesd204_device_clk => jesd204_device_clk
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED,
+
+ -- JESD signals
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_sysref => jesd204_rx_sysref,
+ jesd204_device_clk => jesd204_device_clk
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
index 0cfce242e5..6c6206fdfa 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_jesd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_jesd_pkg.all;
entity mmm_unb2b_jesd is
@@ -139,32 +139,32 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -182,214 +182,214 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2b_jesd
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-
- ram_diag_data_buf_jesd_clk_export => OPEN,
- ram_diag_data_buf_jesd_reset_export => OPEN,
- ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(17 - 1 downto 0),
- ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
- ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
- ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buf_jesd_reset_export => OPEN,
- reg_diag_data_buf_jesd_clk_export => OPEN,
- reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(6 - 1 downto 0),
- reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
- reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
- reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
-
- -- connections to the JESD IP:
-
- --altjesd_reset_seq_irq_irq =>
- altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual => i_reset_n,
- --altjesd_reset_seq_pll_reset_reset =>
- altjesd_reset_seq_reset_in0_reset => mm_rst,
- altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual => '1',
- altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual => rx_xcvr_ready_in,
- --altjesd_rx_csr_cf_export =>
- --altjesd_rx_csr_cs_export =>
- --altjesd_rx_csr_f_export =>
- --altjesd_rx_csr_hd_export =>
- --altjesd_rx_csr_k_export =>
- --altjesd_rx_csr_l_export =>
- altjesd_rx_csr_lane_powerdown_export => rx_csr_lane_powerdown,
- --altjesd_rx_csr_m_export =>
- --altjesd_rx_csr_n_export =>
- --altjesd_rx_csr_np_export =>
- --altjesd_rx_csr_rx_testmode_export =>
- --altjesd_rx_csr_s_export =>
- altjesd_rx_dev_sync_n_export => jesd204_sync_n_out,
- altjesd_rx_jesd204_rx_dlb_data_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_data_valid_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_disperr_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_errdetect_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_kchar_data_export => (others => '0'),
- altjesd_rx_jesd204_rx_frame_error_export => '0',
- altjesd_rx_jesd204_rx_int_irq => jesd204_rx_link_error,
- altjesd_rx_jesd204_rx_link_data => jesd204_rx_link_data,
- altjesd_rx_jesd204_rx_link_valid => jesd204_rx_link_valid,
- altjesd_rx_jesd204_rx_link_ready => jesd204_rx_link_ready,
- altjesd_rx_rx_serial_data_rx_serial_data(0) => jesd204_rx_serial_data,
- altjesd_rx_rxlink_rst_n_reset_n => rx_link_rst_n,
- altjesd_ss_rx_link_reset_out_reset_reset_n => rx_link_rst_n,
- --altjesd_ss_rx_frame_reset_out_reset_reset_n =>
- --altjesd_rx_rxphy_clk_export =>
- --altjesd_rx_sof_export =>
- --altjesd_rx_somf_export =>
- altjesd_rx_sysref_export => jesd204_rx_sysref,
- --altjesd_ss_rx_corepll_locked_export =>
- --altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown =>
- altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready => xcvr_rst_ctrl_rx_ready,
- device_clk_clk => jesd204_device_clk,
- device_clk_reset_reset_n => '1',
- frame_clk_clk => frame_clk,
- pll_out_frame_clk_clk => frame_clk,
- frame_clk_reset_reset_n => '1',
- link_clk_clk => link_clk,
- pll_out_link_clk_clk => link_clk,
- link_clk_reset_reset_n => '1'
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+
+ ram_diag_data_buf_jesd_clk_export => OPEN,
+ ram_diag_data_buf_jesd_reset_export => OPEN,
+ ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(17 - 1 downto 0),
+ ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
+ ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
+ ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buf_jesd_reset_export => OPEN,
+ reg_diag_data_buf_jesd_clk_export => OPEN,
+ reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(6 - 1 downto 0),
+ reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
+ reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
+ reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
+
+
+ -- connections to the JESD IP:
+
+ --altjesd_reset_seq_irq_irq =>
+ altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual => i_reset_n,
+ --altjesd_reset_seq_pll_reset_reset =>
+ altjesd_reset_seq_reset_in0_reset => mm_rst,
+ altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual => '1',
+ altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual => rx_xcvr_ready_in,
+ --altjesd_rx_csr_cf_export =>
+ --altjesd_rx_csr_cs_export =>
+ --altjesd_rx_csr_f_export =>
+ --altjesd_rx_csr_hd_export =>
+ --altjesd_rx_csr_k_export =>
+ --altjesd_rx_csr_l_export =>
+ altjesd_rx_csr_lane_powerdown_export => rx_csr_lane_powerdown,
+ --altjesd_rx_csr_m_export =>
+ --altjesd_rx_csr_n_export =>
+ --altjesd_rx_csr_np_export =>
+ --altjesd_rx_csr_rx_testmode_export =>
+ --altjesd_rx_csr_s_export =>
+ altjesd_rx_dev_sync_n_export => jesd204_sync_n_out,
+ altjesd_rx_jesd204_rx_dlb_data_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_data_valid_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_disperr_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_errdetect_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_kchar_data_export => (others => '0'),
+ altjesd_rx_jesd204_rx_frame_error_export => '0',
+ altjesd_rx_jesd204_rx_int_irq => jesd204_rx_link_error,
+ altjesd_rx_jesd204_rx_link_data => jesd204_rx_link_data,
+ altjesd_rx_jesd204_rx_link_valid => jesd204_rx_link_valid,
+ altjesd_rx_jesd204_rx_link_ready => jesd204_rx_link_ready,
+ altjesd_rx_rx_serial_data_rx_serial_data(0) => jesd204_rx_serial_data,
+ altjesd_rx_rxlink_rst_n_reset_n => rx_link_rst_n,
+ altjesd_ss_rx_link_reset_out_reset_reset_n => rx_link_rst_n,
+ --altjesd_ss_rx_frame_reset_out_reset_reset_n =>
+ --altjesd_rx_rxphy_clk_export =>
+ --altjesd_rx_sof_export =>
+ --altjesd_rx_somf_export =>
+ altjesd_rx_sysref_export => jesd204_rx_sysref,
+ --altjesd_ss_rx_corepll_locked_export =>
+ --altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown =>
+ altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready => xcvr_rst_ctrl_rx_ready,
+ device_clk_clk => jesd204_device_clk,
+ device_clk_reset_reset_n => '1',
+ frame_clk_clk => frame_clk,
+ pll_out_frame_clk_clk => frame_clk,
+ frame_clk_reset_reset_n => '1',
+ link_clk_clk => link_clk,
+ pll_out_link_clk_clk => link_clk,
+ link_clk_reset_reset_n => '1'
);
end generate;
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
index 7adf946bf8..4a36b8f5f0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
@@ -20,199 +20,199 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_jesd_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
-component qsys_unb2b_jesd is
- port (
- altjesd_reset_seq_irq_irq : out std_logic; -- irq
- altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- altjesd_reset_seq_pll_reset_reset : out std_logic; -- reset
- altjesd_reset_seq_reset_in0_reset : in std_logic := 'X'; -- reset
- altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- altjesd_rx_csr_cf_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_cs_export : out std_logic_vector(1 downto 0); -- export
- altjesd_rx_csr_f_export : out std_logic_vector(7 downto 0); -- export
- altjesd_rx_csr_hd_export : out std_logic; -- export
- altjesd_rx_csr_k_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_l_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
- altjesd_rx_csr_m_export : out std_logic_vector(7 downto 0); -- export
- altjesd_rx_csr_n_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_np_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_csr_s_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_dev_sync_n_export : out std_logic; -- export
- altjesd_rx_jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
- altjesd_rx_jesd204_rx_int_irq : out std_logic; -- irq
- altjesd_rx_jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- altjesd_rx_jesd204_rx_link_valid : out std_logic; -- valid
- altjesd_rx_jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- altjesd_rx_rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- altjesd_rx_rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- altjesd_rx_rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
- altjesd_rx_sof_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_somf_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_sysref_export : in std_logic := 'X'; -- export
- altjesd_ss_rx_corepll_locked_export : out std_logic; -- export
- altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready : out std_logic_vector(0 downto 0); -- rx_ready
- altjesd_ss_rx_frame_reset_out_reset_reset_n : out std_logic; -- reset_n
- altjesd_ss_rx_link_reset_out_reset_reset_n : out std_logic; -- reset_n
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- device_clk_clk : in std_logic := 'X'; -- clk
- device_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- frame_clk_clk : in std_logic := 'X'; -- clk
- frame_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- link_clk_clk : in std_logic := 'X'; -- clk
- link_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- pll_out_frame_clk_clk : out std_logic; -- clk
- pll_out_link_clk_clk : out std_logic; -- clk
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_jesd;
+ component qsys_unb2b_jesd is
+ port (
+ altjesd_reset_seq_irq_irq : out std_logic; -- irq
+ altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ altjesd_reset_seq_pll_reset_reset : out std_logic; -- reset
+ altjesd_reset_seq_reset_in0_reset : in std_logic := 'X'; -- reset
+ altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ altjesd_rx_csr_cf_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_cs_export : out std_logic_vector(1 downto 0); -- export
+ altjesd_rx_csr_f_export : out std_logic_vector(7 downto 0); -- export
+ altjesd_rx_csr_hd_export : out std_logic; -- export
+ altjesd_rx_csr_k_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_l_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
+ altjesd_rx_csr_m_export : out std_logic_vector(7 downto 0); -- export
+ altjesd_rx_csr_n_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_np_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_csr_s_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_dev_sync_n_export : out std_logic; -- export
+ altjesd_rx_jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
+ altjesd_rx_jesd204_rx_int_irq : out std_logic; -- irq
+ altjesd_rx_jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ altjesd_rx_jesd204_rx_link_valid : out std_logic; -- valid
+ altjesd_rx_jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ altjesd_rx_rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ altjesd_rx_rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ altjesd_rx_rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
+ altjesd_rx_sof_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_somf_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_sysref_export : in std_logic := 'X'; -- export
+ altjesd_ss_rx_corepll_locked_export : out std_logic; -- export
+ altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready : out std_logic_vector(0 downto 0); -- rx_ready
+ altjesd_ss_rx_frame_reset_out_reset_reset_n : out std_logic; -- reset_n
+ altjesd_ss_rx_link_reset_out_reset_reset_n : out std_logic; -- reset_n
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ device_clk_clk : in std_logic := 'X'; -- clk
+ device_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ frame_clk_clk : in std_logic := 'X'; -- clk
+ frame_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ link_clk_clk : in std_logic := 'X'; -- clk
+ link_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ pll_out_frame_clk_clk : out std_logic; -- clk
+ pll_out_link_clk_clk : out std_logic; -- clk
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_unb2b_jesd;
end qsys_unb2b_jesd_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index ace483155e..80aaf6be45 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd is
generic (
@@ -46,7 +46,7 @@ entity unb2b_jesd is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -188,212 +188,212 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_jesd
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- --
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
-
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_link_error => jesd204_rx_link_error,
- jesd204_rx_link_data => jesd204_rx_link_data,
- jesd204_rx_link_valid => jesd204_rx_link_valid,
- jesd204_rx_link_ready => jesd204_rx_link_ready,
- jesd204_rx_sysref => jesd204_rx_sysref_n,
- jesd204_device_clk => st_clk
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ --
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_link_error => jesd204_rx_link_error,
+ jesd204_rx_link_data => jesd204_rx_link_data,
+ jesd204_rx_link_valid => jesd204_rx_link_valid,
+ jesd204_rx_link_ready => jesd204_rx_link_ready,
+ jesd204_rx_sysref => jesd204_rx_sysref_n,
+ jesd204_device_clk => st_clk
+ );
CLK <= jesd204_device_clk;
--PPS <= jesd204_rx_sysref;
@@ -409,28 +409,28 @@ begin
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => 1,
- g_data_w => 32,
- g_buf_nof_data => 16384, -- 8192,
- g_buf_use_sync => true, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- g_use_rx_seq => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => mm_rst,
- dp_clk => st_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
- ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
- reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
- reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
-
- in_sosi_arr => diag_data_buf_snk_in_arr,
- in_sync => st_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => 1,
+ g_data_w => 32,
+ g_buf_nof_data => 16384, -- 8192,
+ g_buf_use_sync => true, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_use_rx_seq => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => mm_rst,
+ dp_clk => st_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
+
+ in_sosi_arr => diag_data_buf_snk_in_arr,
+ in_sync => st_pps
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
index 2c0f4a07c3..cde1c0382b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2b_pkg.all;
-use i2c_lib.i2c_commander_unb2b_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2b_pkg.all;
+ use i2c_lib.i2c_commander_unb2b_pmbus_pkg.all;
entity tb_unb2b_minimal is
- generic (
- g_design_name : string := "unb2b_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
@@ -188,51 +188,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
index 17b40afcd4..887d42c711 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_minimal_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_minimal_125m is
@@ -77,46 +77,46 @@ architecture str of unb2b_minimal_125m is
begin
u_revision : entity unb2b_minimal_lib.unb2b_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index b686089538..c3e5adc630 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_minimal_pkg.all;
entity mmm_unb2b_minimal is
@@ -120,35 +120,35 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -165,153 +165,153 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2b_minimal
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_scrap_reset_export => OPEN,
- ram_scrap_clk_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
index 78235c8ddc..08853559d1 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
@@ -20,144 +20,144 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb2b_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2b_minimal;
+ component qsys_unb2b_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2b_minimal;
end qsys_unb2b_minimal_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
index 3d548a9e6f..c790f64a7b 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
entity unb2b_minimal is
generic (
@@ -167,228 +167,228 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
index 99a1387392..e4f6c2b9a8 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2b_minimal is
- generic (
- g_design_name : string := "unb2b_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
@@ -188,51 +188,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
index 9311380c77..24289d7397 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2b_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2b_test_10GbE is
@@ -31,8 +31,8 @@ end tb_unb2b_test_10GbE;
architecture tb of tb_unb2b_test_10GbE is
begin
u_tb_unb2b_test : entity unb2b_test_lib.tb_unb2b_test
- generic map (
- g_design_name => "unb2b_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2b_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
index 97f02d9fb2..223f267cbd 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_test_10GbE is
@@ -67,20 +67,20 @@ entity unb2b_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -112,78 +112,78 @@ architecture str of unb2b_test_10GbE is
begin
u_revision : entity unb2b_test_lib.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
index 73fbba0807..c13f455d77 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
@@ -23,7 +23,7 @@
library IEEE, unb2b_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2b_test_ddr_MB_I_II is
@@ -33,9 +33,9 @@ end tb_unb2b_test_ddr_MB_I_II;
architecture tb of tb_unb2b_test_ddr_MB_I_II is
begin
u_tb_unb2b_test : entity unb2b_test_lib.tb_unb2b_test
- generic map (
- g_design_name => "unb2b_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2b_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
index 049740b6f0..0862334f19 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2b_test_ddr_MB_I_II is
@@ -89,56 +89,56 @@ architecture str of unb2b_test_ddr_MB_I_II is
begin
u_revision : entity unb2b_test_lib.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 7af096606c..dab17540c8 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2b_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2b_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2b_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2b_test_pkg.all;
@@ -239,16 +239,16 @@ architecture str of mmm_unb2b_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2b_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2b_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -293,112 +293,112 @@ begin
eth1g_eth1_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -423,10 +423,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
@@ -445,405 +445,405 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2b_test
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_eth0_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
-
- avs_eth_1_reset_export => eth1g_eth1_mm_rst,
- avs_eth_1_clk_export => OPEN,
- avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
- avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
- avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
- avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
- avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
- avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
- avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
- avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_irq_export => eth1g_eth1_reg_interrupt,
-
- reg_unb_sens_reset_export => OPEN,
- reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_reset_export => OPEN,
- reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
- reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
- reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
- reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
- reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
-
- reg_tr_10gbe_back0_reset_export => OPEN,
- reg_tr_10gbe_back0_clk_export => OPEN,
- reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
- reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
- reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
-
- reg_tr_10gbe_back1_reset_export => OPEN,
- reg_tr_10gbe_back1_clk_export => OPEN,
- reg_tr_10gbe_back1_address_export => reg_tr_10GbE_back1_mosi.address(c_reg_tr_10GbE_back1_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_back1_write_export => reg_tr_10GbE_back1_mosi.wr,
- reg_tr_10gbe_back1_writedata_export => reg_tr_10GbE_back1_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back1_read_export => reg_tr_10GbE_back1_mosi.rd,
- reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
-
- reg_eth10g_qsfp_ring_reset_export => OPEN,
- reg_eth10g_qsfp_ring_clk_export => OPEN,
- reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w - 1 downto 0),
- reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
- reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
- reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
-
- reg_eth10g_back0_reset_export => OPEN,
- reg_eth10g_back0_clk_export => OPEN,
- reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w - 1 downto 0),
- reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
- reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
- reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w - 1 downto 0),
-
- reg_eth10g_back1_reset_export => OPEN,
- reg_eth10g_back1_clk_export => OPEN,
- reg_eth10g_back1_address_export => reg_eth10g_back1_mosi.address(c_reg_eth10g_back1_multi_adr_w - 1 downto 0),
- reg_eth10g_back1_write_export => reg_eth10g_back1_mosi.wr,
- reg_eth10g_back1_writedata_export => reg_eth10g_back1_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
- reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
-
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
- reg_bsn_monitor_1gbe_reset_export => OPEN,
- reg_bsn_monitor_1gbe_clk_export => OPEN,
- reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_1gbe_write_export => reg_bsn_monitor_1GbE_mosi.wr,
- reg_bsn_monitor_1gbe_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_1gbe_read_export => reg_bsn_monitor_1GbE_mosi.rd,
- reg_bsn_monitor_1gbe_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_10gbe_reset_export => OPEN,
- reg_bsn_monitor_10gbe_clk_export => OPEN,
- reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
- reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
- reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_1gbe_reset_export => OPEN,
- reg_diag_data_buffer_1gbe_clk_export => OPEN,
- reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_1gbe_write_export => reg_diag_data_buf_1gbe_mosi.wr,
- reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
- reg_diag_data_buffer_1gbe_readdata_export => reg_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_10gbe_reset_export => OPEN,
- reg_diag_data_buffer_10gbe_clk_export => OPEN,
- reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(5 downto 0),
- reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
- reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
- reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_1gbe_clk_export => OPEN,
- ram_diag_data_buffer_1gbe_reset_export => OPEN,
- ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w - 1 downto 0),
- ram_diag_data_buffer_1gbe_write_export => ram_diag_data_buf_1gbe_mosi.wr,
- ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
- ram_diag_data_buffer_1gbe_readdata_export => ram_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_10gbe_clk_export => OPEN,
- ram_diag_data_buffer_10gbe_reset_export => OPEN,
- ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w - 1 downto 0),
- ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
- ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
- ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_1GbE_reset_export => OPEN,
- reg_diag_bg_1GbE_clk_export => OPEN,
- reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
- reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
- reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_10GbE_reset_export => OPEN,
- reg_diag_bg_10GbE_clk_export => OPEN,
- reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
- reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
- reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_bg_1GbE_reset_export => OPEN,
- ram_diag_bg_1GbE_clk_export => OPEN,
- ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w - 1 downto 0),
- ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
- ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
- ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_bg_10GbE_reset_export => OPEN,
- ram_diag_bg_10GbE_clk_export => OPEN,
- ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
- ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
- ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
- ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_I_clk_export => OPEN,
- reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
- reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_I_reset_export => OPEN,
- reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
- reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_II_clk_export => OPEN,
- reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
- reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_II_reset_export => OPEN,
- reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
- reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
- reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
- reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
- reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
- reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
- reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
- reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
- reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
- reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
- ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
- ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
- ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
- ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_eth0_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
+
+ avs_eth_1_reset_export => eth1g_eth1_mm_rst,
+ avs_eth_1_clk_export => OPEN,
+ avs_eth_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
+ avs_eth_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
+ avs_eth_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
+ avs_eth_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
+ avs_eth_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
+ avs_eth_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
+ avs_eth_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
+ avs_eth_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_irq_export => eth1g_eth1_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_reset_export => OPEN,
+ reg_unb_pmbus_clk_export => OPEN,
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
+ reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
+ reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
+
+ reg_tr_10gbe_back0_reset_export => OPEN,
+ reg_tr_10gbe_back0_clk_export => OPEN,
+ reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
+ reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
+ reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
+
+ reg_tr_10gbe_back1_reset_export => OPEN,
+ reg_tr_10gbe_back1_clk_export => OPEN,
+ reg_tr_10gbe_back1_address_export => reg_tr_10GbE_back1_mosi.address(c_reg_tr_10GbE_back1_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_back1_write_export => reg_tr_10GbE_back1_mosi.wr,
+ reg_tr_10gbe_back1_writedata_export => reg_tr_10GbE_back1_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back1_read_export => reg_tr_10GbE_back1_mosi.rd,
+ reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
+
+ reg_eth10g_qsfp_ring_reset_export => OPEN,
+ reg_eth10g_qsfp_ring_clk_export => OPEN,
+ reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w - 1 downto 0),
+ reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
+ reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
+ reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_eth10g_back0_reset_export => OPEN,
+ reg_eth10g_back0_clk_export => OPEN,
+ reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w - 1 downto 0),
+ reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
+ reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
+ reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_eth10g_back1_reset_export => OPEN,
+ reg_eth10g_back1_clk_export => OPEN,
+ reg_eth10g_back1_address_export => reg_eth10g_back1_mosi.address(c_reg_eth10g_back1_multi_adr_w - 1 downto 0),
+ reg_eth10g_back1_write_export => reg_eth10g_back1_mosi.wr,
+ reg_eth10g_back1_writedata_export => reg_eth10g_back1_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
+ reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
+
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ reg_bsn_monitor_1gbe_reset_export => OPEN,
+ reg_bsn_monitor_1gbe_clk_export => OPEN,
+ reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_1gbe_write_export => reg_bsn_monitor_1GbE_mosi.wr,
+ reg_bsn_monitor_1gbe_writedata_export => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_1gbe_read_export => reg_bsn_monitor_1GbE_mosi.rd,
+ reg_bsn_monitor_1gbe_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_10gbe_reset_export => OPEN,
+ reg_bsn_monitor_10gbe_clk_export => OPEN,
+ reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
+ reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
+ reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_1gbe_reset_export => OPEN,
+ reg_diag_data_buffer_1gbe_clk_export => OPEN,
+ reg_diag_data_buffer_1gbe_address_export => reg_diag_data_buf_1gbe_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_1gbe_write_export => reg_diag_data_buf_1gbe_mosi.wr,
+ reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
+ reg_diag_data_buffer_1gbe_readdata_export => reg_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_10gbe_reset_export => OPEN,
+ reg_diag_data_buffer_10gbe_clk_export => OPEN,
+ reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(5 downto 0),
+ reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
+ reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
+ reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_1gbe_clk_export => OPEN,
+ ram_diag_data_buffer_1gbe_reset_export => OPEN,
+ ram_diag_data_buffer_1gbe_address_export => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w - 1 downto 0),
+ ram_diag_data_buffer_1gbe_write_export => ram_diag_data_buf_1gbe_mosi.wr,
+ ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
+ ram_diag_data_buffer_1gbe_readdata_export => ram_diag_data_buf_1gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_10gbe_clk_export => OPEN,
+ ram_diag_data_buffer_10gbe_reset_export => OPEN,
+ ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w - 1 downto 0),
+ ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
+ ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
+ ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_1GbE_reset_export => OPEN,
+ reg_diag_bg_1GbE_clk_export => OPEN,
+ reg_diag_bg_1GbE_address_export => reg_diag_bg_1GbE_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_1GbE_write_export => reg_diag_bg_1GbE_mosi.wr,
+ reg_diag_bg_1GbE_writedata_export => reg_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
+ reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_10GbE_reset_export => OPEN,
+ reg_diag_bg_10GbE_clk_export => OPEN,
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
+ reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
+ reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_1GbE_reset_export => OPEN,
+ ram_diag_bg_1GbE_clk_export => OPEN,
+ ram_diag_bg_1GbE_address_export => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w - 1 downto 0),
+ ram_diag_bg_1GbE_write_export => ram_diag_bg_1GbE_mosi.wr,
+ ram_diag_bg_1GbE_writedata_export => ram_diag_bg_1GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
+ ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_10GbE_reset_export => OPEN,
+ ram_diag_bg_10GbE_clk_export => OPEN,
+ ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
+ ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
+ ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
+ ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_I_clk_export => OPEN,
+ reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
+ reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_I_reset_export => OPEN,
+ reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
+ reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_II_clk_export => OPEN,
+ reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
+ reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_II_reset_export => OPEN,
+ reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
+ reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index eaffab4dbf..03df95ac35 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_test_pkg is
@@ -29,362 +29,362 @@ package qsys_unb2b_test_pkg is
-- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2b_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
- reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
- reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
- reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
- reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
- reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
- reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
- reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
- reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
- reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
- reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
- reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
- reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
- reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
- reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
- reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
- reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
- reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
- reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
- );
- end component qsys_unb2b_test;
+ component qsys_unb2b_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
+ avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
+ avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
+ avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
+ avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
+ avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
+ avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
+ avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
+ avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
+ avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
+ avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
+ avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
+ avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
+ avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
+ avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
+ avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
+ avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
+ avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
+ clk_clk : in std_logic := '0'; -- clk.clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
+ pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
+ pio_pps_read_export : out std_logic; -- pio_pps_read.export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
+ pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
+ pio_pps_write_export : out std_logic; -- pio_pps_write.export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
+ pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
+ pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
+ pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
+ pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
+ pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
+ reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
+ reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
+ reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
+ reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
+ reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
+ reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
+ reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
+ reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
+ reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
+ reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
+ reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
+ reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
+ reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
+ reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
+ reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
+ reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
+ reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
+ reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
+ reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
+ reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
+ reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
+ reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
+ reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
+ reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
+ reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
+ reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
+ reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
+ reg_remu_read_export : out std_logic; -- reg_remu_read.export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
+ reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
+ reg_remu_write_export : out std_logic; -- reg_remu_write.export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
+ reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
+ reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
+ reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
+ reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
+ reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
+ reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
+ reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
+ reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
+ reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
+ reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
+ reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
+ reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
+ reset_reset_n : in std_logic := '0'; -- reset.reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
+ rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
+ rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
+ rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
+ rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
+ );
+ end component qsys_unb2b_test;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
index efb781f7ca..96ac0845d1 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2b_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2b_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2b_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -105,14 +105,28 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC(
+ g_bg_block_size,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ g_bg_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ g_bg_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ g_bg_block_size-1,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
constant c_nof_crc_words : natural := 1;
@@ -157,54 +171,54 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
@@ -212,74 +226,74 @@ begin
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
@@ -304,55 +318,55 @@ begin
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index f9dcc6a928..3d8a1990e6 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2b_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2b_test_pkg.all;
entity unb2b_test is
generic (
@@ -320,10 +320,10 @@ architecture str of unb2b_test is
signal i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -356,13 +356,13 @@ architecture str of unb2b_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -441,381 +441,381 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2b_board_nof_eth,
- g_nof_streams_qsfp => c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2b_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2b_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2b_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2b_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2b_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
@@ -835,90 +835,90 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2b_board_10gbe_lib.unb2b_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -940,163 +940,163 @@ begin
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
-
--- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2b_board_lib.unb2b_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+
+ -- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2b_board_lib.unb2b_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
@@ -1109,156 +1109,156 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
index f78eda85f9..341ebd3375 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2b_test_pkg is
@@ -31,27 +31,27 @@ package unb2b_test_pkg is
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
index 8a8e92d8e2..477b2d2300 100644
--- a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2b_test is
generic (
@@ -187,143 +187,143 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2b_test : entity work.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- -- QSFP_0_TX => si_lpbk_0,
- -- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index ca05062873..14da95c46f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2b_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2b_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2b_board is
generic (
@@ -340,15 +340,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -357,15 +357,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
@@ -374,26 +374,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -407,29 +407,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2b_board_clk200_pll : entity work.unb2b_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -443,48 +443,48 @@ begin
clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2b_board_clk125_pll : entity work.unb2b_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2b_board_node_ctrl : entity work.unb2b_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2b_board_node_ctrl : entity work.unb2b_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -492,33 +492,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2b_board_system_info : entity work.mms_unb2b_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
@@ -556,12 +556,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
@@ -573,15 +573,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2b_board_wdi_reg : entity work.unb2b_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
@@ -591,75 +591,75 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
@@ -669,74 +669,74 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s; -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
u_mms_unb2b_board_sens : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2b_board_pmbus : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_pmbus,
- g_sens_nof_result => 42,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_pmbus,
+ g_sens_nof_result => 42,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2b_fpga_sens : entity work.mms_unb2b_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
@@ -746,18 +746,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
@@ -784,61 +784,61 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
+ end generate;
+
+ u_ram_scrap : entity common_lib.common_ram_r_w
generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true,
- g_sim => g_sim,
- g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ g_ram => c_ram_scrap
)
port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ wr_en => ram_scrap_mosi.wr,
+ wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_en => ram_scrap_mosi.rd,
+ rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_val => ram_scrap_miso.rdval
);
- end generate;
-
- u_ram_scrap : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_scrap
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- wr_en => ram_scrap_mosi.wr,
- wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
- rd_en => ram_scrap_mosi.rd,
- rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
- rd_val => ram_scrap_miso.rdval
- );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
index ca49243913..d1ec7e88c9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2b_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2b_board_sens is
@@ -70,48 +70,48 @@ architecture str of mms_unb2b_board_sens is
begin
u_unb2b_board_sens_reg : entity work.unb2b_board_sens_reg
- generic map (
- g_sens_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
-
- -- Max temp threshold
- temp_high => temp_high
- );
+ generic map (
+ g_sens_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
+
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2b_board_sens : entity work.unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => g_i2c_peripheral,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => g_sens_nof_result,
- g_comma_w => g_comma_w
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => g_i2c_peripheral,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => g_sens_nof_result,
+ g_comma_w => g_comma_w
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 4bf6770a4b..638ed92120 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2b_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2b_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2b_board_system_info;
@@ -70,72 +70,74 @@ architecture str of mms_unb2b_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0'
+ );
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2b_board_system_info: entity work.unb2b_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2b_board_system_info_reg: entity work.unb2b_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index 6087787053..54f17deaf2 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2b_fpga_sens.vhd
library IEEE, technology_lib, common_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2b_fpga_sens is
@@ -59,24 +59,24 @@ architecture str of mms_unb2b_fpga_sens is
begin
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim,
- g_temp_high => g_temp_high
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => mm_start,
- temp_alarm => temp_alarm,
+ start_sense => mm_start,
+ temp_alarm => temp_alarm,
- reg_temp_mosi => reg_temp_mosi,
- reg_temp_miso => reg_temp_miso,
+ reg_temp_mosi => reg_temp_mosi,
+ reg_temp_miso => reg_temp_miso,
- reg_voltage_store_mosi => reg_voltage_mosi,
- reg_voltage_store_miso => reg_voltage_miso
- );
+ reg_voltage_store_mosi => reg_voltage_mosi,
+ reg_voltage_store_miso => reg_voltage_miso
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
index b4e3a66d5b..e8f4217186 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_back_io is
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
index 4d5d867723..afc7f4059a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
-- Description:
@@ -64,47 +64,47 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
index f2e6b39a75..cdf67c5f64 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -140,83 +140,83 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
index cd0e38e1e6..d0d3cd7a00 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -54,16 +54,16 @@ architecture arria10 of unb2b_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
index 32eb4b1ad5..6a93741853 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -59,28 +59,28 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
index ad046d5128..db435b17b6 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_front_io is
@@ -69,8 +69,8 @@ begin
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2b_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
index c0081cd7df..ef5bbe5e5a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_hmc_ctrl is
@@ -59,37 +59,89 @@ architecture rtl of unb2b_board_hmc_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
index bf6f0a7669..038c322333 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
-- Description:
@@ -71,44 +71,44 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2b_board_wdi_extend : entity work.unb2b_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
index 315c4812d9..179d146e14 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2b_board_peripherals_pkg is
@@ -76,10 +76,10 @@ package unb2b_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
index 3d07f2e6e0..1c9c8b609b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2b_board_pkg is
@@ -149,23 +149,25 @@ package unb2b_board_pkg is
type t_c_unb2b_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2b_board_system_info(VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info;
+ function func_unb2b_board_system_info (
+ VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info;
end unb2b_board_pkg;
package body unb2b_board_pkg is
- function func_unb2b_board_system_info(VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info is
+ function func_unb2b_board_system_info (
+ VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info is
variable v_system_info : t_c_unb2b_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
index f88c8c517d..e5c88b475a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_pmbus_ctrl is
@@ -59,37 +59,89 @@ architecture rtl of unb2b_board_pmbus_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR0_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_TCVR1_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CORE_BMR464_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_CTRL_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_FPGAIO_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_PMB_VCCRAM_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
index 56768d4086..b20509eae1 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
-- Description:
@@ -111,43 +111,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -166,20 +166,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
index 6c2bc52569..5fb028a5ce 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_ring_io is
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
index 8af6487703..da8d970985 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_sens is
generic (
@@ -54,18 +54,18 @@ architecture str of unb2b_board_sens is
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
--- octave:4> t=1/50e6
--- t = 2.0000e-08
--- octave:5> delay=2^13 * t
--- delay = 1.6384e-04
--- octave:6> delay/t
--- ans = 8192
--- octave:7> log2(ans)
--- ans = 13
--- octave:8> log2(delay/t)
--- ans = 13
+ -- octave:4> t=1/50e6
+ -- t = 2.0000e-08
+ -- octave:5> delay=2^13 * t
+ -- delay = 1.6384e-04
+ -- octave:6> delay/t
+ -- ans = 8192
+ -- octave:7> log2(ans)
+ -- ans = 13
+ -- octave:8> log2(delay/t)
+ -- ans = 13
--CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
@@ -83,94 +83,94 @@ begin
gen_unb2b_board_sens_ctrl : if g_i2c_peripheral = c_i2c_peripheral_sens generate
u_unb2b_board_sens_ctrl : entity work.unb2b_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2b_board_pmbus_ctrl : if g_i2c_peripheral = c_i2c_peripheral_pmbus generate
u_unb2b_board_pmbus_ctrl : entity work.unb2b_board_pmbus_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2b_board_hmc_ctrl : if g_i2c_peripheral = c_i2c_peripheral_hmc generate
u_unb2b_board_hmc_ctrl : entity work.unb2b_board_hmc_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy,
+ g_clock_stretch_sense_scl => true
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy,
- g_clock_stretch_sense_scl => true
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
end architecture;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
index cdc5cd4fdd..9631da8eb9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_sens_ctrl is
@@ -73,39 +73,93 @@ architecture rtl of unb2b_board_sens_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_SENS_EEPROM_CAT24C02_ADR, CAT24C02_ADR_00,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_HI,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_LO,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_HI,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_LO,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_EEPROM_CAT24C02_ADR,
+ CAT24C02_ADR_00,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_TEMP_TMP451_ADR,
+ TMP451_LOC_HI,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_TEMP_TMP451_ADR,
+ TMP451_LOC_LO,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_TEMP_TMP451_ADR,
+ TMP451_REM_HI,
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_TEMP_TMP451_ADR,
+ TMP451_REM_LO,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_QSFP0_BMR464_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP0_BMR464_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP0_BMR464_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP0_BMR464_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_QSFP1_BMR464_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP1_BMR464_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP1_BMR464_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_QSFP1_BMR464_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_CLK_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_CLK_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_CLK_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_CLK_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_3V3_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_3V3_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_3V3_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_3V3_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE ,
+ I2C_UNB2_SENS_1V2_BMR461_ADR,
+ PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_1V2_BMR461_ADR,
+ PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_1V2_BMR461_ADR,
+ PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD ,
+ I2C_UNB2_SENS_1V2_BMR461_ADR,
+ PMBUS_REG_READ_TEMP,
+
+ SMBUS_C_SAMPLE_SDA,
+ 0,
+ c_timeout_sda,
+ 0,
+ 0,
SMBUS_C_END,
SMBUS_C_NOP
);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
index 6c5be4d3ec..762b6fed6a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2b_board_sens_reg is
generic (
@@ -94,13 +94,15 @@ architecture rtl of unb2b_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
-
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ -- +1 to fit sens_err in the last address
+
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0'
+ );
signal i_temp_high : std_logic_vector(6 downto 0);
@@ -134,11 +136,11 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
-- Read access: get register value
@@ -154,7 +156,7 @@ begin
else
sla_out.rddata(6 downto 0) <= i_temp_high;
end if;
- -- else unused addresses read zero
+ -- else unused addresses read zero
end if;
end if;
end process;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
index e99056b991..f55100b5eb 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index a913aba7b0..dced0945b3 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2b_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2b_board_system_info_reg;
@@ -88,11 +88,13 @@ architecture rtl of unb2b_board_system_info_reg is
constant c_revision_id_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
constant c_design_note_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0'
+ );
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
index 92df366e56..4bed342c91 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -72,27 +72,27 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
index c8ca0c9595..cf56367668 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2b_board_wdi_reg is
port (
@@ -40,18 +40,20 @@ entity unb2b_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2b_board_wdi_reg;
architecture rtl of unb2b_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0'
+ );
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -64,7 +66,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
index 390acfb09a..287994a853 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
@@ -32,12 +32,12 @@ entity tb_mms_unb2b_board_sens is
end tb_mms_unb2b_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
architecture tb of tb_mms_unb2b_board_sens is
@@ -153,63 +153,63 @@ begin
-- I2C sensors master
u_mms_unb2b_board_sens : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => c_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
index ee3b10a99b..6c15e87d63 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk125_pll is
@@ -57,15 +57,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
index 4f4044773d..edaf8924c7 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk200_pll is
@@ -72,45 +72,45 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
index 69037930d6..a90f0b82de 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk25_pll is
@@ -57,15 +57,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
index 1d150935cf..d9ecd6710c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_node_ctrl is
@@ -76,24 +76,24 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2b_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
index 8e3a7c84de..b20152a2d9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
@@ -37,10 +37,10 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2b_board_qsfp_leds is
end tb_unb2b_board_qsfp_leds;
@@ -142,49 +142,49 @@ begin
end process;
u_unb2b_factory_qsfp_leds : entity work.unb2b_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2b_user_qsfp_leds : entity work.unb2b_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
index fd76808239..d5f1099152 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_board_10gbe is
@@ -81,17 +81,17 @@ architecture str of unb2b_board_10gbe is
begin
u_unb2b_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
diff --git a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
index 05ad57e1f9..8c0c8d4ce2 100644
--- a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
+++ b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
entity unb2c_led is
generic (
@@ -118,61 +118,61 @@ begin
-- by using the fpll, the CLKUSR is used for calibration. So in case fpll does not work, check CLKUSR
u_unb2c_board_clk200_pll : entity unb2c_board_lib.unb2c_board_clk200_pll
- generic map (
- g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
- g_technology => g_technology
- )
- port map (
- arst => xo_rst,
- clk200 => CLK,
- st_clk200 => clk200
- );
+ generic map (
+ g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
+ g_technology => g_technology
+ )
+ port map (
+ arst => xo_rst,
+ clk200 => CLK,
+ st_clk200 => clk200
+ );
xo_ethclk <= ETH_CLK(0); -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_ethclk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_ethclk,
+ out_rst => xo_rst
+ );
u_unb2c_board_clk125_pll : entity unb2c_board_lib.unb2c_board_clk125_pll
- generic map (
- g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
- g_technology => g_technology
- )
- port map (
- arst => xo_rst,
- clk125 => xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
- );
+ generic map (
+ g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
+ g_technology => g_technology
+ )
+ port map (
+ arst => xo_rst,
+ clk125 => xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
u_unb2c_board_node_ctrl : entity unb2c_board_lib.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => clk50,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
+ generic map (
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => clk50,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ );
------------------------------------------------------------------------------
-- Toggle red LED when unb2c_minimal is running, green LED for other designs.
@@ -182,15 +182,15 @@ begin
u_extend : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- p_in => mm_pulse_s,
- ep_out => led_flash
- );
+ generic map (
+ g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ p_in => mm_pulse_s,
+ ep_out => led_flash
+ );
@@ -204,36 +204,36 @@ begin
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- p_in => pulse_10Hz,
- ep_out => pulse_10Hz_extended
- );
+ generic map (
+ g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ p_in => pulse_10Hz,
+ ep_out => pulse_10Hz_extended
+ );
u_toggle : entity common_lib.common_toggle
- port map (
- rst => mm_rst,
- clk => clk50,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index a8d6353638..4a5e291a13 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2c_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2c_minimal_pkg.all;
entity mmm_unb2c_minimal is
@@ -113,29 +113,29 @@ begin
gen_mm_file_io : if g_sim = true generate
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -152,137 +152,137 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2c_minimal
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_scrap_reset_export => OPEN,
- ram_scrap_clk_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
);
end generate;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
index 7e84ec8054..bb1825c678 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
@@ -20,130 +20,130 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2c_minimal_pkg is
- ----------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus QSYS builder
- ----------------------------------------------------------------------
+ ----------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus QSYS builder
+ ----------------------------------------------------------------------
- component qsys_unb2c_minimal is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb2c_minimal;
+ component qsys_unb2c_minimal is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb2c_minimal;
end qsys_unb2c_minimal_pkg;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
index 811b44df06..12d20e85d4 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
entity unb2c_minimal is
generic (
@@ -150,211 +150,211 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
--- ETH_clk => ETH_CLK(0),
--- ETH_SGIN => ETH_SGIN(0),
--- ETH_SGOUT => ETH_SGOUT(0)
-
- ETH_clk => ETH_CLK(1),
- ETH_SGIN => ETH_SGIN(1),
- ETH_SGOUT => ETH_SGOUT(1)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ -- ETH_clk => ETH_CLK(0),
+ -- ETH_SGIN => ETH_SGIN(0),
+ -- ETH_SGOUT => ETH_SGOUT(0)
+
+ ETH_clk => ETH_CLK(1),
+ ETH_SGIN => ETH_SGIN(1),
+ ETH_SGOUT => ETH_SGOUT(1)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2c_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
index 40b4f29907..cea63067d4 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
@@ -42,20 +42,20 @@
--
library IEEE, common_lib, unb2c_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2c_minimal is
- generic (
- g_design_name : string := "unb2c_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2c_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2c_minimal;
architecture tb of tb_unb2c_minimal is
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
index a530afa748..eb86d66863 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_10GbE is
@@ -31,8 +31,8 @@ end tb_unb2c_test_10GbE;
architecture tb of tb_unb2c_test_10GbE is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2c_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index e3fba92d2d..98fd46db05 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_10GbE is
@@ -96,64 +96,64 @@ architecture str of unb2c_test_10GbE is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- --BCK_RX => BCK_RX,
- --BCK_TX => BCK_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ --BCK_RX => BCK_RX,
+ --BCK_TX => BCK_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index 4e3e8e0939..7cf1737c37 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -43,7 +43,7 @@
-- > tc_unb2_test_eth.py --gn2 0 --stream 0 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
-- stop simulation.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_1GbE_I is
@@ -71,29 +71,29 @@ begin
eth_sgin <= eth_sgout; -- loopback eth0 and eth1
u_unb2c_test_1GbE_I : entity work.unb2c_test_1GbE_I
- generic map (
- g_sim => true
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => wdi,
- INTA => OPEN,
- INTB => OPEN,
-
- -- Others
- VERSION => "00",
- ID => "00000000",
- TESTIO => OPEN,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_sgin,
- ETH_SGOUT => eth_sgout,
-
- QSFP_LED => open
- );
+ generic map (
+ g_sim => true
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => wdi,
+ INTA => OPEN,
+ INTB => OPEN,
+
+ -- Others
+ VERSION => "00",
+ ID => "00000000",
+ TESTIO => OPEN,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_sgin,
+ ETH_SGOUT => eth_sgout,
+
+ QSFP_LED => open
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
index 9bf4c129f9..4328fd0f8d 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -25,11 +25,11 @@
-- Description:
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_1GbE_I is
@@ -71,35 +71,35 @@ architecture str of unb2c_test_1GbE_I is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
index 6332e970cd..48c5067a2f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
@@ -45,7 +45,7 @@
-- for faster sim.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_1GbE_II is
@@ -73,30 +73,30 @@ begin
eth_sgin <= eth_sgout; -- loopback eth0 and eth1
u_unb2c_test_1GbE_II : entity work.unb2c_test_1GbE_II
- generic map (
- g_sim => true
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => wdi,
- INTA => OPEN,
- INTB => OPEN,
-
- -- Others
- VERSION => "00",
- ID => "00000000",
- TESTIO => OPEN,
-
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_sgin,
- ETH_SGOUT => eth_sgout,
-
- QSFP_LED => open
- );
+ generic map (
+ g_sim => true
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => wdi,
+ INTA => OPEN,
+ INTB => OPEN,
+
+ -- Others
+ VERSION => "00",
+ ID => "00000000",
+ TESTIO => OPEN,
+
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_sgin,
+ ETH_SGOUT => eth_sgout,
+
+ QSFP_LED => open
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
index 262eef85b9..0163c1438b 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
@@ -25,11 +25,11 @@
-- Description:
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_1GbE_II is
@@ -71,35 +71,35 @@ architecture str of unb2c_test_1GbE_II is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
index 0527b55ab7..c1f151cd47 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_ddr is
@@ -31,8 +31,8 @@ end tb_unb2c_test_ddr;
architecture tb of tb_unb2c_test_ddr is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_ddr"
- );
+ generic map (
+ g_design_name => "unb2c_test_ddr"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
index 193ad5ca22..3d00fd98dc 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2c_test_ddr is
@@ -82,49 +82,49 @@ architecture str of unb2c_test_ddr is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
index 64ff992ffd..700d18b758 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_ddr_16G is
@@ -31,8 +31,8 @@ end tb_unb2c_test_ddr_16G;
architecture tb of tb_unb2c_test_ddr_16G is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_ddr_16G"
- );
+ generic map (
+ g_design_name => "unb2c_test_ddr_16G"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
index 831cbf1f67..92d1b263ca 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2c_test_ddr_16G is
@@ -82,49 +82,49 @@ architecture str of unb2c_test_ddr_16G is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
index 8cf3854e05..79b43bcfc2 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_heater is
@@ -31,8 +31,8 @@ end tb_unb2c_test_heater;
architecture tb of tb_unb2c_test_heater is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_heater"
- );
+ generic map (
+ g_design_name => "unb2c_test_heater"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
index 8b2b85ed9f..7d7ac666e1 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_heater is
@@ -67,34 +67,34 @@ architecture str of unb2c_test_heater is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
index 3ca7e706a7..61bf397018 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_jesd204b is
@@ -31,8 +31,8 @@ end tb_unb2c_test_jesd204b;
architecture tb of tb_unb2c_test_jesd204b is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_jesd204b"
- );
+ generic map (
+ g_design_name => "unb2c_test_jesd204b"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
index f8cadf1c29..76007a54f0 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_jesd204b is
@@ -72,41 +72,41 @@ architecture str of unb2c_test_jesd204b is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- jesd204b
- BCK_REF_CLK => BCK_REF_CLK,
- BCK_RX => BCK_RX,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC => JESD204B_SYNC,
+ -- jesd204b
+ BCK_REF_CLK => BCK_REF_CLK,
+ BCK_RX => BCK_RX,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC => JESD204B_SYNC,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
index b0fec68285..166b031f19 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_minimal is
@@ -67,35 +67,35 @@ architecture str of unb2c_test_minimal is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 433eec002f..d02663173a 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2c_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2c_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2c_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2c_test_pkg.all;
entity mmm_unb2c_test is
@@ -287,114 +287,114 @@ begin
eth_1_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
-- . 1GbE_I with TSE setup by NiosII
u_mm_file_reg_eth_0_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
- port map(mm_rst, mm_clk, eth_0_tse_mosi, eth_0_tse_miso);
+ port map(mm_rst, mm_clk, eth_0_tse_mosi, eth_0_tse_miso);
u_mm_file_reg_eth_0_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
- port map(mm_rst, mm_clk, i_eth_0_reg_mosi, eth_0_reg_miso);
+ port map(mm_rst, mm_clk, i_eth_0_reg_mosi, eth_0_reg_miso);
u_mm_file_reg_eth_0_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
- port map(mm_rst, mm_clk, eth_0_ram_mosi, eth_0_ram_miso);
+ port map(mm_rst, mm_clk, eth_0_ram_mosi, eth_0_ram_miso);
-- . 1GbE_II with TSE setup in VHDL
u_mm_file_reg_eth_1_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
- port map(mm_rst, mm_clk, eth_1_tse_mosi, eth_1_tse_miso);
+ port map(mm_rst, mm_clk, eth_1_tse_mosi, eth_1_tse_miso);
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
u_mm_file_reg_reg_diag_bg_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_0")
- port map(mm_rst, mm_clk, reg_diag_bg_eth_0_copi, reg_diag_bg_eth_0_cipo );
+ port map(mm_rst, mm_clk, reg_diag_bg_eth_0_copi, reg_diag_bg_eth_0_cipo );
u_mm_file_reg_hdr_dat_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_0")
- port map(mm_rst, mm_clk, reg_hdr_dat_eth_0_copi, reg_hdr_dat_eth_0_cipo );
+ port map(mm_rst, mm_clk, reg_hdr_dat_eth_0_copi, reg_hdr_dat_eth_0_cipo );
u_mm_file_reg_bsn_monitor_v2_tx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_0")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_0_copi, reg_bsn_monitor_v2_tx_eth_0_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_0_copi, reg_bsn_monitor_v2_tx_eth_0_cipo );
u_mm_file_reg_strobe_total_count_tx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_0")
- port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_0_copi, reg_strobe_total_count_tx_eth_0_cipo );
+ port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_0_copi, reg_strobe_total_count_tx_eth_0_cipo );
u_mm_file_reg_bsn_monitor_v2_rx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_0")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_0_copi, reg_bsn_monitor_v2_rx_eth_0_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_0_copi, reg_bsn_monitor_v2_rx_eth_0_cipo );
u_mm_file_reg_strobe_total_count_rx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_0")
- port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_0_copi, reg_strobe_total_count_rx_eth_0_cipo );
+ port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_0_copi, reg_strobe_total_count_rx_eth_0_cipo );
u_mm_file_reg_reg_diag_bg_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_1")
- port map(mm_rst, mm_clk, reg_diag_bg_eth_1_copi, reg_diag_bg_eth_1_cipo );
+ port map(mm_rst, mm_clk, reg_diag_bg_eth_1_copi, reg_diag_bg_eth_1_cipo );
u_mm_file_reg_hdr_dat_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_1")
- port map(mm_rst, mm_clk, reg_hdr_dat_eth_1_copi, reg_hdr_dat_eth_1_cipo );
+ port map(mm_rst, mm_clk, reg_hdr_dat_eth_1_copi, reg_hdr_dat_eth_1_cipo );
u_mm_file_reg_bsn_monitor_v2_tx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_1")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_1_copi, reg_bsn_monitor_v2_tx_eth_1_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_1_copi, reg_bsn_monitor_v2_tx_eth_1_cipo );
u_mm_file_reg_strobe_total_count_tx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_1")
- port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_1_copi, reg_strobe_total_count_tx_eth_1_cipo );
+ port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_1_copi, reg_strobe_total_count_tx_eth_1_cipo );
u_mm_file_reg_bsn_monitor_v2_rx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_1")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_1_copi, reg_bsn_monitor_v2_rx_eth_1_cipo );
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_1_copi, reg_bsn_monitor_v2_rx_eth_1_cipo );
u_mm_file_reg_strobe_total_count_rx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_1")
- port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_1_copi, reg_strobe_total_count_rx_eth_1_cipo );
+ port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_1_copi, reg_strobe_total_count_rx_eth_1_cipo );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -419,10 +419,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth_0_reg_mosi, i_eth_0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth_0_reg_mosi <= sim_eth_0_reg_mosi;
- else
- eth_0_reg_mosi <= i_eth_0_reg_mosi;
- end if;
+ eth_0_reg_mosi <= sim_eth_0_reg_mosi;
+ else
+ eth_0_reg_mosi <= i_eth_0_reg_mosi;
+ end if;
end process;
@@ -441,464 +441,464 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
u_qsys : qsys_unb2c_test
- port map (
-
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth_0_mm_rst,
- avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth_0_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth_0_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth_0_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth_0_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth_0_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth_0_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth_0_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth_0_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth_0_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth_0_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth_0_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth_0_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth_0_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth_0_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth_0_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth_0_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth_0_reg_interrupt,
-
- avs_eth_1_reset_export => eth_1_mm_rst,
- avs_eth_1_clk_export => OPEN,
- avs_eth_1_tse_address_export => eth_1_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_1_tse_write_export => eth_1_tse_mosi.wr,
- avs_eth_1_tse_read_export => eth_1_tse_mosi.rd,
- avs_eth_1_tse_writedata_export => eth_1_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_tse_readdata_export => eth_1_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_tse_waitrequest_export => eth_1_tse_miso.waitrequest,
- avs_eth_1_reg_address_export => eth_1_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_1_reg_write_export => eth_1_reg_mosi.wr,
- avs_eth_1_reg_read_export => eth_1_reg_mosi.rd,
- avs_eth_1_reg_writedata_export => eth_1_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_reg_readdata_export => eth_1_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_ram_address_export => eth_1_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_1_ram_write_export => eth_1_ram_mosi.wr,
- avs_eth_1_ram_read_export => eth_1_ram_mosi.rd,
- avs_eth_1_ram_writedata_export => eth_1_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_1_ram_readdata_export => eth_1_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_1_irq_export => eth_1_reg_interrupt,
-
- reg_fpga_temp_sens_reset_export => OPEN,
- reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_reset_export => OPEN,
- reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_reset_export => OPEN,
- rom_system_info_clk_export => OPEN,
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_reset_export => OPEN,
- pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_reset_export => OPEN,
- pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_reset_export => OPEN,
- reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_reset_export => OPEN,
- reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_reset_export => OPEN,
- reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_reset_export => OPEN,
- reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_reset_export => OPEN,
- reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_reset_export => OPEN,
- reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_reset_export => OPEN,
- reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
- reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
- reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
- reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
- reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
-
- reg_tr_10gbe_back0_reset_export => OPEN,
- reg_tr_10gbe_back0_clk_export => OPEN,
- reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w - 1 downto 0),
- reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
- reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
- reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w - 1 downto 0),
- reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
-
- reg_eth10g_qsfp_ring_reset_export => OPEN,
- reg_eth10g_qsfp_ring_clk_export => OPEN,
- reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w - 1 downto 0),
- reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
- reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
- reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
-
- reg_eth10g_back0_reset_export => OPEN,
- reg_eth10g_back0_clk_export => OPEN,
- reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w - 1 downto 0),
- reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
- reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w - 1 downto 0),
- reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
- reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_10gbe_reset_export => OPEN,
- reg_bsn_monitor_10gbe_clk_export => OPEN,
- reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
- reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
- reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
- reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_10gbe_reset_export => OPEN,
- reg_diag_data_buffer_10gbe_clk_export => OPEN,
- reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(5 downto 0),
- reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
- reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
- reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_10gbe_clk_export => OPEN,
- ram_diag_data_buffer_10gbe_reset_export => OPEN,
- ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w - 1 downto 0),
- ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
- ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
- ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_10GbE_reset_export => OPEN,
- reg_diag_bg_10GbE_clk_export => OPEN,
- reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
- reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
- reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_bg_10GbE_reset_export => OPEN,
- ram_diag_bg_10GbE_clk_export => OPEN,
- ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
- ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
- ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
- ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_I_clk_export => OPEN,
- reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
- reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_I_reset_export => OPEN,
- reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
- reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
- reg_io_ddr_MB_II_clk_export => OPEN,
- reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
- reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
- reg_io_ddr_MB_II_reset_export => OPEN,
- reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
- reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
- reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
- reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
- reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
- reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
- reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
- reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
- reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
- reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
- ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
- ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
- ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
- ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
- ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_eth_0_reset_export => OPEN,
- reg_diag_bg_eth_0_clk_export => OPEN,
- reg_diag_bg_eth_0_address_export => reg_diag_bg_eth_0_copi.address(4 downto 0),
- reg_diag_bg_eth_0_write_export => reg_diag_bg_eth_0_copi.wr,
- reg_diag_bg_eth_0_writedata_export => reg_diag_bg_eth_0_copi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_eth_0_read_export => reg_diag_bg_eth_0_copi.rd,
- reg_diag_bg_eth_0_readdata_export => reg_diag_bg_eth_0_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_hdr_dat_eth_0_reset_export => OPEN,
- reg_hdr_dat_eth_0_clk_export => OPEN,
- reg_hdr_dat_eth_0_address_export => reg_hdr_dat_eth_0_copi.address(6 downto 0),
- reg_hdr_dat_eth_0_write_export => reg_hdr_dat_eth_0_copi.wr,
- reg_hdr_dat_eth_0_writedata_export => reg_hdr_dat_eth_0_copi.wrdata(c_word_w - 1 downto 0),
- reg_hdr_dat_eth_0_read_export => reg_hdr_dat_eth_0_copi.rd,
- reg_hdr_dat_eth_0_readdata_export => reg_hdr_dat_eth_0_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_tx_eth_0_reset_export => OPEN,
- reg_bsn_monitor_v2_tx_eth_0_clk_export => OPEN,
- reg_bsn_monitor_v2_tx_eth_0_address_export => reg_bsn_monitor_v2_tx_eth_0_copi.address(4 downto 0),
- reg_bsn_monitor_v2_tx_eth_0_write_export => reg_bsn_monitor_v2_tx_eth_0_copi.wr,
- reg_bsn_monitor_v2_tx_eth_0_writedata_export => reg_bsn_monitor_v2_tx_eth_0_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_tx_eth_0_read_export => reg_bsn_monitor_v2_tx_eth_0_copi.rd,
- reg_bsn_monitor_v2_tx_eth_0_readdata_export => reg_bsn_monitor_v2_tx_eth_0_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_strobe_total_count_tx_eth_0_reset_export => OPEN,
- reg_strobe_total_count_tx_eth_0_clk_export => OPEN,
- reg_strobe_total_count_tx_eth_0_address_export => reg_strobe_total_count_tx_eth_0_copi.address(6 downto 0),
- reg_strobe_total_count_tx_eth_0_write_export => reg_strobe_total_count_tx_eth_0_copi.wr,
- reg_strobe_total_count_tx_eth_0_writedata_export => reg_strobe_total_count_tx_eth_0_copi.wrdata(c_word_w - 1 downto 0),
- reg_strobe_total_count_tx_eth_0_read_export => reg_strobe_total_count_tx_eth_0_copi.rd,
- reg_strobe_total_count_tx_eth_0_readdata_export => reg_strobe_total_count_tx_eth_0_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_rx_eth_0_reset_export => OPEN,
- reg_bsn_monitor_v2_rx_eth_0_clk_export => OPEN,
- reg_bsn_monitor_v2_rx_eth_0_address_export => reg_bsn_monitor_v2_rx_eth_0_copi.address(4 downto 0),
- reg_bsn_monitor_v2_rx_eth_0_write_export => reg_bsn_monitor_v2_rx_eth_0_copi.wr,
- reg_bsn_monitor_v2_rx_eth_0_writedata_export => reg_bsn_monitor_v2_rx_eth_0_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_eth_0_read_export => reg_bsn_monitor_v2_rx_eth_0_copi.rd,
- reg_bsn_monitor_v2_rx_eth_0_readdata_export => reg_bsn_monitor_v2_rx_eth_0_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_strobe_total_count_rx_eth_0_reset_export => OPEN,
- reg_strobe_total_count_rx_eth_0_clk_export => OPEN,
- reg_strobe_total_count_rx_eth_0_address_export => reg_strobe_total_count_rx_eth_0_copi.address(6 downto 0),
- reg_strobe_total_count_rx_eth_0_write_export => reg_strobe_total_count_rx_eth_0_copi.wr,
- reg_strobe_total_count_rx_eth_0_writedata_export => reg_strobe_total_count_rx_eth_0_copi.wrdata(c_word_w - 1 downto 0),
- reg_strobe_total_count_rx_eth_0_read_export => reg_strobe_total_count_rx_eth_0_copi.rd,
- reg_strobe_total_count_rx_eth_0_readdata_export => reg_strobe_total_count_rx_eth_0_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_diag_bg_eth_1_reset_export => OPEN,
- reg_diag_bg_eth_1_clk_export => OPEN,
- reg_diag_bg_eth_1_address_export => reg_diag_bg_eth_1_copi.address(2 downto 0),
- reg_diag_bg_eth_1_write_export => reg_diag_bg_eth_1_copi.wr,
- reg_diag_bg_eth_1_writedata_export => reg_diag_bg_eth_1_copi.wrdata(c_word_w - 1 downto 0),
- reg_diag_bg_eth_1_read_export => reg_diag_bg_eth_1_copi.rd,
- reg_diag_bg_eth_1_readdata_export => reg_diag_bg_eth_1_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_hdr_dat_eth_1_reset_export => OPEN,
- reg_hdr_dat_eth_1_clk_export => OPEN,
- reg_hdr_dat_eth_1_address_export => reg_hdr_dat_eth_1_copi.address(4 downto 0),
- reg_hdr_dat_eth_1_write_export => reg_hdr_dat_eth_1_copi.wr,
- reg_hdr_dat_eth_1_writedata_export => reg_hdr_dat_eth_1_copi.wrdata(c_word_w - 1 downto 0),
- reg_hdr_dat_eth_1_read_export => reg_hdr_dat_eth_1_copi.rd,
- reg_hdr_dat_eth_1_readdata_export => reg_hdr_dat_eth_1_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_tx_eth_1_reset_export => OPEN,
- reg_bsn_monitor_v2_tx_eth_1_clk_export => OPEN,
- reg_bsn_monitor_v2_tx_eth_1_address_export => reg_bsn_monitor_v2_tx_eth_1_copi.address(2 downto 0),
- reg_bsn_monitor_v2_tx_eth_1_write_export => reg_bsn_monitor_v2_tx_eth_1_copi.wr,
- reg_bsn_monitor_v2_tx_eth_1_writedata_export => reg_bsn_monitor_v2_tx_eth_1_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_tx_eth_1_read_export => reg_bsn_monitor_v2_tx_eth_1_copi.rd,
- reg_bsn_monitor_v2_tx_eth_1_readdata_export => reg_bsn_monitor_v2_tx_eth_1_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_strobe_total_count_tx_eth_1_reset_export => OPEN,
- reg_strobe_total_count_tx_eth_1_clk_export => OPEN,
- reg_strobe_total_count_tx_eth_1_address_export => reg_strobe_total_count_tx_eth_1_copi.address(4 downto 0),
- reg_strobe_total_count_tx_eth_1_write_export => reg_strobe_total_count_tx_eth_1_copi.wr,
- reg_strobe_total_count_tx_eth_1_writedata_export => reg_strobe_total_count_tx_eth_1_copi.wrdata(c_word_w - 1 downto 0),
- reg_strobe_total_count_tx_eth_1_read_export => reg_strobe_total_count_tx_eth_1_copi.rd,
- reg_strobe_total_count_tx_eth_1_readdata_export => reg_strobe_total_count_tx_eth_1_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_v2_rx_eth_1_reset_export => OPEN,
- reg_bsn_monitor_v2_rx_eth_1_clk_export => OPEN,
- reg_bsn_monitor_v2_rx_eth_1_address_export => reg_bsn_monitor_v2_rx_eth_1_copi.address(2 downto 0),
- reg_bsn_monitor_v2_rx_eth_1_write_export => reg_bsn_monitor_v2_rx_eth_1_copi.wr,
- reg_bsn_monitor_v2_rx_eth_1_writedata_export => reg_bsn_monitor_v2_rx_eth_1_copi.wrdata(c_word_w - 1 downto 0),
- reg_bsn_monitor_v2_rx_eth_1_read_export => reg_bsn_monitor_v2_rx_eth_1_copi.rd,
- reg_bsn_monitor_v2_rx_eth_1_readdata_export => reg_bsn_monitor_v2_rx_eth_1_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_strobe_total_count_rx_eth_1_reset_export => OPEN,
- reg_strobe_total_count_rx_eth_1_clk_export => OPEN,
- reg_strobe_total_count_rx_eth_1_address_export => reg_strobe_total_count_rx_eth_1_copi.address(4 downto 0),
- reg_strobe_total_count_rx_eth_1_write_export => reg_strobe_total_count_rx_eth_1_copi.wr,
- reg_strobe_total_count_rx_eth_1_writedata_export => reg_strobe_total_count_rx_eth_1_copi.wrdata(c_word_w - 1 downto 0),
- reg_strobe_total_count_rx_eth_1_read_export => reg_strobe_total_count_rx_eth_1_copi.rd,
- reg_strobe_total_count_rx_eth_1_readdata_export => reg_strobe_total_count_rx_eth_1_cipo.rddata(c_word_w - 1 downto 0),
-
- reg_heater_reset_export => OPEN,
- reg_heater_clk_export => OPEN,
- reg_heater_address_export => reg_heater_mosi.address(4 downto 0),
- reg_heater_read_export => reg_heater_mosi.rd,
- reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
- reg_heater_write_export => reg_heater_mosi.wr,
- reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0),
-
- jesd204b_reset_export => OPEN,
- jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(11 downto 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
-
- pio_jesd_ctrl_reset_export => OPEN,
- pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(0 downto 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(7 downto 0),
- reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_bsn_source_clk_export => OPEN,
- reg_bsn_source_reset_export => OPEN,
- reg_bsn_source_address_export => reg_bsn_source_mosi.address(1 downto 0),
- reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
- reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
- reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
- reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
-
- ram_diag_data_buffer_bsn_clk_export => OPEN,
- ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0), -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
- ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_data_buffer_bsn_reset_export => OPEN,
- reg_diag_data_buffer_bsn_clk_export => OPEN,
- reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(12 - 1 downto 0),
- reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
-
- ram_scrap_reset_export => OPEN,
- ram_scrap_clk_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
- );
+ port map (
+
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth_0_mm_rst,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth_0_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth_0_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth_0_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth_0_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth_0_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth_0_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth_0_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth_0_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth_0_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth_0_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth_0_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth_0_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth_0_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth_0_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth_0_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth_0_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth_0_reg_interrupt,
+
+ avs_eth_1_reset_export => eth_1_mm_rst,
+ avs_eth_1_clk_export => OPEN,
+ avs_eth_1_tse_address_export => eth_1_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_1_tse_write_export => eth_1_tse_mosi.wr,
+ avs_eth_1_tse_read_export => eth_1_tse_mosi.rd,
+ avs_eth_1_tse_writedata_export => eth_1_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_tse_readdata_export => eth_1_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_tse_waitrequest_export => eth_1_tse_miso.waitrequest,
+ avs_eth_1_reg_address_export => eth_1_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_1_reg_write_export => eth_1_reg_mosi.wr,
+ avs_eth_1_reg_read_export => eth_1_reg_mosi.rd,
+ avs_eth_1_reg_writedata_export => eth_1_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_reg_readdata_export => eth_1_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_ram_address_export => eth_1_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_1_ram_write_export => eth_1_ram_mosi.wr,
+ avs_eth_1_ram_read_export => eth_1_ram_mosi.rd,
+ avs_eth_1_ram_writedata_export => eth_1_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_1_ram_readdata_export => eth_1_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_1_irq_export => eth_1_reg_interrupt,
+
+ reg_fpga_temp_sens_reset_export => OPEN,
+ reg_fpga_temp_sens_clk_export => OPEN,
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_reset_export => OPEN,
+ reg_fpga_voltage_sens_clk_export => OPEN,
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1 downto 0),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
+ reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_write_export => reg_tr_10GbE_qsfp_ring_mosi.wr,
+ reg_tr_10gbe_qsfp_ring_writedata_export => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_read_export => reg_tr_10GbE_qsfp_ring_mosi.rd,
+ reg_tr_10gbe_qsfp_ring_readdata_export => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
+
+ reg_tr_10gbe_back0_reset_export => OPEN,
+ reg_tr_10gbe_back0_clk_export => OPEN,
+ reg_tr_10gbe_back0_address_export => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w - 1 downto 0),
+ reg_tr_10gbe_back0_write_export => reg_tr_10GbE_back0_mosi.wr,
+ reg_tr_10gbe_back0_writedata_export => reg_tr_10GbE_back0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back0_read_export => reg_tr_10GbE_back0_mosi.rd,
+ reg_tr_10gbe_back0_readdata_export => reg_tr_10GbE_back0_miso.rddata(c_word_w - 1 downto 0),
+ reg_tr_10gbe_back0_waitrequest_export => reg_tr_10GbE_back0_miso.waitrequest,
+
+ reg_eth10g_qsfp_ring_reset_export => OPEN,
+ reg_eth10g_qsfp_ring_clk_export => OPEN,
+ reg_eth10g_qsfp_ring_address_export => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w - 1 downto 0),
+ reg_eth10g_qsfp_ring_write_export => reg_eth10g_qsfp_ring_mosi.wr,
+ reg_eth10g_qsfp_ring_writedata_export => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_qsfp_ring_read_export => reg_eth10g_qsfp_ring_mosi.rd,
+ reg_eth10g_qsfp_ring_readdata_export => reg_eth10g_qsfp_ring_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_eth10g_back0_reset_export => OPEN,
+ reg_eth10g_back0_clk_export => OPEN,
+ reg_eth10g_back0_address_export => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w - 1 downto 0),
+ reg_eth10g_back0_write_export => reg_eth10g_back0_mosi.wr,
+ reg_eth10g_back0_writedata_export => reg_eth10g_back0_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_eth10g_back0_read_export => reg_eth10g_back0_mosi.rd,
+ reg_eth10g_back0_readdata_export => reg_eth10g_back0_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_10gbe_reset_export => OPEN,
+ reg_bsn_monitor_10gbe_clk_export => OPEN,
+ reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w - 1 downto 0),
+ reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
+ reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
+ reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_10gbe_reset_export => OPEN,
+ reg_diag_data_buffer_10gbe_clk_export => OPEN,
+ reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(5 downto 0),
+ reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
+ reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
+ reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_10gbe_clk_export => OPEN,
+ ram_diag_data_buffer_10gbe_reset_export => OPEN,
+ ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w - 1 downto 0),
+ ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
+ ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
+ ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_10GbE_reset_export => OPEN,
+ reg_diag_bg_10GbE_clk_export => OPEN,
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
+ reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
+ reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_bg_10GbE_reset_export => OPEN,
+ ram_diag_bg_10GbE_clk_export => OPEN,
+ ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w - 1 downto 0),
+ ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
+ ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
+ ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_I_clk_export => OPEN,
+ reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
+ reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_I_reset_export => OPEN,
+ reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
+ reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_io_ddr_adr_w - 1 downto 0),
+ reg_io_ddr_MB_II_clk_export => OPEN,
+ reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
+ reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_io_ddr_MB_II_reset_export => OPEN,
+ reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
+ reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_rx_seq_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_eth_0_reset_export => OPEN,
+ reg_diag_bg_eth_0_clk_export => OPEN,
+ reg_diag_bg_eth_0_address_export => reg_diag_bg_eth_0_copi.address(4 downto 0),
+ reg_diag_bg_eth_0_write_export => reg_diag_bg_eth_0_copi.wr,
+ reg_diag_bg_eth_0_writedata_export => reg_diag_bg_eth_0_copi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_eth_0_read_export => reg_diag_bg_eth_0_copi.rd,
+ reg_diag_bg_eth_0_readdata_export => reg_diag_bg_eth_0_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_hdr_dat_eth_0_reset_export => OPEN,
+ reg_hdr_dat_eth_0_clk_export => OPEN,
+ reg_hdr_dat_eth_0_address_export => reg_hdr_dat_eth_0_copi.address(6 downto 0),
+ reg_hdr_dat_eth_0_write_export => reg_hdr_dat_eth_0_copi.wr,
+ reg_hdr_dat_eth_0_writedata_export => reg_hdr_dat_eth_0_copi.wrdata(c_word_w - 1 downto 0),
+ reg_hdr_dat_eth_0_read_export => reg_hdr_dat_eth_0_copi.rd,
+ reg_hdr_dat_eth_0_readdata_export => reg_hdr_dat_eth_0_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_tx_eth_0_reset_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_0_clk_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_0_address_export => reg_bsn_monitor_v2_tx_eth_0_copi.address(4 downto 0),
+ reg_bsn_monitor_v2_tx_eth_0_write_export => reg_bsn_monitor_v2_tx_eth_0_copi.wr,
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export => reg_bsn_monitor_v2_tx_eth_0_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_tx_eth_0_read_export => reg_bsn_monitor_v2_tx_eth_0_copi.rd,
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export => reg_bsn_monitor_v2_tx_eth_0_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_strobe_total_count_tx_eth_0_reset_export => OPEN,
+ reg_strobe_total_count_tx_eth_0_clk_export => OPEN,
+ reg_strobe_total_count_tx_eth_0_address_export => reg_strobe_total_count_tx_eth_0_copi.address(6 downto 0),
+ reg_strobe_total_count_tx_eth_0_write_export => reg_strobe_total_count_tx_eth_0_copi.wr,
+ reg_strobe_total_count_tx_eth_0_writedata_export => reg_strobe_total_count_tx_eth_0_copi.wrdata(c_word_w - 1 downto 0),
+ reg_strobe_total_count_tx_eth_0_read_export => reg_strobe_total_count_tx_eth_0_copi.rd,
+ reg_strobe_total_count_tx_eth_0_readdata_export => reg_strobe_total_count_tx_eth_0_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_rx_eth_0_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_0_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_0_address_export => reg_bsn_monitor_v2_rx_eth_0_copi.address(4 downto 0),
+ reg_bsn_monitor_v2_rx_eth_0_write_export => reg_bsn_monitor_v2_rx_eth_0_copi.wr,
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export => reg_bsn_monitor_v2_rx_eth_0_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_eth_0_read_export => reg_bsn_monitor_v2_rx_eth_0_copi.rd,
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export => reg_bsn_monitor_v2_rx_eth_0_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_strobe_total_count_rx_eth_0_reset_export => OPEN,
+ reg_strobe_total_count_rx_eth_0_clk_export => OPEN,
+ reg_strobe_total_count_rx_eth_0_address_export => reg_strobe_total_count_rx_eth_0_copi.address(6 downto 0),
+ reg_strobe_total_count_rx_eth_0_write_export => reg_strobe_total_count_rx_eth_0_copi.wr,
+ reg_strobe_total_count_rx_eth_0_writedata_export => reg_strobe_total_count_rx_eth_0_copi.wrdata(c_word_w - 1 downto 0),
+ reg_strobe_total_count_rx_eth_0_read_export => reg_strobe_total_count_rx_eth_0_copi.rd,
+ reg_strobe_total_count_rx_eth_0_readdata_export => reg_strobe_total_count_rx_eth_0_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_bg_eth_1_reset_export => OPEN,
+ reg_diag_bg_eth_1_clk_export => OPEN,
+ reg_diag_bg_eth_1_address_export => reg_diag_bg_eth_1_copi.address(2 downto 0),
+ reg_diag_bg_eth_1_write_export => reg_diag_bg_eth_1_copi.wr,
+ reg_diag_bg_eth_1_writedata_export => reg_diag_bg_eth_1_copi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_bg_eth_1_read_export => reg_diag_bg_eth_1_copi.rd,
+ reg_diag_bg_eth_1_readdata_export => reg_diag_bg_eth_1_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_hdr_dat_eth_1_reset_export => OPEN,
+ reg_hdr_dat_eth_1_clk_export => OPEN,
+ reg_hdr_dat_eth_1_address_export => reg_hdr_dat_eth_1_copi.address(4 downto 0),
+ reg_hdr_dat_eth_1_write_export => reg_hdr_dat_eth_1_copi.wr,
+ reg_hdr_dat_eth_1_writedata_export => reg_hdr_dat_eth_1_copi.wrdata(c_word_w - 1 downto 0),
+ reg_hdr_dat_eth_1_read_export => reg_hdr_dat_eth_1_copi.rd,
+ reg_hdr_dat_eth_1_readdata_export => reg_hdr_dat_eth_1_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_tx_eth_1_reset_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_1_clk_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_1_address_export => reg_bsn_monitor_v2_tx_eth_1_copi.address(2 downto 0),
+ reg_bsn_monitor_v2_tx_eth_1_write_export => reg_bsn_monitor_v2_tx_eth_1_copi.wr,
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export => reg_bsn_monitor_v2_tx_eth_1_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_tx_eth_1_read_export => reg_bsn_monitor_v2_tx_eth_1_copi.rd,
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export => reg_bsn_monitor_v2_tx_eth_1_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_strobe_total_count_tx_eth_1_reset_export => OPEN,
+ reg_strobe_total_count_tx_eth_1_clk_export => OPEN,
+ reg_strobe_total_count_tx_eth_1_address_export => reg_strobe_total_count_tx_eth_1_copi.address(4 downto 0),
+ reg_strobe_total_count_tx_eth_1_write_export => reg_strobe_total_count_tx_eth_1_copi.wr,
+ reg_strobe_total_count_tx_eth_1_writedata_export => reg_strobe_total_count_tx_eth_1_copi.wrdata(c_word_w - 1 downto 0),
+ reg_strobe_total_count_tx_eth_1_read_export => reg_strobe_total_count_tx_eth_1_copi.rd,
+ reg_strobe_total_count_tx_eth_1_readdata_export => reg_strobe_total_count_tx_eth_1_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_v2_rx_eth_1_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_1_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_1_address_export => reg_bsn_monitor_v2_rx_eth_1_copi.address(2 downto 0),
+ reg_bsn_monitor_v2_rx_eth_1_write_export => reg_bsn_monitor_v2_rx_eth_1_copi.wr,
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export => reg_bsn_monitor_v2_rx_eth_1_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_v2_rx_eth_1_read_export => reg_bsn_monitor_v2_rx_eth_1_copi.rd,
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export => reg_bsn_monitor_v2_rx_eth_1_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_strobe_total_count_rx_eth_1_reset_export => OPEN,
+ reg_strobe_total_count_rx_eth_1_clk_export => OPEN,
+ reg_strobe_total_count_rx_eth_1_address_export => reg_strobe_total_count_rx_eth_1_copi.address(4 downto 0),
+ reg_strobe_total_count_rx_eth_1_write_export => reg_strobe_total_count_rx_eth_1_copi.wr,
+ reg_strobe_total_count_rx_eth_1_writedata_export => reg_strobe_total_count_rx_eth_1_copi.wrdata(c_word_w - 1 downto 0),
+ reg_strobe_total_count_rx_eth_1_read_export => reg_strobe_total_count_rx_eth_1_copi.rd,
+ reg_strobe_total_count_rx_eth_1_readdata_export => reg_strobe_total_count_rx_eth_1_cipo.rddata(c_word_w - 1 downto 0),
+
+ reg_heater_reset_export => OPEN,
+ reg_heater_clk_export => OPEN,
+ reg_heater_address_export => reg_heater_mosi.address(4 downto 0),
+ reg_heater_read_export => reg_heater_mosi.rd,
+ reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
+ reg_heater_write_export => reg_heater_mosi.wr,
+ reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0),
+
+ jesd204b_reset_export => OPEN,
+ jesd204b_clk_export => OPEN,
+ jesd204b_address_export => jesd204b_mosi.address(11 downto 0),
+ jesd204b_write_export => jesd204b_mosi.wr,
+ jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
+ jesd204b_read_export => jesd204b_mosi.rd,
+ jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_jesd_ctrl_reset_export => OPEN,
+ pio_jesd_ctrl_clk_export => OPEN,
+ pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(0 downto 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(7 downto 0),
+ reg_bsn_monitor_input_clk_export => OPEN,
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_monitor_input_reset_export => OPEN,
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_bsn_source_clk_export => OPEN,
+ reg_bsn_source_reset_export => OPEN,
+ reg_bsn_source_address_export => reg_bsn_source_mosi.address(1 downto 0),
+ reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
+ reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
+ reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
+ reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
+
+ ram_diag_data_buffer_bsn_clk_export => OPEN,
+ ram_diag_data_buffer_bsn_reset_export => OPEN,
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0), -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_data_buffer_bsn_reset_export => OPEN,
+ reg_diag_data_buffer_bsn_clk_export => OPEN,
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(12 - 1 downto 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w - 1 downto 0),
+
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(8 downto 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
index 3364ccf86d..f1ecdba410 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
@@ -27,15 +27,15 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity node_adc_input_and_timing_nowg is
generic (
@@ -88,11 +88,13 @@ end node_adc_input_and_timing_nowg;
architecture str of node_adc_input_and_timing_nowg is
- constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0'
+ );
-- Frame parameters TBC
constant c_bs_bsn_w : natural := 64; -- 51;
@@ -136,62 +138,62 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_nof_sync_n => g_nof_sync_n,
- g_jesd_freq => g_jesd_freq
- )
- port map(
- jesd204b_refclk => jesd204b_refclk,
- jesd204b_sysref => jesd204b_sysref,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_internal,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => jesd204b_serial_data(g_nof_streams - 1 downto 0)
- );
+ generic map(
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_nof_sync_n => g_nof_sync_n,
+ g_jesd_freq => g_jesd_freq
+ )
+ port map(
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => jesd204b_serial_data(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source : entity dp_lib.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_mosi,
+ reg_miso => reg_bsn_source_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
mux_sosi_arr <= rx_sosi_arr when rising_edge(rx_clk);
@@ -220,74 +222,74 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => g_bsn_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => g_bsn_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
+ -----------------------------------------------------------------------------
+ -- Diagnostic Data Buffer
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg,
- in_reg => mm_jesd_ctrl_reg
- );
+ generic map (
+ g_reg => c_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg,
+ in_reg => mm_jesd_ctrl_reg
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index e39ec207d0..6e076d3ead 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -20,450 +20,450 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2c_test_pkg is
- component qsys_unb2c_test is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_eth_0_reset_export : out std_logic; -- export
- reg_diag_bg_eth_0_clk_export : out std_logic; -- export
- reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_bg_eth_0_write_export : out std_logic; -- export
- reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_eth_0_read_export : out std_logic; -- export
- reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_eth_1_reset_export : out std_logic; -- export
- reg_diag_bg_eth_1_clk_export : out std_logic; -- export
- reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_eth_1_write_export : out std_logic; -- export
- reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_eth_1_read_export : out std_logic; -- export
- reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
- reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
- reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_hdr_dat_eth_1_write_export : out std_logic; -- export
- reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_eth_1_read_export : out std_logic; -- export
- reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
- reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
- reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_eth_0_write_export : out std_logic; -- export
- reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_eth_0_read_export : out std_logic; -- export
- reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb2c_test;
+ component qsys_unb2c_test is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_0_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_0_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_bg_eth_0_write_export : out std_logic; -- export
+ reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_0_read_export : out std_logic; -- export
+ reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_1_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_1_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_eth_1_write_export : out std_logic; -- export
+ reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_1_read_export : out std_logic; -- export
+ reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_hdr_dat_eth_1_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_1_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_eth_0_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_0_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb2c_test;
end qsys_unb2c_test_pkg;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
index 369db0c801..d453adc0c0 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2c_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2c_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2c_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -105,14 +105,28 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC(
+ g_bg_block_size,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ g_bg_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ g_bg_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ g_bg_block_size-1,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
constant c_nof_crc_words : natural := 1;
@@ -157,54 +171,54 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
@@ -212,74 +226,74 @@ begin
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
@@ -304,55 +318,55 @@ begin
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index 4e407950f5..697d7c255f 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -21,22 +21,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, tech_jesd204b_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2c_test_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2c_test_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2c_test is
@@ -340,7 +340,7 @@ architecture str of unb2c_test is
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 - 1 downto 0);
--- SIGNAL serial_rx_jesd204b_back_arr : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
+ -- SIGNAL serial_rx_jesd204b_back_arr : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
signal reg_10gbase_r_24_mosi : t_mem_mosi;
signal reg_10gbase_r_24_miso : t_mem_miso;
@@ -476,327 +476,327 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
- g_udp_offload => c_use_eth_0_UDP,
- g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth_0_mm_rst,
- eth1g_tse_mosi => eth_0_tse_mosi,
- eth1g_tse_miso => eth_0_tse_miso,
- eth1g_reg_mosi => eth_0_reg_mosi,
- eth1g_reg_miso => eth_0_reg_miso,
- eth1g_reg_interrupt => eth_0_reg_interrupt,
- eth1g_ram_mosi => eth_0_ram_mosi,
- eth1g_ram_miso => eth_0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth_0_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth_0_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth_0_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth_0_udp_rx_siso_arr,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
+ g_udp_offload => c_use_eth_0_UDP,
+ g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth_0_mm_rst,
+ eth1g_tse_mosi => eth_0_tse_mosi,
+ eth1g_tse_miso => eth_0_tse_miso,
+ eth1g_reg_mosi => eth_0_reg_mosi,
+ eth1g_reg_miso => eth_0_reg_miso,
+ eth1g_reg_interrupt => eth_0_reg_interrupt,
+ eth1g_ram_mosi => eth_0_ram_mosi,
+ eth1g_ram_miso => eth_0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth_0_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth_0_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth_0_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth_0_udp_rx_siso_arr,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2c_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_qsfp => c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w,
- g_nof_streams_ring => c_unb2c_board_tr_ring.nof_bus * c_unb2c_board_tr_ring.bus_w,
- g_nof_streams_back0 => c_unb2c_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth_0_mm_rst => eth_0_mm_rst,
- eth_0_tse_mosi => eth_0_tse_mosi,
- eth_0_tse_miso => eth_0_tse_miso,
- eth_0_reg_mosi => eth_0_reg_mosi,
- eth_0_reg_miso => eth_0_reg_miso,
- eth_0_reg_interrupt => eth_0_reg_interrupt,
- eth_0_ram_mosi => eth_0_ram_mosi,
- eth_0_ram_miso => eth_0_ram_miso,
-
- reg_diag_bg_eth_0_copi => reg_diag_bg_eth_0_copi,
- reg_diag_bg_eth_0_cipo => reg_diag_bg_eth_0_cipo,
- reg_hdr_dat_eth_0_copi => reg_hdr_dat_eth_0_copi,
- reg_hdr_dat_eth_0_cipo => reg_hdr_dat_eth_0_cipo,
- reg_bsn_monitor_v2_tx_eth_0_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
- reg_bsn_monitor_v2_tx_eth_0_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
- reg_strobe_total_count_tx_eth_0_copi => reg_strobe_total_count_tx_eth_0_copi,
- reg_strobe_total_count_tx_eth_0_cipo => reg_strobe_total_count_tx_eth_0_cipo,
-
- reg_bsn_monitor_v2_rx_eth_0_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
- reg_bsn_monitor_v2_rx_eth_0_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
- reg_strobe_total_count_rx_eth_0_copi => reg_strobe_total_count_rx_eth_0_copi,
- reg_strobe_total_count_rx_eth_0_cipo => reg_strobe_total_count_rx_eth_0_cipo,
-
- -- eth1g ch1
- eth_1_mm_rst => eth_1_mm_rst,
- eth_1_tse_mosi => eth_1_tse_mosi,
- eth_1_tse_miso => eth_1_tse_miso,
- eth_1_reg_mosi => OPEN,
- eth_1_reg_miso => c_mem_cipo_rst,
- eth_1_reg_interrupt => '0',
- eth_1_ram_mosi => OPEN,
- eth_1_ram_miso => c_mem_cipo_rst,
-
- reg_diag_bg_eth_1_copi => reg_diag_bg_eth_1_copi,
- reg_diag_bg_eth_1_cipo => reg_diag_bg_eth_1_cipo,
- reg_hdr_dat_eth_1_copi => reg_hdr_dat_eth_1_copi,
- reg_hdr_dat_eth_1_cipo => reg_hdr_dat_eth_1_cipo,
- reg_bsn_monitor_v2_tx_eth_1_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
- reg_bsn_monitor_v2_tx_eth_1_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
- reg_strobe_total_count_tx_eth_1_copi => reg_strobe_total_count_tx_eth_1_copi,
- reg_strobe_total_count_tx_eth_1_cipo => reg_strobe_total_count_tx_eth_1_cipo,
-
- reg_bsn_monitor_v2_rx_eth_1_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
- reg_bsn_monitor_v2_rx_eth_1_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
- reg_strobe_total_count_rx_eth_1_copi => reg_strobe_total_count_rx_eth_1_copi,
- reg_strobe_total_count_rx_eth_1_cipo => reg_strobe_total_count_rx_eth_1_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso,
-
- -- block gen
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- bsn
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_qsfp => c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => c_unb2c_board_tr_ring.nof_bus * c_unb2c_board_tr_ring.bus_w,
+ g_nof_streams_back0 => c_unb2c_board_tr_back.bus_w
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth_0_mm_rst => eth_0_mm_rst,
+ eth_0_tse_mosi => eth_0_tse_mosi,
+ eth_0_tse_miso => eth_0_tse_miso,
+ eth_0_reg_mosi => eth_0_reg_mosi,
+ eth_0_reg_miso => eth_0_reg_miso,
+ eth_0_reg_interrupt => eth_0_reg_interrupt,
+ eth_0_ram_mosi => eth_0_ram_mosi,
+ eth_0_ram_miso => eth_0_ram_miso,
+
+ reg_diag_bg_eth_0_copi => reg_diag_bg_eth_0_copi,
+ reg_diag_bg_eth_0_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_eth_0_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_eth_0_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_eth_0_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_eth_0_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_eth_0_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_eth_0_cipo => reg_strobe_total_count_tx_eth_0_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_0_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_eth_0_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_eth_0_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_eth_0_cipo => reg_strobe_total_count_rx_eth_0_cipo,
+
+ -- eth1g ch1
+ eth_1_mm_rst => eth_1_mm_rst,
+ eth_1_tse_mosi => eth_1_tse_mosi,
+ eth_1_tse_miso => eth_1_tse_miso,
+ eth_1_reg_mosi => OPEN,
+ eth_1_reg_miso => c_mem_cipo_rst,
+ eth_1_reg_interrupt => '0',
+ eth_1_ram_mosi => OPEN,
+ eth_1_ram_miso => c_mem_cipo_rst,
+
+ reg_diag_bg_eth_1_copi => reg_diag_bg_eth_1_copi,
+ reg_diag_bg_eth_1_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_eth_1_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_eth_1_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_eth_1_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_eth_1_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_eth_1_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_eth_1_cipo => reg_strobe_total_count_tx_eth_1_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_1_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_eth_1_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_eth_1_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_eth_1_cipo => reg_strobe_total_count_rx_eth_1_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso,
+
+ -- block gen
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- bsn
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
+
+ -- databuffer
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
gen_eth_0_udp : if c_use_eth_0_UDP = true generate
@@ -807,51 +807,51 @@ begin
-- Generate UDP Tx and monitor UDP Rx
u_eth_tester_I : entity eth_lib.eth_tester
- generic map (
- g_nof_streams => c_nof_udp_streams_eth_0,
- g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
- g_remove_crc => true -- use TRUE when using TSE link interface
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
- st_pps => dp_pps,
-
- -- UDP transmit interface
- eth_src_mac => gn_eth_src_mac_I,
- ip_src_addr => gn_ip_src_addr_I,
- udp_src_port => gn_udp_src_port_I,
-
- tx_fifo_rd_emp_arr => OPEN,
-
- tx_udp_sosi_arr => eth_0_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth_0_udp_tx_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => eth_0_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- -- . Tx
- reg_bg_ctrl_copi => reg_diag_bg_eth_0_copi,
- reg_bg_ctrl_cipo => reg_diag_bg_eth_0_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_eth_0_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_eth_0_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_0_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_0_cipo,
- -- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_0_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_0_cipo
- );
+ generic map (
+ g_nof_streams => c_nof_udp_streams_eth_0,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
+ g_remove_crc => true -- use TRUE when using TSE link interface
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_pps => dp_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => gn_eth_src_mac_I,
+ ip_src_addr => gn_ip_src_addr_I,
+ udp_src_port => gn_udp_src_port_I,
+
+ tx_fifo_rd_emp_arr => OPEN,
+
+ tx_udp_sosi_arr => eth_0_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_0_udp_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => eth_0_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_diag_bg_eth_0_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_0_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_0_cipo
+ );
- -- Uses eth.vhd with ETH/TSE interface with UDP streams in ctrl_unb2c_board
- -- to stream UDP data via eth_0 = 1GbE-I.
+ -- Uses eth.vhd with ETH/TSE interface with UDP streams in ctrl_unb2c_board
+ -- to stream UDP data via eth_0 = 1GbE-I.
end generate;
@@ -865,223 +865,223 @@ begin
-- Generate UDP Tx and monitor UDP Rx
u_eth_tester_II : entity eth_lib.eth_tester
- generic map (
- g_nof_streams => c_nof_udp_streams_eth_1,
- g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
- g_remove_crc => true -- use TRUE when using TSE link interface
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
- st_pps => dp_pps,
-
- -- UDP transmit interface
- eth_src_mac => gn_eth_src_mac_II,
- ip_src_addr => gn_ip_src_addr_II,
- udp_src_port => gn_udp_src_port_II,
-
- tx_fifo_rd_emp_arr => OPEN,
-
- tx_udp_sosi_arr => eth_1_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth_1_udp_tx_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => eth_1_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- -- . Tx
- reg_bg_ctrl_copi => reg_diag_bg_eth_1_copi,
- reg_bg_ctrl_cipo => reg_diag_bg_eth_1_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_eth_1_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_eth_1_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_1_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_1_cipo,
- -- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_1_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_1_cipo
- );
+ generic map (
+ g_nof_streams => c_nof_udp_streams_eth_1,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
+ g_remove_crc => true -- use TRUE when using TSE link interface
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_pps => dp_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => gn_eth_src_mac_II,
+ ip_src_addr => gn_ip_src_addr_II,
+ udp_src_port => gn_udp_src_port_II,
+
+ tx_fifo_rd_emp_arr => OPEN,
+
+ tx_udp_sosi_arr => eth_1_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_1_udp_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => eth_1_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_diag_bg_eth_1_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_1_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_1_cipo
+ );
-- Use eth_stream with ETH/TSE interface for UDP port g_rx_udp_port to
-- stream UDP data via eth_1 = 1GbE-II
u_eth_stream : entity eth_lib.eth_stream
- generic map (
- g_technology => g_technology,
- g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
- g_jumbo_en => true,
- g_sim => g_sim,
- g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst, -- eth_1_mm_rst
- mm_clk => mm_clk,
- eth_clk => ETH_CLK(1),
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- TSE setup
- src_mac => gn_eth_src_mac_II,
- setup_done => OPEN,
-
- -- UDP transmit interface
- udp_tx_snk_in => eth_1_udp_tx_sosi_arr(0),
- udp_tx_snk_out => eth_1_udp_tx_siso_arr(0),
-
- -- UDP receive interface
- udp_rx_src_in => c_dp_siso_rdy,
- udp_rx_src_out => eth_1_udp_rx_sosi_arr(0),
-
- -- Memory Mapped Slaves
- tse_ctlr_copi => eth_1_tse_mosi,
- tse_ctlr_cipo => eth_1_tse_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(1),
- eth_rxp => ETH_SGIN(1),
-
- -- LED interface
- tse_led => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
+ g_jumbo_en => true,
+ g_sim => g_sim,
+ g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst, -- eth_1_mm_rst
+ mm_clk => mm_clk,
+ eth_clk => ETH_CLK(1),
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- TSE setup
+ src_mac => gn_eth_src_mac_II,
+ setup_done => OPEN,
+
+ -- UDP transmit interface
+ udp_tx_snk_in => eth_1_udp_tx_sosi_arr(0),
+ udp_tx_snk_out => eth_1_udp_tx_siso_arr(0),
+
+ -- UDP receive interface
+ udp_rx_src_in => c_dp_siso_rdy,
+ udp_rx_src_out => eth_1_udp_rx_sosi_arr(0),
+
+ -- Memory Mapped Slaves
+ tse_ctlr_copi => eth_1_tse_mosi,
+ tse_ctlr_cipo => eth_1_tse_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(1),
+ eth_rxp => ETH_SGIN(1),
+
+ -- LED interface
+ tse_led => open
+ );
end generate;
gen_udp_stream_10GbE : if c_use_10GbE = true and c_use_loopback = false generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
end generate;
gen_jesd204b : if c_use_jesd204b = true generate
u_jesd204b: entity work.node_adc_input_and_timing_nowg
- generic map(
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_jesd204b,
- g_jesd_freq => "200MHz",
- g_nof_sync_n => c_unb2c_board_nof_sync_jesd204b,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => BCK_RX(c_nof_streams_jesd204b - 1 downto 0),
- jesd204b_refclk => BCK_REF_CLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC
- );
+ generic map(
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_jesd_freq => "200MHz",
+ g_nof_sync_n => c_unb2c_board_nof_sync_jesd204b,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => BCK_RX(c_nof_streams_jesd204b - 1 downto 0),
+ jesd204b_refclk => BCK_REF_CLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC
+ );
end generate;
gen_front_10GbE : if c_use_10GbE = true generate
u_tr_10GbE_qsfp_and_ring: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_use_loopback => c_use_loopback,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_use_loopback => c_use_loopback,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -1102,24 +1102,24 @@ begin
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
gen_ring_wires: for i in 0 to c_nof_streams_ring - 1 generate
- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i + c_nof_streams_qsfp);
+ serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i + c_nof_streams_qsfp);
i_serial_10G_rx_qsfp_ring_arr(i + c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
end generate;
@@ -1129,46 +1129,46 @@ begin
RING_1_TX <= i_RING_TX(1);
u_ring_io : entity unb2c_board_lib.unb2c_board_ring_io
- generic map (
- g_nof_ring_bus => 2 -- c_nof_ring_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_ring_arr,
- serial_rx_arr => serial_10G_rx_ring_arr,
- RING_RX => i_RING_RX,
- RING_TX => i_RING_TX
- );
-
-
- gen_10gbe_back0 : if c_use_10GbE_back0 = true generate
- u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- BACK lines (upper)
generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_use_loopback => c_use_loopback,
- g_nof_macs => c_nof_streams_back0,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
+ g_nof_ring_bus => 2 -- c_nof_ring_bus
)
port map (
- tr_ref_clk => SB_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
- reg_mac_miso => reg_tr_10GbE_back0_miso,
- reg_eth10g_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_miso => reg_eth10g_back0_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- serial_tx_arr => i_serial_10G_tx_back0_arr,
- serial_rx_arr => i_serial_10G_rx_back0_arr
+ serial_tx_arr => serial_10G_tx_ring_arr,
+ serial_rx_arr => serial_10G_rx_ring_arr,
+ RING_RX => i_RING_RX,
+ RING_TX => i_RING_TX
);
+
+
+ gen_10gbe_back0 : if c_use_10GbE_back0 = true generate
+ u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- BACK lines (upper)
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_use_loopback => c_use_loopback,
+ g_nof_macs => c_nof_streams_back0,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SB_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ reg_mac_miso => reg_tr_10GbE_back0_miso,
+ reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_miso => reg_eth10g_back0_miso,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ serial_tx_arr => i_serial_10G_tx_back0_arr,
+ serial_rx_arr => i_serial_10G_rx_back0_arr
+ );
end generate;
@@ -1179,93 +1179,93 @@ begin
end generate;
u_back_io : entity unb2c_board_lib.unb2c_board_back_io
- generic map (
- g_nof_back_bus => c_nof_back_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_back_arr,
- serial_rx_arr => serial_10G_rx_back_arr,
-
- -- Serial I/O
- -- back transceivers
- BCK_RX(0) => BCK_RX(c_nof_streams_back0 - 1 downto 0),
- BCK_TX(0) => BCK_TX(c_nof_streams_back0 - 1 downto 0)
- );
+ generic map (
+ g_nof_back_bus => c_nof_back_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_back_arr,
+ serial_rx_arr => serial_10G_rx_back_arr,
+
+ -- Serial I/O
+ -- back transceivers
+ BCK_RX(0) => BCK_RX(c_nof_streams_back0 - 1 downto 0),
+ BCK_TX(0) => BCK_TX(c_nof_streams_back0 - 1 downto 0)
+ );
end generate;
--- gen_jesd204b_wiring : IF c_use_jesd204b = TRUE GENERATE
--- gen_jesd204b_wires: FOR i IN 0 TO c_nof_streams_jesd204b-1 GENERATE
--- serial_rx_jesd204b_arr(i) <= serial_rx_jesd204b_back_arr(i);
--- END GENERATE;
---
--- u_back_io : ENTITY unb2c_board_lib.unb2c_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => 1
--- )
--- PORT MAP (
--- --serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_rx_jesd204b_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_jesd204b-1 downto 0),
--- BCK_TX(0) => open
--- );
--- END GENERATE;
+ -- gen_jesd204b_wiring : IF c_use_jesd204b = TRUE GENERATE
+ -- gen_jesd204b_wires: FOR i IN 0 TO c_nof_streams_jesd204b-1 GENERATE
+ -- serial_rx_jesd204b_arr(i) <= serial_rx_jesd204b_back_arr(i);
+ -- END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2c_board_lib.unb2c_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => 1
+ -- )
+ -- PORT MAP (
+ -- --serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_rx_jesd204b_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_jesd204b-1 downto 0),
+ -- BCK_TX(0) => open
+ -- );
+ -- END GENERATE;
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2c_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2c_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
@@ -1278,183 +1278,183 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_ddr_MB_I,
+ -- IO_DDR
+ g_io_tech_ddr => c_ddr_MB_I,
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_ddr_MB_II,
+ -- IO_DDR
+ g_io_tech_ddr => c_ddr_MB_II,
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
gen_heater : if c_use_heater = true generate
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
- --g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- g_nof_mac4 => 750,
+ --g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_nof_mac4 => 750,
- g_pipeline => 72, -- max 72
- g_nof_ram => 4, -- max 4
+ g_pipeline => 72, -- max 72
+ g_nof_ram => 4, -- max 4
- g_nof_logic => 24 -- max 24
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ g_nof_logic => 24 -- max 24
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end generate;
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index 4ed6dd8e64..153caffb96 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -22,11 +22,11 @@
-- Purpose: Define selections for revisions of the unb2c_test design
library IEEE, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
package unb2c_test_pkg is
@@ -34,27 +34,27 @@ package unb2c_test_pkg is
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
@@ -89,14 +89,14 @@ package unb2c_test_pkg is
constant c_test_jesd204b : t_unb2c_test_config := (false,false,false,false,false,false, true,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
-- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_unb2c_test_config;
+ function func_sel_revision_rec (g_design_name : string) return t_unb2c_test_config;
end unb2c_test_pkg;
package body unb2c_test_pkg is
- function func_sel_revision_rec(g_design_name : string) return t_unb2c_test_config is
+ function func_sel_revision_rec (g_design_name : string) return t_unb2c_test_config is
begin
if g_design_name = "unb2c_test_10GbE" then return c_test_10GbE;
elsif g_design_name = "unb2c_test_ddr" then return c_test_ddr;
diff --git a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
index 23c9cf1f61..45036cec04 100644
--- a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
@@ -42,14 +42,14 @@
--
library IEEE, common_lib, unb2c_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2c_test is
generic (
@@ -164,98 +164,98 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2c_test : entity work.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- -- Serial I/O
--- QSFP_0_TX => si_lpbk_0,
--- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
index 8ae42abc8f..e152b61148 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
@@ -41,93 +41,93 @@
-- --------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
entity bscan2 is
- -- enter the number of BSCAN2 blocks to create. This is the only place that
- -- needs to be modified to control the number of local scan ports created.
- generic ( bscan_ports : positive := 2 );
- port( TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- Turn on slow slew in fitter for output signals
- TDO : out std_logic;
- -- OE control for MSP ports (Active high)
- ENABLE_MSP : in std_logic;
- MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(3 downto 0)
- );
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ generic ( bscan_ports : positive := 2 );
+ port( TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- Turn on slow slew in fitter for output signals
+ TDO : out std_logic;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : in std_logic;
+ MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(3 downto 0)
+ );
end;
architecture behave of bscan2 is
- component top_linker is
- -- do not use the generic map to prevent the synthesis tool from
- -- appending the number of ports to the components name.
- port(TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- enable logic for TDO pins.
- TDO_enable : out std_logic;
- TDO : out std_logic;
- MSPCLK : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTDI : in std_logic_vector(4 * bscan_ports downto 1);
- MSPTDO : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTMS : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTRST : out std_logic_vector(4 * bscan_ports downto 1);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(4 downto 1)
- );
-end component top_linker;
--- synthesis FILE="top_linker.ngo"
+ component top_linker is
+ -- do not use the generic map to prevent the synthesis tool from
+ -- appending the number of ports to the components name.
+ port(TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- enable logic for TDO pins.
+ TDO_enable : out std_logic;
+ TDO : out std_logic;
+ MSPCLK : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTDI : in std_logic_vector(4 * bscan_ports downto 1);
+ MSPTDO : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTMS : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTRST : out std_logic_vector(4 * bscan_ports downto 1);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(4 downto 1)
+ );
+ end component top_linker;
+ -- synthesis FILE="top_linker.ngo"
--- logic to enable TDO pins
-signal ENABLE_TDO : std_logic;
--- signal from tap controler that enables all TDOs.
-signal tdoENABLE : std_logic;
--- logic to generate tdo_sp and tdo_hdr
-signal LSPTMS : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTCK : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTDO : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTRST : std_logic_vector(4 * bscan_ports - 1 downto 0);
--- output of Port Mux
-signal TDO_int : std_logic;
+ -- logic to enable TDO pins
+ signal ENABLE_TDO : std_logic;
+ -- signal from tap controler that enables all TDOs.
+ signal tdoENABLE : std_logic;
+ -- logic to generate tdo_sp and tdo_hdr
+ signal LSPTMS : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTCK : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTDO : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTRST : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- output of Port Mux
+ signal TDO_int : std_logic;
begin
- -- Wire up all of the tri-state controlled lines automatically
- tri_state_lines : for lvar1 in 0 to (4 * bscan_ports - 1) generate
- MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
- MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
- MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
- -- enable MSPTDOs for 1149.1
- MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
- end generate tri_state_lines;
+ -- Wire up all of the tri-state controlled lines automatically
+ tri_state_lines : for lvar1 in 0 to (4 * bscan_ports - 1) generate
+ MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
+ -- enable MSPTDOs for 1149.1
+ MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
+ end generate tri_state_lines;
- -- MSP Port enable controls
- -- enable logic for all TDO pins
- ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
+ -- MSP Port enable controls
+ -- enable logic for all TDO pins
+ ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
- TDO <= TDO_int when tdoENABLE = '1' else 'Z';
+ TDO <= TDO_int when tdoENABLE = '1' else 'Z';
- TopLinkerModule : component top_linker
- port map(
- TDO => TDO_int,
- TMS => TMS,
- TCK => TCK,
- TRST => TRST,
- TDI => TDI,
- TDO_enable => tdoENABLE,
- MSPTDI => MSPTDI,
- MSPTDO => LSPTDO,
- MSPTMS => LSPTMS,
- MSPCLK => LSPTCK,
- MSPTRST => LSPTRST,
- IDN => IDN
- );
+ TopLinkerModule : component top_linker
+ port map(
+ TDO => TDO_int,
+ TMS => TMS,
+ TCK => TCK,
+ TRST => TRST,
+ TDI => TDI,
+ TDO_enable => tdoENABLE,
+ MSPTDI => MSPTDI,
+ MSPTDO => LSPTDO,
+ MSPTMS => LSPTMS,
+ MSPCLK => LSPTCK,
+ MSPTRST => LSPTRST,
+ IDN => IDN
+ );
end behave;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
index c29a1724c7..7b8eddd105 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
@@ -21,133 +21,133 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
architecture str of jtag_top is
- component bscan2 is
+ component bscan2 is
-- enter the number of BSCAN2 blocks to create. This is the only place that
-- needs to be modified to control the number of local scan ports created.
- generic (
- bscan_ports : positive := 2
-
- );
- port (
- TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- Turn on slow slew in fitter for output signals
- TDO : out std_logic;
- -- OE control for MSP ports (Active high)
- ENABLE_MSP : in std_logic;
- MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(3 downto 0)
- );
- end component bscan2;
-
--- internal enable signal for tri-stating the scanbridge
- constant jtag_chains : natural := 5;
- signal ENABLE_SB : std_logic;
- signal TDO_BSCAN : std_logic;
- signal TDA : std_logic;
- signal TDB : std_logic;
- signal TDC : std_logic;
- signal TDD : std_logic;
- signal MSPTDO_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTCK_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTMS_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTRST_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
-
- begin
- bscan : component bscan2
- port map (
- TDI => TDI,
- TCK => TCK,
- TMS => TMS,
- TRST => TRST,
- TDO => TDO_BSCAN,
- ENABLE_MSP => ENABLE_SB,
- MSPTCK(jtag_chains - 1 downto 0) => MSPTCK_BSCAN,
- MSPTDI(jtag_chains - 1 downto 0) => MSPTDI,
- MSPTDO(jtag_chains - 1 downto 0) => MSPTDO_BSCAN,
- MSPTMS(jtag_chains - 1 downto 0) => MSPTMS_BSCAN,
- MSPTRST(jtag_chains - 1 downto 0) => MSPTRST_BSCAN,
- IDN => "0000"
- );
-
-
- p_jtagselect: process(TDI,MSPTDI(jtag_chains - 1 downto 0),TCK,TMS,TRST)
- begin
- ENABLE_SB <= '0';
- MSPTDO(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTCK(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTMS(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTRST(jtag_chains - 1 downto 0) <= "ZZZZZ";
-
- if CTRL(1) = '1' then
- ENABLE_SB <= '1';
- MSPTDO <= MSPTDO_BSCAN;
- TDO <= TDO_BSCAN;
- MSPTCK <= MSPTCK_BSCAN;
- MSPTMS <= MSPTMS_BSCAN;
- MSPTRST <= MSPTRST_BSCAN;
- else
- if LPSEL(0) = '0' then
- MSPTDO(0) <= TDI;
- TDA <= MSPTDI(0);
- MSPTCK(0) <= TCK;
- MSPTMS(0) <= TMS;
- MSPTRST(0) <= TRST;
- else
- TDA <= TDI;
- end if;
-
- if LPSEL(1) = '0' then
- MSPTDO(1) <= TDA;
- TDB <= MSPTDI(1);
- MSPTCK(1) <= TCK;
- MSPTMS(1) <= TMS;
- MSPTRST(1) <= TRST;
- else
- TDB <= TDA;
- end if;
-
- if LPSEL(2) = '0' then
- MSPTDO(2) <= TDB;
- TDC <= MSPTDI(2);
- MSPTCK(2) <= TCK;
- MSPTMS(2) <= TMS;
- MSPTRST(2) <= TRST;
- else
- TDC <= TDB;
- end if;
-
- if LPSEL(3) = '0' then
- MSPTDO(3) <= TDC;
- TDD <= MSPTDI(3);
- MSPTCK(3) <= TCK;
- MSPTMS(3) <= TMS;
- MSPTRST(3) <= TRST;
- else
- TDD <= TDC;
- end if;
-
- if LPSEL(4) = '0' then
- MSPTDO(4) <= TDD;
- TDO <= MSPTDI(4);
- MSPTCK(4) <= TCK;
- MSPTMS(4) <= TMS;
- MSPTRST(4) <= TRST;
- else
- TDO <= TDD;
- end if;
- end if;
+ generic (
+ bscan_ports : positive := 2
+
+ );
+ port (
+ TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- Turn on slow slew in fitter for output signals
+ TDO : out std_logic;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : in std_logic;
+ MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(3 downto 0)
+ );
+ end component bscan2;
+
+ -- internal enable signal for tri-stating the scanbridge
+ constant jtag_chains : natural := 5;
+ signal ENABLE_SB : std_logic;
+ signal TDO_BSCAN : std_logic;
+ signal TDA : std_logic;
+ signal TDB : std_logic;
+ signal TDC : std_logic;
+ signal TDD : std_logic;
+ signal MSPTDO_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTCK_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTMS_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTRST_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+
+begin
+ bscan : component bscan2
+ port map (
+ TDI => TDI,
+ TCK => TCK,
+ TMS => TMS,
+ TRST => TRST,
+ TDO => TDO_BSCAN,
+ ENABLE_MSP => ENABLE_SB,
+ MSPTCK(jtag_chains - 1 downto 0) => MSPTCK_BSCAN,
+ MSPTDI(jtag_chains - 1 downto 0) => MSPTDI,
+ MSPTDO(jtag_chains - 1 downto 0) => MSPTDO_BSCAN,
+ MSPTMS(jtag_chains - 1 downto 0) => MSPTMS_BSCAN,
+ MSPTRST(jtag_chains - 1 downto 0) => MSPTRST_BSCAN,
+ IDN => "0000"
+ );
+
+
+ p_jtagselect: process(TDI,MSPTDI(jtag_chains - 1 downto 0),TCK,TMS,TRST)
+ begin
+ ENABLE_SB <= '0';
+ MSPTDO(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTCK(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTMS(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTRST(jtag_chains - 1 downto 0) <= "ZZZZZ";
+
+ if CTRL(1) = '1' then
+ ENABLE_SB <= '1';
+ MSPTDO <= MSPTDO_BSCAN;
+ TDO <= TDO_BSCAN;
+ MSPTCK <= MSPTCK_BSCAN;
+ MSPTMS <= MSPTMS_BSCAN;
+ MSPTRST <= MSPTRST_BSCAN;
+ else
+ if LPSEL(0) = '0' then
+ MSPTDO(0) <= TDI;
+ TDA <= MSPTDI(0);
+ MSPTCK(0) <= TCK;
+ MSPTMS(0) <= TMS;
+ MSPTRST(0) <= TRST;
+ else
+ TDA <= TDI;
+ end if;
+
+ if LPSEL(1) = '0' then
+ MSPTDO(1) <= TDA;
+ TDB <= MSPTDI(1);
+ MSPTCK(1) <= TCK;
+ MSPTMS(1) <= TMS;
+ MSPTRST(1) <= TRST;
+ else
+ TDB <= TDA;
+ end if;
+
+ if LPSEL(2) = '0' then
+ MSPTDO(2) <= TDB;
+ TDC <= MSPTDI(2);
+ MSPTCK(2) <= TCK;
+ MSPTMS(2) <= TMS;
+ MSPTRST(2) <= TRST;
+ else
+ TDC <= TDB;
+ end if;
+
+ if LPSEL(3) = '0' then
+ MSPTDO(3) <= TDC;
+ TDD <= MSPTDI(3);
+ MSPTCK(3) <= TCK;
+ MSPTMS(3) <= TMS;
+ MSPTRST(3) <= TRST;
+ else
+ TDD <= TDC;
+ end if;
+
+ if LPSEL(4) = '0' then
+ MSPTDO(4) <= TDD;
+ TDO <= MSPTDI(4);
+ MSPTCK(4) <= TCK;
+ MSPTMS(4) <= TMS;
+ MSPTRST(4) <= TRST;
+ else
+ TDO <= TDD;
+ end if;
+ end if;
end process;
end str;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
index 1968d26ac9..7aa11d383d 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
@@ -6,23 +6,23 @@
---------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity jtag_top is
- port (
- CTRL : in std_logic_vector(1 downto 0);
- ENABLE_MSP : in std_logic;
- IDN : in std_logic_vector(3 downto 0);
- LPSEL : in std_logic_vector(4 downto 0);
- MSPTCK : out std_logic_vector(4 downto 0);
- MSPTDI : in std_logic_vector(4 downto 0);
- MSPTDO : out std_logic_vector(4 downto 0);
- MSPTMS : out std_logic_vector(4 downto 0);
- MSPTRST : out std_logic_vector(4 downto 0);
- TCK : in std_logic;
- TDI : in std_logic;
- TDO : out std_logic;
- TMS : in std_logic;
- TRST : in std_logic
- );
+ port (
+ CTRL : in std_logic_vector(1 downto 0);
+ ENABLE_MSP : in std_logic;
+ IDN : in std_logic_vector(3 downto 0);
+ LPSEL : in std_logic_vector(4 downto 0);
+ MSPTCK : out std_logic_vector(4 downto 0);
+ MSPTDI : in std_logic_vector(4 downto 0);
+ MSPTDO : out std_logic_vector(4 downto 0);
+ MSPTMS : out std_logic_vector(4 downto 0);
+ MSPTRST : out std_logic_vector(4 downto 0);
+ TCK : in std_logic;
+ TDI : in std_logic;
+ TDO : out std_logic;
+ TMS : in std_logic;
+ TRST : in std_logic
+ );
end jtag_top;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 96ea994b4e..d98d6cd119 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2c_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2c_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2c_board is
generic (
@@ -322,15 +322,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -339,15 +339,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
@@ -356,26 +356,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -389,29 +389,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2c_board_clk200_pll : entity work.unb2c_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -426,48 +426,48 @@ begin
clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2c_board_clk125_pll : entity work.unb2c_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2c_board_node_ctrl : entity work.unb2c_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2c_board_node_ctrl : entity work.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -475,33 +475,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2c_board_system_info : entity work.mms_unb2c_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
@@ -539,12 +539,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
@@ -556,15 +556,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2c_board_wdi_reg : entity work.unb2c_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
@@ -574,99 +574,99 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
u_mms_unb2c_fpga_sens : entity work.mms_unb2c_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- mm_start => '1',
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ mm_start => '1',
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
@@ -676,18 +676,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
@@ -714,61 +714,61 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT,
+ eth_rxp => ETH_SGIN,
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
+ end generate;
+
+ u_ram_scrap : entity common_lib.common_ram_r_w
generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true,
- g_sim => g_sim,
- g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ g_ram => c_ram_scrap
)
port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT,
- eth_rxp => ETH_SGIN,
-
- -- LED interface
- tse_led => eth1g_led
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ wr_en => ram_scrap_mosi.wr,
+ wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_en => ram_scrap_mosi.rd,
+ rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_val => ram_scrap_miso.rdval
);
- end generate;
-
- u_ram_scrap : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_scrap
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- wr_en => ram_scrap_mosi.wr,
- wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
- rd_en => ram_scrap_mosi.rd,
- rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
- rd_val => ram_scrap_miso.rdval
- );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
index aed541eb2b..f0756a1b5a 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2c_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2c_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2c_board_system_info;
@@ -70,72 +70,74 @@ architecture str of mms_unb2c_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/"; -- TODO: change path
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0'
+ );
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2c_board_system_info: entity work.unb2c_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2c_board_system_info_reg: entity work.unb2c_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
index 856ca0601b..4bc9fb9f93 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2c_fpga_sens.vhd
library IEEE, technology_lib, common_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2c_fpga_sens is
@@ -59,24 +59,24 @@ architecture str of mms_unb2c_fpga_sens is
begin
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim,
- g_temp_high => g_temp_high
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => mm_start,
- temp_alarm => temp_alarm,
+ start_sense => mm_start,
+ temp_alarm => temp_alarm,
- reg_temp_mosi => reg_temp_mosi,
- reg_temp_miso => reg_temp_miso,
+ reg_temp_mosi => reg_temp_mosi,
+ reg_temp_miso => reg_temp_miso,
- reg_voltage_store_mosi => reg_voltage_mosi,
- reg_voltage_store_miso => reg_voltage_miso
- );
+ reg_voltage_store_mosi => reg_voltage_mosi,
+ reg_voltage_store_miso => reg_voltage_miso
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
index 8a297498d4..8f64d3c2ac 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_back_io is
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
index b49538091f..1d75f5de92 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
-- Description:
@@ -64,47 +64,47 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
index 5f8d74ee97..4624b25922 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -140,83 +140,83 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
index bbf90bac97..7086343dde 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -54,16 +54,16 @@ architecture arria10 of unb2c_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
index 15196c296f..812bf277cd 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -59,28 +59,28 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
index 38feccfe05..0020d15e1d 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_front_io is
@@ -67,8 +67,8 @@ begin
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2c_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
index a2c00f0705..dbad2664f0 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
-- Description:
@@ -71,44 +71,44 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2c_board_wdi_extend : entity work.unb2c_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
index 3393b547e5..abc124a830 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2c_board_peripherals_pkg is
@@ -76,10 +76,10 @@ package unb2c_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
index e5f7366450..29b59ecf5c 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2c_board_pkg is
@@ -127,23 +127,25 @@ package unb2c_board_pkg is
type t_c_unb2c_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2c_board_system_info(VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info;
+ function func_unb2c_board_system_info (
+ VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info;
end unb2c_board_pkg;
package body unb2c_board_pkg is
- function func_unb2c_board_system_info(VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info is
+ function func_unb2c_board_system_info (
+ VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info is
variable v_system_info : t_c_unb2c_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
index d5946ebcab..c31683ec0b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
-- Description:
@@ -111,43 +111,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -166,20 +166,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
index c0098cce09..bd4d8934cf 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_ring_io is
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
index dbd91d248c..f26babbdd9 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 9f6723e73f..80527627ca 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2c_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2c_board_system_info_reg;
@@ -88,11 +88,13 @@ architecture rtl of unb2c_board_system_info_reg is
constant c_revision_id_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
constant c_design_note_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0'
+ );
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
index 53b672732f..ffa24fcdb7 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -72,27 +72,27 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
index 4a492464e0..95efd78bd1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2c_board_wdi_reg is
port (
@@ -40,18 +40,20 @@ entity unb2c_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2c_board_wdi_reg;
architecture rtl of unb2c_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0'
+ );
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
@@ -64,7 +66,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
index d081a13807..d327491ad3 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk125_pll is
@@ -57,15 +57,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
index 3f1864bac7..da3cca1c55 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk200_pll is
@@ -72,45 +72,45 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
index 0e6f2a8438..77b5f3efce 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk25_pll is
@@ -57,15 +57,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
index d4965685a2..04a352423a 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_node_ctrl is
@@ -76,24 +76,24 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
index ef1060ab69..7e36cef201 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
@@ -37,10 +37,10 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2c_board_qsfp_leds is
end tb_unb2c_board_qsfp_leds;
@@ -142,49 +142,49 @@ begin
end process;
u_unb2c_factory_qsfp_leds : entity work.unb2c_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2c_user_qsfp_leds : entity work.unb2c_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
index 9ad00ea249..6028dcccae 100644
--- a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_board_10gbe is
@@ -82,17 +82,17 @@ architecture str of unb2c_board_10gbe is
begin
u_unb2c_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
index 39e964b31d..0410a1076e 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
@@ -35,10 +35,10 @@
-- registers.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.axi4_lite_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.axi4_lite_pkg.all;
entity axi4_lite_mm_bridge is
generic (
@@ -112,7 +112,7 @@ begin
d_bvalid <= '0';
end if;
if i_rst = '1' then
- d_bvalid <= '0';
+ d_bvalid <= '0';
end if;
end process;
end str;
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
index 7010309e6f..d0db8c590f 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
@@ -28,12 +28,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
package axi4_lite_pkg is
@@ -94,18 +94,18 @@ package axi4_lite_pkg is
constant c_axi4_lite_resp_decerr : std_logic_vector(c_axi4_lite_resp_w - 1 downto 0) := "11"; -- decode error
-- Functions to convert axi4-lite to MM.
- function func_axi4_lite_to_mm_copi(axi4_copi : t_axi4_lite_copi) return t_mem_copi;
- function func_axi4_lite_to_mm_cipo(axi4_cipo : t_axi4_lite_cipo) return t_mem_cipo;
+ function func_axi4_lite_to_mm_copi (axi4_copi : t_axi4_lite_copi) return t_mem_copi;
+ function func_axi4_lite_to_mm_cipo (axi4_cipo : t_axi4_lite_cipo) return t_mem_cipo;
-- Functions to convert MM to axi4-lite.
- function func_axi4_lite_from_mm_copi(mm_copi : t_mem_copi) return t_axi4_lite_copi;
- function func_axi4_lite_from_mm_cipo(mm_cipo : t_mem_cipo; bvalid : std_logic) return t_axi4_lite_cipo;
+ function func_axi4_lite_from_mm_copi (mm_copi : t_mem_copi) return t_axi4_lite_copi;
+ function func_axi4_lite_from_mm_cipo (mm_cipo : t_mem_cipo; bvalid : std_logic) return t_axi4_lite_cipo;
end axi4_lite_pkg;
package body axi4_lite_pkg is
- function func_axi4_lite_to_mm_copi(axi4_copi : t_axi4_lite_copi) return t_mem_copi is
+ function func_axi4_lite_to_mm_copi (axi4_copi : t_axi4_lite_copi) return t_mem_copi is
variable v_mm_copi : t_mem_copi := c_mem_copi_rst;
begin
if axi4_copi.awvalid = '1' then
@@ -119,7 +119,7 @@ package body axi4_lite_pkg is
return v_mm_copi;
end;
- function func_axi4_lite_to_mm_cipo(axi4_cipo : t_axi4_lite_cipo) return t_mem_cipo is
+ function func_axi4_lite_to_mm_cipo (axi4_cipo : t_axi4_lite_cipo) return t_mem_cipo is
variable v_mm_cipo : t_mem_cipo := c_mem_cipo_rst;
begin
v_mm_cipo.rddata(c_axi4_lite_data_w - 1 downto 0) := axi4_cipo.rdata;
@@ -128,7 +128,7 @@ package body axi4_lite_pkg is
return v_mm_cipo;
end;
- function func_axi4_lite_from_mm_copi(mm_copi : t_mem_copi) return t_axi4_lite_copi is
+ function func_axi4_lite_from_mm_copi (mm_copi : t_mem_copi) return t_axi4_lite_copi is
variable v_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
begin
v_axi4_copi.awaddr := mm_copi.address(c_axi4_lite_address_w - 3 downto 0) & "00"; -- convert word addressed to byte addressed.
@@ -145,7 +145,7 @@ package body axi4_lite_pkg is
return v_axi4_copi;
end;
- function func_axi4_lite_from_mm_cipo(mm_cipo : t_mem_cipo; bvalid : std_logic) return t_axi4_lite_cipo is
+ function func_axi4_lite_from_mm_cipo (mm_cipo : t_mem_cipo; bvalid : std_logic) return t_axi4_lite_cipo is
variable v_axi4_cipo : t_axi4_lite_cipo := c_axi4_lite_cipo_rst;
begin
v_axi4_cipo.awready := not mm_cipo.waitrequest;
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
index f554bfe7fe..12206c6687 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
@@ -48,10 +48,10 @@
-- . AXI4 does not have a DP Xon or sync equivalent.
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.axi4_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.axi4_stream_pkg.all;
entity axi4_stream_dp_bridge is
generic (
@@ -114,20 +114,20 @@ begin
-- Adapt Ready Latency
u_dp_latency_adapter_dp_to_axi : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_dp_rl,
- g_out_latency => g_axi4_rl
- )
- port map (
- clk => in_clk,
- rst => i_rst,
-
- snk_in => dp_in_sosi,
- snk_out => dp_in_siso,
-
- src_out => axi4_from_dp_sosi,
- src_in => axi4_from_dp_siso
- );
+ generic map (
+ g_in_latency => g_dp_rl,
+ g_out_latency => g_axi4_rl
+ )
+ port map (
+ clk => in_clk,
+ rst => i_rst,
+
+ snk_in => dp_in_sosi,
+ snk_out => dp_in_siso,
+
+ src_out => axi4_from_dp_sosi,
+ src_in => axi4_from_dp_siso
+ );
----------------------------
@@ -179,20 +179,20 @@ begin
-- Adapt Ready Latency
u_dp_latency_adapter_axi_to_dp : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_axi4_rl,
- g_out_latency => g_dp_rl
- )
- port map (
- clk => in_clk,
- rst => i_rst,
-
- snk_in => dp_from_axi4_sosi,
- snk_out => dp_from_axi4_siso,
-
- src_out => dp_out_sosi,
- src_in => dp_out_siso
- );
+ generic map (
+ g_in_latency => g_axi4_rl,
+ g_out_latency => g_dp_rl
+ )
+ port map (
+ clk => in_clk,
+ rst => i_rst,
+
+ snk_in => dp_from_axi4_sosi,
+ snk_out => dp_from_axi4_siso,
+
+ src_out => dp_out_sosi,
+ src_in => dp_out_siso
+ );
end str;
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
index b1c8b44e73..0df77d9e0e 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
@@ -47,10 +47,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package axi4_stream_pkg is
@@ -104,92 +104,96 @@ package axi4_stream_pkg is
type t_axi4_sosi_mat is array (integer range <>, integer range <>) of t_axi4_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
- function func_axi4_data_shift_first(head_sosi, tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_axi4_sosi;
+ function func_axi4_data_shift_first (head_sosi, tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_axi4_sosi;
-- Shift and combine part of previous data and this data, use the other sosi from prev_sosi
- function func_axi4_data_shift( prev_sosi, this_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_axi4_sosi;
+ function func_axi4_data_shift ( prev_sosi, this_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_axi4_sosi;
-- Shift part of tail data and account for input empty
- function func_axi4_data_shift_last( tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_axi4_sosi;
+ function func_axi4_data_shift_last ( tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_axi4_sosi;
-- Determine resulting empty if two streams are concatenated or split
- function func_axi4_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
- function func_axi4_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_axi4_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_axi4_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
-- Multiplex the t_axi4_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_axi4_sosi_arr_mux(axi4 : t_axi4_sosi_arr) return t_axi4_sosi;
+ function func_axi4_sosi_arr_mux (axi4 : t_axi4_sosi_arr) return t_axi4_sosi;
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_axi4_*_arr (for all elements or only for the mask[]='1' elements)
- function func_axi4_stream_arr_and(axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_axi4_stream_arr_and(axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_axi4_stream_arr_and(axi4 : t_axi4_siso_arr; str : string) return std_logic;
- function func_axi4_stream_arr_and(axi4 : t_axi4_sosi_arr; str : string) return std_logic;
- function func_axi4_stream_arr_or( axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_axi4_stream_arr_or( axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_axi4_stream_arr_or( axi4 : t_axi4_siso_arr; str : string) return std_logic;
- function func_axi4_stream_arr_or( axi4 : t_axi4_sosi_arr; str : string) return std_logic;
+ function func_axi4_stream_arr_and (axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_axi4_stream_arr_and (axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_axi4_stream_arr_and (axi4 : t_axi4_siso_arr; str : string) return std_logic;
+ function func_axi4_stream_arr_and (axi4 : t_axi4_sosi_arr; str : string) return std_logic;
+ function func_axi4_stream_arr_or ( axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_axi4_stream_arr_or ( axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_axi4_stream_arr_or ( axi4 : t_axi4_siso_arr; str : string) return std_logic;
+ function func_axi4_stream_arr_or ( axi4 : t_axi4_sosi_arr; str : string) return std_logic;
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_axi4_stream_arr_set(axi4 : t_axi4_siso_arr; slv : std_logic_vector; str : string) return t_axi4_siso_arr;
- function func_axi4_stream_arr_set(axi4 : t_axi4_sosi_arr; slv : std_logic_vector; str : string) return t_axi4_sosi_arr;
- function func_axi4_stream_arr_set(axi4 : t_axi4_siso_arr; sl : std_logic; str : string) return t_axi4_siso_arr;
- function func_axi4_stream_arr_set(axi4 : t_axi4_sosi_arr; sl : std_logic; str : string) return t_axi4_sosi_arr;
- function func_axi4_stream_arr_get(axi4 : t_axi4_siso_arr; str : string) return std_logic_vector;
- function func_axi4_stream_arr_get(axi4 : t_axi4_sosi_arr; str : string) return std_logic_vector;
+ function func_axi4_stream_arr_set (axi4 : t_axi4_siso_arr; slv : std_logic_vector; str : string) return t_axi4_siso_arr;
+ function func_axi4_stream_arr_set (axi4 : t_axi4_sosi_arr; slv : std_logic_vector; str : string) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_set (axi4 : t_axi4_siso_arr; sl : std_logic; str : string) return t_axi4_siso_arr;
+ function func_axi4_stream_arr_set (axi4 : t_axi4_sosi_arr; sl : std_logic; str : string) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_get (axi4 : t_axi4_siso_arr; str : string) return std_logic_vector;
+ function func_axi4_stream_arr_get (axi4 : t_axi4_sosi_arr; str : string) return std_logic_vector;
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_siso) return t_axi4_siso_arr;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_sosi) return t_axi4_sosi_arr;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a : t_axi4_siso_arr; b : t_axi4_siso) return t_axi4_siso_arr;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a : t_axi4_sosi_arr; b : t_axi4_sosi) return t_axi4_sosi_arr;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a : t_axi4_siso; b : t_axi4_siso_arr) return t_axi4_siso_arr;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a : t_axi4_sosi; b : t_axi4_sosi_arr) return t_axi4_sosi_arr;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_siso_arr) return t_axi4_siso_arr;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_sosi_arr) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a, b : t_axi4_siso) return t_axi4_siso_arr;
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a, b : t_axi4_sosi) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a : t_axi4_siso_arr; b : t_axi4_siso) return t_axi4_siso_arr;
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a : t_axi4_sosi_arr; b : t_axi4_sosi) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a : t_axi4_siso; b : t_axi4_siso_arr) return t_axi4_siso_arr;
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a : t_axi4_sosi; b : t_axi4_sosi_arr) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a, b : t_axi4_siso_arr) return t_axi4_siso_arr;
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a, b : t_axi4_sosi_arr) return t_axi4_sosi_arr;
-- Fix reversed buses due to connecting TO to DOWNTO range arrays.
- function func_axi4_stream_arr_reverse_range(in_arr : t_axi4_sosi_arr) return t_axi4_sosi_arr;
- function func_axi4_stream_arr_reverse_range(in_arr : t_axi4_siso_arr) return t_axi4_siso_arr;
+ function func_axi4_stream_arr_reverse_range (in_arr : t_axi4_sosi_arr) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_reverse_range (in_arr : t_axi4_siso_arr) return t_axi4_siso_arr;
-- Functions to combinatorially hold the data fields and to set or reset the control fields in an sosi array
- function func_axi4_stream_arr_set_control( axi4 : t_axi4_sosi_arr; ctrl : t_axi4_sosi) return t_axi4_sosi_arr;
- function func_axi4_stream_arr_reset_control(axi4 : t_axi4_sosi_arr ) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_set_control ( axi4 : t_axi4_sosi_arr; ctrl : t_axi4_sosi) return t_axi4_sosi_arr;
+ function func_axi4_stream_arr_reset_control (axi4 : t_axi4_sosi_arr ) return t_axi4_sosi_arr;
-- Functions to convert dp streaming to axi4 streaming
- function func_axi4_stream_from_dp_sosi(dp_sosi : t_dp_sosi) return t_axi4_sosi;
- function func_axi4_stream_from_dp_siso(dp_siso : t_dp_siso) return t_axi4_siso;
+ function func_axi4_stream_from_dp_sosi (dp_sosi : t_dp_sosi) return t_axi4_sosi;
+ function func_axi4_stream_from_dp_siso (dp_siso : t_dp_siso) return t_axi4_siso;
-- Functions to convert dp streaming to axi4 streaming
- function func_axi4_stream_to_dp_sosi(axi4_sosi : t_axi4_sosi) return t_dp_sosi;
- function func_axi4_stream_to_dp_siso(axi4_siso : t_axi4_siso) return t_dp_siso;
+ function func_axi4_stream_to_dp_sosi (axi4_sosi : t_axi4_sosi) return t_dp_sosi;
+ function func_axi4_stream_to_dp_siso (axi4_siso : t_axi4_siso) return t_dp_siso;
-- Function to derive DP empty from AXI4 tkeep by counting the 0s in TKEEP.
- function func_axi4_stream_tkeep_to_dp_empty(tkeep : std_logic_vector) return std_logic_vector;
+ function func_axi4_stream_tkeep_to_dp_empty (tkeep : std_logic_vector) return std_logic_vector;
end axi4_stream_pkg;
@@ -197,11 +201,12 @@ end axi4_stream_pkg;
package body axi4_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.tready;
-- Register siso.ready in c_ready_latency registers
@@ -215,20 +220,22 @@ package body axi4_stream_pkg is
end proc_axi4_siso_alert;
-- Default RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_axi4_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_axi4_siso_alert;
-- SOSI/SISO array version
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).tready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -246,16 +253,17 @@ package body axi4_stream_pkg is
end proc_axi4_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_axi4_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_axi4_siso_alert;
-- Keep part of head data and combine part of tail data
- function func_axi4_data_shift_first(head_sosi, tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_axi4_sosi is
+ function func_axi4_data_shift_first (head_sosi, tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_axi4_sosi is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_axi4_sosi;
begin
@@ -272,7 +280,7 @@ package body axi4_stream_pkg is
-- Shift and combine part of previous data and this data,
- function func_axi4_data_shift(prev_sosi, this_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_axi4_sosi is
+ function func_axi4_data_shift (prev_sosi, this_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_axi4_sosi is
variable vK : natural := nof_symbols_from_this;
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_axi4_sosi;
@@ -305,7 +313,7 @@ package body axi4_stream_pkg is
-- Shift part of tail data and account for input empty
- function func_axi4_data_shift_last(tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_axi4_sosi is
+ function func_axi4_data_shift_last (tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_axi4_sosi is
variable vK : natural := nof_symbols_from_tail;
variable vL : natural := input_empty;
variable vN : natural := nof_symbols_per_data;
@@ -335,7 +343,7 @@ package body axi4_stream_pkg is
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
- function func_axi4_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_axi4_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(head_empty);
@@ -347,7 +355,7 @@ package body axi4_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_axi4_empty_concat;
- function func_axi4_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_axi4_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(input_empty);
@@ -362,7 +370,7 @@ package body axi4_stream_pkg is
-- Multiplex the t_axi4_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_axi4_sosi_arr_mux(axi4 : t_axi4_sosi_arr) return t_axi4_sosi is
+ function func_axi4_sosi_arr_mux (axi4 : t_axi4_sosi_arr) return t_axi4_sosi is
variable v_sosi : t_axi4_sosi := c_axi4_sosi_rst;
begin
for I in axi4'range loop
@@ -376,7 +384,7 @@ package body axi4_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_axi4_*_arr (for all elements or only for the mask[]='1' elements)
- function func_axi4_stream_arr_and(axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_axi4_stream_arr_and (axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(axi4'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -397,7 +405,7 @@ package body axi4_stream_pkg is
end if;
end func_axi4_stream_arr_and;
- function func_axi4_stream_arr_and(axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_axi4_stream_arr_and (axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(axi4'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -418,19 +426,19 @@ package body axi4_stream_pkg is
end if;
end func_axi4_stream_arr_and;
- function func_axi4_stream_arr_and(axi4 : t_axi4_siso_arr; str : string) return std_logic is
+ function func_axi4_stream_arr_and (axi4 : t_axi4_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(axi4'range) := (others => '1');
begin
return func_axi4_stream_arr_and(axi4, c_mask, str);
end func_axi4_stream_arr_and;
- function func_axi4_stream_arr_and(axi4 : t_axi4_sosi_arr; str : string) return std_logic is
+ function func_axi4_stream_arr_and (axi4 : t_axi4_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(axi4'range) := (others => '1');
begin
return func_axi4_stream_arr_and(axi4, c_mask, str);
end func_axi4_stream_arr_and;
- function func_axi4_stream_arr_or(axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_axi4_stream_arr_or (axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(axi4'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -451,7 +459,7 @@ package body axi4_stream_pkg is
end if;
end func_axi4_stream_arr_or;
- function func_axi4_stream_arr_or(axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_axi4_stream_arr_or (axi4 : t_axi4_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(axi4'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -472,13 +480,13 @@ package body axi4_stream_pkg is
end if;
end func_axi4_stream_arr_or;
- function func_axi4_stream_arr_or(axi4 : t_axi4_siso_arr; str : string) return std_logic is
+ function func_axi4_stream_arr_or (axi4 : t_axi4_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(axi4'range) := (others => '1');
begin
return func_axi4_stream_arr_or(axi4, c_mask, str);
end func_axi4_stream_arr_or;
- function func_axi4_stream_arr_or(axi4 : t_axi4_sosi_arr; str : string) return std_logic is
+ function func_axi4_stream_arr_or (axi4 : t_axi4_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(axi4'range) := (others => '1');
begin
return func_axi4_stream_arr_or(axi4, c_mask, str);
@@ -486,7 +494,7 @@ package body axi4_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_axi4_stream_arr_set(axi4 : t_axi4_siso_arr; slv : std_logic_vector; str : string) return t_axi4_siso_arr is
+ function func_axi4_stream_arr_set (axi4 : t_axi4_siso_arr; slv : std_logic_vector; str : string) return t_axi4_siso_arr is
variable v_axi4 : t_axi4_siso_arr(axi4'range) := axi4; -- default
variable v_slv : std_logic_vector(axi4'range) := slv; -- map to ensure same range as for axi4
begin
@@ -498,7 +506,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_set;
- function func_axi4_stream_arr_set(axi4 : t_axi4_sosi_arr; slv : std_logic_vector; str : string) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_set (axi4 : t_axi4_sosi_arr; slv : std_logic_vector; str : string) return t_axi4_sosi_arr is
variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4; -- default
variable v_slv : std_logic_vector(axi4'range) := slv; -- map to ensure same range as for axi4
begin
@@ -510,19 +518,19 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_set;
- function func_axi4_stream_arr_set(axi4 : t_axi4_siso_arr; sl : std_logic; str : string) return t_axi4_siso_arr is
+ function func_axi4_stream_arr_set (axi4 : t_axi4_siso_arr; sl : std_logic; str : string) return t_axi4_siso_arr is
variable v_slv : std_logic_vector(axi4'range) := (others => sl);
begin
return func_axi4_stream_arr_set(axi4, v_slv, str);
end func_axi4_stream_arr_set;
- function func_axi4_stream_arr_set(axi4 : t_axi4_sosi_arr; sl : std_logic; str : string) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_set (axi4 : t_axi4_sosi_arr; sl : std_logic; str : string) return t_axi4_sosi_arr is
variable v_slv : std_logic_vector(axi4'range) := (others => sl);
begin
return func_axi4_stream_arr_set(axi4, v_slv, str);
end func_axi4_stream_arr_set;
- function func_axi4_stream_arr_get(axi4 : t_axi4_siso_arr; str : string) return std_logic_vector is
+ function func_axi4_stream_arr_get (axi4 : t_axi4_siso_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(axi4'range);
begin
for I in axi4'range loop
@@ -533,7 +541,7 @@ package body axi4_stream_pkg is
return v_ctrl;
end func_axi4_stream_arr_get;
- function func_axi4_stream_arr_get(axi4 : t_axi4_sosi_arr; str : string) return std_logic_vector is
+ function func_axi4_stream_arr_get (axi4 : t_axi4_sosi_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(axi4'range);
begin
for I in axi4'range loop
@@ -546,7 +554,7 @@ package body axi4_stream_pkg is
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_siso) return t_axi4_siso_arr is
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a, b : t_axi4_siso) return t_axi4_siso_arr is
variable v_axi4 : t_axi4_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -559,7 +567,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_select;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a : t_axi4_siso_arr; b : t_axi4_siso) return t_axi4_siso_arr is
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a : t_axi4_siso_arr; b : t_axi4_siso) return t_axi4_siso_arr is
variable v_axi4 : t_axi4_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -572,7 +580,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_select;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a : t_axi4_siso; b : t_axi4_siso_arr) return t_axi4_siso_arr is
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a : t_axi4_siso; b : t_axi4_siso_arr) return t_axi4_siso_arr is
variable v_axi4 : t_axi4_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -585,7 +593,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_select;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_siso_arr) return t_axi4_siso_arr is
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a, b : t_axi4_siso_arr) return t_axi4_siso_arr is
variable v_axi4 : t_axi4_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -598,7 +606,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_select;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_sosi) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a, b : t_axi4_sosi) return t_axi4_sosi_arr is
variable v_axi4 : t_axi4_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -611,7 +619,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_select;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a : t_axi4_sosi_arr; b : t_axi4_sosi) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a : t_axi4_sosi_arr; b : t_axi4_sosi) return t_axi4_sosi_arr is
variable v_axi4 : t_axi4_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -624,7 +632,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_select;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a : t_axi4_sosi; b : t_axi4_sosi_arr) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a : t_axi4_sosi; b : t_axi4_sosi_arr) return t_axi4_sosi_arr is
variable v_axi4 : t_axi4_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -637,7 +645,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_select;
- function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_sosi_arr) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_select (sel : std_logic_vector; a, b : t_axi4_sosi_arr) return t_axi4_sosi_arr is
variable v_axi4 : t_axi4_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -650,7 +658,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_select;
- function func_axi4_stream_arr_reverse_range(in_arr : t_axi4_siso_arr) return t_axi4_siso_arr is
+ function func_axi4_stream_arr_reverse_range (in_arr : t_axi4_siso_arr) return t_axi4_siso_arr is
variable v_to_range : t_axi4_siso_arr(0 to in_arr'high);
variable v_downto_range : t_axi4_siso_arr(in_arr'high downto 0);
begin
@@ -667,7 +675,7 @@ package body axi4_stream_pkg is
end if;
end func_axi4_stream_arr_reverse_range;
- function func_axi4_stream_arr_reverse_range(in_arr : t_axi4_sosi_arr) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_reverse_range (in_arr : t_axi4_sosi_arr) return t_axi4_sosi_arr is
variable v_to_range : t_axi4_sosi_arr(0 to in_arr'high);
variable v_downto_range : t_axi4_sosi_arr(in_arr'high downto 0);
begin
@@ -685,7 +693,7 @@ package body axi4_stream_pkg is
end func_axi4_stream_arr_reverse_range;
-- Functions to combinatorially hold the data fields and to set or reset the control fields in an sosi array
- function func_axi4_stream_arr_set_control(axi4 : t_axi4_sosi_arr; ctrl : t_axi4_sosi) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_set_control (axi4 : t_axi4_sosi_arr; ctrl : t_axi4_sosi) return t_axi4_sosi_arr is
variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4; -- hold sosi data
begin
for I in axi4'range loop -- set sosi control
@@ -696,7 +704,7 @@ package body axi4_stream_pkg is
return v_axi4;
end func_axi4_stream_arr_set_control;
- function func_axi4_stream_arr_reset_control(axi4 : t_axi4_sosi_arr) return t_axi4_sosi_arr is
+ function func_axi4_stream_arr_reset_control (axi4 : t_axi4_sosi_arr) return t_axi4_sosi_arr is
variable v_axi4 : t_axi4_sosi_arr(axi4'range) := axi4; -- hold sosi data
begin
for I in axi4'range loop -- reset sosi control
@@ -706,7 +714,7 @@ package body axi4_stream_pkg is
end func_axi4_stream_arr_reset_control;
-- Functions to convert dp streaming to axi4 streaming
- function func_axi4_stream_from_dp_sosi(dp_sosi : t_dp_sosi) return t_axi4_sosi is
+ function func_axi4_stream_from_dp_sosi (dp_sosi : t_dp_sosi) return t_axi4_sosi is
constant c_max_empty_w : natural := ceil_log2(c_axi4_stream_keep_w);
variable v_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
variable v_empty_int : natural := 0;
@@ -730,7 +738,7 @@ package body axi4_stream_pkg is
return v_axi4_sosi;
end func_axi4_stream_from_dp_sosi;
- function func_axi4_stream_from_dp_siso(dp_siso : t_dp_siso) return t_axi4_siso is
+ function func_axi4_stream_from_dp_siso (dp_siso : t_dp_siso) return t_axi4_siso is
variable v_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
-- Note that dp_siso.xon is not used.
begin
@@ -739,7 +747,7 @@ package body axi4_stream_pkg is
end func_axi4_stream_from_dp_siso;
-- Functions to convert dp streaming to axi4 streaming
- function func_axi4_stream_to_dp_sosi(axi4_sosi : t_axi4_sosi) return t_dp_sosi is
+ function func_axi4_stream_to_dp_sosi (axi4_sosi : t_axi4_sosi) return t_dp_sosi is
variable v_dp_sosi : t_dp_sosi := c_dp_sosi_rst;
begin
v_dp_sosi.data(c_axi4_stream_data_w - 1 downto 0) := axi4_sosi.tdata;
@@ -755,7 +763,7 @@ package body axi4_stream_pkg is
return v_dp_sosi;
end func_axi4_stream_to_dp_sosi;
- function func_axi4_stream_to_dp_siso(axi4_siso : t_axi4_siso) return t_dp_siso is
+ function func_axi4_stream_to_dp_siso (axi4_siso : t_axi4_siso) return t_dp_siso is
variable v_dp_siso : t_dp_siso := c_dp_siso_rdy;
begin
v_dp_siso.ready := axi4_siso.tready;
@@ -766,7 +774,7 @@ package body axi4_stream_pkg is
-- Function to derive DP empty from AXI4 tkeep by counting the 0s in TKEEP.
-- This function assumes that only the the last bytes in an AXI4 data element are set to be null by TKEEP.
-- e.g. TKEEP = 11111000 will be valid but TKEEP = 11011111 is not.
- function func_axi4_stream_tkeep_to_dp_empty(tkeep : std_logic_vector) return std_logic_vector is
+ function func_axi4_stream_tkeep_to_dp_empty (tkeep : std_logic_vector) return std_logic_vector is
variable v_count : natural := 0;
begin
for I in tkeep'range loop
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
index d2cdd4decc..234a664a09 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
@@ -43,16 +43,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_textio.all;
-use STD.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use work.axi4_lite_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_textio.all;
+ use STD.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use work.axi4_lite_pkg.all;
entity tb_axi4_lite_mm_bridge is
end tb_axi4_lite_mm_bridge;
@@ -62,11 +62,13 @@ architecture tb of tb_axi4_lite_mm_bridge is
constant c_mm_clk_period : time := 40 ns;
constant c_reset_len : natural := 4;
- constant c_mm_usr_ram : t_c_mem := (latency => 1,
- adr_w => 5,
- dat_w => 8,
- nof_dat => 32,
- init_sl => '0');
+ constant c_mm_usr_ram : t_c_mem := (
+ latency => 1,
+ adr_w => 5,
+ dat_w => 8,
+ nof_dat => 32,
+ init_sl => '0'
+ );
constant c_offset : natural := 57; -- Some value to offset the counter data written to ram.
signal mm_rst : std_logic;
@@ -90,50 +92,50 @@ begin
-- DUT
u_axi4_lite_mm_bridge : entity work.axi4_lite_mm_bridge
- port map (
- in_clk => mm_clk,
- in_rst => mm_rst,
-
- axi4_in_copi => axi_copi,
- axi4_in_cipo => axi_cipo,
- mm_out_copi => mm_out_copi,
- mm_out_cipo => mm_out_cipo,
- mm_in_copi => mm_in_copi,
- mm_in_cipo => mm_in_cipo,
- axi4_out_copi => axi_copi,
- axi4_out_cipo => axi_cipo
- );
+ port map (
+ in_clk => mm_clk,
+ in_rst => mm_rst,
+
+ axi4_in_copi => axi_copi,
+ axi4_in_cipo => axi_cipo,
+ mm_out_copi => mm_out_copi,
+ mm_out_cipo => mm_out_cipo,
+ mm_in_copi => mm_in_copi,
+ mm_in_cipo => mm_in_cipo,
+ axi4_out_copi => axi_copi,
+ axi4_out_cipo => axi_cipo
+ );
-- Provide waitrequest stimuli to model a peripheral with MM flow control.
u_waitrequest_model : entity mm_lib.mm_waitrequest_model
- generic map (
- g_waitrequest => true,
- g_seed => c_offset
- )
- port map (
- mm_clk => mm_clk,
- bus_mosi => mm_out_copi,
- bus_miso => mm_out_cipo,
- slave_mosi => ram_copi,
- slave_miso => ram_cipo
- );
+ generic map (
+ g_waitrequest => true,
+ g_seed => c_offset
+ )
+ port map (
+ mm_clk => mm_clk,
+ bus_mosi => mm_out_copi,
+ bus_miso => mm_out_cipo,
+ slave_mosi => ram_copi,
+ slave_miso => ram_cipo
+ );
-- Use common ram as a MM peripherpal.
u_ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_mm_usr_ram
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- clken => '1',
- wr_en => ram_copi.wr,
- wr_dat => ram_copi.wrdata(c_mm_usr_ram.dat_w - 1 downto 0),
- wr_adr => ram_copi.address(c_mm_usr_ram.adr_w - 1 downto 0),
- rd_en => ram_copi.rd,
- rd_adr => ram_copi.address(c_mm_usr_ram.adr_w - 1 downto 0),
- rd_dat => ram_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0),
- rd_val => ram_cipo.rdval
- );
+ generic map (
+ g_ram => c_mm_usr_ram
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ clken => '1',
+ wr_en => ram_copi.wr,
+ wr_dat => ram_copi.wrdata(c_mm_usr_ram.dat_w - 1 downto 0),
+ wr_adr => ram_copi.address(c_mm_usr_ram.adr_w - 1 downto 0),
+ rd_en => ram_copi.rd,
+ rd_adr => ram_copi.address(c_mm_usr_ram.adr_w - 1 downto 0),
+ rd_dat => ram_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0),
+ rd_val => ram_cipo.rdval
+ );
-- Testbench writes/reads a number of words to/from memory through the axi4_lite_mm_bridge.
-- This tests the interface MM <-> AXI4-Lite <-> MM.
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
index 6f715815a1..ae45e65c8d 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
@@ -26,12 +26,12 @@
-- DP stream. The resulting DP stream is verified.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.axi4_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.axi4_stream_pkg.all;
entity tb_axi4_stream_dp_bridge is
generic (
@@ -168,26 +168,26 @@ begin
dut_sosi.eop <= in_eop;
dut : entity work.axi4_stream_dp_bridge
- generic map (
- g_use_empty => true,
- g_axi4_rl => g_axi4_rl,
- g_dp_rl => g_dp_rl
- )
- port map (
- in_rst => rst,
- in_clk => clk,
- -- ST sink
- dp_in_siso => dut_siso,
- dp_in_sosi => dut_sosi,
- -- ST source
- dp_out_siso => dut_out_siso,
- dp_out_sosi => dut_out_sosi,
- -- AXI4 Loopback
- axi4_in_sosi => dut_axi4_sosi,
- axi4_in_siso => dut_axi4_siso,
- axi4_out_sosi => dut_axi4_sosi,
- axi4_out_siso => dut_axi4_siso
- );
+ generic map (
+ g_use_empty => true,
+ g_axi4_rl => g_axi4_rl,
+ g_dp_rl => g_dp_rl
+ )
+ port map (
+ in_rst => rst,
+ in_clk => clk,
+ -- ST sink
+ dp_in_siso => dut_siso,
+ dp_in_sosi => dut_sosi,
+ -- ST source
+ dp_out_siso => dut_out_siso,
+ dp_out_sosi => dut_out_sosi,
+ -- AXI4 Loopback
+ axi4_in_sosi => dut_axi4_sosi,
+ axi4_in_siso => dut_axi4_siso,
+ axi4_out_sosi => dut_axi4_sosi,
+ axi4_out_siso => dut_axi4_siso
+ );
-- map record to sl, slv
dut_out_siso.ready <= out_ready; -- SISO
diff --git a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
index c1b95ec757..0404249490 100644
--- a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
@@ -25,7 +25,7 @@
-- ready-latency configurations.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_axi4_stream_dp_bridge is
diff --git a/libraries/base/common/src/vhdl/avs_common_mm.vhd b/libraries/base/common/src/vhdl/avs_common_mm.vhd
index fb5f3f1a7e..a14f249c79 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
index 297b27dc3a..12c17bb954 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
@@ -27,7 +27,7 @@
-- . The avs_common_mm_irq_hw.tcl determines the read latency, which is 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_irq is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
index de9a302e22..65d52f3ef2 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
@@ -29,7 +29,7 @@
-- Read latency 0 implies that the MM bus needs to use the waitrequest signal.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency0 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
index f88458d859..54440bc614 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
@@ -28,7 +28,7 @@
-- avs_common_mm_hw.tcl.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency2 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
index 3d6d8a6cb4..115ad78013 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
@@ -28,7 +28,7 @@
-- avs_common_mm_hw.tcl.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency4 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
index 72762cb6dc..fdfde32fce 100644
--- a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
@@ -33,8 +33,8 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
entity avs_common_ram_crw_crw is
generic ( -- t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2**10, 'X'); -- 1 M9K
@@ -76,28 +76,28 @@ begin
u_common_ram_crw_crw : entity work.common_ram_crw_crw
generic map(
- g_ram => c_avs_memrec,
- g_init_file => g_init_file
+ g_ram => c_avs_memrec,
+ g_init_file => g_init_file
)
port map(
- rst_a => csi_system_reset,
- rst_b => coe_rst_export,
- clk_a => csi_system_clk,
- clk_b => coe_clk_export,
- clken_a => '1',
- clken_b => '1',
- wr_en_a => avs_ram_write,
- wr_en_b => coe_wr_en_export,
- wr_dat_a => avs_ram_writedata,
- wr_dat_b => coe_wr_dat_export,
- adr_a => avs_ram_address,
- adr_b => coe_adr_export,
- rd_en_a => avs_ram_read,
- rd_en_b => coe_rd_en_export,
- rd_dat_a => avs_ram_readdata,
- rd_dat_b => coe_rd_dat_export,
- rd_val_a => OPEN,
- rd_val_b => coe_rd_val_export
+ rst_a => csi_system_reset,
+ rst_b => coe_rst_export,
+ clk_a => csi_system_clk,
+ clk_b => coe_clk_export,
+ clken_a => '1',
+ clken_b => '1',
+ wr_en_a => avs_ram_write,
+ wr_en_b => coe_wr_en_export,
+ wr_dat_a => avs_ram_writedata,
+ wr_dat_b => coe_wr_dat_export,
+ adr_a => avs_ram_address,
+ adr_b => coe_adr_export,
+ rd_en_a => avs_ram_read,
+ rd_en_b => coe_rd_en_export,
+ rd_dat_a => avs_ram_readdata,
+ rd_dat_b => coe_rd_dat_export,
+ rd_val_a => OPEN,
+ rd_val_b => coe_rd_val_export
);
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
index 741bec4515..79728a9d83 100644
--- a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
@@ -33,9 +33,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity avs_common_reg_r_w is
generic (
diff --git a/libraries/base/common/src/vhdl/common_acapture.vhd b/libraries/base/common/src/vhdl/common_acapture.vhd
index ab60634803..c2eac15468 100644
--- a/libraries/base/common/src/vhdl/common_acapture.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture.vhd
@@ -38,8 +38,8 @@
-- = 1 could be used.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_acapture is
generic (
@@ -68,29 +68,29 @@ begin
-- pipeline input (all in input clock domain)
u_async_in : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => in_rst,
- clk => in_clk,
- din => in_dat,
- dout => i_in_cap
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => i_in_cap
+ );
-- capture input into output clock domain with first FF, and
-- additional pipeline output with extra FF when g_out_delay_len > 1 to combat potential meta-stability
u_async_out : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => in_rst,
- clk => out_clk,
- din => i_in_cap,
- dout => out_cap
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => out_clk,
+ din => i_in_cap,
+ dout => out_cap
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_acapture_slv.vhd b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
index c36ff80608..76c81ce786 100644
--- a/libraries/base/common/src/vhdl/common_acapture_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
@@ -27,8 +27,8 @@
-- fit in 1 LAB if in_dat'LENGTH <= 10.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_acapture_slv is
generic (
@@ -55,19 +55,19 @@ begin
gen_slv: for I in in_dat'range generate
u_acap : entity work.common_acapture
- generic map (
- g_rst_level => g_rst_level,
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_dat => in_dat(I),
- in_cap => in_cap(I),
- out_clk => out_clk,
- out_cap => out_cap(I)
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_dat => in_dat(I),
+ in_cap => in_cap(I),
+ out_clk => out_clk,
+ out_cap => out_cap(I)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_accumulate.vhd b/libraries/base/common/src/vhdl/common_accumulate.vhd
index f3a2fb991f..6827504cd2 100644
--- a/libraries/base/common/src/vhdl/common_accumulate.vhd
+++ b/libraries/base/common/src/vhdl/common_accumulate.vhd
@@ -26,9 +26,9 @@
-- active.
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_accumulate is
generic (
@@ -48,9 +48,9 @@ end common_accumulate;
architecture rtl of common_accumulate is
- constant c_acc_w : natural := out_dat'length;
+ constant c_acc_w : natural := out_dat'length;
- signal result : std_logic_vector(c_acc_w - 1 downto 0);
+ signal result : std_logic_vector(c_acc_w - 1 downto 0);
begin
diff --git a/libraries/base/common/src/vhdl/common_add_sub.vhd b/libraries/base/common/src/vhdl/common_add_sub.vhd
index 88f16152e0..360d0dfe19 100644
--- a/libraries/base/common/src/vhdl/common_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_add_sub.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_add_sub is
generic (
@@ -84,17 +84,17 @@ begin
end generate;
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
- g_in_dat_w => result'LENGTH,
- g_out_dat_w => result'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result_p(result'range),
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
+ g_in_dat_w => result'LENGTH,
+ g_out_dat_w => result'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result_p(result'range),
+ out_dat => result
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_add_symbol.vhd b/libraries/base/common/src/vhdl/common_add_symbol.vhd
index 9cc606cd2b..7aeedc6e55 100644
--- a/libraries/base/common/src/vhdl/common_add_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_add_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Per symbol add of the two input data stream
-- Description:
@@ -83,50 +83,50 @@ begin
-- pipeline data output
u_out_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_symbols * g_symbol_w,
- g_out_dat_w => g_nof_symbols * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sum_data,
- out_dat => out_data
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_symbols * g_symbol_w,
+ g_out_dat_w => g_nof_symbols * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sum_data,
+ out_dat => out_data
+ );
-- pipeline control output
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_adder_staged.vhd b/libraries/base/common/src/vhdl/common_adder_staged.vhd
index a9ad2faf48..dea48a4bfe 100644
--- a/libraries/base/common/src/vhdl/common_adder_staged.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_staged.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Status:
-- . Compiles OK, but still needs to be functionally verified with a test bench.
@@ -96,34 +96,34 @@ begin
------------------------------------------------------------------------------
u_pipe_a : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline_input,
- g_reset_value => 0,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat_a,
- out_dat => reg_dat_a
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline_input,
+ g_reset_value => 0,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat_a,
+ out_dat => reg_dat_a
+ );
u_pipe_b : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline_input,
- g_reset_value => 0,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat_b,
- out_dat => reg_dat_b
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline_input,
+ g_reset_value => 0,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat_b,
+ out_dat => reg_dat_b
+ );
------------------------------------------------------------------------------
-- Multiple adder sections (g_adder_w < g_dat_w)
@@ -172,28 +172,6 @@ begin
m_b(0, SECTION) <= vec_dat_b((SECTION + 1) * g_adder_w - 1 downto SECTION * g_adder_w);
u_stage_add_input : entity common_lib.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "UNSIGNED", -- must treat the sections as unsigned
- g_pipeline_input => 0,
- g_pipeline_output => 1,
- g_in_dat_w => g_adder_w,
- g_out_dat_w => g_adder_w + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => m_a(0, SECTION),
- in_b => m_b(0, SECTION),
- result => m_sum(0, SECTION)
- );
-
- gen_stage : for STAGE in 1 to c_nof_adder - 1 generate
- m_a(STAGE, SECTION) <= m_sum(STAGE-1, SECTION )(g_adder_w - 1 downto 0); -- sum from preceding stage
- m_b(STAGE, SECTION) <= RESIZE_UVEC(m_sum(STAGE-1, SECTION - 1)(g_adder_w), g_adder_w); -- carry from less significant section in preceding stage
-
- -- Adder stages to add and propagate the carry for each section
- u_add_carry : entity common_lib.common_add_sub
generic map (
g_direction => "ADD",
g_representation => "UNSIGNED", -- must treat the sections as unsigned
@@ -205,10 +183,32 @@ begin
port map (
clk => clk,
clken => clken,
- in_a => m_a(STAGE, SECTION),
- in_b => m_b(STAGE, SECTION), -- + carry 0 or 1 from the less significant adder section
- result => m_sum(STAGE, SECTION)
+ in_a => m_a(0, SECTION),
+ in_b => m_b(0, SECTION),
+ result => m_sum(0, SECTION)
);
+
+ gen_stage : for STAGE in 1 to c_nof_adder - 1 generate
+ m_a(STAGE, SECTION) <= m_sum(STAGE-1, SECTION )(g_adder_w - 1 downto 0); -- sum from preceding stage
+ m_b(STAGE, SECTION) <= RESIZE_UVEC(m_sum(STAGE-1, SECTION - 1)(g_adder_w), g_adder_w); -- carry from less significant section in preceding stage
+
+ -- Adder stages to add and propagate the carry for each section
+ u_add_carry : entity common_lib.common_add_sub
+ generic map (
+ g_direction => "ADD",
+ g_representation => "UNSIGNED", -- must treat the sections as unsigned
+ g_pipeline_input => 0,
+ g_pipeline_output => 1,
+ g_in_dat_w => g_adder_w,
+ g_out_dat_w => g_adder_w + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => m_a(STAGE, SECTION),
+ in_b => m_b(STAGE, SECTION), -- + carry 0 or 1 from the less significant adder section
+ result => m_sum(STAGE, SECTION)
+ );
end generate;
-- map the adder sections from the last stage to the output to slv
@@ -217,19 +217,19 @@ begin
-- Rest output pipeline
u_out_val : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline_output - c_nof_adder,
- g_reset_value => 0,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => vec_add(g_dat_w - 1 downto 0), -- resize length of multiple g_adder_w back to g_dat_w width
- out_dat => out_dat
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline_output - c_nof_adder,
+ g_reset_value => 0,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => vec_add(g_dat_w - 1 downto 0), -- resize length of multiple g_adder_w back to g_dat_w width
+ out_dat => out_dat
+ );
end generate;
@@ -238,19 +238,19 @@ begin
------------------------------------------------------------------------------
u_out_val : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_val_slv,
- out_dat => out_val_slv
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_val_slv,
+ out_dat => out_val_slv
+ );
in_val_slv(0) <= in_val;
out_val <= out_val_slv(0);
diff --git a/libraries/base/common/src/vhdl/common_adder_tree.vhd b/libraries/base/common/src/vhdl/common_adder_tree.vhd
index 067ef08302..66940bc807 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Parallel adder tree.
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
index 71fe3fb65c..876d0d10ff 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
architecture recursive of common_adder_tree is
@@ -33,7 +33,7 @@ architecture recursive of common_adder_tree is
constant c_nof_h2 : natural := g_nof_inputs - g_nof_inputs / 2; -- upper half
-- The h1 branch needs an extra dummy stage when c_nof_h1 is a power of 2 AND c_nof_h2=c_nof_h1+1
- function func_stage_h1(h1, h2 : natural) return boolean is
+ function func_stage_h1 (h1, h2 : natural) return boolean is
variable v_ret : boolean := false;
begin
if h1 > 1 then
@@ -80,69 +80,69 @@ begin
leaf_pipe : if g_nof_inputs = 1 generate
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => result
+ );
end generate;
leaf_add : if g_nof_inputs = 2 generate
u_add : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => c_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_dat( g_dat_w - 1 downto 0 ),
- in_b => in_dat(2 * g_dat_w - 1 downto g_dat_w),
- result => result
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => c_sum_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_dat( g_dat_w - 1 downto 0 ),
+ in_b => in_dat(2 * g_dat_w - 1 downto g_dat_w),
+ result => result
+ );
end generate;
gen_tree : if g_nof_inputs > 2 generate
u_h1 : common_adder_tree
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_nof_inputs => c_nof_h1,
- g_dat_w => g_dat_w,
- g_sum_w => c_sum_h1_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat(c_nof_h1 * g_dat_w - 1 downto 0),
- sum => sum_h1
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_nof_inputs => c_nof_h1,
+ g_dat_w => g_dat_w,
+ g_sum_w => c_sum_h1_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat(c_nof_h1 * g_dat_w - 1 downto 0),
+ sum => sum_h1
+ );
u_h2 : common_adder_tree
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_nof_inputs => c_nof_h2,
- g_dat_w => g_dat_w,
- g_sum_w => c_sum_h2_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat(g_nof_inputs * g_dat_w - 1 downto c_nof_h1 * g_dat_w),
- sum => sum_h2
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_nof_inputs => c_nof_h2,
+ g_dat_w => g_dat_w,
+ g_sum_w => c_sum_h2_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat(g_nof_inputs * g_dat_w - 1 downto c_nof_h1 * g_dat_w),
+ sum => sum_h2
+ );
no_reg_h1 : if c_stage_h1 = false generate
sum_h1_reg <= sum_h1;
@@ -150,36 +150,36 @@ begin
gen_reg_h1 : if c_stage_h1 = true generate
u_reg_h1 : entity work.common_pipeline
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_sum_h1_w,
+ g_out_dat_w => c_sum_h2_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => sum_h1,
+ out_dat => sum_h1_reg
+ );
+ end generate;
+
+ trunk_add : entity work.common_add_sub
generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => c_sum_h1_w,
- g_out_dat_w => c_sum_h2_w
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => c_sum_h_w,
+ g_out_dat_w => c_sum_w
)
port map (
clk => clk,
clken => clken,
- in_dat => sum_h1,
- out_dat => sum_h1_reg
+ in_a => sum_h1_reg,
+ in_b => sum_h2,
+ result => result
);
- end generate;
-
- trunk_add : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => c_sum_h_w,
- g_out_dat_w => c_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => sum_h1_reg,
- in_b => sum_h2,
- result => result
- );
end generate;
sum <= RESIZE_SVEC(result, g_sum_w) when g_representation = "SIGNED" else RESIZE_UVEC(result, g_sum_w);
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
index 3c98a1d554..c16b1bc070 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
architecture str of common_adder_tree is
@@ -94,39 +94,39 @@ begin
gen_stage : for j in 0 to c_nof_stages - 1 generate
gen_add : for i in 0 to (c_N + (2**j) - 1) / (2**(j + 1)) - 1 generate
u_addj : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => c_w + j,
- g_out_dat_w => c_w + j + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => adds(j - 1)((2 * i + 1) * (c_w + j) - 1 downto (2 * i + 0) * (c_w + j)),
- in_b => adds(j - 1)((2 * i + 2) * (c_w + j) - 1 downto (2 * i + 1) * (c_w + j)),
- result => adds(j)((i + 1) * (c_w + j + 1) - 1 downto i * (c_w + j + 1))
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => c_w + j,
+ g_out_dat_w => c_w + j + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => adds(j - 1)((2 * i + 1) * (c_w + j) - 1 downto (2 * i + 0) * (c_w + j)),
+ in_b => adds(j - 1)((2 * i + 2) * (c_w + j) - 1 downto (2 * i + 1) * (c_w + j)),
+ result => adds(j)((i + 1) * (c_w + j + 1) - 1 downto i * (c_w + j + 1))
+ );
end generate;
gen_pipe : if ((c_N + (2**j) - 1) / (2**j)) mod 2 /= 0 generate
u_pipej : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => c_w + j,
- g_out_dat_w => c_w + j + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => adds(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * (c_w + j) - 1 downto
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_w + j,
+ g_out_dat_w => c_w + j + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => adds(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * (c_w + j) - 1 downto
(2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 0) * (c_w + j)),
- out_dat => adds(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * (c_w + j + 1) - 1 downto
+ out_dat => adds(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * (c_w + j + 1) - 1 downto
((c_N + (2**j) - 1) / (2**(j + 1)) ) * (c_w + j + 1))
- );
+ );
end generate;
end generate;
@@ -141,18 +141,18 @@ begin
-- g_dat_w+1 also for g_nof_inputs = 1, because we assume an adder stage
-- that adds 0 to the single in_dat.
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => sum
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_sum_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => sum
+ );
end generate; -- no_tree
end str;
diff --git a/libraries/base/common/src/vhdl/common_areset.vhd b/libraries/base/common/src/vhdl/common_areset.vhd
index 2430164b99..96d8e995ec 100644
--- a/libraries/base/common/src/vhdl/common_areset.vhd
+++ b/libraries/base/common/src/vhdl/common_areset.vhd
@@ -33,14 +33,14 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_areset is
generic (
g_in_rst_level : std_logic := '1'; -- = in_rst level
g_rst_level : std_logic := '1'; -- = out_rst level (keep original generic
- -- name for backward compatibility)
+ -- name for backward compatibility)
g_delay_len : natural := c_meta_delay_len
);
port (
@@ -63,15 +63,15 @@ begin
i_rst <= in_rst when g_in_rst_level = '1' else not in_rst;
u_async : entity work.common_async
- generic map (
- g_rst_level => c_out_rst_level,
- g_delay_len => g_delay_len
- )
- port map (
- rst => i_rst,
- clk => clk,
- din => c_out_rst_level_n,
- dout => out_rst
- );
+ generic map (
+ g_rst_level => c_out_rst_level,
+ g_delay_len => g_delay_len
+ )
+ port map (
+ rst => i_rst,
+ clk => clk,
+ din => c_out_rst_level_n,
+ dout => out_rst
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_async.vhd b/libraries/base/common/src/vhdl/common_async.vhd
index bbfe66d110..69d804f110 100644
--- a/libraries/base/common/src/vhdl/common_async.vhd
+++ b/libraries/base/common/src/vhdl/common_async.vhd
@@ -24,8 +24,8 @@
-- The delay line combats the potential meta-stability of clocked in data.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_async is
generic (
diff --git a/libraries/base/common/src/vhdl/common_async_slv.vhd b/libraries/base/common/src/vhdl/common_async_slv.vhd
index a43771f1d9..53d2b87373 100644
--- a/libraries/base/common/src/vhdl/common_async_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_async_slv.vhd
@@ -25,8 +25,8 @@
-- Remark:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_async_slv is
generic (
@@ -46,16 +46,16 @@ begin
gen_slv: for I in dout'range generate
u_common_async : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_delay_len
- )
- port map (
- rst => rst,
- clk => clk,
- din => din(I),
- dout => dout(I)
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ din => din(I),
+ dout => dout(I)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_bit_delay.vhd b/libraries/base/common/src/vhdl/common_bit_delay.vhd
index bb7cc3dc95..3d422662fb 100644
--- a/libraries/base/common/src/vhdl/common_bit_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_bit_delay.vhd
@@ -34,7 +34,7 @@
-- to remove in_clr or to not use shift_reg(0) combinatorially.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_bit_delay is
generic (
diff --git a/libraries/base/common/src/vhdl/common_blockreg.vhd b/libraries/base/common/src/vhdl/common_blockreg.vhd
index c850060bf0..e92eebaa2a 100755
--- a/libraries/base/common/src/vhdl/common_blockreg.vhd
+++ b/libraries/base/common/src/vhdl/common_blockreg.vhd
@@ -37,10 +37,10 @@
-- valid-dependent like the rest).
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_blockreg is
generic (
@@ -84,25 +84,25 @@ begin
out_val <= i_out_val;
u_fifo : entity work.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false,
- g_dat_w => g_dat_w,
- g_nof_words => g_block_size+1
- )
- port map (
- clk => clk,
- rst => rst,
-
- wr_dat => in_dat,
- wr_req => in_val,
-
- usedw => usedw,
- rd_req => rd_req,
-
- rd_dat => out_dat,
- rd_val => i_out_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false,
+ g_dat_w => g_dat_w,
+ g_nof_words => g_block_size+1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ wr_dat => in_dat,
+ wr_req => in_val,
+
+ usedw => usedw,
+ rd_req => rd_req,
+
+ rd_dat => out_dat,
+ rd_val => i_out_val
+ );
-----------------------------------------------------------------------------
-- Toggle rd_req to create output blocks of g_block_size
@@ -143,11 +143,11 @@ begin
p_clk : process(rst, clk)
begin
if rst = '1' then
- out_cnt <= (others => '0');
- prev_rd_req <= '0';
- elsif rising_edge(clk) then
- out_cnt <= nxt_out_cnt;
- prev_rd_req <= rd_req;
+ out_cnt <= (others => '0');
+ prev_rd_req <= '0';
+ elsif rising_edge(clk) then
+ out_cnt <= nxt_out_cnt;
+ prev_rd_req <= rd_req;
end if;
end process;
diff --git a/libraries/base/common/src/vhdl/common_clip.vhd b/libraries/base/common/src/vhdl/common_clip.vhd
index 67bff34b13..120eaf17f5 100644
--- a/libraries/base/common/src/vhdl/common_clip.vhd
+++ b/libraries/base/common/src/vhdl/common_clip.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Function:
-- When enabled clip input, else pass input on unchanged. Report clippled
@@ -122,18 +122,18 @@ begin
pipe_in <= clip_ovr & clip_dat;
u_output_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => c_output_pipe,
- g_in_dat_w => c_dat_w + 1,
- g_out_dat_w => c_dat_w + 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => pipe_in,
- out_dat => pipe_out
- );
+ generic map (
+ g_pipeline => c_output_pipe,
+ g_in_dat_w => c_dat_w + 1,
+ g_out_dat_w => c_dat_w + 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => pipe_in,
+ out_dat => pipe_out
+ );
out_ovr <= pipe_out(pipe_out'high);
out_dat <= pipe_out(pipe_out'high - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
index a95588c5d2..427456e288 100644
--- a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Detect 400 MHz in_clk active in the 200 MHz dp_clk domain
-- Description:
@@ -78,55 +78,55 @@ architecture str of common_clock_active_detector is
begin
u_common_counter_in_clk : entity work.common_counter
- generic map (
- g_width => g_in_period_w
- )
- port map (
- rst => '0',
- clk => in_clk,
- count => in_clk_cnt
- );
+ generic map (
+ g_width => g_in_period_w
+ )
+ port map (
+ rst => '0',
+ clk => in_clk,
+ count => in_clk_cnt
+ );
in_toggle <= in_clk_cnt(in_clk_cnt'high);
u_common_async_dp_toggle : entity work.common_async
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- din => in_toggle,
- dout => dp_toggle
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ din => in_toggle,
+ dout => dp_toggle
+ );
u_common_evt : entity work.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_sig => dp_toggle,
- out_evt => dp_toggle_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_sig => dp_toggle,
+ out_evt => dp_toggle_revt
+ );
dp_clk_cnt_en <= '1' when unsigned(dp_clk_cnt) < c_dp_clk_cnt_max else '0';
dp_clk_cnt_clr <= dp_toggle_revt or not dp_clk_cnt_en;
u_common_counter_dp_clk : entity work.common_counter
- generic map (
- g_width => c_dp_clk_cnt_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_clr => dp_clk_cnt_clr,
- cnt_en => dp_clk_cnt_en,
- count => dp_clk_cnt
- );
+ generic map (
+ g_width => c_dp_clk_cnt_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_clr => dp_clk_cnt_clr,
+ cnt_en => dp_clk_cnt_en,
+ count => dp_clk_cnt
+ );
nxt_dp_clk_interval <= INCR_UVEC(dp_clk_cnt, 1) when dp_clk_cnt_clr = '1' else dp_clk_interval;
@@ -146,13 +146,13 @@ begin
dp_in_clk_detected <= i_dp_in_clk_detected;
u_common_stable_monitor : entity work.common_stable_monitor
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM
- r_in => i_dp_in_clk_detected,
- r_stable => dp_in_clk_stable,
- r_stable_ack => dp_in_clk_stable_ack
- );
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM
+ r_in => i_dp_in_clk_detected,
+ r_stable => dp_in_clk_stable,
+ r_stable_ack => dp_in_clk_stable_ack
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
index 5b0ac7e4a9..ab2f8994d2 100644
--- a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
@@ -93,8 +93,8 @@
-- pipeline stage.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_clock_phase_detector is
generic (
@@ -133,17 +133,17 @@ begin
-- Capture the in_clk in the clk domain
u_async : entity work.common_async
- generic map (
- g_rising_edge => g_rising_edge,
- g_rst_level => g_phase_rst_level,
- g_delay_len => c_delay_len
- )
- port map (
- rst => rst,
- clk => clk,
- din => in_clk,
- dout => in_phs_cap
- );
+ generic map (
+ g_rising_edge => g_rising_edge,
+ g_rst_level => g_phase_rst_level,
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ din => in_clk,
+ dout => in_phs_cap
+ );
-- Process the registers in the rising edge clk domain
gen_r_wire : if g_rising_edge = true generate
diff --git a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
index a2b8f79847..39570cab9e 100644
--- a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_complex_add_sub is
@@ -48,36 +48,36 @@ end common_complex_add_sub;
architecture str of common_complex_add_sub is
begin
add_re : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => g_representation,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_ar,
- in_b => in_br,
- result => out_re
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => g_representation,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_ar,
+ in_b => in_br,
+ result => out_re
+ );
add_im : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => g_representation,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_ai,
- in_b => in_bi,
- result => out_im
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => g_representation,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_ai,
+ in_b => in_bi,
+ result => out_im
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_complex_round.vhd b/libraries/base/common/src/vhdl/common_complex_round.vhd
index 43a764a4a5..9e4c025fe9 100644
--- a/libraries/base/common/src/vhdl/common_complex_round.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_round.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_complex_round is
generic (
@@ -47,36 +47,36 @@ architecture str of common_complex_round is
begin
re: entity work.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_round,
- g_round_clip => g_round_clip,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_re,
- out_dat => out_re
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_round,
+ g_round_clip => g_round_clip,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_re,
+ out_dat => out_re
+ );
im: entity work.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_round,
- g_round_clip => g_round_clip,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_im,
- out_dat => out_im
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_round,
+ g_round_clip => g_round_clip,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_im,
+ out_dat => out_im
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_components_pkg.vhd b/libraries/base/common/src/vhdl/common_components_pkg.vhd
index dd4a3306c8..77c7f57de2 100644
--- a/libraries/base/common/src/vhdl/common_components_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_components_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
-- Purpose: Component declarations to check positional mapping
-- Description:
@@ -31,22 +31,22 @@ use work.common_mem_pkg.all;
package common_components_pkg is
component common_pipeline is
- generic (
- g_representation : string := "SIGNED"; -- or "UNSIGNED"
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
- g_reset_value : integer := 0;
- g_in_dat_w : natural := 8;
- g_out_dat_w : natural := 9
- );
- port (
- rst : in std_logic := '0';
- clk : in std_logic;
- clken : in std_logic := '1';
- in_clr : in std_logic := '0';
- in_en : in std_logic := '1';
- in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
- out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
- );
+ generic (
+ g_representation : string := "SIGNED"; -- or "UNSIGNED"
+ g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
+ g_reset_value : integer := 0;
+ g_in_dat_w : natural := 8;
+ g_out_dat_w : natural := 9
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_clr : in std_logic := '0';
+ in_en : in std_logic := '1';
+ in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
+ out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
+ );
end component;
component common_pipeline_sl is
diff --git a/libraries/base/common/src/vhdl/common_counter.vhd b/libraries/base/common/src/vhdl/common_counter.vhd
index 904c0c3f3b..226ce8c2d6 100644
--- a/libraries/base/common/src/vhdl/common_counter.vhd
+++ b/libraries/base/common/src/vhdl/common_counter.vhd
@@ -33,8 +33,8 @@
-- via ceil_log2(g_max+1)>g_width and use this to init the cnt_max input.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_counter is
diff --git a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
index 8f5ba4e07e..7eb6f31ccc 100644
--- a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
@@ -50,8 +50,8 @@
-- out_sop and other strobes.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_create_strobes_from_valid is
generic (
diff --git a/libraries/base/common/src/vhdl/common_ddio_in.vhd b/libraries/base/common/src/vhdl/common_ddio_in.vhd
index ce2db6d1e6..d9697ea93e 100644
--- a/libraries/base/common/src/vhdl/common_ddio_in.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_in.vhd
@@ -22,8 +22,8 @@
-- Purpose: Capture double data rate FPGA input
library IEEE, technology_lib, tech_iobuf_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ddio_in is
generic(
@@ -45,17 +45,17 @@ architecture str of common_ddio_in is
begin
u_ddio_in : entity tech_iobuf_lib.tech_iobuf_ddio_in
- generic map (
- g_technology => g_technology,
- g_width => g_width
- )
- port map (
- in_dat => in_dat,
- in_clk => in_clk,
- in_clk_en => in_clk_en,
- rst => rst,
- out_dat_hi => out_dat_hi,
- out_dat_lo => out_dat_lo
- );
+ generic map (
+ g_technology => g_technology,
+ g_width => g_width
+ )
+ port map (
+ in_dat => in_dat,
+ in_clk => in_clk,
+ in_clk_en => in_clk_en,
+ rst => rst,
+ out_dat_hi => out_dat_hi,
+ out_dat_lo => out_dat_lo
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddio_out.vhd b/libraries/base/common/src/vhdl/common_ddio_out.vhd
index e98e80cdea..21b79442c9 100644
--- a/libraries/base/common/src/vhdl/common_ddio_out.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_out.vhd
@@ -22,8 +22,8 @@
-- Purpose: Double data rate FPGA output or register single data rate FPGA output
library IEEE, technology_lib, tech_iobuf_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ddio_out is
generic(
@@ -45,17 +45,17 @@ architecture str of common_ddio_out is
begin
u_ddio_out : entity tech_iobuf_lib.tech_iobuf_ddio_out
- generic map (
- g_technology => g_technology,
- g_width => g_width
- )
- port map (
- rst => rst,
- in_clk => in_clk,
- in_clk_en => in_clk_en,
- in_dat_hi => in_dat_hi,
- in_dat_lo => in_dat_lo,
- out_dat => out_dat
- );
+ generic map (
+ g_technology => g_technology,
+ g_width => g_width
+ )
+ port map (
+ rst => rst,
+ in_clk => in_clk,
+ in_clk_en => in_clk_en,
+ in_dat_hi => in_dat_hi,
+ in_dat_lo => in_dat_lo,
+ out_dat => out_dat
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddreg.vhd b/libraries/base/common/src/vhdl/common_ddreg.vhd
index db5716fb75..da822cbfc8 100644
--- a/libraries/base/common/src/vhdl/common_ddreg.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg.vhd
@@ -70,8 +70,8 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_r is
generic (
@@ -97,29 +97,29 @@ architecture str of common_ddreg_r is
begin
u_in : entity work.common_async
- generic map (
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => rst,
- clk => in_clk,
- din => in_dat,
- dout => in_dat_r
- );
+ generic map (
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => in_dat_r
+ );
in_dat_d <= in_dat_r when g_tsetup_delay_hi = false else in_dat_r when rising_edge(out_clk);
-- Output at rising edge
u_out_hi : entity work.common_async
- generic map (
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => rst,
- clk => out_clk,
- din => in_dat_d,
- dout => out_dat_r
- );
+ generic map (
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => out_clk,
+ din => in_dat_d,
+ dout => out_dat_r
+ );
end str;
@@ -128,8 +128,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_f is
generic (
@@ -155,30 +155,30 @@ architecture str of common_ddreg_f is
begin
u_in : entity work.common_async
- generic map (
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => rst,
- clk => in_clk,
- din => in_dat,
- dout => in_dat_r
- );
+ generic map (
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => in_dat_r
+ );
in_dat_d <= in_dat_r when g_tsetup_delay_lo = false else in_dat_r when falling_edge(out_clk);
-- Capture input at falling edge
u_fall : entity work.common_async
- generic map (
- g_rising_edge => false,
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => rst,
- clk => out_clk,
- din => in_dat_d,
- dout => out_dat_f
- );
+ generic map (
+ g_rising_edge => false,
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => out_clk,
+ din => in_dat_d,
+ dout => out_dat_f
+ );
end str;
@@ -188,8 +188,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_fr is
port (
@@ -218,8 +218,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg is
generic (
@@ -247,39 +247,39 @@ begin
-- out_dat_hi
u_ddreg_hi : entity work.common_ddreg_r
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len,
- g_tsetup_delay_hi => g_tsetup_delay_hi
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_r => out_dat_hi
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len,
+ g_tsetup_delay_hi => g_tsetup_delay_hi
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_r => out_dat_hi
+ );
-- out_dat_lo
u_ddreg_fall : entity work.common_ddreg_f
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len - 1,
- g_tsetup_delay_lo => g_tsetup_delay_lo
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_f => out_dat_f -- clocked at falling edge of out_clk
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len - 1,
+ g_tsetup_delay_lo => g_tsetup_delay_lo
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_f => out_dat_f -- clocked at falling edge of out_clk
+ );
u_ddreg_lo : entity work.common_ddreg_fr
- port map (
- rst => rst,
- clk => out_clk,
- in_dat_f => out_dat_f,
- out_dat_r => out_dat_lo -- clocked at rising edge of out_clk
- );
+ port map (
+ rst => rst,
+ clk => out_clk,
+ in_dat_f => out_dat_f,
+ out_dat_r => out_dat_lo -- clocked at rising edge of out_clk
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddreg_slv.vhd b/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
index abcff1433b..caa0a31e91 100644
--- a/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
@@ -24,8 +24,8 @@
-- Remark:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_slv is
generic (
@@ -48,18 +48,18 @@ begin
gen_slv: for I in in_dat'range generate
u_ddreg : entity work.common_ddreg
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat(I),
- rst => rst,
- out_clk => out_clk,
- out_dat_hi => out_dat_hi(I),
- out_dat_lo => out_dat_lo(I)
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat(I),
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_hi => out_dat_hi(I),
+ out_dat_lo => out_dat_lo(I)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_debounce.vhd b/libraries/base/common/src/vhdl/common_debounce.vhd
index 3029172fcc..e3238f5e45 100644
--- a/libraries/base/common/src/vhdl/common_debounce.vhd
+++ b/libraries/base/common/src/vhdl/common_debounce.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose:
--
@@ -32,8 +32,8 @@ use work.common_pkg.all;
entity common_debounce is
generic (
g_type : string := "BOTH"; -- "BOTH" = debounce g_latency clk cycles for both bgoing high when d_in='1' and for going low when d_in='0'
- -- "HIGH" = debounce g_latency clk cycles for going high when d_in='1', go low immediately when d_in='0'
- -- "LOW" = debounce g_latency clk cycles for going low when d_in='0', go high immediately when d_in='1'
+ -- "HIGH" = debounce g_latency clk cycles for going high when d_in='1', go low immediately when d_in='0'
+ -- "LOW" = debounce g_latency clk cycles for going low when d_in='0', go high immediately when d_in='1'
g_delay_len : natural := c_meta_delay_len; -- = 3, combat meta stability
g_latency : natural := 8; -- >= 1, combat debounces over nof clk cycles
g_init_level : std_logic := '1'
@@ -103,16 +103,16 @@ begin
end generate;
u_counter : entity work.common_counter
- generic map (
- g_width => c_latency_w
- )
- port map (
- rst => '0',
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => c_latency_w
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_deinterleave.vhd b/libraries/base/common/src/vhdl/common_deinterleave.vhd
index 5926f3e523..f16c7600c8 100644
--- a/libraries/base/common/src/vhdl/common_deinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_deinterleave.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Deinterleave input into g_nof_out output streams based on g_block_size.
-- Description:
@@ -38,7 +38,7 @@ entity common_deinterleave is
g_dat_w : natural;
g_block_size : natural;
g_align_out : boolean := false
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -72,18 +72,18 @@ architecture rtl of common_deinterleave is
begin
u_demux : entity work.common_demultiplexer
- generic map (
- g_nof_out => g_nof_out,
- g_dat_w => g_dat_w
- )
- port map (
- in_dat => in_dat,
- in_val => in_val,
-
- out_sel => demux_out_sel,
- out_dat => demux_out_dat,
- out_val => demux_out_val
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ in_dat => in_dat,
+ in_val => in_val,
+
+ out_sel => demux_out_sel,
+ out_dat => demux_out_dat,
+ out_val => demux_out_val
+ );
-----------------------------------------------------------------------------
-- Demultiplexer output selection
@@ -134,21 +134,21 @@ begin
gen_align_out: if g_align_out = true generate
gen_inter: for i in 0 to g_nof_out - 1 generate
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_nof_out * g_block_size - (i + 1) * g_block_size,
- g_nof_dat => 1,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => demux_out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
- in_val => demux_out_val(i),
-
- out_dat => out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
- out_val => out_val(i)
- );
+ generic map (
+ g_pipeline => g_nof_out * g_block_size - (i + 1) * g_block_size,
+ g_nof_dat => 1,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => demux_out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
+ in_val => demux_out_val(i),
+
+ out_dat => out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
+ out_val => out_val(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/common/src/vhdl/common_delay.vhd b/libraries/base/common/src/vhdl/common_delay.vhd
index 20475a681d..9e6662a193 100644
--- a/libraries/base/common/src/vhdl/common_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_delay.vhd
@@ -25,7 +25,7 @@
-- indicates an active clock cycle.
library ieee;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_delay is
generic (
diff --git a/libraries/base/common/src/vhdl/common_demultiplexer.vhd b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
index 5de2f9c789..9054feb152 100644
--- a/libraries/base/common/src/vhdl/common_demultiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
-- Purpose: Assign input to one of g_nof_out output streams based on out_sel input
-- Description: The output streams are concatenated into one SLV.
@@ -35,7 +35,7 @@ entity common_demultiplexer is
g_pipeline_out : natural := 0;
g_nof_out : natural;
g_dat_w : natural
- );
+ );
port (
rst : in std_logic := '0';
clk : in std_logic := '0'; -- for g_pipeline_* = 0 no rst and clk are needed, because then the demultiplexer works combinatorialy
diff --git a/libraries/base/common/src/vhdl/common_duty_cycle.vhd b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
index f5d7de3075..597ff3efe1 100644
--- a/libraries/base/common/src/vhdl/common_duty_cycle.vhd
+++ b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
@@ -36,9 +36,9 @@
-- s_assert
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use WORK.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use WORK.common_pkg.all;
entity common_duty_cycle is
generic (
@@ -90,21 +90,21 @@ begin
case r.state is
when s_idle => v.state := s_idle;
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt or dc_act_cnt = TO_UVEC(0, c_cycle_cnt_w) then
- v.state := s_deassert;
- elsif TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt or dc_act_cnt = dc_per_cnt then
- v.state := s_assert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt or dc_act_cnt = TO_UVEC(0, c_cycle_cnt_w) then
+ v.state := s_deassert;
+ elsif TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt or dc_act_cnt = dc_per_cnt then
+ v.state := s_assert;
+ end if;
when s_assert => v.dc_pulse := g_act_lvl;
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt and dc_act_cnt < dc_per_cnt then
- v.state := s_deassert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt and dc_act_cnt < dc_per_cnt then
+ v.state := s_deassert;
+ end if;
when s_deassert => v.dc_pulse := not(g_act_lvl);
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt and dc_act_cnt /= TO_UVEC(0, c_cycle_cnt_w) then
- v.state := s_assert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt and dc_act_cnt /= TO_UVEC(0, c_cycle_cnt_w) then
+ v.state := s_assert;
+ end if;
end case;
if rst = '1' then
diff --git a/libraries/base/common/src/vhdl/common_evt.vhd b/libraries/base/common/src/vhdl/common_evt.vhd
index 69706e8b87..deba25b162 100644
--- a/libraries/base/common/src/vhdl/common_evt.vhd
+++ b/libraries/base/common/src/vhdl/common_evt.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_evt is
generic (
diff --git a/libraries/base/common/src/vhdl/common_fanout.vhd b/libraries/base/common/src/vhdl/common_fanout.vhd
index abe0e582cb..4e24a15754 100644
--- a/libraries/base/common/src/vhdl/common_fanout.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout.vhd
@@ -28,8 +28,8 @@
-- registers maintain their value.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_fanout is
generic (
@@ -56,42 +56,42 @@ begin
gen_fanout : for i in g_nof_output - 1 downto 0 generate
u_pipe_en : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(i)
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_en,
- in_en => '1',
- out_dat => out_en_vec(i)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i)
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_en,
+ in_en => '1',
+ out_dat => out_en_vec(i)
+ );
u_pipe_valid : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(i)
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_val,
- in_en => in_en,
- out_dat => out_val_vec(i)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i)
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_val,
+ in_en => in_en,
+ out_dat => out_val_vec(i)
+ );
u_pipe_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_arr(i),
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- in_en => in_en,
- out_dat => out_dat_vec((i + 1) * g_dat_w - 1 downto i * g_dat_w)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i),
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ in_en => in_en,
+ out_dat => out_dat_vec((i + 1) * g_dat_w - 1 downto i * g_dat_w)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_fanout_tree.vhd b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
index 28fc5b496e..a5b222ec94 100644
--- a/libraries/base/common/src/vhdl/common_fanout_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Parallel fanout tree.
-- Description:
@@ -126,21 +126,21 @@ begin
gen_cell : for i in 0 to g_nof_output_per_cell**j - 1 generate
-- output k =
u_fanout : entity work.common_fanout
- generic map (
- g_nof_output => g_nof_output_per_cell,
- g_pipeline_arr => c_cell_pipeline_factor_arr(j) * c_cell_pipeline_arr,
- g_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_en => stage_en_vec_arr( j - 1)( i),
- in_val => stage_val_vec_arr(j - 1)( i),
- in_dat => stage_dat_vec_arr(j - 1)((i + 1) * g_dat_w - 1 downto i * g_dat_w),
- out_en_vec => stage_en_vec_arr( j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
- out_val_vec => stage_val_vec_arr(j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
- out_dat_vec => stage_dat_vec_arr(j)((i + 1) * g_nof_output_per_cell * g_dat_w - 1 downto i * g_nof_output_per_cell * g_dat_w)
- );
+ generic map (
+ g_nof_output => g_nof_output_per_cell,
+ g_pipeline_arr => c_cell_pipeline_factor_arr(j) * c_cell_pipeline_arr,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_en => stage_en_vec_arr( j - 1)( i),
+ in_val => stage_val_vec_arr(j - 1)( i),
+ in_dat => stage_dat_vec_arr(j - 1)((i + 1) * g_dat_w - 1 downto i * g_dat_w),
+ out_en_vec => stage_en_vec_arr( j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
+ out_val_vec => stage_val_vec_arr(j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
+ out_dat_vec => stage_dat_vec_arr(j)((i + 1) * g_nof_output_per_cell * g_dat_w - 1 downto i * g_nof_output_per_cell * g_dat_w)
+ );
end generate;
end generate;
@@ -151,21 +151,21 @@ begin
no_tree : if g_nof_output = 1 generate
u_reg : entity work.common_fanout
- generic map (
- g_nof_output => 1,
- g_pipeline_arr => c_cell_pipeline_factor_arr(0) * c_cell_pipeline_arr,
- g_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_en => in_en,
- in_val => in_val,
- in_dat => in_dat,
- out_en_vec => out_en_vec,
- out_val_vec => out_val_vec,
- out_dat_vec => out_dat_vec
- );
+ generic map (
+ g_nof_output => 1,
+ g_pipeline_arr => c_cell_pipeline_factor_arr(0) * c_cell_pipeline_arr,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_en => in_en,
+ in_val => in_val,
+ in_dat => in_dat,
+ out_en_vec => out_en_vec,
+ out_val_vec => out_val_vec,
+ out_dat_vec => out_dat_vec
+ );
end generate; -- no_tree
end str;
diff --git a/libraries/base/common/src/vhdl/common_field_pkg.vhd b/libraries/base/common/src/vhdl/common_field_pkg.vhd
index bdf62486d9..fcf2bcb922 100644
--- a/libraries/base/common/src/vhdl/common_field_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_field_pkg.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
-- Purpose:
-- . Dynamically map record-like field structures onto SLVs.
@@ -54,56 +54,56 @@ package common_field_pkg is
type t_common_field_arr is array(integer range <>) of t_common_field;
- function field_name_pad(name: string) return string;
+ function field_name_pad (name: string) return string;
- function field_default(slv_in: std_logic_vector) return std_logic_vector;
- function field_default(nat_in: natural) return std_logic_vector;
+ function field_default (slv_in: std_logic_vector) return std_logic_vector;
+ function field_default (nat_in: natural) return std_logic_vector;
- function field_map_defaults(field_arr : t_common_field_arr) return std_logic_vector; -- returns slv_out
+ function field_map_defaults (field_arr : t_common_field_arr) return std_logic_vector; -- returns slv_out
- function field_mode (field_arr : t_common_field_arr; name: string ) return string;
- function field_size (field_arr : t_common_field_arr; name: string ) return natural;
- function field_hi (field_arr : t_common_field_arr; name: string ) return integer;
- function field_hi (field_arr : t_common_field_arr; index: natural ) return natural;
- function field_lo (field_arr : t_common_field_arr; name: string ) return natural;
- function field_lo (field_arr : t_common_field_arr; index: natural ) return natural;
- function field_slv_len (field_arr : t_common_field_arr ) return natural;
- function field_slv_in_len (field_arr : t_common_field_arr ) return natural;
+ function field_mode (field_arr : t_common_field_arr; name: string ) return string;
+ function field_size (field_arr : t_common_field_arr; name: string ) return natural;
+ function field_hi (field_arr : t_common_field_arr; name: string ) return integer;
+ function field_hi (field_arr : t_common_field_arr; index: natural ) return natural;
+ function field_lo (field_arr : t_common_field_arr; name: string ) return natural;
+ function field_lo (field_arr : t_common_field_arr; index: natural ) return natural;
+ function field_slv_len (field_arr : t_common_field_arr ) return natural;
+ function field_slv_in_len (field_arr : t_common_field_arr ) return natural;
function field_slv_out_len (field_arr : t_common_field_arr ) return natural;
- function field_nof_words (field_arr : t_common_field_arr; word_w : natural ) return natural;
- function field_map_in (field_arr : t_common_field_arr; slv : std_logic_vector; word_w : natural ; mode : string) return std_logic_vector; -- returns word_arr
- function field_map_out (field_arr : t_common_field_arr; word_arr : std_logic_vector; word_w : natural ) return std_logic_vector; -- returns slv_out
- function field_map (field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector; -- returns word_arr
+ function field_nof_words (field_arr : t_common_field_arr; word_w : natural ) return natural;
+ function field_map_in (field_arr : t_common_field_arr; slv : std_logic_vector; word_w : natural ; mode : string) return std_logic_vector; -- returns word_arr
+ function field_map_out (field_arr : t_common_field_arr; word_arr : std_logic_vector; word_w : natural ) return std_logic_vector; -- returns slv_out
+ function field_map (field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector; -- returns word_arr
- function field_ovr_arr(field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr;
+ function field_ovr_arr (field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr;
- function field_exists(field_arr : t_common_field_arr; name: string) return boolean;
+ function field_exists (field_arr : t_common_field_arr; name: string) return boolean;
- function field_arr_set_mode(field_arr : t_common_field_arr; mode : string) return t_common_field_arr;
+ function field_arr_set_mode (field_arr : t_common_field_arr; mode : string) return t_common_field_arr;
- function sel_a_b(sel : boolean; a, b : t_common_field_arr ) return t_common_field_arr;
+ function sel_a_b (sel : boolean; a, b : t_common_field_arr ) return t_common_field_arr;
end common_field_pkg;
package body common_field_pkg is
- function field_name_pad(name: string) return string is
+ function field_name_pad (name: string) return string is
begin
return pad(name, c_common_field_name_len, ' ');
end field_name_pad;
- function field_default(slv_in: std_logic_vector) return std_logic_vector is
+ function field_default (slv_in: std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(slv_in, c_common_field_default_len);
end field_default;
- function field_default(nat_in: natural) return std_logic_vector is
+ function field_default (nat_in: natural) return std_logic_vector is
begin
return TO_UVEC(nat_in, c_common_field_default_len);
end field_default;
- function field_map_defaults(field_arr : t_common_field_arr) return std_logic_vector is
+ function field_map_defaults (field_arr : t_common_field_arr) return std_logic_vector is
variable v_slv_out : std_logic_vector(field_slv_out_len(field_arr) - 1 downto 0);
begin
for f in 0 to field_arr'high loop
@@ -114,7 +114,7 @@ package body common_field_pkg is
return v_slv_out;
end field_map_defaults;
- function field_mode(field_arr : t_common_field_arr; name: string) return string is
+ function field_mode (field_arr : t_common_field_arr; name: string) return string is
-- Returns the mode string of the passed (via name) field
begin
if field_exists(field_arr, name) then
@@ -128,7 +128,7 @@ package body common_field_pkg is
end if;
end field_mode;
- function field_size(field_arr : t_common_field_arr; name: string) return natural is
+ function field_size (field_arr : t_common_field_arr; name: string) return natural is
-- Returns the size of the passed (via name) field
begin
for i in 0 to field_arr'high loop
@@ -138,8 +138,8 @@ package body common_field_pkg is
end loop;
end field_size;
- function field_hi(field_arr : t_common_field_arr; name: string) return integer is
- -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
+ function field_hi (field_arr : t_common_field_arr; name: string) return integer is
+ -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
variable v_acc_hi : natural := 0;
begin
if field_exists(field_arr, name) then
@@ -156,8 +156,8 @@ package body common_field_pkg is
end if;
end field_hi;
- function field_hi(field_arr : t_common_field_arr; index : natural) return natural is
- -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated SLV
+ function field_hi (field_arr : t_common_field_arr; index : natural) return natural is
+ -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated SLV
variable v_acc_hi : natural := 0;
begin
for i in 0 to index loop
@@ -168,8 +168,8 @@ package body common_field_pkg is
end loop;
end field_hi;
- function field_lo(field_arr : t_common_field_arr; name: string) return natural is
- -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
+ function field_lo (field_arr : t_common_field_arr; name: string) return natural is
+ -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
variable v_acc_hi : natural := 0;
begin
if field_exists(field_arr, name) then
@@ -186,8 +186,8 @@ package body common_field_pkg is
end if;
end field_lo;
- function field_lo(field_arr : t_common_field_arr; index : natural) return natural is
- -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated SLV
+ function field_lo (field_arr : t_common_field_arr; index : natural) return natural is
+ -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated SLV
variable v_acc_hi : natural := 0;
begin
for i in 0 to index loop
@@ -198,8 +198,8 @@ package body common_field_pkg is
end loop;
end field_lo;
- function field_slv_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of all fields in field_arr
+ function field_slv_len (field_arr : t_common_field_arr) return natural is
+ -- Return the total length of all fields in field_arr
variable v_len : natural := 0;
begin
for i in 0 to field_arr'high loop
@@ -208,8 +208,8 @@ package body common_field_pkg is
return v_len;
end field_slv_len;
- function field_slv_in_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of the input fields in field_arr (= all "RO")
+ function field_slv_in_len (field_arr : t_common_field_arr) return natural is
+ -- Return the total length of the input fields in field_arr (= all "RO")
variable v_len : natural := 0;
begin
for f in 0 to field_arr'high loop
@@ -220,8 +220,8 @@ package body common_field_pkg is
return v_len;
end field_slv_in_len;
- function field_slv_out_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of the output fields in field_arr (= all "RW")
+ function field_slv_out_len (field_arr : t_common_field_arr) return natural is
+ -- Return the total length of the output fields in field_arr (= all "RW")
variable v_len : natural := 0;
begin
for f in 0 to field_arr'high loop
@@ -232,8 +232,8 @@ package body common_field_pkg is
return v_len;
end field_slv_out_len;
- function field_nof_words(field_arr : t_common_field_arr; word_w : natural) return natural is
- -- Return the number of words (of width word_w) required to hold field_arr
+ function field_nof_words (field_arr : t_common_field_arr; word_w : natural) return natural is
+ -- Return the number of words (of width word_w) required to hold field_arr
variable v_word_cnt : natural := 0;
variable v_nof_reg_words : natural;
begin
@@ -247,13 +247,13 @@ package body common_field_pkg is
return v_word_cnt;
end field_nof_words;
- function field_map_in(field_arr : t_common_field_arr; slv: std_logic_vector; word_w : natural; mode : string) return std_logic_vector is
- -- Re-map a field SLV into a larger SLV, support mapping both the slv_in or the slv_out that dependents on mode; each field starting at a word boundary (word_w)
+ function field_map_in (field_arr : t_common_field_arr; slv: std_logic_vector; word_w : natural; mode : string) return std_logic_vector is
+ -- Re-map a field SLV into a larger SLV, support mapping both the slv_in or the slv_out that dependents on mode; each field starting at a word boundary (word_w)
variable v_word_arr : std_logic_vector(field_nof_words(field_arr, word_w) * word_w - 1 downto 0) := (others => '0');
variable v_word_cnt : natural := 0;
begin
for f in 0 to field_arr'high loop
- -- Only extract the fields that are inputs
+ -- Only extract the fields that are inputs
if field_arr(f).mode = mode then -- if mode="RO" then slv = slv_in, else if mode="RW" then slv = slv_out
-- Extract the field
v_word_arr( v_word_cnt * word_w + field_arr(f).size-1 downto v_word_cnt * word_w) := slv( field_hi(field_arr, field_arr(f).name) downto field_lo(field_arr, field_arr(f).name) );
@@ -264,8 +264,8 @@ package body common_field_pkg is
return v_word_arr;
end field_map_in;
- function field_map_out(field_arr : t_common_field_arr; word_arr: std_logic_vector; word_w : natural) return std_logic_vector is
- -- Reverse of field_map_in
+ function field_map_out (field_arr : t_common_field_arr; word_arr: std_logic_vector; word_w : natural) return std_logic_vector is
+ -- Reverse of field_map_in
variable v_slv_out : std_logic_vector(field_slv_out_len(field_arr) - 1 downto 0) := (others => '0');
variable v_word_cnt : natural := 0;
begin
@@ -281,8 +281,8 @@ package body common_field_pkg is
return v_slv_out;
end field_map_out;
- function field_map(field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector is
- -- Create one SLV consisting of both read-only and output-readback fields, e.g. as input to an MM reg
+ function field_map (field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector is
+ -- Create one SLV consisting of both read-only and output-readback fields, e.g. as input to an MM reg
variable v_word_arr : std_logic_vector(field_nof_words(field_arr, word_w) * word_w - 1 downto 0);
variable v_word_cnt : natural := 0;
begin
@@ -299,8 +299,8 @@ package body common_field_pkg is
return v_word_arr;
end field_map;
- function field_ovr_arr(field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr is
- -- Copy field_arr but change widths to 1 to create a 1-bit override field for each field in field_arr.
+ function field_ovr_arr (field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr is
+ -- Copy field_arr but change widths to 1 to create a 1-bit override field for each field in field_arr.
variable v_ovr_field_arr : t_common_field_arr(field_arr'range);
begin
v_ovr_field_arr := field_arr;
@@ -311,17 +311,17 @@ package body common_field_pkg is
return v_ovr_field_arr;
end field_ovr_arr;
- function field_exists(field_arr : t_common_field_arr; name: string) return boolean is
+ function field_exists (field_arr : t_common_field_arr; name: string) return boolean is
begin
for i in field_arr'range loop
if field_arr(i).name = field_name_pad(name) then
return true;
end if;
end loop;
- return false;
+ return false;
end field_exists;
- function field_arr_set_mode(field_arr : t_common_field_arr; mode : string) return t_common_field_arr is
+ function field_arr_set_mode (field_arr : t_common_field_arr; mode : string) return t_common_field_arr is
variable v_field_arr : t_common_field_arr(field_arr'range);
begin
v_field_arr := field_arr;
@@ -331,7 +331,7 @@ package body common_field_pkg is
return v_field_arr;
end field_arr_set_mode;
- function sel_a_b(sel :boolean; a, b : t_common_field_arr) return t_common_field_arr is
+ function sel_a_b (sel :boolean; a, b : t_common_field_arr) return t_common_field_arr is
begin
if sel = true then
return a;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc.vhd b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
index 73e41b481f..8f2c75ff06 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
@@ -22,9 +22,9 @@
-- Purpose: Dual clock FIFO
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_dc is
generic (
@@ -77,27 +77,27 @@ begin
-- . synchronize release of rst to wr_clk domain
-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
u_wr_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => rst,
- clk => wr_clk,
- out_rst => wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => rst,
+ clk => wr_clk,
+ out_rst => wr_rst
+ );
-- Delay wr_init to ensure that FIFO ful has gone low after reset release
u_wr_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => wr_rst,
- clk => wr_clk,
- out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => wr_rst,
+ clk => wr_clk,
+ out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
+ );
wr_init_out <= wr_init;
@@ -119,24 +119,24 @@ begin
end process;
u_fifo : entity tech_fifo_lib.tech_fifo_dc
- generic map (
- g_technology => g_technology,
- g_dat_w => g_dat_w,
- g_nof_words => c_nof_words
- )
- port map (
- aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
- data => wr_dat,
- rdclk => rd_clk,
- rdreq => rd_en,
- wrclk => wr_clk,
- wrreq => wr_en,
- q => rd_dat,
- rdempty => emp,
- rdusedw => rdusedw,
- wrfull => ful,
- wrusedw => wrusedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_dat_w => g_dat_w,
+ g_nof_words => c_nof_words
+ )
+ port map (
+ aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
+ data => wr_dat,
+ rdclk => rd_clk,
+ rdreq => rd_en,
+ wrclk => wr_clk,
+ wrreq => wr_en,
+ q => rd_dat,
+ rdempty => emp,
+ rdusedw => rdusedw,
+ wrfull => ful,
+ wrusedw => wrusedw
+ );
proc_common_fifo_asserts("common_fifo_dc", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
index b98ceaf2bb..a8819453e4 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Control the FIFO fill level and report the dual clock lock status
-- Description:
@@ -229,25 +229,25 @@ begin
end process;
u_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_w
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => c_cnt_w
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
u_dc_locked_monitor : entity work.common_stable_monitor
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- MM
- r_in => i_dc_locked,
- r_stable => dc_stable,
- r_stable_ack => dc_stable_ack
- );
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- MM
+ r_in => i_dc_locked,
+ r_stable => dc_stable,
+ r_stable_ack => dc_stable_ack
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
index 6290c8f0b5..3517c930f7 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
@@ -41,9 +41,9 @@
-- been written to the FIFO the rdusedw will wrap and the output goes wrong.
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_dc_mixed_widths is
generic (
@@ -96,27 +96,27 @@ begin
-- . synchronize release of rst to wr_clk domain
-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
u_wr_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => rst,
- clk => wr_clk,
- out_rst => wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => rst,
+ clk => wr_clk,
+ out_rst => wr_rst
+ );
-- Delay wr_init to ensure that FIFO ful has gone low after reset release
u_wr_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => wr_rst,
- clk => wr_clk,
- out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => wr_rst,
+ clk => wr_clk,
+ out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
+ );
-- The FIFO under read and over write protection are kept enabled in the MegaWizard
wr_en <= wr_req and not wr_init; -- check on NOT ful is not necessary according to fifo_generator_ug175.pdf
@@ -135,25 +135,25 @@ begin
end process;
u_fifo : entity tech_fifo_lib.tech_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_nof_words => c_nof_words,
- g_wrdat_w => g_wr_dat_w,
- g_rddat_w => g_rd_dat_w
- )
- port map (
- aclr => wr_rst, -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
- data => wr_dat,
- rdclk => rd_clk,
- rdreq => rd_en,
- wrclk => wr_clk,
- wrreq => wr_en,
- q => rd_dat,
- rdempty => emp,
- rdusedw => rdusedw,
- wrfull => ful,
- wrusedw => wrusedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_words => c_nof_words,
+ g_wrdat_w => g_wr_dat_w,
+ g_rddat_w => g_rd_dat_w
+ )
+ port map (
+ aclr => wr_rst, -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
+ data => wr_dat,
+ rdclk => rd_clk,
+ rdreq => rd_en,
+ wrclk => wr_clk,
+ wrreq => wr_en,
+ q => rd_dat,
+ rdempty => emp,
+ rdusedw => rdusedw,
+ wrfull => ful,
+ wrusedw => wrusedw
+ );
proc_common_fifo_asserts("common_fifo_dc_mixed_widths", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
diff --git a/libraries/base/common/src/vhdl/common_fifo_rd.vhd b/libraries/base/common/src/vhdl/common_fifo_rd.vhd
index b977e8e0e4..090e6bcc7c 100644
--- a/libraries/base/common/src/vhdl/common_fifo_rd.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_rd.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
-- Description: -
@@ -58,21 +58,21 @@ architecture wrap of common_fifo_rd is
begin
u_rl0 : entity work.common_rl_decrease
- generic map (
- g_adapt => true,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => fifo_req,
- snk_in_dat => fifo_dat,
- snk_in_val => fifo_val,
- -- ST source: RL = 0
- src_in_ready => rd_req,
- src_out_dat => rd_dat,
- src_out_val => rd_val
- );
+ generic map (
+ g_adapt => true,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => fifo_req,
+ snk_in_dat => fifo_dat,
+ snk_in_val => fifo_val,
+ -- ST source: RL = 0
+ src_in_ready => rd_req,
+ src_out_dat => rd_dat,
+ src_out_val => rd_val
+ );
end wrap;
diff --git a/libraries/base/common/src/vhdl/common_fifo_sc.vhd b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
index fed8be82f9..cea627ba36 100644
--- a/libraries/base/common/src/vhdl/common_fifo_sc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
@@ -22,9 +22,9 @@
-- Purpose: Single clock FIFO
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_sc is
generic (
@@ -32,8 +32,8 @@ entity common_fifo_sc is
g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_fail_rd_emp : boolean := false; -- when TRUE report FAILURE when read from an empty FIFO
g_use_lut : boolean := false; -- when TRUE then force using LUTs via Altera eab="OFF",
- -- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
- -- there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
+ -- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
+ -- there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
g_reset : boolean := false; -- when TRUE release FIFO reset some cycles after rst release, else use rst directly
g_init : boolean := false; -- when TRUE force wr_req inactive for some cycles after FIFO reset release, else use wr_req as is
g_dat_w : natural := 36; -- 36 * 256 = 1 M9K
@@ -85,15 +85,15 @@ begin
-- Make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf). This is necessary in case
-- the FIFO reset is also used functionally to flush it, so not only after power up.
u_fifo_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => rst,
- clk => clk,
- out_rst => fifo_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => rst,
+ clk => clk,
+ out_rst => fifo_rst
+ );
end generate;
no_fifo_rst : if g_reset = false generate
fifo_rst <= rst;
@@ -102,15 +102,15 @@ begin
gen_init : if g_init = true generate
-- Wait at least 3 cycles after reset release before allowing fifo_wr_en (see fifo_generator_ug175.pdf)
u_fifo_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => fifo_rst,
- clk => clk,
- out_rst => fifo_init
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => fifo_rst,
+ clk => clk,
+ out_rst => fifo_init
+ );
p_init_reg : process(fifo_rst, clk)
begin
@@ -154,23 +154,23 @@ begin
-- 0 < some threshold < usedw < g_nof_words can be used as FIFO almost_full
-- 0 < usedw < some threshold < g_nof_words can be used as FIFO almost_empty
u_fifo : entity tech_fifo_lib.tech_fifo_sc
- generic map (
- g_technology => g_technology,
- g_use_eab => c_use_eab,
- g_dat_w => g_dat_w,
- g_nof_words => g_nof_words
- )
- port map (
- aclr => fifo_rst,
- clock => clk,
- data => fifo_wr_dat,
- rdreq => fifo_rd_en,
- wrreq => fifo_wr_en,
- empty => fifo_empty,
- full => fifo_full,
- q => rd_dat,
- usedw => fifo_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_eab => c_use_eab,
+ g_dat_w => g_dat_w,
+ g_nof_words => g_nof_words
+ )
+ port map (
+ aclr => fifo_rst,
+ clock => clk,
+ data => fifo_wr_dat,
+ rdreq => fifo_rd_en,
+ wrreq => fifo_wr_en,
+ empty => fifo_empty,
+ full => fifo_full,
+ q => rd_dat,
+ usedw => fifo_usedw
+ );
proc_common_fifo_asserts("common_fifo_sc", g_note_is_ful, g_fail_rd_emp, fifo_rst, clk, fifo_full, fifo_wr_en, clk, fifo_empty, fifo_rd_en);
diff --git a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
index 8bc6d474dc..6c726e8f67 100644
--- a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
+++ b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_flank_to_pulse is
port (
@@ -39,7 +39,7 @@ architecture str of common_flank_to_pulse is
begin
- p_in_dly : process(rst, clk)
+ p_in_dly : process(rst, clk)
begin
if rst = '1' then
flank_in_dly <= '0';
diff --git a/libraries/base/common/src/vhdl/common_frame_busy.vhd b/libraries/base/common/src/vhdl/common_frame_busy.vhd
index 00161c8b47..5585eff9e1 100644
--- a/libraries/base/common/src/vhdl/common_frame_busy.vhd
+++ b/libraries/base/common/src/vhdl/common_frame_busy.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Determine when there is an active frame
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_init.vhd b/libraries/base/common/src/vhdl/common_init.vhd
index 2028dcae21..7a471e8010 100644
--- a/libraries/base/common/src/vhdl/common_init.vhd
+++ b/libraries/base/common/src/vhdl/common_init.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
--
@@ -88,15 +88,15 @@ begin
nxt_init_reg <= '1' when cnt_en = '0' and prev_cnt_en = '1' else '0';
u_counter : entity common_lib.common_counter
- generic map (
- g_width => g_latency_w + 1
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => '0',
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => g_latency_w + 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => '0',
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_inout.vhd b/libraries/base/common/src/vhdl/common_inout.vhd
index 7dd8551283..00ac9602c2 100644
--- a/libraries/base/common/src/vhdl/common_inout.vhd
+++ b/libraries/base/common/src/vhdl/common_inout.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Tristate buffer
diff --git a/libraries/base/common/src/vhdl/common_int2float.vhd b/libraries/base/common/src/vhdl/common_int2float.vhd
index 4f66730799..84097e744d 100644
--- a/libraries/base/common/src/vhdl/common_int2float.vhd
+++ b/libraries/base/common/src/vhdl/common_int2float.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose:
-- Convert signed integer to semi-floating point number.
diff --git a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
index 00926e2bcd..1fe7d8805b 100644
--- a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use IEEE.numeric_std.all;
package common_interface_layers_pkg is
@@ -55,15 +55,15 @@ package common_interface_layers_pkg is
constant c_xgmii_c_start : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"01"; -- b'00000001' as byte 0 contains START word FB
constant c_xgmii_c_term : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0) := x"F8"; -- b'11111000' as byte 3 contains TERMINATE word FD, bytes 7..4 are IDLE.
- function func_xgmii_dc( data : in std_logic_vector(c_xgmii_data_w - 1 downto 0); ctrl : in std_logic_vector(c_xgmii_nof_lanes - 1 downto 0)) return std_logic_vector;
- function func_xgmii_d( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector;
- function func_xgmii_c( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector;
+ function func_xgmii_dc ( data : in std_logic_vector(c_xgmii_data_w - 1 downto 0); ctrl : in std_logic_vector(c_xgmii_nof_lanes - 1 downto 0)) return std_logic_vector;
+ function func_xgmii_d ( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector;
+ function func_xgmii_c ( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector;
type t_xgmii_dc_arr is array(integer range <>) of std_logic_vector(c_xgmii_w - 1 downto 0);
type t_xgmii_d_arr is array(integer range <>) of std_logic_vector(c_xgmii_data_w - 1 downto 0);
type t_xgmii_c_arr is array(integer range <>) of std_logic_vector(c_xgmii_nof_lanes - 1 downto 0);
- end common_interface_layers_pkg;
+end common_interface_layers_pkg;
package body common_interface_layers_pkg is
@@ -71,7 +71,7 @@ package body common_interface_layers_pkg is
-- (November 2011) page 3-11: SDR XGMII Tx Interface for the proper mapping.
-- Combine separate data and control bits into one XGMII SLV.
- function func_xgmii_dc( data : in std_logic_vector(c_xgmii_data_w - 1 downto 0); ctrl : in std_logic_vector(c_xgmii_nof_lanes - 1 downto 0)) return std_logic_vector is
+ function func_xgmii_dc ( data : in std_logic_vector(c_xgmii_data_w - 1 downto 0); ctrl : in std_logic_vector(c_xgmii_nof_lanes - 1 downto 0)) return std_logic_vector is
variable data_ctrl_out : std_logic_vector(c_xgmii_w - 1 downto 0);
begin
-- Lane 0:
@@ -103,7 +103,7 @@ package body common_interface_layers_pkg is
end;
-- Extract the data bits from combined data+ctrl XGMII SLV.
- function func_xgmii_d( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector is
+ function func_xgmii_d ( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector is
variable data_out : std_logic_vector(c_xgmii_data_w - 1 downto 0);
begin
-- Lane 0:
@@ -127,7 +127,7 @@ package body common_interface_layers_pkg is
end;
-- Extract the control bits from combined data+ctrl XGMII SLV.
- function func_xgmii_c( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector is
+ function func_xgmii_c ( data_ctrl: in std_logic_vector(c_xgmii_w - 1 downto 0)) return std_logic_vector is
variable ctrl_out : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0);
begin
-- Lane 0:
diff --git a/libraries/base/common/src/vhdl/common_interleave.vhd b/libraries/base/common/src/vhdl/common_interleave.vhd
index 6b2cb0e6bd..b78af46c22 100644
--- a/libraries/base/common/src/vhdl/common_interleave.vhd
+++ b/libraries/base/common/src/vhdl/common_interleave.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Interleave g_nof_in inputs into one output stream based on g_block_size.
-- Description:
@@ -40,7 +40,7 @@ entity common_interleave is
g_nof_in : natural; -- >= 2
g_dat_w : natural;
g_block_size : natural
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -115,46 +115,46 @@ begin
-----------------------------------------------------------------------------
gen_blockregs: for i in 0 to g_nof_in - 1 generate
u_blockreg : entity work.common_blockreg
- generic map (
- g_block_size => g_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => bkr_in_dat_arr(i),
- in_val => in_val,
-
- out_dat => bkr_out_dat_arr(i),
- out_val => bkr_out_val_arr(i)
+ generic map (
+ g_block_size => g_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => bkr_in_dat_arr(i),
+ in_val => in_val,
+
+ out_dat => bkr_out_dat_arr(i),
+ out_val => bkr_out_val_arr(i)
);
u_dat_block_offset_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => i * g_block_size,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => bkr_out_dat_arr(i),
- out_dat => piped_bkr_out_dat_arr(i)
- );
+ generic map (
+ g_pipeline => i * g_block_size,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => bkr_out_dat_arr(i),
+ out_dat => piped_bkr_out_dat_arr(i)
+ );
u_val_block_offset_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => i * g_block_size,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => slv(bkr_out_val_arr(i)),
- sl(out_dat) => piped_bkr_out_val_arr(i)
- );
+ generic map (
+ g_pipeline => i * g_block_size,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => slv(bkr_out_val_arr(i)),
+ sl(out_dat) => piped_bkr_out_val_arr(i)
+ );
end generate;
@@ -169,21 +169,21 @@ begin
-- The multiplexer
-----------------------------------------------------------------------------
u_mux : entity work.common_multiplexer
- generic map (
- g_nof_in => g_nof_in,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => mux_in_sel,
- in_dat => mux_in_concat_dat_arr,
- in_val => mux_in_val,
-
- out_dat => out_dat,
- out_val => out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_sel => mux_in_sel,
+ in_dat => mux_in_concat_dat_arr,
+ in_val => mux_in_val,
+
+ out_dat => out_dat,
+ out_val => out_val
+ );
-----------------------------------------------------------------------------
-- Multiplexer input selection
diff --git a/libraries/base/common/src/vhdl/common_interval_monitor.vhd b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
index be26be9693..cae299bec6 100644
--- a/libraries/base/common/src/vhdl/common_interval_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Monitor the nof valid clock cycles between two in_evt pulses
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_iobuf_in.vhd b/libraries/base/common/src/vhdl/common_iobuf_in.vhd
index 688910ed0d..7cde91658e 100644
--- a/libraries/base/common/src/vhdl/common_iobuf_in.vhd
+++ b/libraries/base/common/src/vhdl/common_iobuf_in.vhd
@@ -22,8 +22,8 @@
-- Purpose: Delay differential FPGA input
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_iobuf_in is
generic(
diff --git a/libraries/base/common/src/vhdl/common_led_controller.vhd b/libraries/base/common/src/vhdl/common_led_controller.vhd
index 145a404713..42a87c504c 100644
--- a/libraries/base/common/src/vhdl/common_led_controller.vhd
+++ b/libraries/base/common/src/vhdl/common_led_controller.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide visual activity information via a LED.
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
index 6e8d384cd4..35b7ac1fd5 100644
--- a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
@@ -30,9 +30,9 @@
-- . Based on Xilinx application note xapp052.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_lfsr_sequences_pkg is
@@ -52,111 +52,547 @@ package common_lfsr_sequences_pkg is
-- (0,0,0,0, 2, 1) yields repeat <0, 1, 2>
-- XNOR feedbacks from outputs for n = 3 .. 72 from Xilinx xapp052.pdf (that lists feedbacks for in total 168 sequences)
- constant c_common_lfsr_sequences : t_SEQUENCES := ((0,0,0,0,0, 1), -- 1 : <0, 1>
- (0,0,0,0, 0, 2), -- 2 : <0, 1, 3, 2>
- (0,0,0,0, 3, 2), -- 3
- (0,0,0,0, 4, 3), -- 4
- (0,0,0,0, 5, 3), -- 5
- (0,0,0,0, 6, 5), -- 6
- (0,0,0,0, 7, 6), -- 7
- (0,0, 8, 6, 5, 4), -- 8
- (0,0,0,0, 9, 5), -- 9
- (0,0,0,0, 10, 7), -- 10
- (0,0,0,0, 11, 9), -- 11
- (0,0, 12, 6, 4, 1), -- 12
- (0,0, 13, 4, 3, 1), -- 13
- (0,0, 14, 5, 3, 1), -- 14
- (0,0,0,0, 15,14 ), -- 15
- (0,0, 16,15,13, 4), -- 16
- (0,0,0,0, 17,14 ), -- 17
- (0,0,0,0, 18,11 ), -- 18
- (0,0, 19, 6, 2, 1), -- 19
- (0,0,0,0, 20,17 ), -- 20
- (0,0,0,0, 21,19 ), -- 21
- (0,0,0,0, 22,21 ), -- 22
- (0,0,0,0, 23,18 ), -- 23
- (0,0, 24,23,22,17), -- 24
- (0,0,0,0, 25,22 ), -- 25
- (0,0, 26, 6, 2, 1), -- 26
- (0,0, 27, 5, 2, 1), -- 27
- (0,0,0,0, 28,25 ), -- 28
- (0,0,0,0, 29,27 ), -- 29
- (0,0, 30, 6, 4, 1), -- 30
- (0,0,0,0, 31,28 ), -- 31
- (0,0, 32,22, 2, 1), -- 32
- (0,0,0,0, 33,20 ), -- 33
- (0,0, 34,27, 2, 1), -- 34
- (0,0,0,0, 35,33 ), -- 35
- (0,0,0,0, 36,25 ), -- 36
- ( 37, 5, 4, 3, 2, 1), -- 37
- (0,0, 38, 6, 5, 1), -- 38
- (0,0,0,0, 39,35 ), -- 39
- (0,0, 40,38,21,19), -- 40
- (0,0,0,0, 41,38 ), -- 41
- (0,0, 42,41,20,19), -- 42
- (0,0, 43,42,38,37), -- 43
- (0,0, 44,43,18,17), -- 44
- (0,0, 45,44,42,41), -- 45
- (0,0, 46,45,26,25), -- 46
- (0,0,0,0, 47,42 ), -- 47
- (0,0, 48,47,21,20), -- 48
- (0,0,0,0, 49,40 ), -- 49
- (0,0, 50,49,24,23), -- 50
- (0,0, 51,50,36,35), -- 51
- (0,0,0,0, 52,49 ), -- 52
- (0,0, 53,52,38,37), -- 53
- (0,0, 54,53,18,17), -- 54
- (0,0,0,0, 55,31 ), -- 55
- (0,0, 56,55,35,34), -- 56
- (0,0,0,0, 57,50 ), -- 57
- (0,0,0,0, 58,39 ), -- 58
- (0,0, 59,58,38,37), -- 59
- (0,0,0,0, 60,59 ), -- 60
- (0,0, 61,60,46,45), -- 61
- (0,0, 62,61, 6, 5), -- 62
- (0,0,0,0, 63,62 ), -- 63
- (0,0, 64,63,61,60), -- 64
- (0,0,0,0, 65,47 ), -- 65
- (0,0, 66,65,57,56), -- 66
- (0,0, 67,66,58,57), -- 67
- (0,0,0,0, 68,59 ), -- 68
- (0,0, 69,67,42,40), -- 69
- (0,0, 70,69,55,54), -- 70
- (0,0,0,0, 71,65 ), -- 71
- (0,0, 72,66,25,19)); -- 72
+ constant c_common_lfsr_sequences : t_SEQUENCES := (
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 1), -- 1 : <0, 1>
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 2), -- 2 : <0, 1, 3, 2>
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 3,
+ 2), -- 3
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 4,
+ 3), -- 4
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 5,
+ 3), -- 5
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 6,
+ 5), -- 6
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 7,
+ 6), -- 7
+ (
+ 0,
+ 0,
+ 8,
+ 6,
+ 5,
+ 4), -- 8
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 9,
+ 5), -- 9
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 10,
+ 7), -- 10
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 11,
+ 9), -- 11
+ (
+ 0,
+ 0,
+ 12,
+ 6,
+ 4,
+ 1), -- 12
+ (
+ 0,
+ 0,
+ 13,
+ 4,
+ 3,
+ 1), -- 13
+ (
+ 0,
+ 0,
+ 14,
+ 5,
+ 3,
+ 1), -- 14
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 15,
+ 14 ), -- 15
+ (
+ 0,
+ 0,
+ 16,
+ 15,
+ 13,
+ 4), -- 16
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 17,
+ 14 ), -- 17
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 18,
+ 11 ), -- 18
+ (
+ 0,
+ 0,
+ 19,
+ 6,
+ 2,
+ 1), -- 19
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 20,
+ 17 ), -- 20
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 21,
+ 19 ), -- 21
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 22,
+ 21 ), -- 22
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 23,
+ 18 ), -- 23
+ (
+ 0,
+ 0,
+ 24,
+ 23,
+ 22,
+ 17), -- 24
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 25,
+ 22 ), -- 25
+ (
+ 0,
+ 0,
+ 26,
+ 6,
+ 2,
+ 1), -- 26
+ (
+ 0,
+ 0,
+ 27,
+ 5,
+ 2,
+ 1), -- 27
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 28,
+ 25 ), -- 28
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 29,
+ 27 ), -- 29
+ (
+ 0,
+ 0,
+ 30,
+ 6,
+ 4,
+ 1), -- 30
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 31,
+ 28 ), -- 31
+ (
+ 0,
+ 0,
+ 32,
+ 22,
+ 2,
+ 1), -- 32
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 33,
+ 20 ), -- 33
+ (
+ 0,
+ 0,
+ 34,
+ 27,
+ 2,
+ 1), -- 34
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 35,
+ 33 ), -- 35
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 36,
+ 25 ), -- 36
+ (
+ 37,
+ 5,
+ 4,
+ 3,
+ 2,
+ 1), -- 37
+ (
+ 0,
+ 0,
+ 38,
+ 6,
+ 5,
+ 1), -- 38
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 39,
+ 35 ), -- 39
+ (
+ 0,
+ 0,
+ 40,
+ 38,
+ 21,
+ 19), -- 40
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 41,
+ 38 ), -- 41
+ (
+ 0,
+ 0,
+ 42,
+ 41,
+ 20,
+ 19), -- 42
+ (
+ 0,
+ 0,
+ 43,
+ 42,
+ 38,
+ 37), -- 43
+ (
+ 0,
+ 0,
+ 44,
+ 43,
+ 18,
+ 17), -- 44
+ (
+ 0,
+ 0,
+ 45,
+ 44,
+ 42,
+ 41), -- 45
+ (
+ 0,
+ 0,
+ 46,
+ 45,
+ 26,
+ 25), -- 46
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 47,
+ 42 ), -- 47
+ (
+ 0,
+ 0,
+ 48,
+ 47,
+ 21,
+ 20), -- 48
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 49,
+ 40 ), -- 49
+ (
+ 0,
+ 0,
+ 50,
+ 49,
+ 24,
+ 23), -- 50
+ (
+ 0,
+ 0,
+ 51,
+ 50,
+ 36,
+ 35), -- 51
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 52,
+ 49 ), -- 52
+ (
+ 0,
+ 0,
+ 53,
+ 52,
+ 38,
+ 37), -- 53
+ (
+ 0,
+ 0,
+ 54,
+ 53,
+ 18,
+ 17), -- 54
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 55,
+ 31 ), -- 55
+ (
+ 0,
+ 0,
+ 56,
+ 55,
+ 35,
+ 34), -- 56
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 57,
+ 50 ), -- 57
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 58,
+ 39 ), -- 58
+ (
+ 0,
+ 0,
+ 59,
+ 58,
+ 38,
+ 37), -- 59
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 60,
+ 59 ), -- 60
+ (
+ 0,
+ 0,
+ 61,
+ 60,
+ 46,
+ 45), -- 61
+ (
+ 0,
+ 0,
+ 62,
+ 61,
+ 6,
+ 5), -- 62
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 63,
+ 62 ), -- 63
+ (
+ 0,
+ 0,
+ 64,
+ 63,
+ 61,
+ 60), -- 64
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 65,
+ 47 ), -- 65
+ (
+ 0,
+ 0,
+ 66,
+ 65,
+ 57,
+ 56), -- 66
+ (
+ 0,
+ 0,
+ 67,
+ 66,
+ 58,
+ 57), -- 67
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 68,
+ 59 ), -- 68
+ (
+ 0,
+ 0,
+ 69,
+ 67,
+ 42,
+ 40), -- 69
+ (
+ 0,
+ 0,
+ 70,
+ 69,
+ 55,
+ 54), -- 70
+ (
+ 0,
+ 0,
+ 0,
+ 0,
+ 71,
+ 65 ), -- 71
+ (
+ 0,
+ 0,
+ 72,
+ 66,
+ 25,
+ 19)
+ ); -- 72
-- Procedure for calculating the next PSRG and COUNTER sequence value
- procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
- constant g_incr : in integer;
- in_en : in std_logic;
- in_req : in std_logic;
- in_dat : in std_logic_vector;
- prsg : in std_logic_vector;
- cntr : in std_logic_vector;
- signal nxt_prsg : out std_logic_vector;
- signal nxt_cntr : out std_logic_vector);
+ procedure common_lfsr_nxt_seq (
+ constant c_lfsr_nr : in natural;
+ constant g_incr : in integer;
+ in_en : in std_logic;
+ in_req : in std_logic;
+ in_dat : in std_logic_vector;
+ prsg : in std_logic_vector;
+ cntr : in std_logic_vector;
+ signal nxt_prsg : out std_logic_vector;
+ signal nxt_cntr : out std_logic_vector);
-- Use lfsr part of common_lfsr_nxt_seq to make a random bit generator function
-- . width of lfsr selects the LFSR sequence
-- . initialized lfsr with (OTHERS=>'0')
-- . use lfsr(lfsr'HIGH) as random bit
- function func_common_random(lfsr : std_logic_vector) return std_logic_vector;
+ function func_common_random (lfsr : std_logic_vector) return std_logic_vector;
end common_lfsr_sequences_pkg;
package body common_lfsr_sequences_pkg is
- procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
- constant g_incr : in integer;
- in_en : in std_logic;
- in_req : in std_logic;
- in_dat : in std_logic_vector;
- prsg : in std_logic_vector;
- cntr : in std_logic_vector;
- signal nxt_prsg : out std_logic_vector;
- signal nxt_cntr : out std_logic_vector) is
+ procedure common_lfsr_nxt_seq (
+ constant c_lfsr_nr : in natural;
+ constant g_incr : in integer;
+ in_en : in std_logic;
+ in_req : in std_logic;
+ in_dat : in std_logic_vector;
+ prsg : in std_logic_vector;
+ cntr : in std_logic_vector;
+ signal nxt_prsg : out std_logic_vector;
+ signal nxt_cntr : out std_logic_vector) is
variable v_feedback : std_logic;
begin
nxt_prsg <= prsg;
@@ -181,7 +617,7 @@ package body common_lfsr_sequences_pkg is
end if;
end common_lfsr_nxt_seq;
- function func_common_random(lfsr : std_logic_vector) return std_logic_vector is
+ function func_common_random (lfsr : std_logic_vector) return std_logic_vector is
constant c_lfsr_nr : natural := lfsr'length - c_common_lfsr_first;
variable v_nxt_lfsr : std_logic_vector(lfsr'range);
variable v_feedback : std_logic;
diff --git a/libraries/base/common/src/vhdl/common_math_pkg.vhd b/libraries/base/common/src/vhdl/common_math_pkg.vhd
index 36c4660556..b25d4da636 100644
--- a/libraries/base/common/src/vhdl/common_math_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_math_pkg.vhd
@@ -33,10 +33,10 @@
-- is reduced to within the [0:2pi> range inside SIN() or COS().
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
package common_math_pkg is
@@ -46,25 +46,25 @@ package common_math_pkg is
-- . freq is the number of periods in N samples
-- . phi is phase offset in radials
-- . use common_math_create_look_up_table_phasor() to create a complex phasor look up table
- function common_math_create_look_up_table_cos(N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr;
- function common_math_create_look_up_table_sin(N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr;
+ function common_math_create_look_up_table_cos (N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr;
+ function common_math_create_look_up_table_sin (N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr;
-- Function to create the cos/sin lookup table with one period and maximum amplitude
-- . N is number of samples in the lookup table, [0:N-1] = [0:N> = [0:2pi>
-- . ampl = 2**(w-1)-1, +ampl is maximum and -ampl is minimim integer value
-- . freq = 1, fixed: one period in lookup table
-- . phi = 0, fixed: no phase offset
- function common_math_create_look_up_table_cos(N : positive; W : positive) return t_nat_integer_arr;
- function common_math_create_look_up_table_sin(N : positive; W : positive) return t_nat_integer_arr;
+ function common_math_create_look_up_table_cos (N : positive; W : positive) return t_nat_integer_arr;
+ function common_math_create_look_up_table_sin (N : positive; W : positive) return t_nat_integer_arr;
-- . idem but with option to invert the waveform (phi = pi rad) or not (phi = 0 rad)
- function common_math_create_look_up_table_cos(N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr;
- function common_math_create_look_up_table_sin(N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr;
+ function common_math_create_look_up_table_cos (N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr;
+ function common_math_create_look_up_table_sin (N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr;
-- Function to sum all values in the lookup table, to determine the DC value
- function common_math_sum_look_up_table(table : t_nat_integer_arr) return integer;
+ function common_math_sum_look_up_table (table : t_nat_integer_arr) return integer;
-- Function to concat Im & Re values in the lookup table, output = (hi << W) + lo
- function common_math_concat_look_up_table(table_hi, table_lo : t_nat_integer_arr; W : positive) return t_nat_integer_arr;
+ function common_math_concat_look_up_table (table_hi, table_lo : t_nat_integer_arr; W : positive) return t_nat_integer_arr;
-- Function to concat Im & Re values of phasor in the lookup table, output = (imag << W) + real
-- . N is number of samples in the lookup table, [0:N-1] = [0:N> = [0:2pi*FREQ>
@@ -77,10 +77,10 @@ package common_math_pkg is
-- Phasor: exp(j*angle) = cos(angle) + j*sin(angle)
-- A complex FFT of N points has N bins or channels: ch = -N/2:0:N/2-1.
-- To create an FFT input phasor with frequency in the middle of a channel use FREQ = ch.
- function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr;
- function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_slv_32_arr; -- range 0 TO N-1
+ function common_math_create_look_up_table_phasor (N, W : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr;
+ function common_math_create_look_up_table_phasor (N, W : positive; AMPL, FREQ, PHI : real) return t_slv_32_arr; -- range 0 TO N-1
- function common_math_create_random_arr(N, W : positive; seed : natural) return t_integer_arr;
+ function common_math_create_random_arr (N, W : positive; seed : natural) return t_integer_arr;
end common_math_pkg;
@@ -88,7 +88,7 @@ end common_math_pkg;
package body common_math_pkg is
- function common_math_create_look_up_table_cos(N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr is
+ function common_math_create_look_up_table_cos (N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr is
variable v_table : t_nat_integer_arr(N - 1 downto 0);
variable v_angle : real;
begin
@@ -100,12 +100,12 @@ package body common_math_pkg is
return v_table;
end;
- function common_math_create_look_up_table_cos(N : positive; W : positive) return t_nat_integer_arr is
+ function common_math_create_look_up_table_cos (N : positive; W : positive) return t_nat_integer_arr is
begin
return common_math_create_look_up_table_cos(N, real(2**(W - 1) - 1), 1.0, 0.0);
end;
- function common_math_create_look_up_table_cos(N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr is
+ function common_math_create_look_up_table_cos (N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr is
begin
if INVERT = false then
return common_math_create_look_up_table_cos(N, real(2**(W - 1) - 1), 1.0, 0.0);
@@ -114,7 +114,7 @@ package body common_math_pkg is
end if;
end;
- function common_math_create_look_up_table_sin(N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr is
+ function common_math_create_look_up_table_sin (N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr is
variable v_table : t_nat_integer_arr(N - 1 downto 0);
variable v_angle : real;
begin
@@ -126,13 +126,13 @@ package body common_math_pkg is
return v_table;
end;
- function common_math_create_look_up_table_sin(N : positive; W : positive) return t_nat_integer_arr is
+ function common_math_create_look_up_table_sin (N : positive; W : positive) return t_nat_integer_arr is
variable v_table : t_nat_integer_arr(N - 1 downto 0);
begin
return common_math_create_look_up_table_sin(N, real(2**(W - 1) - 1), 1.0, 0.0);
end;
- function common_math_create_look_up_table_sin(N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr is
+ function common_math_create_look_up_table_sin (N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr is
begin
if INVERT = false then
return common_math_create_look_up_table_sin(N, real(2**(W - 1) - 1), 1.0, 0.0);
@@ -141,7 +141,7 @@ package body common_math_pkg is
end if;
end;
- function common_math_sum_look_up_table(table : t_nat_integer_arr) return integer is
+ function common_math_sum_look_up_table (table : t_nat_integer_arr) return integer is
variable v_dc : integer := 0;
begin
for I in table'range loop
@@ -150,7 +150,7 @@ package body common_math_pkg is
return v_dc;
end;
- function common_math_concat_look_up_table(table_hi, table_lo : t_nat_integer_arr; W : positive) return t_nat_integer_arr is
+ function common_math_concat_look_up_table (table_hi, table_lo : t_nat_integer_arr; W : positive) return t_nat_integer_arr is
variable v_table : t_nat_integer_arr(table_hi'range);
variable v_hi : std_logic_vector(W - 1 downto 0);
variable v_lo : std_logic_vector(W - 1 downto 0);
@@ -164,7 +164,7 @@ package body common_math_pkg is
return v_table;
end;
- function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr is
+ function common_math_create_look_up_table_phasor (N, W : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr is
constant c_cos_arr : t_nat_integer_arr := common_math_create_look_up_table_cos(N, AMPL, FREQ, PHI);
constant c_sin_arr : t_nat_integer_arr := common_math_create_look_up_table_sin(N, AMPL, FREQ, PHI);
constant c_exp_arr : t_nat_integer_arr := common_math_concat_look_up_table(c_sin_arr, c_cos_arr, W);
@@ -172,7 +172,7 @@ package body common_math_pkg is
return c_exp_arr; -- Concatenated W bit sin imag part & W bit cos real part
end;
- function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_slv_32_arr is
+ function common_math_create_look_up_table_phasor (N, W : positive; AMPL, FREQ, PHI : real) return t_slv_32_arr is
constant c_exp_arr : t_nat_integer_arr := common_math_create_look_up_table_phasor(N, W, AMPL, FREQ, PHI);
variable v_exp_arr : t_slv_32_arr(0 to N - 1);
begin
@@ -182,7 +182,7 @@ package body common_math_pkg is
return v_exp_arr;
end;
- function common_math_create_random_arr(N, W : positive; seed : natural) return t_integer_arr is
+ function common_math_create_random_arr (N, W : positive; seed : natural) return t_integer_arr is
variable v_rand_arr : t_integer_arr(0 to N - 1);
variable v_random : std_logic_vector(W - 1 downto 0) := TO_UVEC(seed, W);
begin
diff --git a/libraries/base/common/src/vhdl/common_mem_demux.vhd b/libraries/base/common/src/vhdl/common_mem_demux.vhd
index 200a1d5620..b516da80a4 100644
--- a/libraries/base/common/src/vhdl/common_mem_demux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_demux.vhd
@@ -51,9 +51,9 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_mem_demux is
generic (
diff --git a/libraries/base/common/src/vhdl/common_mem_mux.vhd b/libraries/base/common/src/vhdl/common_mem_mux.vhd
index 59b667360e..6544ed6cee 100644
--- a/libraries/base/common/src/vhdl/common_mem_mux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_mux.vhd
@@ -58,9 +58,9 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_mem_mux is
generic (
diff --git a/libraries/base/common/src/vhdl/common_mem_pkg.vhd b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
index 728550b388..ff2c10ab88 100644
--- a/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
@@ -48,9 +48,9 @@
-- sufficient widths.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_mem_pkg is
@@ -91,24 +91,24 @@ package common_mem_pkg is
subtype t_mem_copi_arr is t_mem_mosi_arr;
-- Reset only the control fields of the MM record
- function RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) return t_mem_mosi; -- deprecated, use RESET_MEM_COPI_CTRL() instead
- function RESET_MEM_COPI_CTRL(copi : t_mem_copi) return t_mem_copi;
- function RESET_MEM_COPI_CTRL(copi_arr : t_mem_copi_arr) return t_mem_copi_arr;
+ function RESET_MEM_MOSI_CTRL (mosi : t_mem_mosi) return t_mem_mosi; -- deprecated, use RESET_MEM_COPI_CTRL() instead
+ function RESET_MEM_COPI_CTRL (copi : t_mem_copi) return t_mem_copi;
+ function RESET_MEM_COPI_CTRL (copi_arr : t_mem_copi_arr) return t_mem_copi_arr;
- function RESET_MEM_MISO_CTRL(miso : t_mem_miso) return t_mem_miso; -- deprecated, use RESET_MEM_CIPO_CTRL() instead
- function RESET_MEM_CIPO_CTRL(cipo : t_mem_cipo) return t_mem_cipo;
- function RESET_MEM_CIPO_CTRL(cipo_arr : t_mem_cipo_arr) return t_mem_cipo_arr;
+ function RESET_MEM_MISO_CTRL (miso : t_mem_miso) return t_mem_miso; -- deprecated, use RESET_MEM_CIPO_CTRL() instead
+ function RESET_MEM_CIPO_CTRL (cipo : t_mem_cipo) return t_mem_cipo;
+ function RESET_MEM_CIPO_CTRL (cipo_arr : t_mem_cipo_arr) return t_mem_cipo_arr;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
- function TO_MEM_ADDRESS(n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
- function TO_MEM_DATA( n : integer) return std_logic_vector; -- unsigned, alias of TO_MEM_DATA()
- function TO_MEM_UDATA( n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
- function TO_MEM_SDATA( n : integer) return std_logic_vector; -- sign extended
- function RESIZE_MEM_ADDRESS(vec : std_logic_vector) return std_logic_vector; -- unsigned
- function RESIZE_MEM_DATA( vec : std_logic_vector) return std_logic_vector; -- unsigned, alias of RESIZE_MEM_UDATA
- function RESIZE_MEM_UDATA( vec : std_logic_vector) return std_logic_vector; -- unsigned
- function RESIZE_MEM_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extended
- function RESIZE_MEM_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
+ function TO_MEM_ADDRESS (n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
+ function TO_MEM_DATA ( n : integer) return std_logic_vector; -- unsigned, alias of TO_MEM_DATA()
+ function TO_MEM_UDATA ( n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
+ function TO_MEM_SDATA ( n : integer) return std_logic_vector; -- sign extended
+ function RESIZE_MEM_ADDRESS (vec : std_logic_vector) return std_logic_vector; -- unsigned
+ function RESIZE_MEM_DATA ( vec : std_logic_vector) return std_logic_vector; -- unsigned, alias of RESIZE_MEM_UDATA
+ function RESIZE_MEM_UDATA ( vec : std_logic_vector) return std_logic_vector; -- unsigned
+ function RESIZE_MEM_SDATA ( vec : std_logic_vector) return std_logic_vector; -- sign extended
+ function RESIZE_MEM_XDATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
------------------------------------------------------------------------------
-- Procedures to access MM bus
@@ -119,16 +119,19 @@ package common_mem_pkg is
-- check and wait for mm_copi.waitrequest = '0' before removing the MM
-- access.
------------------------------------------------------------------------------
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_wr (
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_copi : out t_mem_copi);
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_wr (
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_copi : out t_mem_copi);
- procedure proc_mem_bus_rd(constant wr_addr : in natural;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_rd (
+ constant wr_addr : in natural;
+ signal mm_copi : out t_mem_copi);
------------------------------------------------------------------------------
-- Burst memory access (for DDR access interface)
@@ -167,13 +170,13 @@ package common_mem_pkg is
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_ctlr_miso or t_mem_ctlr_mosi field width
- function TO_MEM_CTLR_ADDRESS( n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
- function TO_MEM_CTLR_DATA( n : integer) return std_logic_vector; -- unsigned
- function TO_MEM_CTLR_BURSTSIZE(n : integer) return std_logic_vector; -- unsigned
+ function TO_MEM_CTLR_ADDRESS ( n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
+ function TO_MEM_CTLR_DATA ( n : integer) return std_logic_vector; -- unsigned
+ function TO_MEM_CTLR_BURSTSIZE (n : integer) return std_logic_vector; -- unsigned
- function RESIZE_MEM_CTLR_ADDRESS( vec : std_logic_vector) return std_logic_vector; -- unsigned
- function RESIZE_MEM_CTLR_DATA( vec : std_logic_vector) return std_logic_vector; -- unsigned
- function RESIZE_MEM_CTLR_BURSTSIZE(vec : std_logic_vector) return std_logic_vector; -- unsigned
+ function RESIZE_MEM_CTLR_ADDRESS ( vec : std_logic_vector) return std_logic_vector; -- unsigned
+ function RESIZE_MEM_CTLR_DATA ( vec : std_logic_vector) return std_logic_vector; -- unsigned
+ function RESIZE_MEM_CTLR_BURSTSIZE (vec : std_logic_vector) return std_logic_vector; -- unsigned
------------------------------------------------------------------------------
@@ -185,7 +188,7 @@ package common_mem_pkg is
dat_w : natural;
nof_dat : natural; -- optional, nof dat words <= 2**adr_w
init_sl : std_logic; -- optional, init all dat words to std_logic '0', '1' or 'X'
- --init_file : STRING; -- "UNUSED", unconstrained length can not be in record
+ --init_file : STRING; -- "UNUSED", unconstrained length can not be in record
end record;
constant c_mem_ram_rd_latency : natural := 2; -- note common_ram_crw_crw(stratix4) now also supports read latency 1
@@ -200,15 +203,15 @@ package common_mem_pkg is
------------------------------------------------------------------------------
-- Functions to swap endianess
------------------------------------------------------------------------------
- function func_mem_swap_endianess(mm : t_mem_miso; sz : natural) return t_mem_miso;
- function func_mem_swap_endianess(mm : t_mem_mosi; sz : natural) return t_mem_mosi;
+ function func_mem_swap_endianess (mm : t_mem_miso; sz : natural) return t_mem_miso;
+ function func_mem_swap_endianess (mm : t_mem_mosi; sz : natural) return t_mem_mosi;
end common_mem_pkg;
package body common_mem_pkg is
-- Reset only the control fields of the MM record
- function RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) return t_mem_mosi is
+ function RESET_MEM_MOSI_CTRL (mosi : t_mem_mosi) return t_mem_mosi is
variable v_mosi : t_mem_mosi := mosi;
begin
v_mosi.rd := '0';
@@ -216,12 +219,12 @@ package body common_mem_pkg is
return v_mosi;
end RESET_MEM_MOSI_CTRL;
- function RESET_MEM_COPI_CTRL(copi : t_mem_copi) return t_mem_copi is
+ function RESET_MEM_COPI_CTRL (copi : t_mem_copi) return t_mem_copi is
begin
return RESET_MEM_MOSI_CTRL(copi);
end;
- function RESET_MEM_COPI_CTRL(copi_arr : t_mem_copi_arr) return t_mem_copi_arr is
+ function RESET_MEM_COPI_CTRL (copi_arr : t_mem_copi_arr) return t_mem_copi_arr is
variable v_copi_arr : t_mem_copi_arr(copi_arr'range) := copi_arr;
begin
for I in copi_arr'range loop
@@ -230,7 +233,7 @@ package body common_mem_pkg is
return v_copi_arr;
end;
- function RESET_MEM_MISO_CTRL(miso : t_mem_miso) return t_mem_miso is
+ function RESET_MEM_MISO_CTRL (miso : t_mem_miso) return t_mem_miso is
variable v_miso : t_mem_miso := miso;
begin
v_miso.rdval := '0';
@@ -238,12 +241,12 @@ package body common_mem_pkg is
return v_miso;
end RESET_MEM_MISO_CTRL;
- function RESET_MEM_CIPO_CTRL(cipo : t_mem_cipo) return t_mem_cipo is
+ function RESET_MEM_CIPO_CTRL (cipo : t_mem_cipo) return t_mem_cipo is
begin
return RESET_MEM_MISO_CTRL(cipo);
end RESET_MEM_CIPO_CTRL;
- function RESET_MEM_CIPO_CTRL(cipo_arr : t_mem_cipo_arr) return t_mem_cipo_arr is
+ function RESET_MEM_CIPO_CTRL (cipo_arr : t_mem_cipo_arr) return t_mem_cipo_arr is
variable v_cipo_arr : t_mem_cipo_arr(cipo_arr'range) := cipo_arr;
begin
for I in cipo_arr'range loop
@@ -253,47 +256,47 @@ package body common_mem_pkg is
end RESET_MEM_CIPO_CTRL;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
- function TO_MEM_ADDRESS(n : integer) return std_logic_vector is
+ function TO_MEM_ADDRESS (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_mem_address_w);
end TO_MEM_ADDRESS;
- function TO_MEM_DATA(n : integer) return std_logic_vector is
+ function TO_MEM_DATA (n : integer) return std_logic_vector is
begin
return TO_MEM_UDATA(n);
end TO_MEM_DATA;
- function TO_MEM_UDATA(n : integer) return std_logic_vector is
+ function TO_MEM_UDATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_mem_data_w);
end TO_MEM_UDATA;
- function TO_MEM_SDATA(n : integer) return std_logic_vector is
+ function TO_MEM_SDATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_mem_data_w);
end TO_MEM_SDATA;
- function RESIZE_MEM_ADDRESS(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_MEM_ADDRESS (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_mem_address_w);
end RESIZE_MEM_ADDRESS;
- function RESIZE_MEM_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_MEM_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_MEM_UDATA(vec);
end RESIZE_MEM_DATA;
- function RESIZE_MEM_UDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_MEM_UDATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_mem_data_w);
end RESIZE_MEM_UDATA;
- function RESIZE_MEM_SDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_MEM_SDATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_mem_data_w);
end RESIZE_MEM_SDATA;
- function RESIZE_MEM_XDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_MEM_XDATA (vec : std_logic_vector) return std_logic_vector is
variable v_vec : std_logic_vector(c_mem_data_w - 1 downto 0) := (others => 'X');
begin
v_vec(vec'length - 1 downto 0) := vec;
@@ -301,65 +304,68 @@ package body common_mem_pkg is
end RESIZE_MEM_XDATA;
-- Procedures to access MM bus
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_wr (
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.wrdata <= TO_MEM_DATA(wr_data);
mm_copi.wr <= '1';
end proc_mem_bus_wr;
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_wr (
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.wrdata <= RESIZE_MEM_DATA(wr_data);
mm_copi.wr <= '1';
end proc_mem_bus_wr;
- procedure proc_mem_bus_rd(constant wr_addr : in natural;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_rd (
+ constant wr_addr : in natural;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.rd <= '1';
end proc_mem_bus_rd;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
- function TO_MEM_CTLR_ADDRESS(n : integer) return std_logic_vector is
+ function TO_MEM_CTLR_ADDRESS (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_mem_ctlr_address_w);
end TO_MEM_CTLR_ADDRESS;
- function TO_MEM_CTLR_DATA(n : integer) return std_logic_vector is
+ function TO_MEM_CTLR_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_mem_ctlr_data_w);
end TO_MEM_CTLR_DATA;
- function TO_MEM_CTLR_BURSTSIZE(n : integer) return std_logic_vector is
+ function TO_MEM_CTLR_BURSTSIZE (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_mem_ctlr_burstsize_w);
end TO_MEM_CTLR_BURSTSIZE;
- function RESIZE_MEM_CTLR_ADDRESS(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_MEM_CTLR_ADDRESS (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_mem_ctlr_address_w);
end RESIZE_MEM_CTLR_ADDRESS;
- function RESIZE_MEM_CTLR_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_MEM_CTLR_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_mem_ctlr_data_w);
end RESIZE_MEM_CTLR_DATA;
- function RESIZE_MEM_CTLR_BURSTSIZE(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_MEM_CTLR_BURSTSIZE (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_mem_ctlr_burstsize_w);
end RESIZE_MEM_CTLR_BURSTSIZE;
-- Functions to swap endianess
- function func_mem_swap_endianess(mm : t_mem_miso; sz : natural) return t_mem_miso is
+ function func_mem_swap_endianess (mm : t_mem_miso; sz : natural) return t_mem_miso is
variable v_mm : t_mem_miso;
begin
-- Master In Slave Out
@@ -367,7 +373,7 @@ package body common_mem_pkg is
return v_mm;
end func_mem_swap_endianess;
- function func_mem_swap_endianess(mm : t_mem_mosi; sz : natural) return t_mem_mosi is
+ function func_mem_swap_endianess (mm : t_mem_mosi; sz : natural) return t_mem_mosi is
variable v_mm : t_mem_mosi;
begin
-- Master Out Slave In
diff --git a/libraries/base/common/src/vhdl/common_multiplexer.vhd b/libraries/base/common/src/vhdl/common_multiplexer.vhd
index 5dd92bd24a..adb528945d 100644
--- a/libraries/base/common/src/vhdl/common_multiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_multiplexer.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Assign one of g_nof_in input streams to the output based on in_sel input
-- Description: The input streams are concatenated into one SLV.
@@ -33,7 +33,7 @@ entity common_multiplexer is
g_pipeline_out : natural := 0;
g_nof_in : natural;
g_dat_w : natural
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -52,24 +52,24 @@ architecture str of common_multiplexer is
begin
u_select_symbol : entity work.common_select_symbol
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_nof_symbols => g_nof_in,
- g_symbol_w => g_dat_w,
- g_sel_w => ceil_log2(g_nof_in)
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_nof_symbols => g_nof_in,
+ g_symbol_w => g_dat_w,
+ g_sel_w => ceil_log2(g_nof_in)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_data => in_dat,
- in_val => in_val,
+ in_data => in_dat,
+ in_val => in_val,
- in_sel => in_sel,
+ in_sel => in_sel,
- out_symbol => out_dat,
- out_val => out_val
- );
+ out_symbol => out_dat,
+ out_val => out_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
index 520d585be9..49ef37b8a4 100644
--- a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
@@ -23,10 +23,10 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_field_pkg.all;
package common_network_layers_pkg is
@@ -91,9 +91,11 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -140,13 +142,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
c_network_ip_identification_len + c_network_ip_flags_fragment_len +
c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
c_network_ip_addr_len +
c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -180,11 +182,20 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001",
+ "0001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "001",
+ "0000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ARP Packet
@@ -221,12 +232,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len +
c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -252,12 +263,17 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001",
+ "0000000000000001",
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001"
+ );
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -306,8 +322,13 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001",
+ "00000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
------------------------------------------------------------------------------
-- UDP Packet
@@ -332,7 +353,7 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
@@ -353,10 +374,14 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001",
+ "0000000000000001"
+ );
- function func_network_ip_header_checksum(field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector;
+ function func_network_ip_header_checksum (field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector;
end common_network_layers_pkg;
@@ -364,7 +389,7 @@ end common_network_layers_pkg;
package body common_network_layers_pkg is
- function func_network_ip_header_checksum(field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector is
+ function func_network_ip_header_checksum (field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector is
-- function to calculate the ip header checksum based on a header field array.
constant c_cin_w : natural := 4; -- bit width of carry
constant c_nof_halfword : natural := (c_network_ip_header_len / c_halfword_sz) - 1; -- -1 as we exclude the checksum field itself for calculation.
@@ -374,15 +399,15 @@ package body common_network_layers_pkg is
variable vec : std_logic_vector(c_halfword_w * c_nof_halfword - 1 downto 0);
begin
-- vec = whole ip header excluding ip_header_checksum.
- vec :=
- hdr_fields_slv(field_hi(field_arr, "ip_version" ) downto field_lo(field_arr, "ip_protocol" ))
- & hdr_fields_slv(field_hi(field_arr, "ip_src_addr" ) downto field_lo(field_arr, "ip_dst_addr" ));
+ vec :=
+ hdr_fields_slv(field_hi(field_arr, "ip_version" ) downto field_lo(field_arr, "ip_protocol" ))
+ & hdr_fields_slv(field_hi(field_arr, "ip_src_addr" ) downto field_lo(field_arr, "ip_dst_addr" ));
-- sum up vec in halfwords
for i in 0 to c_nof_halfword - 1 loop
sum := sum + unsigned(vec(( i + 1 ) * c_halfword_w - 1 downto i * c_halfword_w));
- end loop;
-
+ end loop;
+
-- checksum = inverted (sum + carry)
crc := not(std_logic_vector(sum(c_halfword_w - 1 downto 0) + sum(sum'high downto c_halfword_w)));
return crc;
diff --git a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
index fde102c9ec..2960b82b3c 100644
--- a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
@@ -50,10 +50,10 @@
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_network_layers_pkg.all;
package common_network_total_header_pkg is
@@ -76,11 +76,13 @@ package common_network_total_header_pkg is
udp : t_network_udp_header;
end record;
- constant c_network_total_header_ones : t_network_total_header := (c_network_eth_header_ones,
- c_network_arp_packet_ones,
- c_network_ip_header_ones,
- c_network_icmp_header_ones,
- c_network_udp_header_ones);
+ constant c_network_total_header_ones : t_network_total_header := (
+ c_network_eth_header_ones,
+ c_network_arp_packet_ones,
+ c_network_ip_header_ones,
+ c_network_icmp_header_ones,
+ c_network_udp_header_ones
+ );
-----------------------------------------------------------------------------
-- Map total network header in words array
@@ -212,72 +214,76 @@ package common_network_total_header_pkg is
-----------------------------------------------------------------------------
-- Combinatorial map of the total header array on to a network header record (type casting an array to a record is not possible, so therefore we need these functions)
- function func_network_total_header_extract_eth( hdr_arr : t_network_total_header_32b_arr) return t_network_eth_header;
- function func_network_total_header_extract_eth( hdr_arr : t_network_total_header_64b_arr) return t_network_eth_header;
- function func_network_total_header_extract_ip( hdr_arr : t_network_total_header_32b_arr) return t_network_ip_header;
- function func_network_total_header_extract_ip( hdr_arr : t_network_total_header_64b_arr) return t_network_ip_header;
- function func_network_total_header_extract_arp( hdr_arr : t_network_total_header_32b_arr) return t_network_arp_packet;
- function func_network_total_header_extract_arp( hdr_arr : t_network_total_header_64b_arr) return t_network_arp_packet;
- function func_network_total_header_extract_icmp(hdr_arr : t_network_total_header_32b_arr) return t_network_icmp_header;
- function func_network_total_header_extract_icmp(hdr_arr : t_network_total_header_64b_arr) return t_network_icmp_header;
- function func_network_total_header_extract_udp( hdr_arr : t_network_total_header_32b_arr) return t_network_udp_header;
- function func_network_total_header_extract_udp( hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header;
+ function func_network_total_header_extract_eth ( hdr_arr : t_network_total_header_32b_arr) return t_network_eth_header;
+ function func_network_total_header_extract_eth ( hdr_arr : t_network_total_header_64b_arr) return t_network_eth_header;
+ function func_network_total_header_extract_ip ( hdr_arr : t_network_total_header_32b_arr) return t_network_ip_header;
+ function func_network_total_header_extract_ip ( hdr_arr : t_network_total_header_64b_arr) return t_network_ip_header;
+ function func_network_total_header_extract_arp ( hdr_arr : t_network_total_header_32b_arr) return t_network_arp_packet;
+ function func_network_total_header_extract_arp ( hdr_arr : t_network_total_header_64b_arr) return t_network_arp_packet;
+ function func_network_total_header_extract_icmp (hdr_arr : t_network_total_header_32b_arr) return t_network_icmp_header;
+ function func_network_total_header_extract_icmp (hdr_arr : t_network_total_header_64b_arr) return t_network_icmp_header;
+ function func_network_total_header_extract_udp ( hdr_arr : t_network_total_header_32b_arr) return t_network_udp_header;
+ function func_network_total_header_extract_udp ( hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header;
-- Combinatorial map just as above but for network packets without word align field.
- function func_network_total_header_no_align_extract_eth( hdr_arr : t_network_total_header_32b_arr) return t_network_eth_header;
- function func_network_total_header_no_align_extract_eth( hdr_arr : t_network_total_header_64b_arr) return t_network_eth_header;
- function func_network_total_header_no_align_extract_ip( hdr_arr : t_network_total_header_32b_arr) return t_network_ip_header;
- function func_network_total_header_no_align_extract_ip( hdr_arr : t_network_total_header_64b_arr) return t_network_ip_header;
- function func_network_total_header_no_align_extract_arp( hdr_arr : t_network_total_header_32b_arr) return t_network_arp_packet;
- function func_network_total_header_no_align_extract_arp( hdr_arr : t_network_total_header_64b_arr) return t_network_arp_packet;
- function func_network_total_header_no_align_extract_icmp(hdr_arr : t_network_total_header_32b_arr) return t_network_icmp_header;
- function func_network_total_header_no_align_extract_icmp(hdr_arr : t_network_total_header_64b_arr) return t_network_icmp_header;
- function func_network_total_header_no_align_extract_udp( hdr_arr : t_network_total_header_32b_arr) return t_network_udp_header;
- function func_network_total_header_no_align_extract_udp( hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header;
+ function func_network_total_header_no_align_extract_eth ( hdr_arr : t_network_total_header_32b_arr) return t_network_eth_header;
+ function func_network_total_header_no_align_extract_eth ( hdr_arr : t_network_total_header_64b_arr) return t_network_eth_header;
+ function func_network_total_header_no_align_extract_ip ( hdr_arr : t_network_total_header_32b_arr) return t_network_ip_header;
+ function func_network_total_header_no_align_extract_ip ( hdr_arr : t_network_total_header_64b_arr) return t_network_ip_header;
+ function func_network_total_header_no_align_extract_arp ( hdr_arr : t_network_total_header_32b_arr) return t_network_arp_packet;
+ function func_network_total_header_no_align_extract_arp ( hdr_arr : t_network_total_header_64b_arr) return t_network_arp_packet;
+ function func_network_total_header_no_align_extract_icmp (hdr_arr : t_network_total_header_32b_arr) return t_network_icmp_header;
+ function func_network_total_header_no_align_extract_icmp (hdr_arr : t_network_total_header_64b_arr) return t_network_icmp_header;
+ function func_network_total_header_no_align_extract_udp ( hdr_arr : t_network_total_header_32b_arr) return t_network_udp_header;
+ function func_network_total_header_no_align_extract_udp ( hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header;
-- Construct the total header array from the individual header records
- function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_32b_arr; -- sets unused words to zero
- function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_64b_arr; -- sets unused words to zero
- function func_network_total_header_construct_arp( eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_32b_arr;
- function func_network_total_header_construct_arp( eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_64b_arr;
- function func_network_total_header_construct_ip( eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_32b_arr; -- sets unused words to zero
- function func_network_total_header_construct_ip( eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_64b_arr; -- sets unused words to zero
- function func_network_total_header_construct_icmp(eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_32b_arr;
- function func_network_total_header_construct_icmp(eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_64b_arr;
- function func_network_total_header_construct_udp( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_32b_arr;
- function func_network_total_header_construct_udp( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_64b_arr;
+ function func_network_total_header_construct_eth ( eth : t_network_eth_header) return t_network_total_header_32b_arr; -- sets unused words to zero
+ function func_network_total_header_construct_eth ( eth : t_network_eth_header) return t_network_total_header_64b_arr; -- sets unused words to zero
+ function func_network_total_header_construct_arp ( eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_32b_arr;
+ function func_network_total_header_construct_arp ( eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_64b_arr;
+ function func_network_total_header_construct_ip ( eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_32b_arr; -- sets unused words to zero
+ function func_network_total_header_construct_ip ( eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_64b_arr; -- sets unused words to zero
+ function func_network_total_header_construct_icmp (eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_32b_arr;
+ function func_network_total_header_construct_icmp (eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_64b_arr;
+ function func_network_total_header_construct_udp ( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_32b_arr;
+ function func_network_total_header_construct_udp ( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_64b_arr;
-- Construct the response total header array for a total header array
- function func_network_total_header_response_eth( eth_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
- function func_network_total_header_response_eth( eth_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_response_arp( arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ function func_network_total_header_response_eth ( eth_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
+ function func_network_total_header_response_eth ( eth_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
+ function func_network_total_header_response_arp (
+ arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
return t_network_total_header_32b_arr;
- function func_network_total_header_response_arp( arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ function func_network_total_header_response_arp (
+ arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
return t_network_total_header_64b_arr;
- function func_network_total_header_response_ip( ip_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
- function func_network_total_header_response_ip( ip_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
- function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_response_udp( udp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
- function func_network_total_header_response_udp( udp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
+ function func_network_total_header_response_ip ( ip_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
+ function func_network_total_header_response_ip ( ip_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
+ function func_network_total_header_response_icmp (icmp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
+ function func_network_total_header_response_icmp (icmp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
+ function func_network_total_header_response_udp ( udp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
+ function func_network_total_header_response_udp ( udp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
-- Construct the response total header array for a total header array without alignment bytes
- function func_network_total_header_no_align_response_eth( eth_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
- function func_network_total_header_no_align_response_eth( eth_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_no_align_response_arp( arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ function func_network_total_header_no_align_response_eth ( eth_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
+ function func_network_total_header_no_align_response_eth ( eth_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
+ function func_network_total_header_no_align_response_arp (
+ arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
return t_network_total_header_32b_arr;
- function func_network_total_header_no_align_response_arp( arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ function func_network_total_header_no_align_response_arp (
+ arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
return t_network_total_header_64b_arr;
- function func_network_total_header_no_align_response_ip( ip_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
- function func_network_total_header_no_align_response_ip( ip_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
- function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_no_align_response_udp( udp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
- function func_network_total_header_no_align_response_udp( udp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
+ function func_network_total_header_no_align_response_ip ( ip_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
+ function func_network_total_header_no_align_response_ip ( ip_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
+ function func_network_total_header_no_align_response_icmp (icmp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
+ function func_network_total_header_no_align_response_icmp (icmp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
+ function func_network_total_header_no_align_response_udp ( udp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
+ function func_network_total_header_no_align_response_udp ( udp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
@@ -290,7 +296,7 @@ package body common_network_total_header_pkg is
-- Assume the total header has been padded with the word align field to have the udp payload at a 32b or 64b boundary
-- Map the 11 32b words or 6 64b longwords from the total header to the header field records
- function func_network_total_header_extract_eth(hdr_arr : t_network_total_header_32b_arr) return t_network_eth_header is
+ function func_network_total_header_extract_eth (hdr_arr : t_network_total_header_32b_arr) return t_network_eth_header is
variable v_hdr : t_network_eth_header;
begin
-- hdr_arr(0)(31 DOWNTO 16) -- ignore word align field
@@ -302,7 +308,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_extract_eth(hdr_arr : t_network_total_header_64b_arr) return t_network_eth_header is
+ function func_network_total_header_extract_eth (hdr_arr : t_network_total_header_64b_arr) return t_network_eth_header is
variable v_hdr : t_network_eth_header;
begin
-- hdr_arr(0)(63 DOWNTO 16) -- ignore word align field
@@ -314,7 +320,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_extract_ip(hdr_arr : t_network_total_header_32b_arr) return t_network_ip_header is
+ function func_network_total_header_extract_ip (hdr_arr : t_network_total_header_32b_arr) return t_network_ip_header is
variable v_hdr : t_network_ip_header;
begin
v_hdr.version := hdr_arr(4)(31 downto 28);
@@ -332,7 +338,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_extract_ip(hdr_arr : t_network_total_header_64b_arr) return t_network_ip_header is
+ function func_network_total_header_extract_ip (hdr_arr : t_network_total_header_64b_arr) return t_network_ip_header is
variable v_hdr : t_network_ip_header;
begin
v_hdr.version := hdr_arr(2)(31 downto 28);
@@ -350,7 +356,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_extract_arp(hdr_arr : t_network_total_header_32b_arr) return t_network_arp_packet is
+ function func_network_total_header_extract_arp (hdr_arr : t_network_total_header_32b_arr) return t_network_arp_packet is
variable v_arp : t_network_arp_packet;
begin
v_arp.htype := hdr_arr(4)(31 downto 16);
@@ -368,7 +374,7 @@ package body common_network_total_header_pkg is
return v_arp;
end;
- function func_network_total_header_extract_arp(hdr_arr : t_network_total_header_64b_arr) return t_network_arp_packet is
+ function func_network_total_header_extract_arp (hdr_arr : t_network_total_header_64b_arr) return t_network_arp_packet is
variable v_arp : t_network_arp_packet;
begin
v_arp.htype := hdr_arr(2)(31 downto 16);
@@ -386,7 +392,7 @@ package body common_network_total_header_pkg is
return v_arp;
end;
- function func_network_total_header_extract_icmp(hdr_arr : t_network_total_header_32b_arr) return t_network_icmp_header is
+ function func_network_total_header_extract_icmp (hdr_arr : t_network_total_header_32b_arr) return t_network_icmp_header is
variable v_hdr : t_network_icmp_header;
begin
v_hdr.msg_type := hdr_arr(9)(31 downto 24);
@@ -397,7 +403,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_extract_icmp(hdr_arr : t_network_total_header_64b_arr) return t_network_icmp_header is
+ function func_network_total_header_extract_icmp (hdr_arr : t_network_total_header_64b_arr) return t_network_icmp_header is
variable v_hdr : t_network_icmp_header;
begin
v_hdr.msg_type := hdr_arr(5)(63 downto 56);
@@ -408,7 +414,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_extract_udp(hdr_arr : t_network_total_header_32b_arr) return t_network_udp_header is
+ function func_network_total_header_extract_udp (hdr_arr : t_network_total_header_32b_arr) return t_network_udp_header is
variable v_hdr : t_network_udp_header;
begin
v_hdr.src_port := hdr_arr(9)(31 downto 16);
@@ -418,7 +424,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_extract_udp(hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header is
+ function func_network_total_header_extract_udp (hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header is
variable v_hdr : t_network_udp_header;
begin
v_hdr.src_port := hdr_arr(5)(63 downto 48);
@@ -431,7 +437,7 @@ package body common_network_total_header_pkg is
-- Assume the total header has NOT been padded with the word align field
-- Map the 11 32b words or 6 64b longwords from the total header to the header field records
- function func_network_total_header_no_align_extract_eth(hdr_arr : t_network_total_header_32b_arr) return t_network_eth_header is
+ function func_network_total_header_no_align_extract_eth (hdr_arr : t_network_total_header_32b_arr) return t_network_eth_header is
variable v_hdr : t_network_eth_header;
begin
v_hdr.dst_mac(47 downto 16) := hdr_arr(0);
@@ -442,7 +448,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_no_align_extract_eth(hdr_arr : t_network_total_header_64b_arr) return t_network_eth_header is
+ function func_network_total_header_no_align_extract_eth (hdr_arr : t_network_total_header_64b_arr) return t_network_eth_header is
variable v_hdr : t_network_eth_header;
begin
v_hdr.dst_mac := hdr_arr(0)(63 downto 16);
@@ -452,7 +458,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_no_align_extract_ip(hdr_arr : t_network_total_header_32b_arr) return t_network_ip_header is
+ function func_network_total_header_no_align_extract_ip (hdr_arr : t_network_total_header_32b_arr) return t_network_ip_header is
variable v_hdr : t_network_ip_header;
begin
v_hdr.version := hdr_arr(3)(15 downto 12);
@@ -472,7 +478,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_no_align_extract_ip(hdr_arr : t_network_total_header_64b_arr) return t_network_ip_header is
+ function func_network_total_header_no_align_extract_ip (hdr_arr : t_network_total_header_64b_arr) return t_network_ip_header is
variable v_hdr : t_network_ip_header;
begin
v_hdr.version := hdr_arr(1)(15 downto 12);
@@ -491,7 +497,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_no_align_extract_arp(hdr_arr : t_network_total_header_32b_arr) return t_network_arp_packet is
+ function func_network_total_header_no_align_extract_arp (hdr_arr : t_network_total_header_32b_arr) return t_network_arp_packet is
variable v_arp : t_network_arp_packet;
begin
v_arp.htype := hdr_arr(3)(15 downto 0);
@@ -509,7 +515,7 @@ package body common_network_total_header_pkg is
return v_arp;
end;
- function func_network_total_header_no_align_extract_arp(hdr_arr : t_network_total_header_64b_arr) return t_network_arp_packet is
+ function func_network_total_header_no_align_extract_arp (hdr_arr : t_network_total_header_64b_arr) return t_network_arp_packet is
variable v_arp : t_network_arp_packet;
begin
v_arp.htype := hdr_arr(1)(15 downto 0);
@@ -526,7 +532,7 @@ package body common_network_total_header_pkg is
return v_arp;
end;
- function func_network_total_header_no_align_extract_icmp(hdr_arr : t_network_total_header_32b_arr) return t_network_icmp_header is
+ function func_network_total_header_no_align_extract_icmp (hdr_arr : t_network_total_header_32b_arr) return t_network_icmp_header is
variable v_hdr : t_network_icmp_header;
begin
v_hdr.msg_type := hdr_arr(8)(15 downto 8);
@@ -537,7 +543,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_no_align_extract_icmp(hdr_arr : t_network_total_header_64b_arr) return t_network_icmp_header is
+ function func_network_total_header_no_align_extract_icmp (hdr_arr : t_network_total_header_64b_arr) return t_network_icmp_header is
variable v_hdr : t_network_icmp_header;
begin
v_hdr.msg_type := hdr_arr(4)(47 downto 40);
@@ -548,7 +554,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_no_align_extract_udp(hdr_arr : t_network_total_header_32b_arr) return t_network_udp_header is
+ function func_network_total_header_no_align_extract_udp (hdr_arr : t_network_total_header_32b_arr) return t_network_udp_header is
variable v_hdr : t_network_udp_header;
begin
v_hdr.src_port := hdr_arr(8)(15 downto 0);
@@ -558,7 +564,7 @@ package body common_network_total_header_pkg is
return v_hdr;
end;
- function func_network_total_header_no_align_extract_udp(hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header is
+ function func_network_total_header_no_align_extract_udp (hdr_arr : t_network_total_header_64b_arr) return t_network_udp_header is
variable v_hdr : t_network_udp_header;
begin
v_hdr.src_port := hdr_arr(4)(47 downto 32);
@@ -569,7 +575,7 @@ package body common_network_total_header_pkg is
end;
-- Construct the total header array from the individual header records
- function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_32b_arr is
+ function func_network_total_header_construct_eth ( eth : t_network_eth_header) return t_network_total_header_32b_arr is
variable v_total : t_network_total_header_32b_arr := (others => (others => '0'));
begin
v_total(0)(31 downto 16) := (others => '0'); -- force word align to zero
@@ -581,7 +587,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_eth( eth : t_network_eth_header) return t_network_total_header_64b_arr is
+ function func_network_total_header_construct_eth ( eth : t_network_eth_header) return t_network_total_header_64b_arr is
variable v_total : t_network_total_header_64b_arr := (others => (others => '0'));
begin
v_total(0)(63 downto 16) := (others => '0'); -- force word align to zero
@@ -593,7 +599,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_arp(eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_32b_arr is
+ function func_network_total_header_construct_arp (eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_32b_arr is
variable v_total : t_network_total_header_32b_arr;
begin
v_total := func_network_total_header_construct_eth(eth);
@@ -613,7 +619,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_arp(eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_64b_arr is
+ function func_network_total_header_construct_arp (eth : t_network_eth_header; arp : t_network_arp_packet) return t_network_total_header_64b_arr is
variable v_total : t_network_total_header_64b_arr;
begin
v_total := func_network_total_header_construct_eth(eth);
@@ -632,7 +638,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_ip(eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_32b_arr is
+ function func_network_total_header_construct_ip (eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_32b_arr is
variable v_total : t_network_total_header_32b_arr := (others => (others => '0'));
begin
v_total := func_network_total_header_construct_eth(eth);
@@ -652,7 +658,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_ip(eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_64b_arr is
+ function func_network_total_header_construct_ip (eth : t_network_eth_header; ip : t_network_ip_header) return t_network_total_header_64b_arr is
variable v_total : t_network_total_header_64b_arr := (others => (others => '0'));
begin
v_total := func_network_total_header_construct_eth(eth);
@@ -672,7 +678,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_icmp(eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_32b_arr is
+ function func_network_total_header_construct_icmp (eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_32b_arr is
variable v_total : t_network_total_header_32b_arr;
begin
v_total := func_network_total_header_construct_ip(eth, ip);
@@ -685,7 +691,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_icmp(eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_64b_arr is
+ function func_network_total_header_construct_icmp (eth : t_network_eth_header; ip : t_network_ip_header; icmp : t_network_icmp_header) return t_network_total_header_64b_arr is
variable v_total : t_network_total_header_64b_arr;
begin
v_total := func_network_total_header_construct_ip(eth, ip);
@@ -698,7 +704,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_udp( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_32b_arr is
+ function func_network_total_header_construct_udp ( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_32b_arr is
variable v_total : t_network_total_header_32b_arr;
begin
v_total := func_network_total_header_construct_ip(eth, ip);
@@ -710,7 +716,7 @@ package body common_network_total_header_pkg is
return v_total;
end;
- function func_network_total_header_construct_udp( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_64b_arr is
+ function func_network_total_header_construct_udp ( eth : t_network_eth_header; ip : t_network_ip_header; udp : t_network_udp_header) return t_network_total_header_64b_arr is
variable v_total : t_network_total_header_64b_arr;
begin
v_total := func_network_total_header_construct_ip(eth, ip);
@@ -723,8 +729,9 @@ package body common_network_total_header_pkg is
end;
-- Construct the response headers
- function func_network_total_header_response_eth(eth_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_eth (
+ eth_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- Default
@@ -739,8 +746,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_eth(eth_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_eth (
+ eth_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- Default
@@ -755,9 +763,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_arp(arp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_arp (
+ arp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -779,9 +788,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_arp(arp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_arp (
+ arp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -802,8 +812,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_ip(ip_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_ip (
+ ip_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -817,8 +828,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_ip(ip_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_ip (
+ ip_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -832,8 +844,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_icmp (
+ icmp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -845,8 +858,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_icmp (
+ icmp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -858,8 +872,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_udp(udp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_udp (
+ udp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -871,8 +886,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_udp(udp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_udp (
+ udp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -887,8 +903,9 @@ package body common_network_total_header_pkg is
-- Construct the response headers for headers without word align padding
- function func_network_total_header_no_align_response_eth(eth_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_eth (
+ eth_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- Default
@@ -903,8 +920,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_eth(eth_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_eth (
+ eth_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- Default
@@ -918,9 +936,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_arp(arp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_arp (
+ arp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -942,9 +961,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_arp(arp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_arp (
+ arp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -965,8 +985,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_ip(ip_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_ip (
+ ip_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -982,8 +1003,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_ip(ip_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_ip (
+ ip_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -998,8 +1020,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_icmp (
+ icmp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -1011,8 +1034,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_icmp (
+ icmp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -1024,8 +1048,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_udp(udp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_udp (
+ udp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -1037,8 +1062,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_udp(udp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_udp (
+ udp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
diff --git a/libraries/base/common/src/vhdl/common_operation.vhd b/libraries/base/common/src/vhdl/common_operation.vhd
index 7eb620884e..c60796b3b9 100644
--- a/libraries/base/common/src/vhdl/common_operation.vhd
+++ b/libraries/base/common/src/vhdl/common_operation.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity common_operation is
generic (
@@ -46,7 +46,7 @@ end common_operation;
architecture rtl of common_operation is
- function func_default(operation, representation : string; w : natural) return std_logic_vector is
+ function func_default (operation, representation : string; w : natural) return std_logic_vector is
constant c_smin : std_logic_vector(w - 1 downto 0) := '1' & c_slv0(w - 2 downto 0);
constant c_umin : std_logic_vector(w - 1 downto 0) := c_slv0(w - 1 downto 0);
constant c_smax : std_logic_vector(w - 1 downto 0) := '0' & c_slv1(w - 2 downto 0);
@@ -64,7 +64,7 @@ architecture rtl of common_operation is
return c_umin; -- void return statement to avoid compiler warning on missing return
end;
- function func_operation(operation, representation : string; a, b : std_logic_vector) return std_logic_vector is
+ function func_operation (operation, representation : string; a, b : std_logic_vector) return std_logic_vector is
begin
if representation = "SIGNED" then
if operation = "MIN" then if signed(a) < signed(b) then return a; else return b; end if; end if;
@@ -107,17 +107,17 @@ begin
nxt_result <= func_operation(g_operation, g_representation, a, b);
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => nxt_result,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => nxt_result,
+ out_dat => result
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_operation_tree.vhd b/libraries/base/common/src/vhdl/common_operation_tree.vhd
index ffdac00b13..bf65909c55 100644
--- a/libraries/base/common/src/vhdl/common_operation_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_operation_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Parallel operation tree.
-- Description:
@@ -86,22 +86,22 @@ begin
gen_stage : for j in 0 to c_nof_stages - 1 generate
gen_oper : for i in 0 to (c_N + (2**j) - 1) / (2**(j + 1)) - 1 generate
u_operj : entity work.common_operation
- generic map (
- g_operation => g_operation,
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
- g_dat_w => c_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => stage_arr(j - 1)((2 * i + 1) * c_w - 1 downto (2 * i + 0) * c_w),
- in_b => stage_arr(j - 1)((2 * i + 2) * c_w - 1 downto (2 * i + 1) * c_w),
- in_en_a => sl(stage_en_arr(j - 1)(2 * i downto 2 * i )),
- in_en_b => sl(stage_en_arr(j - 1)(2 * i + 1 downto 2 * i + 1)),
- result => stage_arr(j)((i + 1) * c_w - 1 downto i * c_w)
- );
+ generic map (
+ g_operation => g_operation,
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
+ g_dat_w => c_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => stage_arr(j - 1)((2 * i + 1) * c_w - 1 downto (2 * i + 0) * c_w),
+ in_b => stage_arr(j - 1)((2 * i + 2) * c_w - 1 downto (2 * i + 1) * c_w),
+ in_en_a => sl(stage_en_arr(j - 1)(2 * i downto 2 * i )),
+ in_en_b => sl(stage_en_arr(j - 1)(2 * i + 1 downto 2 * i + 1)),
+ result => stage_arr(j)((i + 1) * c_w - 1 downto i * c_w)
+ );
-- In case two adjacent inputs are disbaled, the result of their operation should be disabled in the next stage as well.
-- Therfor a logic OR creates the stage_en vector for the next stage.
@@ -116,20 +116,20 @@ begin
stage_en_arr(j)(c_N / (2**(j + 1))) <= in_en_vec(g_nof_inputs - 1);
u_pipej : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
- g_in_dat_w => c_w,
- g_out_dat_w => c_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => stage_arr(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * c_w - 1 downto
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
+ g_in_dat_w => c_w,
+ g_out_dat_w => c_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => stage_arr(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * c_w - 1 downto
(2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 0) * c_w),
- out_dat => stage_arr(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * c_w - 1 downto
+ out_dat => stage_arr(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * c_w - 1 downto
((c_N + (2**j) - 1) / (2**(j + 1)) ) * c_w)
- );
+ );
end generate;
end generate;
@@ -138,18 +138,18 @@ begin
no_tree : if g_nof_inputs = 1 generate
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_data_vec,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_data_vec,
+ out_dat => result
+ );
end generate; -- no_tree
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index a8b67ad0fd..520fdd590a 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -35,12 +35,12 @@
-- . The "use_adr" variant is optimal for speed, so that is set as default.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_crw_crw is
generic (
@@ -86,11 +86,13 @@ architecture rtl of common_paged_ram_crw_crw is
constant c_page_addr_w : natural := ceil_log2(g_page_sz);
-- g_str = "use_mux" :
- constant c_page_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_page_addr_w,
- dat_w => g_data_w,
- nof_dat => g_page_sz,
- init_sl => '0');
+ constant c_page_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_page_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0'
+ );
type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
@@ -99,21 +101,25 @@ architecture rtl of common_paged_ram_crw_crw is
constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w; -- <= 2**c_mem_addr_w
- constant c_mem_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_mem_addr_w,
- dat_w => g_data_w,
- nof_dat => c_mem_nof_words,
- init_sl => '0');
+ constant c_mem_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_mem_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_mem_nof_words,
+ init_sl => '0'
+ );
-- g_str = "use_ofs" :
constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
- constant c_buf_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_buf_addr_w,
- dat_w => g_data_w,
- nof_dat => c_buf_nof_words,
- init_sl => '0');
+ constant c_buf_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_buf_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_buf_nof_words,
+ init_sl => '0'
+ );
-- >>> Page control
@@ -227,32 +233,32 @@ begin
gen_mux : if g_str = "use_mux" generate
gen_pages : for I in 0 to g_nof_pages - 1 generate
u_ram : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_page_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => adr_a,
- wr_en_a => page_wr_en_a(I),
- wr_dat_a => wr_dat_a,
- rd_en_a => page_rd_en_a(I),
- rd_dat_a => page_rd_dat_a(I),
- rd_val_a => page_rd_val_a(I),
- adr_b => adr_b,
- wr_en_b => page_wr_en_b(I),
- wr_dat_b => wr_dat_b,
- rd_en_b => page_rd_en_b(I),
- rd_dat_b => page_rd_dat_b(I),
- rd_val_b => page_rd_val_b(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => adr_a,
+ wr_en_a => page_wr_en_a(I),
+ wr_dat_a => wr_dat_a,
+ rd_en_a => page_rd_en_a(I),
+ rd_dat_a => page_rd_dat_a(I),
+ rd_val_a => page_rd_val_a(I),
+ adr_b => adr_b,
+ wr_en_b => page_wr_en_b(I),
+ wr_dat_b => wr_dat_b,
+ rd_en_b => page_rd_en_b(I),
+ rd_dat_b => page_rd_dat_b(I),
+ rd_val_b => page_rd_val_b(I)
+ );
end generate;
p_mux : process(page_sel_a, wr_en_a, rd_en_a, page_sel_a_dly, page_rd_dat_a, page_rd_val_a,
@@ -278,32 +284,32 @@ begin
gen_adr : if g_str = "use_adr" generate
u_mem : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_mem_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => mem_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- adr_b => mem_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mem_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => mem_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => mem_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
mem_adr_a <= TO_UVEC(page_sel_a, c_mem_nof_pages_w) & adr_a;
mem_adr_b <= TO_UVEC(page_sel_b, c_mem_nof_pages_w) & adr_b;
@@ -312,32 +318,32 @@ begin
gen_ofs : if g_str = "use_ofs" generate
u_buf : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_buf_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => buf_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- adr_b => buf_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => buf_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => buf_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
buf_adr_a <= INCR_UVEC(RESIZE_UVEC(adr_a, c_buf_addr_w), page_ofs_a);
buf_adr_b <= INCR_UVEC(RESIZE_UVEC(adr_b, c_buf_addr_w), page_ofs_b);
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
index ec36a9d874..1ee52bec9b 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
@@ -26,11 +26,11 @@
-- . See common_paged_ram_crw_crw for details.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_r_w is
generic (
@@ -65,35 +65,35 @@ architecture str of common_paged_ram_r_w is
begin
u_rw_rw : entity work.common_paged_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_str => g_str,
- g_data_w => g_data_w,
- g_nof_pages => g_nof_pages,
- g_page_sz => g_page_sz,
- g_start_page_a => g_wr_start_page,
- g_start_page_b => g_rd_start_page,
- g_rd_latency => g_rd_latency,
- g_true_dual_port => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- next_page_a => wr_next_page,
- adr_a => wr_adr,
- wr_en_a => wr_en,
- wr_dat_a => wr_dat,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => rd_next_page,
- adr_b => rd_adr,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en,
- rd_dat_b => rd_dat,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_str => g_str,
+ g_data_w => g_data_w,
+ g_nof_pages => g_nof_pages,
+ g_page_sz => g_page_sz,
+ g_start_page_a => g_wr_start_page,
+ g_start_page_b => g_rd_start_page,
+ g_rd_latency => g_rd_latency,
+ g_true_dual_port => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ next_page_a => wr_next_page,
+ adr_a => wr_adr,
+ wr_en_a => wr_en,
+ wr_dat_a => wr_dat,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => rd_next_page,
+ adr_b => rd_adr,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en,
+ rd_dat_b => rd_dat,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index 425c99ae71..e22b714d5f 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -26,11 +26,11 @@
-- . See common_paged_ram_crw_crw for details.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_rw_rw is
generic (
@@ -71,38 +71,38 @@ architecture str of common_paged_ram_rw_rw is
begin
u_crw_crw : entity work.common_paged_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_str => g_str,
- g_data_w => g_data_w,
- g_nof_pages => g_nof_pages,
- g_page_sz => g_page_sz,
- g_start_page_a => g_start_page_a,
- g_start_page_b => g_start_page_b,
- g_rd_latency => g_rd_latency,
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => clken,
- clken_b => clken,
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_str => g_str,
+ g_data_w => g_data_w,
+ g_nof_pages => g_nof_pages,
+ g_page_sz => g_page_sz,
+ g_start_page_a => g_start_page_a,
+ g_start_page_b => g_start_page_b,
+ g_rd_latency => g_rd_latency,
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => clken,
+ clken_b => clken,
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
index 01e3a408e3..ab6bcbddbe 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
@@ -26,9 +26,9 @@
-- Each page uses one or more RAM blocks.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_w_rr is
generic (
@@ -68,34 +68,34 @@ architecture str of common_paged_ram_w_rr is
begin
u_ww_rr : entity work.common_paged_ram_ww_rr
- generic map (
- g_technology => g_technology,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => g_data_w,
- g_page_sz => g_page_sz,
- g_ram_rd_latency => g_ram_rd_latency
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- -- next page control
- next_page => next_page,
- -- double write access to one page --> use only page a
- wr_adr_a => wr_adr,
- wr_en_a => wr_en,
- wr_dat_a => wr_dat,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => g_data_w,
+ g_page_sz => g_page_sz,
+ g_ram_rd_latency => g_ram_rd_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page --> use only page a
+ wr_adr_a => wr_adr,
+ wr_en_a => wr_en,
+ wr_dat_a => wr_dat,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
index 02889f1645..6ede04b4b8 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
@@ -26,11 +26,11 @@
-- Each page uses one or more RAM blocks.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use work.common_components_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.common_components_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_ww_rr is
generic (
@@ -78,11 +78,13 @@ architecture rtl of common_paged_ram_ww_rr is
constant c_addr_w : natural := ceil_log2(g_page_sz);
- constant c_page_ram : t_c_mem := (latency => g_ram_rd_latency,
- adr_w => c_addr_w,
- dat_w => g_data_w,
- nof_dat => g_page_sz,
- init_sl => '0');
+ constant c_page_ram : t_c_mem := (
+ latency => g_ram_rd_latency,
+ adr_w => c_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0'
+ );
type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
type t_addr_arr is array (integer range <>) of std_logic_vector(c_addr_w - 1 downto 0);
@@ -181,28 +183,28 @@ begin
u_pipe_page_adr_b : common_pipeline generic map ("SIGNED", g_pipeline_in, 0, c_addr_w, c_addr_w) port map (rst, clk, clken, '0', '1', nxt_page_adr_b(I), page_adr_b(I));
u_page : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => c_page_ram,
- g_init_file => "UNUSED"
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- adr_a => page_adr_a(I),
- wr_en_a => page_wr_en_a(I),
- wr_dat_a => page_wr_dat_a,
- rd_en_a => page_rd_en_a(I),
- rd_dat_a => page_rd_dat_a(I),
- rd_val_a => page_rd_val_a(I),
- adr_b => page_adr_b(I),
- wr_en_b => page_wr_en_b(I),
- wr_dat_b => page_wr_dat_b,
- rd_en_b => page_rd_en_b(I),
- rd_dat_b => page_rd_dat_b(I),
- rd_val_b => page_rd_val_b(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => page_adr_a(I),
+ wr_en_a => page_wr_en_a(I),
+ wr_dat_a => page_wr_dat_a,
+ rd_en_a => page_rd_en_a(I),
+ rd_dat_a => page_rd_dat_a(I),
+ rd_val_a => page_rd_val_a(I),
+ adr_b => page_adr_b(I),
+ wr_en_b => page_wr_en_b(I),
+ wr_dat_b => page_wr_dat_b,
+ rd_en_b => page_rd_en_b(I),
+ rd_dat_b => page_rd_dat_b(I),
+ rd_val_b => page_rd_val_b(I)
+ );
end generate;
-- use page_sel_out to account for the RAM read latency
diff --git a/libraries/base/common/src/vhdl/common_paged_reg.vhd b/libraries/base/common/src/vhdl/common_paged_reg.vhd
index bfb3cc4aeb..defa97b3d3 100644
--- a/libraries/base/common/src/vhdl/common_paged_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_reg.vhd
@@ -27,8 +27,8 @@
-- Remarks:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_paged_reg is
generic (
@@ -60,17 +60,17 @@ begin
-- Shift the intermediate data pages when enabled
gen_pages : for I in g_nof_pages - 1 downto 0 generate
u_page : entity work.common_pipeline
- generic map (
- g_in_dat_w => g_data_w,
- g_out_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_en => wr_en(I),
- in_dat => reg_dat(I + 1),
- out_dat => reg_dat(I)
- );
+ generic map (
+ g_in_dat_w => g_data_w,
+ g_out_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_en => wr_en(I),
+ in_dat => reg_dat(I + 1),
+ out_dat => reg_dat(I)
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_peak.vhd b/libraries/base/common/src/vhdl/common_peak.vhd
index 1765183b33..11236fa322 100644
--- a/libraries/base/common/src/vhdl/common_peak.vhd
+++ b/libraries/base/common/src/vhdl/common_peak.vhd
@@ -28,8 +28,8 @@
--
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_peak is
generic (
diff --git a/libraries/base/common/src/vhdl/common_pipeline.vhd b/libraries/base/common/src/vhdl/common_pipeline.vhd
index 5da5682ea0..109e783d16 100644
--- a/libraries/base/common/src/vhdl/common_pipeline.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline is
generic (
diff --git a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
index feb5ac1796..e599174fe4 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline_integer is
generic (
@@ -53,21 +53,21 @@ begin
out_dat <= TO_SINT(out_dat_slv) when g_representation = "SIGNED" else TO_UINT(out_dat_slv);
u_int : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
index ce8d7d5e9d..0e9d479f45 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline_natural is
generic (
@@ -52,21 +52,21 @@ begin
out_dat <= TO_UINT(out_dat_slv);
u_int : entity work.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
index a4afcd92de..8d67207276 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity common_pipeline_sl is
generic (
@@ -53,21 +53,21 @@ begin
out_dat <= out_dat_slv(0);
u_sl : entity work.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline,
- g_reset_value => sel_a_b(g_out_invert, 1 - g_reset_value, g_reset_value),
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline,
+ g_reset_value => sel_a_b(g_out_invert, 1 - g_reset_value, g_reset_value),
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
index edb63c6f59..963b0901b7 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Per symbol pipeline of the input data stream
-- Description:
@@ -69,50 +69,50 @@ begin
-- pipeline per symbol
u_pipe_symbol : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_arr(I),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_dat_arr(I),
- out_dat => out_dat_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_dat_arr(I),
+ out_dat => out_dat_arr(I)
+ );
u_pipe_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val_arr(I)
+ );
u_pipe_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop_arr(I)
+ );
u_pipe_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop_arr(I)
+ );
-- map arr to output vector
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_dat_arr(I);
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 6a03dd4feb..99d1d972c4 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -27,9 +27,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
@@ -181,239 +181,239 @@ package common_pkg is
-- All functions assume [high downto low] input ranges
- function pow2(n : natural) return natural; -- = 2**n
- function ceil_pow2(n : integer) return natural; -- = 2**n, returns 1 for n<0
+ function pow2 (n : natural) return natural; -- = 2**n
+ function ceil_pow2 (n : integer) return natural; -- = 2**n, returns 1 for n<0
- function true_log2(n : natural) return natural; -- true_log2(n) = log2(n)
- function ceil_log2(n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
+ function true_log2 (n : natural) return natural; -- true_log2(n) = log2(n)
+ function ceil_log2 (n : natural) return natural; -- ceil_log2(n) = log2(n), but force ceil_log2(1) = 1
- function floor_log10(n : natural) return natural;
+ function floor_log10 (n : natural) return natural;
- function is_pow2(n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
- function true_log_pow2(n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
+ function is_pow2 (n : natural) return boolean; -- return TRUE when n is a power of 2, so 0, 1, 2, 4, 8, 16, ...
+ function true_log_pow2 (n : natural) return natural; -- 2**true_log2(n), return power of 2 that is >= n
- function ratio( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
- function ratio2(n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
+ function ratio ( n, d : natural) return natural; -- return n/d when n MOD d = 0 else return 0, so ratio * d = n only when integer ratio > 0
+ function ratio2 (n, m : natural) return natural; -- return integer ratio of n/m or m/n, whichever is the largest
-- use almost_equal(a/b, 1.0, max_ratio) to verify that a and b differ less than max_ratio/100 percent
-- use almost_zero(a/b, max_ratio) to verify that a is less than max_ratio/100 percent of b, so almost zero
- function almost_equal(a, b, delta : real) return boolean; -- return TRUE when abs(a - b) < abs(delta), else return FALSE
- function almost_equal(a, b, delta : integer) return boolean;
- function almost_zero(a, delta : real) return boolean; -- return TRUE when abs(a) < abs(delta), else return FALSE
- function almost_zero(a, delta : integer) return boolean;
-
- function ceil_div( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
- function ceil_value( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
- function floor_value(n, d : natural) return natural; -- floor_value = (n/d) * d
- function ceil_div( n : unsigned; d: natural) return unsigned;
- function ceil_value( n : unsigned; d: natural) return unsigned;
- function floor_value(n : unsigned; d: natural) return unsigned;
- function gcd(a, b : natural) return natural; -- greatest common divider
-
- function slv(n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
- function sl( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
-
- function to_sl( n: in boolean) return std_logic; -- if TRUE then return '1' else '0'
- function to_bool(n: in std_logic) return boolean; -- if '1' or 'H' then return TRUE else FALSE
- function to_bool(n: in integer) return boolean; -- if 0 then return FALSE else TRUE
-
- function not_int(n: in integer) return integer; -- if 0 then return 1 else 0
-
- function pack_complex(re, im : integer; w : natural) return integer; -- pack order: im & re
- function unpack_complex_re(data : integer; w : natural) return integer; -- pack order: im & re
- function unpack_complex_re(data : std_logic_vector; w : natural) return integer; -- pack order: im & re
- function unpack_complex_im(data : integer; w : natural) return integer; -- pack order: im & re
- function unpack_complex_im(data : std_logic_vector; w : natural) return integer; -- pack order: im & re
-
- function atan2(Y, X: real) return real; -- = ARCTAN(Y, X) but returns 0 when Y = X = 0, without reporting Error: ARCTAN(0.0, 0.0) is undetermined
-
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr;
- function to_slv_32_arr( n : t_integer_arr) return t_slv_32_arr;
- function to_slv_32_arr( n : t_natural_arr) return t_slv_32_arr;
-
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
- function vector_and(slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
- function vector_or( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
- function vector_xor(slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
-
- function andv(slv : std_logic_vector) return std_logic; -- alias of vector_and
- function orv( slv : std_logic_vector) return std_logic; -- alias of vector_or
- function xorv(slv : std_logic_vector) return std_logic; -- alias of vector_xor
-
- function array_and(arr : t_nat_boolean_arr) return boolean;
- function array_or( arr : t_nat_boolean_arr) return boolean;
-
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
- function matrix_or( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
-
- function smallest(n, m : integer) return integer;
- function smallest(n, m : real) return real;
- function smallest(n, m, l : integer) return integer;
- function smallest(n : t_natural_arr) return natural;
- function smallest(n : t_nat_natural_arr) return natural;
-
- function largest(n, m : integer) return integer;
- function largest(n, m : real) return real;
- function largest(n : t_natural_arr) return natural;
- function largest(n : t_nat_natural_arr) return natural;
-
- function func_sum( n : t_natural_arr) return natural; -- sum of all elements in array
- function func_sum( n : t_nat_natural_arr) return natural;
- function func_product(n : t_natural_arr) return natural; -- product of all elements in array
- function func_product(n : t_nat_natural_arr) return natural;
-
- function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
- function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
- function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
-
- function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
- function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
- function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
- function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
-
- function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
- function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
- function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
-
- function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
+ function almost_equal (a, b, delta : real) return boolean; -- return TRUE when abs(a - b) < abs(delta), else return FALSE
+ function almost_equal (a, b, delta : integer) return boolean;
+ function almost_zero (a, delta : real) return boolean; -- return TRUE when abs(a) < abs(delta), else return FALSE
+ function almost_zero (a, delta : integer) return boolean;
+
+ function ceil_div ( n, d : natural) return natural; -- ceil_div = n/d + (n MOD d)/=0
+ function ceil_value ( n, d : natural) return natural; -- ceil_value = ceil_div(n, d) * d
+ function floor_value (n, d : natural) return natural; -- floor_value = (n/d) * d
+ function ceil_div ( n : unsigned; d: natural) return unsigned;
+ function ceil_value ( n : unsigned; d: natural) return unsigned;
+ function floor_value (n : unsigned; d: natural) return unsigned;
+ function gcd (a, b : natural) return natural; -- greatest common divider
+
+ function slv (n: in std_logic) return std_logic_vector; -- standard logic to 1 element standard logic vector
+ function sl ( n: in std_logic_vector) return std_logic; -- 1 element standard logic vector to standard logic
+
+ function to_sl ( n: in boolean) return std_logic; -- if TRUE then return '1' else '0'
+ function to_bool (n: in std_logic) return boolean; -- if '1' or 'H' then return TRUE else FALSE
+ function to_bool (n: in integer) return boolean; -- if 0 then return FALSE else TRUE
+
+ function not_int (n: in integer) return integer; -- if 0 then return 1 else 0
+
+ function pack_complex (re, im : integer; w : natural) return integer; -- pack order: im & re
+ function unpack_complex_re (data : integer; w : natural) return integer; -- pack order: im & re
+ function unpack_complex_re (data : std_logic_vector; w : natural) return integer; -- pack order: im & re
+ function unpack_complex_im (data : integer; w : natural) return integer; -- pack order: im & re
+ function unpack_complex_im (data : std_logic_vector; w : natural) return integer; -- pack order: im & re
+
+ function atan2 (Y, X: real) return real; -- = ARCTAN(Y, X) but returns 0 when Y = X = 0, without reporting Error: ARCTAN(0.0, 0.0) is undetermined
+
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr; -- if to_zero=TRUE then negative numbers are forced to zero, otherwise they will give a compile range error
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr;
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr;
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr;
+ function to_slv_32_arr ( n : t_integer_arr) return t_slv_32_arr;
+ function to_slv_32_arr ( n : t_natural_arr) return t_slv_32_arr;
+
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic; -- Core operation tree function for vector "AND", "OR", "XOR"
+ function vector_and (slv : std_logic_vector) return std_logic; -- '1' when all slv bits are '1' else '0'
+ function vector_or ( slv : std_logic_vector) return std_logic; -- '0' when all slv bits are '0' else '1'
+ function vector_xor (slv : std_logic_vector) return std_logic; -- '1' when the slv has an odd number of '1' bits else '0'
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector; -- Returns slv when it contains one hot bit, else returns 0.
+
+ function andv (slv : std_logic_vector) return std_logic; -- alias of vector_and
+ function orv ( slv : std_logic_vector) return std_logic; -- alias of vector_or
+ function xorv (slv : std_logic_vector) return std_logic; -- alias of vector_xor
+
+ function array_and (arr : t_nat_boolean_arr) return boolean;
+ function array_or ( arr : t_nat_boolean_arr) return boolean;
+
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '1' when all matrix bits are '1' else '0'
+ function matrix_or ( mat : t_sl_matrix; wi, wj : natural) return std_logic; -- '0' when all matrix bits are '0' else '1'
+
+ function smallest (n, m : integer) return integer;
+ function smallest (n, m : real) return real;
+ function smallest (n, m, l : integer) return integer;
+ function smallest (n : t_natural_arr) return natural;
+ function smallest (n : t_nat_natural_arr) return natural;
+
+ function largest (n, m : integer) return integer;
+ function largest (n, m : real) return real;
+ function largest (n : t_natural_arr) return natural;
+ function largest (n : t_nat_natural_arr) return natural;
+
+ function func_sum ( n : t_natural_arr) return natural; -- sum of all elements in array
+ function func_sum ( n : t_nat_natural_arr) return natural;
+ function func_product (n : t_natural_arr) return natural; -- product of all elements in array
+ function func_product (n : t_nat_natural_arr) return natural;
+
+ function "+" (L, R: t_natural_arr) return t_natural_arr; -- element wise sum
+ function "+" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise sum
+ function "+" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise sum
+
+ function "-" (L, R: t_natural_arr) return t_natural_arr; -- element wise subtract
+ function "-" (L, R: t_natural_arr) return t_integer_arr; -- element wise subtract, support negative result
+ function "-" (L : t_natural_arr; R : integer) return t_natural_arr; -- element wise subtract
+ function "-" (L : integer; R : t_natural_arr) return t_natural_arr; -- element wise subtract
+
+ function "*" (L, R: t_natural_arr) return t_natural_arr; -- element wise product
+ function "*" (L : t_natural_arr; R : natural) return t_natural_arr; -- element wise product
+ function "*" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise product
+
+ function "/" (L, R: t_natural_arr) return t_natural_arr; -- element wise division
function "/" (L : t_natural_arr; R : positive) return t_natural_arr; -- element wise division
- function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
-
- function is_true(a : std_logic) return boolean;
- function is_true(a : std_logic) return natural;
- function is_true(a : boolean) return std_logic;
- function is_true(a : boolean) return natural;
- function is_true(a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
- function is_true(a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
-
- function sel_a_b(sel, a, b : boolean) return boolean;
- function sel_a_b(sel, a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : integer) return integer;
- function sel_a_b(sel : boolean; a, b : real) return real;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector;
- function sel_a_b(sel : boolean; a, b : signed) return signed;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
- function sel_a_b(sel : boolean; a, b : string) return string;
- function sel_a_b(sel : integer; a, b : string) return string;
- function sel_a_b(sel : boolean; a, b : time) return time;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level;
+ function "/" (L : natural; R : t_natural_arr) return t_natural_arr; -- element wise division
+
+ function is_true (a : std_logic) return boolean;
+ function is_true (a : std_logic) return natural;
+ function is_true (a : boolean) return std_logic;
+ function is_true (a : boolean) return natural;
+ function is_true (a : integer) return boolean; -- also covers NATURAL because it is a subtype of INTEGER
+ function is_true (a : integer) return std_logic; -- also covers NATURAL because it is a subtype of INTEGER
+
+ function sel_a_b (sel, a, b : boolean) return boolean;
+ function sel_a_b (sel, a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : integer) return integer;
+ function sel_a_b (sel : boolean; a, b : real) return real;
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic;
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function sel_a_b (sel : boolean; a, b : signed) return signed;
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned;
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr;
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr;
+ function sel_a_b (sel : boolean; a, b : string) return string;
+ function sel_a_b (sel : integer; a, b : string) return string;
+ function sel_a_b (sel : boolean; a, b : time) return time;
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level;
-- sel_n() index sel = 0, 1, 2, ... will return a, b, c, ...
- function sel_n(sel : natural; a, b, c : boolean) return boolean; -- 3
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean; -- 4
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
-
- function sel_n(sel : natural; a, b, c : integer) return integer; -- 3
- function sel_n(sel : natural; a, b, c, d : integer) return integer; -- 4
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
-
- function sel_n(sel : natural; a, b : string) return string; -- 2
- function sel_n(sel : natural; a, b, c : string) return string; -- 3
- function sel_n(sel : natural; a, b, c, d : string) return string; -- 4
- function sel_n(sel : natural; a, b, c, d, e : string) return string; -- 5
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string; -- 6
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
- function array_init(init : boolean; nof : natural) return t_nat_boolean_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
- function array_init(init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
- function array_init(init, nof, incr : natural) return t_nat_natural_arr;
- function array_init(init, nof, incr : integer) return t_slv_16_arr;
- function array_init(init, nof, incr : integer) return t_slv_32_arr;
- function array_init(init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
- function array_init(init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
- function array_sinit(init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
-
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
+ function sel_n (sel : natural; a, b, c : boolean) return boolean; -- 3
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean; -- 10
+
+ function sel_n (sel : natural; a, b, c : integer) return integer; -- 3
+ function sel_n (sel : natural; a, b, c, d : integer) return integer; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer; -- 10
+
+ function sel_n (sel : natural; a, b : string) return string; -- 2
+ function sel_n (sel : natural; a, b, c : string) return string; -- 3
+ function sel_n (sel : natural; a, b, c, d : string) return string; -- 4
+ function sel_n (sel : natural; a, b, c, d, e : string) return string; -- 5
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string; -- 6
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string; -- 7
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string; -- 8
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string; -- 9
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string; -- 10
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector; -- useful to init a unconstrained array of size 1
+ function array_init (init : boolean; nof : natural) return t_nat_boolean_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof : natural) return t_nat_natural_arr; -- useful to init a unconstrained array of size 1
+ function array_init (init, nof, incr : natural) return t_natural_arr; -- useful to init an array with incrementing numbers
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr;
+ function array_init (init, nof, incr : integer) return t_slv_16_arr;
+ function array_init (init, nof, incr : integer) return t_slv_32_arr;
+ function array_init (init, nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+ function array_init (init, nof, width, incr : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with incrementing content
+ function array_sinit (init : integer; nof, width : natural) return std_logic_vector; -- useful to init an unconstrained std_logic_vector with repetitive content
+
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix; -- initialize all elements in t_slv_64_matrix to value k
-- Concatenate two or more STD_LOGIC_VECTORs into a single STD_LOGIC_VECTOR or extract one of them from a concatenated STD_LOGIC_VECTOR
-- . Note that using func_slv_concat() without the BOOLEAN use_* is equivalent to using the
-- slv concatenation operator & directly. However this overloaded func_slv_concat() is
-- still nice to have, because it shows the relation with the inverse func_slv_extract().
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a, b, c, d, e, f, g, h : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
- function func_slv_concat( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
- function func_slv_concat( a, b, c, d, e, f, g, h : std_logic_vector) return std_logic_vector;
- function func_slv_concat( a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
- function func_slv_concat( a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
- function func_slv_concat( a, b, c, d, e : std_logic_vector) return std_logic_vector;
- function func_slv_concat( a, b, c, d : std_logic_vector) return std_logic_vector;
- function func_slv_concat( a, b, c : std_logic_vector) return std_logic_vector;
- function func_slv_concat( a, b : std_logic_vector) return std_logic_vector;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
- function func_slv_extract( a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a, b, c, d, e, f, g, h : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( a, b, c, d, e, f, g, h : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( a, b, c, d, e, f : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( a, b, c, d, e : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( a, b, c, d : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( a, b, c : std_logic_vector) return std_logic_vector;
+ function func_slv_concat ( a, b : std_logic_vector) return std_logic_vector;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural;
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
+ function func_slv_extract ( a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector;
-- Number formats, see:
-- . https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
-- . https://support.astron.nl/confluence/display/L2M/L4+SDPFW+Decision%3A+Number+representation%2C+resizing+and+rounding
- function TO_UINT(vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
- function TO_SINT(vec : std_logic_vector) return integer;
+ function TO_UINT (vec : std_logic_vector) return natural; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
+ function TO_SINT (vec : std_logic_vector) return integer;
- function TO_UVEC(dec, w : natural) return std_logic_vector;
- function TO_SVEC(dec, w : integer) return std_logic_vector;
+ function TO_UVEC (dec, w : natural) return std_logic_vector;
+ function TO_SVEC (dec, w : integer) return std_logic_vector;
- function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
+ function TO_SVEC_32 (dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
- function TO_UINT(udec : real; w, resolution_w : integer) return natural; -- REAL >= 0 to NATURAL fixed point number
- function TO_SINT(sdec : real; w, resolution_w : integer) return integer; -- REAL to INTEGER fixed point number
- function TO_UVEC(udec : real; w, resolution_w : integer) return std_logic_vector; -- REAL >= 0 to unsigned SLV fixed point number
- function TO_SVEC(sdec : real; w, resolution_w : integer) return std_logic_vector; -- REAL to signed SLV fixed point number
+ function TO_UINT (udec : real; w, resolution_w : integer) return natural; -- REAL >= 0 to NATURAL fixed point number
+ function TO_SINT (sdec : real; w, resolution_w : integer) return integer; -- REAL to INTEGER fixed point number
+ function TO_UVEC (udec : real; w, resolution_w : integer) return std_logic_vector; -- REAL >= 0 to unsigned SLV fixed point number
+ function TO_SVEC (sdec : real; w, resolution_w : integer) return std_logic_vector; -- REAL to signed SLV fixed point number
- function TO_UREAL(uvec : std_logic_vector) return real; -- convert unsigned slv of any length to REAL, fixed point number with resolution = 1
- function TO_SREAL(svec : std_logic_vector) return real; -- convert signed slv of any length to REAL, fixed point number with resolution = 1
- function TO_UREAL(uvec : std_logic_vector; resolution_w : integer) return real; -- convert unsigned fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
- function TO_SREAL(svec : std_logic_vector; resolution_w : integer) return real; -- convert signed fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
+ function TO_UREAL (uvec : std_logic_vector) return real; -- convert unsigned slv of any length to REAL, fixed point number with resolution = 1
+ function TO_SREAL (svec : std_logic_vector) return real; -- convert signed slv of any length to REAL, fixed point number with resolution = 1
+ function TO_UREAL (uvec : std_logic_vector; resolution_w : integer) return real; -- convert unsigned fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
+ function TO_SREAL (svec : std_logic_vector; resolution_w : integer) return real; -- convert signed fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
-- RESIZE_NUM() original description:
-- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
@@ -447,167 +447,170 @@ package common_pkg is
-- RESIZE() does (keeping the MSbit and the w-1 LSbits). The wrapping of RESIZE_NUM() preserves the
-- capability of recovering from intermediate overflow in a summator, which can be beneficial for e.g.
-- a beamformer.
- function RESIZE_NUM( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
- function RESIZE_NUM( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
- function RESIZE_UINT(u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
- function RESIZE_SINT(s : integer; w : natural) return integer; -- extend sign bit or keep LS part
-
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
-
- function NEGATE_SVEC(vec : std_logic_vector) return std_logic_vector; -- assume negated ranges fits within -+max
- function NEGATE_SVEC(vec : std_logic_vector; w : integer) return std_logic_vector; -- avoid overflow by forcing -min to +max. Use w <= vec'LENGTH
-
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
-
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
-
- function MULT_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec * r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH + r_vec'LENGTH
- function MULT_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec * r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH + r_vec'LENGTH
-
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
+ function RESIZE_NUM ( u : unsigned; w : natural) return unsigned; -- left extend with '0' or keep LS part (same as RESIZE for UNSIGNED)
+ function RESIZE_NUM ( s : signed; w : natural) return signed; -- extend sign bit or keep LS part
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector; -- left extend with '0' into slv
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- left extend with '0' or keep LS part
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector; -- extend sign bit or keep LS part
+ function RESIZE_UINT (u : integer; w : natural) return integer; -- left extend with '0' or keep LS part
+ function RESIZE_SINT (s : integer; w : natural) return integer; -- extend sign bit or keep LS part
+
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_UVEC() with w=32 for t_slv_32_arr slv elements
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector; -- = RESIZE_SVEC() with w=32 for t_slv_32_arr slv elements
+
+ function NEGATE_SVEC (vec : std_logic_vector) return std_logic_vector; -- assume negated ranges fits within -+max
+ function NEGATE_SVEC (vec : std_logic_vector; w : integer) return std_logic_vector; -- avoid overflow by forcing -min to +max. Use w <= vec'LENGTH
+
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector;
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector;
+ -- Used in common_add_sub.vhd
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is res_w
+
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
+
+ function MULT_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec * r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH + r_vec'LENGTH
+ function MULT_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector; -- l_vec * r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH + r_vec'LENGTH
+
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-- Convert between polar and rectangular coordinates
- function COMPLEX_RADIUS(re, im : real) return real;
- function COMPLEX_RADIUS(re, im : integer) return real;
+ function COMPLEX_RADIUS (re, im : real) return real;
+ function COMPLEX_RADIUS (re, im : integer) return real;
- function COMPLEX_PHASE( re, im : real; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_PHASE( re, im : integer; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_PHASE( re, im : real) return real; -- phase in degrees
- function COMPLEX_PHASE( re, im : integer) return real; -- phase in degrees
+ function COMPLEX_PHASE ( re, im : real; radians : boolean) return real; -- phase in radians or degrees
+ function COMPLEX_PHASE ( re, im : integer; radians : boolean) return real; -- phase in radians or degrees
+ function COMPLEX_PHASE ( re, im : real) return real; -- phase in degrees
+ function COMPLEX_PHASE ( re, im : integer) return real; -- phase in degrees
- function COMPLEX_RE(ampl, phase : real; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_RE(ampl, phase : integer; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_RE(ampl, phase : real) return real; -- phase in degrees
- function COMPLEX_RE(ampl, phase : integer) return real; -- phase in degrees
+ function COMPLEX_RE (ampl, phase : real; radians : boolean) return real; -- phase in radians or degrees
+ function COMPLEX_RE (ampl, phase : integer; radians : boolean) return real; -- phase in radians or degrees
+ function COMPLEX_RE (ampl, phase : real) return real; -- phase in degrees
+ function COMPLEX_RE (ampl, phase : integer) return real; -- phase in degrees
- function COMPLEX_IM(ampl, phase : real; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_IM(ampl, phase : integer; radians : boolean) return real; -- phase in radians or degrees
- function COMPLEX_IM(ampl, phase : real) return real; -- phase in degrees
- function COMPLEX_IM(ampl, phase : integer) return real; -- phase in degrees
+ function COMPLEX_IM (ampl, phase : real; radians : boolean) return real; -- phase in radians or degrees
+ function COMPLEX_IM (ampl, phase : integer; radians : boolean) return real; -- phase in radians or degrees
+ function COMPLEX_IM (ampl, phase : real) return real; -- phase in degrees
+ function COMPLEX_IM (ampl, phase : integer) return real; -- phase in degrees
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 shift left, > 0 shift right
- function ROTATE_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 rotate left, > 0 rotate right
+ function ROTATE_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector; -- < 0 rotate left, > 0 rotate right
- function offset_binary(a : std_logic_vector) return std_logic_vector;
+ function offset_binary (a : std_logic_vector) return std_logic_vector;
- function truncate( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function scale( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
- function scale_and_resize_uvec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
- function scale_and_resize_svec( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
- function truncate_or_resize_uvec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
- function truncate_or_resize_svec( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
+ function truncate ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec, so result has width vec'LENGTH-n
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- remove n LSBits from vec and then resize to width w
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function scale ( vec : std_logic_vector; n: natural) return std_logic_vector; -- add n '0' LSBits to vec
+ function scale_and_resize_uvec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- add n '0' LSBits to vec and then resize to width w
+ function scale_and_resize_svec ( vec : std_logic_vector; n, w : natural) return std_logic_vector; -- idem for signed values
+ function truncate_or_resize_uvec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- when b=TRUE then truncate to width w, else resize to width w
+ function truncate_or_resize_svec ( vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector; -- idem for signed values
- function s_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
- function s_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
- function s_round( vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector; -- idem but round half to even for signed
- function u_round( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
- function u_round( vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector; -- idem but round half to even for unsigned
+ function s_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n, and clip to avoid wrap
+ function s_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- remove n LSBits from vec by rounding away from 0, so result has width vec'LENGTH-n
+ function s_round ( vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector; -- idem but round half to even for signed
+ function u_round ( vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector; -- idem round up for unsigned values
+ function u_round ( vec : std_logic_vector; n : natural) return std_logic_vector; -- idem round up for unsigned values
+ function u_round ( vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector; -- idem but round half to even for unsigned
- function u_to_s(u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
- function s_to_u(s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
+ function u_to_s (u : natural; w : natural) return integer; -- interpret w bit unsigned u as w bit signed, and remove any MSbits
+ function s_to_u (s : integer; w : natural) return natural; -- interpret w bit signed s as w bit unsigned, and remove any MSbits
- function u_wrap(u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
- function s_wrap(s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
+ function u_wrap (u : natural; w : natural) return natural; -- return u & 2**w-1 (bit wise and), so keep w LSbits of unsigned u, and remove MSbits
+ function s_wrap (s : integer; w : natural) return integer; -- return s & 2**w-1 (bit wise and), so keep w LSbits of signed s, and remove MSbits
- function u_clip(u : natural; max : natural) return natural; -- if s < max return s, else return n
- function s_clip(s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
- function s_clip(s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
+ function u_clip (u : natural; max : natural) return natural; -- if s < max return s, else return n
+ function s_clip (s : integer; max : natural; min : integer) return integer; -- if s <= min return min, else if s >= max return max, else return s
+ function s_clip (s : integer; max : natural ) return integer; -- if s <= -max return -max, else if s >= max return max, else return s
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
- function hton(a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
- function ntoh(a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in symbols of width w
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from host to network, sz in bytes
+ function hton (a : std_logic_vector ) return std_logic_vector; -- convert endianity from host to network, for all bytes in a
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector; -- convert endianity from network to host, sz in bytes, ntoh() = hton()
+ function ntoh (a : std_logic_vector ) return std_logic_vector; -- convert endianity from network to host, for all bytes in a, ntoh() = hton()
- function flip(a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
- function flip(a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
- function flip(a : t_slv_32_arr) return t_slv_32_arr;
- function flip(a : t_integer_arr) return t_integer_arr;
- function flip(a : t_natural_arr) return t_natural_arr;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr;
+ function flip (a : std_logic_vector) return std_logic_vector; -- bit flip a vector, map a[h:0] to [0:h]
+ function flip (a, w : natural) return natural; -- bit flip a vector, map a[h:0] to [0:h], h = w-1
+ function flip (a : t_slv_32_arr) return t_slv_32_arr;
+ function flip (a : t_integer_arr) return t_integer_arr;
+ function flip (a : t_natural_arr) return t_natural_arr;
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
- function transpose(a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector; -- transpose a vector, map a[i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural; -- transpose index a = [i*row+j] to output index [j*col+i]
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural;
- function pad(str: string; width: natural; pad_char: character) return string;
+ function pad (str: string; width: natural; pad_char: character) return string;
- function slice_up(str: string; width: natural; i: natural) return string;
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string;
- function slice_dn(str: string; width: natural; i: natural) return string;
+ function slice_up (str: string; width: natural; i: natural) return string;
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string;
+ function slice_dn (str: string; width: natural; i: natural) return string;
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector;
------------------------------------------------------------------------------
-- Component specific functions
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
- function func_common_reorder2_is_there(I, J : natural) return boolean;
- function func_common_reorder2_is_active(I, J, N : natural) return boolean;
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer;
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural;
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
+ function func_common_reorder2_is_there (I, J : natural) return boolean;
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean;
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer;
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural;
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
- function pow2(n : natural) return natural is
+ function pow2 (n : natural) return natural is
begin
return 2**n;
end;
- function ceil_pow2(n : integer) return natural is
+ function ceil_pow2 (n : integer) return natural is
-- Also allows negative exponents and rounds up before returning the value
begin
return natural(integer(ceil(2**real(n))));
end;
- function true_log2(n : natural) return natural is
+ function true_log2 (n : natural) return natural is
-- Purpose: For calculating extra vector width of existing vector
-- Description: Return mathematical ceil(log2(n))
-- n log2()
@@ -626,7 +629,7 @@ package body common_pkg is
return natural(integer(ceil(log2(real(n)))));
end;
- function ceil_log2(n : natural) return natural is
+ function ceil_log2 (n : natural) return natural is
-- Purpose: For calculating vector width of new vector
-- Description:
-- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
@@ -644,22 +647,22 @@ package body common_pkg is
end if;
end;
- function floor_log10(n : natural) return natural is
+ function floor_log10 (n : natural) return natural is
begin
return natural(integer(floor(log10(real(n)))));
end;
- function is_pow2(n : natural) return boolean is
+ function is_pow2 (n : natural) return boolean is
begin
return n = 2**true_log2(n);
end;
- function true_log_pow2(n : natural) return natural is
+ function true_log_pow2 (n : natural) return natural is
begin
return 2**true_log2(n);
end;
- function ratio(n, d : natural) return natural is
+ function ratio (n, d : natural) return natural is
begin
if n mod d = 0 then
return n / d;
@@ -668,12 +671,12 @@ package body common_pkg is
end if;
end;
- function ratio2(n, m : natural) return natural is
+ function ratio2 (n, m : natural) return natural is
begin
return largest(ratio(n,m), ratio(m,n));
end;
- function almost_equal(a, b, delta : real) return boolean is
+ function almost_equal (a, b, delta : real) return boolean is
begin
if abs(a - b) <= abs(delta) then
return true;
@@ -682,7 +685,7 @@ package body common_pkg is
end if;
end;
- function almost_equal(a, b, delta : integer) return boolean is
+ function almost_equal (a, b, delta : integer) return boolean is
begin
if abs(a - b) <= abs(delta) then
return true;
@@ -691,37 +694,37 @@ package body common_pkg is
end if;
end;
- function almost_zero(a, delta : real) return boolean is
+ function almost_zero (a, delta : real) return boolean is
begin
return almost_equal(a, 0.0, delta);
end;
- function almost_zero(a, delta : integer) return boolean is
+ function almost_zero (a, delta : integer) return boolean is
begin
return almost_equal(a, 0, delta);
end;
- function ceil_div(n, d : natural) return natural is
+ function ceil_div (n, d : natural) return natural is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1);
end;
- function ceil_value(n, d : natural) return natural is
+ function ceil_value (n, d : natural) return natural is
begin
return ceil_div(n, d) * d;
end;
- function floor_value(n, d : natural) return natural is
+ function floor_value (n, d : natural) return natural is
begin
return (n / d) * d;
end;
- function ceil_div(n : unsigned; d: natural) return unsigned is
+ function ceil_div (n : unsigned; d: natural) return unsigned is
begin
return n / d + sel_a_b(n mod d = 0, 0, 1); -- "/" returns same width as n
end;
- function ceil_value(n : unsigned; d: natural) return unsigned is
+ function ceil_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -729,7 +732,7 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function floor_value(n : unsigned; d: natural) return unsigned is
+ function floor_value (n : unsigned; d: natural) return unsigned is
constant w : natural := n'length;
variable p : unsigned(2 * w - 1 downto 0);
begin
@@ -737,7 +740,7 @@ package body common_pkg is
return p(w - 1 downto 0); -- return same width as n
end;
- function gcd(a, b : natural) return natural is -- greatest common divider
+ function gcd (a, b : natural) return natural is -- greatest common divider
begin
if b = 0 then
return a;
@@ -746,14 +749,14 @@ package body common_pkg is
end if;
end;
- function slv(n: in std_logic) return std_logic_vector is
+ function slv (n: in std_logic) return std_logic_vector is
variable r : std_logic_vector(0 downto 0);
begin
r(0) := n;
return r;
end;
- function sl(n: in std_logic_vector) return std_logic is
+ function sl (n: in std_logic_vector) return std_logic is
variable r : std_logic;
begin
r := n(n'low);
@@ -761,7 +764,7 @@ package body common_pkg is
end;
- function to_sl(n: in boolean) return std_logic is
+ function to_sl (n: in boolean) return std_logic is
begin
if n = true then
return '1';
@@ -770,22 +773,22 @@ package body common_pkg is
end if;
end;
- function to_bool(n: in std_logic) return boolean is
+ function to_bool (n: in std_logic) return boolean is
begin
return n = '1' or n = 'H';
end;
- function to_bool(n: in integer) return boolean is
+ function to_bool (n: in integer) return boolean is
begin
return not (n = 0);
end;
- function not_int(n : integer) return integer is
+ function not_int (n : integer) return integer is
begin
return sel_a_b(n = 0, 1, 0);
end;
- function pack_complex(re, im : integer; w : natural) return integer is
+ function pack_complex (re, im : integer; w : natural) return integer is
constant c_complex_w : natural := 2 * w;
variable v_complex_slv : std_logic_vector(c_complex_w - 1 downto 0) := TO_SVEC(im, w) & TO_SVEC(re, w);
begin
@@ -797,33 +800,33 @@ package body common_pkg is
end if;
end;
- function unpack_complex_re(data : std_logic_vector; w : natural) return integer is
+ function unpack_complex_re (data : std_logic_vector; w : natural) return integer is
begin
assert w <= c_word_w report "common_pkg: Complex value to large to unpack into 32 bit integer parts" severity FAILURE;
return TO_SINT(data(w - 1 downto 0)); -- Re in LS part
end;
- function unpack_complex_re(data : integer; w : natural) return integer is
+ function unpack_complex_re (data : integer; w : natural) return integer is
constant c_complex_w : natural := 2 * w;
variable v_complex_slv : std_logic_vector(c_complex_w - 1 downto 0) := TO_SVEC(data, c_complex_w);
begin
return TO_SINT(v_complex_slv(w - 1 downto 0)); -- Re in LS part
end;
- function unpack_complex_im(data : std_logic_vector; w : natural) return integer is
+ function unpack_complex_im (data : std_logic_vector; w : natural) return integer is
begin
assert w <= c_word_w report "common_pkg: Complex value to large to unpack into 32 bit integer parts" severity FAILURE;
return TO_SINT(data(2 * w - 1 downto w)); -- Im in MS part
end;
- function unpack_complex_im(data : integer; w : natural) return integer is
+ function unpack_complex_im (data : integer; w : natural) return integer is
constant c_complex_w : natural := 2 * w;
variable v_complex_slv : std_logic_vector(c_complex_w - 1 downto 0) := TO_SVEC(data, c_complex_w);
begin
return TO_SINT(v_complex_slv(c_complex_w - 1 downto w)); -- Im in MS part
end;
- function atan2(Y, X: real) return real is
+ function atan2 (Y, X: real) return real is
begin
if Y = 0.0 and X = 0.0 then
return 0.0;
@@ -832,7 +835,7 @@ package body common_pkg is
end if;
end;
- function to_natural_arr(n : t_integer_arr; to_zero : boolean) return t_natural_arr is
+ function to_natural_arr (n : t_integer_arr; to_zero : boolean) return t_natural_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -850,7 +853,7 @@ package body common_pkg is
return vR;
end;
- function to_natural_arr(n : t_nat_natural_arr) return t_natural_arr is
+ function to_natural_arr (n : t_nat_natural_arr) return t_natural_arr is
variable vN : t_nat_natural_arr(n'length - 1 downto 0);
variable vR : t_natural_arr(n'length - 1 downto 0);
begin
@@ -861,7 +864,7 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_integer_arr(n'length - 1 downto 0);
begin
@@ -872,14 +875,14 @@ package body common_pkg is
return vR;
end;
- function to_integer_arr(n : t_nat_natural_arr) return t_integer_arr is
+ function to_integer_arr (n : t_nat_natural_arr) return t_integer_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return to_integer_arr(vN);
end;
- function to_slv_32_arr(n : t_integer_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_integer_arr) return t_slv_32_arr is
variable vN : t_integer_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -890,7 +893,7 @@ package body common_pkg is
return vR;
end;
- function to_slv_32_arr(n : t_natural_arr) return t_slv_32_arr is
+ function to_slv_32_arr (n : t_natural_arr) return t_slv_32_arr is
variable vN : t_natural_arr(n'length - 1 downto 0);
variable vR : t_slv_32_arr(n'length - 1 downto 0);
begin
@@ -901,7 +904,7 @@ package body common_pkg is
return vR;
end;
- function vector_tree(slv : std_logic_vector; operation : string) return std_logic is
+ function vector_tree (slv : std_logic_vector; operation : string) return std_logic is
-- Linear loop to determine result takes combinatorial delay that is proportional to slv'LENGTH:
-- FOR I IN slv'RANGE LOOP
-- v_result := v_result OPERATION slv(I);
@@ -934,22 +937,22 @@ package body common_pkg is
return v_stage_arr(c_nof_stages - 1)(0);
end;
- function vector_and(slv : std_logic_vector) return std_logic is
+ function vector_and (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function vector_or(slv : std_logic_vector) return std_logic is
+ function vector_or (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function vector_xor(slv : std_logic_vector) return std_logic is
+ function vector_xor (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function vector_one_hot(slv : std_logic_vector) return std_logic_vector is
+ function vector_one_hot (slv : std_logic_vector) return std_logic_vector is
variable v_one_hot : boolean := false;
variable v_zeros : std_logic_vector(slv'range) := (others => '0');
begin
@@ -968,36 +971,36 @@ package body common_pkg is
return slv;
end;
- function andv(slv : std_logic_vector) return std_logic is
+ function andv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "AND");
end;
- function orv(slv : std_logic_vector) return std_logic is
+ function orv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "OR");
end;
- function xorv(slv : std_logic_vector) return std_logic is
+ function xorv (slv : std_logic_vector) return std_logic is
begin
return vector_tree(slv, "XOR");
end;
- function array_and(arr : t_nat_boolean_arr) return boolean is
+ function array_and (arr : t_nat_boolean_arr) return boolean is
variable v_slv : std_logic_vector(arr'range);
begin
for I in arr'range loop v_slv(I) := sel_a_b(arr(I), '1', '0'); end loop; -- wire map boolean arr to slv
return sel_a_b(vector_and(v_slv) = '1', true, false); -- use vector_tree to determine result
end;
- function array_or(arr : t_nat_boolean_arr) return boolean is
+ function array_or (arr : t_nat_boolean_arr) return boolean is
variable v_slv : std_logic_vector(arr'range);
begin
for I in arr'range loop v_slv(I) := sel_a_b(arr(I), '1', '0'); end loop; -- wire map boolean arr to slv
return sel_a_b(vector_or(v_slv) = '1', true, false); -- use vector_tree to determine result
end;
- function matrix_and(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_and (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '1';
begin
@@ -1009,7 +1012,7 @@ package body common_pkg is
return v_result;
end;
- function matrix_or(mat : t_sl_matrix; wi, wj : natural) return std_logic is
+ function matrix_or (mat : t_sl_matrix; wi, wj : natural) return std_logic is
variable v_mat : t_sl_matrix(0 to wi - 1, 0 to wj - 1) := mat; -- map to fixed range
variable v_result : std_logic := '0';
begin
@@ -1021,7 +1024,7 @@ package body common_pkg is
return v_result;
end;
- function smallest(n, m : integer) return integer is
+ function smallest (n, m : integer) return integer is
begin
if n < m then
return n;
@@ -1030,7 +1033,7 @@ package body common_pkg is
end if;
end;
- function smallest(n, m : real) return real is
+ function smallest (n, m : real) return real is
begin
if n < m then
return n;
@@ -1039,16 +1042,16 @@ package body common_pkg is
end if;
end;
- function smallest(n, m, l : integer) return integer is
+ function smallest (n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
end;
- function smallest(n : t_natural_arr) return natural is
+ function smallest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -1059,7 +1062,7 @@ package body common_pkg is
return m;
end;
- function smallest(n : t_nat_natural_arr) return natural is
+ function smallest (n : t_nat_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -1070,7 +1073,7 @@ package body common_pkg is
return m;
end;
- function largest(n, m : integer) return integer is
+ function largest (n, m : integer) return integer is
begin
if n > m then
return n;
@@ -1079,7 +1082,7 @@ package body common_pkg is
end if;
end;
- function largest(n, m : real) return real is
+ function largest (n, m : real) return real is
begin
if n > m then
return n;
@@ -1088,7 +1091,7 @@ package body common_pkg is
end if;
end;
- function largest(n : t_natural_arr) return natural is
+ function largest (n : t_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -1099,7 +1102,7 @@ package body common_pkg is
return m;
end;
- function largest(n : t_nat_natural_arr) return natural is
+ function largest (n : t_nat_natural_arr) return natural is
variable m : natural := 0;
begin
for I in n'range loop
@@ -1110,7 +1113,7 @@ package body common_pkg is
return m;
end;
- function func_sum(n : t_natural_arr) return natural is
+ function func_sum (n : t_natural_arr) return natural is
variable vS : natural;
begin
vS := 0;
@@ -1120,14 +1123,14 @@ package body common_pkg is
return vS;
end;
- function func_sum(n : t_nat_natural_arr) return natural is
+ function func_sum (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
return func_sum(vN);
end;
- function func_product(n : t_natural_arr) return natural is
+ function func_product (n : t_natural_arr) return natural is
variable vP : natural;
begin
vP := 1;
@@ -1137,7 +1140,7 @@ package body common_pkg is
return vP;
end;
- function func_product(n : t_nat_natural_arr) return natural is
+ function func_product (n : t_nat_natural_arr) return natural is
variable vN : t_natural_arr(n'length - 1 downto 0);
begin
vN := to_natural_arr(n);
@@ -1296,14 +1299,14 @@ package body common_pkg is
return vP;
end;
- function is_true(a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
- function is_true(a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
- function is_true(a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
- function is_true(a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
- function is_true(a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
- function is_true(a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
+ function is_true (a : std_logic) return boolean is begin if a = '1' then return true; else return false; end if; end;
+ function is_true (a : std_logic) return natural is begin if a = '1' then return 1; else return 0; end if; end;
+ function is_true (a : boolean) return std_logic is begin if a = true then return '1'; else return '0'; end if; end;
+ function is_true (a : boolean) return natural is begin if a = true then return 1; else return 0; end if; end;
+ function is_true (a : integer) return boolean is begin if a /= 0 then return true; else return false; end if; end;
+ function is_true (a : integer) return std_logic is begin if a /= 0 then return '1'; else return '0'; end if; end;
- function sel_a_b(sel, a, b : integer) return integer is
+ function sel_a_b (sel, a, b : integer) return integer is
begin
if sel /= 0 then
return a;
@@ -1312,7 +1315,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel, a, b : boolean) return boolean is
+ function sel_a_b (sel, a, b : boolean) return boolean is
begin
if sel = true then
return a;
@@ -1321,7 +1324,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : integer) return integer is
+ function sel_a_b (sel : boolean; a, b : integer) return integer is
begin
if sel = true then
return a;
@@ -1330,7 +1333,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : real) return real is
+ function sel_a_b (sel : boolean; a, b : real) return real is
begin
if sel = true then
return a;
@@ -1339,7 +1342,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : boolean; a, b : std_logic) return std_logic is
begin
if sel = true then
return a;
@@ -1348,7 +1351,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic) return std_logic is
+ function sel_a_b (sel : integer; a, b : std_logic) return std_logic is
begin
if sel /= 0 then
return a;
@@ -1357,7 +1360,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : integer; a, b : std_logic_vector) return std_logic_vector is
begin
if sel /= 0 then
return a;
@@ -1366,7 +1369,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function sel_a_b (sel : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
if sel = true then
return a;
@@ -1375,7 +1378,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : signed) return signed is
+ function sel_a_b (sel : boolean; a, b : signed) return signed is
begin
if sel = true then
return a;
@@ -1384,7 +1387,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : unsigned) return unsigned is
+ function sel_a_b (sel : boolean; a, b : unsigned) return unsigned is
begin
if sel = true then
return a;
@@ -1393,7 +1396,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_integer_arr) return t_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_integer_arr) return t_integer_arr is
begin
if sel = true then
return a;
@@ -1402,7 +1405,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_natural_arr) return t_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_natural_arr) return t_natural_arr is
begin
if sel = true then
return a;
@@ -1411,7 +1414,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_integer_arr) return t_nat_integer_arr is
begin
if sel = true then
return a;
@@ -1420,7 +1423,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
+ function sel_a_b (sel : boolean; a, b : t_nat_natural_arr) return t_nat_natural_arr is
begin
if sel = true then
return a;
@@ -1429,7 +1432,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : string) return string is
+ function sel_a_b (sel : boolean; a, b : string) return string is
begin
if sel = true then
return a;
@@ -1438,7 +1441,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : integer; a, b : string) return string is
+ function sel_a_b (sel : integer; a, b : string) return string is
begin
if sel /= 0 then
return a;
@@ -1447,7 +1450,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : time) return time is
+ function sel_a_b (sel : boolean; a, b : time) return time is
begin
if sel = true then
return a;
@@ -1456,7 +1459,7 @@ package body common_pkg is
end if;
end;
- function sel_a_b(sel : boolean; a, b : severity_level) return severity_level is
+ function sel_a_b (sel : boolean; a, b : severity_level) return severity_level is
begin
if sel = true then
return a;
@@ -1466,115 +1469,115 @@ package body common_pkg is
end;
-- sel_n : boolean
- function sel_n(sel : natural; a, b, c : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : boolean) return boolean is
constant c_arr : t_nat_boolean_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : integer
- function sel_n(sel : natural; a, b, c : integer) return integer is
+ function sel_n (sel : natural; a, b, c : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i);
begin
return c_arr(sel);
end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : integer) return integer is
constant c_arr : t_nat_integer_arr := (a, b, c, d, e, f, g, h, i, j);
begin
return c_arr(sel);
end;
-- sel_n : string
- function sel_n(sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
- function sel_n(sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
- function sel_n(sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
- function sel_n(sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
- function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
-
- function array_init(init : std_logic; nof : natural) return std_logic_vector is
+ function sel_n (sel : natural; a, b : string) return string is begin if sel = 0 then return a ; else return b; end if; end;
+ function sel_n (sel : natural; a, b, c : string) return string is begin if sel < 2 then return sel_n(sel, a, b ); else return c; end if; end;
+ function sel_n (sel : natural; a, b, c, d : string) return string is begin if sel < 3 then return sel_n(sel, a, b, c ); else return d; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e : string) return string is begin if sel < 4 then return sel_n(sel, a, b, c, d ); else return e; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f : string) return string is begin if sel < 5 then return sel_n(sel, a, b, c, d, e ); else return f; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g : string) return string is begin if sel < 6 then return sel_n(sel, a, b, c, d, e, f ); else return g; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h : string) return string is begin if sel < 7 then return sel_n(sel, a, b, c, d, e, f, g ); else return h; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i : string) return string is begin if sel < 8 then return sel_n(sel, a, b, c, d, e, f, g, h ); else return i; end if; end;
+ function sel_n (sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
+
+ function array_init (init : std_logic; nof : natural) return std_logic_vector is
variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1583,7 +1586,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init : boolean; nof : natural) return t_nat_boolean_arr is
+ function array_init (init : boolean; nof : natural) return t_nat_boolean_arr is
variable v_arr : t_nat_boolean_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1592,7 +1595,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_natural_arr is
+ function array_init (init, nof : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1601,7 +1604,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof : natural) return t_nat_natural_arr is
+ function array_init (init, nof : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
begin
for I in v_arr'range loop
@@ -1610,7 +1613,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_natural_arr is
+ function array_init (init, nof, incr : natural) return t_natural_arr is
variable v_arr : t_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1622,7 +1625,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : natural) return t_nat_natural_arr is
+ function array_init (init, nof, incr : natural) return t_nat_natural_arr is
variable v_arr : t_nat_natural_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1634,7 +1637,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_16_arr is
+ function array_init (init, nof, incr : integer) return t_slv_16_arr is
variable v_arr : t_slv_16_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1646,7 +1649,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, incr : integer) return t_slv_32_arr is
+ function array_init (init, nof, incr : integer) return t_slv_32_arr is
variable v_arr : t_slv_32_arr(0 to nof - 1);
variable v_i : natural;
begin
@@ -1658,7 +1661,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width : natural) return std_logic_vector is
+ function array_init (init, nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1667,7 +1670,7 @@ package body common_pkg is
return v_arr;
end;
- function array_init(init, nof, width, incr : natural) return std_logic_vector is
+ function array_init (init, nof, width, incr : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
variable v_i : natural;
begin
@@ -1679,7 +1682,7 @@ package body common_pkg is
return v_arr;
end;
- function array_sinit(init :integer; nof, width : natural) return std_logic_vector is
+ function array_sinit (init :integer; nof, width : natural) return std_logic_vector is
variable v_arr : std_logic_vector(nof * width - 1 downto 0);
begin
for I in 0 to nof - 1 loop
@@ -1688,7 +1691,7 @@ package body common_pkg is
return v_arr;
end;
- function init_slv_64_matrix(nof_a, nof_b, k : integer) return t_slv_64_matrix is
+ function init_slv_64_matrix (nof_a, nof_b, k : integer) return t_slv_64_matrix is
variable v_mat : t_slv_64_matrix(nof_a - 1 downto 0, nof_b - 1 downto 0);
begin
for I in 0 to nof_a - 1 loop
@@ -1700,7 +1703,7 @@ package body common_pkg is
end;
-- Support concatenation of up to 8 slv into 1 slv
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a, b, c, d, e, f, g, h : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a, b, c, d, e, f, g, h : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length + h'length;
variable v_res : std_logic_vector(c_max_w - 1 downto 0) := (others => '0');
variable v_len : natural := 0;
@@ -1716,72 +1719,72 @@ package body common_pkg is
return v_res(v_len - 1 downto 0);
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g, false, a, b, c, d, e, f, g, "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, false, false, a, b, c, d, e, f, "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d, use_e : boolean; a, b, c, d, e : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, use_e, false, false, false, a, b, c, d, e, "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c, use_d : boolean; a, b, c, d : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, use_d, false, false, false, false, a, b, c, d, "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b, use_c : boolean; a, b, c : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, use_c, false, false, false, false, false, a, b, c, "0", "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (use_a, use_b : boolean; a, b : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(use_a, use_b, false, false, false, false, false, false, a, b, "0", "0", "0", "0", "0", "0");
end func_slv_concat;
- function func_slv_concat(a, b, c, d, e, f, g, h : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (a, b, c, d, e, f, g, h : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(true, true, true, true, true, true, true, true, a, b, c, d, e, f, g, h);
end func_slv_concat;
- function func_slv_concat(a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(true, true, true, true, true, true, true, a, b, c, d, e, f, g);
end func_slv_concat;
- function func_slv_concat(a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (a, b, c, d, e, f : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(true, true, true, true, true, true, a, b, c, d, e, f);
end func_slv_concat;
- function func_slv_concat(a, b, c, d, e: std_logic_vector) return std_logic_vector is
+ function func_slv_concat (a, b, c, d, e: std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(true, true, true, true, true, a, b, c, d, e);
end func_slv_concat;
- function func_slv_concat(a, b, c, d : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (a, b, c, d : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(true, true, true, true, a, b, c, d);
end func_slv_concat;
- function func_slv_concat(a, b, c : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (a, b, c : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(true, true, true, a, b, c);
end func_slv_concat;
- function func_slv_concat(a, b : std_logic_vector) return std_logic_vector is
+ function func_slv_concat (a, b : std_logic_vector) return std_logic_vector is
begin
return func_slv_concat(true, true, a, b);
end func_slv_concat;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural) return natural is
variable v_len : natural := 0;
begin
if use_a = true then v_len := v_len + a_w; end if;
@@ -1795,38 +1798,38 @@ package body common_pkg is
return v_len;
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, false, a_w, b_w, c_w, d_w, e_w, f_w, g_w, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, false, false, a_w, b_w, c_w, d_w, e_w, f_w, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, false, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, use_d, false, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, use_c, false, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0, 0);
end func_slv_concat_w;
- function func_slv_concat_w(use_a, use_b : boolean; a_w, b_w : natural) return natural is
+ function func_slv_concat_w (use_a, use_b : boolean; a_w, b_w : natural) return natural is
begin
return func_slv_concat_w(use_a, use_b, false, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, 0);
end func_slv_concat_w;
-- extract slv
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
variable v_w : natural := 0;
variable v_lo : natural := 0;
begin
@@ -1881,97 +1884,97 @@ package body common_pkg is
return vec(v_w - 1 + v_lo downto v_lo); -- extracted slv
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g, false, a_w, b_w, c_w, d_w, e_w, f_w, g_w, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e, use_f : boolean; a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, false, false, a_w, b_w, c_w, d_w, e_w, f_w, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d, use_e : boolean; a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, use_e, false, false, false, a_w, b_w, c_w, d_w, e_w, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c, use_d : boolean; a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, use_d, false, false, false, false, a_w, b_w, c_w, d_w, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b, use_c : boolean; a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, use_c, false, false, false, false, false, a_w, b_w, c_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (use_a, use_b : boolean; a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(use_a, use_b, false, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
- function func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(true, true, true, true, true, true, true, true, a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w, vec, sel);
end func_slv_extract;
- function func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (a_w, b_w, c_w, d_w, e_w, f_w, g_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(true, true, true, true, true, true, true, a_w, b_w, c_w, d_w, e_w, f_w, g_w, vec, sel);
end func_slv_extract;
- function func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (a_w, b_w, c_w, d_w, e_w, f_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(true, true, true, true, true, true, a_w, b_w, c_w, d_w, e_w, f_w, vec, sel);
end func_slv_extract;
- function func_slv_extract(a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (a_w, b_w, c_w, d_w, e_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(true, true, true, true, true, a_w, b_w, c_w, d_w, e_w, vec, sel);
end func_slv_extract;
- function func_slv_extract(a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (a_w, b_w, c_w, d_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(true, true, true, true, a_w, b_w, c_w, d_w, vec, sel);
end func_slv_extract;
- function func_slv_extract(a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (a_w, b_w, c_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(true, true, true, a_w, b_w, c_w, vec, sel);
end func_slv_extract;
- function func_slv_extract(a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
+ function func_slv_extract (a_w, b_w : natural; vec : std_logic_vector; sel : natural) return std_logic_vector is
begin
return func_slv_extract(true, true, a_w, b_w, vec, sel);
end func_slv_extract;
- function TO_UINT(vec : std_logic_vector) return natural is
+ function TO_UINT (vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
end;
- function TO_SINT(vec : std_logic_vector) return integer is
+ function TO_SINT (vec : std_logic_vector) return integer is
begin
return to_integer(signed(vec));
end;
- function TO_UVEC(dec, w : natural) return std_logic_vector is
+ function TO_UVEC (dec, w : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(dec, w));
end;
- function TO_SVEC(dec, w : integer) return std_logic_vector is
+ function TO_SVEC (dec, w : integer) return std_logic_vector is
begin
return std_logic_vector(to_signed(dec, w));
end;
- function TO_SVEC_32(dec : integer) return std_logic_vector is
+ function TO_SVEC_32 (dec : integer) return std_logic_vector is
begin
return TO_SVEC(dec, 32);
end;
- function TO_UINT(udec : real; w, resolution_w : integer) return natural is
+ function TO_UINT (udec : real; w, resolution_w : integer) return natural is
constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
constant c_ureal : real := ROUND(udec / c_resolution); -- rounds away from zero
begin
@@ -1983,7 +1986,7 @@ package body common_pkg is
end if;
end;
- function TO_SINT(sdec : real; w, resolution_w : integer) return integer is
+ function TO_SINT (sdec : real; w, resolution_w : integer) return integer is
constant c_max : real := 2.0**REAL(w - 1) - 1.0;
constant c_min : real := -2.0**REAL(w - 1);
constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
@@ -2003,7 +2006,7 @@ package body common_pkg is
end if;
end;
- function TO_UVEC(udec : real; w, resolution_w : integer) return std_logic_vector is
+ function TO_UVEC (udec : real; w, resolution_w : integer) return std_logic_vector is
-- Determine range that fits w bits
constant c_uvec_max : std_logic_vector(w - 1 downto 0) := (others => '1');
constant c_max : real := 2.0**REAL(w) - 1.0;
@@ -2048,7 +2051,7 @@ package body common_pkg is
end if;
end;
- function TO_SVEC(sdec : real; w, resolution_w : integer) return std_logic_vector is
+ function TO_SVEC (sdec : real; w, resolution_w : integer) return std_logic_vector is
-- Determine range that fits w bits
constant c_svec_max : std_logic_vector(w - 1 downto 0) := '0' & (w - 2 downto 0 => '1');
constant c_svec_min : std_logic_vector(w - 1 downto 0) := '1' & (w - 2 downto 0 => '0');
@@ -2056,8 +2059,8 @@ package body common_pkg is
constant c_min : real := -2.0**REAL(w - 1);
constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
constant c_sreal : real := ROUND(sdec / c_resolution); -- rounds away from zero
- -- Convert to positive using TO_UVEC, so if sdec is negative, then
- -- negate sdec to have positive c_udec.
+ -- Convert to positive using TO_UVEC, so if sdec is negative, then
+ -- negate sdec to have positive c_udec.
constant c_pos : boolean := sdec >= 0.0;
constant c_udec : real := sel_a_b(c_pos, sdec, -sdec);
-- Determine SLV value for positive REAL, use w+1 to fit negate of most negative value
@@ -2078,7 +2081,7 @@ package body common_pkg is
end if;
end;
- function TO_UREAL(uvec : std_logic_vector) return real is
+ function TO_UREAL (uvec : std_logic_vector) return real is
constant c_len : natural := uvec'length;
constant c_uvec : std_logic_vector(c_len - 1 downto 0) := uvec;
variable v_real : real := 0.0;
@@ -2092,7 +2095,7 @@ package body common_pkg is
return v_real;
end;
- function TO_SREAL(svec : std_logic_vector) return real is
+ function TO_SREAL (svec : std_logic_vector) return real is
-- Increase vector length by +1 so the c_uvec can also fit abs() of most negative is -1 * -2**(c_len-1)
constant c_len : natural := svec'length + 1;
constant c_svec : std_logic_vector(c_len - 1 downto 0) := RESIZE_SVEC(svec, c_len);
@@ -2109,14 +2112,14 @@ package body common_pkg is
-- Fixed point format
-- . https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
- function TO_UREAL(uvec : std_logic_vector; resolution_w : integer) return real is
+ function TO_UREAL (uvec : std_logic_vector; resolution_w : integer) return real is
begin
-- First convert as unsigned integer, then scale to real. See TO_SREAL()
-- for interpretation of resolution_w
return TO_UREAL(uvec) / 2.0**REAL(resolution_w);
end;
- function TO_SREAL(svec : std_logic_vector; resolution_w : integer) return real is
+ function TO_SREAL (svec : std_logic_vector; resolution_w : integer) return real is
begin
-- First convert as unsigned integer, then scale to real
-- . The resolution_w is the number of bits that LSbit 0 in svec(HIGH-1 DOWNTO 0) is after
@@ -2129,13 +2132,13 @@ package body common_pkg is
end;
- function RESIZE_NUM(u : unsigned; w : natural) return unsigned is
+ function RESIZE_NUM (u : unsigned; w : natural) return unsigned is
begin
-- left extend with '0' or remove MSbits and keep LS part (= u[w-1:0])
return resize(u, w); -- same as RESIZE for UNSIGNED
end;
- function RESIZE_NUM(s : signed; w : natural) return signed is
+ function RESIZE_NUM (s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
if w > s'length then
@@ -2150,58 +2153,58 @@ package body common_pkg is
end if;
end;
- function RESIZE_UVEC(sl : std_logic; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (sl : std_logic; w : natural) return std_logic_vector is
variable v_slv0 : std_logic_vector(w - 1 downto 1) := (others => '0');
begin
return v_slv0 & sl;
end;
- function RESIZE_UVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_UVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(vec), w));
end;
- function RESIZE_SVEC(vec : std_logic_vector; w : natural) return std_logic_vector is
+ function RESIZE_SVEC (vec : std_logic_vector; w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(vec), w));
end;
- function RESIZE_UINT(u : integer; w : natural) return integer is
+ function RESIZE_UINT (u : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_UVEC(u, c_word_w);
return TO_UINT(v(w - 1 downto 0));
end;
- function RESIZE_SINT(s : integer; w : natural) return integer is
+ function RESIZE_SINT (s : integer; w : natural) return integer is
variable v : std_logic_vector(c_word_w - 1 downto 0);
begin
v := TO_SVEC(s, c_word_w);
return TO_SINT(v(w - 1 downto 0));
end;
- function RESIZE_UVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_UVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, 32);
end;
- function RESIZE_SVEC_32(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_SVEC_32 (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, 32);
end;
-- Negate vec, assume value range fits -+c_max, so no logic needed to check for c_min
- function NEGATE_SVEC(vec : std_logic_vector) return std_logic_vector is
+ function NEGATE_SVEC (vec : std_logic_vector) return std_logic_vector is
begin
-- use NUMERIC_STD to avoid range limitation of 32b INTEGER
-- default approach
return std_logic_vector(-signed(vec)); -- negate by multiplying by -1
- -- alternative equivalent approach
- -- RETURN INCR_UVEC(NOT vec, 1); -- negate by using two complement negate
+ -- alternative equivalent approach
+ -- RETURN INCR_UVEC(NOT vec, 1); -- negate by using two complement negate
end;
-- Negate vec, but avoid overflow by forcing -min to +max. Use w <= vec'LENGTH.
- function NEGATE_SVEC(vec : std_logic_vector; w : integer) return std_logic_vector is
+ function NEGATE_SVEC (vec : std_logic_vector; w : integer) return std_logic_vector is
constant c_max : integer := 2**(w - 1) - 1;
constant c_min : integer := -2**(w - 1);
constant c_vec_w : natural := vec'length;
@@ -2217,7 +2220,7 @@ package body common_pkg is
end if;
end;
- function INCR_UVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
variable v_dec : integer;
begin
if dec < 0 then
@@ -2229,63 +2232,63 @@ package body common_pkg is
end if;
end;
- function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector is
+ function INCR_UVEC (vec : std_logic_vector; dec : unsigned) return std_logic_vector is
begin
return std_logic_vector(unsigned(vec) + dec);
end;
- function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : integer) return std_logic_vector is
begin
return std_logic_vector(signed(vec) + dec); -- uses function "+" (L : SIGNED, R : INTEGER)
end;
- function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector is
+ function INCR_SVEC (vec : std_logic_vector; dec : signed) return std_logic_vector is
begin
return std_logic_vector(signed(vec) + dec);
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) + signed(r_vec));
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(signed(l_vec), res_w) - signed(r_vec));
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) + unsigned(r_vec));
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector is
begin
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
- function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_SVEC(l_vec, r_vec, l_vec'length);
end;
- function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function ADD_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_UVEC(l_vec, r_vec, l_vec'length);
end;
- function SUB_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function SUB_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return SUB_UVEC(l_vec, r_vec, l_vec'length);
end;
- function MULT_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function MULT_SVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
constant c_product_w : natural := l_vec'length + r_vec'length;
variable v_product : std_logic_vector(c_product_w - 1 downto 0);
begin
@@ -2293,7 +2296,7 @@ package body common_pkg is
return v_product;
end;
- function MULT_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
+ function MULT_UVEC (l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
constant c_product_w : natural := l_vec'length + r_vec'length;
variable v_product : std_logic_vector(c_product_w - 1 downto 0);
begin
@@ -2301,18 +2304,18 @@ package body common_pkg is
return v_product;
end;
- function COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_REAL (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_re * b_re - a_im * b_im);
end;
- function COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : integer) return integer is
+ function COMPLEX_MULT_IMAG (a_re, a_im, b_re, b_im : integer) return integer is
begin
return (a_im * b_re + a_re * b_im);
end;
- function COMPLEX_RADIUS(re, im : real) return real is
+ function COMPLEX_RADIUS (re, im : real) return real is
begin
-- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0.
-- Must must use brackets (ABS()) to avoid compile error.
@@ -2320,12 +2323,12 @@ package body common_pkg is
return SQRT((abs(re))**2.0 + (abs(im))**2.0);
end;
- function COMPLEX_RADIUS(re, im : integer) return real is
+ function COMPLEX_RADIUS (re, im : integer) return real is
begin
return COMPLEX_RADIUS(real(re), real(im));
end;
- function COMPLEX_PHASE(re, im : real; radians : boolean) return real is
+ function COMPLEX_PHASE (re, im : real; radians : boolean) return real is
begin
if radians = true then
return ATAN2(Y => im, X => re);
@@ -2334,22 +2337,22 @@ package body common_pkg is
end if;
end;
- function COMPLEX_PHASE(re, im : integer; radians : boolean) return real is
+ function COMPLEX_PHASE (re, im : integer; radians : boolean) return real is
begin
return COMPLEX_PHASE(real(re), real(im), radians);
end;
- function COMPLEX_PHASE(re, im : real) return real is
+ function COMPLEX_PHASE (re, im : real) return real is
begin
return COMPLEX_PHASE(re, im, false);
end;
- function COMPLEX_PHASE(re, im : integer) return real is
+ function COMPLEX_PHASE (re, im : integer) return real is
begin
return COMPLEX_PHASE(real(re), real(im), false);
end;
- function COMPLEX_RE(ampl, phase : real; radians : boolean) return real is
+ function COMPLEX_RE (ampl, phase : real; radians : boolean) return real is
begin
if radians = true then
return ampl * COS(phase);
@@ -2358,22 +2361,22 @@ package body common_pkg is
end if;
end;
- function COMPLEX_RE(ampl, phase : integer; radians : boolean) return real is
+ function COMPLEX_RE (ampl, phase : integer; radians : boolean) return real is
begin
return COMPLEX_RE(real(ampl), real(phase), radians);
end;
- function COMPLEX_RE(ampl, phase : real) return real is
+ function COMPLEX_RE (ampl, phase : real) return real is
begin
return COMPLEX_RE(ampl, phase, false);
end;
- function COMPLEX_RE(ampl, phase : integer) return real is
+ function COMPLEX_RE (ampl, phase : integer) return real is
begin
return COMPLEX_RE(real(ampl), real(phase), false);
end;
- function COMPLEX_IM(ampl, phase : real; radians : boolean) return real is
+ function COMPLEX_IM (ampl, phase : real; radians : boolean) return real is
begin
if radians = true then
return ampl * SIN(phase);
@@ -2382,23 +2385,23 @@ package body common_pkg is
end if;
end;
- function COMPLEX_IM(ampl, phase : integer; radians : boolean) return real is
+ function COMPLEX_IM (ampl, phase : integer; radians : boolean) return real is
begin
return COMPLEX_IM(real(ampl), real(phase), radians);
end;
- function COMPLEX_IM(ampl, phase : real) return real is
+ function COMPLEX_IM (ampl, phase : real) return real is
begin
return COMPLEX_IM(ampl, phase, false);
end;
- function COMPLEX_IM(ampl, phase : integer) return real is
+ function COMPLEX_IM (ampl, phase : integer) return real is
begin
return COMPLEX_IM(real(ampl), real(phase), false);
end;
- function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(unsigned(vec), -shift)); -- fill zeros from right
@@ -2407,7 +2410,7 @@ package body common_pkg is
end if;
end;
- function SHIFT_SVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function SHIFT_SVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(SHIFT_LEFT(signed(vec), -shift)); -- same as SHIFT_LEFT for UNSIGNED
@@ -2416,14 +2419,14 @@ package body common_pkg is
end if;
end;
- function ROTATE_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
+ function ROTATE_UVEC (vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
return std_logic_vector(ROTATE_LEFT(unsigned(vec), -shift)); -- /<-- vec <--\
- -- \---------->/
+ -- \---------->/
else
return std_logic_vector(ROTATE_RIGHT(unsigned(vec), shift)); -- /--> vec -->\
- -- \<----------/
+ -- \<----------/
end if;
end;
@@ -2444,24 +2447,24 @@ package body common_pkg is
-- The offset_binary() mapping can be done and undone both ways.
-- The offset_binary() mapping to two-complement binary yields a DC offset
-- of -0.5 Lsb.
- function offset_binary(a : std_logic_vector) return std_logic_vector is
+ function offset_binary (a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
- function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function truncate (vec : std_logic_vector; n : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
- function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -2472,7 +2475,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function truncate_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_trunc_w : natural := c_vec_w - n;
variable v_trunc : std_logic_vector(c_trunc_w - 1 downto 0);
@@ -2483,7 +2486,7 @@ package body common_pkg is
return v_res;
end;
- function scale(vec : std_logic_vector; n: natural) return std_logic_vector is
+ function scale (vec : std_logic_vector; n: natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_res : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -2492,7 +2495,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_uvec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -2503,7 +2506,7 @@ package body common_pkg is
return v_res;
end;
- function scale_and_resize_svec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
+ function scale_and_resize_svec (vec : std_logic_vector; n, w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
constant c_scale_w : natural := c_vec_w + n;
variable v_scale : std_logic_vector(c_scale_w - 1 downto 0) := (others => '0');
@@ -2514,7 +2517,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_uvec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_uvec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -2527,7 +2530,7 @@ package body common_pkg is
return v_res;
end;
- function truncate_or_resize_svec(vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
+ function truncate_or_resize_svec (vec : std_logic_vector; b : boolean; w : natural) return std_logic_vector is
constant c_vec_w : natural := vec'length;
variable c_n : integer := c_vec_w - w;
variable v_res : std_logic_vector(w - 1 downto 0);
@@ -2606,7 +2609,7 @@ package body common_pkg is
-- maximum product is -8*-8=+64 <= 127-8, so wrapping due to rounding
-- overflow will never occur.
- function s_round(vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector is
-- # Round half away from zero when even = FALSE, else round half to even.
-- # Round half to even algorithm:
-- # vec: -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5
@@ -2653,18 +2656,18 @@ package body common_pkg is
return std_logic_vector(v_out);
end;
- function s_round(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
begin
return s_round(vec, n, clip, false); -- no round half to even
end;
- function s_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function s_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return s_round(vec, n, false); -- no round clip
end;
-- for unsigned round half away and round half up are equivalent
- function u_round(vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural; clip, even : boolean) return std_logic_vector is
constant c_in_w : natural := vec'length;
constant c_out_w : natural := vec'length - n;
variable in_vec : std_logic_vector(c_in_w downto 0);
@@ -2676,41 +2679,41 @@ package body common_pkg is
return out_vec(c_out_w - 1 downto 0);
end;
- function u_round(vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural; clip : boolean) return std_logic_vector is
begin
return u_round(vec, n, clip, false); -- no round half to even
end;
- function u_round(vec : std_logic_vector; n : natural) return std_logic_vector is
+ function u_round (vec : std_logic_vector; n : natural) return std_logic_vector is
begin
return u_round(vec, n, false); -- no round clip
end;
- function u_to_s(u : natural; w : natural) return integer is
+ function u_to_s (u : natural; w : natural) return integer is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_u(w - 1 downto 0));
end;
- function s_to_u(s : integer; w : natural) return natural is
+ function s_to_u (s : integer; w : natural) return natural is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_s(w - 1 downto 0));
end;
- function u_wrap(u : natural; w : natural) return natural is
+ function u_wrap (u : natural; w : natural) return natural is
variable v_u : std_logic_vector(31 downto 0) := TO_UVEC(u, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_UINT(v_u(w - 1 downto 0));
end;
- function s_wrap(s : integer; w : natural) return integer is
+ function s_wrap (s : integer; w : natural) return integer is
variable v_s : std_logic_vector(31 downto 0) := TO_SVEC(s, 32); -- via 32 bit word to avoid NUMERIC_STD.TO_SIGNED: vector truncated warming
begin
return TO_SINT(v_s(w - 1 downto 0));
end;
- function u_clip(u : natural; max : natural) return natural is
+ function u_clip (u : natural; max : natural) return natural is
begin
if u > max then
return max;
@@ -2719,7 +2722,7 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural; min : integer) return integer is
+ function s_clip (s : integer; max : natural; min : integer) return integer is
begin
if s < min then
return min;
@@ -2732,12 +2735,12 @@ package body common_pkg is
end if;
end;
- function s_clip(s : integer; max : natural) return integer is
+ function s_clip (s : integer; max : natural) return integer is
begin
return s_clip(s, max, -max);
end;
- function hton(a : std_logic_vector; w, sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; w, sz : natural) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a; -- map a to range [h:0]
variable v_b : std_logic_vector(a'length - 1 downto 0) := a; -- default b = a
variable vL : natural;
@@ -2753,28 +2756,28 @@ package body common_pkg is
return v_b;
end function;
- function hton(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function hton (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, c_byte_w, sz); -- symbol width w = c_byte_w = 8
end function;
- function hton(a : std_logic_vector) return std_logic_vector is
+ function hton (a : std_logic_vector) return std_logic_vector is
constant c_sz : natural := a'length / c_byte_w;
begin
return hton(a, c_byte_w, c_sz); -- symbol width w = c_byte_w = 8
end function;
- function ntoh(a : std_logic_vector; sz : natural) return std_logic_vector is
+ function ntoh (a : std_logic_vector; sz : natural) return std_logic_vector is
begin
return hton(a, sz); -- i.e. ntoh() = hton()
end function;
- function ntoh(a : std_logic_vector) return std_logic_vector is
+ function ntoh (a : std_logic_vector) return std_logic_vector is
begin
return hton(a); -- i.e. ntoh() = hton()
end function;
- function flip(a : std_logic_vector) return std_logic_vector is
+ function flip (a : std_logic_vector) return std_logic_vector is
variable v_a : std_logic_vector(a'length - 1 downto 0) := a;
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2784,12 +2787,12 @@ package body common_pkg is
return v_b;
end;
- function flip(a, w : natural) return natural is
+ function flip (a, w : natural) return natural is
begin
return TO_UINT(flip(TO_UVEC(a, w)));
end;
- function flip(a : t_slv_32_arr) return t_slv_32_arr is
+ function flip (a : t_slv_32_arr) return t_slv_32_arr is
variable v_a : t_slv_32_arr(a'length - 1 downto 0) := a;
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
@@ -2799,7 +2802,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_integer_arr) return t_integer_arr is
+ function flip (a : t_integer_arr) return t_integer_arr is
variable v_a : t_integer_arr(a'length - 1 downto 0) := a;
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
@@ -2809,7 +2812,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_natural_arr) return t_natural_arr is
+ function flip (a : t_natural_arr) return t_natural_arr is
variable v_a : t_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
@@ -2819,7 +2822,7 @@ package body common_pkg is
return v_b;
end;
- function flip(a : t_nat_natural_arr) return t_nat_natural_arr is
+ function flip (a : t_nat_natural_arr) return t_nat_natural_arr is
variable v_a : t_nat_natural_arr(a'length - 1 downto 0) := a;
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
@@ -2829,7 +2832,7 @@ package body common_pkg is
return v_b;
end;
- function transpose(a : std_logic_vector; row, col : natural) return std_logic_vector is
+ function transpose (a : std_logic_vector; row, col : natural) return std_logic_vector is
variable vIn : std_logic_vector(a'length - 1 downto 0);
variable vOut : std_logic_vector(a'length - 1 downto 0);
begin
@@ -2843,7 +2846,7 @@ package body common_pkg is
return vOut;
end function;
- function transpose(a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
+ function transpose (a, row, col : natural) return natural is -- transpose index a = [i*row+j] to output index [j*col+i]
variable vI : natural;
variable vJ : natural;
begin
@@ -2852,7 +2855,7 @@ package body common_pkg is
return vJ * col + vI;
end;
- function split_w(input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
+ function split_w (input_w: natural; min_out_w: natural; max_out_w: natural) return natural is -- Calculate input_w in multiples as close as possible to max_out_w
-- Examples: split_w(256, 8, 32) = 32; split_w(16, 8, 32) = 16; split_w(72, 8, 32) = 18; -- Input_w must be multiple of 2.
variable r: natural;
begin
@@ -2867,34 +2870,34 @@ package body common_pkg is
end loop;
end;
- function pad(str: string; width: natural; pad_char: character) return string is
+ function pad (str: string; width: natural; pad_char: character) return string is
variable v_str : string(1 to width) := (others => pad_char);
begin
v_str(width - str'length + 1 to width) := str;
return v_str;
end;
- function slice_up(str: string; width: natural; i: natural) return string is
+ function slice_up (str: string; width: natural; i: natural) return string is
begin
return str(i * width + 1 to (i + 1) * width);
end;
-- If the input value is not a multiple of the desired width, the return value is padded with
-- the passed pad value. E.g. if input='10' and desired width is 4, return value is '0010'.
- function slice_up(str: string; width: natural; i: natural; pad_char: character) return string is
+ function slice_up (str: string; width: natural; i: natural; pad_char: character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
- function slice_dn(str: string; width: natural; i: natural) return string is
+ function slice_dn (str: string; width: natural; i: natural) return string is
begin
return str((i + 1) * width - 1 downto i * width);
end;
- function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
+ function nat_arr_to_concat_slv (nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
for i in 0 to nof_elements - 1 loop
@@ -2908,16 +2911,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2930,7 +2934,7 @@ package body common_pkg is
assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
- --synthesis translate_on
+ --synthesis translate_on
end procedure proc_common_fifo_asserts;
@@ -2938,8 +2942,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining (
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2960,7 +2965,7 @@ package body common_pkg is
------------------------------------------------------------------------------
-- Determine whether the stage I and row J index refer to any (active or redundant) 2-input reorder cell instantiation
- function func_common_reorder2_is_there(I, J : natural) return boolean is
+ function func_common_reorder2_is_there (I, J : natural) return boolean is
variable v_odd : boolean;
variable v_even : boolean;
begin
@@ -2970,7 +2975,7 @@ package body common_pkg is
end func_common_reorder2_is_there;
-- Determine whether the stage I and row J index refer to an active 2-input reorder cell instantiation in a reorder network with N stages
- function func_common_reorder2_is_active(I, J, N : natural) return boolean is
+ function func_common_reorder2_is_active (I, J, N : natural) return boolean is
variable v_inst : boolean;
variable v_act : boolean;
begin
@@ -2980,7 +2985,7 @@ package body common_pkg is
end func_common_reorder2_is_active;
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
+ function func_common_reorder2_get_select_index (I, J, N : natural) return integer is
constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
@@ -3002,7 +3007,7 @@ package body common_pkg is
end func_common_reorder2_get_select_index;
-- Get the select setting for the reorder2 cell on stage I and row J in a reorder network with N stages
- function func_common_reorder2_get_select(I, J, N : natural; select_arr : t_natural_arr) return natural is
+ function func_common_reorder2_get_select (I, J, N : natural; select_arr : t_natural_arr) return natural is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -3017,7 +3022,7 @@ package body common_pkg is
end func_common_reorder2_get_select;
-- Determine the inverse of a reorder network by using two reorder networks in series
- function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr is
+ function func_common_reorder2_inverse_select (N : natural; select_arr : t_natural_arr) return t_natural_arr is
constant c_nof_select : natural := select_arr'length;
constant c_select_arr : t_natural_arr(c_nof_select - 1 downto 0) := select_arr; -- force range downto 0
variable v_sel : natural;
@@ -3043,8 +3048,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -3083,9 +3088,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk (
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
@@ -3110,7 +3116,7 @@ package body common_pkg is
end if;
wait for v_speriod / 2;
SCLK <= '1';
- -- Wait for next DCLK
+ -- Wait for next DCLK
end loop;
wait;
end proc_common_dclk_generate_sclk;
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay.vhd b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
index 906cf0d0ec..cf545307b1 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
@@ -26,8 +26,8 @@
-- . Note: pulse_out must have occurured before the next pulse_in can be delayed.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pulse_delay is
generic (
@@ -61,17 +61,17 @@ begin
-- Switch to start counter @ pulse_in, and stop counter @ pulse_out.
-------------------------------------------------------------------------------
u_common_switch : entity work.common_switch
- generic map (
- g_or_high => true,
- g_priority_lo => false
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => pulse_in,
- switch_low => nxt_pulse_out,
- out_level => common_counter_cnt_en
- );
+ generic map (
+ g_or_high => true,
+ g_priority_lo => false
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => pulse_in,
+ switch_low => nxt_pulse_out,
+ out_level => common_counter_cnt_en
+ );
-------------------------------------------------------------------------------
-- Count delay cycles relative to pulse_in
@@ -81,18 +81,18 @@ begin
-- output count value after cnt_en (also 0).
-------------------------------------------------------------------------------
u_common_counter : entity work.common_counter
- generic map (
- g_width => c_pulse_delay_max_width,
- g_init => 1
- )
- port map (
- clk => clk,
- rst => rst,
- cnt_ld => pulse_in, -- Clear (load "1") the counter on every pulse_in
- cnt_en => common_counter_cnt_en,
- load => TO_UVEC(1, c_pulse_delay_max_width),
- count => common_counter_count
- );
+ generic map (
+ g_width => c_pulse_delay_max_width,
+ g_init => 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ cnt_ld => pulse_in, -- Clear (load "1") the counter on every pulse_in
+ cnt_en => common_counter_cnt_en,
+ load => TO_UVEC(1, c_pulse_delay_max_width),
+ count => common_counter_count
+ );
-------------------------------------------------------------------------------
-- Assign nxt_pulse_out
@@ -101,7 +101,7 @@ begin
nxt_pulse_delay_reg <= pulse_delay when pulse_in = '1' else pulse_delay_reg;
nxt_pulse_out <= pulse_in when pulse_delay = TO_UVEC(0, c_pulse_delay_max_width) else -- 0 cycles delay (pulse_delay_reg not valid yet; using pulse_delay)
- '1' when common_counter_count = pulse_delay_reg else '0'; -- >=1 cycles delay (so pulse_delay_reg will contain registered pulse_delay)
+ '1' when common_counter_count = pulse_delay_reg else '0'; -- >=1 cycles delay (so pulse_delay_reg will contain registered pulse_delay)
-------------------------------------------------------------------------------
-- Optional output register
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
index 4e51dd1e6b..bae2ea70b0 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
@@ -27,15 +27,15 @@
-- Set pulse_delay between incoming and outgoing pulse, in units of dp_clk cycles (5ns)
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_pulse_delay_reg is
generic (
g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and pulse_clk are the same, else use TRUE to cross the clock domain
g_pulse_delay_max : natural := 0 -- Maximum number of clk cycles that pulse can be delayed
- );
+ );
port (
pulse_clk : in std_logic;
pulse_rst : in std_logic;
@@ -53,11 +53,13 @@ architecture rtl of common_pulse_delay_reg is
constant c_nof_mm_regs : natural := 1;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_mm_regs),
- dat_w => c_word_w,
- nof_dat => c_nof_mm_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_mm_regs),
+ dat_w => c_word_w,
+ nof_dat => c_nof_mm_regs,
+ init_sl => '0'
+ );
signal mm_pulse_delay : std_logic_vector(ceil_log2(g_pulse_delay_max) - 1 downto 0);
@@ -128,16 +130,16 @@ begin
gen_common_reg_cross_domain : if g_cross_clock_domain = true generate
u_common_reg_cross_domain : entity work.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_pulse_delay,
- in_done => OPEN,
- out_rst => pulse_rst,
- out_clk => pulse_clk,
- out_dat => pulse_delay,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_pulse_delay,
+ in_done => OPEN,
+ out_rst => pulse_rst,
+ out_clk => pulse_clk,
+ out_dat => pulse_delay,
+ out_new => open
+ );
end generate; -- gen_common_reg_cross_domain
diff --git a/libraries/base/common/src/vhdl/common_pulse_extend.vhd b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
index 05cf366e99..7719929406 100644
--- a/libraries/base/common/src/vhdl/common_pulse_extend.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Extend the active high time of a pulse
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_pulser.vhd b/libraries/base/common/src/vhdl/common_pulser.vhd
index b6b6c7efee..fdb08b64b1 100644
--- a/libraries/base/common/src/vhdl/common_pulser.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Output a one cycle pulse every period
-- Description:
@@ -87,17 +87,17 @@ begin
cnt_clr <= pulse_clr or cnt_period;
u_cnt : entity common_lib.common_counter
- generic map (
- g_init => c_pulse_init,
- g_width => c_pulse_period_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_init => c_pulse_init,
+ g_width => c_pulse_period_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
index 20b4ac30b8..5540dfc914 100644
--- a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide timing pulses for interval 1 us, 1 ms and 1 s
@@ -77,45 +77,45 @@ begin
end process;
u_common_pulser_us : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_us,
- g_pulse_phase => g_pulse_us - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => '1',
- pulse_clr => sync,
- pulse_out => pulse_us_pp
- );
+ generic map (
+ g_pulse_period => g_pulse_us,
+ g_pulse_phase => g_pulse_us - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => '1',
+ pulse_clr => sync,
+ pulse_out => pulse_us_pp
+ );
u_common_pulser_ms : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_ms,
- g_pulse_phase => g_pulse_ms - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_us_pp,
- pulse_clr => sync,
- pulse_out => pulse_ms_p
- );
+ generic map (
+ g_pulse_period => g_pulse_ms,
+ g_pulse_phase => g_pulse_ms - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_us_pp,
+ pulse_clr => sync,
+ pulse_out => pulse_ms_p
+ );
u_common_pulser_s : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_s,
- g_pulse_phase => g_pulse_s - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_ms_p,
- pulse_clr => sync,
- pulse_out => pulse_s_reg
- );
+ generic map (
+ g_pulse_period => g_pulse_s,
+ g_pulse_phase => g_pulse_s - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_ms_p,
+ pulse_clr => sync,
+ pulse_out => pulse_s_reg
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
index b158278dca..d40d4f05e0 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_cr_cw is
generic (
@@ -59,30 +59,30 @@ begin
-- Use port b only for read in read clock domain
u_cr_cw : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst_a => wr_rst,
- rst_b => rd_rst,
- clk_a => wr_clk,
- clk_b => rd_clk,
- clken_a => wr_clken,
- clken_b => rd_clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => wr_rst,
+ rst_b => rd_rst,
+ clk_a => wr_clk,
+ clk_b => rd_clk,
+ clken_a => wr_clken,
+ clken_b => rd_clken,
+ wr_en_a => wr_en,
+ wr_en_b => '0',
+ wr_dat_a => wr_dat,
+ wr_dat_b => (others => '0'),
+ adr_a => wr_adr,
+ adr_b => rd_adr,
+ rd_en_a => '0',
+ rd_en_b => rd_en,
+ rd_dat_a => OPEN,
+ rd_dat_b => rd_dat,
+ rd_val_a => OPEN,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
index 5c39e57838..20cfddd5fd 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_cr_cw_ratio is
generic (
@@ -60,31 +60,31 @@ begin
-- Use port b only for read in read clock domain
u_cr_cw : entity work.common_ram_crw_crw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_a => g_ram_wr,
- g_ram_b => g_ram_rd,
- g_init_file => g_init_file
- )
- port map (
- rst_a => wr_rst,
- rst_b => rd_rst,
- clk_a => wr_clk,
- clk_b => rd_clk,
- clken_a => wr_clken,
- clken_b => rd_clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_a => g_ram_wr,
+ g_ram_b => g_ram_rd,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => wr_rst,
+ rst_b => rd_rst,
+ clk_a => wr_clk,
+ clk_b => rd_clk,
+ clken_a => wr_clken,
+ clken_b => rd_clken,
+ wr_en_a => wr_en,
+ wr_en_b => '0',
+ wr_dat_a => wr_dat,
+ wr_dat_b => (others => '0'),
+ adr_a => wr_adr,
+ adr_b => rd_adr,
+ rd_en_a => '0',
+ rd_en_b => rd_en,
+ rd_dat_a => OPEN,
+ rd_dat_b => rd_dat,
+ rd_val_a => OPEN,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
index 1e75acda70..03e34b1c3a 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_cr is
generic (
@@ -63,30 +63,30 @@ begin
-- Use port b for read only in ST clock domain
u_crw_cr : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst_a => mm_rst,
- rst_b => st_rst,
- clk_a => mm_clk,
- clk_b => st_clk,
- clken_a => mm_clken,
- clken_b => st_clken,
- wr_en_a => mm_wr_en,
- wr_en_b => '0',
- wr_dat_a => mm_wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => mm_adr,
- adr_b => st_adr,
- rd_en_a => mm_rd_en,
- rd_en_b => st_rd_en,
- rd_dat_a => mm_rd_dat,
- rd_dat_b => st_rd_dat,
- rd_val_a => mm_rd_val,
- rd_val_b => st_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => mm_rst,
+ rst_b => st_rst,
+ clk_a => mm_clk,
+ clk_b => st_clk,
+ clken_a => mm_clken,
+ clken_b => st_clken,
+ wr_en_a => mm_wr_en,
+ wr_en_b => '0',
+ wr_dat_a => mm_wr_dat,
+ wr_dat_b => (others => '0'),
+ adr_a => mm_adr,
+ adr_b => st_adr,
+ rd_en_a => mm_rd_en,
+ rd_en_b => st_rd_en,
+ rd_dat_a => mm_rd_dat,
+ rd_dat_b => st_rd_dat,
+ rd_val_a => mm_rd_val,
+ rd_val_b => st_rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
index d0fca90bc6..e2460d4a65 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib, tech_memory_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_crw is
generic (
@@ -79,80 +79,80 @@ begin
-- memory access
gen_true_dual_port : if g_true_dual_port = true generate
u_ram : entity tech_memory_lib.tech_memory_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_adr_w => g_ram.adr_w,
- g_dat_w => g_ram.dat_w,
- g_nof_words => g_ram.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map (
- clock_a => clk_a,
- clock_b => clk_b,
- enable_a => clken_a,
- enable_b => clken_b,
- wren_a => wr_en_a,
- wren_b => wr_en_b,
- data_a => wr_dat_a,
- data_b => wr_dat_b,
- address_a => adr_a,
- address_b => adr_b,
- q_a => ram_rd_dat_a,
- q_b => ram_rd_dat_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map (
+ clock_a => clk_a,
+ clock_b => clk_b,
+ enable_a => clken_a,
+ enable_b => clken_b,
+ wren_a => wr_en_a,
+ wren_b => wr_en_b,
+ data_a => wr_dat_a,
+ data_b => wr_dat_b,
+ address_a => adr_a,
+ address_b => adr_b,
+ q_a => ram_rd_dat_a,
+ q_b => ram_rd_dat_b
+ );
end generate;
gen_simple_dual_port : if g_true_dual_port = false generate
u_ram : entity tech_memory_lib.tech_memory_ram_cr_cw
- generic map (
- g_technology => g_technology,
- g_adr_w => g_ram.adr_w,
- g_dat_w => g_ram.dat_w,
- g_nof_words => g_ram.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map
(
- wrclock => clk_a,
- wrclocken => clken_a,
- wren => wr_en_a,
- wraddress => adr_a,
- data => wr_dat_a,
- rdclock => clk_b,
- rdclocken => clken_b,
- rdaddress => adr_b,
- q => ram_rd_dat_b
- );
+ wrclock => clk_a,
+ wrclocken => clken_a,
+ wren => wr_en_a,
+ wraddress => adr_a,
+ data => wr_dat_a,
+ rdclock => clk_b,
+ rdclocken => clken_b,
+ rdaddress => adr_b,
+ q => ram_rd_dat_b
+ );
end generate;
-- read output
u_pipe_a : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram.dat_w,
- g_out_dat_w => g_ram.dat_w
- )
- port map (
- clk => clk_a,
- clken => clken_a,
- in_dat => ram_rd_dat_a,
- out_dat => rd_dat_a
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => clk_a,
+ clken => clken_a,
+ in_dat => ram_rd_dat_a,
+ out_dat => rd_dat_a
+ );
u_pipe_b : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram.dat_w,
- g_out_dat_w => g_ram.dat_w
- )
- port map (
- clk => clk_b,
- clken => clken_b,
- in_dat => ram_rd_dat_b,
- out_dat => rd_dat_b
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => clk_b,
+ clken => clken_b,
+ in_dat => ram_rd_dat_b,
+ out_dat => rd_dat_b
+ );
-- rd_val control
ram_rd_en_a(0) <= rd_en_a;
@@ -162,29 +162,29 @@ begin
rd_val_b <= ram_rd_val_b(0);
u_rd_val_a : entity work.common_pipeline
- generic map (
- g_pipeline => g_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk_a,
- clken => clken_a,
- in_dat => ram_rd_en_a,
- out_dat => ram_rd_val_a
- );
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk_a,
+ clken => clken_a,
+ in_dat => ram_rd_en_a,
+ out_dat => ram_rd_val_a
+ );
u_rd_val_b : entity work.common_pipeline
- generic map (
- g_pipeline => g_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk_b,
- clken => clken_b,
- in_dat => ram_rd_en_b,
- out_dat => ram_rd_val_b
- );
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk_b,
+ clken => clken_b,
+ in_dat => ram_rd_en_b,
+ out_dat => ram_rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
index c86ae8119d..d673d3ad88 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib, tech_memory_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_crw_ratio is
generic (
@@ -84,58 +84,58 @@ begin
-- memory access
u_ramk : entity tech_memory_lib.tech_memory_ram_crwk_crw
- generic map (
- g_technology => g_technology,
- g_adr_a_w => g_ram_a.adr_w,
- g_adr_b_w => g_ram_b.adr_w,
- g_dat_a_w => g_ram_a.dat_w,
- g_dat_b_w => g_ram_b.dat_w,
- g_nof_words_a => g_ram_a.nof_dat,
- g_nof_words_b => g_ram_b.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map (
- clock_a => clk_a,
- clock_b => clk_b,
- enable_a => clken_a,
- enable_b => clken_b,
- wren_a => wr_en_a,
- wren_b => wr_en_b,
- data_a => wr_dat_a,
- data_b => wr_dat_b,
- address_a => adr_a,
- address_b => adr_b,
- q_a => ram_rd_dat_a,
- q_b => ram_rd_dat_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_adr_a_w => g_ram_a.adr_w,
+ g_adr_b_w => g_ram_b.adr_w,
+ g_dat_a_w => g_ram_a.dat_w,
+ g_dat_b_w => g_ram_b.dat_w,
+ g_nof_words_a => g_ram_a.nof_dat,
+ g_nof_words_b => g_ram_b.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map (
+ clock_a => clk_a,
+ clock_b => clk_b,
+ enable_a => clken_a,
+ enable_b => clken_b,
+ wren_a => wr_en_a,
+ wren_b => wr_en_b,
+ data_a => wr_dat_a,
+ data_b => wr_dat_b,
+ address_a => adr_a,
+ address_b => adr_b,
+ q_a => ram_rd_dat_a,
+ q_b => ram_rd_dat_b
+ );
-- read output
u_pipe_a : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram_a.dat_w,
- g_out_dat_w => g_ram_a.dat_w
- )
- port map (
- clk => clk_a,
- clken => clken_a,
- in_dat => ram_rd_dat_a,
- out_dat => rd_dat_a
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram_a.dat_w,
+ g_out_dat_w => g_ram_a.dat_w
+ )
+ port map (
+ clk => clk_a,
+ clken => clken_a,
+ in_dat => ram_rd_dat_a,
+ out_dat => rd_dat_a
+ );
u_pipe_b : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram_b.dat_w,
- g_out_dat_w => g_ram_b.dat_w
- )
- port map (
- clk => clk_b,
- clken => clken_b,
- in_dat => ram_rd_dat_b,
- out_dat => rd_dat_b
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram_b.dat_w,
+ g_out_dat_w => g_ram_b.dat_w
+ )
+ port map (
+ clk => clk_b,
+ clken => clken_b,
+ in_dat => ram_rd_dat_b,
+ out_dat => rd_dat_b
+ );
-- rd_val control
ram_rd_en_a(0) <= rd_en_a;
@@ -145,29 +145,29 @@ begin
rd_val_b <= ram_rd_val_b(0);
u_rd_val_a : entity work.common_pipeline
- generic map (
- g_pipeline => c_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk_a,
- clken => clken_a,
- in_dat => ram_rd_en_a,
- out_dat => ram_rd_val_a
- );
+ generic map (
+ g_pipeline => c_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk_a,
+ clken => clken_a,
+ in_dat => ram_rd_en_a,
+ out_dat => ram_rd_val_a
+ );
u_rd_val_b : entity work.common_pipeline
- generic map (
- g_pipeline => c_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk_b,
- clken => clken_b,
- in_dat => ram_rd_en_b,
- out_dat => ram_rd_val_b
- );
+ generic map (
+ g_pipeline => c_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk_b,
+ clken => clken_b,
+ in_dat => ram_rd_en_b,
+ out_dat => ram_rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
index 11d283a57a..81a3bf9d5a 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_cw is
generic (
@@ -62,30 +62,30 @@ begin
-- Use port b for write only in ST clock domain
u_crw_cw : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst_a => mm_rst,
- rst_b => st_rst,
- clk_a => mm_clk,
- clk_b => st_clk,
- clken_a => mm_clken,
- clken_b => st_clken,
- wr_en_a => mm_wr_en,
- wr_en_b => st_wr_en,
- wr_dat_a => mm_wr_dat,
- wr_dat_b => st_wr_dat,
- adr_a => mm_adr,
- adr_b => st_adr,
- rd_en_a => mm_rd_en,
- rd_en_b => '0',
- rd_dat_a => mm_rd_dat,
- rd_dat_b => OPEN,
- rd_val_a => mm_rd_val,
- rd_val_b => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => mm_rst,
+ rst_b => st_rst,
+ clk_a => mm_clk,
+ clk_b => st_clk,
+ clken_a => mm_clken,
+ clken_b => st_clken,
+ wr_en_a => mm_wr_en,
+ wr_en_b => st_wr_en,
+ wr_dat_a => mm_wr_dat,
+ wr_dat_b => st_wr_dat,
+ adr_a => mm_adr,
+ adr_b => st_adr,
+ rd_en_a => mm_rd_en,
+ rd_en_b => '0',
+ rd_dat_a => mm_rd_dat,
+ rd_dat_b => OPEN,
+ rd_val_a => mm_rd_val,
+ rd_val_b => open
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
index d703c059af..79650b9128 100644
--- a/libraries/base/common/src/vhdl/common_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_r_w is
generic (
@@ -54,29 +54,29 @@ begin
-- Use port b only for read
u_rw_rw : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file,
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- --wr_dat_b => (OTHERS=>'0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file,
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ wr_en_a => wr_en,
+ wr_en_b => '0',
+ wr_dat_a => wr_dat,
+ --wr_dat_b => (OTHERS=>'0'),
+ adr_a => wr_adr,
+ adr_b => rd_adr,
+ rd_en_a => '0',
+ rd_en_b => rd_en,
+ rd_dat_a => OPEN,
+ rd_dat_b => rd_dat,
+ rd_val_a => OPEN,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
index 6877523f97..a6bf21f78b 100644
--- a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_rw_rw is
generic (
@@ -58,31 +58,31 @@ begin
-- Use only one clock domain
u_crw_crw : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file,
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => clken,
- clken_b => clken,
- wr_en_a => wr_en_a,
- wr_en_b => wr_en_b,
- wr_dat_a => wr_dat_a,
- wr_dat_b => wr_dat_b,
- adr_a => adr_a,
- adr_b => adr_b,
- rd_en_a => rd_en_a,
- rd_en_b => rd_en_b,
- rd_dat_a => rd_dat_a,
- rd_dat_b => rd_dat_b,
- rd_val_a => rd_val_a,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file,
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => clken,
+ clken_b => clken,
+ wr_en_a => wr_en_a,
+ wr_en_b => wr_en_b,
+ wr_dat_a => wr_dat_a,
+ wr_dat_b => wr_dat_b,
+ adr_a => adr_a,
+ adr_b => adr_b,
+ rd_en_a => rd_en_a,
+ rd_en_b => rd_en_b,
+ rd_dat_a => rd_dat_a,
+ rd_dat_b => rd_dat_b,
+ rd_val_a => rd_val_a,
+ rd_val_b => rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
index ba5edc3b88..5eb17b0c0d 100644
--- a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.common_mem_pkg.all;
-- Purpose: Get in_dat from in_clk to out_clk domain when in_new is asserted.
-- Remarks:
@@ -171,15 +171,15 @@ begin
-- cross clock domain
------------------------------------------------------------------------------
u_cross_req : entity common_lib.common_spulse
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_pulse => cross_req,
- in_busy => cross_busy,
- out_rst => out_rst,
- out_clk => out_clk,
- out_pulse => out_en
- );
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_pulse => cross_req,
+ in_busy => cross_busy,
+ out_rst => out_rst,
+ out_clk => out_clk,
+ out_pulse => out_en
+ );
------------------------------------------------------------------------------
-- out_clk domain
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w.vhd b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
index 571de7cad2..4e2d279d82 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
-- Derived from LOFAR cfg_single_reg
@@ -117,17 +117,17 @@ begin
-- Pipeline to support read data latency > 1
u_pipe_rd : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => c_pipe_dat_w,
- g_out_dat_w => c_pipe_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => pipe_dat_in,
- out_dat => pipe_dat_out
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => c_pipe_dat_w,
+ g_out_dat_w => c_pipe_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => pipe_dat_in,
+ out_dat => pipe_dat_out
+ );
pipe_dat_in <= int_rd_val & int_rd_dat;
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
index f6d2ba975a..d54077e213 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
@@ -52,9 +52,9 @@
-- the data.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity common_reg_r_w_dc is
generic (
@@ -112,27 +112,27 @@ begin
sla_out <= i_sla_out;
u_reg : entity work.common_reg_r_w
- generic map (
- g_reg => g_reg,
- g_init_reg => g_init_reg
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => sla_in.wr,
- wr_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
- wr_dat => sla_in.wrdata(g_reg.dat_w - 1 downto 0),
- rd_en => sla_in.rd,
- rd_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
- rd_dat => i_sla_out.rddata(g_reg.dat_w - 1 downto 0),
- rd_val => i_sla_out.rdval,
- -- data side
- reg_wr_arr => vector_wr_arr,
- reg_rd_arr => vector_rd_arr,
- out_reg => out_vector,
- in_reg => in_vector
- );
+ generic map (
+ g_reg => g_reg,
+ g_init_reg => g_init_reg
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => sla_in.wr,
+ wr_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
+ wr_dat => sla_in.wrdata(g_reg.dat_w - 1 downto 0),
+ rd_en => sla_in.rd,
+ rd_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
+ rd_dat => i_sla_out.rddata(g_reg.dat_w - 1 downto 0),
+ rd_val => i_sla_out.rdval,
+ -- data side
+ reg_wr_arr => vector_wr_arr,
+ reg_rd_arr => vector_rd_arr,
+ out_reg => out_vector,
+ in_reg => in_vector
+ );
------------------------------------------------------------------------------
@@ -168,51 +168,51 @@ begin
gen_rd : if g_readback = false generate
u_in_vector : entity work.common_reg_cross_domain
- generic map (
- g_in_new_latency => g_in_new_latency
+ generic map (
+ g_in_new_latency => g_in_new_latency
+ )
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => in_new,
+ in_dat => in_reg,
+ in_done => OPEN,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => in_vector,
+ out_new => open
+ );
+ end generate;
+
+ u_out_reg : entity work.common_reg_cross_domain
+ generic map(
+ g_out_dat_init => g_init_reg
)
port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => in_new,
- in_dat => in_reg,
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => out_vector,
in_done => OPEN,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => in_vector,
- out_new => open
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => out_reg,
+ out_new => out_new_i
);
- end generate;
-
- u_out_reg : entity work.common_reg_cross_domain
- generic map(
- g_out_dat_init => g_init_reg
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => out_vector,
- in_done => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => out_reg,
- out_new => out_new_i
- );
u_toggle : entity work.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- switch_high => wr_pulse,
- switch_low => out_new_i,
- out_level => toggle
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ switch_high => wr_pulse,
+ switch_low => out_new_i,
+ out_level => toggle
+ );
wr_pulse <= '0' when vector_or(reg_wr_arr_i) = '0' else '1';
out_new <= out_new_i and toggle;
@@ -220,26 +220,26 @@ begin
gen_access_evt : for I in 0 to g_reg.nof_dat - 1 generate
u_reg_wr_arr : entity work.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => vector_wr_arr(I),
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => reg_wr_arr_i(I)
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => vector_wr_arr(I),
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => reg_wr_arr_i(I)
+ );
u_reg_rd_arr : entity work.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => vector_rd_arr(I),
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => reg_rd_arr(I)
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => vector_rd_arr(I),
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => reg_rd_arr(I)
+ );
end generate;
end generate; -- gen_cross
diff --git a/libraries/base/common/src/vhdl/common_reinterleave.vhd b/libraries/base/common/src/vhdl/common_reinterleave.vhd
index 524f0a9e46..95d355cf9a 100644
--- a/libraries/base/common/src/vhdl/common_reinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_reinterleave.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose:
-- Deinterleave g_nof_in inputs based on g_deint_block_size and re-interleave
@@ -41,7 +41,7 @@ entity common_reinterleave is
g_inter_block_size : natural;
g_dat_w : natural;
g_align_out : boolean := false
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -74,14 +74,14 @@ architecture rtl of common_reinterleave is
constant c_wires_only : boolean := g_nof_in = 1 and g_nof_out = 1;
constant c_nof_deint : natural := sel_a_b( c_interleave_only, 0,
- sel_a_b( c_deinterleave_only, 1,
- sel_a_b( c_wires_only, 0,
- g_nof_in)));
+ sel_a_b( c_deinterleave_only, 1,
+ sel_a_b( c_wires_only, 0,
+ g_nof_in)));
constant c_nof_inter : natural := sel_a_b( c_interleave_only, 1,
- sel_a_b( c_deinterleave_only, 0,
- sel_a_b( c_wires_only, 0,
- g_nof_out)));
+ sel_a_b( c_deinterleave_only, 0,
+ sel_a_b( c_wires_only, 0,
+ g_nof_out)));
constant c_nof_deint_out : natural := g_nof_out;
constant c_nof_inter_in : natural := g_nof_in;
@@ -144,22 +144,22 @@ begin
deint_in_val <= in_val;
u_deinterleave : entity work.common_deinterleave
- generic map (
- g_nof_out => c_nof_deint_out,
- g_dat_w => g_dat_w,
- g_block_size => g_deint_block_size,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => deint_in_dat_arr(i),
- in_val => deint_in_val,
-
- out_dat => deint_out_concat_dat_arr(i),
- out_val => deint_out_concat_val_arr(i)
- );
+ generic map (
+ g_nof_out => c_nof_deint_out,
+ g_dat_w => g_dat_w,
+ g_block_size => g_deint_block_size,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => deint_in_dat_arr(i),
+ in_val => deint_in_val,
+
+ out_dat => deint_out_concat_dat_arr(i),
+ out_val => deint_out_concat_val_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -220,21 +220,21 @@ begin
-----------------------------------------------------------------------------
gen_inter: for i in 0 to c_nof_inter - 1 generate
u_interleave : entity work.common_interleave
- generic map (
- g_nof_in => c_nof_inter_in,
- g_dat_w => g_dat_w,
- g_block_size => g_inter_block_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => inter_in_concat_dat_arr(i),
- in_val => inter_in_concat_val_arr(i)(0), -- All input streams are valid at the same time.
-
- out_dat => inter_out_dat_arr(i),
- out_val => inter_out_val(i)
- );
+ generic map (
+ g_nof_in => c_nof_inter_in,
+ g_dat_w => g_dat_w,
+ g_block_size => g_inter_block_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => inter_in_concat_dat_arr(i),
+ in_val => inter_in_concat_val_arr(i)(0), -- All input streams are valid at the same time.
+
+ out_dat => inter_out_dat_arr(i),
+ out_val => inter_out_val(i)
+ );
out_dat( i * g_dat_w + g_dat_w - 1 downto i * g_dat_w) <= inter_out_dat_arr(i);
out_val(i) <= inter_out_val(i);
diff --git a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
index 43b0801d19..7acfb84f75 100644
--- a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Reorder symbols from input data stream
--
@@ -131,7 +131,7 @@ architecture rtl of common_reorder_symbol is
type t_select_2arr is array (integer range <>) of t_natural_arr(g_nof_select - 1 downto 0); -- all stages
-- Perform the basic two port reorder cell function, see description section for explanation
- function func_reorder2(data : t_symbol_arr(1 downto 0); sel : natural) return t_symbol_arr is
+ function func_reorder2 (data : t_symbol_arr(1 downto 0); sel : natural) return t_symbol_arr is
variable v_sel : std_logic_vector(1 downto 0) := TO_UVEC(sel, 2);
variable v_data : t_symbol_arr(1 downto 0);
begin
@@ -157,17 +157,17 @@ begin
-- optional input pipelining
u_pipe_input : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline_arr(0),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => reorder_2arr(-1)(J),
- out_dat => reorder_2arr(0)(J)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(0),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => reorder_2arr(-1)(J),
+ out_dat => reorder_2arr(0)(J)
+ );
end generate;
-- in_select
@@ -177,16 +177,16 @@ begin
-- align in_select to the optional input pipelining
u_pipe_input : entity work.common_pipeline_natural
- generic map (
- g_pipeline => c_pipeline_arr(0),
- g_dat_w => g_select_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => select_2arr(-1)(K),
- out_dat => select_2arr(0)(K)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(0),
+ g_dat_w => g_select_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => select_2arr(-1)(K),
+ out_dat => select_2arr(0)(K)
+ );
end generate;
@@ -204,32 +204,32 @@ begin
-- optional pipelining per reorder stage
u_pipe_stage : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline_arr(I),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => nxt_reorder_2arr(I)(J),
- out_dat => reorder_2arr(I)(J)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(I),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => nxt_reorder_2arr(I)(J),
+ out_dat => reorder_2arr(I)(J)
+ );
end generate;
-- align in_select to the optional pipelining per reorder stage
gen_select : for K in 0 to g_nof_select - 1 generate
u_pipe_stage : entity work.common_pipeline_natural
- generic map (
- g_pipeline => c_pipeline_arr(I),
- g_dat_w => g_select_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => select_2arr(I - 1)(K),
- out_dat => select_2arr(I)(K)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(I),
+ g_dat_w => g_select_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => select_2arr(I - 1)(K),
+ out_dat => select_2arr(I)(K)
+ );
end generate;
end generate;
@@ -248,47 +248,47 @@ begin
------------------------------------------------------------------------------
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => out_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => out_sync
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index e733f00704..f32b51d0fa 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Requantize the input data to the output data width by removing
-- LSbits and/or MSbits
@@ -55,14 +55,14 @@ entity common_requantize is
generic (
g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_lsb_w : integer := 4; -- when > 0, number of LSbits to remove from in_dat
- -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
- -- when 0 then no effect
+ -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
+ -- when 0 then no effect
g_lsb_round : boolean := true; -- when TRUE round else truncate the input LSbits
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_even : boolean := true; -- when TRUE round half to even, else round half away from zero
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_gain_w : natural := 0; -- do not use, must be 0, use negative g_lsb_w instead
g_pipeline_remove_lsb : natural := 0; -- >= 0
g_pipeline_remove_msb : natural := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
@@ -98,41 +98,41 @@ begin
-- Remove LSBits using ROUND or TRUNCATE
u_remove_lsb : entity common_lib.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_lsb_round,
- g_round_clip => g_lsb_round_clip,
- g_round_even => g_lsb_round_even,
- g_pipeline_input => 0,
- g_pipeline_output => g_pipeline_remove_lsb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_rem_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat(g_in_dat_w - 1 downto 0),
- out_dat => rem_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_lsb_round,
+ g_round_clip => g_lsb_round_clip,
+ g_round_even => g_lsb_round_even,
+ g_pipeline_input => 0,
+ g_pipeline_output => g_pipeline_remove_lsb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_rem_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat(g_in_dat_w - 1 downto 0),
+ out_dat => rem_dat
+ );
-- Remove MSBits using CLIP or WRAP
u_remove_msb : entity common_lib.common_resize
- generic map (
- g_representation => g_representation,
- g_pipeline_input => 0,
- g_pipeline_output => g_pipeline_remove_msb,
- g_clip => g_msb_clip,
- g_clip_symmetric => g_msb_clip_symmetric,
- g_in_dat_w => c_rem_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => rem_dat,
- out_dat => res_dat,
- out_ovr => out_ovr
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline_input => 0,
+ g_pipeline_output => g_pipeline_remove_msb,
+ g_clip => g_msb_clip,
+ g_clip_symmetric => g_msb_clip_symmetric,
+ g_in_dat_w => c_rem_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => rem_dat,
+ out_dat => res_dat,
+ out_ovr => out_ovr
+ );
-- Output gain
gain_dat(g_out_dat_w + c_gain_w - 1 downto c_gain_w) <= res_dat;
diff --git a/libraries/base/common/src/vhdl/common_request.vhd b/libraries/base/common/src/vhdl/common_request.vhd
index 083480a2c4..7a1d796d40 100644
--- a/libraries/base/common/src/vhdl/common_request.vhd
+++ b/libraries/base/common/src/vhdl/common_request.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_request is
port (
@@ -83,14 +83,14 @@ begin
in_req_evt <= in_req_reg and not in_req_prev;
u_protocol_act : entity work.common_switch
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- switch_high => in_req_evt,
- switch_low => out_req,
- out_level => req_pending
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ switch_high => in_req_evt,
+ switch_low => out_req,
+ out_level => req_pending
+ );
out_req <= req_pending and sync_reg;
nxt_out_req_evt <= out_req and not out_req_prev;
diff --git a/libraries/base/common/src/vhdl/common_resize.vhd b/libraries/base/common/src/vhdl/common_resize.vhd
index 07d3bc37ca..af5373694f 100644
--- a/libraries/base/common/src/vhdl/common_resize.vhd
+++ b/libraries/base/common/src/vhdl/common_resize.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_resize is
generic (
g_representation : string := "SIGNED"; -- SIGNED or UNSIGNED resizing
g_clip : boolean := false; -- when TRUE clip input if it is outside the output range, else wrap
g_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_clip=FALSE the g_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_clip=FALSE the g_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_pipeline_input : natural := 0; -- >= 0
g_pipeline_output : natural := 1; -- >= 0
g_in_dat_w : integer := 36;
@@ -69,18 +69,18 @@ architecture rtl of common_resize is
begin
u_input_pipe : entity work.common_pipeline -- pipeline input
- generic map (
- g_representation => "SIGNED",
- g_pipeline => g_pipeline_input,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => reg_dat
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => g_pipeline_input,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => reg_dat
+ );
no_clip : if c_clip = false generate
-- Note that g_pipeline_input=0 AND g_clip=FALSE is equivalent to using RESIZE_SVEC or RESIZE_UVEC directly.
@@ -119,18 +119,18 @@ begin
res_vec <= res_ovr & res_dat;
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => g_pipeline_output,
- g_in_dat_w => g_out_dat_w + 1,
- g_out_dat_w => g_out_dat_w + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => res_vec,
- out_dat => out_vec
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => g_pipeline_output,
+ g_in_dat_w => g_out_dat_w + 1,
+ g_out_dat_w => g_out_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => res_vec,
+ out_dat => out_vec
+ );
out_ovr <= out_vec(g_out_dat_w);
out_dat <= out_vec(g_out_dat_w - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
index 9794be857f..6bd1f5d97e 100644
--- a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
+++ b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
@@ -19,9 +19,9 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Author:
-- . Eric Kooistra, 14 Feb 2023
@@ -123,23 +123,23 @@ begin
end process;
u_common_demultiplexer : entity work.common_demultiplexer
- generic map (
- g_pipeline_in => g_pipeline_demux_in,
- g_pipeline_out => g_pipeline_demux_out,
- g_nof_out => g_reverse_len,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_data,
- in_val => in_val,
-
- out_sel => in_sel,
- out_dat => demux_data_vec,
- out_val => demux_val_vec
- );
+ generic map (
+ g_pipeline_in => g_pipeline_demux_in,
+ g_pipeline_out => g_pipeline_demux_out,
+ g_nof_out => g_reverse_len,
+ g_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_data,
+ in_val => in_val,
+
+ out_sel => in_sel,
+ out_dat => demux_data_vec,
+ out_val => demux_val_vec
+ );
-- All g_reverse_len parts in demux_data_vec carry the same data, the
-- demux_val_vec determines for which demux stream it is. Use demux_data
@@ -189,63 +189,63 @@ begin
--
gen_reverse : for I in 0 to g_reverse_len - 1 generate
u_reverse_data : entity work.common_pipeline
+ generic map (
+ g_pipeline => 2 * I,
+ g_in_dat_w => g_data_w,
+ g_out_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => demux_data_vec((g_reverse_len - 1 - I + 1) * g_data_w - 1 downto (g_reverse_len - 1 - I) * g_data_w),
+ out_dat => reverse_data_vec((I + 1) * g_data_w - 1 downto I * g_data_w)
+ );
+
+ u_reverse_val : entity work.common_pipeline_sl
+ generic map (
+ g_pipeline => 2 * I
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => demux_val_vec(g_reverse_len - 1 - I),
+ out_dat => reverse_val_vec(I)
+ );
+ end generate;
+
+ reverse_val <= vector_or(reverse_val_vec);
+
+ -- pipeline in_sel to align reverse_sel to reverse_data_vec and reverse_val_vec
+ u_pipe_sel : entity work.common_pipeline
generic map (
- g_pipeline => 2 * I,
- g_in_dat_w => g_data_w,
- g_out_dat_w => g_data_w
+ g_pipeline => g_pipeline_demux_in + g_pipeline_demux_out + g_reverse_len - 1,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
)
port map (
rst => rst,
clk => clk,
- in_dat => demux_data_vec((g_reverse_len - 1 - I + 1) * g_data_w - 1 downto (g_reverse_len - 1 - I) * g_data_w),
- out_dat => reverse_data_vec((I + 1) * g_data_w - 1 downto I * g_data_w)
+ in_dat => in_sel,
+ out_dat => reverse_sel
);
- u_reverse_val : entity work.common_pipeline_sl
+ u_common_multiplexer : entity work.common_multiplexer
generic map (
- g_pipeline => 2 * I
+ g_pipeline_in => g_pipeline_mux_in,
+ g_pipeline_out => g_pipeline_mux_out,
+ g_nof_in => g_reverse_len,
+ g_dat_w => g_data_w
)
port map (
- rst => rst,
- clk => clk,
- in_dat => demux_val_vec(g_reverse_len - 1 - I),
- out_dat => reverse_val_vec(I)
- );
- end generate;
-
- reverse_val <= vector_or(reverse_val_vec);
+ rst => rst,
+ clk => clk,
- -- pipeline in_sel to align reverse_sel to reverse_data_vec and reverse_val_vec
- u_pipe_sel : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_demux_in + g_pipeline_demux_out + g_reverse_len - 1,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sel,
- out_dat => reverse_sel
- );
+ in_sel => reverse_sel,
+ in_dat => reverse_data_vec,
+ in_val => reverse_val,
- u_common_multiplexer : entity work.common_multiplexer
- generic map (
- g_pipeline_in => g_pipeline_mux_in,
- g_pipeline_out => g_pipeline_mux_out,
- g_nof_in => g_reverse_len,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => reverse_sel,
- in_dat => reverse_data_vec,
- in_val => reverse_val,
-
- out_dat => out_data,
- out_val => out_val -- = in_val delayed by c_pipeline_total
- );
+ out_dat => out_data,
+ out_val => out_val -- = in_val delayed by c_pipeline_total
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_rl_decrease.vhd b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
index c7c12eb69c..1698251904 100644
--- a/libraries/base/common/src/vhdl/common_rl_decrease.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
@@ -23,7 +23,7 @@
-- >>> Ported from UniBoard dp_latency_adapter for fixed RL 0 --> 1
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
-- Description: -
diff --git a/libraries/base/common/src/vhdl/common_rl_increase.vhd b/libraries/base/common/src/vhdl/common_rl_increase.vhd
index 84317884ec..28e8ff5117 100644
--- a/libraries/base/common/src/vhdl/common_rl_increase.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_increase.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- >>> Ported from UniBoard dp_latency_increase for fixed RL 0 --> 1
--
diff --git a/libraries/base/common/src/vhdl/common_rl_register.vhd b/libraries/base/common/src/vhdl/common_rl_register.vhd
index 0744e5f19a..44ae61d8e1 100644
--- a/libraries/base/common/src/vhdl/common_rl_register.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_register.vhd
@@ -23,7 +23,7 @@
-- >>> Ported from UniBoard dp_pipeline_ready for fixed RL 1 --> 0 --> 1
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Register both the data and the ready by going from RL=1 to 0 to 1.
-- Description: -
@@ -68,40 +68,40 @@ architecture str of common_rl_register is
begin
u_rl0 : entity common_lib.common_rl_decrease
- generic map (
- g_adapt => g_adapt,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => snk_out_ready,
- snk_in_dat => snk_in_dat,
- snk_in_val => snk_in_val,
- -- ST source: RL = 0
- src_in_ready => reg_ready,
- src_out_dat => reg_dat,
- src_out_val => reg_val
- );
+ generic map (
+ g_adapt => g_adapt,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => snk_out_ready,
+ snk_in_dat => snk_in_dat,
+ snk_in_val => snk_in_val,
+ -- ST source: RL = 0
+ src_in_ready => reg_ready,
+ src_out_dat => reg_dat,
+ src_out_val => reg_val
+ );
u_rl1 : entity common_lib.common_rl_increase
- generic map (
- g_adapt => g_adapt,
- g_hold_dat_en => g_hold_dat_en,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- Sink
- snk_out_ready => reg_ready, -- sink RL = 0
- snk_in_dat => reg_dat,
- snk_in_val => reg_val,
- -- Source
- src_in_ready => src_in_ready, -- source RL = 1
- src_out_dat => src_out_dat,
- src_out_val => src_out_val
- );
+ generic map (
+ g_adapt => g_adapt,
+ g_hold_dat_en => g_hold_dat_en,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Sink
+ snk_out_ready => reg_ready, -- sink RL = 0
+ snk_in_dat => reg_dat,
+ snk_in_val => reg_val,
+ -- Source
+ src_in_ready => src_in_ready, -- source RL = 1
+ src_out_dat => src_out_dat,
+ src_out_val => src_out_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_rom.vhd b/libraries/base/common/src/vhdl/common_rom.vhd
index f899344c7c..8bb8f998ce 100644
--- a/libraries/base/common/src/vhdl/common_rom.vhd
+++ b/libraries/base/common/src/vhdl/common_rom.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_rom is
generic (
@@ -49,22 +49,22 @@ begin
-- Only use the read port
u_r_w : entity work.common_ram_r_w
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- wr_en => '0',
- --wr_adr => (OTHERS=>'0'),
- --wr_dat => (OTHERS=>'0'),
- rd_en => rd_en,
- rd_adr => rd_adr,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ wr_en => '0',
+ --wr_adr => (OTHERS=>'0'),
+ --wr_dat => (OTHERS=>'0'),
+ rd_en => rd_en,
+ rd_adr => rd_adr,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_round.vhd b/libraries/base/common/src/vhdl/common_round.vhd
index 16c232b6ef..06c52e6b12 100644
--- a/libraries/base/common/src/vhdl/common_round.vhd
+++ b/libraries/base/common/src/vhdl/common_round.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_round is
@@ -68,18 +68,18 @@ architecture rtl of common_round is
begin
u_input_pipe : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_input,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => reg_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_input,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => reg_dat
+ );
-- Increase to out_dat width
no_s : if c_remove_w <= 0 and g_representation = "SIGNED" generate
@@ -103,17 +103,17 @@ begin
end generate;
u_output_pipe : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => res_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => res_dat,
+ out_dat => out_dat
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
index 8d03b932cf..1e3dbe67cd 100644
--- a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
+++ b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
-- Purpose: Select M symbols from an input data stream with N symbols
-- Description:
@@ -112,32 +112,32 @@ begin
in_select_arr(I) <= in_select_reg((I + 1) * c_sel_w - 1 downto I * c_sel_w);
u_sel : entity work.common_select_symbol
- generic map (
- g_pipeline_in => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out,
- g_nof_symbols => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_reg,
- in_val => in_val_reg,
- in_sop => in_sop_reg,
- in_eop => in_eop_reg,
- in_sync => in_sync_reg,
-
- in_sel => in_select_arr(I),
- out_sel => OPEN,
-
- out_symbol => out_data_arr(I),
- out_val => out_val_arr(I), -- pipelined in_val
- out_sop => out_sop_arr(I), -- pipelined in_sop
- out_eop => out_eop_arr(I), -- pipelined in_eop
- out_sync => out_sync_arr(I) -- pipelined in_sync
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out,
+ g_nof_symbols => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_reg,
+ in_val => in_val_reg,
+ in_sop => in_sop_reg,
+ in_eop => in_eop_reg,
+ in_sync => in_sync_reg,
+
+ in_sel => in_select_arr(I),
+ out_sel => OPEN,
+
+ out_symbol => out_data_arr(I),
+ out_val => out_val_arr(I), -- pipelined in_val
+ out_sop => out_sop_arr(I), -- pipelined in_sop
+ out_eop => out_eop_arr(I), -- pipelined in_eop
+ out_sync => out_sync_arr(I) -- pipelined in_sync
+ );
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_data_arr(I);
end generate;
diff --git a/libraries/base/common/src/vhdl/common_select_symbol.vhd b/libraries/base/common/src/vhdl/common_select_symbol.vhd
index 2b52a29174..04d89f1341 100644
--- a/libraries/base/common/src/vhdl/common_select_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_select_symbol.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
-- Purpose: Select symbol from input data stream
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_shiftram.vhd b/libraries/base/common/src/vhdl/common_shiftram.vhd
index 81c47fa48f..d704399758 100644
--- a/libraries/base/common/src/vhdl/common_shiftram.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftram.vhd
@@ -50,11 +50,11 @@
-- r0..r2 = register stages.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_shiftram is
generic (
@@ -87,8 +87,13 @@ architecture rtl of common_shiftram is
constant c_ram_data_w : natural := g_data_w;
constant c_ram_nof_dat : natural := g_nof_words;
constant c_ram_init_sl : std_logic := '0';
- constant c_ram : t_c_mem := (c_ram_rl, c_ram_addr_w, c_ram_data_w,
- c_ram_nof_dat, c_ram_init_sl);
+ constant c_ram : t_c_mem := (
+ c_ram_rl,
+ c_ram_addr_w,
+ c_ram_data_w,
+ c_ram_nof_dat,
+ c_ram_init_sl
+ );
signal ram_data_out : std_logic_vector(g_data_w - 1 downto 0);
signal ram_data_out_val : std_logic;
@@ -102,11 +107,13 @@ architecture rtl of common_shiftram is
ram_wr_shift_incr : boolean;
end record;
- constant c_reg_0_defaults : t_reg_0 := ( (others => '0'),
- (others => '0'),
- '0',
- (others => '0'),
- false);
+ constant c_reg_0_defaults : t_reg_0 := (
+ (others => '0'),
+ (others => '0'),
+ '0',
+ (others => '0'),
+ false
+ );
signal r0, nxt_r0 : t_reg_0 := c_reg_0_defaults;
@@ -117,9 +124,11 @@ architecture rtl of common_shiftram is
ram_rd_shift : std_logic_vector(c_ram_addr_w - 1 downto 0);
end record;
- constant c_reg_1_defaults : t_reg_1 := ( (others => '0'),
- '0',
- (others => '0'));
+ constant c_reg_1_defaults : t_reg_1 := (
+ (others => '0'),
+ '0',
+ (others => '0')
+ );
signal r1, nxt_r1 : t_reg_1 := c_reg_1_defaults;
@@ -139,9 +148,11 @@ architecture rtl of common_shiftram is
data_out_val : std_logic;
end record;
- constant c_reg_3_defaults : t_reg_3 := ( (others => '0'),
- (others => '0'),
- '0');
+ constant c_reg_3_defaults : t_reg_3 := (
+ (others => '0'),
+ (others => '0'),
+ '0'
+ );
signal r3, nxt_r3 : t_reg_3 := c_reg_3_defaults;
@@ -163,7 +174,7 @@ begin
if data_in_val = '1' then
-- Limit max shift to g_nof_words-2
- v_data_in_shift := data_in_shift;
+ v_data_in_shift := data_in_shift;
if v_data_in_shift = TO_UVEC(g_nof_words - 1, c_ram_addr_w) then
v_data_in_shift := TO_UVEC(g_nof_words - 2, c_ram_addr_w);
@@ -256,30 +267,30 @@ begin
nxt_r2 <= v;
end process;
--- data_out_shift <= r2.data_out_shift;
+ -- data_out_shift <= r2.data_out_shift;
-----------------------------------------------------------------------------
-- RAM
-----------------------------------------------------------------------------
u_common_ram_r_w: entity common_lib.common_ram_r_w
- generic map (
- g_technology => g_technology,
- g_ram => c_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- wr_en => r0.ram_wr_en,
- wr_adr => r0.ram_wr_addr,
- wr_dat => r0.ram_wr_data,
- rd_en => r1.ram_rd_en,
- rd_adr => r1.ram_rd_addr,
- rd_dat => ram_data_out,
- rd_val => ram_data_out_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ wr_en => r0.ram_wr_en,
+ wr_adr => r0.ram_wr_addr,
+ wr_dat => r0.ram_wr_data,
+ rd_en => r1.ram_rd_en,
+ rd_adr => r1.ram_rd_addr,
+ rd_dat => ram_data_out,
+ rd_val => ram_data_out_val
+ );
gen_outputs: if g_output_invalid_during_shift_incr = false generate
data_out_shift <= r2.data_out_shift;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg.vhd b/libraries/base/common/src/vhdl/common_shiftreg.vhd
index 4eccd0fb42..39e66d67f8 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Shift register when in_val is active with optional flush at in_eop.
-- Description:
@@ -138,16 +138,16 @@ begin
-- Shift control
u_flush : entity work.common_switch
- generic map (
- g_rst_level => '0'
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_eop,
- switch_low => eop_arr(0),
- out_level => flush
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_eop,
+ switch_low => eop_arr(0),
+ out_level => flush
+ );
shift_en <= in_val or flush when g_flush_en = true else in_val or out_req;
@@ -190,68 +190,68 @@ begin
out_eop <= i_out_eop_vec(0);
u_out_data_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat * g_dat_w,
- g_out_dat_w => g_nof_dat * g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => data_vec,
- out_dat => i_out_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat * g_dat_w,
+ g_out_dat_w => g_nof_dat * g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => data_vec,
+ out_dat => i_out_data_vec
+ );
u_out_val_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => val_vec,
- out_dat => i_out_val_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => val_vec,
+ out_dat => i_out_val_vec
+ );
u_out_sop_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sop_vec,
- out_dat => i_out_sop_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sop_vec,
+ out_dat => i_out_sop_vec
+ );
u_out_eop_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => eop_vec,
- out_dat => i_out_eop_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => eop_vec,
+ out_dat => i_out_eop_vec
+ );
u_out_cnt : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => c_cnt_w,
- g_out_dat_w => c_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_cnt,
- out_dat => out_cnt
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_cnt_w,
+ g_out_dat_w => c_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_cnt,
+ out_dat => out_cnt
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
index 3d1b500feb..89495d826b 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Per symbol shift register of the input data stream
-- Description:
@@ -73,26 +73,26 @@ begin
-- pipeline per symbol
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_pipeline,
- g_flush_en => g_flush_en,
- g_nof_dat => g_shiftline_arr(I),
- g_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_dat_arr(I),
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
-
- out_dat => out_dat_arr(I),
- out_val => out_val_arr(I),
- out_sop => out_sop_arr(I),
- out_eop => out_eop_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_flush_en => g_flush_en,
+ g_nof_dat => g_shiftline_arr(I),
+ g_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_dat_arr(I),
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+
+ out_dat => out_dat_arr(I),
+ out_val => out_val_arr(I),
+ out_sop => out_sop_arr(I),
+ out_eop => out_eop_arr(I)
+ );
-- map arr to output vector
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_dat_arr(I);
diff --git a/libraries/base/common/src/vhdl/common_spulse.vhd b/libraries/base/common/src/vhdl/common_spulse.vhd
index 61d8e90541..20e2124e15 100644
--- a/libraries/base/common/src/vhdl/common_spulse.vhd
+++ b/libraries/base/common/src/vhdl/common_spulse.vhd
@@ -31,8 +31,8 @@
-- the out_clk rate.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_spulse is
generic (
@@ -64,14 +64,14 @@ architecture rtl of common_spulse is
begin
capture_in_pulse : entity work.common_switch
- port map (
- clk => in_clk,
- clken => in_clken,
- rst => in_rst,
- switch_high => in_pulse,
- switch_low => pulse_ack,
- out_level => in_level
- );
+ port map (
+ clk => in_clk,
+ clken => in_clken,
+ rst => in_rst,
+ switch_high => in_pulse,
+ switch_low => pulse_ack,
+ out_level => in_level
+ );
in_busy <= in_level or pulse_ack;
diff --git a/libraries/base/common/src/vhdl/common_stable_delayed.vhd b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
index e9ac7533ea..bd339ac58c 100644
--- a/libraries/base/common/src/vhdl/common_stable_delayed.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Output active r_in if it is still active after some delay.
@@ -84,15 +84,15 @@ begin
end process;
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_delayed_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => g_delayed_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_stable_monitor.vhd b/libraries/base/common/src/vhdl/common_stable_monitor.vhd
index 157a2a9674..dbc0270f77 100644
--- a/libraries/base/common/src/vhdl/common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_monitor.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Monitor whether r_in did not go low since the previous ack
-- Description:
@@ -64,30 +64,30 @@ begin
nxt_r_stable <= r_in and not r_evt_occured;
u_r_evt : entity work.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => r_in,
- out_evt => r_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => r_in,
+ out_evt => r_evt
+ );
u_r_evt_occured : entity work.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => true,
- g_and_low => false
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => r_evt,
- switch_low => r_stable_ack,
- out_level => r_evt_occured
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => true,
+ g_and_low => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => r_evt,
+ switch_low => r_stable_ack,
+ out_level => r_evt_occured
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_str_pkg.vhd b/libraries/base/common/src/vhdl/common_str_pkg.vhd
index af8f915c7b..e5ff2d146b 100644
--- a/libraries/base/common/src/vhdl/common_str_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_str_pkg.vhd
@@ -29,46 +29,46 @@
-- . None
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use STD.TEXTIO.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use STD.TEXTIO.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_pkg.all;
package common_str_pkg is
type t_str_4_arr is array (integer range <>) of string(1 to 4);
- function nof_digits(number: natural) return natural;
- function nof_digits_int(number: integer) return natural;
+ function nof_digits (number: natural) return natural;
+ function nof_digits_int (number: integer) return natural;
- function bool_to_str(bool : boolean) return string;
- function time_to_str(in_time : time) return string;
- function str_to_time(in_str : string) return time;
- function slv_to_str(slv : std_logic_vector) return string;
- function sl_to_str(sl : std_logic) return string;
- function str_to_hex(str : string) return string;
- function slv_to_hex(slv : std_logic_vector) return string;
- function hex_to_slv(str : string) return std_logic_vector;
+ function bool_to_str (bool : boolean) return string;
+ function time_to_str (in_time : time) return string;
+ function str_to_time (in_str : string) return time;
+ function slv_to_str (slv : std_logic_vector) return string;
+ function sl_to_str (sl : std_logic) return string;
+ function str_to_hex (str : string) return string;
+ function slv_to_hex (slv : std_logic_vector) return string;
+ function hex_to_slv (str : string) return std_logic_vector;
- function hex_nibble_to_slv(c: character) return std_logic_vector;
+ function hex_nibble_to_slv (c: character) return std_logic_vector;
- function int_to_str(int: integer) return string;
- function real_to_str(re: real; width : integer; digits : integer) return string;
+ function int_to_str (int: integer) return string;
+ function real_to_str (re: real; width : integer; digits : integer) return string;
- procedure print_str(str : string);
- procedure print_str(str: string; enable: boolean);
+ procedure print_str (str : string);
+ procedure print_str (str: string; enable: boolean);
- function str_to_ascii_integer_arr(s: string) return t_integer_arr;
- function str_to_ascii_slv_8_arr( s: string) return t_slv_8_arr;
- function str_to_ascii_slv_32_arr( s: string) return t_slv_32_arr;
- function str_to_ascii_slv_32_arr( s: string; arr_size : natural) return t_slv_32_arr;
+ function str_to_ascii_integer_arr (s: string) return t_integer_arr;
+ function str_to_ascii_slv_8_arr ( s: string) return t_slv_8_arr;
+ function str_to_ascii_slv_32_arr ( s: string) return t_slv_32_arr;
+ function str_to_ascii_slv_32_arr ( s: string; arr_size : natural) return t_slv_32_arr;
end common_str_pkg;
package body common_str_pkg is
- function nof_digits(number: natural) return natural is
+ function nof_digits (number: natural) return natural is
-- Returns number of digits in a natural number. Only used in string processing, so defined here.
-- log10(0) is not allowed so:
-- . nof_digits(0) = 1
@@ -84,7 +84,7 @@ package body common_str_pkg is
end if;
end;
- function nof_digits_int(number: integer) return natural is
+ function nof_digits_int (number: integer) return natural is
-- Returns number of digits in a natural number. Only used in string processing, so defined here.
-- log10(0) is not allowed so:
-- . nof_digits(0) = 1
@@ -105,7 +105,7 @@ package body common_str_pkg is
end if;
end;
- function bool_to_str(bool : boolean) return string is
+ function bool_to_str (bool : boolean) return string is
constant c_max_len_bool : natural := 5; -- "TRUE", "FALSE"
variable v_line: LINE;
variable v_str: string(1 to c_max_len_bool) := (others => ' ');
@@ -116,38 +116,38 @@ package body common_str_pkg is
return v_str;
end;
- function time_to_str(in_time : time) return string is
+ function time_to_str (in_time : time) return string is
constant c_max_len_time : natural := 20;
- variable v_line : LINE;
- variable v_str : string(1 to c_max_len_time) := (others => ' ');
+ variable v_line : LINE;
+ variable v_str : string(1 to c_max_len_time) := (others => ' ');
begin
write(v_line, in_time);
- v_str(v_line.ALL'range) := v_line.all;
- deallocate(v_line);
- return v_str;
+ v_str(v_line.ALL'range) := v_line.all;
+ deallocate(v_line);
+ return v_str;
end;
- function str_to_time(in_str : string) return time is
+ function str_to_time (in_str : string) return time is
begin
return time'value(in_str);
end;
- function slv_to_str(slv : std_logic_vector) return string is
+ function slv_to_str (slv : std_logic_vector) return string is
variable v_line : LINE;
variable v_str : string(1 to slv'length) := (others => ' ');
begin
- write(v_line, slv);
- v_str(v_line.ALL'range) := v_line.all;
- deallocate(v_line);
- return v_str;
+ write(v_line, slv);
+ v_str(v_line.ALL'range) := v_line.all;
+ deallocate(v_line);
+ return v_str;
end;
- function sl_to_str(sl : std_logic) return string is
+ function sl_to_str (sl : std_logic) return string is
begin
- return slv_to_str(slv(sl));
+ return slv_to_str(slv(sl));
end;
- function str_to_hex(str : string) return string is
+ function str_to_hex (str : string) return string is
constant c_nof_nibbles : natural := ceil_div(str'LENGTH, c_nibble_w);
variable v_nibble_arr : t_str_4_arr(0 to c_nof_nibbles - 1) := (others => (others => '0'));
variable v_hex : string(1 to c_nof_nibbles) := (others => '0');
@@ -178,23 +178,23 @@ package body common_str_pkg is
return v_hex;
end;
- function slv_to_hex(slv :std_logic_vector) return string is
+ function slv_to_hex (slv :std_logic_vector) return string is
begin
return str_to_hex(slv_to_str(slv));
end;
- function hex_to_slv(str: string) return std_logic_vector is
- constant c_length : natural := str'length;
- variable v_str : string(1 to str'length) := str; -- Keep local copy of str to prevent range mismatch
- variable v_result : std_logic_vector(c_length * 4 - 1 downto 0);
+ function hex_to_slv (str: string) return std_logic_vector is
+ constant c_length : natural := str'length;
+ variable v_str : string(1 to str'length) := str; -- Keep local copy of str to prevent range mismatch
+ variable v_result : std_logic_vector(c_length * 4 - 1 downto 0);
begin
- for i in c_length downto 1 loop
- v_result(3 + (c_length - i) * 4 downto (c_length - i) * 4) := hex_nibble_to_slv(v_str(i));
- end loop;
- return v_result;
+ for i in c_length downto 1 loop
+ v_result(3 + (c_length - i) * 4 downto (c_length - i) * 4) := hex_nibble_to_slv(v_str(i));
+ end loop;
+ return v_result;
end;
- function hex_nibble_to_slv(c: character) return std_logic_vector is
+ function hex_nibble_to_slv (c: character) return std_logic_vector is
variable v_result : std_logic_vector(3 downto 0);
begin
case c is
@@ -225,12 +225,12 @@ package body common_str_pkg is
when 'z' => v_result := "ZZZZ";
when 'Z' => v_result := "ZZZZ";
- when others => v_result := "0000";
- end case;
- return v_result;
+ when others => v_result := "0000";
+ end case;
+ return v_result;
end hex_nibble_to_slv;
- function int_to_str(int: integer) return string is
+ function int_to_str (int: integer) return string is
variable v_line: LINE;
variable v_str: string(1 to nof_digits_int(int)) := (others => ' ');
begin
@@ -240,7 +240,7 @@ package body common_str_pkg is
return v_str;
end;
- function real_to_str(re: real; width : integer; digits : integer) return string is
+ function real_to_str (re: real; width : integer; digits : integer) return string is
-- . The number length is width + 1, with +1 for the . in the floating point number.
-- However if width is too small to fit the number, then it will use more characters.
-- Therefore define sufficiently large v_str(20) and return actual number width or
@@ -262,7 +262,7 @@ package body common_str_pkg is
end if;
end;
- procedure print_str(str: string) is
+ procedure print_str (str: string) is
variable v_line: LINE;
begin
write(v_line, str);
@@ -270,7 +270,7 @@ package body common_str_pkg is
deallocate(v_line);
end;
- procedure print_str(str: string; enable: boolean) is
+ procedure print_str (str: string; enable: boolean) is
variable v_line: LINE;
begin
if enable then
@@ -278,7 +278,7 @@ package body common_str_pkg is
end if;
end;
- function str_to_ascii_integer_arr(s: string) return t_integer_arr is
+ function str_to_ascii_integer_arr (s: string) return t_integer_arr is
variable r: t_integer_arr(0 to s'right - 1);
begin
for i in s'range loop
@@ -287,7 +287,7 @@ package body common_str_pkg is
return r;
end;
- function str_to_ascii_slv_8_arr(s: string) return t_slv_8_arr is
+ function str_to_ascii_slv_8_arr (s: string) return t_slv_8_arr is
variable r: t_slv_8_arr(0 to s'right - 1);
begin
for i in s'range loop
@@ -297,7 +297,7 @@ package body common_str_pkg is
end;
-- Returns minimum array size required to fit the string
- function str_to_ascii_slv_32_arr(s: string) return t_slv_32_arr is
+ function str_to_ascii_slv_32_arr (s: string) return t_slv_32_arr is
constant c_slv_8: t_slv_8_arr(0 to s'right - 1) := str_to_ascii_slv_8_arr(s);
constant c_bytes_per_word : natural := 4;
-- Initialize all elements to (OTHERS=>'0') so any unused bytes become a NULL character
@@ -315,7 +315,7 @@ package body common_str_pkg is
end;
-- Overloaded version to match array size to arr_size
- function str_to_ascii_slv_32_arr(s: string; arr_size: natural) return t_slv_32_arr is
+ function str_to_ascii_slv_32_arr (s: string; arr_size: natural) return t_slv_32_arr is
constant slv_32: t_slv_32_arr(0 to ceil_div(s'right * c_byte_w, c_word_w) - 1) := str_to_ascii_slv_32_arr(s);
variable r: t_slv_32_arr(0 to arr_size-1) := (others => (others => '0'));
begin
diff --git a/libraries/base/common/src/vhdl/common_switch.vhd b/libraries/base/common/src/vhdl/common_switch.vhd
index 9b3ecd744d..3bcd783ed1 100644
--- a/libraries/base/common/src/vhdl/common_switch.vhd
+++ b/libraries/base/common/src/vhdl/common_switch.vhd
@@ -30,7 +30,7 @@
-- switch_low are active simultaneously.
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
entity common_switch is
generic (
diff --git a/libraries/base/common/src/vhdl/common_toggle.vhd b/libraries/base/common/src/vhdl/common_toggle.vhd
index fbe06ef8dd..d49d98e128 100644
--- a/libraries/base/common/src/vhdl/common_toggle.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_toggle is
generic (
@@ -68,18 +68,18 @@ begin
-- Detect in_dat event
u_in_evt : entity work.common_evt
- generic map (
- g_evt_type => g_evt_type,
- g_out_invert => false,
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => in_hld,
- out_evt => in_evt
- );
+ generic map (
+ g_evt_type => g_evt_type,
+ g_out_invert => false,
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => in_hld,
+ out_evt => in_evt
+ );
-- Toggle output at in_dat event
nxt_out_dat <= not i_out_dat when in_evt = '1' else i_out_dat;
diff --git a/libraries/base/common/src/vhdl/common_toggle_align.vhd b/libraries/base/common/src/vhdl/common_toggle_align.vhd
index f557c23e53..9b36fd1ecb 100644
--- a/libraries/base/common/src/vhdl/common_toggle_align.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle_align.vhd
@@ -33,7 +33,7 @@
-- even when in_toggle stops toggling or change phase for some reason.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_toggle_align is
generic (
@@ -98,15 +98,15 @@ begin
end process;
u_common_pipeline_sl : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => nxt_out_toggle,
- out_dat => out_toggle
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => nxt_out_toggle,
+ out_dat => out_toggle
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_transpose.vhd b/libraries/base/common/src/vhdl/common_transpose.vhd
index 671247e9e9..135c6f0286 100644
--- a/libraries/base/common/src/vhdl/common_transpose.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Transpose the g_nof_data symbols in g_nof_data in_data to
-- g_nof_data symbols in g_nof_data out_data,
@@ -94,205 +94,205 @@ architecture str of common_transpose is
begin
u_sreg_data : entity common_lib.common_shiftreg
- generic map (
- g_pipeline => g_pipeline_shiftreg,
- g_flush_en => true,
- g_nof_dat => g_nof_data,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_data,
- in_val => in_val,
- in_eop => in_eop,
-
- out_data_vec => sreg_data_vec,
- out_cnt => sreg_sel,
-
- out_val => sreg_val,
- out_eop => sreg_eop
- );
+ generic map (
+ g_pipeline => g_pipeline_shiftreg,
+ g_flush_en => true,
+ g_nof_dat => g_nof_data,
+ g_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_data,
+ in_val => in_val,
+ in_eop => in_eop,
+
+ out_data_vec => sreg_data_vec,
+ out_cnt => sreg_sel,
+
+ out_val => sreg_val,
+ out_eop => sreg_eop
+ );
u_sreg_addr : entity common_lib.common_shiftreg
- generic map (
- g_pipeline => g_pipeline_shiftreg,
- g_flush_en => true,
- g_nof_dat => g_nof_data,
- g_dat_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_addr,
- in_val => in_val,
- in_eop => in_eop,
-
- out_data_vec => sreg_addr_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_shiftreg,
+ g_flush_en => true,
+ g_nof_dat => g_nof_data,
+ g_dat_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_addr,
+ in_val => in_val,
+ in_eop => in_eop,
+
+ out_data_vec => sreg_addr_vec
+ );
sreg_full <= '1' when sreg_val = '1' and TO_UINT(sreg_sel) = 0 else '0';
u_transpose_data : entity common_lib.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline_transpose,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => sreg_data_vec,
- out_data => trans_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => sreg_data_vec,
+ out_data => trans_data_vec
+ );
gen_offsets : for I in g_nof_data - 1 downto 0 generate
offset_addr_vec((I + 1) * g_addr_w - 1 downto I * g_addr_w) <= TO_UVEC(I * TO_UINT(in_offset), g_addr_w);
end generate;
u_add_addr : entity common_lib.common_add_symbol
- generic map (
- g_pipeline => g_pipeline_transpose,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_a => offset_addr_vec,
- in_b => sreg_addr_vec,
-
- out_data => add_addr_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_a => offset_addr_vec,
+ in_b => sreg_addr_vec,
+
+ out_data => add_addr_vec
+ );
u_trans_full : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_transpose
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_full,
- out_dat => trans_full
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_full,
+ out_dat => trans_full
+ );
u_hold_data : entity common_lib.common_shiftreg_symbol
- generic map (
- g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
- g_pipeline => g_pipeline_hold,
- g_flush_en => false,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => trans_data_vec,
- in_val => trans_full,
-
- out_data => hold_data_vec
- );
+ generic map (
+ g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
+ g_pipeline => g_pipeline_hold,
+ g_flush_en => false,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => trans_data_vec,
+ in_val => trans_full,
+
+ out_data => hold_data_vec
+ );
u_hold_addr : entity common_lib.common_shiftreg_symbol
- generic map (
- g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
- g_pipeline => g_pipeline_hold,
- g_flush_en => false,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => add_addr_vec,
- in_val => trans_full,
-
- out_data => hold_addr_vec
- );
+ generic map (
+ g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
+ g_pipeline => g_pipeline_hold,
+ g_flush_en => false,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => add_addr_vec,
+ in_val => trans_full,
+
+ out_data => hold_addr_vec
+ );
u_hold_sel : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_pipeline_sel,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_sel,
- out_dat => hold_sel
- );
+ generic map (
+ g_pipeline => c_pipeline_sel,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_sel,
+ out_dat => hold_sel
+ );
u_hold_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_sel
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_val,
- out_dat => hold_val
- );
+ generic map (
+ g_pipeline => c_pipeline_sel
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_val,
+ out_dat => hold_val
+ );
u_hold_eop : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_sel
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_eop,
- out_dat => hold_eop
- );
+ generic map (
+ g_pipeline => c_pipeline_sel
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_eop,
+ out_dat => hold_eop
+ );
u_output_data : entity common_lib.common_select_symbol
- generic map (
- g_pipeline_in => 0,
- g_pipeline_out => g_pipeline_select,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_data_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => hold_data_vec,
- in_val => hold_val,
- in_eop => hold_eop,
-
- in_sel => hold_sel,
-
- out_symbol => out_data,
- out_val => out_val,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline_in => 0,
+ g_pipeline_out => g_pipeline_select,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_data_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => hold_data_vec,
+ in_val => hold_val,
+ in_eop => hold_eop,
+
+ in_sel => hold_sel,
+
+ out_symbol => out_data,
+ out_val => out_val,
+ out_eop => out_eop
+ );
u_output_addr : entity common_lib.common_select_symbol
- generic map (
- g_pipeline_in => 0,
- g_pipeline_out => g_pipeline_select,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => hold_addr_vec,
- in_val => hold_val,
- in_eop => hold_eop,
-
- in_sel => hold_sel,
-
- out_symbol => out_addr
- );
+ generic map (
+ g_pipeline_in => 0,
+ g_pipeline_out => g_pipeline_select,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => hold_addr_vec,
+ in_val => hold_val,
+ in_eop => hold_eop,
+
+ in_sel => hold_sel,
+
+ out_symbol => out_addr
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
index 86173325be..2c6871524e 100644
--- a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Transpose of in_data to out_data
-- Description:
@@ -103,50 +103,50 @@ begin
-- pipeline data output
u_out_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_data * g_data_w,
- g_out_dat_w => g_nof_data * g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => trans_data,
- out_dat => out_data
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_data * g_data_w,
+ g_out_dat_w => g_nof_data * g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => trans_data,
+ out_dat => out_data
+ );
-- pipeline control output
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index 122814e457..b3002adb6c 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -27,8 +27,8 @@
-- --------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_variable_delay is
generic (
diff --git a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
index 17f2092f41..d63ef7f5cf 100644
--- a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
+++ b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
@@ -32,8 +32,8 @@
-- eases the use of this scope within a design.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_wideband_data_scope is
generic (
diff --git a/libraries/base/common/src/vhdl/common_zip.vhd b/libraries/base/common/src/vhdl/common_zip.vhd
index 67b5952382..c763abc815 100644
--- a/libraries/base/common/src/vhdl/common_zip.vhd
+++ b/libraries/base/common/src/vhdl/common_zip.vhd
@@ -25,8 +25,8 @@
-- to avoid the loss of data.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_zip is
generic (
diff --git a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
index ca32557a71..7d9eaebf6d 100644
--- a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
@@ -25,17 +25,17 @@
-- . MM wrapper for common_pulse_delay.vhd
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_common_pulse_delay is
generic (
g_pulse_delay_max : natural := 0; -- Maximum number of clk cycles that pulse can be delayed
g_register_out : boolean
- );
+ );
port (
pulse_clk : in std_logic;
pulse_rst : in std_logic;
@@ -60,36 +60,36 @@ begin
-- common_pulse_delay
------------------------------------------------------------------------------
u_common_pulse_delay : entity common_lib.common_pulse_delay
- generic map (
- g_pulse_delay_max => g_pulse_delay_max,
- g_register_out => true
- )
- port map (
- clk => pulse_clk,
- rst => pulse_rst,
- pulse_in => pulse_in,
- pulse_delay => pulse_delay,
- pulse_out => pulse_out
- );
+ generic map (
+ g_pulse_delay_max => g_pulse_delay_max,
+ g_register_out => true
+ )
+ port map (
+ clk => pulse_clk,
+ rst => pulse_rst,
+ pulse_in => pulse_in,
+ pulse_delay => pulse_delay,
+ pulse_out => pulse_out
+ );
------------------------------------------------------------------------------
-- New MM interface via avs_common_mm
------------------------------------------------------------------------------
u_common_pulse_delay_reg : entity work.common_pulse_delay_reg
- generic map (
- g_cross_clock_domain => true,
- g_pulse_delay_max => g_pulse_delay_max
- )
- port map (
- pulse_clk => pulse_clk,
- pulse_rst => pulse_rst,
- pulse_delay => pulse_delay,
+ generic map (
+ g_cross_clock_domain => true,
+ g_pulse_delay_max => g_pulse_delay_max
+ )
+ port map (
+ pulse_clk => pulse_clk,
+ pulse_rst => pulse_rst,
+ pulse_delay => pulse_delay,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- sla_in => reg_mosi,
- sla_out => reg_miso
- );
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ sla_in => reg_mosi,
+ sla_out => reg_miso
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_reg.vhd b/libraries/base/common/src/vhdl/mms_common_reg.vhd
index 8857a3c267..66dae5c3ab 100644
--- a/libraries/base/common/src/vhdl/mms_common_reg.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_reg.vhd
@@ -23,9 +23,9 @@
-- Description: Wrapper, see common_reg_r_w_dc.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_common_reg is
@@ -66,29 +66,29 @@ architecture str of mms_common_reg is
begin
u_common_reg_r_w_dc : entity work.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => g_mm_reg,
- g_init_reg => c_init_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => g_mm_reg,
+ g_init_reg => c_init_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => in_reg,
- out_reg => out_reg
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => in_reg,
+ out_reg => out_reg
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
index 0d43f61630..34bc178a27 100644
--- a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
@@ -23,9 +23,9 @@
-- Description: See common_stable_monitor.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_common_stable_monitor is
@@ -56,11 +56,13 @@ architecture str of mms_common_stable_monitor is
constant c_adr_w : natural := ceil_log2(c_nof_dat);
constant c_dat_w : natural := sel_a_b(c_nof_dat = 1, g_nof_input, c_word_w);
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_adr_w,
- dat_w => c_dat_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_adr_w,
+ dat_w => c_dat_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_dat,
+ init_sl => '0'
+ );
signal reg_rd_arr : std_logic_vector(c_mm_reg.nof_dat - 1 downto 0);
@@ -72,28 +74,28 @@ architecture str of mms_common_stable_monitor is
begin
u_mm_reg : entity work.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => reg_rd_arr,
- in_reg => in_reg,
- out_reg => open
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
+ in_reg => in_reg,
+ out_reg => open
+ );
in_reg(g_nof_input - 1 downto 0) <= st_stable_arr;
@@ -102,14 +104,14 @@ begin
gen_mon : for I in g_nof_input - 1 downto 0 generate
u_stable_monitor : entity work.common_stable_monitor
- port map (
- rst => st_rst,
- clk => st_clk,
- -- MM
- r_in => st_in_arr(I),
- r_stable => st_stable_arr(I),
- r_stable_ack => st_stable_ack
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- MM
+ r_in => st_in_arr(I),
+ r_stable => st_stable_arr(I),
+ r_stable_ack => st_stable_ack
+ );
end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
index 46fb0e5745..32a86d6224 100644
--- a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
@@ -26,10 +26,10 @@
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity mms_common_variable_delay is
port (
@@ -65,31 +65,31 @@ begin
-- device under test
u_common_variable_delay : entity work.common_variable_delay
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- delay => delay,
- enable => enable,
- in_pulse => trigger,
- out_pulse => trigger_dly
- );
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ delay => delay,
+ enable => enable,
+ in_pulse => trigger,
+ out_pulse => trigger_dly
+ );
u_mms_common_reg : entity work.mms_common_reg
- generic map (
- g_mm_reg => c_enable_mem_reg
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- reg_mosi => reg_enable_mosi,
- reg_miso => reg_enable_miso,
-
- in_reg => enable_reg,
- out_reg => enable_reg
- );
+ generic map (
+ g_mm_reg => c_enable_mem_reg
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ reg_mosi => reg_enable_mosi,
+ reg_miso => reg_enable_miso,
+
+ in_reg => enable_reg,
+ out_reg => enable_reg
+ );
end;
diff --git a/libraries/base/common/tb/vhdl/tb_common_acapture.vhd b/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
index 526dcc1b23..6e33b669df 100644
--- a/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_acapture is
end tb_common_acapture;
@@ -79,15 +79,15 @@ begin
end process;
u_acapture : entity work.common_acapture
- generic map (
- g_rst_level => '0'
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_dat => in_dat,
- out_clk => out_clk,
- out_cap => out_cap
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_dat => in_dat,
+ out_clk => out_clk,
+ out_cap => out_cap
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
index 99e634373c..94340e1eab 100644
--- a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_add_sub is
@@ -42,7 +42,7 @@ architecture tb of tb_common_add_sub is
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_in + g_pipeline_out;
- function func_result(in_a, in_b : std_logic_vector) return std_logic_vector is
+ function func_result (in_a, in_b : std_logic_vector) return std_logic_vector is
variable v_a, v_b, v_result : integer;
begin
-- Calculate expected result
@@ -54,7 +54,7 @@ architecture tb of tb_common_add_sub is
if g_direction = "BOTH" and g_sel_add = '0' then v_result := v_a - v_b; end if;
-- Wrap to avoid warning: NUMERIC_STD.TO_SIGNED: vector truncated
if v_result > 2**(g_out_dat_w - 1) - 1 then v_result := v_result - 2**g_out_dat_w; end if;
- if v_result < - 2**(g_out_dat_w - 1) then v_result := v_result + 2**g_out_dat_w; end if;
+ if v_result < - 2**(g_out_dat_w - 1) then v_result := v_result + 2**g_out_dat_w; end if;
return TO_SVEC(v_result, g_out_dat_w);
end;
@@ -132,38 +132,38 @@ begin
out_result <= func_result(in_a, in_b);
u_result : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_result,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_result,
+ out_dat => result_expected
+ );
u_dut_rtl : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => "SIGNED",
- g_pipeline_input => g_pipeline_in,
- g_pipeline_output => g_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => g_sel_add,
- in_a => in_a,
- in_b => in_b,
- result => result_rtl
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => g_pipeline_in,
+ g_pipeline_output => g_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => g_sel_add,
+ in_a => in_a,
+ in_b => in_b,
+ result => result_rtl
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
index 1a99bf170c..810f58e86b 100644
--- a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
@@ -31,10 +31,10 @@
-- . The p_verify makes the tb self checking and asserts when the results are not equal
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_adder_tree is
@@ -60,7 +60,7 @@ architecture tb of tb_common_adder_tree is
type t_symbol_arr is array (integer range <>) of std_logic_vector(g_symbol_w - 1 downto 0);
-- Use the same symbol value g_nof_inputs time in the data_vec
- function func_data_vec(symbol : integer) return std_logic_vector is
+ function func_data_vec (symbol : integer) return std_logic_vector is
variable v_data_vec : std_logic_vector(c_data_vec_w - 1 downto 0);
begin
for I in 0 to g_nof_inputs - 1 loop
@@ -70,7 +70,7 @@ architecture tb of tb_common_adder_tree is
end;
-- Calculate the expected result of the sum of the symbols in the data_vec
- function func_result(data_vec : std_logic_vector) return std_logic_vector is
+ function func_result (data_vec : std_logic_vector) return std_logic_vector is
variable v_result : integer;
begin
v_result := 0;
@@ -129,20 +129,20 @@ begin
-- . Pipeline the in_data_vec to align with the result
-- . Map the concatenated symbols in in_data_vec into an in_data_arr_p array
u_data_vec_p : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_data_vec_w,
- g_out_dat_w => c_data_vec_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_data_vec,
- out_dat => in_data_vec_p
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_data_vec_w,
+ g_out_dat_w => c_data_vec_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_data_vec,
+ out_dat => in_data_vec_p
+ );
p_data_arr : process(in_data_vec_p)
begin
@@ -154,36 +154,36 @@ begin
result_comb <= func_result(in_data_vec);
u_result : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => g_sum_w,
- g_out_dat_w => g_sum_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => result_comb,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => g_sum_w,
+ g_out_dat_w => g_sum_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => result_comb,
+ out_dat => result_expected
+ );
-- Using work.common_adder_tree(recursive) will only invoke the recursive architecture once, because the next recursive level will default to using the last compiled architecture
-- Therefore only instatiatiate the DUT once in this tb and use compile order to influence which architecture is used.
dut : entity work.common_adder_tree -- uses last compile architecture
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_symbol_w,
- g_sum_w => g_sum_w
- )
- port map (
- clk => clk,
- in_dat => in_data_vec,
- sum => result_dut
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_symbol_w,
+ g_sum_w => g_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_data_vec,
+ sum => result_dut
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_async.vhd b/libraries/base/common/tb/vhdl/tb_common_async.vhd
index 5ca9fad4cf..0f7261f423 100644
--- a/libraries/base/common/tb/vhdl/tb_common_async.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_async.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_async is
end tb_common_async;
@@ -86,26 +86,26 @@ begin
end process;
u_async : entity work.common_async
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- rst => in_rst,
- clk => clk,
- din => in_dat,
- dout => out_async
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => clk,
+ din => in_dat,
+ dout => out_async
+ );
u_areset : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- in_rst => in_rst,
- clk => clk,
- out_rst => out_areset
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ in_rst => in_rst,
+ clk => clk,
+ out_rst => out_areset
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
index 0eb908d210..46c5729d96 100644
--- a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_clock_phase_detector is
generic (
@@ -91,31 +91,31 @@ begin
end process;
u_common_clock_phase_detector_r : entity work.common_clock_phase_detector
- generic map (
- g_rising_edge => true,
- g_meta_delay_len => c_delay_len,
- g_clk_factor => c_clk_factor_num
- )
- port map (
- in_clk => in_clk, -- used as data input for clk domain
- rst => rst,
- clk => clk,
- phase => phase_r,
- phase_det => phase_r_det
- );
+ generic map (
+ g_rising_edge => true,
+ g_meta_delay_len => c_delay_len,
+ g_clk_factor => c_clk_factor_num
+ )
+ port map (
+ in_clk => in_clk, -- used as data input for clk domain
+ rst => rst,
+ clk => clk,
+ phase => phase_r,
+ phase_det => phase_r_det
+ );
u_common_clock_phase_detector_f : entity work.common_clock_phase_detector
- generic map (
- g_rising_edge => false,
- g_meta_delay_len => c_delay_len,
- g_clk_factor => c_clk_factor_num
- )
- port map (
- in_clk => in_clk, -- used as data input for clk domain
- rst => rst,
- clk => clk,
- phase => phase_f,
- phase_det => phase_f_det
- );
+ generic map (
+ g_rising_edge => false,
+ g_meta_delay_len => c_delay_len,
+ g_clk_factor => c_clk_factor_num
+ )
+ port map (
+ in_clk => in_clk, -- used as data input for clk domain
+ rst => rst,
+ clk => clk,
+ phase => phase_f,
+ phase_det => phase_f_det
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_counter.vhd b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
index 945ccb8ca8..d7dd089402 100644
--- a/libraries/base/common/tb/vhdl/tb_common_counter.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_counter is
end tb_common_counter;
@@ -90,21 +90,21 @@ begin
-- device under test
u_dut : entity work.common_counter
- generic map (
- g_init => c_cnt_init,
- g_width => c_cnt_w,
- g_step_size => 1
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_ld => cnt_ld,
- cnt_en => cnt_en,
- cnt_max => cnt_max,
- load => load,
- count => count
- );
+ generic map (
+ g_init => c_cnt_init,
+ g_width => c_cnt_w,
+ g_step_size => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_ld => cnt_ld,
+ cnt_en => cnt_en,
+ cnt_max => cnt_max,
+ load => load,
+ count => count
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
index d72f974ea3..c99ec18944 100644
--- a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
@@ -24,9 +24,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_create_strobes_from_valid is
generic (
@@ -124,19 +124,19 @@ begin
end process;
u_in_sync : entity work.common_create_strobes_from_valid
- generic map (
- g_pipeline => g_pipeline,
- g_nof_clk_per_sync => g_nof_clk_per_sync,
- g_nof_clk_per_block => g_nof_clk_per_block
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_clk_per_sync => g_nof_clk_per_sync,
+ g_nof_clk_per_block => g_nof_clk_per_block
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd b/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
index 662e1596a8..b3f7aeca47 100644
--- a/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
@@ -27,10 +27,10 @@
-- Description: See common_ddreg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_ddreg_slv is
end tb_common_ddreg_slv;
@@ -70,18 +70,18 @@ begin
end process;
u_common_ddreg_slv : entity work.common_ddreg_slv
- generic map (
- g_in_delay_len => 1,
- g_out_delay_len => c_meta_delay_len
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_hi => out_dat_hi,
- out_dat_lo => out_dat_lo
- );
+ generic map (
+ g_in_delay_len => 1,
+ g_out_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_hi => out_dat_hi,
+ out_dat_lo => out_dat_lo
+ );
out_dat <= out_dat_hi & out_dat_lo;
diff --git a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
index 02b9ab8552..706c50fdca 100644
--- a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
@@ -38,8 +38,8 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_common_debounce is
end tb_common_debounce;
@@ -171,46 +171,46 @@ begin
end process;
u_debounce_both : entity work.common_debounce
- generic map (
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_both
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_both
- );
+ generic map (
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_both
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_both
+ );
u_debounce_high : entity work.common_debounce
- generic map (
- g_type => "HIGH",
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_high
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_high
- );
+ generic map (
+ g_type => "HIGH",
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_high
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_high
+ );
u_debounce_low : entity work.common_debounce
- generic map (
- g_type => "LOW",
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_low
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_low
- );
+ generic map (
+ g_type => "LOW",
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_low
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_low
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd b/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
index e3f154712c..f8c9ff9ec8 100644
--- a/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_duty_cycle is
end tb_common_duty_cycle;
@@ -113,22 +113,22 @@ begin
-----------------------------------------------------------------------------
dut : entity work.common_duty_cycle
- generic map (
- g_rst_lvl => '0',
- g_dis_lvl => '0',
- g_act_lvl => '1',
- g_per_cnt => c_dc_max_period_cnt,
- g_act_cnt => 10
- )
- port map (
- rst => rst,
- clk => clk,
-
- dc_per_cnt => dc_per_cnt,
- dc_act_cnt => dc_act_cnt,
-
- dc_out_en => dc_out_en,
- dc_out => dc_out
- );
+ generic map (
+ g_rst_lvl => '0',
+ g_dis_lvl => '0',
+ g_act_lvl => '1',
+ g_per_cnt => c_dc_max_period_cnt,
+ g_act_cnt => 10
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ dc_per_cnt => dc_per_cnt,
+ dc_act_cnt => dc_act_cnt,
+
+ dc_out_en => dc_out_en,
+ dc_out => dc_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
index 3622a2762e..f013c7dd06 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
@@ -27,11 +27,11 @@
-- when the fanout data is not incrementing.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fanout_tree is
generic (
@@ -58,7 +58,7 @@ architecture tb of tb_common_fanout_tree is
constant c_nof_output : natural := g_nof_output_per_cell**g_nof_stages;
constant c_tree_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := func_common_fanout_tree_pipelining(g_nof_stages, g_nof_output_per_cell, c_nof_output,
- g_cell_pipeline_factor_arr, g_cell_pipeline_arr);
+ g_cell_pipeline_factor_arr, g_cell_pipeline_arr);
constant c_tree_pipeline_max : natural := largest(c_tree_pipeline_arr);
type t_data_arr is array (integer range <>) of std_logic_vector(c_dat_w - 1 downto 0);
@@ -114,23 +114,23 @@ begin
proc_common_gen_data(c_rl, c_init, rst, clk, cnt_en, ready, in_dat, in_val);
dut : entity work.common_fanout_tree
- generic map (
- g_nof_stages => g_nof_stages,
- g_nof_output_per_cell => g_nof_output_per_cell,
- g_nof_output => g_nof_output,
- g_cell_pipeline_factor_arr => g_cell_pipeline_factor_arr,
- g_cell_pipeline_arr => g_cell_pipeline_arr,
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- in_en => in_en,
- in_dat => in_dat,
- in_val => in_val,
- out_en_vec => out_en_vec,
- out_dat_vec => out_dat_vec,
- out_val_vec => out_val_vec
- );
+ generic map (
+ g_nof_stages => g_nof_stages,
+ g_nof_output_per_cell => g_nof_output_per_cell,
+ g_nof_output => g_nof_output,
+ g_cell_pipeline_factor_arr => g_cell_pipeline_factor_arr,
+ g_cell_pipeline_arr => g_cell_pipeline_arr,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ in_en => in_en,
+ in_dat => in_dat,
+ in_val => in_val,
+ out_en_vec => out_en_vec,
+ out_dat_vec => out_dat_vec,
+ out_val_vec => out_val_vec
+ );
-- Verify data for fanout output 0
proc_common_verify_data(c_rl, clk, verify_en, ready, out_val_vec(0), out_dat_arr(0), prev_out_dat_arr(0));
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
index c250de09b6..773b898a98 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
@@ -26,10 +26,10 @@
-- . observe rd_dat in wave window
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fifo_dc_mixed_widths is
@@ -38,7 +38,7 @@ entity tb_common_fifo_dc_mixed_widths is
g_rd_clk_freq : positive := 1; -- normalized read clock frequency
g_wr_dat_w : natural := 8;
g_rd_dat_w : natural := 16
- --g_rd_dat_w : NATURAL := 4
+ --g_rd_dat_w : NATURAL := 4
);
end tb_common_fifo_dc_mixed_widths;
@@ -110,24 +110,24 @@ begin
rd_req <= '1';
u_dut : entity work.common_fifo_dc_mixed_widths
- generic map (
- g_nof_words => c_wr_fifo_nof_words,
- g_wr_dat_w => g_wr_dat_w,
- g_rd_dat_w => g_rd_dat_w
- )
- port map (
- rst => rst,
- wr_clk => wr_clk,
- wr_dat => wr_dat,
- wr_req => wr_val,
- wr_ful => wr_ful,
- wrusedw => wr_usedw,
- rd_clk => rd_clk,
- rd_dat => rd_dat,
- rd_req => rd_req,
- rd_emp => rd_emp,
- rdusedw => rd_usedw,
- rd_val => rd_val
- );
+ generic map (
+ g_nof_words => c_wr_fifo_nof_words,
+ g_wr_dat_w => g_wr_dat_w,
+ g_rd_dat_w => g_rd_dat_w
+ )
+ port map (
+ rst => rst,
+ wr_clk => wr_clk,
+ wr_dat => wr_dat,
+ wr_req => wr_val,
+ wr_ful => wr_ful,
+ wrusedw => wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ rd_emp => rd_emp,
+ rdusedw => rd_usedw,
+ rd_val => rd_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
index 359890d7f2..ab86edd57a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fifo_rd is
@@ -83,20 +83,20 @@ begin
u_dut : entity work.common_fifo_rd
- generic map (
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- fifo_req => fifo_req,
- fifo_dat => fifo_dat,
- fifo_val => fifo_val,
- -- ST source: RL = 0
- rd_req => rd_req,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ fifo_req => fifo_req,
+ fifo_dat => fifo_dat,
+ fifo_val => fifo_val,
+ -- ST source: RL = 0
+ rd_req => rd_req,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd b/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
index 46fb3f4e27..2770390e2d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_flank_to_pulse is
end tb_common_flank_to_pulse;
@@ -58,11 +58,11 @@ begin
end process;
u_dut: entity work.common_flank_to_pulse
- port map (
- clk => clk,
- rst => rst,
- flank_in => flank_in,
- pulse_out => pulse_out
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ flank_in => flank_in,
+ pulse_out => pulse_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
index c87848367e..c4b9e84b54 100644
--- a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
@@ -25,9 +25,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_gcd is
end tb_common_gcd;
diff --git a/libraries/base/common/tb/vhdl/tb_common_init.vhd b/libraries/base/common/tb/vhdl/tb_common_init.vhd
index 5c6503ab7c..174de9e43d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_init.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_init.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_init is
end tb_common_init;
@@ -44,25 +44,25 @@ begin
clk <= not clk after clk_period / 2;
u_reset : entity work.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => clk,
- out_rst => rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => clk,
+ out_rst => rst
+ );
u_init: entity work.common_init
- generic map (
- g_latency_w => c_latency_w
- )
- port map (
- rst => rst,
- clk => clk,
- hold => hold,
- init => init
- );
+ generic map (
+ g_latency_w => c_latency_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ hold => hold,
+ init => init
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
index bc1482793c..c0844040f5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
@@ -1,7 +1,7 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_common_int2float is
end tb_common_int2float;
@@ -86,13 +86,13 @@ begin
end process;
u_float : entity work.common_int2float
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
index fcc72043a2..c2a3b0707e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
@@ -26,9 +26,9 @@
-- in Wave window zoom in and expand out_dat to see the 50 ps delays
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_iobuf_in is
end tb_common_iobuf_in;
@@ -56,15 +56,15 @@ begin
in_dat <= not(in_dat) when rising_edge(clk);
u_dut : entity work.common_iobuf_in
- generic map (
- g_width => c_width,
- g_delay_arr => c_delay_arr
- )
- port map (
- config_rst => rst,
- config_clk => clk,
- in_dat => in_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_width => c_width,
+ g_delay_arr => c_delay_arr
+ )
+ port map (
+ config_rst => rst,
+ config_clk => clk,
+ in_dat => in_dat,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
index 4eb4886d2f..36b601b3c3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
@@ -32,8 +32,8 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_common_led_controller is
end tb_common_led_controller;
@@ -104,40 +104,40 @@ begin
end process;
u_common_pulser_us_ms_s : entity work.common_pulser_us_ms_s
- generic map (
- g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
- g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => pulse_ms -- pulses after every g_pulse_us*g_pulse_ms clock cycles
- );
+ generic map (
+ g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
+ g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => pulse_ms -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ );
u_common_toggle_ms : entity work.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => pulse_ms,
- out_dat => toggle_ms
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => pulse_ms,
+ out_dat => toggle_ms
+ );
u_common_led_controller : entity work.common_led_controller
- generic map (
- g_nof_ms => c_led_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => pulse_ms,
- -- led control
- ctrl_on => ctrl_on,
- ctrl_evt => ctrl_evt,
- ctrl_input => toggle_ms,
- -- led output
- led => LED
- );
+ generic map (
+ g_nof_ms => c_led_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => pulse_ms,
+ -- led control
+ ctrl_on => ctrl_on,
+ ctrl_evt => ctrl_evt,
+ ctrl_input => toggle_ms,
+ -- led output
+ led => LED
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_log.vhd b/libraries/base/common/tb/vhdl/tb_common_log.vhd
index 1e7937f573..e02928c1d1 100644
--- a/libraries/base/common/tb/vhdl/tb_common_log.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_log.vhd
@@ -22,9 +22,9 @@
-- Usage:
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
entity tb_common_log is
end tb_common_log;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
index 0a4b58aee9..726f270ce2 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use work.tb_common_pkg.all;
-use work.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.tb_common_pkg.all;
+ use work.tb_common_mem_pkg.all;
entity tb_common_mem_mux is
- generic (
+ generic (
g_nof_mosi : positive := 16; -- Number of memory interfaces in the array.
g_mult_addr_w : positive := 4 -- Address width of each memory-interface element in the array.
);
@@ -44,11 +44,13 @@ architecture tb of tb_common_mem_mux is
constant clk_period : time := 10 ns;
constant c_data_w : natural := 32;
- constant c_test_ram : t_c_mem := (latency => 1,
- adr_w => g_mult_addr_w,
- dat_w => c_data_w,
- nof_dat => 2**g_mult_addr_w,
- init_sl => '0');
+ constant c_test_ram : t_c_mem := (
+ latency => 1,
+ adr_w => g_mult_addr_w,
+ dat_w => c_data_w,
+ nof_dat => 2**g_mult_addr_w,
+ init_sl => '0'
+ );
signal rst : std_logic;
signal clk : std_logic := '1';
signal tb_end : std_logic;
@@ -93,34 +95,34 @@ begin
generation_of_test_rams : for I in 0 to g_nof_mosi - 1 generate
u_test_rams : entity work.common_ram_r_w
+ generic map (
+ g_ram => c_test_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ wr_en => mosi_arr(I).wr,
+ wr_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
+ wr_dat => mosi_arr(I).wrdata(c_data_w - 1 downto 0),
+ rd_en => mosi_arr(I).rd,
+ rd_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
+ rd_dat => miso_arr(I).rddata(c_data_w - 1 downto 0),
+ rd_val => miso_arr(I).rdval
+ );
+ end generate;
+
+ d_dut : entity work.common_mem_mux
generic map (
- g_ram => c_test_ram,
- g_init_file => "UNUSED"
+ g_nof_mosi => g_nof_mosi,
+ g_mult_addr_w => g_mult_addr_w
)
port map (
- rst => rst,
- clk => clk,
- clken => '1',
- wr_en => mosi_arr(I).wr,
- wr_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
- wr_dat => mosi_arr(I).wrdata(c_data_w - 1 downto 0),
- rd_en => mosi_arr(I).rd,
- rd_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
- rd_dat => miso_arr(I).rddata(c_data_w - 1 downto 0),
- rd_val => miso_arr(I).rdval
+ mosi_arr => mosi_arr,
+ miso_arr => miso_arr,
+ mosi => mosi,
+ miso => miso
);
- end generate;
-
- d_dut : entity work.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_mosi,
- g_mult_addr_w => g_mult_addr_w
- )
- port map (
- mosi_arr => mosi_arr,
- miso_arr => miso_arr,
- mosi => mosi,
- miso => miso
- );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
index e03840a534..e68a64815a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
package tb_common_mem_pkg is
@@ -37,65 +37,76 @@ package tb_common_mem_pkg is
-- as signal).
-- Write data to the MM bus
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in integer; -- [31:0]
- signal wr_data : in std_logic_vector; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in std_logic_vector; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_wr (
+ constant wr_addr : in natural; -- [31:0]
+ constant wr_data : in integer; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr (
+ constant wr_addr : in integer; -- [31:0]
+ signal wr_data : in std_logic_vector; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr (
+ constant wr_addr : in natural; -- [31:0]
+ constant wr_data : in integer; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr (
+ constant wr_addr : in natural; -- [31:0]
+ constant wr_data : in std_logic_vector; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Read data request to the MM bus
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_rd (
+ constant rd_addr : in natural; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_rd (
+ constant rd_addr : in natural; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Wait for read data valid after read latency mm_clk cycles
- procedure proc_mem_mm_bus_rd_latency(constant c_rd_latency : in natural;
- signal mm_clk : in std_logic);
+ procedure proc_mem_mm_bus_rd_latency (
+ constant c_rd_latency : in natural;
+ signal mm_clk : in std_logic);
-- Write array of data words to the memory
- procedure proc_mem_write_ram(constant offset : in natural;
- constant nof_data : in natural;
- constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_write_ram(constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_write_ram (
+ constant offset : in natural;
+ constant nof_data : in natural;
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_write_ram (
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Read array of data words from the memory
- procedure proc_mem_read_ram(constant offset : in natural;
- constant nof_data : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr);
-
- procedure proc_mem_read_ram(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr);
+ procedure proc_mem_read_ram (
+ constant offset : in natural;
+ constant nof_data : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr);
+
+ procedure proc_mem_read_ram (
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr);
end tb_common_mem_pkg;
@@ -107,8 +118,9 @@ package body tb_common_mem_pkg is
------------------------------------------------------------------------------
-- Issues a rd or a wr MM access
- procedure proc_mm_access(signal mm_clk : in std_logic;
- signal mm_access : out std_logic) is
+ procedure proc_mm_access (
+ signal mm_clk : in std_logic;
+ signal mm_access : out std_logic) is
begin
mm_access <= '1';
wait until rising_edge(mm_clk);
@@ -116,9 +128,10 @@ package body tb_common_mem_pkg is
end proc_mm_access;
-- Issues a rd or a wr MM access and wait for it to have finished
- procedure proc_mm_access(signal mm_clk : in std_logic;
- signal mm_waitreq : in std_logic;
- signal mm_access : out std_logic) is
+ procedure proc_mm_access (
+ signal mm_clk : in std_logic;
+ signal mm_waitreq : in std_logic;
+ signal mm_access : out std_logic) is
begin
mm_access <= '1';
wait until rising_edge(mm_clk);
@@ -133,42 +146,46 @@ package body tb_common_mem_pkg is
------------------------------------------------------------------------------
-- Write data to the MM bus
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr (
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= TO_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in integer;
- signal wr_data : in std_logic_vector;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr (
+ constant wr_addr : in integer;
+ signal wr_data : in std_logic_vector;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= RESIZE_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr (
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= TO_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr (
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= RESIZE_UVEC(wr_data, c_mem_data_w);
@@ -179,18 +196,20 @@ package body tb_common_mem_pkg is
-- Read data request to the MM bus
-- Use proc_mem_mm_bus_rd_latency() to wait for the MM MISO rd_data signal
-- to show the data after some read latency
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_rd (
+ constant rd_addr : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(rd_addr);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.rd);
end proc_mem_mm_bus_rd;
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_rd (
+ constant rd_addr : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(rd_addr);
proc_mm_access(mm_clk, mm_mosi.rd);
@@ -198,19 +217,21 @@ package body tb_common_mem_pkg is
-- Wait for read data valid after read latency mm_clk cycles
-- Directly assign mm_miso.rddata to capture the read data
- procedure proc_mem_mm_bus_rd_latency(constant c_rd_latency : in natural;
- signal mm_clk : in std_logic) is
+ procedure proc_mem_mm_bus_rd_latency (
+ constant c_rd_latency : in natural;
+ signal mm_clk : in std_logic) is
begin
for I in 0 to c_rd_latency - 1 loop wait until rising_edge(mm_clk); end loop;
end proc_mem_mm_bus_rd_latency;
-- Write array of data words to the memory
- procedure proc_mem_write_ram(constant offset : in natural;
- constant nof_data : in natural;
- constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_write_ram (
+ constant offset : in natural;
+ constant nof_data : in natural;
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
constant c_data_arr : t_slv_32_arr(data_arr'length - 1 downto 0) := data_arr; -- map to fixed range [h:0]
begin
for I in 0 to nof_data - 1 loop
@@ -218,9 +239,10 @@ package body tb_common_mem_pkg is
end loop;
end proc_mem_write_ram;
- procedure proc_mem_write_ram(constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_write_ram (
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
constant c_offset : natural := 0;
constant c_nof_data : natural := data_arr'length;
begin
@@ -228,12 +250,13 @@ package body tb_common_mem_pkg is
end proc_mem_write_ram;
-- Read array of data words from the memory
- procedure proc_mem_read_ram(constant offset : in natural;
- constant nof_data : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr) is
+ procedure proc_mem_read_ram (
+ constant offset : in natural;
+ constant nof_data : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr) is
begin
for I in 0 to nof_data - 1 loop
proc_mem_mm_bus_rd(offset + I, mm_clk, mm_mosi);
@@ -244,10 +267,11 @@ package body tb_common_mem_pkg is
wait until rising_edge(mm_clk);
end proc_mem_read_ram;
- procedure proc_mem_read_ram(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr) is
+ procedure proc_mem_read_ram (
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr) is
constant c_offset : natural := 0;
constant c_nof_data : natural := data_arr'length;
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
index e579fe51f6..588284790e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
-- Purpose: Test bench for common_multiplexer.vhd and common_demultiplexer.vhd
-- Usage:
@@ -130,59 +130,59 @@ begin
-- . Demultiplex single input to output[in_sel]
u_demux : entity work.common_demultiplexer
- generic map (
- g_pipeline_in => g_pipeline_demux_in,
- g_pipeline_out => g_pipeline_demux_out,
- g_nof_out => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map(
- rst => rst,
- clk => clk,
-
- in_dat => in_dat,
- in_val => in_val,
-
- out_sel => in_sel,
- out_dat => demux_dat_vec,
- out_val => demux_val_vec
- );
+ generic map (
+ g_pipeline_in => g_pipeline_demux_in,
+ g_pipeline_out => g_pipeline_demux_out,
+ g_nof_out => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_dat,
+ in_val => in_val,
+
+ out_sel => in_sel,
+ out_dat => demux_dat_vec,
+ out_val => demux_val_vec
+ );
-- . pipeline in_sel to align demux_sel to demux_*_vec
u_pipe_sel : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_pipeline_demux,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sel,
- out_dat => demux_sel
- );
+ generic map (
+ g_pipeline => c_pipeline_demux,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sel,
+ out_dat => demux_sel
+ );
demux_val <= demux_val_vec(TO_UINT(demux_sel));
-- . Multiplex input[demux_sel] back to a single output
u_mux : entity work.common_multiplexer
- generic map (
- g_pipeline_in => g_pipeline_mux_in,
- g_pipeline_out => g_pipeline_mux_out,
- g_nof_in => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => demux_sel,
- in_dat => demux_dat_vec,
- in_val => demux_val,
-
- out_dat => out_dat,
- out_val => out_val
- );
+ generic map (
+ g_pipeline_in => g_pipeline_mux_in,
+ g_pipeline_out => g_pipeline_mux_out,
+ g_nof_in => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_sel => demux_sel,
+ in_dat => demux_dat_vec,
+ in_val => demux_val,
+
+ out_dat => out_dat,
+ out_val => out_val
+ );
------------------------------------------------------------------------------
diff --git a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
index 3c38959ed5..c0d44ebea7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
@@ -29,11 +29,11 @@
-- not equal
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_operation_tree is
@@ -65,7 +65,7 @@ architecture tb of tb_common_operation_tree is
type t_data_arr is array (integer range <>) of std_logic_vector(c_dat_w - 1 downto 0);
-- Use random data values for the g_nof_inputs time in the data_vec
- function func_data_vec(init : integer) return std_logic_vector is
+ function func_data_vec (init : integer) return std_logic_vector is
variable v_data_vec : std_logic_vector(c_data_vec_w - 1 downto 0);
variable v_in : std_logic_vector(c_dat_w - 1 downto 0);
begin
@@ -78,7 +78,7 @@ architecture tb of tb_common_operation_tree is
end;
-- Calculate the expected result of the operation on the data in the data_vec
- function func_result(operation, representation : string; data_vec : std_logic_vector) return std_logic_vector is
+ function func_result (operation, representation : string; data_vec : std_logic_vector) return std_logic_vector is
variable v_in : std_logic_vector(c_dat_w - 1 downto 0);
variable v_result : integer := 0;
begin
@@ -154,19 +154,19 @@ begin
-- . Pipeline the in_data_vec to align with the result
-- . Map the concatenated dat in in_data_vec into an in_data_arr_p array
u_data_vec_p : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_data_vec_w,
- g_out_dat_w => c_data_vec_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => in_data_vec_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_data_vec_w,
+ g_out_dat_w => c_data_vec_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => in_data_vec_p
+ );
p_data_arr : process(in_data_vec_p)
begin
@@ -178,47 +178,47 @@ begin
expected_comb <= func_result(g_operation, g_representation, in_data_vec);
u_result : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => expected_comb,
- out_dat => expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => expected_comb,
+ out_dat => expected
+ );
u_expected_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => expected_val
- );
+ generic map (
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => expected_val
+ );
dut : entity work.common_operation_tree
- generic map (
- g_operation => g_operation,
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_pipeline_mod => g_pipeline_mod,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- in_data_vec => in_data_vec,
- in_en_vec => in_en_vec,
- result => result
- );
+ generic map (
+ g_operation => g_operation,
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_pipeline_mod => g_pipeline_mod,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => in_data_vec,
+ in_en_vec => in_en_vec,
+ result => result
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
index c5d8fe20ff..24f75bf954 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
-- Purpose: Test bench for common_paged_ram_crw_crw
--
@@ -127,100 +127,100 @@ begin
end process;
u_dut_mux : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_mux",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => mux_rd_dat_b,
- rd_val_b => mux_rd_val_b
- );
+ generic map (
+ g_str => "use_mux",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => mux_rd_dat_b,
+ rd_val_b => mux_rd_val_b
+ );
u_dut_adr : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_adr",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => adr_rd_dat_b,
- rd_val_b => adr_rd_val_b
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => adr_rd_dat_b,
+ rd_val_b => adr_rd_val_b
+ );
u_dut_ofs : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_ofs",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => ofs_rd_dat_b,
- rd_val_b => ofs_rd_val_b
- );
+ generic map (
+ g_str => "use_ofs",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => ofs_rd_dat_b,
+ rd_val_b => ofs_rd_val_b
+ );
-- Verify that the read data is incrementing data
proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val_b, mux_rd_dat_b, prev_mux_rd_dat_b);
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
index 1f16076346..c515e74a03 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
-- Purpose: Test bench for common_paged_ram_ww_rr
-- Description:
@@ -186,66 +186,66 @@ begin
-- Double write - double read
u_dut_ww_rr : entity work.common_paged_ram_ww_rr
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => c_data_w,
- g_page_sz => g_page_sz
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- next page control
- next_page => next_page,
- -- double write access to one page
- wr_adr_a => wr_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- wr_adr_b => wr_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => wwrr_rd_dat_a,
- rd_val_a => wwrr_rd_val_a,
- rd_dat_b => wwrr_rd_dat_b,
- rd_val_b => wwrr_rd_val_b
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => c_data_w,
+ g_page_sz => g_page_sz
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page
+ wr_adr_a => wr_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ wr_adr_b => wr_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => wwrr_rd_dat_a,
+ rd_val_a => wwrr_rd_val_a,
+ rd_dat_b => wwrr_rd_dat_b,
+ rd_val_b => wwrr_rd_val_b
+ );
-- Single write - double read
u_dut_w_rr : entity work.common_paged_ram_w_rr
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => c_data_w,
- g_page_sz => g_page_sz
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- next page control
- next_page => next_page,
- -- double write access to one page
- wr_adr => in_adr,
- wr_en => in_en,
- wr_dat => in_dat,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => wrr_rd_dat_a,
- rd_val_a => wrr_rd_val_a,
- rd_dat_b => wrr_rd_dat_b,
- rd_val_b => wrr_rd_val_b
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => c_data_w,
+ g_page_sz => g_page_sz
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page
+ wr_adr => in_adr,
+ wr_en => in_en,
+ wr_dat => in_dat,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => wrr_rd_dat_a,
+ rd_val_a => wrr_rd_val_a,
+ rd_dat_b => wrr_rd_dat_b,
+ rd_val_b => wrr_rd_val_b
+ );
------------------------------------------------------------------------------
-- Verify
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index fe6d6b3415..1fae5df90e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -30,11 +30,11 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all; -- for boolean, integer file IO
-use IEEE.std_logic_textio.all; -- for std_logic, std_logic_vector file IO
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all; -- for boolean, integer file IO
+ use IEEE.std_logic_textio.all; -- for std_logic, std_logic_vector file IO
+ use work.common_pkg.all;
package tb_common_pkg is
@@ -50,295 +50,350 @@ package tb_common_pkg is
-- Wait for some time or until
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in natural);
-
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in real);
-
- procedure proc_common_wait_some_cycles(signal clk_in : in std_logic;
- signal clk_out : in std_logic;
- c_nof_cycles : in natural);
-
- procedure proc_common_wait_some_pulses(signal clk : in std_logic;
- signal pulse : in std_logic;
- c_nof_pulses : in natural);
-
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in integer);
-
- procedure proc_common_wait_until_evt(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_high(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_high(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_clk_and_high(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_low(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_low(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_clk_and_low(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_hi_lo(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_hi_lo(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_lo_hi(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_lo_hi(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in integer);
-
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector);
-
- procedure proc_common_wait_until_value(constant c_timeout : in natural;
- constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector);
+ procedure proc_common_wait_some_cycles (
+ signal clk : in std_logic;
+ c_nof_cycles : in natural);
+
+ procedure proc_common_wait_some_cycles (
+ signal clk : in std_logic;
+ c_nof_cycles : in real);
+
+ procedure proc_common_wait_some_cycles (
+ signal clk_in : in std_logic;
+ signal clk_out : in std_logic;
+ c_nof_cycles : in natural);
+
+ procedure proc_common_wait_some_pulses (
+ signal clk : in std_logic;
+ signal pulse : in std_logic;
+ c_nof_pulses : in natural);
+
+ procedure proc_common_wait_until_evt (
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_evt (
+ signal clk : in std_logic;
+ signal level : in integer);
+
+ procedure proc_common_wait_until_evt (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_high (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_high (
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_clk_and_high (
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_low (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_low (
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_clk_and_low (
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_hi_lo (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_hi_lo (
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_lo_hi (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_lo_hi (
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_value (
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in integer);
+
+ procedure proc_common_wait_until_value (
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector);
+
+ procedure proc_common_wait_until_value (
+ constant c_timeout : in natural;
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector);
-- Wait until absolute simulation time NOW = c_time
- procedure proc_common_wait_until_time(signal clk : in std_logic;
- constant c_time : in time);
+ procedure proc_common_wait_until_time (
+ signal clk : in std_logic;
+ constant c_time : in time);
-- Exit simulation on timeout failure
- procedure proc_common_timeout_failure(constant c_timeout : in time;
- signal tb_end : in std_logic);
+ procedure proc_common_timeout_failure (
+ constant c_timeout : in time;
+ signal tb_end : in std_logic);
-- Stop simulation using severity FAILURE when g_tb_end=TRUE, else for use in multi tb report as severity NOTE
- procedure proc_common_stop_simulation(signal tb_end : in std_logic);
+ procedure proc_common_stop_simulation (signal tb_end : in std_logic);
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- constant g_latency : in natural; -- latency between tb_done and tb_)end
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic);
+ procedure proc_common_stop_simulation (
+ constant g_tb_end : in boolean;
+ constant g_latency : in natural; -- latency between tb_done and tb_)end
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic);
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic);
+ procedure proc_common_stop_simulation (
+ constant g_tb_end : in boolean;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic);
-- Handle stream ready signal, only support ready latency c_rl = 0 or 1.
- procedure proc_common_ready_latency(constant c_rl : in natural;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '1' then active output when ready
- signal ready : in std_logic;
- signal out_valid : out std_logic);
+ procedure proc_common_ready_latency (
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '1' then active output when ready
+ signal ready : in std_logic;
+ signal out_valid : out std_logic);
-- Wait for clock domain crossing latency, e.g. for MM readback after MM write
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic;
- constant c_nof_cycles : in natural);
+ procedure proc_common_wait_cross_clock_domain_latency (
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic;
+ constant c_nof_cycles : in natural);
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic);
+ procedure proc_common_wait_cross_clock_domain_latency (
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic);
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time;
- constant c_nof_cycles : in natural);
+ procedure proc_common_wait_cross_clock_domain_latency (
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time;
+ constant c_nof_cycles : in natural);
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time);
+ procedure proc_common_wait_cross_clock_domain_latency (
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time);
-- Generate a single active, inactive pulse
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse (
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Pulse forever after rst was released
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse (
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Generate a single '1', '0' pulse
- procedure proc_common_gen_pulse(signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse (
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Generate a periodic pulse with arbitrary duty cycle
- procedure proc_common_gen_duty_pulse(constant c_delay : in natural; -- delay pulse for nof_clk after enable
- constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- once enabled, the pulse remains enabled
- signal pulse : out std_logic);
-
- procedure proc_common_gen_duty_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- once enabled, the pulse remains enabled
- signal pulse : out std_logic);
+ procedure proc_common_gen_duty_pulse (
+ constant c_delay : in natural; -- delay pulse for nof_clk after enable
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- once enabled, the pulse remains enabled
+ signal pulse : out std_logic);
+
+ procedure proc_common_gen_duty_pulse (
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- once enabled, the pulse remains enabled
+ signal pulse : out std_logic);
-- Generate counter data with valid and arbitrary increment or fixed increment=1
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- constant c_incr : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic);
-
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic);
+ procedure proc_common_gen_data (
+ constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_init : in integer;
+ constant c_incr : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic);
+
+ procedure proc_common_gen_data (
+ constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_init : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic);
-- Generate frame control
- procedure proc_common_sop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_sop : out std_logic);
-
- procedure proc_common_eop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic);
-
- procedure proc_common_val(constant c_val_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic);
-
- procedure proc_common_val_duty(constant c_hi_len : in natural;
- constant c_lo_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic);
-
- procedure proc_common_eop_flush(constant c_flush_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic);
+ procedure proc_common_sop (
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_sop : out std_logic);
+
+ procedure proc_common_eop (
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic);
+
+ procedure proc_common_val (
+ constant c_val_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic);
+
+ procedure proc_common_val_duty (
+ constant c_hi_len : in natural;
+ constant c_lo_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic);
+
+ procedure proc_common_eop_flush (
+ constant c_flush_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic);
-- Verify the DUT output incrementing data, only support ready latency c_rl = 0 or 1.
- procedure proc_common_verify_data(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal out_valid : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_common_verify_data (
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify the DUT output valid for ready latency, only support ready latency c_rl = 0 or 1.
- procedure proc_common_verify_valid(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal prev_ready : inout std_logic;
- signal out_valid : in std_logic);
+ procedure proc_common_verify_valid (
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal prev_ready : inout std_logic;
+ signal out_valid : in std_logic);
-- Verify the DUT input to output latency for SL ctrl signals
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "valid", "sop", "eop"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_ctrl : in std_logic;
- signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
- signal out_ctrl : in std_logic);
+ procedure proc_common_verify_latency (
+ constant c_str : in string; -- e.g. "valid", "sop", "eop"
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_ctrl : in std_logic;
+ signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
+ signal out_ctrl : in std_logic);
-- Verify the DUT input to output latency for SLV data signals
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_data : in std_logic_vector;
- signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
- signal out_data : in std_logic_vector);
+ procedure proc_common_verify_latency (
+ constant c_str : in string; -- e.g. "data"
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_data : in std_logic_vector;
+ signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
+ signal out_data : in std_logic_vector);
-- Verify the expected value, e.g. to check that a test has ran at all
- procedure proc_common_verify_value(constant mode : in natural;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector);
+ procedure proc_common_verify_value (
+ constant mode : in natural;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector);
-- open, read line, close file
- procedure proc_common_open_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- file_name : in string;
- file_mode : in FILE_OPEN_KIND);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer;
- read_value_1 : out integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- value_array : out t_integer_arr;
- nof_reads : in integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_slv : out std_logic_vector);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- res_string : out string);
-
- procedure proc_common_close_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT);
+ procedure proc_common_open_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ file_name : in string;
+ file_mode : in FILE_OPEN_KIND);
+
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer);
+
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer;
+ read_value_1 : out integer);
+
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ value_array : out t_integer_arr;
+ nof_reads : in integer);
+
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_slv : out std_logic_vector);
+
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ res_string : out string);
+
+ procedure proc_common_close_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT);
-- read entire file
- procedure proc_common_read_integer_file(file_name : in string;
- nof_header_lines : natural;
- nof_row : natural;
- nof_col : natural;
- signal return_array : out t_integer_arr);
+ procedure proc_common_read_integer_file (
+ file_name : in string;
+ nof_header_lines : natural;
+ nof_row : natural;
+ nof_col : natural;
+ signal return_array : out t_integer_arr);
- procedure proc_common_read_mif_file(file_name : in string;
- signal return_array : out t_integer_arr);
+ procedure proc_common_read_mif_file (
+ file_name : in string;
+ signal return_array : out t_integer_arr);
-- Complex multiply function with conjugate option for input b
- function func_complex_multiply(in_ar, in_ai, in_br, in_bi : std_logic_vector; conjugate_b : boolean; str : string; g_out_dat_w : natural) return std_logic_vector;
+ function func_complex_multiply (in_ar, in_ai, in_br, in_bi : std_logic_vector; conjugate_b : boolean; str : string; g_out_dat_w : natural) return std_logic_vector;
- function func_decstring_to_integer(in_string: string) return integer;
+ function func_decstring_to_integer (in_string: string) return integer;
- function func_hexstring_to_integer(in_string: string) return integer;
+ function func_hexstring_to_integer (in_string: string) return integer;
- function func_find_char_in_string(in_string: string; find_char: character) return integer;
+ function func_find_char_in_string (in_string: string; find_char: character) return integer;
- function func_find_string_in_string(in_string: string; find_string: string) return boolean;
+ function func_find_string_in_string (in_string: string; find_string: string) return boolean;
end tb_common_pkg;
@@ -348,21 +403,24 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait some clock cycles
------------------------------------------------------------------------------
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in natural) is
+ procedure proc_common_wait_some_cycles (
+ signal clk : in std_logic;
+ c_nof_cycles : in natural) is
begin
for I in 0 to c_nof_cycles - 1 loop wait until rising_edge(clk); end loop;
end proc_common_wait_some_cycles;
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in real) is
+ procedure proc_common_wait_some_cycles (
+ signal clk : in std_logic;
+ c_nof_cycles : in real) is
begin
proc_common_wait_some_cycles(clk, natural(c_nof_cycles));
end proc_common_wait_some_cycles;
- procedure proc_common_wait_some_cycles(signal clk_in : in std_logic;
- signal clk_out : in std_logic;
- c_nof_cycles : in natural) is
+ procedure proc_common_wait_some_cycles (
+ signal clk_in : in std_logic;
+ signal clk_out : in std_logic;
+ c_nof_cycles : in natural) is
begin
proc_common_wait_some_cycles(clk_in, c_nof_cycles);
proc_common_wait_some_cycles(clk_out, c_nof_cycles);
@@ -371,9 +429,10 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait some pulses
------------------------------------------------------------------------------
- procedure proc_common_wait_some_pulses(signal clk : in std_logic;
- signal pulse : in std_logic;
- c_nof_pulses : in natural) is
+ procedure proc_common_wait_some_pulses (
+ signal clk : in std_logic;
+ signal pulse : in std_logic;
+ c_nof_pulses : in natural) is
begin
for I in 0 to c_nof_pulses - 1 loop
proc_common_wait_until_hi_lo(clk, pulse);
@@ -386,8 +445,9 @@ package body tb_common_pkg is
-- PROCEDURE: Wait until the level input is low
-- PROCEDURE: Wait until the input is equal to c_value
------------------------------------------------------------------------------
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_evt (
+ signal clk : in std_logic;
+ signal level : in std_logic) is
variable v_level : std_logic := level;
begin
wait until rising_edge(clk);
@@ -397,8 +457,9 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in integer) is
+ procedure proc_common_wait_until_evt (
+ signal clk : in std_logic;
+ signal level : in integer) is
variable v_level : integer := level;
begin
wait until rising_edge(clk);
@@ -408,9 +469,10 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_evt(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_evt (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
variable v_level : std_logic := level;
variable v_I : natural := 0;
begin
@@ -426,23 +488,26 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_high(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_high (
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
wait until rising_edge(clk) and level = '1';
end if;
end proc_common_wait_until_high;
- procedure proc_common_wait_until_clk_and_high(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_clk_and_high (
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
wait until rising_edge(clk) and level = '1';
end proc_common_wait_until_clk_and_high;
- procedure proc_common_wait_until_high(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_high (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
for I in 0 to c_timeout - 1 loop
if level = '1' then
@@ -456,23 +521,26 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_high;
- procedure proc_common_wait_until_low(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_low (
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
wait until rising_edge(clk) and level = '0';
end if;
end proc_common_wait_until_low;
- procedure proc_common_wait_until_clk_and_low(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_clk_and_low (
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
wait until rising_edge(clk) and level = '0';
end proc_common_wait_until_clk_and_low;
- procedure proc_common_wait_until_low(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_low (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
for I in 0 to c_timeout - 1 loop
if level = '0' then
@@ -486,8 +554,9 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_low;
- procedure proc_common_wait_until_hi_lo(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_hi_lo (
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
proc_common_wait_until_high(clk, level);
@@ -495,9 +564,10 @@ package body tb_common_pkg is
proc_common_wait_until_low(clk, level);
end proc_common_wait_until_hi_lo;
- procedure proc_common_wait_until_hi_lo(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_hi_lo (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
proc_common_wait_until_high(c_timeout, clk, level);
@@ -505,8 +575,9 @@ package body tb_common_pkg is
proc_common_wait_until_low(c_timeout, clk, level);
end proc_common_wait_until_hi_lo;
- procedure proc_common_wait_until_lo_hi(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_lo_hi (
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
proc_common_wait_until_low(clk, level);
@@ -514,9 +585,10 @@ package body tb_common_pkg is
proc_common_wait_until_high(clk, level);
end proc_common_wait_until_lo_hi;
- procedure proc_common_wait_until_lo_hi(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_lo_hi (
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
proc_common_wait_until_low(c_timeout, clk, level);
@@ -524,28 +596,31 @@ package body tb_common_pkg is
proc_common_wait_until_high(c_timeout, clk, level);
end proc_common_wait_until_lo_hi;
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in integer) is
+ procedure proc_common_wait_until_value (
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in integer) is
begin
while level /= c_value loop
wait until rising_edge(clk);
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector) is
+ procedure proc_common_wait_until_value (
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector) is
begin
while signed(level) /= c_value loop
wait until rising_edge(clk);
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_value(constant c_timeout : in natural;
- constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector) is
+ procedure proc_common_wait_until_value (
+ constant c_timeout : in natural;
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector) is
begin
for I in 0 to c_timeout - 1 loop
if signed(level) = c_value then
@@ -559,16 +634,18 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_time(signal clk : in std_logic;
- constant c_time : in time) is
+ procedure proc_common_wait_until_time (
+ signal clk : in std_logic;
+ constant c_time : in time) is
begin
while NOW < c_time loop
wait until rising_edge(clk);
end loop;
end procedure;
- procedure proc_common_timeout_failure(constant c_timeout : in time;
- signal tb_end : in std_logic) is
+ procedure proc_common_timeout_failure (
+ constant c_timeout : in time;
+ signal tb_end : in std_logic) is
begin
while tb_end = '0' loop
assert NOW < c_timeout report "Test bench timeout." severity ERROR;
@@ -577,7 +654,7 @@ package body tb_common_pkg is
end loop;
end procedure;
- procedure proc_common_stop_simulation(signal tb_end : in std_logic) is
+ procedure proc_common_stop_simulation (signal tb_end : in std_logic) is
begin
wait until tb_end = '1';
-- For modelsim_regression_test_vhdl.py:
@@ -588,11 +665,12 @@ package body tb_common_pkg is
wait;
end procedure;
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- constant g_latency : in natural;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic) is
+ procedure proc_common_stop_simulation (
+ constant g_tb_end : in boolean;
+ constant g_latency : in natural;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic) is
begin
-- Wait until simulation indicates done
proc_common_wait_until_high(clk, tb_done);
@@ -614,10 +692,11 @@ package body tb_common_pkg is
wait;
end procedure;
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic) is
+ procedure proc_common_stop_simulation (
+ constant g_tb_end : in boolean;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic) is
begin
proc_common_stop_simulation(g_tb_end, 0, clk, tb_done, tb_end);
end procedure;
@@ -627,11 +706,12 @@ package body tb_common_pkg is
-- . output active when ready='1' and enable='1'
-- . only support ready latency c_rl = 0 or 1
------------------------------------------------------------------------------
- procedure proc_common_ready_latency(constant c_rl : in natural;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal ready : in std_logic;
- signal out_valid : out std_logic) is
+ procedure proc_common_ready_latency (
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : out std_logic) is
begin
-- skip ready cycles until enable='1'
out_valid <= '0';
@@ -671,31 +751,35 @@ package body tb_common_pkg is
-- PROCEDURE: Wait for clock domain crossing latency, e.g. for MM readback after MM write
------------------------------------------------------------------------------
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic;
- constant c_nof_cycles : in natural) is
+ procedure proc_common_wait_cross_clock_domain_latency (
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic;
+ constant c_nof_cycles : in natural) is
begin
proc_common_wait_some_cycles(mm_clk, c_nof_cycles);
proc_common_wait_some_cycles(st_clk, c_nof_cycles);
end proc_common_wait_cross_clock_domain_latency;
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic) is
+ procedure proc_common_wait_cross_clock_domain_latency (
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic) is
begin
proc_common_wait_some_cycles(mm_clk, c_common_cross_clock_domain_latency);
proc_common_wait_some_cycles(st_clk, c_common_cross_clock_domain_latency);
end proc_common_wait_cross_clock_domain_latency;
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time;
- constant c_nof_cycles : in natural) is
+ procedure proc_common_wait_cross_clock_domain_latency (
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time;
+ constant c_nof_cycles : in natural) is
begin
wait for c_nof_cycles * c_mm_clk_period;
wait for c_nof_cycles * c_st_clk_period;
end proc_common_wait_cross_clock_domain_latency;
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time) is
+ procedure proc_common_wait_cross_clock_domain_latency (
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time) is
begin
wait for c_common_cross_clock_domain_latency * c_mm_clk_period;
wait for c_common_cross_clock_domain_latency * c_st_clk_period;
@@ -704,11 +788,12 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Generate a single active, inactive pulse
------------------------------------------------------------------------------
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal clk : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_pulse (
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
variable v_cnt : natural range 0 to c_period := 0;
begin
while v_cnt < c_period loop
@@ -723,12 +808,13 @@ package body tb_common_pkg is
end proc_common_gen_pulse;
-- Pulse forever after rst was released
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_pulse (
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
variable v_cnt : natural range 0 to c_period := 0;
begin
pulse <= not c_level;
@@ -741,8 +827,9 @@ package body tb_common_pkg is
end proc_common_gen_pulse;
-- pulse '1', '0'
- procedure proc_common_gen_pulse(signal clk : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_pulse (
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
begin
proc_common_gen_pulse(1, 2, '1', clk, pulse);
end proc_common_gen_pulse;
@@ -750,14 +837,15 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Generate a periodic pulse with arbitrary duty cycle
------------------------------------------------------------------------------
- procedure proc_common_gen_duty_pulse(constant c_delay : in natural; -- delay pulse for nof_clk after enable
- constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_duty_pulse (
+ constant c_delay : in natural; -- delay pulse for nof_clk after enable
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal pulse : out std_logic) is
variable v_cnt : natural range 0 to c_period - 1 := 0;
begin
pulse <= not c_level;
@@ -780,13 +868,14 @@ package body tb_common_pkg is
end if;
end proc_common_gen_duty_pulse;
- procedure proc_common_gen_duty_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal pulse : out std_logic) is
+ procedure proc_common_gen_duty_pulse (
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal pulse : out std_logic) is
begin
proc_common_gen_duty_pulse(0, c_active, c_period, c_level, rst, clk, enable, pulse);
end proc_common_gen_duty_pulse;
@@ -796,15 +885,16 @@ package body tb_common_pkg is
-- . Output counter data dependent on enable and ready
------------------------------------------------------------------------------
-- arbitrary c_incr
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- constant c_incr : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic) is
+ procedure proc_common_gen_data (
+ constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_init : in integer;
+ constant c_incr : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic) is
constant c_data_w : natural := out_data'length;
variable v_data : std_logic_vector(c_data_w - 1 downto 0) := TO_SVEC(c_init, c_data_w);
begin
@@ -821,14 +911,15 @@ package body tb_common_pkg is
end proc_common_gen_data;
-- c_incr = 1
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic) is
+ procedure proc_common_gen_data (
+ constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_init : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic) is
begin
proc_common_gen_data(c_rl, c_init, 1, rst, clk, enable, ready, out_data, out_valid);
end proc_common_gen_data;
@@ -837,9 +928,10 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Generate frame control
------------------------------------------------------------------------------
- procedure proc_common_sop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_sop : out std_logic) is
+ procedure proc_common_sop (
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_sop : out std_logic) is
begin
in_val <= '1';
in_sop <= '1';
@@ -847,9 +939,10 @@ package body tb_common_pkg is
in_sop <= '0';
end proc_common_sop;
- procedure proc_common_eop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic) is
+ procedure proc_common_eop (
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic) is
begin
in_val <= '1';
in_eop <= '1';
@@ -858,19 +951,21 @@ package body tb_common_pkg is
in_eop <= '0';
end proc_common_eop;
- procedure proc_common_val(constant c_val_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic) is
+ procedure proc_common_val (
+ constant c_val_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic) is
begin
in_val <= '1';
proc_common_wait_some_cycles(clk, c_val_len);
in_val <= '0';
end proc_common_val;
- procedure proc_common_val_duty(constant c_hi_len : in natural;
- constant c_lo_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic) is
+ procedure proc_common_val_duty (
+ constant c_hi_len : in natural;
+ constant c_lo_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic) is
begin
in_val <= '1';
proc_common_wait_some_cycles(clk, c_hi_len);
@@ -878,10 +973,11 @@ package body tb_common_pkg is
proc_common_wait_some_cycles(clk, c_lo_len);
end proc_common_val_duty;
- procedure proc_common_eop_flush(constant c_flush_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic) is
+ procedure proc_common_eop_flush (
+ constant c_flush_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic) is
begin
-- . eop
proc_common_eop(clk, in_val, in_eop);
@@ -893,13 +989,14 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Verify incrementing data
------------------------------------------------------------------------------
- procedure proc_common_verify_data(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal out_valid : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_common_verify_data (
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
variable v_exp_data : std_logic_vector(out_data'range);
begin
if rising_edge(clk) then
@@ -923,12 +1020,13 @@ package body tb_common_pkg is
-- PROCEDURE: Verify the DUT output valid
-- . only support ready latency c_rl = 0 or 1
------------------------------------------------------------------------------
- procedure proc_common_verify_valid(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal prev_ready : inout std_logic;
- signal out_valid : in std_logic) is
+ procedure proc_common_verify_valid (
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal prev_ready : inout std_logic;
+ signal out_valid : in std_logic) is
begin
if rising_edge(clk) then
-- for ready latency c_rl = 1 out_valid may only be asserted after ready
@@ -950,13 +1048,14 @@ package body tb_common_pkg is
-- PROCEDURE: Verify the DUT input to output latency
------------------------------------------------------------------------------
-- for SL ctrl
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "valid", "sop", "eop"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_ctrl : in std_logic;
- signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
- signal out_ctrl : in std_logic) is
+ procedure proc_common_verify_latency (
+ constant c_str : in string; -- e.g. "valid", "sop", "eop"
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_ctrl : in std_logic;
+ signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
+ signal out_ctrl : in std_logic) is
begin
if rising_edge(clk) then
pipe_ctrl_vec <= in_ctrl & pipe_ctrl_vec(0 to c_latency - 1); -- note: pipe_ctrl_vec(c_latency) is a dummy place holder to avoid [0:-1] range
@@ -976,13 +1075,14 @@ package body tb_common_pkg is
-- for SLV data
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_data : in std_logic_vector;
- signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
- signal out_data : in std_logic_vector) is
+ procedure proc_common_verify_latency (
+ constant c_str : in string; -- e.g. "data"
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_data : in std_logic_vector;
+ signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
+ signal out_data : in std_logic_vector) is
constant c_data_w : natural := in_data'length;
constant c_data_vec_w : natural := pipe_data_vec'length; -- = (1 + c_latency) * c_data_w
begin
@@ -1006,11 +1106,12 @@ package body tb_common_pkg is
-- PROCEDURE: Verify the expected value
-- . e.g. to check that a test has ran at all
------------------------------------------------------------------------------
- procedure proc_common_verify_value(constant mode : in natural;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector) is
+ procedure proc_common_verify_value (
+ constant mode : in natural;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector) is
begin
if rising_edge(clk) then
if en = '1' then
@@ -1027,10 +1128,11 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Opens a file for access and reports fail or success of opening.
------------------------------------------------------------------------------
- procedure proc_common_open_file( file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- file_name : in string;
- file_mode : in FILE_OPEN_KIND) is
+ procedure proc_common_open_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ file_name : in string;
+ file_mode : in FILE_OPEN_KIND) is
begin
if file_status = OPEN_OK then
file_close(in_file);
@@ -1043,14 +1145,15 @@ package body tb_common_pkg is
end if;
end proc_common_open_file;
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
-- PROCEDURE: Reads an integer from a file.
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer) is
- variable v_line : LINE;
- variable v_good : boolean;
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
begin
if file_status /= OPEN_OK then
report "COMMON : file is not opened " severity FAILURE;
@@ -1070,12 +1173,13 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Reads two integers from two columns in a file.
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer;
- read_value_1 : out integer) is
- variable v_line : LINE;
- variable v_good : boolean;
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer;
+ read_value_1 : out integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
begin
if file_status /= OPEN_OK then
report "COMMON : file is not opened " severity FAILURE;
@@ -1096,15 +1200,16 @@ package body tb_common_pkg is
end if;
end proc_common_readline_file;
-------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
-- PROCEDURE: Reads an array of integer from a file.
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- value_array : out t_integer_arr;
- nof_reads : in integer) is
- variable v_line : LINE;
- variable v_good : boolean;
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ value_array : out t_integer_arr;
+ nof_reads : in integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
begin
if file_status /= OPEN_OK then
report "COMMON : file is not opened " severity FAILURE;
@@ -1126,11 +1231,12 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Reads an std_logic_vector from a file
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_slv : out std_logic_vector) is
- variable v_line : LINE;
- variable v_good : boolean;
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_slv : out std_logic_vector) is
+ variable v_line : LINE;
+ variable v_good : boolean;
begin
if file_status /= OPEN_OK then
report "COMMON : file is not opened " severity FAILURE;
@@ -1150,9 +1256,10 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Reads a string of any length from a file pointer.
------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- res_string : out string) is
+ procedure proc_common_readline_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ res_string : out string) is
variable v_line : LINE;
variable v_char : character;
variable is_string : boolean;
@@ -1166,16 +1273,16 @@ package body tb_common_pkg is
readline(in_file, v_line);
-- clear the contents of the result string
for I in res_string'range loop
- res_string(I) := ' ';
+ res_string(I) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for I in res_string'range loop
- read(v_line, v_char, is_string);
- if not is_string then -- found end of line
- exit;
- end if;
- res_string(I) := v_char;
+ read(v_line, v_char, is_string);
+ if not is_string then -- found end of line
+ exit;
+ end if;
+ res_string(I) := v_char;
end loop;
end if;
end if;
@@ -1185,8 +1292,9 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Closes a file.
------------------------------------------------------------------------------
- procedure proc_common_close_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT) is
+ procedure proc_common_close_file (
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT) is
begin
if file_status /= OPEN_OK then
report "COMMON : file was not opened " severity WARNING;
@@ -1200,11 +1308,12 @@ package body tb_common_pkg is
-- row from a file and returns it row by row in an array of
-- integers.
------------------------------------------------------------------------------
- procedure proc_common_read_integer_file(file_name : in string;
- nof_header_lines : natural;
- nof_row : natural;
- nof_col : natural;
- signal return_array : out t_integer_arr) is
+ procedure proc_common_read_integer_file (
+ file_name : in string;
+ nof_header_lines : natural;
+ nof_row : natural;
+ nof_col : natural;
+ signal return_array : out t_integer_arr) is
variable v_file_status : FILE_OPEN_STATUS;
file v_in_file : TEXT;
variable v_input_line : LINE;
@@ -1241,8 +1350,9 @@ package body tb_common_pkg is
-- PROCEDURE: Reads the data column from a .mif file and returns it in an
-- array of integers
------------------------------------------------------------------------------
- procedure proc_common_read_mif_file( file_name : in string;
- signal return_array : out t_integer_arr) is
+ procedure proc_common_read_mif_file (
+ file_name : in string;
+ signal return_array : out t_integer_arr) is
variable v_file_status : FILE_OPEN_STATUS;
file v_in_file : TEXT;
variable v_input_line : LINE;
@@ -1285,7 +1395,7 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- FUNCTION: Complex multiply with conjugate option for input b
------------------------------------------------------------------------------
- function func_complex_multiply(in_ar, in_ai, in_br, in_bi : std_logic_vector; conjugate_b : boolean; str : string; g_out_dat_w : natural) return std_logic_vector is
+ function func_complex_multiply (in_ar, in_ai, in_br, in_bi : std_logic_vector; conjugate_b : boolean; str : string; g_out_dat_w : natural) return std_logic_vector is
-- Function: Signed complex multiply
-- p = a * b when g_conjugate_b = FALSE
-- = (ar + j ai) * (br + j bi)
@@ -1343,7 +1453,7 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- FUNCTION: Converts the decimal value represented in a string to an integer value.
------------------------------------------------------------------------------
- function func_decstring_to_integer(in_string: string) return integer is
+ function func_decstring_to_integer (in_string: string) return integer is
constant c_nof_digits : natural := in_string'length; -- Define the length of the string
variable v_char : character;
variable v_weight : integer := 1;
@@ -1353,17 +1463,17 @@ package body tb_common_pkg is
for I in c_nof_digits - 1 downto 0 loop
v_char := in_string(I + in_string'low);
case v_char is
- when '0' => v_return_int := v_return_int + 0 * v_weight;
- when '1' => v_return_int := v_return_int + 1 * v_weight;
- when '2' => v_return_int := v_return_int + 2 * v_weight;
- when '3' => v_return_int := v_return_int + 3 * v_weight;
- when '4' => v_return_int := v_return_int + 4 * v_weight;
- when '5' => v_return_int := v_return_int + 5 * v_weight;
- when '6' => v_return_int := v_return_int + 6 * v_weight;
- when '7' => v_return_int := v_return_int + 7 * v_weight;
- when '8' => v_return_int := v_return_int + 8 * v_weight;
- when '9' => v_return_int := v_return_int + 9 * v_weight;
- when others => null;
+ when '0' => v_return_int := v_return_int + 0 * v_weight;
+ when '1' => v_return_int := v_return_int + 1 * v_weight;
+ when '2' => v_return_int := v_return_int + 2 * v_weight;
+ when '3' => v_return_int := v_return_int + 3 * v_weight;
+ when '4' => v_return_int := v_return_int + 4 * v_weight;
+ when '5' => v_return_int := v_return_int + 5 * v_weight;
+ when '6' => v_return_int := v_return_int + 6 * v_weight;
+ when '7' => v_return_int := v_return_int + 7 * v_weight;
+ when '8' => v_return_int := v_return_int + 8 * v_weight;
+ when '9' => v_return_int := v_return_int + 9 * v_weight;
+ when others => null;
end case;
if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
v_weight := v_weight * 10; -- Addapt the weight for the next decimal digit.
@@ -1375,7 +1485,7 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- FUNCTION: Converts the hexadecimal value represented in a string to an integer value.
------------------------------------------------------------------------------
- function func_hexstring_to_integer(in_string: string) return integer is
+ function func_hexstring_to_integer (in_string: string) return integer is
constant c_nof_digits : natural := in_string'length; -- Define the length of the string
variable v_char : character;
variable v_weight : integer := 1;
@@ -1385,23 +1495,23 @@ package body tb_common_pkg is
for I in c_nof_digits - 1 downto 0 loop
v_char := in_string(I + in_string'low);
case v_char is
- when '0' => v_return_int := v_return_int + 0 * v_weight;
- when '1' => v_return_int := v_return_int + 1 * v_weight;
- when '2' => v_return_int := v_return_int + 2 * v_weight;
- when '3' => v_return_int := v_return_int + 3 * v_weight;
- when '4' => v_return_int := v_return_int + 4 * v_weight;
- when '5' => v_return_int := v_return_int + 5 * v_weight;
- when '6' => v_return_int := v_return_int + 6 * v_weight;
- when '7' => v_return_int := v_return_int + 7 * v_weight;
- when '8' => v_return_int := v_return_int + 8 * v_weight;
- when '9' => v_return_int := v_return_int + 9 * v_weight;
- when 'A' | 'a' => v_return_int := v_return_int + 10 * v_weight;
- when 'B' | 'b' => v_return_int := v_return_int + 11 * v_weight;
- when 'C' | 'c' => v_return_int := v_return_int + 12 * v_weight;
- when 'D' | 'd' => v_return_int := v_return_int + 13 * v_weight;
- when 'E' | 'e' => v_return_int := v_return_int + 14 * v_weight;
- when 'F' | 'f' => v_return_int := v_return_int + 15 * v_weight;
- when others => null;
+ when '0' => v_return_int := v_return_int + 0 * v_weight;
+ when '1' => v_return_int := v_return_int + 1 * v_weight;
+ when '2' => v_return_int := v_return_int + 2 * v_weight;
+ when '3' => v_return_int := v_return_int + 3 * v_weight;
+ when '4' => v_return_int := v_return_int + 4 * v_weight;
+ when '5' => v_return_int := v_return_int + 5 * v_weight;
+ when '6' => v_return_int := v_return_int + 6 * v_weight;
+ when '7' => v_return_int := v_return_int + 7 * v_weight;
+ when '8' => v_return_int := v_return_int + 8 * v_weight;
+ when '9' => v_return_int := v_return_int + 9 * v_weight;
+ when 'A' | 'a' => v_return_int := v_return_int + 10 * v_weight;
+ when 'B' | 'b' => v_return_int := v_return_int + 11 * v_weight;
+ when 'C' | 'c' => v_return_int := v_return_int + 12 * v_weight;
+ when 'D' | 'd' => v_return_int := v_return_int + 13 * v_weight;
+ when 'E' | 'e' => v_return_int := v_return_int + 14 * v_weight;
+ when 'F' | 'f' => v_return_int := v_return_int + 15 * v_weight;
+ when others => null;
end case;
if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
v_weight := v_weight * 16; -- Addapt the weight for the next hexadecimal digit.
@@ -1414,7 +1524,7 @@ package body tb_common_pkg is
-- FUNCTION: Finds the first instance of a given character in a string
-- and returns its position.
------------------------------------------------------------------------------
- function func_find_char_in_string(in_string: string; find_char: character) return integer is
+ function func_find_char_in_string (in_string: string; find_char: character) return integer is
variable v_char_position : integer := 0;
begin
for I in 1 to in_string'length loop
@@ -1429,7 +1539,7 @@ package body tb_common_pkg is
-- FUNCTION: Checks if a string(find_string) is part of a larger string(in_string).
-- The result is returned as a BOOLEAN.
------------------------------------------------------------------------------
- function func_find_string_in_string(in_string: string; find_string: string) return boolean is
+ function func_find_string_in_string (in_string: string; find_string: string) return boolean is
constant c_in_length : natural := in_string'length; -- Define the length of the string to search in
constant c_find_length : natural := find_string'length; -- Define the length of the string to be find
variable v_found_it : boolean := false;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
index 0743eff398..b5ddce40a5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
@@ -30,9 +30,9 @@
-- . if no failure messages are printed, TB ran OK.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_common_pulse_delay is
end tb_common_pulse_delay;
@@ -105,18 +105,18 @@ begin
-- common_pulse_delay
-----------------------------------------------------------------------------
u_common_pulse_delay : entity work.common_pulse_delay
- generic map (
- g_pulse_delay_max => c_pulse_delay_max,
- g_register_out => true
- )
- port map (
- clk => clk,
- rst => rst,
-
- pulse_in => pulse_in,
- pulse_delay => pulse_delay,
- pulse_out => pulse_out
- );
+ generic map (
+ g_pulse_delay_max => c_pulse_delay_max,
+ g_register_out => true
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ pulse_in => pulse_in,
+ pulse_delay => pulse_delay,
+ pulse_out => pulse_out
+ );
-----------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
index 57b2c858be..5ec2a3aa45 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_pulse_extend is
generic (
@@ -74,17 +74,17 @@ begin
end process;
u_spulse : entity work.common_pulse_extend
- generic map (
- g_rst_level => '0',
- g_p_in_level => g_p_in_level,
- g_ep_out_level => g_ep_out_level,
- g_extend_w => c_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- p_in => pulse_in,
- ep_out => pulse_out
- );
+ generic map (
+ g_rst_level => '0',
+ g_p_in_level => g_p_in_level,
+ g_ep_out_level => g_ep_out_level,
+ g_extend_w => c_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ p_in => pulse_in,
+ ep_out => pulse_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
index e66980b996..fd6a974e05 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_pulser is
end tb_common_pulser;
@@ -69,54 +69,54 @@ begin
end process;
u_reset : entity work.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => clk,
- out_rst => rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => clk,
+ out_rst => rst
+ );
u_pulse_us : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_us,
- g_pulse_phase => c_pulse_us - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => '1',
- pulse_clr => '0',
- pulse_out => pulse_us
- );
+ generic map (
+ g_pulse_period => c_pulse_us,
+ g_pulse_phase => c_pulse_us - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => '1',
+ pulse_clr => '0',
+ pulse_out => pulse_us
+ );
u_pulse_ms_via_clk_en : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_ms
- )
- port map (
- rst => rst,
- clk => clk,
- clken => pulse_us,
- pulse_en => '1',
- pulse_clr => pulse_ms_clr,
- pulse_out => pulse_ms_via_clk_en
- );
+ generic map (
+ g_pulse_period => c_pulse_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => pulse_us,
+ pulse_en => '1',
+ pulse_clr => pulse_ms_clr,
+ pulse_out => pulse_ms_via_clk_en
+ );
u_pulse_ms_via_pulse_en : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_ms
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_us,
- pulse_clr => pulse_ms_clr,
- pulse_out => pulse_ms_via_pulse_en
- );
+ generic map (
+ g_pulse_period => c_pulse_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_us,
+ pulse_clr => pulse_ms_clr,
+ pulse_out => pulse_ms_via_pulse_en
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
index 73b51cfc43..09ff22fd10 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
@@ -30,9 +30,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_pulser_us_ms_s is
end tb_common_pulser_us_ms_s;
@@ -92,18 +92,18 @@ begin
end process;
u_common_pulser_us_ms_s : entity work.common_pulser_us_ms_s
- generic map (
- g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
- g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- sync => sync,
- pulse_us => pulse_us, -- pulses after every g_pulse_us clock cycles
- pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
- pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
- );
+ generic map (
+ g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
+ g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ sync => sync,
+ pulse_us => pulse_us, -- pulses after every g_pulse_us clock cycles
+ pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
index b1d3dbe6d1..dae12b4845 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_reg_cross_domain is
end tb_common_reg_cross_domain;
@@ -111,26 +111,26 @@ begin
end process;
u_out_rst : entity work.common_areset
- port map (
- in_rst => in_rst,
- clk => out_clk,
- out_rst => out_rst
- );
+ port map (
+ in_rst => in_rst,
+ clk => out_clk,
+ out_rst => out_rst
+ );
u_reg_cross_domain : entity work.common_reg_cross_domain
- generic map (
- g_in_new_latency => c_in_new_latency
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_new => in_new, -- when '1' then new in_dat is available after g_in_new_latency
- in_dat => in_dat,
- in_done => in_done,
- out_rst => out_rst,
- out_clk => out_clk,
- out_dat => out_dat,
- out_new => out_new -- when '1' then the out_dat was updated with in_dat due to in_new
- );
+ generic map (
+ g_in_new_latency => c_in_new_latency
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_new => in_new, -- when '1' then new in_dat is available after g_in_new_latency
+ in_dat => in_dat,
+ in_done => in_done,
+ out_rst => out_rst,
+ out_clk => out_clk,
+ out_dat => out_dat,
+ out_new => out_new -- when '1' then the out_dat was updated with in_dat due to in_new
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
index e6aaf8a6fc..6ae3451752 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
-- Purpose: Test bench to check reinterleave function visually
-- Usage:
@@ -40,7 +40,7 @@ entity tb_common_reinterleave is
g_inter_block_size : natural := 2;
g_concat_id : boolean := true; -- Concatenate a 1 byte stream ID 0xA..F @ MSB so user can follow streams in wave window
g_cnt_sync : boolean := true -- When TRUE all generated streams start at 0, else they're offset by 16 counter values.
- );
+ );
end;
architecture rtl of tb_common_reinterleave is
@@ -146,23 +146,23 @@ begin
-- DUT
-----------------------------------------------------------------------------
u_reinterleave : entity work.common_reinterleave
- generic map (
- g_nof_in => g_nof_in,
- g_deint_block_size => g_deint_block_size,
- g_nof_out => g_nof_out,
- g_inter_block_size => g_inter_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => dut_in_dat,
- in_val => dut_in_val_arr(0), -- All input streams should be synchronous in terms of timing
-
- out_dat => dut_out_dat,
- out_val => dut_out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_deint_block_size => g_deint_block_size,
+ g_nof_out => g_nof_out,
+ g_inter_block_size => g_inter_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => dut_in_dat,
+ in_val => dut_in_val_arr(0), -- All input streams should be synchronous in terms of timing
+
+ out_dat => dut_out_dat,
+ out_val => dut_out_val
+ );
-----------------------------------------------------------------------------
-- Map DUT output SLV to array of streams (to ease viewing in wave window)
@@ -175,23 +175,23 @@ begin
-- REVERSE FUNCTION; the outputs should match the DUT inputs (with delay)
-----------------------------------------------------------------------------
u_rev_reinterleave : entity work.common_reinterleave
- generic map (
- g_nof_in => g_nof_out, -- Note the reversed generics
- g_deint_block_size => g_inter_block_size,
- g_nof_out => g_nof_in,
- g_inter_block_size => g_deint_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => dut_out_dat,
- in_val => dut_out_val(0),
-
- out_dat => rev_out_dat,
- out_val => rev_out_val
- );
+ generic map (
+ g_nof_in => g_nof_out, -- Note the reversed generics
+ g_deint_block_size => g_inter_block_size,
+ g_nof_out => g_nof_in,
+ g_inter_block_size => g_deint_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => dut_out_dat,
+ in_val => dut_out_val(0),
+
+ out_dat => rev_out_dat,
+ out_val => rev_out_val
+ );
-----------------------------------------------------------------------------
-- Map REV output SLV to array of streams
diff --git a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
index 5d6a184eb8..1af391257d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Test bench for common_reorder_symbol.vhd
-- Usage:
@@ -45,11 +45,11 @@ use common_lib.common_pkg.all;
entity tb_common_reorder_symbol is
generic (
--- g_nof_input : NATURAL := 3;
--- g_nof_output : NATURAL := 3;
--- g_symbol_w : NATURAL := 8;
--- g_select_arr : t_natural_arr := (3, 3, 3); --array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
--- g_pipeline_arr : t_natural_arr := (0,0,0,0) --array_init(0, 5) -- range must fit [0:c_N]
+ -- g_nof_input : NATURAL := 3;
+ -- g_nof_output : NATURAL := 3;
+ -- g_symbol_w : NATURAL := 8;
+ -- g_select_arr : t_natural_arr := (3, 3, 3); --array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
+ -- g_pipeline_arr : t_natural_arr := (0,0,0,0) --array_init(0, 5) -- range must fit [0:c_N]
g_nof_input : natural := 5;
g_nof_output : natural := 5;
g_symbol_w : natural := 8;
@@ -154,32 +154,32 @@ begin
-- DUT
u_reorder_in : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_output,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
- in_sync => in_sync,
-
- in_select => in_select_vec,
-
- out_data => reorder_data_vec,
- out_val => reorder_val,
- out_sop => reorder_sop,
- out_eop => reorder_eop,
- out_sync => reorder_sync
- );
+ generic map (
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_output,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+ in_sync => in_sync,
+
+ in_select => in_select_vec,
+
+ out_data => reorder_data_vec,
+ out_val => reorder_val,
+ out_sop => reorder_sop,
+ out_eop => reorder_eop,
+ out_sync => reorder_sync
+ );
-- inverse DUT
inverse_select_arr <= func_common_reorder2_inverse_select(c_N, in_select_arr);
@@ -189,60 +189,60 @@ begin
end generate;
u_inverse_in : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => reorder_data_vec,
- in_val => reorder_val,
- in_sop => reorder_sop,
- in_eop => reorder_eop,
- in_sync => reorder_sync,
-
- in_select => inverse_select_vec(c_nof_select * c_select_w - 1 downto 0),
-
- out_data => inverse_data_vec,
- out_val => inverse_val,
- out_sop => inverse_sop,
- out_eop => inverse_eop,
- out_sync => inverse_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => reorder_data_vec,
+ in_val => reorder_val,
+ in_sop => reorder_sop,
+ in_eop => reorder_eop,
+ in_sync => reorder_sync,
+
+ in_select => inverse_select_vec(c_nof_select * c_select_w - 1 downto 0),
+
+ out_data => inverse_data_vec,
+ out_val => inverse_val,
+ out_sop => inverse_sop,
+ out_eop => inverse_eop,
+ out_sync => inverse_sync
+ );
u_inverse_out : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => inverse_data_vec,
- in_val => inverse_val,
- in_sop => inverse_sop,
- in_eop => inverse_eop,
- in_sync => inverse_sync,
-
- in_select => inverse_select_vec(2 * c_nof_select * c_select_w - 1 downto c_nof_select * c_select_w),
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => inverse_data_vec,
+ in_val => inverse_val,
+ in_sop => inverse_sop,
+ in_eop => inverse_eop,
+ in_sync => inverse_sync,
+
+ in_select => inverse_select_vec(2 * c_nof_select * c_select_w - 1 downto c_nof_select * c_select_w),
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
-- Verification
p_verify : process(rst, clk)
@@ -259,61 +259,61 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => c_total_pipeline,
- g_in_dat_w => g_nof_input * g_symbol_w,
- g_out_dat_w => g_nof_input * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => c_total_pipeline,
+ g_in_dat_w => g_nof_input * g_symbol_w,
+ g_out_dat_w => g_nof_input * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => exp_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => exp_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
index 9976c8b156..3bbc9e7fd3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
@@ -38,11 +38,11 @@
-- works when g_rl_increase_en is FALSE or both are FALSE.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_rl is
@@ -157,64 +157,64 @@ begin
fifo_out_ready <= '1';
u_fifo_sc : entity work.common_fifo_sc
- generic map (
- g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_dat_w => c_dat_w,
- g_nof_words => g_fifo_size,
- g_af_margin => c_fifo_af_margin
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_in_dat,
- wr_req => fifo_in_val,
- wr_ful => fifo_ful,
- wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_increase_in_ready
- rd_dat => fifo_out_dat,
- rd_req => fifo_in_ready,
- rd_emp => fifo_emp,
- rd_val => fifo_out_val,
- usedw => fifo_usedw
- );
+ generic map (
+ g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_dat_w => c_dat_w,
+ g_nof_words => g_fifo_size,
+ g_af_margin => c_fifo_af_margin
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_in_dat,
+ wr_req => fifo_in_val,
+ wr_ful => fifo_ful,
+ wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_increase_in_ready
+ rd_dat => fifo_out_dat,
+ rd_req => fifo_in_ready,
+ rd_emp => fifo_emp,
+ rd_val => fifo_out_val,
+ usedw => fifo_usedw
+ );
-- RL 1 --> 0
u_rl_decrease : entity work.common_rl_decrease
- generic map (
- g_adapt => g_rl_decrease_en,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => fifo_in_ready,
- snk_in_dat => fifo_out_dat,
- snk_in_val => fifo_out_val,
- -- ST source: RL = 0
- src_in_ready => rl_decrease_in_ready,
- src_out_dat => rl_decrease_out_dat,
- src_out_val => rl_decrease_out_val
- );
+ generic map (
+ g_adapt => g_rl_decrease_en,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => fifo_in_ready,
+ snk_in_dat => fifo_out_dat,
+ snk_in_val => fifo_out_val,
+ -- ST source: RL = 0
+ src_in_ready => rl_decrease_in_ready,
+ src_out_dat => rl_decrease_out_dat,
+ src_out_val => rl_decrease_out_val
+ );
-- RL 0 --> 1
u_rl_increase : entity work.common_rl_increase
- generic map (
- g_adapt => c_rl_increase_en,
- g_hold_dat_en => g_rl_increase_hold_dat_en,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- Sink
- snk_out_ready => rl_decrease_in_ready,
- snk_in_dat => rl_decrease_out_dat,
- snk_in_val => rl_decrease_out_val,
- -- Source
- src_in_ready => rl_increase_in_ready,
- src_out_dat => rl_increase_out_dat,
- src_out_val => rl_increase_out_val
- );
+ generic map (
+ g_adapt => c_rl_increase_en,
+ g_hold_dat_en => g_rl_increase_hold_dat_en,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Sink
+ snk_out_ready => rl_decrease_in_ready,
+ snk_in_dat => rl_decrease_out_dat,
+ snk_in_val => rl_decrease_out_val,
+ -- Source
+ src_in_ready => rl_increase_in_ready,
+ src_out_dat => rl_increase_out_dat,
+ src_out_val => rl_increase_out_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
index badacc5236..52bf654214 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
@@ -30,11 +30,11 @@
-- rl_register_in_ready='1' to avoid FIFO overflow.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_rl_register is
@@ -136,44 +136,44 @@ begin
fifo_out_ready <= '1';
u_fifo_sc : entity work.common_fifo_sc
- generic map (
- g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_dat_w => c_dat_w,
- g_nof_words => g_fifo_size,
- g_af_margin => c_fifo_af_margin
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_in_dat,
- wr_req => fifo_in_val,
- wr_ful => fifo_ful,
- wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_register_in_ready
- rd_dat => fifo_out_dat,
- rd_req => fifo_in_ready,
- rd_emp => fifo_emp,
- rd_val => fifo_out_val,
- usedw => fifo_usedw
- );
+ generic map (
+ g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_dat_w => c_dat_w,
+ g_nof_words => g_fifo_size,
+ g_af_margin => c_fifo_af_margin
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_in_dat,
+ wr_req => fifo_in_val,
+ wr_ful => fifo_ful,
+ wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_register_in_ready
+ rd_dat => fifo_out_dat,
+ rd_req => fifo_in_ready,
+ rd_emp => fifo_emp,
+ rd_val => fifo_out_val,
+ usedw => fifo_usedw
+ );
-- RL 1 --> 0 --> 1
u_rl_register : entity work.common_rl_register
- generic map (
- g_adapt => g_rl_register_en,
- g_hold_dat_en => g_rl_register_hold_dat_en,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => fifo_in_ready,
- snk_in_dat => fifo_out_dat,
- snk_in_val => fifo_out_val,
- -- ST source: RL = 0
- src_in_ready => rl_register_in_ready,
- src_out_dat => rl_register_out_dat,
- src_out_val => rl_register_out_val
- );
+ generic map (
+ g_adapt => g_rl_register_en,
+ g_hold_dat_en => g_rl_register_hold_dat_en,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => fifo_in_ready,
+ snk_in_dat => fifo_out_dat,
+ snk_in_val => fifo_out_val,
+ -- ST source: RL = 0
+ src_in_ready => rl_register_in_ready,
+ src_out_dat => rl_register_out_dat,
+ src_out_val => rl_register_out_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
index d7aca1f817..6a7e14936c 100644
--- a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Test bench for common_select_m_symbols.vhd
-- Usage:
@@ -137,64 +137,64 @@ begin
-- DUT
u_reorder_in : entity work.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_output,
- g_symbol_w => g_symbol_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
- in_sync => in_sync,
-
- in_select => in_select_vec,
-
- out_data => reorder_data_vec,
- out_val => reorder_val,
- out_sop => reorder_sop,
- out_eop => reorder_eop,
- out_sync => reorder_sync
- );
+ generic map (
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_output,
+ g_symbol_w => g_symbol_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+ in_sync => in_sync,
+
+ in_select => in_select_vec,
+
+ out_data => reorder_data_vec,
+ out_val => reorder_val,
+ out_sop => reorder_sop,
+ out_eop => reorder_eop,
+ out_sync => reorder_sync
+ );
gen_inverse_select_vec: for K in g_nof_output - 1 downto 0 generate
inverse_select_vec((K + 1) * c_select_w - 1 downto K * c_select_w) <= TO_UVEC(inverse_select_arr(K), c_select_w);
end generate;
u_inverse_out : entity work.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => reorder_data_vec,
- in_val => reorder_val,
- in_sop => reorder_sop,
- in_eop => reorder_eop,
- in_sync => reorder_sync,
-
- in_select => inverse_select_vec,
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => reorder_data_vec,
+ in_val => reorder_val,
+ in_sop => reorder_sop,
+ in_eop => reorder_eop,
+ in_sync => reorder_sync,
+
+ in_select => inverse_select_vec,
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
-- Verification
p_verify : process(rst, clk)
@@ -211,61 +211,61 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => c_total_pipeline,
- g_in_dat_w => g_nof_input * g_symbol_w,
- g_out_dat_w => g_nof_input * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => c_total_pipeline,
+ g_in_dat_w => g_nof_input * g_symbol_w,
+ g_out_dat_w => g_nof_input * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => exp_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => exp_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
index a177c30446..e5e8234626 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
@@ -30,10 +30,10 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_shiftram is
generic (
@@ -110,22 +110,22 @@ begin
-- DUT
u_common_shiftram : entity work.common_shiftram
- generic map (
- g_data_w => g_data_w,
- g_nof_words => g_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_in => data_in,
- data_in_val => data_in_val,
- data_in_shift => data_in_shift,
-
- data_out => data_out,
- data_out_val => data_out_val,
- data_out_shift => data_out_shift
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_nof_words => g_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_in => data_in,
+ data_in_val => data_in_val,
+ data_in_shift => data_in_shift,
+
+ data_out => data_out,
+ data_out_val => data_out_val,
+ data_out_shift => data_out_shift
+ );
-- Make sure prev_data_out has been assigned
p_verify_start: process
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
index 6ef434b87d..5f7f04aa0d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
-- Purpose: Test bench for common_shiftreg.vhd
-- Usage:
@@ -158,32 +158,32 @@ begin
-- DUT
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_pipeline,
- g_flush_en => g_flush_en,
- g_nof_dat => g_nof_dat,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_dat,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
-
- out_data_vec => out_data_vec,
- out_val_vec => out_val_vec,
- out_sop_vec => out_sop_vec,
- out_eop_vec => out_eop_vec,
- out_cnt => out_cnt,
-
- out_dat => out_dat,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_flush_en => g_flush_en,
+ g_nof_dat => g_nof_dat,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_dat,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+
+ out_data_vec => out_data_vec,
+ out_val_vec => out_val_vec,
+ out_sop_vec => out_sop_vec,
+ out_eop_vec => out_eop_vec,
+ out_cnt => out_cnt,
+
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop
+ );
-- Verification
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_dat, prev_out_dat);
diff --git a/libraries/base/common/tb/vhdl/tb_common_spulse.vhd b/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
index c8e5d4a023..365a1caa51 100644
--- a/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
@@ -27,9 +27,9 @@
-- > run 1 us
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_spulse is
end tb_common_spulse;
@@ -70,23 +70,23 @@ begin
end process;
u_out_rst : entity work.common_areset
- port map (
- in_rst => in_rst,
- clk => out_clk,
- out_rst => out_rst
- );
+ port map (
+ in_rst => in_rst,
+ clk => out_clk,
+ out_rst => out_rst
+ );
u_spulse : entity work.common_spulse
- generic map (
- g_delay_len => c_meta_delay
- )
- port map (
- in_clk => in_clk,
- in_rst => in_rst,
- in_pulse => in_pulse,
- out_clk => out_clk,
- out_rst => out_rst,
- out_pulse => out_pulse
- );
+ generic map (
+ g_delay_len => c_meta_delay
+ )
+ port map (
+ in_clk => in_clk,
+ in_rst => in_rst,
+ in_pulse => in_pulse,
+ out_clk => out_clk,
+ out_rst => out_rst,
+ out_pulse => out_pulse
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_switch.vhd b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
index 9200eaae31..04c4badad0 100644
--- a/libraries/base/common/tb/vhdl/tb_common_switch.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_switch is
end tb_common_switch;
@@ -49,13 +49,13 @@ architecture tb of tb_common_switch is
constant c_nof_dut : natural := 2**c_nof_generics;
constant c_generics_matrix : t_boolean_matrix(0 to c_nof_dut - 1, 0 to c_nof_generics - 1) := ((false, false, false),
- (false, false, true),
- (false, true, false),
- (false, true, true),
- ( true, false, false),
- ( true, false, true),
- ( true, true, false),
- ( true, true, true));
+ (false, false, true),
+ (false, true, false),
+ (false, true, true),
+ ( true, false, false),
+ ( true, false, true),
+ ( true, true, false),
+ ( true, true, true));
-- View constants in Wave window
signal dbg_c_generics_matrix : t_boolean_matrix(0 to c_nof_dut - 1, 0 to c_nof_generics - 1) := c_generics_matrix;
signal dbg_state : natural;
@@ -226,20 +226,20 @@ begin
gen_dut : for I in 0 to c_nof_dut - 1 generate
u_switch : entity work.common_switch
- generic map (
- g_rst_level => '0', -- output level at reset.
- --g_rst_level => '1',
- g_priority_lo => c_generics_matrix(I,0),
- g_or_high => c_generics_matrix(I,1),
- g_and_low => c_generics_matrix(I,2)
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_hi,
- switch_low => in_lo,
- out_level => out_level(I)
- );
+ generic map (
+ g_rst_level => '0', -- output level at reset.
+ --g_rst_level => '1',
+ g_priority_lo => c_generics_matrix(I,0),
+ g_or_high => c_generics_matrix(I,1),
+ g_and_low => c_generics_matrix(I,2)
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_hi,
+ switch_low => in_lo,
+ out_level => out_level(I)
+ );
end generate;
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
index fa6aae58d7..ae07044cae 100644
--- a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
@@ -42,9 +42,9 @@
-- signals with radix unsigend.
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use work.common_pkg.all;
entity tb_common_to_sreal is
@@ -71,8 +71,9 @@ architecture tb of tb_common_to_sreal is
signal dbg_resolution_w : integer := 0;
signal dbg_resolution : real := 0.0;
- procedure proc_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in natural) is
+ procedure proc_wait_some_cycles (
+ signal clk : in std_logic;
+ c_nof_cycles : in natural) is
begin
for I in 0 to c_nof_cycles - 1 loop wait until rising_edge(clk); end loop;
end proc_wait_some_cycles;
@@ -135,19 +136,19 @@ begin
v_real := -6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := -6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 7.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
proc_wait_some_cycles(clk, 5);
-- . Just overflow with 4 bit integers for -16.5 : +15.5
v_real := -15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
proc_wait_some_cycles(clk, 5);
-- . Negative clip to 0 for unsigned
@@ -164,17 +165,17 @@ begin
v_real := -28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := -18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
proc_wait_some_cycles(clk, 10);
tb_end <= '1';
diff --git a/libraries/base/common/tb/vhdl/tb_common_toggle.vhd b/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
index b1eb5283ae..186b5c3bec 100644
--- a/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
@@ -27,9 +27,9 @@
-- Observe the out_toggle during the different stimuli indicated by tb_state.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_toggle is
end tb_common_toggle;
@@ -100,17 +100,17 @@ begin
end process;
u_toggle : entity work.common_toggle
- generic map (
- g_evt_type => "RISING",
- g_rst_level => '0'
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_dat,
- in_val => in_val,
- out_dat => out_toggle
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_dat,
+ in_val => in_val,
+ out_dat => out_toggle
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd b/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
index b8658765ef..f6b937eab7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
@@ -27,9 +27,9 @@
-- Observe out_toggle in Wave Window in relation to in_toggle and align
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_toggle_align is
end tb_common_toggle_align;
@@ -129,16 +129,16 @@ begin
end process;
u_toggle : entity work.common_toggle_align
- generic map (
- g_pipeline => c_pipeline,
- g_nof_clk_per_period => c_toggle_period
- )
- port map (
- rst => rst,
- clk => clk,
- in_align => in_align,
- in_toggle => in_toggle,
- out_toggle => out_toggle
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_nof_clk_per_period => c_toggle_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_align => in_align,
+ in_toggle => in_toggle,
+ out_toggle => out_toggle
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
index 176ebc3051..5d1aec3419 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
-- Purpose: Test bench for common_transpose.vhd
-- Usage:
@@ -61,9 +61,10 @@ architecture tb of tb_common_transpose is
constant c_frame_len : natural := 7 * g_nof_data;
constant c_frame_eop : natural := (c_frame_len - 1) mod c_frame_len;
- procedure proc_align_eop(signal clk : in std_logic;
- signal stimuli_phase : in std_logic;
- signal in_val : out std_logic) is
+ procedure proc_align_eop (
+ signal clk : in std_logic;
+ signal stimuli_phase : in std_logic;
+ signal in_val : out std_logic) is
begin
while stimuli_phase = '0' loop
in_val <= '1';
@@ -209,58 +210,58 @@ begin
-- DUT
u_transpose_in : entity common_lib.common_transpose
- generic map (
- g_pipeline_shiftreg => g_pipeline_shiftreg,
- g_pipeline_transpose => g_pipeline_transpose,
- g_pipeline_hold => g_pipeline_hold,
- g_pipeline_select => g_pipeline_select,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w,
- g_addr_w => g_addr_w,
- g_addr_offset => g_addr_offset
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_offset => in_offset,
- in_addr => in_addr,
- in_data => in_data,
- in_val => in_val,
- in_eop => in_eop,
-
- out_addr => trans_addr,
- out_data => trans_data,
- out_val => trans_val,
- out_eop => trans_eop
- );
+ generic map (
+ g_pipeline_shiftreg => g_pipeline_shiftreg,
+ g_pipeline_transpose => g_pipeline_transpose,
+ g_pipeline_hold => g_pipeline_hold,
+ g_pipeline_select => g_pipeline_select,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w,
+ g_addr_w => g_addr_w,
+ g_addr_offset => g_addr_offset
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_offset => in_offset,
+ in_addr => in_addr,
+ in_data => in_data,
+ in_val => in_val,
+ in_eop => in_eop,
+
+ out_addr => trans_addr,
+ out_data => trans_data,
+ out_val => trans_val,
+ out_eop => trans_eop
+ );
u_transpose_out : entity common_lib.common_transpose
- generic map (
- g_pipeline_shiftreg => g_pipeline_shiftreg,
- g_pipeline_transpose => g_pipeline_transpose,
- g_pipeline_hold => g_pipeline_hold,
- g_pipeline_select => g_pipeline_select,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w,
- g_addr_w => g_addr_w,
- g_addr_offset => g_addr_offset
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_offset => trans_offset,
- in_addr => trans_addr,
- in_data => trans_data,
- in_val => trans_val,
- in_eop => trans_eop,
-
- out_addr => out_addr,
- out_data => out_data,
- out_val => out_val,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline_shiftreg => g_pipeline_shiftreg,
+ g_pipeline_transpose => g_pipeline_transpose,
+ g_pipeline_hold => g_pipeline_hold,
+ g_pipeline_select => g_pipeline_select,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w,
+ g_addr_w => g_addr_w,
+ g_addr_offset => g_addr_offset
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_offset => trans_offset,
+ in_addr => trans_addr,
+ in_data => trans_data,
+ in_val => trans_val,
+ in_eop => trans_eop,
+
+ out_addr => out_addr,
+ out_data => out_data,
+ out_val => out_val,
+ out_eop => out_eop
+ );
-- Verification p_verify
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_addr, prev_out_addr);
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
index 9dd8ce887d..2a2beb8732 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Test bench for common_transpose_symbol.vhd
-- Usage:
@@ -104,46 +104,46 @@ begin
-- DUT
u_transpose_in : entity work.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
-
- out_data => trans_data_vec,
- out_val => trans_val,
- out_sop => trans_sop,
- out_eop => trans_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+
+ out_data => trans_data_vec,
+ out_val => trans_val,
+ out_sop => trans_sop,
+ out_eop => trans_eop
+ );
u_transpose_out : entity work.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => trans_data_vec,
- in_val => trans_val,
- in_sop => trans_sop,
- in_eop => trans_eop,
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => trans_data_vec,
+ in_val => trans_val,
+ in_sop => trans_sop,
+ in_eop => trans_eop,
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop
+ );
-- Verification
p_verify : process(rst, clk)
@@ -159,50 +159,50 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline * 2,
- g_in_dat_w => g_nof_data * g_data_w,
- g_out_dat_w => g_nof_data * g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline * 2,
+ g_in_dat_w => g_nof_data * g_data_w,
+ g_out_dat_w => g_nof_data * g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index fa8c3c137f..9a10d4ddf5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -27,11 +27,11 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_variable_delay is
end tb_common_variable_delay;
@@ -71,7 +71,7 @@ begin
proc_common_gen_pulse(1, c_trigger_interval, '1', rst, clk, trigger);
p_in_stimuli : process
- variable clk_cnt : natural := 0;
+ variable clk_cnt : natural := 0;
begin
delay <= 0;
enable <= '0';
@@ -109,15 +109,15 @@ begin
-- device under test
u_dut : entity work.common_variable_delay
- port map (
- rst => rst,
- clk => clk,
-
- delay => delay,
- enable => enable,
- in_pulse => trigger,
- out_pulse => trigger_dly
- );
+ port map (
+ rst => rst,
+ clk => clk,
+
+ delay => delay,
+ enable => enable,
+ in_pulse => trigger,
+ out_pulse => trigger_dly
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_zip.vhd b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
index ad0e3a4497..acb9f52ff0 100644
--- a/libraries/base/common/tb/vhdl/tb_common_zip.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
@@ -29,11 +29,11 @@
-- to the out_dat vector.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_zip is
@@ -80,18 +80,18 @@ begin
enable <= ena and ena_mask;
u_dut : entity work.common_zip
- generic map (
- g_nof_streams => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_dat_arr => in_dat_arr,
- out_val => out_val,
- out_dat => out_dat
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_dat_arr => in_dat_arr,
+ out_val => out_val,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd b/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
index 062ea3a05b..41be24411a 100644
--- a/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
+++ b/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
@@ -86,8 +86,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity tb_delta_cycle_demo is
diff --git a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
index d5ad7b2d0b..58d68d37e8 100644
--- a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
@@ -29,13 +29,13 @@
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
-use work.tb_common_pkg.all;
-use work.common_mem_pkg.all;
-use work.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
+ use work.tb_common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.tb_common_mem_pkg.all;
entity tb_mms_common_variable_delay is
end tb_mms_common_variable_delay;
@@ -93,19 +93,19 @@ begin
-- device under test
u_dut : entity work.mms_common_variable_delay
- port map (
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
-
- reg_enable_mosi => mm_mosi,
- reg_enable_miso => mm_miso,
-
- delay => delay,
- trigger => trigger,
- trigger_dly => trigger_dly
- );
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+
+ reg_enable_mosi => mm_mosi,
+ reg_enable_miso => mm_miso,
+
+ delay => delay,
+ trigger => trigger,
+ trigger_dly => trigger_dly
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_requantize.vhd b/libraries/base/common/tb/vhdl/tb_requantize.vhd
index 292bc82c74..a8146383bd 100644
--- a/libraries/base/common/tb/vhdl/tb_requantize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_requantize.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Test bench for common_requantize.vhd
-- Usage:
@@ -138,190 +138,190 @@ begin
in_vec <= in_val & in_dat;
u_pipe : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_in_dat_w => c_in_dat_w + 1,
- g_out_dat_w => c_in_dat_w + 1
- )
- port map (
- clk => clk,
- in_dat => in_vec,
- out_dat => reg_vec
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_in_dat_w => c_in_dat_w + 1,
+ g_out_dat_w => c_in_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ in_dat => in_vec,
+ out_dat => reg_vec
+ );
reg_val <= reg_vec(c_in_dat_w);
reg_dat <= reg_vec(c_in_dat_w - 1 downto 0);
-- DUT for "SIGNED"
u_s_r_c : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_r_c_dat,
- out_ovr => out_s_r_c_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_r_c_dat,
+ out_ovr => out_s_r_c_ovr
+ );
u_s_r_w : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_r_w_dat,
- out_ovr => out_s_r_w_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_r_w_dat,
+ out_ovr => out_s_r_w_ovr
+ );
u_s_t_c : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_t_c_dat,
- out_ovr => out_s_t_c_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_t_c_dat,
+ out_ovr => out_s_t_c_ovr
+ );
u_s_t_w : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_t_w_dat,
- out_ovr => out_s_t_w_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_t_w_dat,
+ out_ovr => out_s_t_w_ovr
+ );
-- DUT for "UNSIGNED"
u_u_r_c : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_r_c_dat,
- out_ovr => out_u_r_c_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_r_c_dat,
+ out_ovr => out_u_r_c_ovr
+ );
u_u_r_w : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_r_w_dat,
- out_ovr => out_u_r_w_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_r_w_dat,
+ out_ovr => out_u_r_w_ovr
+ );
u_u_t_c : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_t_c_dat,
- out_ovr => out_u_t_c_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_t_c_dat,
+ out_ovr => out_u_t_c_ovr
+ );
u_u_t_w : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_t_w_dat,
- out_ovr => out_u_t_w_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_t_w_dat,
+ out_ovr => out_u_t_w_ovr
+ );
-- Verification usign golden results from file
p_verify : process
@@ -341,127 +341,127 @@ begin
out_u_ovr_vec <= out_u_r_c_ovr & out_u_r_w_ovr & out_u_t_c_ovr & out_u_t_w_ovr;
u_output_file_s_dat : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_dat.out",
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_s_dat_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_dat.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_s_dat_vec,
+ in_val => reg_val
+ );
u_ref_file_s_dat : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_dat.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_s_dat_vec,
- out_val => ref_val,
- out_eof => ref_eof
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_dat.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_s_dat_vec,
+ out_val => ref_val,
+ out_eof => ref_eof
+ );
u_output_file_s_ovr : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_ovr.out",
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_s_ovr_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_ovr.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_s_ovr_vec,
+ in_val => reg_val
+ );
u_ref_file_s_ovr : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_ovr.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_s_ovr_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_ovr.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_s_ovr_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
u_output_file_u_dat : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_dat.out",
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_u_dat_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_dat.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_u_dat_vec,
+ in_val => reg_val
+ );
u_ref_file_u_dat : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_dat.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_u_dat_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_dat.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_u_dat_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
u_output_file_u_ovr : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_ovr.out",
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_u_ovr_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_ovr.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_u_ovr_vec,
+ in_val => reg_val
+ );
u_ref_file_u_ovr : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_ovr.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_u_ovr_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_ovr.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_u_ovr_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_resize.vhd
index 103347252d..046c685b08 100644
--- a/libraries/base/common/tb/vhdl/tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_resize.vhd
@@ -34,9 +34,9 @@
-- . Observe reg_dat with respect to out_udat, out_uovr for unsigned
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_resize is
generic (
@@ -162,39 +162,39 @@ begin
-- DUT for "SIGNED"
u_s_resize : entity work.common_resize
- generic map (
- g_representation => "SIGNED",
- g_clip => g_clip,
- g_clip_symmetric => g_clip_symmetric,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_sdat,
- out_ovr => out_sovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_clip => g_clip,
+ g_clip_symmetric => g_clip_symmetric,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_sdat,
+ out_ovr => out_sovr
+ );
-- DUT for "UNSIGNED"
u_u_resize : entity work.common_resize
- generic map (
- g_representation => "UNSIGNED",
- g_clip => g_clip,
- g_clip_symmetric => g_clip_symmetric,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_udat,
- out_ovr => out_uovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_clip => g_clip,
+ g_clip_symmetric => g_clip_symmetric,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_udat,
+ out_ovr => out_uovr
+ );
-- Verification
p_verify : process
@@ -229,7 +229,7 @@ begin
signed(out_sdat) /= -g_clip_smin report "Wrong clipped symmetrical out_sdat" severity ERROR;
else
assert (signed(out_sdat) = signed(lowrange_sdat) or signed(out_sdat) = g_clip_smin or signed(out_sdat) = g_clip_smax)
- report "Wrong clipped out_sdat" severity ERROR;
+ report "Wrong clipped out_sdat" severity ERROR;
end if;
else
assert signed(out_sdat) = signed(lowrange_sdat) report "Wrong wrapped out_sdat" severity ERROR;
diff --git a/libraries/base/common/tb/vhdl/tb_round.vhd b/libraries/base/common/tb/vhdl/tb_round.vhd
index 025a5ed282..de54951a3b 100644
--- a/libraries/base/common/tb/vhdl/tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_round.vhd
@@ -36,9 +36,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_round is
generic (
@@ -274,86 +274,86 @@ begin
-----------------------------------------------------------------------------
s_truncate : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => false,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_truncate
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => false,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_truncate
+ );
s_round_half_away : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_away
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_away
+ );
s_round_half_away_clip : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_away_clip
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_away_clip
+ );
s_round_half_even : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_even
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_even
+ );
s_round_half_even_clip : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_even_clip
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_even_clip
+ );
-----------------------------------------------------------------------------
@@ -362,86 +362,86 @@ begin
-- DUT for truncate
u_truncate : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => false,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_truncate
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => false,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_truncate
+ );
u_round_half_up : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_up
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_up
+ );
u_round_half_up_clip : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_up_clip
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_up_clip
+ );
u_round_half_even : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => false,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_even
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_even
+ );
u_round_half_even_clip : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => true,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_even_clip
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_even_clip
+ );
-- Observe fixed point SLV values as REAL
-- . signed
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
index f26ba9b443..1dfe5596d0 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_add_sub is
end tb_tb_common_add_sub;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
index ac64038aab..f6ab79a108 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_adder_tree is
end tb_tb_common_adder_tree;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
index 5db16f1873..7e9539fe63 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
@@ -24,7 +24,7 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_create_strobes_from_valid is
end tb_tb_common_create_strobes_from_valid;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
index 3d130abe33..67cfca18e9 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_fanout_tree is
end tb_tb_common_fanout_tree;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
index 7c6305bf7c..67ddec4c4b 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_multiplexer is
end tb_tb_common_multiplexer;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
index b540247419..33169d8c32 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_operation_tree is
end tb_tb_common_operation_tree;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
index 8e92623818..f82a502d66 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_paged_ram_ww_rr is
end tb_tb_common_paged_ram_ww_rr;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
index 9af7279df9..77036c5673 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_reinterleave is
generic (
g_dat_w : natural
- );
+ );
end;
architecture rtl of tb_tb_common_reinterleave is
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
index 743ed42a04..5e3c4181fa 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_reorder_symbol is
end tb_tb_common_reorder_symbol;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
index 0e5227f17c..c6c1e7ceae 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_rl is
end tb_tb_common_rl;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
index 3e6a3c19fb..be1ea40f48 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_rl_register is
end tb_tb_common_rl_register;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
index 69f7d62d7f..8aa876c5c8 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Multi-test bench for common_transpose.vhd
-- Usage:
@@ -34,13 +34,13 @@ architecture tb of tb_tb_common_transpose is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_pipeline_shiftreg : NATURAL := 0;
--- | g_pipeline_transpose : NATURAL := 0;
--- | | g_pipeline_hold : NATURAL := 0;
--- | | | g_pipeline_select : NATURAL := 1;
--- | | | | g_nof_data : NATURAL := 3;
--- | | | | | g_data_w : NATURAL := 12
--- | | | | | |
+ -- g_pipeline_shiftreg : NATURAL := 0;
+ -- | g_pipeline_transpose : NATURAL := 0;
+ -- | | g_pipeline_hold : NATURAL := 0;
+ -- | | | g_pipeline_select : NATURAL := 1;
+ -- | | | | g_nof_data : NATURAL := 3;
+ -- | | | | | g_data_w : NATURAL := 12
+ -- | | | | | |
u_4_4 : entity common_lib.tb_common_transpose generic map(0, 0, 0, 1, 4, 4);
u_4_8 : entity common_lib.tb_common_transpose generic map(0, 0, 0, 1, 4, 8);
diff --git a/libraries/base/common/tb/vhdl/tb_tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
index af84a20edf..fd5ac65da3 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
@@ -20,7 +20,7 @@
-- Purpose: Multi tb for common_resize.vhd and RESIZE_NUM() in common_pkg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_resize is
end tb_tb_resize;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_round.vhd b/libraries/base/common/tb/vhdl/tb_tb_round.vhd
index d6d452e9d1..a437ca42b2 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_round.vhd
@@ -20,7 +20,7 @@
-- Purpose: Multi tb for common_round.vhd and s_round(), u_round() in common_pkg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_round is
end tb_tb_round;
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
index f569e4a935..e60dd13816 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
--
-- Function: Signed complex multiply
@@ -96,73 +96,73 @@ begin
-- Propagate in_val with c_pipeline latency
u_out_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_complex_mult : entity tech_mult_lib.tech_complex_mult
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => g_out_p_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- result_re => result_re,
- result_im => result_im
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ result_re => result_re,
+ result_im => result_im
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_re_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => std_logic_vector(result_re),
- out_dat => out_pr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => std_logic_vector(result_re),
+ out_dat => out_pr
+ );
u_output_im_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => std_logic_vector(result_im),
- out_dat => out_pi
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => std_logic_vector(result_im),
+ out_dat => out_pi
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
index ff35daacc5..b1df559030 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
entity common_complex_mult_add is
generic (
@@ -75,68 +75,68 @@ begin
-- u_complex_mult : entity work.common_complex_mult(stratix4) -- requires sum of g_pipeline >= 3
u_complex_mult : entity work.common_complex_mult -- suits sum of g_pipeline >= 0
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => c_prod_w,
- g_conjugate_b => c_conjugate,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- out_pr => out_pr,
- out_pi => out_pi
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => c_prod_w,
+ g_conjugate_b => c_conjugate,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ out_pr => out_pr,
+ out_pi => out_pi
+ );
add_inr <= RESIZE_SVEC(out_pr, g_out_p_w); -- Connect the output of the multiplier to the adders input
add_ini <= RESIZE_SVEC(out_pi, g_out_p_w);
u_adder_real : entity common_lib.common_add_sub
- generic map (
- g_direction => c_direction,
- g_representation => "SIGNED",
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => c_sel_add,
- in_a => in_chr,
- in_b => add_inr,
- result => out_sumr
- );
+ generic map (
+ g_direction => c_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => c_sel_add,
+ in_a => in_chr,
+ in_b => add_inr,
+ result => out_sumr
+ );
u_adder_imag : entity common_lib.common_add_sub
- generic map (
- g_direction => c_direction,
- g_representation => "SIGNED",
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => c_sel_add,
- in_a => in_chi,
- in_b => add_ini,
- result => out_sumi
- );
+ generic map (
+ g_direction => c_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => c_sel_add,
+ in_a => in_chi,
+ in_b => add_ini,
+ result => out_sumi
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult.vhd b/libraries/base/common_mult/src/vhdl/common_mult.vhd
index b4050a065d..fb0afbf679 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library ieee, common_lib, tech_mult_lib, technology_lib;
-use ieee.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
-- Function: Default one or more independent products dependent on g_nof_mult
--
@@ -76,57 +76,57 @@ architecture str of common_mult is
begin
u_mult : entity tech_mult_lib.tech_mult
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => g_out_p_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => g_representation
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- out_p => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => result
+ );
-- Propagate in_val with c_pipeline latency
u_out_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => in_val,
+ out_dat => out_val
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_output,
- g_in_dat_w => result'LENGTH,
- g_out_dat_w => result'length
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => std_logic_vector(result),
- out_dat => out_p
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => result'LENGTH,
+ g_out_dat_w => result'length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => std_logic_vector(result),
+ out_dat => out_p
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
index a46453b384..58ce1da641 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
@@ -34,9 +34,9 @@
--
library ieee, common_lib;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use common_lib.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use common_lib.common_pkg.all;
entity common_mult_add is
generic (
@@ -56,9 +56,9 @@ entity common_mult_add is
out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
);
begin
- -- ASSERT g_pipeline=3
- -- REPORT "pipeline value not supported"
- -- SEVERITY FAILURE;
+-- ASSERT g_pipeline=3
+-- REPORT "pipeline value not supported"
+-- SEVERITY FAILURE;
end common_mult_add;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
index 821a0f00a7..aca818ca6f 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib, tech_mult_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
-- Function: vector low part product + or - vector high part product
-- Call:
@@ -73,45 +73,45 @@ architecture str of common_mult_add2 is
begin
u_mult_add2 : entity tech_mult_lib.tech_mult_add2
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_res_w => g_res_w,
- g_force_dsp => g_force_dsp,
- g_add_sub => g_add_sub,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- res => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => result
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => res'LENGTH,
- g_out_dat_w => res'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result,
- out_dat => res
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => res'LENGTH,
+ g_out_dat_w => res'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result,
+ out_dat => res
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
index 56a3b6da68..edb48dc06a 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib, tech_mult_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
-- Function: vector low part product + or - vector high part product
-- Call:
@@ -78,47 +78,47 @@ architecture str of common_mult_add4 is
begin
u_mult_add4 : entity tech_mult_lib.tech_mult_add4
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_res_w => g_res_w,
- g_force_dsp => g_force_dsp,
- g_add_sub0 => g_add_sub0,
- g_add_sub1 => g_add_sub1,
- g_add_sub => g_add_sub,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- res => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub0 => g_add_sub0,
+ g_add_sub1 => g_add_sub1,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => result
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => res'LENGTH,
- g_out_dat_w => res'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result,
- out_dat => res
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => res'LENGTH,
+ g_out_dat_w => res'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result,
+ out_dat => res
+ );
end str;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
index 45a7f60398..4d41e720c0 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
@@ -27,13 +27,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_complex_mult is
@@ -222,76 +222,76 @@ begin
ref_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", c_out_dat_w);
u_result_re : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => c_out_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => ref_result_re,
- out_dat => result_re_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => c_out_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => ref_result_re,
+ out_dat => result_re_expected
+ );
u_result_im : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => c_out_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => ref_result_im,
- out_dat => result_im_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => c_out_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => ref_result_im,
+ out_dat => result_im_expected
+ );
u_result_val_expected : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline,
- g_reset_value => 0
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_val,
- out_dat => result_val_expected
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_reset_value => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_val,
+ out_dat => result_val_expected
+ );
u_dut : entity work.common_complex_mult
- generic map (
- g_technology => c_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => c_out_dat_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- in_val => in_val,
- out_pr => result_re_dut,
- out_pi => result_im_dut,
- out_val => result_val_dut
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => c_out_dat_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ in_val => in_val,
+ out_pr => result_re_dut,
+ out_pi => result_im_dut,
+ out_val => result_val_dut
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
index a2d5185bb1..85f653d6a6 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
@@ -27,11 +27,11 @@
-- > run -all
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_mult is
@@ -57,7 +57,7 @@ architecture tb of tb_common_mult is
constant c_technology : natural := c_tech_select_default;
- function func_sresult(in_a, in_b : std_logic_vector) return std_logic_vector is
+ function func_sresult (in_a, in_b : std_logic_vector) return std_logic_vector is
constant c_res_w : natural := 2 * g_in_dat_w; -- use sufficiently large result width
variable v_a : std_logic_vector(g_in_dat_w - 1 downto 0);
variable v_b : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -70,7 +70,7 @@ architecture tb of tb_common_mult is
return RESIZE_SVEC(std_logic_vector(v_result), g_out_dat_w); -- Truncate MSbits or sign extend MSBits
end;
- function func_uresult(in_a, in_b : std_logic_vector) return std_logic_vector is
+ function func_uresult (in_a, in_b : std_logic_vector) return std_logic_vector is
constant c_res_w : natural := 2 * g_in_dat_w; -- use sufficiently large result width
variable v_a : std_logic_vector(g_in_dat_w - 1 downto 0);
variable v_b : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -165,36 +165,36 @@ begin
-- pipeline inputs to ease comparison in the Wave window
u_in_a_pipeline : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_a,
- out_dat => in_a_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_a,
+ out_dat => in_a_p
+ );
u_in_b_pipeline : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_b,
- out_dat => in_b_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_b,
+ out_dat => in_b_p
+ );
gen_wires : for I in 0 to g_nof_mult - 1 generate
-- use same input for all multipliers
@@ -215,124 +215,124 @@ begin
uresult_ip <= uresult_arr_ip(g_out_dat_w - 1 downto 0);
u_sresult : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_sresult,
- out_dat => sresult_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_sresult,
+ out_dat => sresult_expected
+ );
u_uresult : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_uresult,
- out_dat => uresult_expected
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_uresult,
+ out_dat => uresult_expected
+ );
u_sdut_rtl : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "SIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => sresult_arr_rtl
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "SIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => sresult_arr_rtl
+ );
u_udut_rtl : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => uresult_arr_rtl
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => uresult_arr_rtl
+ );
u_sdut_ip : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "IP",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "SIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => sresult_arr_ip
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "IP",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "SIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => sresult_arr_ip
+ );
u_udut_ip : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "IP",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => uresult_arr_ip
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "IP",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => uresult_arr_ip
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
index 22c75a7df4..4395a1ce43 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
@@ -27,10 +27,10 @@
-- > run -all
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_common_mult_add2 is
@@ -59,7 +59,7 @@ architecture tb of tb_common_mult_add2 is
constant c_min : integer := -c_max_p;
constant c_max_n : integer := -2**(g_in_dat_w - 1);
- function func_result(in_a0, in_b0, in_a1, in_b1 : std_logic_vector) return std_logic_vector is
+ function func_result (in_a0, in_b0, in_a1, in_b1 : std_logic_vector) return std_logic_vector is
-- From mti_numeric_std.vhd follows:
-- . SIGNED * --> output width = 2 * input width
-- . SIGNED + --> output width = largest(input width)
@@ -80,7 +80,7 @@ architecture tb of tb_common_mult_add2 is
if g_add_sub = "SUB" then v_result := RESIZE_NUM(v_a0 * v_b0, c_res_w) - v_a1 * v_b1; end if;
-- Wrap to avoid warning: NUMERIC_STD.TO_SIGNED: vector truncated
if v_result > 2**(g_out_dat_w - 1) - 1 then v_result := v_result - 2**g_out_dat_w; end if;
- if v_result < - 2**(g_out_dat_w - 1) then v_result := v_result + 2**g_out_dat_w; end if;
+ if v_result < - 2**(g_out_dat_w - 1) then v_result := v_result + 2**g_out_dat_w; end if;
return std_logic_vector(v_result);
end;
@@ -180,43 +180,43 @@ begin
out_result <= func_result(in_a0, in_b0, in_a1, in_b1);
u_result : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_result,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_result,
+ out_dat => result_expected
+ );
u_dut_rtl : entity work.common_mult_add2
- generic map (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_res_w => g_out_dat_w, -- g_in_a_w + g_in_b_w + log2(2)
- g_force_dsp => g_force_dsp, -- not applicable for 'rtl'
- g_add_sub => g_add_sub,
- g_nof_mult => 2,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a,
- in_b => in_b,
- res => result_rtl
- );
+ generic map (
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_res_w => g_out_dat_w, -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp => g_force_dsp, -- not applicable for 'rtl'
+ g_add_sub => g_add_sub,
+ g_nof_mult => 2,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a,
+ in_b => in_b,
+ res => result_rtl
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
index 65c3e0f31a..99a3fe0b42 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
@@ -26,9 +26,9 @@
-- --------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_tb_common_complex_mult is
end tb_tb_common_complex_mult;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
index 96dfc359e2..8fdf00b29b 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
@@ -24,7 +24,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_mult is
end tb_tb_common_mult;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen.vhd b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
index 75fa9d3177..5545ea8044 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
@@ -73,11 +73,11 @@
-- . out_sosi.re(g_buf_dat_w/2-1: 0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity diag_block_gen is
generic (
@@ -128,179 +128,179 @@ architecture rtl of diag_block_gen is
begin
- -- xon is not clk cycle timing critical, so can use register xon to ease timing closure
- xon_reg <= out_siso.xon when rising_edge(clk);
-
- p_comb : process(r, rst, ctrl, en_sync, out_siso, xon_reg)
- variable v : reg_type;
- variable v_samples_per_packet : natural;
- variable v_gapsize : natural;
- variable v_blocks_per_sync : natural;
- variable v_mem_low_adrs : natural;
- variable v_mem_high_adrs : natural;
- begin
-
- v_samples_per_packet := TO_UINT(r.ctrl_hold.samples_per_packet);
- v_gapsize := TO_UINT(r.ctrl_hold.gapsize);
- v_blocks_per_sync := TO_UINT(r.ctrl_hold.blocks_per_sync);
- v_mem_low_adrs := TO_UINT(r.ctrl_hold.mem_low_adrs);
- v_mem_high_adrs := TO_UINT(r.ctrl_hold.mem_high_adrs);
-
- v := r; -- default hold all r fields
- v.pls_sync := '0';
- v.valid := '0';
- v.sop := '0';
- v.eop := '0';
- v.rd_ena := '0';
-
- -- Control block generator enable
- if ctrl.enable_sync = '0' then
- -- apply ctrl.enable immediately
+ -- xon is not clk cycle timing critical, so can use register xon to ease timing closure
+ xon_reg <= out_siso.xon when rising_edge(clk);
+
+ p_comb : process(r, rst, ctrl, en_sync, out_siso, xon_reg)
+ variable v : reg_type;
+ variable v_samples_per_packet : natural;
+ variable v_gapsize : natural;
+ variable v_blocks_per_sync : natural;
+ variable v_mem_low_adrs : natural;
+ variable v_mem_high_adrs : natural;
+ begin
+
+ v_samples_per_packet := TO_UINT(r.ctrl_hold.samples_per_packet);
+ v_gapsize := TO_UINT(r.ctrl_hold.gapsize);
+ v_blocks_per_sync := TO_UINT(r.ctrl_hold.blocks_per_sync);
+ v_mem_low_adrs := TO_UINT(r.ctrl_hold.mem_low_adrs);
+ v_mem_high_adrs := TO_UINT(r.ctrl_hold.mem_high_adrs);
+
+ v := r; -- default hold all r fields
+ v.pls_sync := '0';
+ v.valid := '0';
+ v.sop := '0';
+ v.eop := '0';
+ v.rd_ena := '0';
+
+ -- Control block generator enable
+ if ctrl.enable_sync = '0' then
+ -- apply ctrl.enable immediately
+ v.blk_en := ctrl.enable;
+ else
+ -- keep blk_en and apply ctrl.enable (on or off) at input sync pulse
+ if en_sync = '1' then
v.blk_en := ctrl.enable;
- else
- -- keep blk_en and apply ctrl.enable (on or off) at input sync pulse
- if en_sync = '1' then
- v.blk_en := ctrl.enable;
- end if;
end if;
+ end if;
- -- The pulse sync is high at the sop of the first block, the block sync is high during the entire block until the eop
- if r.eop = '1' then
- v.blk_sync := '0';
- end if;
+ -- The pulse sync is high at the sop of the first block, the block sync is high during the entire block until the eop
+ if r.eop = '1' then
+ v.blk_sync := '0';
+ end if;
- -- Increment the block sequence number counter after each block
- if r.eop = '1' then
- v.bsn_cnt := incr_uvec(r.bsn_cnt, 1);
- end if;
+ -- Increment the block sequence number counter after each block
+ if r.eop = '1' then
+ v.bsn_cnt := incr_uvec(r.bsn_cnt, 1);
+ end if;
- case r.state is
- when s_idle =>
- v.blk_xon := xon_reg;
- v.blk_sync := '0';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- v.mem_cnt := v_mem_low_adrs;
- if r.blk_en = '1' then -- Wait until enabled
- if xon_reg = '1' then -- Wait until XON is 1
- v.ctrl_hold := ctrl; -- hold new control settings while BG is enabled
- v.bsn_cnt := ctrl.bsn_init;
- v.rd_ena := '1';
- v.state := s_block;
- end if;
- end if;
-
- when s_block =>
- if out_siso.ready = '1' then
-
- v.rd_ena := '1'; -- read next data
- if r.samples_cnt = 0 and r.blocks_cnt = 0 then
- v.pls_sync := '1'; -- Always start with a pulse sync
- v.blk_sync := '1';
- v.sop := '1';
- v.samples_cnt := v.samples_cnt + 1;
- elsif r.samples_cnt = 0 then
- v.sop := '1';
- v.samples_cnt := v.samples_cnt + 1;
- elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync - 1 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.blocks_cnt := r.blocks_cnt + 1;
- elsif r.samples_cnt >= v_samples_per_packet - 1 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.rd_ena := '0';
- v.state := s_gap;
- else
- v.samples_cnt := r.samples_cnt + 1;
- end if;
- v.valid := '1'; -- output pending data
-
- if r.mem_cnt >= v_mem_high_adrs then
- v.mem_cnt := v_mem_low_adrs;
- else
- v.mem_cnt := r.mem_cnt + 1;
- end if;
-
- if v.eop = '1' and r.blk_en = '0' then
- v.state := s_idle; -- accept disable after eop, not during block
- end if;
- end if; -- out_siso.ready='1'
- if r.eop = '1' then
- v.blk_xon := xon_reg; -- accept XOFF after eop, not during block
+ case r.state is
+ when s_idle =>
+ v.blk_xon := xon_reg;
+ v.blk_sync := '0';
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.mem_cnt := v_mem_low_adrs;
+ if r.blk_en = '1' then -- Wait until enabled
+ if xon_reg = '1' then -- Wait until XON is 1
+ v.ctrl_hold := ctrl; -- hold new control settings while BG is enabled
+ v.bsn_cnt := ctrl.bsn_init;
+ v.rd_ena := '1';
+ v.state := s_block;
end if;
+ end if;
- when s_gap =>
- if r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ when s_block =>
+ if out_siso.ready = '1' then
+
+ v.rd_ena := '1'; -- read next data
+ if r.samples_cnt = 0 and r.blocks_cnt = 0 then
+ v.pls_sync := '1'; -- Always start with a pulse sync
+ v.blk_sync := '1';
+ v.sop := '1';
+ v.samples_cnt := v.samples_cnt + 1;
+ elsif r.samples_cnt = 0 then
+ v.sop := '1';
+ v.samples_cnt := v.samples_cnt + 1;
+ elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ v.eop := '1';
v.samples_cnt := 0;
v.blocks_cnt := 0;
- v.rd_ena := '1';
- v.state := s_block;
- elsif r.samples_cnt >= v_gapsize-1 then
+ elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 then
+ v.eop := '1';
v.samples_cnt := 0;
v.blocks_cnt := r.blocks_cnt + 1;
- v.rd_ena := '1';
- v.state := s_block;
+ elsif r.samples_cnt >= v_samples_per_packet - 1 then
+ v.eop := '1';
+ v.samples_cnt := 0;
+ v.rd_ena := '0';
+ v.state := s_gap;
else
v.samples_cnt := r.samples_cnt + 1;
end if;
+ v.valid := '1'; -- output pending data
- if r.blk_en = '0' then
- v.state := s_idle;
+ if r.mem_cnt >= v_mem_high_adrs then
+ v.mem_cnt := v_mem_low_adrs;
+ else
+ v.mem_cnt := r.mem_cnt + 1;
end if;
- v.blk_xon := xon_reg;
-
- when others =>
- v.state := s_idle;
-
- end case;
-
- if rst = '1' then
- v.ctrl_hold := c_diag_block_gen_rst;
- v.blk_en := '0';
- v.blk_xon := '0';
- v.blk_sync := '0';
- v.pls_sync := '0';
- v.valid := '0';
- v.sop := '0';
- v.eop := '0';
- v.rd_ena := '0';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- v.bsn_cnt := (others => '0');
- v.mem_cnt := 0;
- v.state := s_idle;
- end if;
- rin <= v;
+ if v.eop = '1' and r.blk_en = '0' then
+ v.state := s_idle; -- accept disable after eop, not during block
+ end if;
+ end if; -- out_siso.ready='1'
+ if r.eop = '1' then
+ v.blk_xon := xon_reg; -- accept XOFF after eop, not during block
+ end if;
- end process;
+ when s_gap =>
+ if r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.rd_ena := '1';
+ v.state := s_block;
+ elsif r.samples_cnt >= v_gapsize-1 then
+ v.samples_cnt := 0;
+ v.blocks_cnt := r.blocks_cnt + 1;
+ v.rd_ena := '1';
+ v.state := s_block;
+ else
+ v.samples_cnt := r.samples_cnt + 1;
+ end if;
- p_regs : process(rst, clk)
- begin
- if rising_edge(clk) then
- r <= rin;
- end if;
- end process;
-
- -- Connect to the outside world
- out_sosi_i.sop <= r.sop and r.blk_xon;
- out_sosi_i.eop <= r.eop and r.blk_xon;
- out_sosi_i.sync <= r.pls_sync and r.blk_xon when g_blk_sync = false else r.blk_sync and r.blk_xon;
- out_sosi_i.valid <= r.valid and r.blk_xon;
- out_sosi_i.bsn <= r.bsn_cnt;
- out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w / 2 - 1 downto 0)); -- treat as signed
- out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w - 1 downto g_buf_dat_w / 2)); -- treat as signed
- out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w - 1 downto 0)); -- treat as unsigned
-
- out_sosi <= out_sosi_i;
- buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
- buf_rden <= r.rd_ena;
-
- ctrl_hold <= r.ctrl_hold;
+ if r.blk_en = '0' then
+ v.state := s_idle;
+ end if;
+ v.blk_xon := xon_reg;
+
+ when others =>
+ v.state := s_idle;
+
+ end case;
+
+ if rst = '1' then
+ v.ctrl_hold := c_diag_block_gen_rst;
+ v.blk_en := '0';
+ v.blk_xon := '0';
+ v.blk_sync := '0';
+ v.pls_sync := '0';
+ v.valid := '0';
+ v.sop := '0';
+ v.eop := '0';
+ v.rd_ena := '0';
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.bsn_cnt := (others => '0');
+ v.mem_cnt := 0;
+ v.state := s_idle;
+ end if;
+
+ rin <= v;
+
+ end process;
+
+ p_regs : process(rst, clk)
+ begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+ end process;
+
+ -- Connect to the outside world
+ out_sosi_i.sop <= r.sop and r.blk_xon;
+ out_sosi_i.eop <= r.eop and r.blk_xon;
+ out_sosi_i.sync <= r.pls_sync and r.blk_xon when g_blk_sync = false else r.blk_sync and r.blk_xon;
+ out_sosi_i.valid <= r.valid and r.blk_xon;
+ out_sosi_i.bsn <= r.bsn_cnt;
+ out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w / 2 - 1 downto 0)); -- treat as signed
+ out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w - 1 downto g_buf_dat_w / 2)); -- treat as signed
+ out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w - 1 downto 0)); -- treat as unsigned
+
+ out_sosi <= out_sosi_i;
+ buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
+ buf_rden <= r.rd_ena;
+
+ ctrl_hold <= r.ctrl_hold;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
index 99425a108c..68e2ef8e51 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
@@ -21,11 +21,11 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
entity diag_block_gen_reg is
generic (
@@ -143,15 +143,15 @@ begin
-- Assume diag BG enable gets written last, so when diag BG enable is transfered properly to the dp_clk domain, then
-- the other diag BG control fields are stable as well
u_bg_enable : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- din => mm_bg_ctrl.enable,
- dout => dp_bg_ctrl.enable
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ din => mm_bg_ctrl.enable,
+ dout => dp_bg_ctrl.enable
+ );
dp_bg_ctrl.enable_sync <= mm_bg_ctrl.enable_sync;
dp_bg_ctrl.samples_per_packet <= mm_bg_ctrl.samples_per_packet;
dp_bg_ctrl.blocks_per_sync <= mm_bg_ctrl.blocks_per_sync;
diff --git a/libraries/base/diag/src/vhdl/diag_bypass.vhd b/libraries/base/diag/src/vhdl/diag_bypass.vhd
index 481b79c224..315b4f56ea 100644
--- a/libraries/base/diag/src/vhdl/diag_bypass.vhd
+++ b/libraries/base/diag/src/vhdl/diag_bypass.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity diag_bypass is
@@ -116,7 +116,7 @@ begin
if bypass_en_reg = '1' then
mod_clk <= '0';
end if;
- -- synthesis translate_on
+ -- synthesis translate_on
end process;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
index 6e1e27f9e8..a9d151426c 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
@@ -44,12 +44,12 @@
-- a c_word_w parts.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_data_buffer is
generic (
@@ -87,23 +87,29 @@ architecture rtl of diag_data_buffer is
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
constant g_data_mm_w : natural := g_data_w / c_mm_factor;
- constant c_buf_mm : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_data_mm),
- dat_w => g_data_mm_w,
- nof_dat => c_nof_data_mm,
- init_sl => '0');
+ constant c_buf_mm : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_data_mm),
+ dat_w => g_data_mm_w,
+ nof_dat => c_nof_data_mm,
+ init_sl => '0'
+ );
- constant c_buf_st : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_data),
- dat_w => g_data_w,
- nof_dat => g_nof_data,
- init_sl => '0');
+ constant c_buf_st : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_data),
+ dat_w => g_data_w,
+ nof_dat => g_nof_data,
+ init_sl => '0'
+ );
- constant c_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_db_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
- init_sl => '0');
+ constant c_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_db_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
+ init_sl => '0'
+ );
signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
@@ -138,17 +144,17 @@ begin
-- Determine the write trigger
use_rd_last : if g_use_in_sync = false generate
u_wr_sync : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => rd_last,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => wr_sync
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => rd_last,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => wr_sync
+ );
end generate;
use_in_sync : if g_use_in_sync = true generate
@@ -192,75 +198,75 @@ begin
end process;
u_buf : entity common_lib.common_ram_crw_crw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_a => c_buf_mm,
- g_ram_b => c_buf_st,
- g_init_file => "UNUSED"
- )
- port map (
- -- MM read/write port clock domain
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_mm_mosi.wr,
- wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w - 1 downto 0),
- adr_a => ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0),
- rd_en_a => ram_mm_mosi.rd,
- rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w - 1 downto 0),
- rd_val_a => i_ram_mm_miso.rdval,
-
- -- ST write only port clock domain
- rst_b => st_rst,
- clk_b => st_clk,
- wr_en_b => wr_en,
- wr_dat_b => wr_data,
- adr_b => wr_addr,
- rd_en_b => '0',
- rd_dat_b => OPEN,
- rd_val_b => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_a => c_buf_mm,
+ g_ram_b => c_buf_st,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ -- MM read/write port clock domain
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_mm_mosi.wr,
+ wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w - 1 downto 0),
+ adr_a => ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0),
+ rd_en_a => ram_mm_mosi.rd,
+ rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w - 1 downto 0),
+ rd_val_a => i_ram_mm_miso.rdval,
+
+ -- ST write only port clock domain
+ rst_b => st_rst,
+ clk_b => st_clk,
+ wr_en_b => wr_en,
+ wr_dat_b => wr_data,
+ adr_b => wr_addr,
+ rd_en_b => '0',
+ rd_dat_b => OPEN,
+ rd_val_b => open
+ );
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_reg => c_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mm_mosi,
- sla_out => reg_mm_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => reg_rd_arr,
- in_reg => reg_slv,
- out_reg => open
- );
+ generic map (
+ g_reg => c_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mm_mosi,
+ sla_out => reg_mm_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
+ in_reg => reg_slv,
+ out_reg => open
+ );
reg_slv <= word_cnt & sync_cnt;
u_word_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => wr_en,
- cnt_clr => wr_sync,
- count => word_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => wr_en,
+ cnt_clr => wr_sync,
+ count => word_cnt
+ );
u_sync_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => wr_sync,
- cnt_clr => sync_cnt_clr,
- count => sync_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => wr_sync,
+ cnt_clr => sync_cnt_clr,
+ count => sync_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
index ad85335ca7..99bbdf204e 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -65,12 +65,12 @@
-- a c_word_w parts.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_data_buffer_dev is
generic (
@@ -110,23 +110,29 @@ architecture rtl of diag_data_buffer_dev is
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
constant g_data_mm_w : natural := g_data_w / c_mm_factor;
- constant c_buf_mm : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_data_mm),
- dat_w => g_data_mm_w,
- nof_dat => c_nof_data_mm,
- init_sl => '0');
+ constant c_buf_mm : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_data_mm),
+ dat_w => g_data_mm_w,
+ nof_dat => c_nof_data_mm,
+ init_sl => '0'
+ );
- constant c_buf_st : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_data),
- dat_w => g_data_w,
- nof_dat => g_nof_data,
- init_sl => '0');
+ constant c_buf_st : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_data),
+ dat_w => g_data_w,
+ nof_dat => g_nof_data,
+ init_sl => '0'
+ );
- constant c_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_db_dev_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_db_dev_reg_nof_dat, -- 3: reg_sync_delay 2: valid_cnt 1: word_cnt; 0:sync_cnt
- init_sl => '0');
+ constant c_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_db_dev_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_db_dev_reg_nof_dat, -- 3: reg_sync_delay 2: valid_cnt 1: word_cnt; 0:sync_cnt
+ init_sl => '0'
+ );
signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
@@ -176,17 +182,17 @@ begin
rd_last <= '1' when unsigned(ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0)) = c_nof_data_mm - 1 and ram_mm_mosi.rd = '1' else '0';
u_rd_last_clock_cross : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => rd_last,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => rd_last_st
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => rd_last,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => rd_last_st
+ );
-- Determine the write trigger in NON-SYNC MODE
use_rd_last : if g_use_in_sync = false generate
@@ -291,55 +297,55 @@ begin
end process;
u_buf : entity common_lib.common_ram_crw_crw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_a => c_buf_mm,
- g_ram_b => c_buf_st,
- g_init_file => "UNUSED"
- )
- port map (
- -- MM read/write port clock domain
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_mm_mosi.wr,
- wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w - 1 downto 0),
- adr_a => ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0),
- rd_en_a => ram_mm_mosi.rd,
- rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w - 1 downto 0),
- rd_val_a => i_ram_mm_miso.rdval,
-
- -- ST write only port clock domain
- rst_b => st_rst,
- clk_b => st_clk,
- wr_en_b => wr_en,
- wr_dat_b => wr_data,
- adr_b => wr_addr,
- rd_en_b => '0',
- rd_dat_b => OPEN,
- rd_val_b => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_a => c_buf_mm,
+ g_ram_b => c_buf_st,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ -- MM read/write port clock domain
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_mm_mosi.wr,
+ wr_dat_a => ram_mm_mosi.wrdata(c_buf_mm.dat_w - 1 downto 0),
+ adr_a => ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0),
+ rd_en_a => ram_mm_mosi.rd,
+ rd_dat_a => i_ram_mm_miso.rddata(c_buf_mm.dat_w - 1 downto 0),
+ rd_val_a => i_ram_mm_miso.rdval,
+
+ -- ST write only port clock domain
+ rst_b => st_rst,
+ clk_b => st_clk,
+ wr_en_b => wr_en,
+ wr_dat_b => wr_data,
+ adr_b => wr_addr,
+ rd_en_b => '0',
+ rd_dat_b => OPEN,
+ rd_val_b => open
+ );
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_reg => c_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mm_mosi,
- sla_out => reg_mm_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => reg_rd_arr,
- in_reg => reg_slv_rd,
- out_reg => reg_slv_wr
- );
+ generic map (
+ g_reg => c_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mm_mosi,
+ sla_out => reg_mm_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => reg_rd_arr,
+ in_reg => reg_slv_rd,
+ out_reg => reg_slv_wr
+ );
arm_enable <= reg_wr_arr(2);
reg_sync_delay <= reg_slv_wr(4 * c_word_w - 1 downto 3 * c_word_w);
@@ -347,31 +353,31 @@ begin
reg_sync_delay & valid_cnt & word_cnt & sync_cnt;
u_word_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => wr_en,
- cnt_clr => wr_sync,
- count => word_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => wr_en,
+ cnt_clr => wr_sync,
+ count => word_cnt
+ );
u_sync_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => wr_sync,
- cnt_clr => sync_cnt_clr,
- count => sync_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => wr_sync,
+ cnt_clr => sync_cnt_clr,
+ count => sync_cnt
+ );
u_valid_cnt : entity common_lib.common_counter
- port map (
- rst => st_rst,
- clk => st_clk,
- cnt_en => in_val,
- cnt_clr => in_sync,
- count => valid_cnt
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ cnt_en => in_val,
+ cnt_clr => in_sync,
+ count => valid_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
index 85e13db8ba..2a337a4e06 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Generate a stream of frames with test sequence data.
@@ -43,7 +43,7 @@ entity diag_frm_generator is
g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
g_frame_len : natural := 2; -- >= 2, test frame length in nof dat words
g_sof_period : natural := 1; -- >= 1, nof cycles between sop that start a frame, typically >> g_frame_len
- -- to generate frames with idle in between
+ -- to generate frames with idle in between
g_frame_cnt_w : natural := 32;
g_dat_w : natural := 16; -- >= 1, test data width
g_symbol_w : natural := 16; -- >= 1, and nof_symbols_per_dat = g_dat_w/g_symbol_w, must be an integer
@@ -99,17 +99,17 @@ begin
-- Signal begin of diag_en
u_diag_en_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => diag_en,
- out_evt => diag_en_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => diag_en,
+ out_evt => diag_en_revt
+ );
p_clk : process (rst, clk)
begin
@@ -127,63 +127,63 @@ begin
nxt_diag_init <= TO_UVEC(c_init, g_dat_w) when diag_en = '0' else INCR_UVEC(diag_init, 1) when i_out_sop = '1';
u_pulse_sop : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_sof_period
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- pulse_period => diag_sof_period,
- pulse_en => diag_en,
- pulse_clr => diag_en_revt,
- pulse_out => diag_sop
- );
+ generic map (
+ g_pulse_period => g_sof_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ pulse_period => diag_sof_period,
+ pulse_en => diag_en,
+ pulse_clr => diag_en_revt,
+ pulse_out => diag_sop
+ );
-- Hold last frame count also when the generator is disabled, clear when it is restarted
nxt_diag_frame_cnt <= (others => '0') when diag_en_revt = '1' else frame_cnt;
u_frm_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => i_out_eop,
- count => frame_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => i_out_eop,
+ count => frame_cnt
+ );
u_tx_frm : entity work.diag_tx_frm
- generic map (
- g_sel => g_sel,
- g_init => c_init,
- g_frame_len => g_frame_len,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
-
- -- Static control input (connect via MM or leave open to use default)
- diag_sel => diag_sel,
- diag_dc => diag_dc,
- diag_frame_len => diag_frame_len,
-
- -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
- diag_ready => diag_ready,
- diag_init => diag_init,
- diag_sop => diag_sop,
-
- -- ST output
- out_ready => out_ready,
- out_dat => out_dat,
- out_val => out_val,
- out_sop => i_out_sop,
- out_eop => i_out_eop
- );
+ generic map (
+ g_sel => g_sel,
+ g_init => c_init,
+ g_frame_len => g_frame_len,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_sel => diag_sel,
+ diag_dc => diag_dc,
+ diag_frame_len => diag_frame_len,
+
+ -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
+ diag_ready => diag_ready,
+ diag_init => diag_init,
+ diag_sop => diag_sop,
+
+ -- ST output
+ out_ready => out_ready,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sop => i_out_sop,
+ out_eop => i_out_eop
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
index 9a01db05af..a253db5404 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Monitor a stream of frames with test sequence data.
@@ -93,17 +93,17 @@ begin
-- Signal begin of diag_en
u_diag_en_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => diag_en,
- out_evt => diag_en_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => diag_en,
+ out_evt => diag_en_revt
+ );
-- Hold last frame and error counts also when the monitor is disabled, clear when it is restarted
nxt_diag_frame_cnt <= (others => '0') when diag_en_revt = '1' else frame_cnt;
@@ -111,32 +111,32 @@ begin
-- Count all received frames
u_frm_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => in_eop,
- count => frame_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => in_eop,
+ count => frame_cnt
+ );
-- Count the received frames that had an error
frm_error <= in_eop and in_error;
u_err_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => frm_error,
- count => error_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => frm_error,
+ count => error_cnt
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd
index 9c72a414e2..a3c615fbbb 100644
--- a/libraries/base/diag/src/vhdl/diag_pkg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
package diag_pkg is
@@ -61,7 +61,7 @@ package diag_pkg is
constant c_diag_wg_phase_w : natural := 16; -- = c_diag_wg_nofsamples_w
constant c_diag_wg_freq_w : natural := 31; -- >> c_diag_wg_nofsamples_w, determines the minimum frequency = Fs / 2**c_diag_wg_freq_w
constant c_diag_wg_ampl_w : natural := 17; -- Typically fit DSP multiply 18x18 element so use <= 17, to fit unsigned in 18 bit signed,
- -- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
+ -- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
constant c_diag_wg_mode_off : natural := 0;
constant c_diag_wg_mode_calc : natural := 1;
@@ -77,23 +77,35 @@ package diag_pkg is
end record;
constant c_diag_wg_ampl_norm : real := 1.0; -- Use this default amplitude norm = 1.0 when WG data width = WG waveform buffer data width,
- -- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
+ -- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
constant c_diag_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
- -- For c_diag_wg_gain_w = 1 there is clipping from [1 2> For normalized values >= 2**c_diag_wg_gain_w = 2
- -- the behaviour becomes more or less undefined. Due to wrapping it appears that normalized values [2 3>
- -- result in a sinus again. Therefore use normalized range [0 2**c_diag_wg_gain_w>.
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- For c_diag_wg_gain_w = 1 there is clipping from [1 2> For normalized values >= 2**c_diag_wg_gain_w = 2
+ -- the behaviour becomes more or less undefined. Due to wrapping it appears that normalized values [2 3>
+ -- result in a sinus again. Therefore use normalized range [0 2**c_diag_wg_gain_w>.
constant c_diag_wg_ampl_unit : real := 2**REAL(c_diag_wg_ampl_w - c_diag_wg_gain_w) * c_diag_wg_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
constant c_diag_wg_freq_unit : real := 2**REAL(c_diag_wg_freq_w); -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
constant c_diag_wg_phase_unit : real := 2**REAL(c_diag_wg_phase_w) / 360.0; -- ^= 1 degree
constant c_diag_wg_latency : natural := 10; -- WG starts 10 cycles after trigger
- constant c_diag_wg_rst : t_diag_wg := (TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
- TO_UVEC( 1024, c_diag_wg_nofsamples_w),
- TO_UVEC( 0, c_diag_wg_phase_w),
- TO_UVEC( 0, c_diag_wg_freq_w),
- TO_UVEC( 0, c_diag_wg_ampl_w));
+ constant c_diag_wg_rst : t_diag_wg := (
+ TO_UVEC(
+ c_diag_wg_mode_off,
+ c_diag_wg_mode_w),
+ TO_UVEC(
+ 1024,
+ c_diag_wg_nofsamples_w),
+ TO_UVEC(
+ 0,
+ c_diag_wg_phase_w),
+ TO_UVEC(
+ 0,
+ c_diag_wg_freq_w),
+ TO_UVEC(
+ 0,
+ c_diag_wg_ampl_w)
+ );
type t_diag_wg_arr is array (integer range <>) of t_diag_wg;
@@ -141,32 +153,60 @@ package diag_pkg is
bsn_init : natural;
end record;
- constant c_diag_block_gen_rst : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC( 256, c_diag_bg_samples_per_packet_w),
- TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 128, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( 1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
- constant c_diag_block_gen_enabled : t_diag_block_gen := ( '1',
- '0',
- TO_UVEC( 50, c_diag_bg_samples_per_packet_w),
- TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 7, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( 15, c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_diag_block_gen_rst : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC(
+ 256,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ 10,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ 128,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ 1,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
+
+ constant c_diag_block_gen_enabled : t_diag_block_gen := (
+ '1',
+ '0',
+ TO_UVEC(
+ 50,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ 10,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ 7,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ 15,
+ c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
type t_diag_block_gen_arr is array (integer range <>) of t_diag_block_gen;
type t_diag_block_gen_integer_arr is array (integer range <>) of t_diag_block_gen_integer;
-- Overloaded sel_a_b (from common_pkg) for t_diag_block_gen
- function sel_a_b(sel : boolean; a, b : t_diag_block_gen) return t_diag_block_gen;
+ function sel_a_b (sel : boolean; a, b : t_diag_block_gen) return t_diag_block_gen;
- function func_diag_bg_ctrl_integer_to_slv(bg_ctrl_int : t_diag_block_gen_integer) return t_diag_block_gen;
- function func_diag_bg_ctrl_slv_to_integer(bg_ctrl_slv : t_diag_block_gen) return t_diag_block_gen_integer;
+ function func_diag_bg_ctrl_integer_to_slv (bg_ctrl_int : t_diag_block_gen_integer) return t_diag_block_gen;
+ function func_diag_bg_ctrl_slv_to_integer (bg_ctrl_slv : t_diag_block_gen) return t_diag_block_gen_integer;
-----------------------------------------------------------------------------
-- Data buffer
@@ -225,7 +265,7 @@ end diag_pkg;
package body diag_pkg is
- function sel_a_b(sel : boolean; a, b : t_diag_block_gen) return t_diag_block_gen is
+ function sel_a_b (sel : boolean; a, b : t_diag_block_gen) return t_diag_block_gen is
begin
if sel = true then
return a;
@@ -234,7 +274,7 @@ package body diag_pkg is
end if;
end;
- function func_diag_bg_ctrl_integer_to_slv(bg_ctrl_int : t_diag_block_gen_integer) return t_diag_block_gen is
+ function func_diag_bg_ctrl_integer_to_slv (bg_ctrl_int : t_diag_block_gen_integer) return t_diag_block_gen is
begin
return ( bg_ctrl_int.enable,
bg_ctrl_int.enable_sync,
@@ -246,7 +286,7 @@ package body diag_pkg is
TO_UVEC(bg_ctrl_int.bsn_init , c_diag_bg_bsn_init_w));
end;
- function func_diag_bg_ctrl_slv_to_integer(bg_ctrl_slv : t_diag_block_gen) return t_diag_block_gen_integer is
+ function func_diag_bg_ctrl_slv_to_integer (bg_ctrl_slv : t_diag_block_gen) return t_diag_block_gen_integer is
begin
return ( bg_ctrl_slv.enable,
bg_ctrl_slv.enable_sync,
diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index 617a63b397..60aa71a674 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -90,11 +90,11 @@
-- in case they occur.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.diag_pkg.all;
entity diag_rx_seq is
generic (
@@ -215,19 +215,19 @@ begin
-- Use initialisation to set initial diag_res to invalid
diag_res <= diag_res_int; -- use initialisation of internal signal diag_res_int rather than initialisation of entity output diag_res
--- -- Use rst to set initial diag_res to invalid
--- p_rst_clk : PROCESS (rst, clk)
--- BEGIN
--- IF rst='1' THEN
--- diag_res <= c_diag_res_invalid;
--- ELSIF rising_edge(clk) THEN
--- IF clken='1' THEN
--- -- Internal.
--- diag_res <= nxt_diag_res;
--- -- Outputs.
--- END IF;
--- END IF;
--- END PROCESS;
+ -- -- Use rst to set initial diag_res to invalid
+ -- p_rst_clk : PROCESS (rst, clk)
+ -- BEGIN
+ -- IF rst='1' THEN
+ -- diag_res <= c_diag_res_invalid;
+ -- ELSIF rising_edge(clk) THEN
+ -- IF clken='1' THEN
+ -- -- Internal.
+ -- diag_res <= nxt_diag_res;
+ -- -- Outputs.
+ -- END IF;
+ -- END IF;
+ -- END PROCESS;
p_clk : process (clk)
begin
@@ -272,24 +272,24 @@ begin
------------------------------------------------------------------------------
u_in_val_1 : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => in_val_reg,
- switch_low => diag_dis,
- out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => in_val_reg,
+ switch_low => diag_dis,
+ out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
+ );
in_val_act <= in_val_1 and in_val_reg; -- Signal the second valid in_dat after diag_en='1'
u_in_val_2 : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => in_val_act,
- switch_low => diag_dis,
- out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => in_val_act,
+ switch_low => diag_dis,
+ out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
+ );
-- Use in_val_2_act instead of in_val_2 to have stable start in case diag_dis takes just a pulse and in_val is continue high
in_val_2_act <= vector_and(in_val_2 & in_val_2_dly);
@@ -338,13 +338,13 @@ begin
-- Hold any difference on the in_dat bus lines
u_dat : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => diff_dat(I),
- switch_low => diff_dis,
- out_level => diff_res(I)
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => diff_dat(I),
+ switch_low => diff_dis,
+ out_level => diff_res(I)
+ );
end generate;
end generate;
@@ -388,13 +388,13 @@ begin
-- hold detected diff detect
u_dat : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => diff_detect,
- switch_low => diff_dis,
- out_level => diff_hold
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => diff_detect,
+ switch_low => diff_dis,
+ out_level => diff_hold
+ );
diff_res <= (others => diff_hold); -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
end generate;
@@ -422,16 +422,16 @@ begin
-- Count number of valid input data
------------------------------------------------------------------------------
u_common_counter : entity common_lib.common_counter
- generic map (
- g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
- g_width => g_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
- cnt_en => in_val,
- count => in_cnt
- );
+ generic map (
+ g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => g_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_en => in_val,
+ count => in_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
index 99abf4c043..1ae3f7d00a 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
-- Purpose: Transmit a frame with PRSG or COUNTER test sequence data.
-- Description:
@@ -142,33 +142,33 @@ begin
nxt_out_eop <= cnt_done;
u_cnt_len : entity common_lib.common_counter
- generic map (
- g_width => diag_frame_len'length
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => diag_frame_len'length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
u_frame_dat : entity work.diag_tx_seq
- generic map (
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_dc => diag_dc,
- diag_init => diag_init,
- diag_req => out_ready,
- out_dat => out_dat,
- out_val => open
- );
+ generic map (
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_dc => diag_dc,
+ diag_init => diag_init,
+ diag_req => out_ready,
+ out_dat => out_dat,
+ out_val => open
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
index bb4be8bda0..cf3d463301 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
-- Purpose: Transmit continuous PRSG or COUNTER test sequence data.
-- Description:
@@ -137,17 +137,17 @@ begin
-- Count number of valid output data
u_common_counter : entity common_lib.common_counter
- generic map (
- g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
- g_width => g_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
- cnt_en => nxt_out_val,
- count => out_cnt
- );
+ generic map (
+ g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => g_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_en => nxt_out_val,
+ count => out_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_wg.vhd b/libraries/base/diag/src/vhdl/diag_wg.vhd
index 557165d10f..323f86e473 100644
--- a/libraries/base/diag/src/vhdl/diag_wg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg.vhd
@@ -46,25 +46,25 @@
-- CW with fractional frequency is SNR ~= 56 dB, even if g_calc_dat_w > 9.
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_wg is
generic (
g_technology : natural := c_tech_select_default;
g_buf_dat_w : natural := 18; -- Use >= g_calc_dat_w and typically <= DSP multiply 18x18 element
g_buf_addr_w : natural := 11; -- Waveform buffer size 2**g_buf_addr_w nof samples
- -- . in calc mode fill the entire buffer with one sinus wave, ctrl.phase and ctrl.freq will map on the entire range
- -- . in single or repeat mode fill the buffer with an arbitrary signal and define actual the period via ctrl.nof_samples
+ -- . in calc mode fill the entire buffer with one sinus wave, ctrl.phase and ctrl.freq will map on the entire range
+ -- . in single or repeat mode fill the buffer with an arbitrary signal and define actual the period via ctrl.nof_samples
g_rate_factor : natural := 1; -- Default 1 for unit frequency Fs, else g_rate_factor * Fs using g_rate_factor nof parallel outputs
g_rate_offset : natural := 0; -- Selects which of the parallel outputs [0:g_rate_factor-1] this WG should generate
g_calc_support : boolean := true; -- When FALSE then calc mode falls back to repeat mode to save logic.
g_calc_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have full scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- . use gain 2**0 = 1 to have full scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
g_calc_dat_w : natural := 12 -- Effective range of the WG out_dat
);
port (
@@ -231,7 +231,7 @@ begin
when c_diag_wg_mode_single => if init_repeat_done = '1' then nxt_state <= s_single; nxt_init_sync <= '1'; end if;
when c_diag_wg_mode_repeat => if init_repeat_done = '1' then nxt_state <= s_repeat; nxt_init_sync <= '1'; end if;
when c_diag_wg_mode_calc => if g_calc_support = false and init_repeat_done = '1' then nxt_state <= s_repeat; nxt_init_sync <= '1'; end if;
- if g_calc_support = true and init_calc_done = '1' then nxt_state <= s_calc; nxt_init_sync <= '1'; end if;
+ if g_calc_support = true and init_calc_done = '1' then nxt_state <= s_calc; nxt_init_sync <= '1'; end if;
when others => nxt_state <= s_off;
end case;
when s_single =>
@@ -350,98 +350,98 @@ begin
end process;
mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => g_buf_dat_w,
- g_in_b_w => c_ampl_w,
- g_out_p_w => c_mult_w,
- g_pipeline_input => c_mult_pipeline_input,
- g_pipeline_product => c_mult_pipeline_product,
- g_pipeline_output => c_mult_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- in_a => buf_rddat,
- in_b => ctrl_ampl,
- out_p => mult_dat
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_buf_dat_w,
+ g_in_b_w => c_ampl_w,
+ g_out_p_w => c_mult_w,
+ g_pipeline_input => c_mult_pipeline_input,
+ g_pipeline_product => c_mult_pipeline_product,
+ g_pipeline_output => c_mult_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_a => buf_rddat,
+ in_b => ctrl_ampl,
+ out_p => mult_dat
+ );
-- Skip the double-sign bit
prod_dat <= mult_dat(c_prod_w - 1 downto 0);
u_round : entity common_lib.common_round
- generic map(
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => 0,
- g_pipeline_output => c_round_pipeline,
- g_in_dat_w => c_prod_w,
- g_out_dat_w => c_round_w
- )
- port map (
- clk => clk,
- in_dat => prod_dat,
- out_dat => round_dat
- );
+ generic map(
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => 0,
+ g_pipeline_output => c_round_pipeline,
+ g_in_dat_w => c_prod_w,
+ g_out_dat_w => c_round_w
+ )
+ port map (
+ clk => clk,
+ in_dat => prod_dat,
+ out_dat => round_dat
+ );
u_clip : entity common_lib.common_clip
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_clip_pipeline,
- g_full_scale => to_unsigned(c_calc_full_scale, g_calc_dat_w)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => round_dat,
- out_dat => clip_dat,
- out_ovr => clip_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_clip_pipeline,
+ g_full_scale => to_unsigned(c_calc_full_scale, g_calc_dat_w)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => round_dat,
+ out_dat => clip_dat,
+ out_ovr => clip_ovr
+ );
u_rdval_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_calc_pipeline,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(buf_rdval),
- sl(out_dat) => buf_rdval_dly
- );
+ generic map (
+ g_pipeline => c_calc_pipeline,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(buf_rdval),
+ sl(out_dat) => buf_rdval_dly
+ );
u_sync_default_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_sync_dly,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(init_sync),
- sl(out_dat) => sync_dly_default
- );
+ generic map (
+ g_pipeline => c_sync_dly,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(init_sync),
+ sl(out_dat) => sync_dly_default
+ );
u_sync_calc_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_calc_pipeline,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(sync_dly_default),
- sl(out_dat) => sync_dly_calc
- );
+ generic map (
+ g_pipeline => c_calc_pipeline,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(sync_dly_default),
+ sl(out_dat) => sync_dly_calc
+ );
output_proc : process(state, buf_rdval_dly, clip_dat, clip_ovr, buf_rdval, buf_rddat, sync_dly_default, sync_dly_calc)
begin
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index 76c0f064a8..60af5e0039 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -25,12 +25,12 @@
-- . For g_wideband_factor=1 this diag_wg_wideband defaults to diag_wg.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_wg_wideband is
generic (
@@ -78,14 +78,16 @@ end diag_wg_wideband;
architecture str of diag_wg_wideband is
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_addr_w,
- dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
- nof_dat => 2**g_buf_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_addr_w,
+ dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
+ nof_dat => 2**g_buf_addr_w, -- = 2**adr_w
+ init_sl => '0'
+ );
constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_2048x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_1024x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, g_buf_dir & "diag_sin_1024x8.hex", "UNUSED")));
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_1024x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, g_buf_dir & "diag_sin_1024x8.hex", "UNUSED")));
type t_buf_dat_arr is array (natural range <>) of std_logic_vector(g_buf_dat_w - 1 downto 0);
type t_buf_adr_arr is array (natural range <>) of std_logic_vector(g_buf_addr_w - 1 downto 0);
@@ -115,60 +117,60 @@ begin
gen_wg : for I in 0 to g_wideband_factor - 1 generate
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_dat_a => mm_wrdata,
- adr_a => mm_address,
- wr_en_a => mm_wr,
- rd_en_a => mm_rd,
- rd_val_a => buf_rdval(I),
- rd_dat_a => buf_rddata(I),
- rst_b => st_rst,
- clk_b => st_clk,
- wr_dat_b => (others => '0'),
- adr_b => st_address(I),
- wr_en_b => '0',
- rd_en_b => st_rd(I),
- rd_val_b => st_rdval(I),
- rd_dat_b => st_rddata(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_dat_a => mm_wrdata,
+ adr_a => mm_address,
+ wr_en_a => mm_wr,
+ rd_en_a => mm_rd,
+ rd_val_a => buf_rdval(I),
+ rd_dat_a => buf_rddata(I),
+ rst_b => st_rst,
+ clk_b => st_clk,
+ wr_dat_b => (others => '0'),
+ adr_b => st_address(I),
+ wr_en_b => '0',
+ rd_en_b => st_rd(I),
+ rd_val_b => st_rdval(I),
+ rd_dat_b => st_rddata(I)
+ );
-- Waveform generator
u_wg : entity work.diag_wg
- generic map (
- g_technology => g_technology,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_rate_factor => g_wideband_factor,
- g_rate_offset => I,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- restart => st_restart,
-
- buf_rddat => st_rddata(I),
- buf_rdval => st_rdval(I),
- buf_addr => st_address(I),
- buf_rden => st_rd(I),
-
- ctrl => st_ctrl,
- mon_ctrl => st_mon_ctrl_arr(I),
-
- out_ovr => out_ovr( g_wideband_factor - I - 1),
- out_dat => out_dat((g_wideband_factor - I) * g_buf_dat_w - 1 downto (g_wideband_factor - I - 1) * g_buf_dat_w),
- out_val => out_val( g_wideband_factor - I - 1),
- out_sync => out_sync( g_wideband_factor - I - 1)
- );
+ generic map (
+ g_technology => g_technology,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_rate_factor => g_wideband_factor,
+ g_rate_offset => I,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ restart => st_restart,
+
+ buf_rddat => st_rddata(I),
+ buf_rdval => st_rdval(I),
+ buf_addr => st_address(I),
+ buf_rden => st_rd(I),
+
+ ctrl => st_ctrl,
+ mon_ctrl => st_mon_ctrl_arr(I),
+
+ out_ovr => out_ovr( g_wideband_factor - I - 1),
+ out_dat => out_dat((g_wideband_factor - I) * g_buf_dat_w - 1 downto (g_wideband_factor - I - 1) * g_buf_dat_w),
+ out_val => out_val( g_wideband_factor - I - 1),
+ out_sync => out_sync( g_wideband_factor - I - 1)
+ );
end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
index 33c2b9598d..92e76b42fa 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
@@ -41,10 +41,10 @@
-- diag_wg_reg.vhd.
library IEEE, common_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
entity diag_wg_wideband_reg is
generic (
@@ -71,11 +71,13 @@ end diag_wg_wideband_reg;
architecture rtl of diag_wg_wideband_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**2,
+ init_sl => '0'
+ );
-- Registers in mm_clk domain
signal mm_wg_ctrl : t_diag_wg;
@@ -83,7 +85,7 @@ architecture rtl of diag_wg_wideband_reg is
signal mm_mon_ctrl : t_diag_wg;
- -- Registers in st_clk domain
+-- Registers in st_clk domain
begin
@@ -185,17 +187,17 @@ begin
-- Assume diag WG mode gets written last, so when diag WG mode is transfered properly to the st_clk domain, then
-- the other diag WG control fields are stable as well
u_mode : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_wg_ctrl_mode_wr, -- when '1' then new in_dat is available after g_in_new_latency
- in_dat => mm_wg_ctrl.mode,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_wg_ctrl.mode,
- out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_wg_ctrl_mode_wr, -- when '1' then new in_dat is available after g_in_new_latency
+ in_dat => mm_wg_ctrl.mode,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_wg_ctrl.mode,
+ out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
+ );
end generate;
-- The other wg_ctrl only take effect in diag_wg after the mode has been set
@@ -207,54 +209,54 @@ begin
-- Read: ST to MM clock domain
gen_cross_rd : if g_cross_clock_domain = true generate
u_mode : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.mode,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.mode
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.mode,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.mode
+ );
u_nof_samples : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.nof_samples,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.nof_samples
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.nof_samples,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.nof_samples
+ );
u_freq : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.freq,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.freq
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.freq,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.freq
+ );
u_phase : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.phase,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.phase
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.phase,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.phase
+ );
u_ampl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.ampl,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.ampl
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.ampl,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.ampl
+ );
end generate;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 0a3d83d233..4a072e57f6 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -94,13 +94,13 @@
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_block_gen is
generic (
@@ -150,11 +150,13 @@ end mms_diag_block_gen;
architecture rtl of mms_diag_block_gen is
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_addr_w,
- dat_w => g_buf_dat_w,
- nof_dat => 2**g_buf_addr_w,
- init_sl => '0');
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_addr_w,
+ dat_w => g_buf_dat_w,
+ nof_dat => 2**g_buf_addr_w,
+ init_sl => '0'
+ );
constant c_post_buf_file : string := ".hex";
@@ -205,32 +207,32 @@ begin
mux_ctrl <= 0 when bg_ctrl.enable = '0' else 1;
u_bg_ctrl : entity work.diag_block_gen_reg
- generic map(
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_diag_block_gen_rst => g_diag_block_gen_rst
- )
- port map (
- mm_rst => mm_rst, -- Clocks and reset
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_mosi => reg_bg_ctrl_mosi,
- mm_miso => reg_bg_ctrl_miso,
- bg_ctrl => bg_ctrl
- );
+ generic map(
+ g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_diag_block_gen_rst => g_diag_block_gen_rst
+ )
+ port map (
+ mm_rst => mm_rst, -- Clocks and reset
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_mosi => reg_bg_ctrl_mosi,
+ mm_miso => reg_bg_ctrl_miso,
+ bg_ctrl => bg_ctrl
+ );
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux_bg_data : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => g_buf_addr_w
- )
- port map (
- mosi => ram_bg_data_mosi,
- miso => ram_bg_data_miso,
- mosi_arr => ram_bg_data_mosi_arr,
- miso_arr => ram_bg_data_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => g_buf_addr_w
+ )
+ port map (
+ mosi => ram_bg_data_mosi,
+ miso => ram_bg_data_miso,
+ mosi_arr => ram_bg_data_mosi_arr,
+ miso_arr => ram_bg_data_miso_arr
+ );
gen_streams : for I in 0 to g_nof_streams - 1 generate
no_buffer_ram : if g_use_bg_buffer_ram = false generate
@@ -243,53 +245,53 @@ begin
gen_buffer_ram : if g_use_bg_buffer_ram = true generate
u_buffer_ram : entity common_lib.common_ram_crw_crw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf,
+ -- Sequence number and ".hex" extension are added to the relative path in case a ram file is provided.
+ g_init_file => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & natural'image(g_file_index_arr(I)) & c_post_buf_file)
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_bg_data_mosi_arr(I).wr,
+ wr_dat_a => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w - 1 downto 0),
+ adr_a => ram_bg_data_mosi_arr(I).address(c_buf.adr_w - 1 downto 0),
+ rd_en_a => ram_bg_data_mosi_arr(I).rd,
+ rd_dat_a => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w - 1 downto 0),
+ rd_val_a => ram_bg_data_miso_arr(I).rdval,
+ -- Waveform side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => st_addr_arr(I),
+ rd_en_b => st_rd_arr(I),
+ rd_dat_b => st_rddata_arr(I),
+ rd_val_b => st_rdval_arr(I)
+ );
+ end generate;
+
+ u_diag_block_gen : entity work.diag_block_gen
generic map (
- g_technology => g_technology,
- g_ram => c_buf,
- -- Sequence number and ".hex" extension are added to the relative path in case a ram file is provided.
- g_init_file => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & natural'image(g_file_index_arr(I)) & c_post_buf_file)
+ g_blk_sync => g_blk_sync,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w
)
port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_bg_data_mosi_arr(I).wr,
- wr_dat_a => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w - 1 downto 0),
- adr_a => ram_bg_data_mosi_arr(I).address(c_buf.adr_w - 1 downto 0),
- rd_en_a => ram_bg_data_mosi_arr(I).rd,
- rd_dat_a => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w - 1 downto 0),
- rd_val_a => ram_bg_data_miso_arr(I).rdval,
- -- Waveform side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => st_addr_arr(I),
- rd_en_b => st_rd_arr(I),
- rd_dat_b => st_rddata_arr(I),
- rd_val_b => st_rdval_arr(I)
+ rst => dp_rst,
+ clk => dp_clk,
+ buf_addr => st_addr_arr(I),
+ buf_rden => st_rd_arr(I),
+ buf_rddat => st_rddata_arr(I),
+ buf_rdval => st_rdval_arr(I),
+ ctrl => bg_ctrl, -- same BG control for all streams
+ ctrl_hold => bg_ctrl_hold_arr(I), -- active BG control can differ in time per stream
+ en_sync => en_sync,
+ out_siso => bg_src_in_arr(I),
+ out_sosi => bg_src_out_arr(I)
);
- end generate;
-
- u_diag_block_gen : entity work.diag_block_gen
- generic map (
- g_blk_sync => g_blk_sync,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- buf_addr => st_addr_arr(I),
- buf_rden => st_rd_arr(I),
- buf_rddat => st_rddata_arr(I),
- buf_rdval => st_rdval_arr(I),
- ctrl => bg_ctrl, -- same BG control for all streams
- ctrl_hold => bg_ctrl_hold_arr(I), -- active BG control can differ in time per stream
- en_sync => en_sync,
- out_siso => bg_src_in_arr(I),
- out_sosi => bg_src_out_arr(I)
- );
end generate;
end generate;
@@ -305,7 +307,7 @@ begin
-- User input only, BG only or no input
mux_src_out_arr <= usr_sosi_arr when g_use_usr_input = true else
bg_src_out_arr when g_use_bg = true else
- (others => c_dp_sosi_rst);
+ (others => c_dp_sosi_rst);
end generate;
@@ -316,19 +318,19 @@ begin
gen_streams : for I in 0 to g_nof_streams - 1 generate
-- Add user xon flow control if the user input does not already support it
u_dp_xonoff : entity dp_lib.dp_xonoff
- generic map (
- g_bypass => g_usr_bypass_xonoff -- if the user input already has xon flow control then bypass using g_usr_bypass_xonoff=TRUE
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Frame in
- in_siso => usr_siso_arr(I),
- in_sosi => usr_sosi_arr(I),
- -- Frame out
- out_siso => usr_xflow_src_in_arr(I), -- flush control via out_siso.xon
- out_sosi => usr_xflow_src_out_arr(I)
- );
+ generic map (
+ g_bypass => g_usr_bypass_xonoff -- if the user input already has xon flow control then bypass using g_usr_bypass_xonoff=TRUE
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Frame in
+ in_siso => usr_siso_arr(I),
+ in_sosi => usr_sosi_arr(I),
+ -- Frame out
+ out_siso => usr_xflow_src_in_arr(I), -- flush control via out_siso.xon
+ out_sosi => usr_xflow_src_out_arr(I)
+ );
-- Multiplex the inputs:
-- . [0] = usr input
@@ -340,30 +342,30 @@ begin
mux_snk_in_2arr_2(I)(1) <= bg_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_technology => g_technology,
- -- MUX
- g_mode => 4, -- g_mode=4 for framed input select via sel_ctrl
- g_nof_input => c_mux_nof_input, -- >= 1
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, c_mux_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, c_mux_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Control
- sel_ctrl => mux_ctrl, -- 0 = usr, 1 = BG
- -- ST sinks
- snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
- snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
- -- ST source
- src_in => mux_src_in_arr(I),
- src_out => mux_src_out_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ -- MUX
+ g_mode => 4, -- g_mode=4 for framed input select via sel_ctrl
+ g_nof_input => c_mux_nof_input, -- >= 1
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, c_mux_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, c_mux_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Control
+ sel_ctrl => mux_ctrl, -- 0 = usr, 1 = BG
+ -- ST sinks
+ snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- ST source
+ src_in => mux_src_in_arr(I),
+ src_out => mux_src_out_arr(I)
+ );
end generate;
end generate;
@@ -376,29 +378,29 @@ begin
gen_tx_seq : if g_use_tx_seq = true generate
u_mms_diag_tx_seq : entity work.mms_diag_tx_seq
- generic map (
- g_use_usr_input => c_use_tx_seq_input,
- g_mm_broadcast => c_reg_tx_seq_broadcast,
- g_nof_streams => g_nof_streams,
- g_seq_dat_w => g_seq_dat_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_tx_seq_mosi,
- reg_miso => reg_tx_seq_miso,
-
- -- DP streaming interface
- usr_snk_out_arr => mux_src_in_arr, -- connect when g_use_usr_input=TRUE, else leave not connected
- usr_snk_in_arr => mux_src_out_arr,
- tx_src_out_arr => out_sosi_arr,
- tx_src_in_arr => out_siso_arr
- );
+ generic map (
+ g_use_usr_input => c_use_tx_seq_input,
+ g_mm_broadcast => c_reg_tx_seq_broadcast,
+ g_nof_streams => g_nof_streams,
+ g_seq_dat_w => g_seq_dat_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_tx_seq_mosi,
+ reg_miso => reg_tx_seq_miso,
+
+ -- DP streaming interface
+ usr_snk_out_arr => mux_src_in_arr, -- connect when g_use_usr_input=TRUE, else leave not connected
+ usr_snk_in_arr => mux_src_out_arr,
+ tx_src_out_arr => out_sosi_arr,
+ tx_src_in_arr => out_siso_arr
+ );
end generate;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
index 750bea9c85..5ae37c1574 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
@@ -58,13 +58,13 @@
-- capture some data before and after the trigger event.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_data_buffer is
generic (
@@ -134,28 +134,28 @@ begin
gen_db : if g_use_db = true generate
-- Combine the internal array of mm interfaces for the data_buf to one array that is connected to the port of the MM bus
u_mem_mux_data_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_buf_adr_w
- )
- port map (
- mosi => ram_data_buf_mosi,
- miso => ram_data_buf_miso,
- mosi_arr => ram_data_buf_mosi_arr,
- miso_arr => ram_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_buf_adr_w
+ )
+ port map (
+ mosi => ram_data_buf_mosi,
+ miso => ram_data_buf_miso,
+ mosi_arr => ram_data_buf_mosi_arr,
+ miso_arr => ram_data_buf_miso_arr
+ );
u_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_data_buf_mosi,
- miso => reg_data_buf_miso,
- mosi_arr => reg_data_buf_mosi_arr,
- miso_arr => reg_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_data_buf_mosi,
+ miso => reg_data_buf_miso,
+ mosi_arr => reg_data_buf_mosi_arr,
+ miso_arr => reg_data_buf_miso_arr
+ );
gen_stream : for I in 0 to g_nof_streams - 1 generate
in_data_arr(I) <= in_sosi_arr(I).im(g_data_w / 2 - 1 downto 0) & in_sosi_arr(I).re(g_data_w / 2 - 1 downto 0) when g_data_type = e_complex else
@@ -164,31 +164,31 @@ begin
in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
u_diag_data_buffer : entity work.diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_data => g_buf_nof_data,
- g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_mm_mosi => ram_data_buf_mosi_arr(I),
- ram_mm_miso => ram_data_buf_miso_arr(I),
-
- reg_mm_mosi => reg_data_buf_mosi_arr(I),
- reg_mm_miso => reg_data_buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- in_data => in_data_arr(I),
- in_sync => in_sync,
- in_val => in_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_data => g_buf_nof_data,
+ g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_mm_mosi => ram_data_buf_mosi_arr(I),
+ ram_mm_miso => ram_data_buf_miso_arr(I),
+
+ reg_mm_mosi => reg_data_buf_mosi_arr(I),
+ reg_mm_miso => reg_data_buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ in_data => in_data_arr(I),
+ in_sync => in_sync,
+ in_val => in_sosi_arr(I).valid
+ );
end generate;
end generate;
@@ -198,27 +198,27 @@ begin
gen_rx_seq : if g_use_rx_seq = true generate
u_mms_diag_rx_seq : entity work.mms_diag_rx_seq
- generic map (
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
- g_data_w => g_data_w -- >= g_seq_dat_w, user data width
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped Slave
- reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
- reg_miso => reg_rx_seq_miso,
-
- -- Streaming interface
- rx_snk_in_arr => in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
+ g_data_w => g_data_w -- >= g_seq_dat_w, user data width
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped Slave
+ reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
+ reg_miso => reg_rx_seq_miso,
+
+ -- Streaming interface
+ rx_snk_in_arr => in_sosi_arr
+ );
end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
index 799e3fdc23..0d08392cb9 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
@@ -58,13 +58,13 @@
-- capture some data before and after the trigger event.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_data_buffer_dev is
generic (
@@ -135,28 +135,28 @@ begin
gen_db : if g_use_db = true generate
-- Combine the internal array of mm interfaces for the data_buf to one array that is connected to the port of the MM bus
u_mem_mux_data_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_buf_adr_w
- )
- port map (
- mosi => ram_data_buf_mosi,
- miso => ram_data_buf_miso,
- mosi_arr => ram_data_buf_mosi_arr,
- miso_arr => ram_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_buf_adr_w
+ )
+ port map (
+ mosi => ram_data_buf_mosi,
+ miso => ram_data_buf_miso,
+ mosi_arr => ram_data_buf_mosi_arr,
+ miso_arr => ram_data_buf_miso_arr
+ );
u_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_data_buf_mosi,
- miso => reg_data_buf_miso,
- mosi_arr => reg_data_buf_mosi_arr,
- miso_arr => reg_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_data_buf_mosi,
+ miso => reg_data_buf_miso,
+ mosi_arr => reg_data_buf_mosi_arr,
+ miso_arr => reg_data_buf_miso_arr
+ );
gen_stream : for I in 0 to g_nof_streams - 1 generate
in_data_arr(I) <= in_sosi_arr(I).im(g_data_w / 2 - 1 downto 0) & in_sosi_arr(I).re(g_data_w / 2 - 1 downto 0) when g_data_type = e_complex else
@@ -165,32 +165,32 @@ begin
in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
u_diag_data_buffer : entity work.diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_data => g_buf_nof_data,
- g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_mm_mosi => ram_data_buf_mosi_arr(I),
- ram_mm_miso => ram_data_buf_miso_arr(I),
-
- reg_mm_mosi => reg_data_buf_mosi_arr(I),
- reg_mm_miso => reg_data_buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- in_data => in_data_arr(I),
- in_sync => in_sync,
- in_val => in_sosi_arr(I).valid,
- out_wr_done => out_wr_done_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_data => g_buf_nof_data,
+ g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_mm_mosi => ram_data_buf_mosi_arr(I),
+ ram_mm_miso => ram_data_buf_miso_arr(I),
+
+ reg_mm_mosi => reg_data_buf_mosi_arr(I),
+ reg_mm_miso => reg_data_buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ in_data => in_data_arr(I),
+ in_sync => in_sync,
+ in_val => in_sosi_arr(I).valid,
+ out_wr_done => out_wr_done_arr(I)
+ );
end generate;
end generate;
@@ -200,27 +200,27 @@ begin
gen_rx_seq : if g_use_rx_seq = true generate
u_mms_diag_rx_seq : entity work.mms_diag_rx_seq
- generic map (
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
- g_data_w => g_data_w -- >= g_seq_dat_w, user data width
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped Slave
- reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
- reg_miso => reg_rx_seq_miso,
-
- -- Streaming interface
- rx_snk_in_arr => in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
+ g_data_w => g_data_w -- >= g_seq_dat_w, user data width
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped Slave
+ reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
+ reg_miso => reg_rx_seq_miso,
+
+ -- Streaming interface
+ rx_snk_in_arr => in_sosi_arr
+ );
end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index 6c879f1d14..89621734b2 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -95,13 +95,13 @@
-- COUNTER increment values.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity mms_diag_rx_seq is
generic (
@@ -131,21 +131,23 @@ end mms_diag_rx_seq;
architecture str of mms_diag_rx_seq is
-- Define MM slave register size
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_seq_rx_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_seq_rx_reg_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_seq_rx_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_seq_rx_reg_nof_dat,
+ init_sl => '0'
+ );
-- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("step_3"), "RW", c_word_w, field_default(0) ), -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
- ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ), -- [6] = diag_steps_arr[2]
- ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ), -- [5] = diag_steps_arr[1]
- ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ), -- [4] = diag_steps_arr[0]
- ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ), -- [3]
- ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ), -- [2]
- ( field_name_pad("result"), "RO", 2, field_default(0) ), -- [1] = result[1:0] = res_val_n & res_ok_n
- ( field_name_pad("control"), "RW", 2, field_default(0) )); -- [0] = control[1:0] = diag_sel & diag_en
+ ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ), -- [6] = diag_steps_arr[2]
+ ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ), -- [5] = diag_steps_arr[1]
+ ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ), -- [4] = diag_steps_arr[0]
+ ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ), -- [3]
+ ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ), -- [2]
+ ( field_name_pad("result"), "RO", 2, field_default(0) ), -- [1] = result[1:0] = res_val_n & res_ok_n
+ ( field_name_pad("control"), "RW", 2, field_default(0) )); -- [0] = control[1:0] = diag_sel & diag_en
constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
constant c_reg_dat_w : natural := smallest(c_word_w, g_seq_dat_w);
@@ -217,34 +219,34 @@ begin
-- detect rx sequence errors
u_diag_rx_seq: entity WORK.diag_rx_seq
- generic map (
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_cnt_w => c_word_w,
- g_dat_w => g_seq_dat_w,
- g_diag_res_w => g_seq_dat_w -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Write and read back registers:
- diag_en => diag_en_arr(I),
- diag_sel => diag_sel_arr(I),
- diag_steps_arr => diag_steps_2arr(I),
-
- -- Read only registers:
- diag_res => diag_res_arr(I),
- diag_res_val => diag_res_val_arr(I),
- diag_sample => rx_sample_arr(I),
- diag_sample_diff => rx_sample_diff_arr(I),
- diag_sample_val => rx_sample_val_arr(I),
-
- -- Streaming
- in_cnt => rx_cnt_arr(I),
- in_dat => rx_seq_arr(I),
- in_val => rx_seq_val_arr(I)
- );
+ generic map (
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_cnt_w => c_word_w,
+ g_dat_w => g_seq_dat_w,
+ g_diag_res_w => g_seq_dat_w -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Write and read back registers:
+ diag_en => diag_en_arr(I),
+ diag_sel => diag_sel_arr(I),
+ diag_steps_arr => diag_steps_2arr(I),
+
+ -- Read only registers:
+ diag_res => diag_res_arr(I),
+ diag_res_val => diag_res_val_arr(I),
+ diag_sample => rx_sample_arr(I),
+ diag_sample_diff => rx_sample_diff_arr(I),
+ diag_sample_val => rx_sample_val_arr(I),
+
+ -- Streaming
+ in_cnt => rx_cnt_arr(I),
+ in_dat => rx_seq_arr(I),
+ in_val => rx_seq_val_arr(I)
+ );
-- Map diag_res to single bit and register it to ease timing closure
stat_res_ok_n_arr(I) <= orv(diag_res_arr(I)) when rising_edge(dp_clk);
@@ -272,40 +274,40 @@ begin
end process;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(I),
- sla_out => reg_miso_arr(I),
-
- -- MM registers in dp_clk domain
- in_reg => stat_reg_arr(I),
- out_reg => ctrl_reg_arr(I)
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(I),
+ sla_out => reg_miso_arr(I),
+
+ -- MM registers in dp_clk domain
+ in_reg => stat_reg_arr(I),
+ out_reg => ctrl_reg_arr(I)
+ );
end generate;
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg.adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg.adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 24fdcbad24..11461f4029 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -151,12 +151,12 @@
library IEEE, common_lib, dp_lib; -- init value for out_dat when diag_en = '0'
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity mms_diag_tx_seq is
generic (
@@ -188,17 +188,19 @@ end mms_diag_tx_seq;
architecture str of mms_diag_tx_seq is
-- Define MM slave register size
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_seq_tx_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_seq_tx_reg_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_seq_tx_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_seq_tx_reg_nof_dat,
+ init_sl => '0'
+ );
-- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("modulo"), "RW", c_word_w, field_default(0) ),
- ( field_name_pad("tx_cnt"), "RO", c_word_w, field_default(0) ),
- ( field_name_pad("init"), "RW", c_word_w, field_default(0) ),
- ( field_name_pad("control"), "RW", 3, field_default(0) )); -- control[2:0] = diag_dc & diag_sel & diag_en
+ ( field_name_pad("tx_cnt"), "RO", c_word_w, field_default(0) ),
+ ( field_name_pad("init"), "RW", c_word_w, field_default(0) ),
+ ( field_name_pad("control"), "RW", 3, field_default(0) )); -- control[2:0] = diag_dc & diag_sel & diag_en
constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
@@ -243,28 +245,28 @@ begin
gen_nof_streams: for I in 0 to g_nof_streams - 1 generate
u_diag_tx_seq: entity WORK.diag_tx_seq
- generic map (
- g_latency => c_latency,
- g_cnt_w => c_word_w,
- g_dat_w => g_seq_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Write and read back registers:
- diag_en => diag_en_arr(I),
- diag_sel => diag_sel_arr(I),
- diag_dc => diag_dc_arr(I),
- diag_init => diag_init_arr(I),
- diag_mod => diag_mod_arr(I),
-
- -- Streaming
- diag_req => tx_req_arr(I),
- out_cnt => tx_cnt_arr(I),
- out_dat => tx_dat_arr(I),
- out_val => tx_val_arr(I)
- );
+ generic map (
+ g_latency => c_latency,
+ g_cnt_w => c_word_w,
+ g_dat_w => g_seq_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Write and read back registers:
+ diag_en => diag_en_arr(I),
+ diag_sel => diag_sel_arr(I),
+ diag_dc => diag_dc_arr(I),
+ diag_init => diag_init_arr(I),
+ diag_mod => diag_mod_arr(I),
+
+ -- Streaming
+ diag_req => tx_req_arr(I),
+ out_cnt => tx_cnt_arr(I),
+ out_dat => tx_dat_arr(I),
+ out_val => tx_val_arr(I)
+ );
tx_req_arr(I) <= tx_seq_src_in_arr(I).ready;
@@ -293,41 +295,41 @@ begin
end process;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(I),
- sla_out => reg_miso_arr(I),
-
- -- MM registers in dp_clk domain
- in_reg => stat_reg_arr(I), -- connect out_reg to in_reg for write and readback register
- out_reg => ctrl_reg_arr(I)
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(I),
+ sla_out => reg_miso_arr(I),
+
+ -- MM registers in dp_clk domain
+ in_reg => stat_reg_arr(I), -- connect out_reg to in_reg for write and readback register
+ out_reg => ctrl_reg_arr(I)
+ );
end generate;
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_broadcast => g_mm_broadcast,
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg.adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_broadcast => g_mm_broadcast,
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg.adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
ignore_usr_input : if g_use_usr_input = false generate
-- flow control
@@ -370,19 +372,19 @@ begin
-- Pipeline the streams by 1 to register the mux_seq_src_out_arr data to ease timing closure given that c_tx_seq_latency=0
u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out_arr => mux_seq_src_in_arr,
- snk_in_arr => mux_seq_src_out_arr,
- -- ST source
- src_in_arr => tx_src_in_arr,
- src_out_arr => tx_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out_arr => mux_seq_src_in_arr,
+ snk_in_arr => mux_seq_src_out_arr,
+ -- ST source
+ src_in_arr => tx_src_in_arr,
+ src_out_arr => tx_src_out_arr
+ );
end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
index dfa264de60..e0a0d49bf5 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
@@ -28,12 +28,12 @@
--
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_wg_wideband is
generic (
@@ -86,65 +86,65 @@ architecture str of mms_diag_wg_wideband is
begin
u_mm_reg : entity work.diag_wg_wideband_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- st_wg_ctrl => st_wg_ctrl,
- st_mon_ctrl => st_mon_ctrl
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ st_wg_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl
+ );
u_wg_wideband : entity work.diag_wg_wideband
- generic map (
- g_technology => g_technology,
- -- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
- g_buf_dir => g_buf_dir,
-
- -- Wideband parameters
- g_wideband_factor => g_wideband_factor,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- mm_wrdata => buf_mosi.wrdata(g_buf_dat_w - 1 downto 0),
- mm_address => buf_mosi.address(g_buf_addr_w - 1 downto 0),
- mm_wr => buf_mosi.wr,
- mm_rd => buf_mosi.rd,
- mm_rdval => buf_miso.rdval,
- mm_rddata => buf_miso.rddata(g_buf_dat_w - 1 downto 0),
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => st_restart,
-
- st_ctrl => st_wg_ctrl,
- st_mon_ctrl => st_mon_ctrl,
-
- out_ovr => out_ovr,
- out_dat => out_dat,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_technology => g_technology,
+ -- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
+ g_buf_dir => g_buf_dir,
+
+ -- Wideband parameters
+ g_wideband_factor => g_wideband_factor,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ mm_wrdata => buf_mosi.wrdata(g_buf_dat_w - 1 downto 0),
+ mm_address => buf_mosi.address(g_buf_addr_w - 1 downto 0),
+ mm_wr => buf_mosi.wr,
+ mm_rd => buf_mosi.rd,
+ mm_rdval => buf_miso.rdval,
+ mm_rddata => buf_miso.rddata(g_buf_dat_w - 1 downto 0),
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => st_restart,
+
+ st_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl,
+
+ out_ovr => out_ovr,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sync => out_sync
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
index f7d439ef96..1c8e5f84d7 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
@@ -27,13 +27,13 @@
-- no need to make a mms_diag_wg.vhd.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_wg_wideband_arr is
generic (
@@ -93,63 +93,63 @@ architecture str of mms_diag_wg_wideband_arr is
begin
u_common_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
u_common_mem_mux_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => g_buf_addr_w
- )
- port map (
- mosi => buf_mosi,
- miso => buf_miso,
- mosi_arr => buf_mosi_arr,
- miso_arr => buf_miso_arr
- );
-
- gen_wg : for I in 0 to g_nof_streams - 1 generate
- u_mms_diag_wg_wideband : entity work.mms_diag_wg_wideband
generic map (
- g_technology => g_technology,
- g_cross_clock_domain => g_cross_clock_domain,
- g_buf_dir => g_buf_dir,
- g_wideband_factor => g_wideband_factor,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => g_buf_addr_w
)
port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_mosi_arr(I),
- reg_miso => reg_miso_arr(I),
-
- buf_mosi => buf_mosi_arr(I),
- buf_miso => buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => st_restart,
+ mosi => buf_mosi,
+ miso => buf_miso,
+ mosi_arr => buf_mosi_arr,
+ miso_arr => buf_miso_arr
+ );
- out_ovr => wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
- out_dat => wg_dat( (I + 1) * g_wideband_factor * g_buf_dat_w - 1 downto I * g_wideband_factor * g_buf_dat_w),
- out_val => wg_val( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
- out_sync => wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )
- );
+ gen_wg : for I in 0 to g_nof_streams - 1 generate
+ u_mms_diag_wg_wideband : entity work.mms_diag_wg_wideband
+ generic map (
+ g_technology => g_technology,
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_buf_dir => g_buf_dir,
+ g_wideband_factor => g_wideband_factor,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi_arr(I),
+ reg_miso => reg_miso_arr(I),
+
+ buf_mosi => buf_mosi_arr(I),
+ buf_miso => buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => st_restart,
+
+ out_ovr => wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
+ out_dat => wg_dat( (I + 1) * g_wideband_factor * g_buf_dat_w - 1 downto I * g_wideband_factor * g_buf_dat_w),
+ out_val => wg_val( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
+ out_sync => wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )
+ );
-- wire the wg signals to sosi outputs
@@ -160,8 +160,8 @@ begin
out_sosi_arr(I).valid <= vector_or(wg_val( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ));
out_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ));
out_sosi_arr(I).err <= TO_DP_ERROR(0) when
- vector_or(wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )) = '0' else
- TO_DP_ERROR(2**7); -- pass ADC or WG overflow info on as an error signal
+ vector_or(wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )) = '0' else
+ TO_DP_ERROR(2**7); -- pass ADC or WG overflow info on as an error signal
end generate;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
index e35441f5e3..f1d432634b 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
@@ -28,17 +28,17 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_math_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_math_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_block_gen is
generic (
@@ -51,7 +51,7 @@ entity tb_diag_block_gen is
g_buf_adr_w : natural := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
g_buf_dat_w : natural := 32; -- Waveform buffer stored data width (requires corresponding c_buf_file)
g_try_phasor : boolean := false -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
- -- decimal and analogue format, no self test
+ -- decimal and analogue format, no self test
);
end tb_diag_block_gen;
@@ -64,11 +64,13 @@ architecture tb of tb_diag_block_gen is
constant c_runtime : natural := 1500;
-- Default settings
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_adr_w,
- dat_w => g_buf_dat_w,
- nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_adr_w,
+ dat_w => g_buf_dat_w,
+ nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
+ init_sl => '0'
+ );
constant c_buf_file : string := sel_a_b(c_buf.adr_w = 7 and c_buf.dat_w = 32, "data/diag_block.hex", "UNUSED");
@@ -93,14 +95,28 @@ architecture tb of tb_diag_block_gen is
c_phasor_phase);
-- Default BG control
- constant c_bg_ctrl : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC(g_nof_samples_per_packet, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC(g_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC(95, c_diag_bg_mem_high_adrs_w),
- TO_UVEC(42, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC(
+ g_nof_samples_per_packet,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ g_nof_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ g_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ 95,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 42,
+ c_diag_bg_bsn_init_w)
+ );
constant c_bg_period : natural := TO_UINT(c_bg_ctrl.samples_per_packet) + TO_UINT(c_bg_ctrl.gapsize);
-- Some alternative BG control settings
@@ -109,14 +125,28 @@ architecture tb of tb_diag_block_gen is
constant c_alternative_data_gap : natural := 1 + c_alternative_mem_low_adrs;
-- Another BG control for verifying XON
- constant c_bg_ctrl2 : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC(17, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 0, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC(16, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl2 : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC(
+ 17,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ g_nof_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ 16,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
constant c_bg_period2 : natural := TO_UINT(c_bg_ctrl2.samples_per_packet) + TO_UINT(c_bg_ctrl2.gapsize);
@@ -231,46 +261,46 @@ begin
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => '0',
- rst_b => '0',
- clk_a => clk,
- clk_b => clk,
- wr_en_a => mm_buf_mosi.wr,
- wr_en_b => '0',
- wr_dat_a => mm_buf_mosi.wrdata(c_buf.dat_w - 1 downto 0),
- wr_dat_b => (others => '0'),
- adr_a => mm_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- adr_b => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- rd_en_a => mm_buf_mosi.rd,
- rd_en_b => bg_buf_mosi.rd,
- rd_dat_a => mm_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- rd_dat_b => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- rd_val_a => mm_buf_miso.rdval,
- rd_val_b => bg_buf_miso.rdval
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => '0',
+ rst_b => '0',
+ clk_a => clk,
+ clk_b => clk,
+ wr_en_a => mm_buf_mosi.wr,
+ wr_en_b => '0',
+ wr_dat_a => mm_buf_mosi.wrdata(c_buf.dat_w - 1 downto 0),
+ wr_dat_b => (others => '0'),
+ adr_a => mm_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ adr_b => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ rd_en_a => mm_buf_mosi.rd,
+ rd_en_b => bg_buf_mosi.rd,
+ rd_dat_a => mm_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ rd_dat_b => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ rd_val_a => mm_buf_miso.rdval,
+ rd_val_b => bg_buf_miso.rdval
+ );
u_dut : entity work.diag_block_gen
- generic map(
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w
- )
- port map (
- rst => rst,
- clk => clk,
- buf_addr => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- buf_rden => bg_buf_mosi.rd,
- buf_rddat => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- buf_rdval => bg_buf_miso.rdval,
- ctrl => bg_ctrl,
- ctrl_hold => bg_ctrl_hold,
- out_siso => out_siso_bg,
- out_sosi => out_sosi
- );
+ generic map(
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ buf_addr => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ buf_rden => bg_buf_mosi.rd,
+ buf_rddat => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ buf_rdval => bg_buf_miso.rdval,
+ ctrl => bg_ctrl,
+ ctrl_hold => bg_ctrl_hold,
+ out_siso => out_siso_bg,
+ out_sosi => out_sosi
+ );
random <= func_common_random(random) when rising_edge(clk);
toggle <= not toggle when rising_edge(clk);
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
index 6a0e60f20e..de95569b0b 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
@@ -39,17 +39,17 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_data_buffer is
@@ -114,14 +114,28 @@ architecture tb of tb_diag_data_buffer is
constant c_bg_nof_blocks_per_sync : natural := 8;
constant c_bg_mem_high_addr : natural := g_nof_data - 1;
- constant c_bg_ctrl : t_diag_block_gen := ( '0', -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
- TO_UVEC( c_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_mem_high_addr, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable: On by default in simulation; MM enable required on hardware.
+ '0', -- enable_sync
+ TO_UVEC(
+ c_block_size,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ c_bg_nof_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ c_bg_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ c_bg_mem_high_addr,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
-- Configuration of the databuffers:
constant c_db_nof_streams : positive := g_nof_streams;
@@ -156,7 +170,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -219,10 +233,10 @@ begin
end loop;
nof_valids <= 1;
--- WHILE nof_valids /= 0 LOOP
- proc_mem_mm_bus_rd( 2, mm_clk, reg_diag_data_buf_mosi);
- nof_valids <= TO_UINT(reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0));
--- END LOOP;
+ -- WHILE nof_valids /= 0 LOOP
+ proc_mem_mm_bus_rd( 2, mm_clk, reg_diag_data_buf_mosi);
+ nof_valids <= TO_UINT(reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0));
+ -- END LOOP;
proc_common_wait_some_cycles(mm_clk, 10);
-- Arm the databuffer
@@ -235,56 +249,56 @@ begin
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity work.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_diag_block_gen_rst => c_bg_ctrl,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => bg_sosi_arr(0).sync,
- in_sosi_arr => bg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => bg_sosi_arr(0).sync,
+ in_sosi_arr => bg_sosi_arr
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
index 321cc22b9f..ef32bf68c1 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_frm_generator is
end tb_diag_frm_generator;
@@ -127,35 +127,35 @@ begin
end process;
u_frm_gen : entity work.diag_frm_generator
- generic map (
- g_sel => c_sel,
- g_frame_len => c_frame_len,
- g_sof_period => c_sof_period,
- g_frame_cnt_w => c_frame_cnt_w,
- g_dat_w => c_dat_w,
- g_symbol_w => c_symbol_w,
- g_empty => c_empty
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
-
- -- Static control input (connect via MM or leave open to use default)
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_frame_len => diag_frame_len,
- diag_sof_period => diag_sof_period,
- diag_frame_cnt => diag_frame_cnt,
-
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop,
- out_empty => seq_empty
- );
+ generic map (
+ g_sel => c_sel,
+ g_frame_len => c_frame_len,
+ g_sof_period => c_sof_period,
+ g_frame_cnt_w => c_frame_cnt_w,
+ g_dat_w => c_dat_w,
+ g_symbol_w => c_symbol_w,
+ g_empty => c_empty
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_frame_len => diag_frame_len,
+ diag_sof_period => diag_sof_period,
+ diag_frame_cnt => diag_frame_cnt,
+
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop,
+ out_empty => seq_empty
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
@@ -171,7 +171,7 @@ begin
if seq_sop = '1' then assert seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) report "Unexpected seq_sop"; end if;
if seq_eop = '1' then assert seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) + c_frame_len - 1 report "Unexpected seq_eop"; end if;
- if seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) then assert seq_sop = '1' report "Missing seq_sop"; end if;
+ if seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) then assert seq_sop = '1' report "Missing seq_sop"; end if;
if seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) + c_frame_len - 1 then assert seq_eop = '1' report "Missing seq_eop"; end if;
if seq_sop = '1' then assert unsigned(seq_dat) = unsigned(init_dat) report "Wrong first seq_dat"; end if;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
index 723af72104..b6c6f9bb9c 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_frm_monitor is
end tb_diag_frm_monitor;
@@ -128,54 +128,54 @@ begin
end process;
u_frm_gen : entity work.diag_frm_generator
- generic map (
- g_sel => c_sel,
- g_frame_len => c_frame_len,
- g_sof_period => c_sof_period,
- g_frame_cnt_w => c_frame_cnt_w,
- g_dat_w => c_dat_w,
- g_symbol_w => c_dat_w,
- g_empty => 0
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
-
- -- Static control input (connect via MM or leave open to use default)
- diag_en => gen_diag_en,
- diag_sel => gen_diag_sel,
- diag_frame_len => gen_diag_frame_len,
- diag_sof_period => gen_diag_sof_period,
- diag_frame_cnt => gen_diag_frame_cnt,
-
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop
- );
+ generic map (
+ g_sel => c_sel,
+ g_frame_len => c_frame_len,
+ g_sof_period => c_sof_period,
+ g_frame_cnt_w => c_frame_cnt_w,
+ g_dat_w => c_dat_w,
+ g_symbol_w => c_dat_w,
+ g_empty => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_en => gen_diag_en,
+ diag_sel => gen_diag_sel,
+ diag_frame_len => gen_diag_frame_len,
+ diag_sof_period => gen_diag_sof_period,
+ diag_frame_cnt => gen_diag_frame_cnt,
+
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop
+ );
u_frm_mon : entity work.diag_frm_monitor
- generic map (
- g_frame_cnt_w => c_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
+ generic map (
+ g_frame_cnt_w => c_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
- -- Static control input (connect via MM)
- diag_en => mon_diag_en,
- diag_frame_cnt => mon_diag_frame_cnt,
- diag_error_cnt => mon_diag_error_cnt,
+ -- Static control input (connect via MM)
+ diag_en => mon_diag_en,
+ diag_frame_cnt => mon_diag_frame_cnt,
+ diag_error_cnt => mon_diag_error_cnt,
- -- ST input
- in_eop => seq_eop,
- in_error => seq_error
- );
+ -- ST input
+ in_eop => seq_eop,
+ in_error => seq_error
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
@@ -192,7 +192,7 @@ begin
if seq_sop = '1' then assert seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) report "Unexpected seq_sop"; end if;
if seq_eop = '1' then assert seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) + c_frame_len - 1 report "Unexpected seq_eop"; end if;
- if seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) then assert seq_sop = '1' report "Missing seq_sop"; end if;
+ if seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) then assert seq_sop = '1' report "Missing seq_sop"; end if;
if seq_val = '1' and unsigned(seq_dat) = unsigned(init_dat) + c_frame_len - 1 then assert seq_eop = '1' report "Missing seq_eop"; end if;
if seq_sop = '1' then assert unsigned(seq_dat) = unsigned(init_dat) report "Wrong first seq_dat"; end if;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index 4990dd0672..9f7b8d6413 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -23,16 +23,16 @@
-- Purpose: Test bench package for diag library
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
package tb_diag_pkg is
@@ -44,162 +44,175 @@ package tb_diag_pkg is
s_expect_no_result
);
- procedure proc_diag_seq_read_all(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_tx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- constant c_tx_init : in natural;
- constant c_tx_mod : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_tx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_write_steps(constant c_stream : in natural;
- constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_verify(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal tb_mode : inout t_tb_diag_seq_mode_enum;
- signal tb_verify : out std_logic;
- signal rd_reg : inout t_diag_seq_mm_reg); -- read all MM reg
+ procedure proc_diag_seq_read_all (
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_tx_enable (
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ constant c_tx_init : in natural;
+ constant c_tx_mod : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_enable (
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_tx_disable (
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_disable (
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_write_steps (
+ constant c_stream : in natural;
+ constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_verify (
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal tb_mode : inout t_tb_diag_seq_mode_enum;
+ signal tb_verify : out std_logic;
+ signal rd_reg : inout t_diag_seq_mm_reg); -- read all MM reg
-- Measure ADC/WG input power and determine effective sine amplitude
- procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural; -- number of samples per in_start interval
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal track_max : inout real; -- store local tracker in signal
- signal track_min : inout real; -- store local tracker in signal
- signal accum_mean : inout real; -- store local accumulator in signal
- signal accum_power : inout real; -- store local accumulator in signal
- signal measured_max : out real; -- maximum sample value
- signal measured_min : out real; -- minimum sample value
- signal measured_mean : out real; -- average sample value (DC)
- signal measured_power : out real; -- average sample power
- signal measured_ampl : out real); -- corresponding sine amplitude
+ procedure proc_diag_measure_cw_statistics (
+ constant c_nof_samples : in natural; -- number of samples per in_start interval
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal track_max : inout real; -- store local tracker in signal
+ signal track_min : inout real; -- store local tracker in signal
+ signal accum_mean : inout real; -- store local accumulator in signal
+ signal accum_power : inout real; -- store local accumulator in signal
+ signal measured_max : out real; -- maximum sample value
+ signal measured_min : out real; -- minimum sample value
+ signal measured_mean : out real; -- average sample value (DC)
+ signal measured_power : out real; -- average sample power
+ signal measured_ampl : out real); -- corresponding sine amplitude
-- Measure ADC/WG amplitude and phase using local sin and cos
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural; -- number of samples per in_start interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal ref_I : out real; -- output local I as signal for debugging in wave window
- signal ref_Q : out real; -- output local Q as signal for debugging in wave window
- signal accum_I : inout real; -- store local I accumulator in signal
- signal accum_Q : inout real; -- store local Q accumulator in signal
- signal measured_ampl : out real; -- measured CW amplitude
- signal measured_phase : out real; -- measured CW phase in radials
- signal measured_phase_Ts : out real); -- measured CW phase in sample periods
-
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal ref_I : out real;
- signal ref_Q : out real;
- signal accum_I : inout real;
- signal accum_Q : inout real;
- signal measured_ampl : out real;
- signal measured_phase : out real;
- signal measured_phase_Ts : out real);
+ procedure proc_diag_measure_cw_ampl_and_phase (
+ constant c_nof_samples : in natural; -- number of samples per in_start interval
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal ref_I : out real; -- output local I as signal for debugging in wave window
+ signal ref_Q : out real; -- output local Q as signal for debugging in wave window
+ signal accum_I : inout real; -- store local I accumulator in signal
+ signal accum_Q : inout real; -- store local Q accumulator in signal
+ signal measured_ampl : out real; -- measured CW amplitude
+ signal measured_phase : out real; -- measured CW phase in radials
+ signal measured_phase_Ts : out real); -- measured CW phase in sample periods
+
+ procedure proc_diag_measure_cw_ampl_and_phase (
+ constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal ref_I : out real;
+ signal ref_Q : out real;
+ signal accum_I : inout real;
+ signal accum_Q : inout real;
+ signal measured_ampl : out real;
+ signal measured_phase : out real;
+ signal measured_phase_Ts : out real);
-- Use estimated CW to determine noise power in input sine (e.g. WG sine)
- procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural; -- number of samples per integration interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal cw_ampl : in real; -- estimated CW amplitude of in_dat
- signal cw_phase : in real; -- estimated CW phase of in_dat
- signal cw_dat : out integer; -- estimated CW
- signal cw_noise : out real; -- estimated CW quantization noise
- signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real) ; -- measured noise power in in_dat
-
- procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal cw_ampl : in real;
- signal cw_phase : in real;
- signal cw_dat : out integer;
- signal cw_noise : out real;
- signal accum_noise_power : inout real;
- signal measured_noise_power : out real);
+ procedure proc_diag_measure_cw_noise_power (
+ constant c_nof_samples : in natural; -- number of samples per integration interval
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal cw_ampl : in real; -- estimated CW amplitude of in_dat
+ signal cw_phase : in real; -- estimated CW phase of in_dat
+ signal cw_dat : out integer; -- estimated CW
+ signal cw_noise : out real; -- estimated CW quantization noise
+ signal accum_noise_power : inout real; -- store noise power accumulator in signal
+ signal measured_noise_power : out real) ; -- measured noise power in in_dat
+
+ procedure proc_diag_measure_cw_noise_power (
+ constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal cw_ampl : in real;
+ signal cw_phase : in real;
+ signal cw_dat : out integer;
+ signal cw_noise : out real;
+ signal accum_noise_power : inout real;
+ signal measured_noise_power : out real);
end tb_diag_pkg;
package body tb_diag_pkg is
- procedure proc_diag_seq_read_all(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_read_all (
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
begin
@@ -253,17 +266,18 @@ package body tb_diag_pkg is
rd_reg.rx_sample <= rx_miso.rddata(c_word_w - 1 downto 0);
end proc_diag_seq_read_all;
- procedure proc_diag_seq_tx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- constant c_tx_init : in natural;
- constant c_tx_mod : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_tx_enable (
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ constant c_tx_init : in natural;
+ constant c_tx_mod : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
@@ -283,15 +297,16 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_tx_enable;
- procedure proc_diag_seq_rx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_rx_enable (
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
@@ -308,14 +323,15 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_enable;
- procedure proc_diag_seq_tx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_tx_disable (
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
begin
proc_mem_mm_bus_wr(c_tx_offset + 0, 0, mm_clk, tx_miso, tx_mosi);
@@ -323,14 +339,15 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_tx_disable;
- procedure proc_diag_seq_rx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_rx_disable (
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
begin
proc_mem_mm_bus_wr(c_rx_offset + 0, 0, mm_clk, rx_miso, rx_mosi);
@@ -338,15 +355,16 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_disable;
- procedure proc_diag_seq_rx_write_steps(constant c_stream : in natural;
- constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ procedure proc_diag_seq_rx_write_steps (
+ constant c_stream : in natural;
+ constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
@@ -360,19 +378,20 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_write_steps;
- procedure proc_diag_seq_verify(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal tb_mode : inout t_tb_diag_seq_mode_enum;
- signal tb_verify : out std_logic;
- signal rd_reg : inout t_diag_seq_mm_reg) is -- read all MM reg
- variable v_rx_stat : std_logic_vector(c_word_w - 1 downto 0);
- variable v_rx_sample : std_logic_vector(c_word_w - 1 downto 0);
- variable v_rx_cnt : natural;
- variable v_tx_cnt : natural;
+ procedure proc_diag_seq_verify (
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal tb_mode : inout t_tb_diag_seq_mode_enum;
+ signal tb_verify : out std_logic;
+ signal rd_reg : inout t_diag_seq_mm_reg) is -- read all MM reg
+ variable v_rx_stat : std_logic_vector(c_word_w - 1 downto 0);
+ variable v_rx_sample : std_logic_vector(c_word_w - 1 downto 0);
+ variable v_rx_cnt : natural;
+ variable v_tx_cnt : natural;
begin
-- Read all
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
@@ -461,20 +480,21 @@ package body tb_diag_pkg is
-- measure DC.
-- . accumulate samples during interval and calculate effective amplitude.
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural; -- number of samples per in_start interval
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal track_max : inout real; -- store local tracker in signal
- signal track_min : inout real; -- store local tracker in signal
- signal accum_mean : inout real; -- store local accumulator in signal
- signal accum_power : inout real; -- store local accumulator in signal
- signal measured_max : out real; -- maximum sample value
- signal measured_min : out real; -- minimum sample value
- signal measured_mean : out real; -- average sample value (DC)
- signal measured_power : out real; -- average sample power
- signal measured_ampl : out real) is -- corresponding sine amplitude
+ procedure proc_diag_measure_cw_statistics (
+ constant c_nof_samples : in natural; -- number of samples per in_start interval
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal track_max : inout real; -- store local tracker in signal
+ signal track_min : inout real; -- store local tracker in signal
+ signal accum_mean : inout real; -- store local accumulator in signal
+ signal accum_power : inout real; -- store local accumulator in signal
+ signal measured_max : out real; -- maximum sample value
+ signal measured_min : out real; -- minimum sample value
+ signal measured_mean : out real; -- average sample value (DC)
+ signal measured_power : out real; -- average sample power
+ signal measured_ampl : out real) is -- corresponding sine amplitude
constant c_Nsamples : real := real(c_nof_samples);
constant c_dat : real := real(TO_SINT(in_dat));
constant c_mean : real := accum_mean / c_Nsamples;
@@ -541,21 +561,22 @@ package body tb_diag_pkg is
-- . the sine power of the perfect reference CW (carrier wave) is:
-- cwPower = (A**2)/2
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural; -- number of samples per in_start interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal ref_I : out real; -- output local I as signal for debugging in wave window
- signal ref_Q : out real; -- output local Q as signal for debugging in wave window
- signal accum_I : inout real; -- store local I accumulator in signal
- signal accum_Q : inout real; -- store local Q accumulator in signal
- signal measured_ampl : out real; -- measured CW amplitude
- signal measured_phase : out real; -- measured CW phase in radials
- signal measured_phase_Ts : out real) is -- measured CW phase in sample periods
+ procedure proc_diag_measure_cw_ampl_and_phase (
+ constant c_nof_samples : in natural; -- number of samples per in_start interval
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal ref_I : out real; -- output local I as signal for debugging in wave window
+ signal ref_Q : out real; -- output local Q as signal for debugging in wave window
+ signal accum_I : inout real; -- store local I accumulator in signal
+ signal accum_Q : inout real; -- store local Q accumulator in signal
+ signal measured_ampl : out real; -- measured CW amplitude
+ signal measured_phase : out real; -- measured CW phase in radials
+ signal measured_phase_Ts : out real) is -- measured CW phase in sample periods
constant c_Nsamples : real := real(c_nof_samples);
constant c_Nfft : real := real(c_fft_size);
constant c_omega : real := MATH_2_PI * c_sub / c_Nfft;
@@ -590,20 +611,21 @@ package body tb_diag_pkg is
end if;
end proc_diag_measure_cw_ampl_and_phase;
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal ref_I : out real;
- signal ref_Q : out real;
- signal accum_I : inout real;
- signal accum_Q : inout real;
- signal measured_ampl : out real;
- signal measured_phase : out real;
- signal measured_phase_Ts : out real) is
+ procedure proc_diag_measure_cw_ampl_and_phase (
+ constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal ref_I : out real;
+ signal ref_Q : out real;
+ signal accum_I : inout real;
+ signal accum_Q : inout real;
+ signal measured_ampl : out real;
+ signal measured_phase : out real;
+ signal measured_phase_Ts : out real) is
begin
proc_diag_measure_cw_ampl_and_phase(c_fft_size, c_fft_size, c_sub, dp_clk,
in_dat, in_start, in_val, in_cnt,
@@ -631,20 +653,21 @@ package body tb_diag_pkg is
--
-- SNR = 10*log10(cwPower / noisePower) [dB]
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural; -- number of samples per integration interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal cw_ampl : in real; -- estimated CW amplitude of in_dat
- signal cw_phase : in real; -- estimated CW phase of in_dat
- signal cw_dat : out integer; -- estimated CW
- signal cw_noise : out real; -- estimated CW quantization noise
- signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real) is -- measured noise power in in_dat
+ procedure proc_diag_measure_cw_noise_power (
+ constant c_nof_samples : in natural; -- number of samples per integration interval
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal cw_ampl : in real; -- estimated CW amplitude of in_dat
+ signal cw_phase : in real; -- estimated CW phase of in_dat
+ signal cw_dat : out integer; -- estimated CW
+ signal cw_noise : out real; -- estimated CW quantization noise
+ signal accum_noise_power : inout real; -- store noise power accumulator in signal
+ signal measured_noise_power : out real) is -- measured noise power in in_dat
constant c_Nsamples : real := real(c_nof_samples);
constant c_Nfft : real := real(c_fft_size);
constant c_omega : real := MATH_2_PI * c_sub / c_Nfft;
@@ -673,19 +696,20 @@ package body tb_diag_pkg is
end if;
end proc_diag_measure_cw_noise_power;
- procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal cw_ampl : in real;
- signal cw_phase : in real;
- signal cw_dat : out integer;
- signal cw_noise : out real;
- signal accum_noise_power : inout real;
- signal measured_noise_power : out real) is
+ procedure proc_diag_measure_cw_noise_power (
+ constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal cw_ampl : in real;
+ signal cw_phase : in real;
+ signal cw_dat : out integer;
+ signal cw_noise : out real;
+ signal accum_noise_power : inout real;
+ signal measured_noise_power : out real) is
begin
proc_diag_measure_cw_noise_power(c_fft_size, c_fft_size, c_sub, dp_clk,
in_dat, in_start, in_val, in_cnt,
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd b/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
index 1bc0566e9e..5f22f28ff1 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
@@ -30,7 +30,7 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_diag_regression is
end tb_diag_regression;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 0355c249d6..6f6f15117e 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
-- Purpose: test bench for diag_rx_seq control
-- Usage:
@@ -258,39 +258,39 @@ begin
end process;
u_diag_tx_seq : entity work.diag_tx_seq
- generic map (
- g_cnt_incr => g_tx_cnt_incr,
- g_dat_w => g_seq_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- diag_en => tx_diag_en,
- diag_sel => tx_diag_sel,
- diag_mod => tx_diag_mod,
- diag_req => tx_diag_req,
- out_dat => seq_dat,
- out_val => seq_val
- );
+ generic map (
+ g_cnt_incr => g_tx_cnt_incr,
+ g_dat_w => g_seq_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ diag_en => tx_diag_en,
+ diag_sel => tx_diag_sel,
+ diag_mod => tx_diag_mod,
+ diag_req => tx_diag_req,
+ out_dat => seq_dat,
+ out_val => seq_val
+ );
u_diag_rx_seq : entity work.diag_rx_seq
- generic map (
- g_use_steps => g_rx_use_steps,
- g_nof_steps => c_rx_nof_steps,
- g_dat_w => g_seq_dat_w,
- g_diag_res_w => c_diag_res_w
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => seq_dat,
- in_val => seq_val,
- diag_en => rx_diag_en,
- diag_sel => rx_diag_sel,
- diag_steps_arr => rx_diag_steps_arr,
- diag_res => diag_res,
- diag_res_val => diag_res_val
- );
+ generic map (
+ g_use_steps => g_rx_use_steps,
+ g_nof_steps => c_rx_nof_steps,
+ g_dat_w => g_seq_dat_w,
+ g_diag_res_w => c_diag_res_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => seq_dat,
+ in_val => seq_val,
+ diag_en => rx_diag_en,
+ diag_sel => rx_diag_sel,
+ diag_steps_arr => rx_diag_steps_arr,
+ diag_res => diag_res,
+ diag_res_val => diag_res_val
+ );
p_report : process (clk)
begin
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
index ce4be53f02..60bdaf9aeb 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_tx_frm is
end tb_diag_tx_frm;
@@ -156,30 +156,30 @@ begin
end process;
u_diag_tx_frm : entity work.diag_tx_frm
- generic map (
- g_sel => c_sel,
- g_init => c_init,
- g_frame_len => c_frame_len,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- Static control input (connect via MM or leave open to use default)
- diag_sel => diag_sel,
- diag_frame_len => diag_frame_len,
- -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
- diag_ready => diag_ready,
- diag_init => diag_init,
- diag_sop => diag_sop,
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop
- );
+ generic map (
+ g_sel => c_sel,
+ g_init => c_init,
+ g_frame_len => c_frame_len,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- Static control input (connect via MM or leave open to use default)
+ diag_sel => diag_sel,
+ diag_frame_len => diag_frame_len,
+ -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
+ diag_ready => diag_ready,
+ diag_init => diag_init,
+ diag_sop => diag_sop,
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
index 0247eb2740..bea94e2b3a 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_tx_seq is
end tb_diag_tx_seq;
@@ -107,18 +107,18 @@ begin
end process;
u_diag_tx_seq : entity work.diag_tx_seq
- generic map (
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_req => diag_req,
- out_dat => seq_dat,
- out_val => seq_val
- );
+ generic map (
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_req => diag_req,
+ out_dat => seq_dat,
+ out_val => seq_val
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
index 9853faafcf..07c888133b 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
@@ -21,12 +21,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
-- Usage:
-- > do wave_diag_wg_wideband.do
@@ -51,20 +51,22 @@ architecture tb of tb_diag_wg is
constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
-- Default settings
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_adr_w,
- dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
- nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_adr_w,
+ dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
+ nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
+ init_sl => '0'
+ );
constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, "data/diag_sin_2048x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, "data/diag_sin_1024x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, "data/diag_sin_1024x8.hex", "UNUSED")));
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, "data/diag_sin_1024x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, "data/diag_sin_1024x8.hex", "UNUSED")));
constant c_wg_nof_samples : natural := c_buf.nof_dat; -- must be <= c_buf.nof_dat
constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
constant c_wg_full_scale : natural := 2**(g_wg_dat_w - 1) - 1;
@@ -124,13 +126,13 @@ begin
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
--- wg_freq <= INTEGER(0.5 * c_freq_unit);
--- wg_phase <= INTEGER(90.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(0.5 * c_freq_unit);
+ -- wg_phase <= INTEGER(90.0 * c_phase_unit);
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
-- this also applies to 2.0, 3.0, 4.0 etc
--- wg_freq <= INTEGER(1.0 * c_freq_unit);
--- wg_phase <= INTEGER(45.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(45.0 * c_phase_unit);
-- Sinus Fs/16
wg_freq <= integer(0.0625 * c_freq_unit);
@@ -140,12 +142,12 @@ begin
wg_phase <= integer(0.0 * c_phase_unit);
-- Sinus Fs/17
--- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
--- wg_phase <= INTEGER(0.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(0.0 * c_phase_unit);
wg_ampl <= integer(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
--- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
--- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
+ -- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
+ -- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
wait until rising_edge(clk); -- align to rising edge
wait for c_clk_period * 200;
@@ -209,55 +211,55 @@ begin
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => '0',
- rst_b => '0',
- clk_a => clk,
- clk_b => clk,
- wr_en_a => '0',
- wr_en_b => '0',
- wr_dat_a => (others => '0'),
- wr_dat_b => (others => '0'),
- adr_a => (others => '0'),
- adr_b => buf_addr,
- rd_en_a => '0',
- rd_en_b => buf_rden,
- rd_dat_a => OPEN,
- rd_dat_b => buf_rddat,
- rd_val_a => OPEN,
- rd_val_b => buf_rdval
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => '0',
+ rst_b => '0',
+ clk_a => clk,
+ clk_b => clk,
+ wr_en_a => '0',
+ wr_en_b => '0',
+ wr_dat_a => (others => '0'),
+ wr_dat_b => (others => '0'),
+ adr_a => (others => '0'),
+ adr_b => buf_addr,
+ rd_en_a => '0',
+ rd_en_b => buf_rden,
+ rd_dat_a => OPEN,
+ rd_dat_b => buf_rddat,
+ rd_val_a => OPEN,
+ rd_val_b => buf_rdval
+ );
-- Waveform generator
u_wg : entity work.diag_wg
- generic map (
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w,
- g_calc_support => true,
- g_calc_gain_w => c_wg_gain_w,
- g_calc_dat_w => g_wg_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- restart => restart,
-
- buf_rddat => buf_rddat,
- buf_rdval => buf_rdval,
- buf_addr => buf_addr,
- buf_rden => buf_rden,
-
- ctrl => wg_ctrl,
-
- out_ovr => wg_ovr,
- out_dat => wg_dat,
- out_val => wg_val,
- out_sync => wg_sync
- );
+ generic map (
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w,
+ g_calc_support => true,
+ g_calc_gain_w => c_wg_gain_w,
+ g_calc_dat_w => g_wg_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ restart => restart,
+
+ buf_rddat => buf_rddat,
+ buf_rdval => buf_rdval,
+ buf_addr => buf_addr,
+ buf_rden => buf_rden,
+
+ ctrl => wg_ctrl,
+
+ out_ovr => wg_ovr,
+ out_dat => wg_dat,
+ out_val => wg_val,
+ out_sync => wg_sync
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index e91f7354c6..844e7bf3a5 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -29,17 +29,17 @@
-- . Observe state in diag_wg(0).
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_wg_wideband is
generic (
-- Wideband parameters
g_wideband_factor : natural := 4; -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
- -- Take care that the g_wideband_factor and c_clk_freq match the simulation time resolution of integer 1 ps
+ -- Take care that the g_wideband_factor and c_clk_freq match the simulation time resolution of integer 1 ps
-- Basic WG parameters, see diag_wg.vhd for their meaning
g_buf_addr_w : natural := 10;
g_buf_dat_w : natural := 8;
@@ -56,8 +56,8 @@ architecture tb of tb_diag_wg_wideband is
constant c_buf_nof_dat : natural := 2**g_buf_addr_w;
constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
constant c_wg_full_scale : natural := 2**(g_wg_dat_w - 1) - 1;
@@ -133,13 +133,13 @@ begin
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
--- wg_freq <= INTEGER(0.5 * c_freq_unit);
--- wg_phase <= INTEGER(90.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(0.5 * c_freq_unit);
+ -- wg_phase <= INTEGER(90.0 * c_phase_unit);
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
-- this also applies to 2.0, 3.0, 4.0 etc
--- wg_freq <= INTEGER(1.0 * c_freq_unit);
--- wg_phase <= INTEGER(45.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(45.0 * c_phase_unit);
-- Sinus Fs/16
wg_freq <= integer(0.0625 * c_freq_unit);
@@ -149,12 +149,12 @@ begin
wg_phase <= integer(0.0 * c_phase_unit);
-- Sinus Fs/17
--- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
--- wg_phase <= INTEGER(0.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(0.0 * c_phase_unit);
wg_ampl <= integer(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
--- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
--- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
+ -- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
+ -- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
wait until rising_edge(clk); -- align to rising edge
cur_ctrl <= wg_ctrl;
@@ -265,41 +265,41 @@ begin
u_wideband_wg : entity work.diag_wg_wideband
- generic map (
- -- Wideband parameters
- g_wideband_factor => g_wideband_factor,
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => c_wg_gain_w,
- g_calc_dat_w => g_wg_dat_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => '0',
- mm_clk => '0',
-
- mm_wrdata => (others => '0'),
- mm_address => (others => '0'),
- mm_wr => '0',
- mm_rd => '0',
- mm_rdval => OPEN,
- mm_rddata => OPEN,
-
- -- Streaming clock domain
- st_rst => rst,
- st_clk => clk,
- st_restart => restart,
-
- st_ctrl => wg_ctrl,
- st_mon_ctrl => mon_ctrl,
-
- out_ovr => out_ovr,
- out_dat => out_dat,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ -- Wideband parameters
+ g_wideband_factor => g_wideband_factor,
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => c_wg_gain_w,
+ g_calc_dat_w => g_wg_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => '0',
+ mm_clk => '0',
+
+ mm_wrdata => (others => '0'),
+ mm_address => (others => '0'),
+ mm_wr => '0',
+ mm_rd => '0',
+ mm_rdval => OPEN,
+ mm_rddata => OPEN,
+
+ -- Streaming clock domain
+ st_rst => rst,
+ st_clk => clk,
+ st_restart => restart,
+
+ st_ctrl => wg_ctrl,
+ st_mon_ctrl => mon_ctrl,
+
+ out_ovr => out_ovr,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sync => out_sync
+ );
-- Map wideband WG out_* slv to wg_* arrays to ease interpretation in wave window
gen_wires : for I in 0 to g_wideband_factor - 1 generate
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
index 05e007d5bb..bbd0b6e7ba 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
@@ -27,17 +27,17 @@
-- Observe tb_state and check the out_sosi_0 fields if data is OK.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
entity tb_mms_diag_block_gen is
generic (
@@ -216,24 +216,24 @@ begin
-- User input modelled by another BG
-------------------------------------------------
u_user : entity work.mms_diag_block_gen
- generic map (
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => c_buf_dat_w,
- g_buf_addr_w => c_buf_addr_w,
- g_file_name_prefix => c_file_name_prefix,
- g_diag_block_gen_rst => c_diag_block_gen_enabled -- user BG is default enabled
- )
- port map (
- -- System
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => '0',
- -- ST interface
- out_siso_arr => usr_src_in_arr,
- out_sosi_arr => usr_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => c_buf_dat_w,
+ g_buf_addr_w => c_buf_addr_w,
+ g_file_name_prefix => c_file_name_prefix,
+ g_diag_block_gen_rst => c_diag_block_gen_enabled -- user BG is default enabled
+ )
+ port map (
+ -- System
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => '0',
+ -- ST interface
+ out_siso_arr => usr_src_in_arr,
+ out_sosi_arr => usr_src_out_arr
+ );
-- Use sufficiently large FIFO to provide siso.ready flow control to the user input
no_user_fifo : if c_use_user_fifo = false generate
@@ -244,37 +244,37 @@ begin
gen_user_fifo : if c_use_user_fifo = true generate
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_user_fifo : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_buf_dat_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true,
- g_use_complex => false,
- g_fifo_size => c_usr_fifo_size,
- g_fifo_af_margin => 4,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- wr_ful => OPEN,
- usedw => OPEN,
- rd_emp => OPEN,
- -- ST sink
- snk_out => usr_src_in_arr(I),
- snk_in => usr_src_out_arr(I),
- -- ST source
- src_in => usr_fifo_src_in_arr(I),
- src_out => usr_fifo_src_out_arr(I)
- );
+ generic map (
+ g_data_w => c_buf_dat_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true,
+ g_use_complex => false,
+ g_fifo_size => c_usr_fifo_size,
+ g_fifo_af_margin => 4,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => OPEN,
+ usedw => OPEN,
+ rd_emp => OPEN,
+ -- ST sink
+ snk_out => usr_src_in_arr(I),
+ snk_in => usr_src_out_arr(I),
+ -- ST source
+ src_in => usr_fifo_src_in_arr(I),
+ src_out => usr_fifo_src_out_arr(I)
+ );
end generate;
end generate;
@@ -303,44 +303,44 @@ begin
-- Device under test
-------------------------------------------------
u_dut : entity work.mms_diag_block_gen
- generic map (
- -- Generate configurations
- g_use_usr_input => g_use_usr_input,
- g_use_bg => g_use_bg,
- g_use_tx_seq => g_use_tx_seq,
- -- General
- g_nof_streams => g_nof_streams,
- -- BG settings
- g_use_bg_buffer_ram => g_use_bg_buffer_ram,
- g_buf_dat_w => c_buf_dat_w,
- g_buf_addr_w => c_buf_addr_w,
- g_file_name_prefix => c_file_name_prefix,
- g_diag_block_gen_rst => c_diag_block_gen_rst, -- user BG is default disabled, MM controlled by p_dut_bg_ctrl
- -- User input multiplexer option
- g_usr_bypass_xonoff => g_usr_bypass_xonoff,
- -- Tx_seq
- g_seq_dat_w => c_buf_dat_w -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_buf_dat_w
- )
- port map (
- -- System
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => en_sync,
- -- MM interface
- ram_bg_data_mosi => ram_bg_data_mosi,
- ram_bg_data_miso => ram_bg_data_miso,
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => reg_bg_ctrl_miso,
- reg_tx_seq_mosi => reg_tx_seq_mosi,
- reg_tx_seq_miso => reg_tx_seq_miso,
- -- ST interface
- usr_siso_arr => usr_fifo_src_in_arr,
- usr_sosi_arr => usr_fifo_src_out_arr,
- out_siso_arr => out_siso_arr,
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ -- Generate configurations
+ g_use_usr_input => g_use_usr_input,
+ g_use_bg => g_use_bg,
+ g_use_tx_seq => g_use_tx_seq,
+ -- General
+ g_nof_streams => g_nof_streams,
+ -- BG settings
+ g_use_bg_buffer_ram => g_use_bg_buffer_ram,
+ g_buf_dat_w => c_buf_dat_w,
+ g_buf_addr_w => c_buf_addr_w,
+ g_file_name_prefix => c_file_name_prefix,
+ g_diag_block_gen_rst => c_diag_block_gen_rst, -- user BG is default disabled, MM controlled by p_dut_bg_ctrl
+ -- User input multiplexer option
+ g_usr_bypass_xonoff => g_usr_bypass_xonoff,
+ -- Tx_seq
+ g_seq_dat_w => c_buf_dat_w -- >= 1, test sequence data width. Choose g_seq_dat_w <= g_buf_dat_w
+ )
+ port map (
+ -- System
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => en_sync,
+ -- MM interface
+ ram_bg_data_mosi => ram_bg_data_mosi,
+ ram_bg_data_miso => ram_bg_data_miso,
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => reg_bg_ctrl_miso,
+ reg_tx_seq_mosi => reg_tx_seq_mosi,
+ reg_tx_seq_miso => reg_tx_seq_miso,
+ -- ST interface
+ usr_siso_arr => usr_fifo_src_in_arr,
+ usr_sosi_arr => usr_fifo_src_out_arr,
+ out_siso_arr => out_siso_arr,
+ out_sosi_arr => out_sosi_arr
+ );
-------------------------------------------------
-- Verification
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
index 0efb8a4a81..8321460d57 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
@@ -28,17 +28,17 @@
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
-use work.tb_diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
+ use work.tb_diag_pkg.all;
entity tb_mms_diag_seq is
generic (
@@ -287,48 +287,48 @@ begin
u_mms_diag_tx_seq: entity WORK.mms_diag_tx_seq
- generic map(
- g_mm_broadcast => g_mm_broadcast_tx,
- g_nof_streams => g_nof_streams,
- g_seq_dat_w => g_seq_dat_w
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_tx_mosi,
- reg_miso => reg_tx_miso,
-
- -- DP streaming interface
- tx_src_out_arr => tx_src_out_arr,
- tx_src_in_arr => tx_src_in_arr
- );
+ generic map(
+ g_mm_broadcast => g_mm_broadcast_tx,
+ g_nof_streams => g_nof_streams,
+ g_seq_dat_w => g_seq_dat_w
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_tx_mosi,
+ reg_miso => reg_tx_miso,
+
+ -- DP streaming interface
+ tx_src_out_arr => tx_src_out_arr,
+ tx_src_in_arr => tx_src_in_arr
+ );
u_mms_diag_rx_seq: entity WORK.mms_diag_rx_seq
- generic map(
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_seq_dat_w => g_seq_dat_w,
- g_data_w => g_data_w
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_rx_mosi,
- reg_miso => reg_rx_miso,
-
- -- DP streaming interface
- rx_snk_in_arr => rx_snk_in_arr
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_seq_dat_w => g_seq_dat_w,
+ g_data_w => g_data_w
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_rx_mosi,
+ reg_miso => reg_rx_miso,
+
+ -- DP streaming interface
+ rx_snk_in_arr => rx_snk_in_arr
+ );
p_connect : process(tx_src_out_arr, force_low_error, force_replicate_error)
begin
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
index 7dc5753126..3333725f5f 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
@@ -29,8 +29,8 @@
-- > run -all
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_diag_block_gen is
end tb_tb_diag_block_gen;
@@ -51,7 +51,7 @@ begin
-- g_buf_adr_w : NATURAL := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
-- g_buf_dat_w : NATURAL := 32 -- Waveform buffer stored data width (requires corresponding c_buf_file)
-- g_try_phasor : BOOLEAN := FALSE -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
- -- decimal and analogue format, no self test
+ -- decimal and analogue format, no self test
u_bg : entity work.tb_diag_block_gen generic map (e_active, 96, 10, 32, 7, 32, false);
u_bg_ready : entity work.tb_diag_block_gen generic map (e_random, 96, 10, 32, 7, 32, false);
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
index 2eca397d4c..a9f4524dad 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_diag_rx_seq is
end tb_tb_diag_rx_seq;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
index 5365f236bc..6b45dcd30f 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_mms_diag_block_gen is
end tb_tb_mms_diag_block_gen;
@@ -43,15 +43,15 @@ architecture tb of tb_tb_mms_diag_block_gen is
begin
--- g_use_usr_input : BOOLEAN := TRUE;
--- g_use_bg : BOOLEAN := TRUE;
--- g_use_tx_seq : BOOLEAN := FALSE;
--- g_use_bg_buffer_ram : BOOLEAN := TRUE;
--- g_usr_bypass_xonoff : BOOLEAN := FALSE;
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
--- g_nof_repeat : NATURAL := 2;
--- g_nof_streams : NATURAL := 16;
--- g_gap_size : NATURAL := 160
+ -- g_use_usr_input : BOOLEAN := TRUE;
+ -- g_use_bg : BOOLEAN := TRUE;
+ -- g_use_tx_seq : BOOLEAN := FALSE;
+ -- g_use_bg_buffer_ram : BOOLEAN := TRUE;
+ -- g_usr_bypass_xonoff : BOOLEAN := FALSE;
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- g_nof_repeat : NATURAL := 2;
+ -- g_nof_streams : NATURAL := 16;
+ -- g_gap_size : NATURAL := 160
u_bg_one_stream : entity work.tb_mms_diag_block_gen generic map (false, true, false, true, false, e_active, 1, 1, 0);
u_bg_gap_0 : entity work.tb_mms_diag_block_gen generic map (false, true, false, true, false, e_active, 1, 3, 0);
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
index edb55d1e35..8d12bb0fa8 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_mms_diag_seq is
end tb_tb_mms_diag_seq;
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
index 969c2edca0..f6c4c3636b 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
@@ -32,11 +32,11 @@
-- All control inputs and status outputs apply to an individual stream.
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity diagnostics is
generic (
@@ -46,7 +46,7 @@ entity diagnostics is
g_src_latency : natural := 1;
g_snk_latency : natural := 1;
g_separate_clk : boolean := false -- Use separate SRC and SNK clock domains
- );
+ );
port (
rst : in std_logic := '0';
clk : in std_logic := '0';
@@ -137,57 +137,57 @@ begin
snk_diag_res_val(i) <= andv(substream_snk_diag_res_val(i)); -- If all substream diag results are valid, the stream's diag_res is valid.
u_tx_latency_adpt: entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_src_latency
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_src_latency
)
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
- snk_out => tx_dpmon_siso_arr(i),
- snk_in => tx_dpmon_sosi_arr(i),
+ snk_out => tx_dpmon_siso_arr(i),
+ snk_in => tx_dpmon_sosi_arr(i),
- src_out => src_out_arr(i),
- src_in => src_in_arr(i)
- );
+ src_out => src_out_arr(i),
+ src_in => src_in_arr(i)
+ );
u_rx_latency_adpt: entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_snk_latency,
- g_out_latency => 1
- )
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
+ generic map (
+ g_in_latency => g_snk_latency,
+ g_out_latency => 1
+ )
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
- src_out => rx_dpmon_sosi_arr(i),
- src_in => rx_dpmon_siso_arr(i)
- );
+ src_out => rx_dpmon_sosi_arr(i),
+ src_in => rx_dpmon_siso_arr(i)
+ );
tx_diag_req(i) <= tx_siso_arr(i).ready and tx_siso_arr(i).xon;
gen_bg : if g_block_len > 0 generate
u_dp_block_gen: entity dp_lib.dp_block_gen
- generic map (
- g_nof_data => g_block_len,
- g_empty => 0,
- g_channel => 0,
- g_error => 0
- )
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
+ generic map (
+ g_nof_data => g_block_len,
+ g_empty => 0,
+ g_channel => 0,
+ g_error => 0
+ )
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
- src_in => tx_bg_siso_arr(i),
- src_out => tx_bg_sosi_arr(i),
+ src_in => tx_bg_siso_arr(i),
+ src_out => tx_bg_sosi_arr(i),
- en => src_diag_en(i)
- );
+ en => src_diag_en(i)
+ );
tx_sosi_arr(i).sop <= tx_bg_sosi_arr(i).sop;
tx_sosi_arr(i).eop <= tx_bg_sosi_arr(i).eop;
@@ -201,41 +201,41 @@ begin
gen_nof_substreams : for j in c_nof_substreams - 1 downto 0 generate
u_diag_tx_seq: entity diag_lib.diag_tx_seq
- generic map (
- g_dat_w => c_sub_stream_dat_w
+ generic map (
+ g_dat_w => c_sub_stream_dat_w
)
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
- clken => tb_clken(i),
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
+ clken => tb_clken(i),
- diag_en => src_diag_en(i),
- diag_sel => src_diag_md(i),
- diag_init => (others => '0'),
+ diag_en => src_diag_en(i),
+ diag_sel => src_diag_md(i),
+ diag_init => (others => '0'),
- diag_req => tx_diag_req(i),
- out_dat => tx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w ),
- out_val => tx_seq_out_val(i)(j)
- );
+ diag_req => tx_diag_req(i),
+ out_dat => tx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w ),
+ out_val => tx_seq_out_val(i)(j)
+ );
u_diag_rx_seq: entity diag_lib.diag_rx_seq
- generic map (
- g_dat_w => c_sub_stream_dat_w,
- g_diag_res_w => c_sub_stream_dat_w
+ generic map (
+ g_dat_w => c_sub_stream_dat_w,
+ g_diag_res_w => c_sub_stream_dat_w
)
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
- diag_en => snk_diag_en(i),
- diag_sel => snk_diag_md(i),
+ diag_en => snk_diag_en(i),
+ diag_sel => snk_diag_md(i),
- orv(diag_res) => substream_snk_diag_res(i)(j), -- vector-wise OR to create a one-bit diag_result per substream
- diag_res_val => substream_snk_diag_res_val(i)(j),
+ orv(diag_res) => substream_snk_diag_res(i)(j), -- vector-wise OR to create a one-bit diag_result per substream
+ diag_res_val => substream_snk_diag_res_val(i)(j),
- in_dat => rx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w),
- in_val => rx_sosi_arr(i).valid
- );
+ in_dat => rx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w),
+ in_val => rx_sosi_arr(i).valid
+ );
end generate;
tx_sosi_arr(i).valid <= tx_seq_out_val(i)(0);
@@ -245,42 +245,42 @@ begin
u_tx_dpmon : entity dp_lib.dp_mon
- generic map (
- g_latency => 1
- )
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
- en => src_diag_en(i),
+ generic map (
+ g_latency => 1
+ )
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
+ en => src_diag_en(i),
- snk_out => tx_siso_arr(i),
- snk_in => tx_sosi_arr(i),
+ snk_out => tx_siso_arr(i),
+ snk_in => tx_sosi_arr(i),
- src_in => tx_dpmon_siso_arr(i),
- src_out => tx_dpmon_sosi_arr(i),
+ src_in => tx_dpmon_siso_arr(i),
+ src_out => tx_dpmon_sosi_arr(i),
- clr => src_val_cnt_clr(i),
- word_cnt => src_val_cnt(i)
- );
+ clr => src_val_cnt_clr(i),
+ word_cnt => src_val_cnt(i)
+ );
u_rx_dpmon : entity dp_lib.dp_mon
- generic map (
- g_latency => 1
- )
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
- en => snk_diag_en(i),
-
- snk_out => rx_dpmon_siso_arr(i),
- snk_in => rx_dpmon_sosi_arr(i),
-
- src_in => rx_siso_arr(i),
- src_out => rx_sosi_arr(i),
-
- clr => snk_val_cnt_clr(i),
- word_cnt => snk_val_cnt(i)
- );
+ generic map (
+ g_latency => 1
+ )
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
+ en => snk_diag_en(i),
+
+ snk_out => rx_dpmon_siso_arr(i),
+ snk_in => rx_dpmon_sosi_arr(i),
+
+ src_in => rx_siso_arr(i),
+ src_out => rx_sosi_arr(i),
+
+ clr => snk_val_cnt_clr(i),
+ word_cnt => snk_val_cnt(i)
+ );
end generate;
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
index 30a9492f49..a76ee316d9 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
entity diagnostics_reg is
generic (
g_nof_streams : natural;
g_separate_clk : boolean := false -- Use separate SRC and SNK clock domains
- );
+ );
port (
-- Clocks and reset
mm_rst : in std_logic; -- reset synchronous with mm_clk
@@ -60,7 +60,7 @@ entity diagnostics_reg is
st_snk_cnt_clr_evt : out std_logic_vector(g_nof_streams - 1 downto 0);
st_snk_diag_val : in std_logic_vector(g_nof_streams - 1 downto 0);
st_snk_diag_res : in std_logic_vector(g_nof_streams - 1 downto 0)
- );
+ );
end diagnostics_reg;
@@ -68,11 +68,13 @@ architecture rtl of diagnostics_reg is
constant c_nof_registers : natural := 40; -- src_cnt and snk_cnt registers should be variable in size....but the CASE process makes that difficult.
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_registers),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_registers,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_registers),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_registers,
+ init_sl => '0'
+ );
-- Registers in mm_clk domain
signal mm_src_en : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -352,11 +354,11 @@ begin
out_pulse => st_snk_cnt_clr_evt(i)
);
- -- Diag_res and related signals are polled after a certain nof words has been
- -- received - data will be stable.
+ -- Diag_res and related signals are polled after a certain nof words has been
+ -- received - data will be stable.
--- mm_snk_diag_val(i) <= st_snk_diag_val(i);
--- mm_snk_diag_res(i) <= st_snk_diag_res(i);
+ -- mm_snk_diag_val(i) <= st_snk_diag_val(i);
+ -- mm_snk_diag_res(i) <= st_snk_diag_res(i);
end generate;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
index 19e0c35d62..01c10a1a5f 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
@@ -21,20 +21,20 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mm_rx_logger is
generic (
g_technology : natural := c_tech_select_default;
g_dat_w : natural;
g_fifo_wr_depth : natural := 128 -- Only put powers of 2 here.
- );
+ );
port (
rx_rst : in std_logic;
rx_clk : in std_logic;
@@ -94,7 +94,7 @@ architecture str of mm_rx_logger is
signal trig_log_en : std_logic;
signal log_en : std_logic;
signal mm_ovr : std_logic := '0'; -- Normal operation (mm_over='0') : trigger enable/disable inputs control log_en
- -- Overridden operation (mm_over='1'): MM master controls log_en
+ -- Overridden operation (mm_over='1'): MM master controls log_en
signal mm_trig_on : std_logic;
signal mm_trig_one_shot : std_logic;
@@ -123,17 +123,17 @@ begin
-- FSM to enable/disable logging based on trigger inputs
u_mm_rx_logger_trig : entity work.mm_rx_logger_trig
- port map (
- clk => rx_clk,
- rst => rx_rst,
- trig_on => mm_trig_on,
- one_shot => mm_trig_one_shot,
- log_en_evt => trig_en_evt,
- log_dis_evt => trig_dis_evt,
- log_nof_words => mm_trig_nof_words,
- log_cnt => mm_trig_nof_logged_words,
- log_en => trig_log_en
- );
+ port map (
+ clk => rx_clk,
+ rst => rx_rst,
+ trig_on => mm_trig_on,
+ one_shot => mm_trig_one_shot,
+ log_en_evt => trig_en_evt,
+ log_dis_evt => trig_dis_evt,
+ log_nof_words => mm_trig_nof_words,
+ log_cnt => mm_trig_nof_logged_words,
+ log_en => trig_log_en
+ );
log_en <= trig_log_en or sla_log_en; -- Allow slave input to enable logging
mst_log_en <= log_en; -- Forward log_en signal to master output
@@ -145,41 +145,41 @@ begin
-- The FIFO's almost_full will de-assert it's snk ready signal. We'll use
-- that to flush the FIFO on the src side.
u_data_log_fifo : entity dp_lib.dp_fifo_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_dat_w,
- g_use_ctrl => false,
- g_fifo_size => g_fifo_wr_depth
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
-
- snk_out => data_log_fifo_siso,
- snk_in => data_log_fifo_sosi,
-
- src_in => data_flusher_siso,
- src_out => data_flusher_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_dat_w,
+ g_use_ctrl => false,
+ g_fifo_size => g_fifo_wr_depth
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+
+ snk_out => data_log_fifo_siso,
+ snk_in => data_log_fifo_sosi,
+
+ src_in => data_flusher_siso,
+ src_out => data_flusher_sosi
+ );
-- dp_flush to flush data log FIFO when almost full.
u_data_flush: entity dp_lib.dp_flush
- generic map (
- g_framed_xon => false,
- g_framed_xoff => false
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- -- ST sink
- snk_in => data_flusher_sosi,
- snk_out => data_flusher_siso,
- -- ST source
- src_in => ovr_data_dpmm_fifo_siso,
- src_out => data_dpmm_fifo_sosi,
- -- Enable flush
- flush_en => flush_en
- );
+ generic map (
+ g_framed_xon => false,
+ g_framed_xoff => false
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ -- ST sink
+ snk_in => data_flusher_sosi,
+ snk_out => data_flusher_siso,
+ -- ST source
+ src_in => ovr_data_dpmm_fifo_siso,
+ src_out => data_dpmm_fifo_sosi,
+ -- Enable flush
+ flush_en => flush_en
+ );
flush_en <= not data_log_fifo_siso.ready; -- We'll flush when the data log fifo is almost full.
@@ -190,47 +190,47 @@ begin
ovr_data_dpmm_fifo_siso.xon <= data_dpmm_fifo_siso.xon; -- leave xon as it is
u_data_dpmm_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_wr_data_w => g_dat_w,
- g_rd_data_w => c_word_w,
- g_use_ctrl => false,
- g_wr_fifo_size => c_dpmm_fifo_wr_depth
- )
- port map (
- wr_rst => rx_rst,
- wr_clk => rx_clk,
- rd_rst => mm_rst,
- rd_clk => mm_clk,
-
- snk_out => data_dpmm_fifo_siso,
- snk_in => data_dpmm_fifo_sosi,
-
- wr_usedw => OPEN,
- rd_usedw => data_dpmm_fifo_rd_usedw,
- rd_emp => OPEN,
-
- src_in => data_mm_siso,
- src_out => data_mm_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_wr_data_w => g_dat_w,
+ g_rd_data_w => c_word_w,
+ g_use_ctrl => false,
+ g_wr_fifo_size => c_dpmm_fifo_wr_depth
+ )
+ port map (
+ wr_rst => rx_rst,
+ wr_clk => rx_clk,
+ rd_rst => mm_rst,
+ rd_clk => mm_clk,
+
+ snk_out => data_dpmm_fifo_siso,
+ snk_in => data_dpmm_fifo_sosi,
+
+ wr_usedw => OPEN,
+ rd_usedw => data_dpmm_fifo_rd_usedw,
+ rd_emp => OPEN,
+
+ src_in => data_mm_siso,
+ src_out => data_mm_sosi
+ );
u_data_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => c_data_dpmm_fifo_rd_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- snk_out => data_mm_siso,
- snk_in => data_mm_sosi,
- usedw => data_dpmm_fifo_rd_usedw, -- used words from the clock crossing FIFO (NOT the logging FIFO)
-
- mm_rd => data_mm_rd,
- mm_rddata => data_mm_rd_data,
- mm_rdval => data_mm_rd_val,
- mm_usedw => data_mm_rd_usedw -- used words resized to 32 bits
- );
+ generic map(
+ g_fifo_size => c_data_dpmm_fifo_rd_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ snk_out => data_mm_siso,
+ snk_in => data_mm_sosi,
+ usedw => data_dpmm_fifo_rd_usedw, -- used words from the clock crossing FIFO (NOT the logging FIFO)
+
+ mm_rd => data_mm_rd,
+ mm_rddata => data_mm_rd_data,
+ mm_rdval => data_mm_rd_val,
+ mm_usedw => data_mm_rd_usedw -- used words resized to 32 bits
+ );
-- data read output to mm bus
data_miso.rddata(c_word_w - 1 downto 0) <= data_mm_rd_data;
@@ -240,24 +240,24 @@ begin
-- ============== MM control ========================================================================
u_ctrl_reg : entity work.mm_rx_logger_reg
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- rx_rst => rx_rst,
- rx_clk => rx_clk,
-
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
-
- rx_trig_on => mm_trig_on,
- rx_trig_one_shot => mm_trig_one_shot,
- rx_mm_ovr => mm_ovr,
- rx_log_en_evt => mm_trig_en_evt,
- rx_log_dis_evt => mm_trig_dis_evt,
- rx_trig_nof_words => mm_trig_nof_words,
- rx_trig_nof_logged_words => mm_trig_nof_logged_words,
- mm_data_usedw => data_mm_rd_usedw
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ rx_rst => rx_rst,
+ rx_clk => rx_clk,
+
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
+
+ rx_trig_on => mm_trig_on,
+ rx_trig_one_shot => mm_trig_one_shot,
+ rx_mm_ovr => mm_ovr,
+ rx_log_en_evt => mm_trig_en_evt,
+ rx_log_dis_evt => mm_trig_dis_evt,
+ rx_trig_nof_words => mm_trig_nof_words,
+ rx_trig_nof_logged_words => mm_trig_nof_logged_words,
+ mm_data_usedw => data_mm_rd_usedw
+ );
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
index fa51795373..06c69f465c 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_rx_logger_reg is
port (
@@ -48,17 +48,19 @@ entity mm_rx_logger_reg is
-- MM registers
mm_data_usedw : in std_logic_vector(31 downto 0)
- );
+ );
end mm_rx_logger_reg;
architecture rtl of mm_rx_logger_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 8,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(8),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 8,
+ init_sl => '0'
+ );
-- Registers in mm_clk domain
signal mm_trig_on : std_logic;
signal mm_trig_one_shot : std_logic;
@@ -128,7 +130,7 @@ begin
sla_out.rddata(c_word_w - 1 downto 0) <= mm_trig_nof_logged_words;
when 4 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_data_usedw;
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
end if;
end if;
@@ -152,59 +154,59 @@ begin
------------------------------------------------------------------------------
u_spulse_log_en_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_log_en_evt,
- in_busy => OPEN,
- out_rst => rx_rst,
- out_clk => rx_clk,
- out_pulse => rx_log_en_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_log_en_evt,
+ in_busy => OPEN,
+ out_rst => rx_rst,
+ out_clk => rx_clk,
+ out_pulse => rx_log_en_evt
+ );
u_spulse_log_dis_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_log_dis_evt,
- in_busy => OPEN,
- out_rst => rx_rst,
- out_clk => rx_clk,
- out_pulse => rx_log_dis_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_log_dis_evt,
+ in_busy => OPEN,
+ out_rst => rx_rst,
+ out_clk => rx_clk,
+ out_pulse => rx_log_dis_evt
+ );
u_async_mm_ovr : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_ovr,
- dout => rx_mm_ovr
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_ovr,
+ dout => rx_mm_ovr
+ );
u_async_mm_trig_on : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_trig_on,
- dout => rx_trig_on
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_trig_on,
+ dout => rx_trig_on
+ );
u_async_mm_trig_one_shot : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_trig_one_shot,
- dout => rx_trig_one_shot
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_trig_one_shot,
+ dout => rx_trig_one_shot
+ );
rx_trig_nof_words <= mm_trig_nof_words;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
index d1334a75b7..fbf5ad2cd7 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity mm_rx_logger_trig is
@@ -37,7 +37,7 @@ entity mm_rx_logger_trig is
log_nof_words : in std_logic_vector(c_word_w - 1 downto 0); -- unlimited (as long as there's no dis_evt) when zero (log FIFO keeps flushing then)
log_cnt : out std_logic_vector(c_word_w - 1 downto 0);
log_en : out std_logic
- );
+ );
end mm_rx_logger_trig;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
index 634096505c..7bc0ace661 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
@@ -21,19 +21,19 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mm_tx_framer is
generic(
g_technology : natural := c_tech_select_default;
g_dat_out_w : natural;
g_rd_fifo_depth : natural := 128
- );
+ );
port (
mm_clk : in std_logic;
mm_rst : in std_logic;
@@ -52,8 +52,8 @@ entity mm_tx_framer is
master_release : out std_logic; -- If used this instance will provide master release control for other instance(s)
slave_release : in std_logic := '0' -- If this instance is slave of another instance, the an MM write to the master's MM release will
- -- also release the frames in the slave(s)
- );
+ -- also release the frames in the slave(s)
+ );
end mm_tx_framer;
@@ -76,65 +76,65 @@ begin
master_release <= release;
u_data_dp_fifo_from_mm : entity dp_lib.dp_fifo_from_mm
- generic map (
- g_fifo_size => c_wr_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- ST soure connected to FIFO input
- src_out => mm_to_fifo_sosi,
- usedw => wr_usedw,
- -- Control for FIFO read access
- mm_wr => data_mosi.wr,
- mm_wrdata => data_mosi.wrdata(c_word_w - 1 downto 0),
- mm_usedw => OPEN,
- mm_availw => mm_availw
- );
+ generic map (
+ g_fifo_size => c_wr_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- ST soure connected to FIFO input
+ src_out => mm_to_fifo_sosi,
+ usedw => wr_usedw,
+ -- Control for FIFO read access
+ mm_wr => data_mosi.wr,
+ mm_wrdata => data_mosi.wrdata(c_word_w - 1 downto 0),
+ mm_usedw => OPEN,
+ mm_availw => mm_availw
+ );
u_mm_to_dp_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_wr_data_w => c_word_w,
- g_rd_data_w => g_dat_out_w,
- g_use_ctrl => false,
- g_wr_fifo_size => c_wr_fifo_depth
- )
- port map (
- wr_rst => mm_rst,
- wr_clk => mm_clk,
- rd_rst => tx_rst,
- rd_clk => tx_clk,
-
- snk_out => OPEN,
- snk_in => mm_to_fifo_sosi,
-
- wr_usedw => wr_usedw, -- Using wr_usedw because that side is in mm_clk domain
- rd_usedw => OPEN,
- rd_emp => OPEN,
-
- src_in => fifo_siso,
- src_out => fifo_out_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_wr_data_w => c_word_w,
+ g_rd_data_w => g_dat_out_w,
+ g_use_ctrl => false,
+ g_wr_fifo_size => c_wr_fifo_depth
+ )
+ port map (
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ rd_rst => tx_rst,
+ rd_clk => tx_clk,
+
+ snk_out => OPEN,
+ snk_in => mm_to_fifo_sosi,
+
+ wr_usedw => wr_usedw, -- Using wr_usedw because that side is in mm_clk domain
+ rd_usedw => OPEN,
+ rd_emp => OPEN,
+
+ src_in => fifo_siso,
+ src_out => fifo_out_sosi
+ );
data_out <= fifo_out_sosi.data(g_dat_out_w - 1 downto 0) when fifo_out_sosi.valid = '1' and (release = '1' or slave_release = '1') else data_out_default;
fifo_siso.ready <= release or slave_release;
u_reg : entity work.mm_tx_framer_reg
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- tx_clk => tx_clk,
- tx_rst => tx_rst,
+ tx_clk => tx_clk,
+ tx_rst => tx_rst,
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
- mm_availw => mm_availw,
- tx_release => release
+ mm_availw => mm_availw,
+ tx_release => release
- );
+ );
end str;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
index 04b094cc99..7e210578f9 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_tx_framer_reg is
port (
@@ -43,17 +43,19 @@ entity mm_tx_framer_reg is
-- MM registers
mm_availw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mm_tx_framer_reg;
architecture rtl of mm_tx_framer_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0'
+ );
-- Registers in mm_clk domain
signal mm_release : std_logic;
@@ -87,7 +89,7 @@ begin
-- Write Block Sync
when 1 =>
mm_release <= sla_in.wrdata(0);
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
-- Read access: get register value
@@ -98,7 +100,7 @@ begin
-- Read Block Sync
when 0 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_availw;
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
end if;
end if;
@@ -122,15 +124,15 @@ begin
------------------------------------------------------------------------------
u_async_release : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => tx_rst,
- clk => tx_clk,
- din => mm_release,
- dout => tx_release
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => tx_rst,
+ clk => tx_clk,
+ din => mm_release,
+ dout => tx_release
+ );
end rtl;
diff --git a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
index 5d3278f5c1..7f0910955e 100644
--- a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_diagnostics is
generic (
@@ -89,74 +89,74 @@ begin
snk_en_out <= snk_diag_en;
u_diagnostics: entity work.diagnostics
- generic map (
- g_dat_w => g_data_w,
- g_block_len => g_block_len,
- g_nof_streams => g_nof_streams,
- g_src_latency => g_src_latency,
- g_snk_latency => g_snk_latency,
- g_separate_clk => g_separate_clk
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- src_rst => src_rst,
- src_clk => src_clk,
-
- snk_rst => snk_rst,
- snk_clk => snk_clk,
-
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- snk_diag_en => snk_diag_en,
- snk_diag_md => snk_diag_md,
- snk_diag_res => snk_diag_res,
- snk_diag_res_val => snk_diag_res_val,
- snk_val_cnt => snk_val_cnt,
- snk_val_cnt_clr => snk_val_cnt_clr,
-
- src_out_arr => src_out_arr,
- src_in_arr => src_in_arr,
- src_diag_en => src_diag_en,
- src_diag_md => src_diag_md,
- src_val_cnt => src_val_cnt,
- src_val_cnt_clr => src_val_cnt_clr
- );
+ generic map (
+ g_dat_w => g_data_w,
+ g_block_len => g_block_len,
+ g_nof_streams => g_nof_streams,
+ g_src_latency => g_src_latency,
+ g_snk_latency => g_snk_latency,
+ g_separate_clk => g_separate_clk
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ src_rst => src_rst,
+ src_clk => src_clk,
+
+ snk_rst => snk_rst,
+ snk_clk => snk_clk,
+
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ snk_diag_en => snk_diag_en,
+ snk_diag_md => snk_diag_md,
+ snk_diag_res => snk_diag_res,
+ snk_diag_res_val => snk_diag_res_val,
+ snk_val_cnt => snk_val_cnt,
+ snk_val_cnt_clr => snk_val_cnt_clr,
+
+ src_out_arr => src_out_arr,
+ src_in_arr => src_in_arr,
+ src_diag_en => src_diag_en,
+ src_diag_md => src_diag_md,
+ src_val_cnt => src_val_cnt,
+ src_val_cnt_clr => src_val_cnt_clr
+ );
u_diagnostics_reg: entity work.diagnostics_reg
- generic map(
- g_nof_streams => g_nof_streams,
- g_separate_clk => g_separate_clk
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- src_rst => src_rst,
- src_clk => src_clk,
-
- snk_rst => snk_rst,
- snk_clk => snk_clk,
-
- sla_in => mm_mosi,
- sla_out => mm_miso,
-
- st_src_en => src_diag_en,
- st_src_md => src_diag_md,
- st_src_cnt => src_val_cnt,
- st_src_cnt_clr_evt => src_val_cnt_clr,
-
- st_snk_en => snk_diag_en,
- st_snk_md => snk_diag_md,
- st_snk_cnt => snk_val_cnt,
- st_snk_cnt_clr_evt => snk_val_cnt_clr,
- st_snk_diag_val => snk_diag_res_val,
- st_snk_diag_res => snk_diag_res
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_separate_clk => g_separate_clk
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ src_rst => src_rst,
+ src_clk => src_clk,
+
+ snk_rst => snk_rst,
+ snk_clk => snk_clk,
+
+ sla_in => mm_mosi,
+ sla_out => mm_miso,
+
+ st_src_en => src_diag_en,
+ st_src_md => src_diag_md,
+ st_src_cnt => src_val_cnt,
+ st_src_cnt_clr_evt => src_val_cnt_clr,
+
+ st_snk_en => snk_diag_en,
+ st_snk_md => snk_diag_md,
+ st_snk_cnt => snk_val_cnt,
+ st_snk_cnt_clr_evt => snk_val_cnt_clr,
+ st_snk_diag_val => snk_diag_res_val,
+ st_snk_diag_res => snk_diag_res
+ );
end str;
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
index b77389110e..dfd4811f0b 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
@@ -27,12 +27,12 @@
-- > run -a
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_unsigned.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_diagnostics is
end entity tb_diagnostics;
@@ -60,7 +60,7 @@ architecture str of tb_diagnostics is
signal src_diag_en : std_logic_vector(c_nof_streams - 1 downto 0);
signal src_val_cnt : t_slv_32_arr(c_nof_streams - 1 downto 0);
- begin
+begin
-- Run for 1us
@@ -109,7 +109,7 @@ architecture str of tb_diagnostics is
generic map (
g_dat_w => c_dat_w,
g_nof_streams => c_nof_streams
- )
+ )
port map (
rst => rst,
clk => clk,
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
index 384ec35117..8295686738 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use STD.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use STD.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
package tb_diagnostics_trnb_pkg is
@@ -34,32 +34,37 @@ package tb_diagnostics_trnb_pkg is
-- Global procedures
- procedure proc_diagnostics_trnb_tx_set_mode_prbs( signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_diagnostics_trnb_tx_set_mode_prbs (
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_diagnostics_trnb_rx_set_mode_prbs( signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_diagnostics_trnb_rx_set_mode_prbs (
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_diagnostics_trnb_tx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_diagnostics_trnb_tx_set_mode_counter (
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_diagnostics_trnb_rx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_diagnostics_trnb_rx_set_mode_counter (
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_diagnostics_trnb_run_and_verify(constant c_chip_id : in natural;
- constant c_nof_gx : in natural;
- constant c_nof_gx_mask : in integer;
- constant c_link_delay : in real;
- constant c_diag_on_interval : in real;
- constant c_diag_off_interval : in real;
- constant c_mm_clk_1us : in real;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_diagnostics_trnb_run_and_verify (
+ constant c_chip_id : in natural;
+ constant c_nof_gx : in natural;
+ constant c_nof_gx_mask : in integer;
+ constant c_link_delay : in real;
+ constant c_diag_on_interval : in real;
+ constant c_diag_off_interval : in real;
+ constant c_mm_clk_1us : in real;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi);
- -- Private procedures
+-- Private procedures
end tb_diagnostics_trnb_pkg;
@@ -71,14 +76,16 @@ package body tb_diagnostics_trnb_pkg is
-- PROCEDURE: Set all gx to default mode PRBS
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_tx_set_mode_prbs(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_tx_set_mode_prbs (
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr( 1, 0, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_tx_set_mode_prbs;
- procedure proc_diagnostics_trnb_rx_set_mode_prbs(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_rx_set_mode_prbs (
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr(20, 0, mm_clk, mm_mosi); -- set sink mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_rx_set_mode_prbs;
@@ -89,16 +96,18 @@ package body tb_diagnostics_trnb_pkg is
-- default mode PRBS
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_tx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_tx_set_mode_counter (
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr( 1, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_tx_set_mode_counter;
- procedure proc_diagnostics_trnb_rx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_rx_set_mode_counter (
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr(20, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_rx_set_mode_counter;
@@ -108,16 +117,17 @@ package body tb_diagnostics_trnb_pkg is
-- PROCEDURE: Run a diagnostic measurement and verify the result
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_run_and_verify(constant c_chip_id : in natural;
- constant c_nof_gx : in natural;
- constant c_nof_gx_mask : in integer;
- constant c_link_delay : in real;
- constant c_diag_on_interval : in real;
- constant c_diag_off_interval : in real;
- constant c_mm_clk_1us : in real;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_run_and_verify (
+ constant c_chip_id : in natural;
+ constant c_nof_gx : in natural;
+ constant c_nof_gx_mask : in integer;
+ constant c_link_delay : in real;
+ constant c_diag_on_interval : in real;
+ constant c_diag_off_interval : in real;
+ constant c_mm_clk_1us : in real;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
constant c_nof_gx_mask_slv : std_logic_vector(c_nof_gx - 1 downto 0) := TO_UVEC(c_nof_gx_mask, c_nof_gx);
variable v_diag_results_valid : std_logic_vector(c_nof_gx - 1 downto 0);
variable v_diag_results : std_logic_vector(c_nof_gx - 1 downto 0);
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
index 6bbfe25053..eabd3f538f 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_mm_tx_framer is
end tb_mm_tx_framer;
@@ -139,43 +139,43 @@ begin
-- simultaneously.
------------------------------------------------------------------------------
u_mm_tx_framer_mst: entity work.mm_tx_framer
- generic map(
- g_dat_out_w => 64
- )
- port map(
- tx_rst => tx_rst,
- tx_clk => tx_clk,
+ generic map(
+ g_dat_out_w => 64
+ )
+ port map(
+ tx_rst => tx_rst,
+ tx_clk => tx_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- ctrl_mosi => ctrl_mosi,
- ctrl_miso => ctrl_miso,
+ ctrl_mosi => ctrl_mosi,
+ ctrl_miso => ctrl_miso,
- data_mosi => mst_data_mosi,
- data_miso => mst_data_miso,
+ data_mosi => mst_data_mosi,
+ data_miso => mst_data_miso,
- data_out => mst_data_out,
- master_release => mst_release
- );
+ data_out => mst_data_out,
+ master_release => mst_release
+ );
u_mm_tx_framer_sla: entity work.mm_tx_framer
- generic map(
- g_dat_out_w => 32
- )
- port map(
- tx_rst => tx_rst,
- tx_clk => tx_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- data_mosi => sla_data_mosi,
- data_miso => sla_data_miso,
-
- data_out => sla_data_out,
- slave_release => mst_release
- );
+ generic map(
+ g_dat_out_w => 32
+ )
+ port map(
+ tx_rst => tx_rst,
+ tx_clk => tx_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ data_mosi => sla_data_mosi,
+ data_miso => sla_data_miso,
+
+ data_out => sla_data_out,
+ slave_release => mst_release
+ );
end tb;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index 937e8c43bb..8658801d80 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -38,22 +38,22 @@
-- used to target hardware (--unb # --fn # --bn #)
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, tech_tse_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use common_lib.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
entity mmm_unb1_dp_offload is
generic (
@@ -190,40 +190,40 @@ begin
eth1g_ram_mosi <= c_mem_mosi_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+ port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
- port map(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+ port map(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
- port map(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+ port map(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
u_mm_file_ram_diag_data_buffer : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
u_mm_file_reg_diag_data_buffer : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -247,10 +247,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -266,145 +266,145 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_dp_offload
- port map (
- clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- 125 MHz system clock
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
- dp_clk => i_dp_clk,
- cal_reconf_clk => OPEN,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tech_tse_byte_addr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_tx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_rx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buffer
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- 125 MHz system clock
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
+ dp_clk => i_dp_clk,
+ cal_reconf_clk => OPEN,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tech_tse_byte_addr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_tx_hdr_dat
+ coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
+ coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
+ coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_rx_hdr_dat
+ coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
+ coe_read_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
+ coe_write_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buffer
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
index 8586285c28..1c14784fff 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
@@ -27,19 +27,19 @@
-- instances via 1GbE (32b user interface)
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use diag_lib.diag_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use common_lib.common_field_pkg.all;
entity unb1_dp_offload is
generic (
@@ -52,7 +52,7 @@ entity unb1_dp_offload is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
+ -- CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
PPS : in std_logic;
WDI : out std_logic;
INTA : inout std_logic;
@@ -85,46 +85,60 @@ architecture str of unb1_dp_offload is
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize : natural := 100;
constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0', -- enable
+ '0', -- enable_sync
+ TO_UVEC(
+ c_bg_block_size,
+ c_diag_bg_samples_per_packet_w),
+ TO_UVEC(
+ c_bg_blocks_per_sync,
+ c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(
+ c_bg_gapsize,
+ c_diag_bg_gapsize_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(
+ c_bg_block_size-1,
+ c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(
+ 0,
+ c_diag_bg_bsn_init_w)
+ );
-- dp_offload_tx
constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(128) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(108) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(128) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(108) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1101" & "111111111100" & "1111" & "001111111";
@@ -210,28 +224,28 @@ begin
-- TX: Block generator
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "hex/counter_data_" & natural'image(c_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(c_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso
+ );
---------------------------------------------------------------------------------------
-- Use a FIFO when the source has no flow control
@@ -239,56 +253,56 @@ begin
---------------------------------------------------------------------------------------
gen_dp_fifo_sc : for i in 0 to c_nof_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_use_bsn => true,
- g_bsn_w => 64,
- g_use_sync => true,
- g_fifo_size => 100
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => block_gen_src_out_arr(i),
- snk_out => block_gen_src_in_arr(i),
-
- src_out => dp_offload_tx_snk_in_arr(i),
- src_in => dp_offload_tx_snk_out_arr(i)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_use_bsn => true,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_fifo_size => 100
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => block_gen_src_out_arr(i),
+ snk_out => block_gen_src_in_arr(i),
+
+ src_out => dp_offload_tx_snk_in_arr(i),
+ src_in => dp_offload_tx_snk_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_use_complex => false,
- g_nof_words_per_block => c_nof_words_per_block,
- g_nof_blocks_per_packet => c_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => dp_offload_tx_snk_out_arr,
-
- src_out_arr => dp_offload_tx_src_out_arr,
- src_in_arr => dp_offload_tx_src_in_arr,
-
- hdr_fields_in_arr => hdr_fields_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_use_complex => false,
+ g_nof_words_per_block => c_nof_words_per_block,
+ g_nof_blocks_per_packet => c_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => dp_offload_tx_src_out_arr,
+ src_in_arr => dp_offload_tx_src_in_arr,
+
+ hdr_fields_in_arr => hdr_fields_in_arr
+ );
gen_hdr_in_fields : for i in 0 to c_nof_streams - 1 generate
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000" & ID(7 downto 3) & RESIZE_UVEC(ID(2 downto 0), c_byte_w);
@@ -304,30 +318,30 @@ begin
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => hdr_fields_out_arr
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
);
gen_hdr_out_fields : for i in 0 to c_nof_streams - 1 generate
@@ -349,200 +363,200 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => 2 * c_bg_blocks_per_sync * (c_bg_block_size + c_bg_gapsize),
- g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync * c_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => 2 * c_bg_blocks_per_sync * (c_bg_block_size + c_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync * c_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sop,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sop,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb1_board : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => c_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_nof_streams,
- g_dp_clk_use_pll => false
- )
- port map (
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => OPEN,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
- udp_tx_siso_arr => dp_offload_tx_src_in_arr,
- udp_rx_sosi_arr => dp_offload_rx_snk_in_arr,
- udp_rx_siso_arr => dp_offload_rx_snk_out_arr,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- UniBoard FPGA pins
- CLK => '0',
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => c_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_nof_streams,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => OPEN,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
+ udp_tx_siso_arr => dp_offload_tx_src_in_arr,
+ udp_rx_sosi_arr => dp_offload_rx_snk_in_arr,
+ udp_rx_siso_arr => dp_offload_rx_snk_out_arr,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- UniBoard FPGA pins
+ CLK => '0',
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm_unb1_dp_offload : entity work.mmm_unb1_dp_offload
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams => c_nof_streams,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- dp_clk => dp_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
-
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams => c_nof_streams,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ dp_clk => dp_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso
+ );
end str;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
index 6b2673d5ee..a392f6297a 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
@@ -39,11 +39,11 @@
-- . run -a
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_dp_offload is
end tb_unb1_dp_offload;
@@ -98,6 +98,6 @@ begin
ETH_clk => eth_clk,
ETH_SGIN => eth_lpbk,
ETH_SGOUT => eth_lpbk
- );
+ );
end tb;
diff --git a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
index 18d0aa9b68..9526aa7d24 100644
--- a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
+++ b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
@@ -23,10 +23,10 @@
-- Description:
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_barrel_shift is
generic (
@@ -53,8 +53,10 @@ architecture str of dp_barrel_shift is
shift_out : std_logic_vector(ceil_log2(g_nof_streams) - 1 downto 0);
end record;
- constant c_reg_defaults : t_reg := ( (others => c_dp_sosi_rst),
- (others => '0') );
+ constant c_reg_defaults : t_reg := (
+ (others => c_dp_sosi_rst),
+ (others => '0')
+ );
signal r, nxt_r : t_reg := c_reg_defaults;
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 057eaddc33..ee440cb29c 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -64,11 +64,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_from_mm is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index 92774c9804..b29e331fc8 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -40,11 +40,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_from_mm_dc is
generic (
@@ -113,17 +113,17 @@ begin
-- if mm_start_pulse arrive one clock cycle early and mm_sync_hi arrives one
-- clock cycle late.
u_common_spulse_start_pulse : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len + 4
- )
- port map (
- in_rst => dp_rst,
- in_clk => dp_clk,
- in_pulse => start_pulse,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_pulse => mm_start_pulse
- );
+ generic map (
+ g_delay_len => c_meta_delay_len + 4
+ )
+ port map (
+ in_rst => dp_rst,
+ in_clk => dp_clk,
+ in_pulse => start_pulse,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_pulse => mm_start_pulse
+ );
-- The synchronous start_pulse and sync_in in the dp_clk domain cannot be
-- passed on via two separate common_spulse instances, because then they may
@@ -131,17 +131,17 @@ begin
-- dp_clk and mm_clk are asynchronous on HW. Therefore use mm_sync_level to
-- pass on sync_in.
u_common_spulse_sync : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => dp_rst,
- in_clk => dp_clk,
- in_pulse => sync_in,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_pulse => mm_sync_hi
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => dp_rst,
+ in_clk => dp_clk,
+ in_pulse => sync_in,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_pulse => mm_sync_hi
+ );
p_mm_sync : process(mm_clk)
begin
@@ -161,75 +161,75 @@ begin
mm_start_address <= TO_UINT(mm_start_address_slv);
u_common_async_slv_start_address : entity common_lib.common_async_slv
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => start_address_slv,
- dout => mm_start_address_slv
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => start_address_slv,
+ dout => mm_start_address_slv
+ );
u_common_async_slv_bsn : entity common_lib.common_async_slv
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => bsn_at_sync,
- dout => mm_bsn_at_sync
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => bsn_at_sync,
+ dout => mm_bsn_at_sync
+ );
u_dp_fifo_fill_eop : entity work.dp_fifo_fill_eop
- generic map (
- g_use_dual_clock => true,
- g_data_w => c_word_w,
- g_bsn_w => g_bsn_w,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_fill => c_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- wr_rst => mm_rst,
- wr_clk => mm_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
- -- ST sink
- snk_in => mm_fifo_sosi,
- snk_out => mm_fifo_siso,
- -- ST source
- src_out => dp_out_sosi,
- src_in => dp_out_siso
- );
+ generic map (
+ g_use_dual_clock => true,
+ g_data_w => c_word_w,
+ g_bsn_w => g_bsn_w,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_fill => c_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+ -- ST sink
+ snk_in => mm_fifo_sosi,
+ snk_out => mm_fifo_siso,
+ -- ST source
+ src_out => dp_out_sosi,
+ src_in => dp_out_siso
+ );
u_dp_block_from_mm : entity work.dp_block_from_mm
- generic map (
- g_user_size => g_user_size,
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data,
- g_word_w => g_word_w,
- g_reverse_word_order => g_reverse_word_order,
- g_bsn_w => g_bsn_w,
- g_bsn_incr_enable => g_bsn_incr_enable
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
-
- start_pulse => mm_start_pulse,
- sync_in => mm_sync,
- bsn_at_sync => mm_bsn_at_sync,
- start_address => mm_start_address,
- mm_done => mm_done, -- = mm_fifo_sosi.eop
- mm_mosi => mm_mosi,
- mm_miso => mm_miso,
- out_sosi => mm_fifo_sosi,
- out_siso => mm_fifo_siso
- );
+ generic map (
+ g_user_size => g_user_size,
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data,
+ g_word_w => g_word_w,
+ g_reverse_word_order => g_reverse_word_order,
+ g_bsn_w => g_bsn_w,
+ g_bsn_incr_enable => g_bsn_incr_enable
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+
+ start_pulse => mm_start_pulse,
+ sync_in => mm_sync,
+ bsn_at_sync => mm_bsn_at_sync,
+ start_address => mm_start_address,
+ mm_done => mm_done, -- = mm_fifo_sosi.eop
+ mm_mosi => mm_mosi,
+ mm_miso => mm_miso,
+ out_sosi => mm_fifo_sosi,
+ out_siso => mm_fifo_siso
+ );
-- Wire output
out_sop <= dp_out_sosi.sop;
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen.vhd b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
index b5df7fc890..c9fc9763ce 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
@@ -64,10 +64,10 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_gen is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
index 8d2d582a9e..27dd9c6674 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
@@ -140,10 +140,10 @@
-- allow for a fractional amount of blocks per sync period.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_gen_valid_arr is
generic (
@@ -171,15 +171,15 @@ end dp_block_gen_valid_arr;
architecture rtl of dp_block_gen_valid_arr is
-- Check consistancy of the parameters, the function return value is void, because always true or abort due to failure
- function parameter_asserts(g_check_input_sync : boolean; g_nof_pages_bsn : natural) return boolean is
+ function parameter_asserts (g_check_input_sync : boolean; g_nof_pages_bsn : natural) return boolean is
begin
if g_check_input_sync = true then
assert g_nof_pages_bsn = 0 report "When g_check_input_sync=TRUE then g_nof_pages_bsn must be 0." severity FAILURE;
- -- because snk_in.sync and snk_in.bsn are then already aligned with the first snk_in.valid
+ -- because snk_in.sync and snk_in.bsn are then already aligned with the first snk_in.valid
end if;
if g_nof_pages_bsn > 0 then
assert g_check_input_sync = false report "When g_nof_pages_bsn>0 then g_check_input_sync must be false." severity FAILURE;
- -- because snk_in.sync and snk_in.bsn are then NOT aligned with the first snk_in.valid
+ -- because snk_in.sync and snk_in.bsn are then NOT aligned with the first snk_in.valid
end if;
return true;
end parameter_asserts;
@@ -230,17 +230,17 @@ begin
in_sync_wr_en <= (others => snk_in.sync);
u_paged_bsn : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_bsn_w,
- g_nof_pages => g_nof_pages_bsn
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => in_sync_wr_en,
- wr_dat => snk_in.bsn,
- out_dat => in_bsn_buffer
- );
+ generic map (
+ g_data_w => c_dp_stream_bsn_w,
+ g_nof_pages => g_nof_pages_bsn
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => in_sync_wr_en,
+ wr_dat => snk_in.bsn,
+ out_dat => in_bsn_buffer
+ );
p_snk_in : process(snk_in, in_bsn_buffer)
begin
@@ -336,18 +336,18 @@ begin
use_global_bsn : if g_restore_global_bsn = true generate
u_dp_bsn_restore_global : entity work.dp_bsn_restore_global
- generic map (
- g_bsn_w => c_dp_stream_bsn_w,
- g_pipeline => 0 -- pipeline registering is done via nxt_src_out_arr
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => nxt_r.reg_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_pipeline => 0 -- pipeline registering is done via nxt_src_out_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => nxt_r.reg_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end generate;
-- Combine input data with the same out_put info and output ctrl for all streams
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
index 46e39a01fb..45436704e8 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
@@ -72,10 +72,10 @@
-- an input block stream.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape is
generic (
@@ -101,7 +101,7 @@ end dp_block_reshape;
architecture str of dp_block_reshape is
constant c_nof_counters : natural := 2; -- counter [0] is used for block reshape and valid index,
- -- counter [1] is only used for sop_index
+ -- counter [1] is only used for sop_index
constant c_nof_block_per_sync : natural := sel_a_b(g_input_nof_data_per_sync > g_reshape_nof_data_per_blk,
g_input_nof_data_per_sync / g_reshape_nof_data_per_blk, 1);
@@ -115,26 +115,26 @@ architecture str of dp_block_reshape is
begin
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => c_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => input_src_out,
- src_in => src_in,
-
- count_src_out_arr => cnt_sosi_arr
- );
+ generic map (
+ g_nof_counters => c_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => input_src_out,
+ src_in => src_in,
+
+ count_src_out_arr => cnt_sosi_arr
+ );
src_index_arr(1) <= TO_UINT(cnt_sosi_arr(1).data); -- sop index
src_index_arr(0) <= TO_UINT(cnt_sosi_arr(0).data); -- valid index
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
index d5af701f4c..1f37667739 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
@@ -33,10 +33,10 @@
--
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape_arr is
generic (
@@ -129,23 +129,23 @@ begin
-- Instantiate dp_block_reshape per stream
gen_streams : for I in 0 to g_nof_streams - 1 generate
u_block_reshape : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => g_input_nof_data_per_sync,
- g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => in_sosi_arr(I),
- snk_out => in_siso_arr(I),
-
- src_out => out_sosi_arr(I),
- src_in => out_siso_arr(I),
- src_index_arr => out_index_2arr_2(I)
- );
+ generic map (
+ g_input_nof_data_per_sync => g_input_nof_data_per_sync,
+ g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => in_sosi_arr(I),
+ snk_out => in_siso_arr(I),
+
+ src_out => out_sosi_arr(I),
+ src_in => out_siso_arr(I),
+ src_index_arr => out_index_2arr_2(I)
+ );
end generate;
-- Wire index arr
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
index ca7a6337cd..36894decd4 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
@@ -65,10 +65,10 @@
-- dp_sync_insert.vhd.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape_sync is
generic (
@@ -108,8 +108,8 @@ architecture str of dp_block_reshape_sync is
constant c_nof_counters : natural := sel_a_b(c_nof_output_sync_per_input_sync > 1, 3, 2);
constant c_range_start : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (others => 0);
constant c_range_stop : t_nat_natural_arr(c_nof_counters - 1 downto 0) := sel_a_b(c_nof_output_sync_per_input_sync > 1,
- (c_nof_output_sync_per_input_sync, g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk),
- (g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk));
+ (c_nof_output_sync_per_input_sync, g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk),
+ (g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk));
constant c_range_step : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (others => 1);
signal cnt_sosi_arr : t_dp_sosi_arr(c_nof_counters - 1 downto 0);
@@ -135,26 +135,26 @@ architecture str of dp_block_reshape_sync is
begin
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => c_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => input_sosi,
- src_in => input_siso,
-
- count_src_out_arr => cnt_sosi_arr
- );
+ generic map (
+ g_nof_counters => c_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => input_sosi,
+ src_in => input_siso,
+
+ count_src_out_arr => cnt_sosi_arr
+ );
gen_sync_index : if c_nof_output_sync_per_input_sync > 1 generate
sync_index <= TO_UINT(cnt_sosi_arr(2).data);
diff --git a/libraries/base/dp/src/vhdl/dp_block_resize.vhd b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
index 1ffc044acc..1db28628cf 100644
--- a/libraries/base/dp/src/vhdl/dp_block_resize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Author: Eric Kooistra, 16 Mar 2018
-- Purpose:
@@ -63,8 +63,8 @@ end dp_block_resize;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture rtl of dp_block_resize is
@@ -130,18 +130,18 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_select.vhd b/libraries/base/dp/src/vhdl/dp_block_select.vhd
index 0682c23741..9728eca6b8 100644
--- a/libraries/base/dp/src/vhdl/dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_select.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author: Eric Kooistra, 14 Dec 2018
-- Purpose:
@@ -75,8 +75,8 @@ end dp_block_select;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture rtl of dp_block_select is
@@ -144,18 +144,18 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 530ee3a465..e046775bb1 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -26,11 +26,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_to_mm is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
index 983aba1db1..0c436734cf 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
@@ -61,11 +61,11 @@
-- =====================================================================
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_bsn_at_sync is
generic (
@@ -94,11 +94,13 @@ architecture rtl of dp_block_validate_bsn_at_sync is
constant c_nof_regs : natural := 3;
constant c_clear_adr : natural := c_nof_regs - 1;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs, -- total counter + discarded counter
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs, -- total counter + discarded counter
+ init_sl => '0'
+ );
-- Registers in st_clk domain
signal count_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
@@ -134,61 +136,61 @@ begin
-- discarded counter
u_discarded_counter : entity common_lib.common_counter
- generic map (
- g_width => c_word_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => c_word_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_discarded_en,
- count => cnt_discarded
- );
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_discarded_en,
+ count => cnt_discarded
+ );
-- sync counter
u_blk_counter : entity common_lib.common_counter
- generic map (
- g_width => c_word_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => c_word_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => in_sosi.sync,
- count => cnt_sync
- );
+ cnt_clr => cnt_clr,
+ cnt_en => in_sosi.sync,
+ count => cnt_sync
+ );
-- Register mapping
count_reg( c_word_w - 1 downto 0 ) <= cnt_discarded;
count_reg(2 * c_word_w - 1 downto c_word_w ) <= cnt_sync;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => count_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => count_reg, -- read only
+ out_reg => open -- no write
+ );
-- Process to check the bsn at sync. It captures the bsn at the sync of bs_sosi. Then compares that bsn to
-- the bsn at sync of in_sosi. If they are unequal all packets during that sync period with in_sosi.channel
@@ -258,16 +260,16 @@ begin
end process;
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => block_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => block_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
index 505401f8be..66e3e3469f 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
@@ -32,11 +32,11 @@
-- Remarks:
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_channel is
generic (
@@ -67,16 +67,16 @@ begin
assert g_mode = "=" or g_mode = "<" or g_mode = ">" report "g_mode must be one of three options: '=', '<' or '>'" severity ERROR;
gen_equal : if g_mode = "=" generate -- remove all blocks with ch = remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) = unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) = unsigned(remove_channel) else '0';
end generate;
gen_smaller : if g_mode = "<" generate -- remove all blocks with ch < remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) < unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) < unsigned(remove_channel) else '0';
end generate;
gen_larger : if g_mode = ">" generate -- remove all blocks with ch > remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) > unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) > unsigned(remove_channel) else '0';
end generate;
p_dp_clk : process(dp_rst, dp_clk)
@@ -106,29 +106,29 @@ begin
end process;
u_pipe_remove : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => remove_sosi,
- -- ST source
- src_out => out_remove_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => remove_sosi,
+ -- ST source
+ src_out => out_remove_sosi
+ );
u_pipe_keep : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => keep_sosi,
- -- ST source
- src_out => out_keep_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => keep_sosi,
+ -- ST source
+ src_out => out_keep_sosi
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
index e56d4b1444..8670de86b3 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
@@ -72,11 +72,11 @@
-- ====================================================================================
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_err is
generic (
@@ -127,11 +127,13 @@ architecture rtl of dp_block_validate_err is
type t_cnt_err_arr is array (integer range <>) of std_logic_vector(g_cnt_w - 1 downto 0);
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0'
+ );
-- Registers in st_clk domain
signal ref_sync_reg : std_logic := '0';
@@ -191,39 +193,22 @@ begin
-- block counter
cnt_blk_en <= cnt_this_eop;
u_blk_counter : entity common_lib.common_counter
- generic map (
- g_width => g_blk_cnt_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- cnt_clr => cnt_clr,
- cnt_en => cnt_blk_en,
- count => cnt_blk
- );
+ generic map (
+ g_width => g_blk_cnt_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_blk_en,
+ count => cnt_blk
+ );
-- discarded block counter
cnt_discarded_en <= cnt_this_eop when TO_UINT(snk_in.err(g_nof_err_counts - 1 downto 0)) > 0 else '0';
u_discarded_counter : entity common_lib.common_counter
- generic map (
- g_width => g_cnt_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- cnt_clr => cnt_clr,
- cnt_en => cnt_discarded_en,
- count => cnt_discarded
- );
-
- -- error counters
- gen_err_counters : for I in 0 to g_nof_err_counts - 1 generate
- cnt_err_en_arr(I) <= cnt_this_eop and snk_in.err(I);
- u_blk_counter : entity common_lib.common_counter
generic map (
g_width => g_cnt_w,
g_clip => true
@@ -233,9 +218,26 @@ begin
clk => dp_clk,
cnt_clr => cnt_clr,
- cnt_en => cnt_err_en_arr(I),
- count => cnt_err_arr(I)
+ cnt_en => cnt_discarded_en,
+ count => cnt_discarded
);
+
+ -- error counters
+ gen_err_counters : for I in 0 to g_nof_err_counts - 1 generate
+ cnt_err_en_arr(I) <= cnt_this_eop and snk_in.err(I);
+ u_blk_counter : entity common_lib.common_counter
+ generic map (
+ g_width => g_cnt_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_err_en_arr(I),
+ count => cnt_err_arr(I)
+ );
end generate;
-- Hold counter values at ref_sync_reg to have stable values for MM read for comparision between nodes
@@ -272,71 +274,71 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => count_reg, -- read only
- out_reg => open -- no write
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => count_reg, -- read only
+ out_reg => open -- no write
+ );
u_fifo_fill_eop : entity work.dp_fifo_fill_eop
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_max_block_size,
- g_fifo_size => g_fifo_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => block_siso,
- src_out => block_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_max_block_size,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => block_siso,
+ src_out => block_sosi
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => block_siso,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => block_sosi_piped
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => block_siso,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => block_sosi_piped
+ );
p_dp_clk : process(dp_rst, dp_clk)
begin
@@ -352,19 +354,19 @@ begin
err_ok <= not vector_or(snk_in.err(g_nof_err_counts - 1 downto 0)) when snk_in.eop = '1' else err_ok_reg;
u_fifo_err_ok : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => 1,
- g_nof_words => c_nof_err_ok
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_dat(0) => err_ok,
- wr_req => snk_in.eop,
- rd_req => block_sosi.sop,
- rd_dat(0) => fifo_err_ok,
- rd_val => fifo_err_ok_val
- );
+ generic map (
+ g_dat_w => 1,
+ g_nof_words => c_nof_err_ok
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_dat(0) => err_ok,
+ wr_req => snk_in.eop,
+ rd_req => block_sosi.sop,
+ rd_dat(0) => fifo_err_ok,
+ rd_val => fifo_err_ok_val
+ );
out_valid <= fifo_err_ok when fifo_err_ok_val = '1' else out_valid_reg;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
index cd6316d9a2..f59123d64f 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
@@ -43,8 +43,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_block_validate_length is
generic (
@@ -114,18 +114,18 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
index 7f12910cd4..2684b5c169 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Future note:
-- The dp_bsn_align aligns at BSN level. In retrospect it is probably
@@ -237,67 +237,67 @@ begin
-- control user input enable updates to not occur during a block
u_in_en_new : entity common_lib.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_en_evt,
- switch_low => in_en_ack,
- out_level => in_en_new
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_en_evt,
+ switch_low => in_en_ack,
+ out_level => in_en_new
+ );
-- block reference
u_block_gen : entity work.dp_block_gen
- generic map (
- g_nof_data => g_block_size,
- g_empty => 0,
- g_channel => 0,
- g_error => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming source
- src_in => blk_siso,
- src_out => blk_sosi,
- -- MM control
- en => blk_en
- );
+ generic map (
+ g_nof_data => g_block_size,
+ g_empty => 0,
+ g_channel => 0,
+ g_error => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming source
+ src_in => blk_siso,
+ src_out => blk_sosi,
+ -- MM control
+ en => blk_en
+ );
-- Hold the sink input to be able to register the source output
u_block_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => blk_siso, -- wired blk_siso = hold_blk_in
- snk_in => blk_sosi,
- -- ST source
- src_in => hold_blk_in,
- next_src_out => next_blk_buf,
- pend_src_out => OPEN,
- src_out_reg => r.blk_buf
- );
-
- gen_inputs : for I in g_nof_input - 1 downto 0 generate
- u_hold : entity work.dp_hold_input
port map (
rst => rst,
clk => clk,
-- ST sink
- snk_out => OPEN,
- snk_in => snk_in_arr(I),
+ snk_out => blk_siso, -- wired blk_siso = hold_blk_in
+ snk_in => blk_sosi,
-- ST source
- src_in => hold_src_in_arr(I),
- next_src_out => next_src_buf_arr(I),
- pend_src_out => pend_src_buf_arr(I),
- src_out_reg => r.src_buf_arr(I)
+ src_in => hold_blk_in,
+ next_src_out => next_blk_buf,
+ pend_src_out => OPEN,
+ src_out_reg => r.blk_buf
);
+
+ gen_inputs : for I in g_nof_input - 1 downto 0 generate
+ u_hold : entity work.dp_hold_input
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => hold_src_in_arr(I),
+ next_src_out => next_src_buf_arr(I),
+ pend_src_out => pend_src_buf_arr(I),
+ src_out_reg => r.src_buf_arr(I)
+ );
end generate;
-- This is not Erlang or Haskell, but that does not mean that we can not do some functional programming in VHDL as well.
@@ -328,38 +328,38 @@ begin
-- Use tree instead of folding to ease timing closure:
-- pend_bsn_max <= func_dp_stream_arr_bsn_max(pend_src_buf_arr, r.in_en_arr, c_bsn_align_w);
u_pend_bsn_max : entity common_lib.common_operation_tree
- generic map (
- g_operation => "MAX",
- g_representation => "UNSIGNED",
- g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
- g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
- g_nof_inputs => g_nof_input,
- g_dat_w => c_bsn_align_w
- )
- port map (
- clk => clk,
- in_data_vec => pend_bsn_vec,
- in_en_vec => r.in_en_arr,
- result => pend_bsn_max
- );
+ generic map (
+ g_operation => "MAX",
+ g_representation => "UNSIGNED",
+ g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
+ g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_nof_inputs => g_nof_input,
+ g_dat_w => c_bsn_align_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => pend_bsn_vec,
+ in_en_vec => r.in_en_arr,
+ result => pend_bsn_max
+ );
-- Use tree instead of folding to ease timing closure:
-- pend_bsn_min <= func_dp_stream_arr_bsn_min(pend_src_buf_arr, r.in_en_arr, c_bsn_align_w);
u_pend_bsn_min : entity common_lib.common_operation_tree
- generic map (
- g_operation => "MIN",
- g_representation => "UNSIGNED",
- g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
- g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
- g_nof_inputs => g_nof_input,
- g_dat_w => c_bsn_align_w
- )
- port map (
- clk => clk,
- in_data_vec => pend_bsn_vec,
- in_en_vec => r.in_en_arr,
- result => pend_bsn_min
- );
+ generic map (
+ g_operation => "MIN",
+ g_representation => "UNSIGNED",
+ g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
+ g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_nof_inputs => g_nof_input,
+ g_dat_w => c_bsn_align_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => pend_bsn_vec,
+ in_en_vec => r.in_en_arr,
+ result => pend_bsn_min
+ );
-- Hold input registers
nxt_r.blk_buf <= next_blk_buf;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
index f33ad05275..ed6c533b6d 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
@@ -41,9 +41,9 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_align_reg is
generic (
@@ -71,11 +71,13 @@ end dp_bsn_align_reg;
architecture str of dp_bsn_align_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_input),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => g_nof_input,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_input),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => g_nof_input,
+ init_sl => '0'
+ );
-- FUNCTION array_init(init : NATURAL; nof, width : NATURAL) RETURN STD_LOGIC_VECTOR; -- useful to init an unconstrained std_logic_vector with repetitive content
constant c_reg_init : std_logic_vector(g_nof_input * c_word_w - 1 downto 0) := array_init(1, g_nof_input, c_word_w);
@@ -87,32 +89,32 @@ architecture str of dp_bsn_align_reg is
begin
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg,
- g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
-
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => OPEN,
- in_new => OPEN,
- in_reg => out_en_arr_reg, -- read
- out_reg => out_en_arr_reg, -- write
- out_new => out_en_evt
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg,
+ g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => OPEN,
+ in_new => OPEN,
+ in_reg => out_en_arr_reg, -- read
+ out_reg => out_en_arr_reg, -- write
+ out_new => out_en_evt
+ );
gen_out_arr : for I in 0 to g_nof_input - 1 generate
out_en_arr(I) <= out_en_arr_reg(I * c_word_w);
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index f2b7d843e4..64a92b68ee 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -48,11 +48,11 @@
-- robust.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_align_v2 is
@@ -99,11 +99,13 @@ architecture rtl of dp_bsn_align_v2 is
constant c_buffer_nof_blocks : natural := true_log_pow2(1 + g_nof_aligners_max * g_bsn_latency_max);
constant c_ram_size : natural := c_buffer_nof_blocks * g_block_size;
- constant c_ram_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_size),
- dat_w => g_data_w,
- nof_dat => c_ram_size,
- init_sl => '0');
+ constant c_ram_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_size),
+ dat_w => g_data_w,
+ nof_dat => c_ram_size,
+ init_sl => '0'
+ );
-- Use +1 to ensure that g_block_size that is power of 2 also fits in c_block_size_slv
constant c_block_size_w : natural := ceil_log2(g_block_size + 1);
@@ -158,27 +160,31 @@ architecture rtl of dp_bsn_align_v2 is
out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
end record;
- constant c_reg_rst : t_reg := (0,
- (others => c_mem_copi_rst),
- (others => (others => '0')),
- (others => '0'),
- (others => '0'),
- (others => (others => '0')),
- c_dp_sosi_rst,
- c_dp_sosi_rst,
- 0,
- (others => '0'),
- c_mem_copi_rst,
- (others => c_mem_cipo_rst),
- (others => '0'),
- (others => (others => '0')),
- (others => '0'));
-
- constant c_comb_rst : t_comb := (c_dp_sosi_rst,
- (others => '0'),
- (others => '0'),
- (others => '0'),
- (others => c_dp_sosi_rst));
+ constant c_reg_rst : t_reg := (
+ 0,
+ (others => c_mem_copi_rst),
+ (others => (others => '0')),
+ (others => '0'),
+ (others => '0'),
+ (others => (others => '0')),
+ c_dp_sosi_rst,
+ c_dp_sosi_rst,
+ 0,
+ (others => '0'),
+ c_mem_copi_rst,
+ (others => c_mem_cipo_rst),
+ (others => '0'),
+ (others => (others => '0')),
+ (others => '0')
+ );
+
+ constant c_comb_rst : t_comb := (
+ c_dp_sosi_rst,
+ (others => '0'),
+ (others => '0'),
+ (others => '0'),
+ (others => c_dp_sosi_rst)
+ );
-- State registers for p_comb
signal r : t_reg;
@@ -369,7 +375,7 @@ begin
-- . pass on input data from the buffer
w.out_sosi_arr := rd_sosi_arr; -- = v.fill_cipo_arr in streaming format, contains the
- -- input data from the buffer or replacement data
+ -- input data from the buffer or replacement data
if rd_sosi_arr(0).sop = '1' then
-- . at sop pass on input info from r.dp_sosi to all streams in out_sosi_arr
w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.dp_sosi.sync, "SYNC");
@@ -388,8 +394,8 @@ begin
-- . until next sop pass on BSN to all streams, to ease view in wave window
w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.out_bsn, "BSN");
for I in 0 to g_nof_streams - 1 loop
- -- . until next sop pass on channel bit 0 per stream, to ease view in wave window
- w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(r.out_channel_arr(I));
+ -- . until next sop pass on channel bit 0 per stream, to ease view in wave window
+ w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(r.out_channel_arr(I));
end loop;
end if;
@@ -415,20 +421,20 @@ begin
gen_data_buffer : for I in 0 to g_nof_streams - 1 generate
u_data_buffer : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_buf
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_en => r.wr_copi_arr(I).wr,
- wr_adr => r.wr_copi_arr(I).address(c_ram_buf.adr_w - 1 downto 0),
- wr_dat => r.wr_copi_arr(I).wrdata(c_ram_buf.dat_w - 1 downto 0),
- rd_en => rd_copi.rd,
- rd_adr => rd_copi.address(c_ram_buf.adr_w - 1 downto 0),
- rd_dat => rd_cipo_arr(I).rddata(c_ram_buf.dat_w - 1 downto 0),
- rd_val => rd_cipo_arr(I).rdval
- );
+ generic map (
+ g_ram => c_ram_buf
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_en => r.wr_copi_arr(I).wr,
+ wr_adr => r.wr_copi_arr(I).address(c_ram_buf.adr_w - 1 downto 0),
+ wr_dat => r.wr_copi_arr(I).wrdata(c_ram_buf.dat_w - 1 downto 0),
+ rd_en => rd_copi.rd,
+ rd_adr => rd_copi.address(c_ram_buf.adr_w - 1 downto 0),
+ rd_dat => rd_cipo_arr(I).rddata(c_ram_buf.dat_w - 1 downto 0),
+ rd_val => rd_cipo_arr(I).rdval
+ );
end generate;
------------------------------------------------------------------------------
@@ -438,26 +444,26 @@ begin
gen_streaming_output : if not g_use_mm_output generate
gen_mm_to_dp : for I in 0 to g_nof_streams - 1 generate
u_mm_to_dp: entity work.dp_block_from_mm
- generic map (
- g_user_size => 1,
- g_data_size => 1,
- g_step_size => 1,
- g_nof_data => g_block_size,
- g_word_w => g_data_w,
- g_mm_rd_latency => g_rd_latency,
- g_reverse_word_order => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- start_pulse => r.mm_sosi.sop,
- start_address => 0,
- mm_done => dp_done_arr(I),
- mm_mosi => dp_copi_arr(I),
- mm_miso => nxt_r.fill_cipo_arr(I),
- out_sosi => rd_sosi_arr(I),
- out_siso => c_dp_siso_rdy
- );
+ generic map (
+ g_user_size => 1,
+ g_data_size => 1,
+ g_step_size => 1,
+ g_nof_data => g_block_size,
+ g_word_w => g_data_w,
+ g_mm_rd_latency => g_rd_latency,
+ g_reverse_word_order => false
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ start_pulse => r.mm_sosi.sop,
+ start_address => 0,
+ mm_done => dp_done_arr(I),
+ mm_mosi => dp_copi_arr(I),
+ mm_miso => nxt_r.fill_cipo_arr(I),
+ out_sosi => rd_sosi_arr(I),
+ out_siso => c_dp_siso_rdy
+ );
end generate;
-- Use dp_copi_arr(0) to read same addresses in parallel for all streams
@@ -470,16 +476,16 @@ begin
------------------------------------------------------------------------------
gen_cnt_replace : for I in 0 to g_nof_streams - 1 generate
u_cnt_replace : entity common_lib.common_counter
- generic map (
- g_width => c_word_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_clr => in_sosi_arr_p(0).sync,
- cnt_en => r.replace_cnt_en_arr(I),
- count => replace_cnt_arr(I)
- );
+ generic map (
+ g_width => c_word_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_clr => in_sosi_arr_p(0).sync,
+ cnt_en => r.replace_cnt_en_arr(I),
+ count => replace_cnt_arr(I)
+ );
end generate;
nxt_hold_replace_cnt_arr <= replace_cnt_arr when in_sosi_arr_p(0).sync = '1' else hold_replace_cnt_arr;
@@ -492,35 +498,35 @@ begin
-- . input streams
u_in_sosi_arr_p : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_input -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_out_arr => in_sosi_arr_p
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => g_pipeline_input -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_out_arr => in_sosi_arr_p
+ );
-- . read RAM
rd_copi <= nxt_r.rd_copi when g_rd_latency = 1 else r.rd_copi;
-- . output streams
u_out_sosi_arr_p : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => comb_out_sosi_arr,
- -- ST source
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => g_pipeline_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => comb_out_sosi_arr,
+ -- ST source
+ src_out_arr => out_sosi_arr
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
index 3b3ca696b9..3fe36bdb80 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : Delay the input sync and BSN so they remain aligned to the data
-- path processing.
@@ -113,18 +113,18 @@ begin
-- Hold the in_sync during the block until the in_eop
u_hold_sync : entity common_lib.common_switch
- generic map (
- g_priority_lo => false, -- in_sync has priority over in_eop, because they may occur simultaneously
- g_or_high => false, -- hold_sync goes high after in_sync
- g_and_low => false -- hold_sync goes low after in_eop
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_sync,
- switch_low => in_eop,
- out_level => hold_sync
- );
+ generic map (
+ g_priority_lo => false, -- in_sync has priority over in_eop, because they may occur simultaneously
+ g_or_high => false, -- hold_sync goes high after in_sync
+ g_and_low => false -- hold_sync goes low after in_eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_sync,
+ switch_low => in_eop,
+ out_level => hold_sync
+ );
-- Delay line for in_sync and in_bsn at block level
sync_dly(0) <= hold_sync;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
index 93f37c4079..5ba1d8857a 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
@@ -41,10 +41,10 @@
-- valid remains active until an acknowledge by ready)
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_monitor is
@@ -167,33 +167,33 @@ begin
nof_valid <= INCR_UVEC(cnt_valid, 1); -- +1 because the valid at the sync also counts
u_sync_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_sync_timeout_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sync_timeout_n,
- count => sync_timeout_cnt
- );
+ generic map (
+ g_width => c_sync_timeout_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sync_timeout_n,
+ count => sync_timeout_cnt
+ );
sync_timeout_n <= not nxt_sync_timeout;
nxt_sync_timeout <= '1' when unsigned(sync_timeout_cnt) >= g_sync_timeout else '0';
u_sync_timeout_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_invert => false,
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => sync_timeout,
- out_evt => sync_timeout_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_invert => false,
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => sync_timeout,
+ out_evt => sync_timeout_revt
+ );
p_clk : process(rst, clk)
begin
@@ -248,24 +248,24 @@ begin
nxt_xon <= in_siso.xon;
u_ready_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => ready,
- r_stable => ready_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => ready,
+ r_stable => ready_stable,
+ r_stable_ack => sync
+ );
u_xon_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => xon,
- r_stable => xon_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => xon,
+ r_stable => xon_stable,
+ r_stable_ack => sync
+ );
-- Sample the BSN, because BSN is only valid during sop.
nxt_current_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else i_current_bsn;
@@ -292,52 +292,52 @@ begin
end generate;
u_cnt_sop : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sop,
- count => cnt_sop
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sop,
+ count => cnt_sop
+ );
u_nof_err : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => err,
- count => cnt_err
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => err,
+ count => cnt_err
+ );
u_cnt_valid : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_valid_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => valid,
- count => cnt_valid
- );
+ generic map (
+ g_width => c_cnt_valid_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => valid,
+ count => cnt_valid
+ );
u_cnt_cycle : entity common_lib.common_counter
- generic map (
- g_width => c_word_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => in_sosi.sop,
- cnt_en => '1',
- count => cnt_cycle
- );
+ generic map (
+ g_width => c_word_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => in_sosi.sop,
+ cnt_en => '1',
+ count => cnt_cycle
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
index 39e9921aeb..97a42fa249 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
@@ -47,9 +47,9 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_monitor_reg is
generic (
@@ -86,11 +86,13 @@ end dp_bsn_monitor_reg;
architecture str of dp_bsn_monitor_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 4,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 9,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 4,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 9,
+ init_sl => '0'
+ );
-- Registers in st_clk domain
signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
@@ -108,29 +110,29 @@ begin
mon_reg(9 * c_word_w - 1 downto 8 * c_word_w) <= RESIZE_UVEC(mon_bsn_first_cycle_cnt, c_word_w);
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => mon_evt,
- in_reg => mon_reg, -- read only
- out_reg => open -- no write
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => mon_evt,
+ in_reg => mon_reg, -- read only
+ out_reg => open -- no write
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
index fb0a4c4edf..39e7402635 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
@@ -43,9 +43,9 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_monitor_reg_v2 is
generic (
@@ -81,11 +81,13 @@ end dp_bsn_monitor_reg_v2;
architecture str of dp_bsn_monitor_reg_v2 is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 3,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 7,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 3,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 7,
+ init_sl => '0'
+ );
-- Registers in st_clk domain
signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
@@ -102,29 +104,29 @@ begin
mon_reg(7 * c_word_w - 1 downto 6 * c_word_w) <= RESIZE_UVEC(mon_latency, c_word_w);
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => mon_evt,
- in_reg => mon_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => mon_evt,
+ in_reg => mon_reg, -- read only
+ out_reg => open -- no write
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
index fc3841cc1c..88949f85a6 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
@@ -40,10 +40,10 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_monitor_v2 is
@@ -178,33 +178,33 @@ begin
ref_sync_reg <= ref_sync when rising_edge(clk);
u_sync_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_sync_timeout_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sync_timeout_n,
- count => sync_timeout_cnt
- );
+ generic map (
+ g_width => c_sync_timeout_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sync_timeout_n,
+ count => sync_timeout_cnt
+ );
sync_timeout_n <= not nxt_sync_timeout;
nxt_sync_timeout <= '1' when unsigned(sync_timeout_cnt) >= g_sync_timeout else '0';
u_sync_timeout_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_invert => false,
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => sync_timeout,
- out_evt => sync_timeout_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_invert => false,
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => sync_timeout,
+ out_evt => sync_timeout_revt
+ );
p_clk : process(rst, clk)
begin
@@ -260,24 +260,24 @@ begin
nxt_xon <= in_siso.xon;
u_ready_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => ready,
- r_stable => ready_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => ready,
+ r_stable => ready_stable,
+ r_stable_ack => sync
+ );
u_xon_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => xon,
- r_stable => xon_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => xon,
+ r_stable => xon_stable,
+ r_stable_ack => sync
+ );
-- Sample the BSN, because BSN is only valid during sop.
nxt_current_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else i_current_bsn;
@@ -292,54 +292,54 @@ begin
nxt_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else bsn; -- keep bsn as defined at sop
u_cnt_sop : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
- cnt_en => sop,
- load => TO_SVEC(1, c_cnt_sop_w),
- count => cnt_sop
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
+ cnt_en => sop,
+ load => TO_SVEC(1, c_cnt_sop_w),
+ count => cnt_sop
+ );
u_nof_err : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => err,
- count => cnt_err
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => err,
+ count => cnt_err
+ );
u_cnt_valid : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_valid_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
- cnt_en => valid,
- load => TO_SVEC(1, c_cnt_valid_w),
- count => cnt_valid
- );
+ generic map (
+ g_width => c_cnt_valid_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
+ cnt_en => valid,
+ load => TO_SVEC(1, c_cnt_valid_w),
+ count => cnt_valid
+ );
u_cnt_latency : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_latency_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => ref_sync_reg,
- cnt_en => '1',
- count => cnt_latency
- );
+ generic map (
+ g_width => c_cnt_latency_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => ref_sync_reg,
+ cnt_en => '1',
+ count => cnt_latency
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
index 11f30ee777..c633eebe81 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author: Eric Kooistra, 17 nov 2017
-- Purpose:
@@ -83,19 +83,19 @@ begin
-- Create block sync from snk_in.sync, this blk_sync is active during entire first sop-eop block of sync interval
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '0', -- Defines the output level at reset.
- g_priority_lo => false, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_in.sync, -- A pulse on switch_high makes the out_level go high
- switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
- out_level => blk_sync
- );
+ generic map (
+ g_rst_level => '0', -- Defines the output level at reset.
+ g_priority_lo => false, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_in.sync, -- A pulse on switch_high makes the out_level go high
+ switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
+ out_level => blk_sync
+ );
-- Use stored global BSN at sync and add local BSN to restore the global BSN for every next sop
bsn_restored <= snk_in.bsn when blk_sync = '1' else ADD_UVEC(bsn_at_sync, snk_in.bsn, g_bsn_w);
@@ -104,18 +104,18 @@ begin
-- Add pipeline to ensure timing closure for the restored BSN summation
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in_restored,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in_restored,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
index 2bb5db1000..13ef44fdc9 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : Schedule an output trigger based on the Data Path BSN[]
-- Description:
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
index d90b7705c3..20d93ad9e3 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
@@ -32,9 +32,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_scheduler_reg is
generic (
@@ -63,11 +63,13 @@ architecture rtl of dp_bsn_scheduler_reg is
constant c_bsn_w : natural := st_current_bsn'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0'
+ );
-- Registers in mm_clk domain
signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
@@ -168,31 +170,31 @@ begin
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_init_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_scheduled_bsn_wr, -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
- in_dat => mm_scheduled_bsn(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_scheduled_bsn,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_scheduled_bsn_wr, -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
+ in_dat => mm_scheduled_bsn(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_scheduled_bsn,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
end generate; -- gen_cross
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
index 5dc319ffda..2034b516c9 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
@@ -33,10 +33,10 @@
-- has to disable (dp_on='0') the data path before restarting it.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_source is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
index 4e0beb0889..ad7d03155a 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
@@ -39,9 +39,9 @@
-- ====================================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_source_reg is
generic (
@@ -75,11 +75,13 @@ architecture rtl of dp_bsn_source_reg is
constant c_bsn_w : natural := st_init_bsn'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**2,
+ init_sl => '0'
+ );
-- Registers in mm_clk domain
signal mm_on : std_logic;
@@ -95,7 +97,7 @@ architecture rtl of dp_bsn_source_reg is
signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
- -- Registers in st_clk domain
+-- Registers in st_clk domain
begin
@@ -211,16 +213,16 @@ begin
gen_cross : if g_cross_clock_domain = true generate
-- Block sync registers
u_dp_on_ctrl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_on_ctrl,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_on_ctrl,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_on_ctrl,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_on_ctrl,
+ out_new => open
+ );
mm_on_ctrl(0) <= mm_on;
mm_on_ctrl(1) <= mm_on_pps;
@@ -229,56 +231,56 @@ begin
st_on_pps <= st_on_ctrl(1);
u_mm_on_status : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_on_status,
- dout => mm_on_status
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_on_status,
+ dout => mm_on_status
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_nof_block_per_sync,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_nof_block_per_sync,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_nof_block_per_sync,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_nof_block_per_sync,
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_init_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_init_bsn_wr, -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
- in_dat => mm_init_bsn(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_init_bsn,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_init_bsn_wr, -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
+ in_dat => mm_init_bsn(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_init_bsn,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
end generate; -- gen_cross
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
index 872ffa66a5..56f5f5f714 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
@@ -40,9 +40,9 @@
-- ====================================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_source_reg_v2 is
generic (
@@ -78,11 +78,13 @@ architecture rtl of dp_bsn_source_reg_v2 is
constant c_bsn_time_offset_w : natural := st_bsn_time_offset'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 3,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**3,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 3,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**3,
+ init_sl => '0'
+ );
-- Registers in mm_clk domain
signal mm_on : std_logic;
@@ -101,7 +103,7 @@ architecture rtl of dp_bsn_source_reg_v2 is
signal mm_bsn_time_offset : std_logic_vector(c_bsn_time_offset_w - 1 downto 0) := (others => '0');
signal mm_bsn_time_offset_wr : std_logic;
- -- Registers in st_clk domain
+-- Registers in st_clk domain
begin
@@ -235,16 +237,16 @@ begin
gen_cross : if g_cross_clock_domain = true generate
-- Block sync registers
u_dp_on_ctrl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_on_ctrl,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_on_ctrl,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_on_ctrl,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_on_ctrl,
+ out_new => open
+ );
mm_on_ctrl(0) <= mm_on;
mm_on_ctrl(1) <= mm_on_pps;
@@ -253,70 +255,70 @@ begin
st_on_pps <= st_on_ctrl(1);
u_mm_on_status : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_on_status,
- dout => mm_on_status
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_on_status,
+ dout => mm_on_status
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_nof_clk_per_sync,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_nof_clk_per_sync,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_nof_clk_per_sync,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_nof_clk_per_sync,
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_bsn_init : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_bsn_init_wr, -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
- in_dat => mm_bsn_init(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_bsn_init,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_bsn_init_wr, -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
+ in_dat => mm_bsn_init(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_bsn_init,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_bsn_time_offset : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_bsn_time_offset_wr,
- in_dat => mm_bsn_time_offset,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_bsn_time_offset,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_bsn_time_offset_wr,
+ in_dat => mm_bsn_time_offset,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_bsn_time_offset,
+ out_new => open
+ );
end generate; -- gen_cross
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
index c6fb19795c..b44f5d9ab3 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -55,10 +55,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_source_v2 is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index b826cc3eb1..56af43986b 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -111,10 +111,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_sync_scheduler is
generic (
@@ -357,9 +357,9 @@ begin
-- Assume output_sync_bsn is in future
v.update_bsn := '0';
- -- If output_sync_bsn is still in past, due to lost input blocks, then
- -- last r.input_bsn will be used to keep update_bsn active for more clk
- -- cycles to catch up for lost input blocks.
+ -- If output_sync_bsn is still in past, due to lost input blocks, then
+ -- last r.input_bsn will be used to keep update_bsn active for more clk
+ -- cycles to catch up for lost input blocks.
end if;
-- Hold input bsn
@@ -429,17 +429,17 @@ begin
-- Pipeline output to avoid timing closure problems due to use of output_enable
-----------------------------------------------------------------------------
u_out_sosi : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => output_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => output_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
gen_pipe_out_start : if g_pipeline = 1 generate
out_start <= output_start when rising_edge(clk);
diff --git a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
index fd3d15755d..750c6b0be3 100644
--- a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
@@ -26,15 +26,15 @@
-- snk_in.eop of that block.
library IEEE, common_lib, easics_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-use easics_lib.PCK_CRC8_D8.all;
-use easics_lib.PCK_CRC16_D16.all;
-use easics_lib.PCK_CRC28_D28.all;
-use easics_lib.PCK_CRC32_D32.all;
-use easics_lib.PCK_CRC32_D64.all;
+ use easics_lib.PCK_CRC8_D8.all;
+ use easics_lib.PCK_CRC16_D16.all;
+ use easics_lib.PCK_CRC28_D28.all;
+ use easics_lib.PCK_CRC32_D32.all;
+ use easics_lib.PCK_CRC32_D64.all;
entity dp_calculate_crc is
@@ -56,7 +56,7 @@ architecture rtl of dp_calculate_crc is
constant c_crc_init : std_logic_vector(g_crc_w - 1 downto 0) := (others => '1');
- function func_next_crc(data, crc : std_logic_vector) return std_logic_vector is
+ function func_next_crc (data, crc : std_logic_vector) return std_logic_vector is
variable v_crc : std_logic_vector(g_crc_w - 1 downto 0) := c_crc_init;
begin
if g_data_w = 8 and g_crc_w = 8 then v_crc := nextCRC8_D8(data, crc);
diff --git a/libraries/base/dp/src/vhdl/dp_complex_add.vhd b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
index ab564fbffe..f9535c5b1b 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_add.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -38,7 +38,7 @@ entity dp_complex_add is
g_technology : natural := c_tech_select_default;
g_nof_inputs : natural;
g_data_w : natural -- Complex input data width
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -78,33 +78,33 @@ begin
-- One adder tree for the real part
u_adder_tree_re : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_data_w,
- g_sum_w => c_common_adder_tree_sum_w
- )
- port map (
- clk => clk,
- in_dat => common_adder_tree_re_in_dat,
- sum => common_adder_tree_re_sum
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_data_w,
+ g_sum_w => c_common_adder_tree_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => common_adder_tree_re_in_dat,
+ sum => common_adder_tree_re_sum
+ );
-- One adder tree for the imaginary part
u_adder_tree_im : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_data_w,
- g_sum_w => c_common_adder_tree_sum_w
- )
- port map (
- clk => clk,
- in_dat => common_adder_tree_im_in_dat,
- sum => common_adder_tree_im_sum
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_data_w,
+ g_sum_w => c_common_adder_tree_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => common_adder_tree_im_in_dat,
+ sum => common_adder_tree_im_sum
+ );
p_src_out : process(snk_in_pipe, common_adder_tree_re_sum, common_adder_tree_im_sum)
begin
@@ -121,16 +121,16 @@ begin
snk_in <= snk_in_arr(0);
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline_adder_tree
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_pipe
- );
+ generic map (
+ g_pipeline => c_pipeline_adder_tree
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_pipe
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
index 38abb50d56..3d64131ea4 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -43,7 +43,7 @@ entity dp_complex_mult is
g_conjugate_b : boolean := false; -- Conjugate input 1 of snk_in_2arr2(i)(1 DOWNTO 0)
g_data_w : natural; -- Input data width. Output data width = 2*input data width.
g_variant : string := "IP"
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -68,27 +68,27 @@ begin
-----------------------------------------------------------------------------
gen_common_complex_mult : for i in 0 to g_nof_multipliers - 1 generate
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_data_w,
- g_in_b_w => g_data_w,
- g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
- g_conjugate_b => g_conjugate_b
- )
- port map (
- clk => clk,
- clken => '1',
- rst => '0',
- in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
- in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
- in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
- in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
- in_val => snk_in_2arr_2(i)(0).valid,
- out_pr => common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0),
- out_pi => common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0),
- out_val => common_complex_mult_src_out_arr(i).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_data_w,
+ g_in_b_w => g_data_w,
+ g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
+ g_conjugate_b => g_conjugate_b
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ rst => '0',
+ in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
+ in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
+ in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
+ in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
+ in_val => snk_in_2arr_2(i)(0).valid,
+ out_pr => common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0),
+ out_pi => common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0),
+ out_val => common_complex_mult_src_out_arr(i).valid
+ );
src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0));
src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0));
@@ -99,15 +99,15 @@ begin
-- Forward the input sync with the correct latency
-----------------------------------------------------------------------------
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_dat => snk_in_2arr_2(0)(0).sync,
- out_dat => src_out_arr(0).sync
- );
+ in_dat => snk_in_2arr_2(0)(0).sync,
+ out_dat => src_out_arr(0).sync
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
index 697fb8fba2..206f88d64b 100644
--- a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
@@ -24,9 +24,9 @@
-- Description:
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_components_pkg is
diff --git a/libraries/base/dp/src/vhdl/dp_concat.vhd b/libraries/base/dp/src/vhdl/dp_concat.vhd
index 39714a6101..956f53c805 100644
--- a/libraries/base/dp/src/vhdl/dp_concat.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Concat two frames into one frame.
@@ -158,18 +158,18 @@ begin
gen_input : for I in c_head to c_tail generate
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => hold_src_in_arr(I),
- next_src_out => next_src_out_arr(I),
- pend_src_out => pend_src_out_arr(I),
- src_out_reg => src_out_buf_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => hold_src_in_arr(I),
+ next_src_out => next_src_out_arr(I),
+ pend_src_out => pend_src_out_arr(I),
+ src_out_reg => src_out_buf_arr(I)
+ );
end generate;
-- default ready for hold input when ready for sink input or also ready for hold input when the eop is there
diff --git a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
index f896d428f9..b5de2a8a92 100644
--- a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
@@ -37,13 +37,13 @@
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_concat_field_blk is
generic (
@@ -128,31 +128,31 @@ begin
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w,
- g_in_symbol_w => g_symbol_w,
- g_out_symbol_w => g_symbol_w,
- g_pipeline_ready => g_pipeline_ready
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_out => dp_field_blk_src_out_arr(i),
- src_in => dp_field_blk_src_in_arr(i),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w,
+ g_in_symbol_w => g_symbol_w,
+ g_out_symbol_w => g_symbol_w,
+ g_pipeline_ready => g_pipeline_ready
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_out => dp_field_blk_src_out_arr(i),
+ src_in => dp_field_blk_src_in_arr(i),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
@@ -165,35 +165,35 @@ begin
dp_concat_snk_in_2arr(i)(1) <= dp_field_blk_src_out_arr(i);
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_counter.vhd b/libraries/base/dp/src/vhdl/dp_counter.vhd
index e84b4ee2a8..488893513c 100644
--- a/libraries/base/dp/src/vhdl/dp_counter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter.vhd
@@ -63,10 +63,10 @@
-- Any other useage will break counters >= stage i
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter is
generic (
@@ -112,55 +112,55 @@ begin
-- dp_counter_func
------------------------------------------------------------------------------
u_dp_counter_func : entity work.dp_counter_func
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step
- )
- port map (
- rst => rst,
- clk => clk,
-
- count_en => snk_in.valid,
-
- count_offset_in_arr => count_offset_in_arr,
- count_src_out_arr => dp_counter_func_src_out_arr
- );
-
- ------------------------------------------------------------------------------
- -- dp_pipeline
- ------------------------------------------------------------------------------
- gen_dp_pipeline : if c_use_dp_pipeline = true generate
- u_dp_pipeline_snk_in : entity work.dp_pipeline
generic map (
- g_pipeline => g_pipeline_src_out
+ g_nof_counters => g_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step
)
port map (
- clk => clk,
- rst => rst,
+ rst => rst,
+ clk => clk,
- snk_in => snk_in,
- snk_out => snk_out,
+ count_en => snk_in.valid,
- src_out => src_out,
- src_in => src_in
+ count_offset_in_arr => count_offset_in_arr,
+ count_src_out_arr => dp_counter_func_src_out_arr
);
- gen_dp_pipeline_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
- u_dp_pipeline_count_src_out_arr : entity work.dp_pipeline
+ ------------------------------------------------------------------------------
+ -- dp_pipeline
+ ------------------------------------------------------------------------------
+ gen_dp_pipeline : if c_use_dp_pipeline = true generate
+ u_dp_pipeline_snk_in : entity work.dp_pipeline
generic map (
g_pipeline => g_pipeline_src_out
)
port map (
- clk => clk,
- rst => rst,
+ clk => clk,
+ rst => rst,
- snk_in => dp_counter_func_src_out_arr(i),
+ snk_in => snk_in,
+ snk_out => snk_out,
- src_out => count_src_out_arr(i),
- src_in => src_in
+ src_out => src_out,
+ src_in => src_in
);
+
+ gen_dp_pipeline_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
+ u_dp_pipeline_count_src_out_arr : entity work.dp_pipeline
+ generic map (
+ g_pipeline => g_pipeline_src_out
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => dp_counter_func_src_out_arr(i),
+
+ src_out => count_src_out_arr(i),
+ src_in => src_in
+ );
end generate;
end generate;
@@ -169,34 +169,34 @@ begin
------------------------------------------------------------------------------
gen_dp_pipeline_ready : if c_use_dp_pipeline_ready = true generate
u_dp_pipeline_ready : entity work.dp_pipeline_ready
- generic map (
- g_in_latency => 1
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in
- );
-
- gen_dp_pipeline_ready_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
- u_dp_pipeline_ready_count_src_out_arr : entity work.dp_pipeline_ready
generic map (
- g_in_latency => 1
+ g_in_latency => 1
)
port map (
- clk => clk,
- rst => rst,
+ clk => clk,
+ rst => rst,
- snk_in => dp_counter_func_src_out_arr(i),
+ snk_in => snk_in,
+ snk_out => snk_out,
- src_out => count_src_out_arr(i),
- src_in => src_in
+ src_out => src_out,
+ src_in => src_in
);
+
+ gen_dp_pipeline_ready_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
+ u_dp_pipeline_ready_count_src_out_arr : entity work.dp_pipeline_ready
+ generic map (
+ g_in_latency => 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => dp_counter_func_src_out_arr(i),
+
+ src_out => count_src_out_arr(i),
+ src_in => src_in
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func.vhd b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
index 9f074ba9fe..035d75ec86 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
@@ -38,10 +38,10 @@
-- logic when minimum/maximum values per dimension are reached.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter_func is
generic (
@@ -93,8 +93,8 @@ begin
end generate;
gen_c1_upwards : if i > 0 generate
- count_en_arr(i) <= count_init_arr(i - 1) or count_min_arr(i - 1);
- check_max_arr(i) <= count_max_arr(i - 1);
+ count_en_arr(i) <= count_init_arr(i - 1) or count_min_arr(i - 1);
+ check_max_arr(i) <= count_max_arr(i - 1);
end generate;
end generate;
@@ -104,24 +104,24 @@ begin
-------------------------------------------------------------------------------
gen_dp_counter_func_single : for i in 0 to g_nof_counters - 1 generate
u_dp_counter_func_single : entity work.dp_counter_func_single
- generic map (
- g_range_start => c_range_start(i),
- g_range_stop => c_range_stop(i),
- g_range_step => c_range_step(i)
- )
- port map (
- rst => rst,
- clk => clk,
-
- count_en => count_en_arr(i),
- check_max => check_max_arr(i),
- count_offset => count_offset_in_arr(i),
-
- count => count_arr(i),
- count_init => count_init_arr(i),
- count_min => count_min_arr(i),
- count_max => count_max_arr(i)
- );
+ generic map (
+ g_range_start => c_range_start(i),
+ g_range_stop => c_range_stop(i),
+ g_range_step => c_range_step(i)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ count_en => count_en_arr(i),
+ check_max => check_max_arr(i),
+ count_offset => count_offset_in_arr(i),
+
+ count => count_arr(i),
+ count_init => count_init_arr(i),
+ count_min => count_min_arr(i),
+ count_max => count_max_arr(i)
+ );
end generate;
--------------------------------------------------------------------------------
@@ -129,7 +129,7 @@ begin
-------------------------------------------------------------------------------
gen_dp_counter_func_single_output : for i in 0 to g_nof_counters - 1 generate
count_src_out_arr(i).sync <= '0'; -- not used, force to '0' to avoid toggling between '0' and 'X' in Wave window
- -- when sync is passed on through other components
+ -- when sync is passed on through other components
count_src_out_arr(i).sop <= count_min_arr(i);
count_src_out_arr(i).eop <= count_max_arr(i);
count_src_out_arr(i).valid <= count_en;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
index b258fec131..3215f00194 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
@@ -29,10 +29,10 @@
-- . Not for standalone use; part of dp_counter_func.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter_func_single is -- FIXME move this to common
generic (
@@ -58,7 +58,7 @@ end dp_counter_func_single;
architecture rtl of dp_counter_func_single is
- -- The user defines the counters like a Python range(start,stop,step) in which the stop value
+ -- The user defines the counters like a Python range(start,stop,step) in which the stop value
-- is never actually reached. Calculate the actual maximum values here.
-- . Example:
-- . range(0,4,2) = [0, 2]
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
index 8418f9578d..41027f9c5d 100644
--- a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -88,22 +88,22 @@ begin
common_deinterleave_in_val <= snk_in.valid;
u_deinterleave : entity common_lib.common_deinterleave
- generic map (
- g_nof_out => g_nof_out,
- g_block_size => g_block_size_int,
- g_dat_w => g_dat_w,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => common_deinterleave_in_dat,
- in_val => common_deinterleave_in_val,
-
- out_dat => common_deinterleave_out_dat,
- out_val => common_deinterleave_out_val
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_block_size => g_block_size_int,
+ g_dat_w => g_dat_w,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => common_deinterleave_in_dat,
+ in_val => common_deinterleave_in_val,
+
+ out_dat => common_deinterleave_out_dat,
+ out_val => common_deinterleave_out_val
+ );
-----------------------------------------------------------------------------
-- Use complex fields if required
@@ -127,19 +127,19 @@ begin
gen_ctrl : if g_use_ctrl = true generate
gen_dp_block_gen : for i in 0 to g_nof_out - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_block_size_output,
- g_preserve_sync => true,
- g_preserve_bsn => true
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => common_deinterleave_src_out_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_block_size_output,
+ g_preserve_sync => true,
+ g_preserve_bsn => true
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => common_deinterleave_src_out_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -153,20 +153,20 @@ begin
align_out : if g_use_sync_bsn = true generate
gen_dp_fifo_info: for i in 0 to g_nof_out - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in, -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in, -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
index 5c9bd2ba3d..fdf777440d 100755
--- a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Eric Kooistra
@@ -153,19 +153,19 @@ begin
snk_out <= out_siso_arr(0); -- all out_siso_arr have the same siso, so wire output 0
u_pipeline_outputs : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_outputs,
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out_arr => out_siso_arr,
- snk_in_arr => out_sosi_arr,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_outputs,
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out_arr => out_siso_arr,
+ snk_in_arr => out_sosi_arr,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_demux.vhd b/libraries/base/dp/src/vhdl/dp_demux.vhd
index 392e745ddc..76c534547d 100644
--- a/libraries/base/dp/src/vhdl/dp_demux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_demux.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
@@ -171,8 +171,8 @@ begin
else
output_select <= g_nof_output - 1 - sel_ctrl;
end if;
- -- User might need this status port to indicate if/when the output has actually been switched
- sel_stat <= output_select;
+ -- User might need this status port to indicate if/when the output has actually been switched
+ sel_stat <= output_select;
end if;
end process;
@@ -188,16 +188,16 @@ begin
-- The dp_packet_detect component simply asserts its output from SOP to EOP
u_dp_packet_detect : entity work.dp_packet_detect
- generic map (
- g_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- sosi => adapt_sosi,
- siso => adapt_siso, -- We're using the adapted sink_in with RL=0
- pkt_det => pkt_det
- );
+ generic map (
+ g_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ sosi => adapt_sosi,
+ siso => adapt_siso, -- We're using the adapted sink_in with RL=0
+ pkt_det => pkt_det
+ );
end generate;
@@ -244,20 +244,20 @@ begin
gen_individual : if g_combined = false and g_nof_output > 1 generate
-- Adapt input to RL = 0 to have show-ahead
u_rl_0 : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => adapt_siso,
- src_out => adapt_sosi
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => adapt_siso,
+ src_out => adapt_sosi
+ );
sel_channel <= adapt_sosi.channel;
sel_eop <= adapt_sosi.eop and adapt_siso.ready; -- RL = 0, so eop is only valid when the ready acknowledges it
@@ -291,20 +291,20 @@ begin
-- Back to output RL = 1
gen_rl_1 : for I in 0 to g_nof_output - 1 generate
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => prev_src_in_arr(I),
- snk_in => pend_src_out_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => prev_src_in_arr(I),
+ snk_in => pend_src_out_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_distribute.vhd b/libraries/base/dp/src/vhdl/dp_distribute.vhd
index 23a5d39635..81a075a50d 100644
--- a/libraries/base/dp/src/vhdl/dp_distribute.vhd
+++ b/libraries/base/dp/src/vhdl/dp_distribute.vhd
@@ -76,11 +76,11 @@
-- gets lost or an input is not used.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_distribute is
generic (
@@ -161,33 +161,33 @@ begin
gen_fifo : if g_use_fifo = true generate
gen_input : for I in 0 to g_nof_input - 1 generate
u_fifo : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => in_siso_arr(I),
- src_out => in_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => in_siso_arr(I),
+ src_out => in_sosi_arr(I)
+ );
end generate;
end generate;
@@ -199,20 +199,20 @@ begin
gen_dec : if g_decode_channel_lo = true generate
gen_i : for I in 0 to g_nof_input - 1 generate
u_dec : entity work.dp_packet_dec_channel_lo
- generic map (
- g_data_w => g_data_w,
- g_channel_lo => c_link_channel_lo
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => in_siso_arr(I),
- snk_in => in_sosi_arr(I),
- -- ST source
- src_in => rx_siso_arr(I),
- src_out => rx_sosi_arr(I)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_channel_lo => c_link_channel_lo
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
+ -- ST source
+ src_in => rx_siso_arr(I),
+ src_out => rx_sosi_arr(I)
+ );
end generate;
end generate;
@@ -224,22 +224,22 @@ begin
gen_transpose : if g_nof_input /= g_nof_output or g_transpose = true generate
gen_demux : for I in 0 to g_nof_input - 1 generate
u_demux : entity work.dp_demux
- generic map (
- g_mode => c_demux_mode,
- g_nof_output => g_nof_output,
- g_remove_channel_lo => c_demux_remove_channel_lo,
- g_combined => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => rx_siso_arr(I),
- snk_in => rx_sosi_arr(I),
- -- ST source
- src_in_arr => demux_siso_2arr(I),
- src_out_arr => demux_sosi_2arr(I)
- );
+ generic map (
+ g_mode => c_demux_mode,
+ g_nof_output => g_nof_output,
+ g_remove_channel_lo => c_demux_remove_channel_lo,
+ g_combined => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => rx_siso_arr(I),
+ snk_in => rx_sosi_arr(I),
+ -- ST source
+ src_in_arr => demux_siso_2arr(I),
+ src_out_arr => demux_sosi_2arr(I)
+ );
end generate;
-- Rewire to distribute
@@ -252,26 +252,26 @@ begin
gen_mux : for J in 0 to g_nof_output - 1 generate
u_mux : entity work.dp_mux
- generic map (
- -- MUX
- g_mode => c_mux_mode,
- g_nof_input => g_nof_input,
- g_append_channel_lo => c_mux_append_channel_lo,
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, g_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => mux_siso_2arr(J),
- snk_in_arr => mux_sosi_2arr(J),
- -- ST source
- src_in => tx_siso_arr(J),
- src_out => tx_sosi_arr(J)
- );
+ generic map (
+ -- MUX
+ g_mode => c_mux_mode,
+ g_nof_input => g_nof_input,
+ g_append_channel_lo => c_mux_append_channel_lo,
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, g_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => mux_siso_2arr(J),
+ snk_in_arr => mux_sosi_2arr(J),
+ -- ST source
+ src_in => tx_siso_arr(J),
+ src_out => tx_sosi_arr(J)
+ );
end generate;
end generate;
@@ -283,18 +283,18 @@ begin
gen_enc : if g_encode_channel_lo = true generate
gen_j : for J in 0 to g_nof_output - 1 generate
u_enc : entity work.dp_packet_enc_channel_lo
- generic map (
- g_data_w => g_data_w,
- g_channel_lo => c_link_channel_lo
- )
- port map (
- -- ST sinks
- snk_out => tx_siso_arr(J),
- snk_in => tx_sosi_arr(J),
- -- ST source
- src_in => src_in_arr(J),
- src_out => src_out_arr(J)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_channel_lo => c_link_channel_lo
+ )
+ port map (
+ -- ST sinks
+ snk_out => tx_siso_arr(J),
+ snk_in => tx_sosi_arr(J),
+ -- ST source
+ src_in => src_in_arr(J),
+ src_out => src_out_arr(J)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
index 86fed113e9..f689ba4ab0 100644
--- a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
@@ -24,10 +24,10 @@
-- Provide packetized dummy values when sink is ready
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_dummy_source is
generic (
@@ -39,7 +39,7 @@ entity dp_dummy_source is
g_dummy_empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0) := x"DD";
g_dummy_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := x"DDDDDDDD";
g_dummy_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := x"DDDDDDDD"
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -72,18 +72,18 @@ begin
src_out.err <= c_dp_sosi_dummy.err;
u_dp_block_gen: entity work.dp_block_gen
- generic map (
- g_nof_data => g_dummy_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
-
- src_in => src_in,
- src_out => block_sosi,
-
- en => '1'
- );
+ generic map (
+ g_nof_data => g_dummy_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ src_in => src_in,
+ src_out => block_sosi,
+
+ en => '1'
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_eop_extend.vhd b/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
index 512c340bd8..8653b6aefc 100644
--- a/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
+++ b/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- The extended eop output can be used to gate valid eop related stream info
@@ -49,13 +49,13 @@ architecture rtl of dp_eop_extend is
begin
u_extend : entity common_lib.common_switch
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_eop,
- switch_low => in_sop,
- out_level => extend
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_eop,
+ switch_low => in_sop,
+ out_level => extend
+ );
eop_extend <= (in_eop or extend) and not in_sop;
diff --git a/libraries/base/dp/src/vhdl/dp_example_dut.vhd b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
index 03efd8b3a0..a64c607174 100644
--- a/libraries/base/dp/src/vhdl/dp_example_dut.vhd
+++ b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
@@ -163,9 +163,9 @@
-- the test bench.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_example_dut is
port (
@@ -238,7 +238,7 @@ begin
v.hold_out.valid := '1'; -- the function has new data to output
- --< end of component function >
+ --< end of component function >
end if;
-- output input stage into output stage when ready, else hold_out.valid to signal pending output
@@ -288,7 +288,7 @@ begin
begin
r_snk_out <= c_dp_siso_rdy;
- -- < force r_snk_out.ready='0' based on nxt_r if function needs to apply backpressure >
+ -- < force r_snk_out.ready='0' based on nxt_r if function needs to apply backpressure >
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
index 5497055960..0eac2ad2dc 100644
--- a/libraries/base/dp/src/vhdl/dp_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- . Source a DP data block of which the contents are read from snk_in.data when snk_in.valid = '1'
@@ -109,27 +109,27 @@ entity dp_field_blk is
-- Source mode
-- . Single cycle SLV input
--- slv_in : IN STD_LOGIC_VECTOR(g_snk_data_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Input for the RW fields defined in g_field_arr
--- slv_in_val : IN STD_LOGIC := '0';
+ -- slv_in : IN STD_LOGIC_VECTOR(g_snk_data_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Input for the RW fields defined in g_field_arr
+ -- slv_in_val : IN STD_LOGIC := '0';
-- . Multi cycle block output
-- Sink mode
-- . Multi cycle block input
-- . Single cycle SLV output
--- slv_out : OUT STD_LOGIC_VECTOR(g_src_data_w-1 DOWNTO 0); -- Output for the RO fields defined in g_field_arr
--- slv_out_val : OUT STD_LOGIC;
+ -- slv_out : OUT STD_LOGIC_VECTOR(g_src_data_w-1 DOWNTO 0); -- Output for the RO fields defined in g_field_arr
+ -- slv_out_val : OUT STD_LOGIC;
reg_slv_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_slv_miso : out t_mem_miso
--- reg_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
--- reg_ovr_miso : OUT t_mem_miso
+ -- reg_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ -- reg_ovr_miso : OUT t_mem_miso
);
end dp_field_blk;
architecture str of dp_field_blk is
--- CONSTANT c_ovr_field_arr : t_common_field_arr(g_field_arr'RANGE) := field_ovr_arr(g_field_arr, g_field_sel);
+ -- CONSTANT c_ovr_field_arr : t_common_field_arr(g_field_arr'RANGE) := field_ovr_arr(g_field_arr, g_field_sel);
-- Mode: fields to data block (c_field_to_block=True) or data block to fields (c_field_to_block=False)
-- a.k.a. wire to narrow or narrow to wide
@@ -194,50 +194,50 @@ begin
snk_out <= dp_repack_data_snk_out;
u_dp_repack_data : entity work.dp_repack_data
- generic map (
- g_in_dat_w => g_snk_data_w,
- g_in_nof_words => ceil_div(g_src_data_w, g_snk_data_w),
- g_out_dat_w => g_src_data_w,
- g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w),
- g_in_symbol_w => g_in_symbol_w,
- g_out_symbol_w => g_out_symbol_w,
- g_pipeline_ready => g_pipeline_ready
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => dp_repack_data_snk_out,
- snk_in => dp_repack_data_snk_in,
-
- src_in => dp_repack_data_src_in,
- src_out => dp_repack_data_src_out
- );
+ generic map (
+ g_in_dat_w => g_snk_data_w,
+ g_in_nof_words => ceil_div(g_src_data_w, g_snk_data_w),
+ g_out_dat_w => g_src_data_w,
+ g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w),
+ g_in_symbol_w => g_in_symbol_w,
+ g_out_symbol_w => g_out_symbol_w,
+ g_pipeline_ready => g_pipeline_ready
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_repack_data_snk_out,
+ snk_in => dp_repack_data_snk_in,
+
+ src_in => dp_repack_data_src_in,
+ src_out => dp_repack_data_src_out
+ );
---------------------------------------------------------------------------------------
-- mm_fields for MM access to each field
---------------------------------------------------------------------------------------
u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => g_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_mosi => reg_slv_mosi,
- mm_miso => reg_slv_miso,
-
- slv_clk => dp_clk,
- slv_rst => dp_rst,
-
- slv_in => mm_fields_slv_in,
- slv_in_val => mm_fields_slv_in_val,
- slv_out => mm_fields_slv_out
- );
-
- ---------------------------------------------------------------------------------------
- -- mm_fields to set override bits
+ generic map(
+ g_field_arr => g_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_mosi => reg_slv_mosi,
+ mm_miso => reg_slv_miso,
+
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
+
+ slv_in => mm_fields_slv_in,
+ slv_in_val => mm_fields_slv_in_val,
+ slv_out => mm_fields_slv_out
+ );
+
+---------------------------------------------------------------------------------------
+-- mm_fields to set override bits
-- ---------------------------------------------------------------------------------------
-- u_mm_fields_ovr: ENTITY mm_lib.mm_fields
-- GENERIC MAP(
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index 91105a6c8c..6d23005678 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -40,11 +40,11 @@
-- ready signal.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_core is
generic (
@@ -174,25 +174,25 @@ begin
gen_common_fifo_sc : if g_use_dual_clock = false generate
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_lut => g_use_lut_sc,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rd_val => fifo_rd_val,
- usedw => fifo_rd_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
+ );
wr_init <= '0'; -- to avoid no driver warning in synthesis
fifo_wr_usedw <= fifo_rd_usedw;
@@ -200,26 +200,26 @@ begin
gen_common_fifo_dc : if g_use_dual_clock = true generate
u_common_fifo_dc : entity common_lib.common_fifo_dc
- generic map (
- g_technology => g_technology,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => arst,
- wr_clk => wr_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_init_out => wr_init,
- wr_ful => fifo_wr_ful,
- wrusedw => fifo_wr_usedw,
- rd_clk => rd_clk,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rdusedw => fifo_rd_usedw,
- rd_val => fifo_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_init_out => wr_init,
+ wr_ful => fifo_wr_ful,
+ wrusedw => fifo_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rdusedw => fifo_rd_usedw,
+ rd_val => fifo_rd_val
+ );
arst <= wr_rst or rd_rst;
end generate;
@@ -248,19 +248,19 @@ begin
rd_sosi.eop <= fifo_rd_val and rd_ctrl(0);
u_ready_latency : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso,
- snk_in => rd_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
index 1ec8ea0443..776f3a50a7 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -44,11 +44,11 @@
-- . It is possible to add additonal signals to the fifo using in_aux/out_aux.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_core_arr is
generic (
@@ -196,50 +196,50 @@ begin
gen_common_fifo_sc : if g_use_dual_clock = false generate
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_lut => g_use_lut_sc,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rd_val => fifo_rd_val,
- usedw => fifo_rd_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
+ );
fifo_wr_usedw <= fifo_rd_usedw;
end generate;
gen_common_fifo_dc : if g_use_dual_clock = true generate
u_common_fifo_dc : entity common_lib.common_fifo_dc
- generic map (
- g_technology => g_technology,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => arst,
- wr_clk => wr_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- wrusedw => fifo_wr_usedw,
- rd_clk => rd_clk,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rdusedw => fifo_rd_usedw,
- rd_val => fifo_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ wrusedw => fifo_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rdusedw => fifo_rd_usedw,
+ rd_val => fifo_rd_val
+ );
arst <= wr_rst or rd_rst;
end generate;
@@ -276,6 +276,24 @@ begin
rd_sosi_arr(I).eop <= fifo_rd_val and rd_ctrl(0);
u_ready_latency : entity work.dp_latency_adapter
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso_arr(I),
+ snk_in => rd_sosi_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
+ end generate;
+
+ -- Using extra dp_latency_adapter for aux signal
+ u_ready_latency_aux : entity work.dp_latency_adapter
generic map (
g_in_latency => 1,
g_out_latency => g_fifo_rl
@@ -284,28 +302,10 @@ begin
rst => rd_rst,
clk => rd_clk,
-- ST sink
- snk_out => rd_siso_arr(I),
- snk_in => rd_sosi_arr(I),
+ snk_in => in_aux_sosi,
-- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ src_in => src_in_arr(0),
+ src_out => out_aux_sosi
);
- end generate;
-
- -- Using extra dp_latency_adapter for aux signal
- u_ready_latency_aux : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_in => in_aux_sosi,
- -- ST source
- src_in => src_in_arr(0),
- src_out => out_aux_sosi
- );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index 41adce2ef4..3ed1a6947d 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -23,11 +23,11 @@
-- Description: See dp_fifo_core.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc is
generic (
@@ -74,43 +74,43 @@ architecture str of dp_fifo_dc is
begin
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
index 4ce5463f84..8f0ea8a511 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -25,11 +25,11 @@
-- Description: See dp_fifo_core_arr.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc_arr is
generic (
@@ -81,48 +81,48 @@ architecture str of dp_fifo_dc_arr is
begin
u_dp_fifo_core_arr : entity work.dp_fifo_core_arr
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_aux_w => g_aux_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_aux => g_use_aux,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- in_aux => in_aux,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr,
- out_aux => out_aux
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_aux_w => g_aux_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_aux => g_use_aux,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ in_aux => in_aux,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ out_aux => out_aux
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
index 3e3fd2fc20..d7509e7b72 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
@@ -101,11 +101,11 @@
-- . add this multi tb-tb test bench to tb_tb_tb_dp_backpressure.vhd
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc_mixed_widths is
generic (
@@ -202,37 +202,37 @@ begin
gen_equal : if c_nof_narrow = 1 generate -- fall back to equal width FIFO
u_dp_fifo_dc : entity work.dp_fifo_dc
- generic map (
- g_technology => g_technology,
- g_data_w => g_wr_data_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_ctrl => g_use_ctrl,
- g_fifo_size => g_wr_fifo_size,
- g_fifo_af_margin => g_wr_fifo_af_margin,
- g_fifo_rl => g_rd_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- ST sink
- snk_out => i_snk_out,
- snk_in => snk_in,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_wr_data_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_ctrl => g_use_ctrl,
+ g_fifo_size => g_wr_fifo_size,
+ g_fifo_af_margin => g_wr_fifo_af_margin,
+ g_fifo_rl => g_rd_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- ST sink
+ snk_out => i_snk_out,
+ snk_in => snk_in,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate; -- gen_equal
gen_mixed : if c_nof_narrow > 1 generate -- mixed width FIFO
@@ -271,26 +271,26 @@ begin
fifo_rd_req <= rd_siso.ready;
u_fifo_mw : entity common_lib.common_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_nof_words => g_wr_fifo_size, -- FIFO size in nof wr_dat words
- g_wr_dat_w => c_fifo_wr_dat_w,
- g_rd_dat_w => c_fifo_rd_dat_w
- )
- port map (
- rst => arst,
- wr_clk => wr_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- wrusedw => i_wr_usedw,
- rd_clk => rd_clk,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => rd_emp,
- rdusedw => rd_usedw,
- rd_val => fifo_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_words => g_wr_fifo_size, -- FIFO size in nof wr_dat words
+ g_wr_dat_w => c_fifo_wr_dat_w,
+ g_rd_dat_w => c_fifo_rd_dat_w
+ )
+ port map (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ wrusedw => i_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => rd_emp,
+ rdusedw => rd_usedw,
+ rd_val => fifo_rd_val
+ );
-- FIFO write multiple parallel --> read one serial
gen_wr_wide : if c_wr_wide = true generate
@@ -453,20 +453,20 @@ begin
-- Support show ahead FIFO with ready latency = 0 at read output
u_rl : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_rd_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso,
- snk_in => rd_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_rd_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate; -- gen_mixed
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
index 20d57efaa1..25625a2f73 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
@@ -26,11 +26,11 @@
-- for new designs.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill is
generic (
@@ -80,45 +80,45 @@ architecture str of dp_fifo_fill is
begin
u_dp_fifo_fill_sc : entity work.dp_fifo_fill_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- usedw => usedw,
- rd_emp => rd_emp,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ usedw => usedw,
+ rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
index 1b296951d8..62d7a5f615 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
@@ -57,11 +57,11 @@
-- directly.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_core is
generic (
@@ -160,83 +160,83 @@ begin
gen_dp_fifo_sc : if g_use_dual_clock = false generate
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => c_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => c_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
+ );
wr_fifo_usedw <= rd_fifo_usedw;
end generate;
gen_dp_fifo_dc : if g_use_dual_clock = true generate
u_dp_fifo_dc : entity work.dp_fifo_dc
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- --g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => c_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_fifo_usedw,
- rd_usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ --g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => c_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_fifo_usedw,
+ rd_usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
+ );
end generate;
no_fill : if g_fifo_fill = 0 generate
@@ -331,18 +331,18 @@ begin
-- Hold the sink input for source output
u_snk : entity work.dp_hold_input
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso, -- SISO ready
- snk_in => rd_sosi, -- SOSI
- -- ST source
- src_in => hold_src_in, -- SISO ready
- next_src_out => OPEN, -- SOSI
- pend_src_out => pend_src_out,
- src_out_reg => i_src_out
- );
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso, -- SISO ready
+ snk_in => rd_sosi, -- SOSI
+ -- ST source
+ src_in => hold_src_in, -- SISO ready
+ next_src_out => OPEN, -- SOSI
+ pend_src_out => pend_src_out,
+ src_out_reg => i_src_out
+ );
p_state : process(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
index d5099ebc8f..6b039b9aaa 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
@@ -24,11 +24,11 @@
-- Description: See dp_fifo_fill_core.vhd.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_dc is
generic (
@@ -78,46 +78,46 @@ architecture str of dp_fifo_fill_dc is
begin
u_dp_fifo_fill_core : entity work.dp_fifo_fill_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 3f2abfd71d..07c39473c9 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -53,11 +53,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_eop is
generic (
@@ -169,61 +169,61 @@ begin
rd_fill_ctrl <= rd_fill_32b(c_fifo_size_w - 1 downto 0);
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => g_use_dual_clock,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => c_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_fifo_usedw,
- rd_usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => g_use_dual_clock,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => c_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_fifo_usedw,
+ rd_usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
+ );
-- Transfer eop counter across clock domains for dual clock
gen_rd_eop_cnt_dc : if g_use_dual_clock = true generate
reg_wr_eop_cnt <= TO_UVEC(wr_eop_cnt, c_word_w);
u_common_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => wr_rst,
- in_clk => wr_clk,
- in_dat => reg_wr_eop_cnt,
- in_new => wr_eop_new,
- in_done => wr_eop_done,
- out_rst => rd_rst,
- out_clk => rd_clk,
- out_dat => reg_rd_eop_cnt,
- out_new => rd_eop_new
- );
+ port map (
+ in_rst => wr_rst,
+ in_clk => wr_clk,
+ in_dat => reg_wr_eop_cnt,
+ in_new => wr_eop_new,
+ in_done => wr_eop_done,
+ out_rst => rd_rst,
+ out_clk => rd_clk,
+ out_dat => reg_rd_eop_cnt,
+ out_new => rd_eop_new
+ );
end generate;
-- No need to transfer eop counter across clock domains for single clock
@@ -334,18 +334,18 @@ begin
-- Hold the sink input for source output
u_snk : entity work.dp_hold_input
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso, -- SISO ready
- snk_in => rd_sosi, -- SOSI
- -- ST source
- src_in => hold_src_in, -- SISO ready
- next_src_out => OPEN, -- SOSI
- pend_src_out => pend_src_out,
- src_out_reg => i_src_out
- );
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso, -- SISO ready
+ snk_in => rd_sosi, -- SOSI
+ -- ST source
+ src_in => hold_src_in, -- SISO ready
+ next_src_out => OPEN, -- SOSI
+ pend_src_out => pend_src_out,
+ src_out_reg => i_src_out
+ );
end generate;
gen_rl_0 : if g_fifo_rl = 0 generate
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
index 7b6567b870..883b2fd530 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
@@ -25,11 +25,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_eop_sc is
generic (
@@ -77,48 +77,48 @@ architecture wrap of dp_fifo_fill_eop_sc is
begin
u_dp_fifo_fill_eop : entity work.dp_fifo_fill_eop
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => false, -- single clock
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw, -- use rd_usedw, similar as in dp_fifo_sc, dp_fifo_fill_sc
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => false, -- single clock
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw, -- use rd_usedw, similar as in dp_fifo_sc, dp_fifo_fill_sc
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end wrap;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
index 0dd0ef1ce9..a7d453a917 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
@@ -51,9 +51,9 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_fill_reg is
generic (
@@ -85,11 +85,13 @@ architecture str of dp_fifo_fill_reg is
constant c_nof_regs_per_stream : natural := 4; -- Must always be a power of 2 in order to meet the python register definition.
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_streams * c_nof_regs_per_stream),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => g_nof_streams * c_nof_regs_per_stream,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_streams * c_nof_regs_per_stream),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => g_nof_streams * c_nof_regs_per_stream,
+ init_sl => '0'
+ );
-- Registers in st_clk domain
signal in_arr_reg : std_logic_vector(g_nof_streams * c_nof_regs_per_stream * c_word_w - 1 downto 0) := (others => '0');
@@ -106,47 +108,47 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg,
- g_init_reg => (others => '1')
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
-
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => reg_rd_arr,
- in_new => OPEN,
- in_reg => in_arr_reg, -- read
- out_reg => OPEN, -- write
- out_new => open
- );
-
- gen_peak_meters : for I in 0 to g_nof_streams - 1 generate
- u_peak_meter : entity common_lib.common_peak
- generic map(
- g_dat_w => c_word_w
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg,
+ g_init_reg => (others => '1')
)
port map (
- rst => st_rst,
- clk => st_clk,
- in_dat => used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
- in_val => '1',
- in_clear => reg_rd_arr(I * c_nof_regs_per_stream + c_reg_max_used_words_offset),
- out_dat => peak_used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
- out_val => open
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => reg_rd_arr,
+ in_new => OPEN,
+ in_reg => in_arr_reg, -- read
+ out_reg => OPEN, -- write
+ out_new => open
);
+
+ gen_peak_meters : for I in 0 to g_nof_streams - 1 generate
+ u_peak_meter : entity common_lib.common_peak
+ generic map(
+ g_dat_w => c_word_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ in_dat => used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
+ in_val => '1',
+ in_clear => reg_rd_arr(I * c_nof_regs_per_stream + c_reg_max_used_words_offset),
+ out_dat => peak_used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
+ out_val => open
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
index 7c9972b085..50400a401c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
@@ -24,11 +24,11 @@
-- Description: See dp_fifo_fill_core.vhd.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_sc is
generic (
@@ -79,47 +79,47 @@ architecture str of dp_fifo_fill_sc is
begin
u_dp_fifo_fill_core : entity work.dp_fifo_fill_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => false,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw,
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => false,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw,
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
index ecc96675a1..ee526c08c8 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Provide MM access to the ST input of a FIFO.
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
index c9cc0fa633..1e7ee6c90a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_from_mm_reg is
port (
@@ -37,17 +37,19 @@ entity dp_fifo_from_mm_reg is
-- MM registers
mm_wr_usedw : in std_logic_vector(c_word_w - 1 downto 0);
mm_wr_availw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end dp_fifo_from_mm_reg;
architecture rtl of dp_fifo_from_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0'
+ );
begin
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
index 16d0f00cdc..3052669e32 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
@@ -71,11 +71,11 @@
-- - dp_block_gen_valid_arr
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_info is
generic (
@@ -158,19 +158,19 @@ begin
-- Data pipeline register to compensate for the fifo rd_req to rd_val latency of 1
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => data_snk_out,
- snk_in => data_snk_in,
- -- ST source
- src_in => dp_pipeline_data_src_in,
- src_out => dp_pipeline_data_src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => data_snk_out,
+ snk_in => data_snk_in,
+ -- ST source
+ src_in => dp_pipeline_data_src_in,
+ src_out => dp_pipeline_data_src_out
+ );
-- Buffer sop info
gen_info_sop : if c_fifo_sop_dat_w > 0 generate
@@ -185,25 +185,25 @@ begin
info_snk_in.channel(g_channel_w - 1 downto 0));
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
- g_dat_w => c_fifo_sop_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_sop_wr_dat,
- wr_req => fifo_sop_wr_req,
- wr_ful => fifo_sop_wr_ful,
- rd_dat => fifo_sop_rd_dat,
- rd_req => fifo_sop_rd_req,
- rd_emp => fifo_sop_rd_emp,
- rd_val => fifo_sop_rd_val,
- usedw => fifo_sop_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_dat_w => c_fifo_sop_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_sop_wr_dat,
+ wr_req => fifo_sop_wr_req,
+ wr_ful => fifo_sop_wr_ful,
+ rd_dat => fifo_sop_rd_dat,
+ rd_req => fifo_sop_rd_req,
+ rd_emp => fifo_sop_rd_emp,
+ rd_val => fifo_sop_rd_val,
+ usedw => fifo_sop_usedw
+ );
-- Extract the sop data from the FIFO output SLV
info_src_out.sync <= rd_sync(0);
@@ -223,25 +223,25 @@ begin
info_snk_in.err(g_error_w - 1 downto 0));
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
- g_dat_w => c_fifo_eop_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_eop_wr_dat,
- wr_req => fifo_eop_wr_req,
- wr_ful => fifo_eop_wr_ful,
- rd_dat => fifo_eop_rd_dat,
- rd_req => fifo_eop_rd_req,
- rd_emp => fifo_eop_rd_emp,
- rd_val => fifo_eop_rd_val,
- usedw => fifo_eop_usedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_dat_w => c_fifo_eop_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_eop_wr_dat,
+ wr_req => fifo_eop_wr_req,
+ wr_ful => fifo_eop_wr_ful,
+ rd_dat => fifo_eop_rd_dat,
+ rd_req => fifo_eop_rd_req,
+ rd_emp => fifo_eop_rd_emp,
+ rd_val => fifo_eop_rd_val,
+ usedw => fifo_eop_usedw
+ );
-- Extract the eop data from the FIFO output SLV
info_src_out.empty(g_empty_w - 1 downto 0) <= func_slv_extract(g_use_empty, g_use_error, g_empty_w, g_error_w, fifo_eop_rd_dat, 0);
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
index 85c6969c7b..c3639b99fa 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
@@ -28,12 +28,12 @@
-- desired monitoring inputs and control outputs.
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_fifo_monitor is
port (
@@ -59,10 +59,10 @@ end dp_fifo_monitor;
architecture str of dp_fifo_monitor is
constant c_field_arr : t_common_field_arr(4 downto 0) := ( (field_name_pad("rd_usedw"), "RO", 32, field_default(0) ),
- (field_name_pad("wr_usedw"), "RO", 32, field_default(0) ),
- (field_name_pad("rd_empty"), "RO", 1, field_default(0) ),
- (field_name_pad("wr_full" ), "RO", 1, field_default(0) ),
- (field_name_pad("rd_fill" ), "RW", 32, field_default(0) ));
+ (field_name_pad("wr_usedw"), "RO", 32, field_default(0) ),
+ (field_name_pad("rd_empty"), "RO", 1, field_default(0) ),
+ (field_name_pad("wr_full" ), "RO", 1, field_default(0) ),
+ (field_name_pad("rd_fill" ), "RW", 32, field_default(0) ));
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -75,25 +75,25 @@ begin
mm_fields_in(field_hi(c_field_arr, "wr_full") downto field_lo(c_field_arr, "wr_full")) <= slv(wr_full);
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in => mm_fields_in,
- slv_in_val => '1',
+ slv_in => mm_fields_in,
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
rd_fill_32b <= mm_fields_out(field_hi(c_field_arr, "rd_fill") downto field_lo(c_field_arr, "rd_fill"));
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
index 8b6ceee5e2..2019becd57 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
@@ -27,12 +27,12 @@
-- . see dp_fifo_monitor.vhd
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_fifo_monitor_arr is
generic (
@@ -68,35 +68,35 @@ architecture str of dp_fifo_monitor_arr is
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(c_nof_regs)
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(c_nof_regs)
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_dp_fifo_monitor : for i in 0 to g_nof_streams - 1 generate
u_dp_fifo_monitor: entity work.dp_fifo_monitor
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- reg_mosi => reg_mosi_arr(i),
- reg_miso => reg_miso_arr(i),
-
- rd_usedw_32b => rd_usedw_32b_arr(i),
- wr_usedw_32b => wr_usedw_32b_arr(i),
- rd_emp => rd_emp_arr(i),
- wr_full => wr_full_arr(i),
- rd_fill_32b => rd_fill_32b_arr(i)
- );
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_mosi => reg_mosi_arr(i),
+ reg_miso => reg_miso_arr(i),
+
+ rd_usedw_32b => rd_usedw_32b_arr(i),
+ wr_usedw_32b => wr_usedw_32b_arr(i),
+ rd_emp => rd_emp_arr(i),
+ wr_full => wr_full_arr(i),
+ rd_fill_32b => rd_fill_32b_arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index 52ef061d74..85428902c0 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -23,11 +23,11 @@
-- Description: See dp_fifo_core.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_sc is
generic (
@@ -73,45 +73,45 @@ architecture str of dp_fifo_sc is
begin
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => false,
- g_use_lut_sc => g_use_lut,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => false,
+ g_use_lut_sc => g_use_lut,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
index 7340848573..450b9ec12a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Provide MM access to the ST output of a FIFO.
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
index 8f1c2af2fe..6d38c81a36 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_to_mm_reg is
port (
@@ -37,17 +37,19 @@ entity dp_fifo_to_mm_reg is
-- MM registers
mm_rd_usedw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end dp_fifo_to_mm_reg;
architecture rtl of dp_fifo_to_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0'
+ );
begin
diff --git a/libraries/base/dp/src/vhdl/dp_flush.vhd b/libraries/base/dp/src/vhdl/dp_flush.vhd
index 56e1cd282c..baed673eda 100644
--- a/libraries/base/dp/src/vhdl/dp_flush.vhd
+++ b/libraries/base/dp/src/vhdl/dp_flush.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose: Flush snk_in when src_in will be not ready for a long time.
-- Description:
@@ -151,19 +151,19 @@ begin
end process;
u_src_en : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => true,
- g_or_high => true,
- g_and_low => true
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => src_en_hi,
- switch_low => src_en_lo,
- out_level => src_en
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => true,
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => src_en_hi,
+ switch_low => src_en_lo,
+ out_level => src_en
+ );
p_snk_flush : process(snk_in, flush_dly)
variable v_hi : std_logic;
@@ -196,19 +196,19 @@ begin
end process;
u_snk_flush : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => true, -- priority does not matter
- g_or_high => true,
- g_and_low => true
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_flush_hi,
- switch_low => snk_flush_lo,
- out_level => snk_flush
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => true, -- priority does not matter
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_flush_hi,
+ switch_low => snk_flush_lo,
+ out_level => snk_flush
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_folder.vhd b/libraries/base/dp/src/vhdl/dp_folder.vhd
index 1e0a142afc..e13d3234c6 100644
--- a/libraries/base/dp/src/vhdl/dp_folder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_folder.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Status:
-- . Active (recommended for new designs)
@@ -164,20 +164,20 @@ begin
-----------------------------------------------------------------------------
gen_dp_folder: if (g_nof_folds < 0 and c_nof_muxes > 1) or g_nof_folds > 1 generate
u_dp_folder : dp_folder
- generic map (
- g_nof_inputs => c_nof_muxes,
- g_nof_folds => g_nof_folds - 1,
- g_output_block_size => g_output_block_size,
- g_fwd_sync_bsn => g_fwd_sync_bsn,
- g_use_channel => g_use_channel
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in_arr => mux_src_out_arr,
- src_out_arr => dp_folder_src_out_arr
- );
+ generic map (
+ g_nof_inputs => c_nof_muxes,
+ g_nof_folds => g_nof_folds - 1,
+ g_output_block_size => g_output_block_size,
+ g_fwd_sync_bsn => g_fwd_sync_bsn,
+ g_use_channel => g_use_channel
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in_arr => mux_src_out_arr,
+ src_out_arr => dp_folder_src_out_arr
+ );
src_out_arr <= dp_folder_src_out_arr;
@@ -195,20 +195,20 @@ begin
gen_ctrl : if g_output_block_size > 0 generate
gen_dp_block_gen : for i in 0 to c_nof_muxes - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_output_block_size,
- g_preserve_sync => true,
- g_preserve_bsn => true,
- g_preserve_channel => g_use_channel
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => dp_block_gen_snk_in_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_output_block_size,
+ g_preserve_sync => true,
+ g_preserve_bsn => true,
+ g_preserve_channel => g_use_channel
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_block_gen_snk_in_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -222,20 +222,20 @@ begin
gen_sync_bsn : if g_fwd_sync_bsn = true generate
gen_dp_fifo_info: for i in 0 to c_nof_muxes - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
index 43f175cd0c..b695e66819 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
@@ -61,10 +61,10 @@
-- then the force_data is void.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_force_data_parallel is
generic (
@@ -101,8 +101,8 @@ end dp_force_data_parallel;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_force_data_parallel is
@@ -150,19 +150,19 @@ begin
end process;
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => data_in,
- -- ST source
- src_in => src_in,
- src_out => data_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => data_in,
+ -- ST source
+ src_in => src_in,
+ src_out => data_out
+ );
src_out <= data_out;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
index c42bffb0ee..6dd8301f1c 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
@@ -76,10 +76,10 @@
-- then the force_data is void.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_force_data_serial is
generic (
@@ -127,18 +127,18 @@ begin
force_zero <= not force_zero_n;
u_common_counter : entity common_lib.common_counter
- generic map (
- g_latency => 0, -- default 1 for registered count output, use 0 for immediate combinatorial count output
- g_width => c_cnt_w,
- g_max => g_index_period
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_latency => 0, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => c_cnt_w,
+ g_max => g_index_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
p_comb : process(snk_in, cnt, force_en, force_index, force_value, force_zero, force_data, force_re, force_im)
begin
@@ -165,18 +165,18 @@ begin
end process;
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => data_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => data_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame.vhd b/libraries/base/dp/src/vhdl/dp_frame.vhd
index 27cc63b903..38e072a0e8 100644
--- a/libraries/base/dp/src/vhdl/dp_frame.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
-- Reuse from LOFAR rad_frame.vhd and rad_frame(rtl).vhd
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
index 70a5a265d8..de7cc4111c 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
@@ -27,9 +27,9 @@
-- Use g_pipeline > 0 to register snk_in_busy to ease timing closure.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_busy is
generic (
@@ -51,31 +51,31 @@ architecture str of dp_frame_busy is
begin
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '0', -- Defines the output level at reset.
- g_priority_lo => true, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_in.sop, -- A pulse on switch_high makes the out_level go high
- switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
- out_level => busy
- );
+ generic map (
+ g_rst_level => '0', -- Defines the output level at reset.
+ g_priority_lo => true, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_in.sop, -- A pulse on switch_high makes the out_level go high
+ switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
+ out_level => busy
+ );
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline, -- 0 for wires, > 0 for registers,
- g_reset_value => 0, -- 0 or 1, bit reset value,
- g_out_invert => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => busy,
- out_dat => snk_in_busy
- );
+ generic map (
+ g_pipeline => g_pipeline, -- 0 for wires, > 0 for registers,
+ g_reset_value => 0, -- 0 or 1, bit reset value,
+ g_out_invert => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => busy,
+ out_dat => snk_in_busy
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
index 066cc3ec50..4d169b1d1c 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
@@ -24,8 +24,8 @@
-- See dp_frame_busy.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_busy_arr is
generic (
@@ -46,15 +46,15 @@ begin
gen_nof_inputs : for I in 0 to g_nof_inputs - 1 generate
u_dp_frame_busy : entity work.dp_frame_busy
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in => snk_in_arr(I),
- snk_in_busy => snk_in_busy_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in => snk_in_arr(I),
+ snk_in_busy => snk_in_busy_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
index f4d5cc2b5c..95721a4736 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Reuse from LOFAR rad_frame_hdr.vhd and rad_frame_hdr(rtl).vhd
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
index 512e5f8c7f..dbd298574f 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
@@ -23,7 +23,7 @@
-- Reuse from LOFAR rad_rdframe.vhd and rad_rdframe(rtl).vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
-- Read or flush one frame from a FIFO.
@@ -217,7 +217,7 @@ begin
end process;
next_out_throttle <= nxt_out_throttle; -- note next_out_throttle high in is same cycle as out_throttle when g_throttle_den=1
- -- else next_out_throttle is high one cycle before out_throttle when g_throttle_den>1
+ -- else next_out_throttle is high one cycle before out_throttle when g_throttle_den>1
p_frm_cnt : process(frm_cnt, frm_req, nxt_frm_done)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
index ea3baac904..ce743e2dce 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_remove is
generic (
@@ -68,60 +68,60 @@ begin
no_bypass : if g_internal_bypass = false generate
u_dp_latency_adpapter: entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_snk_latency,
- g_out_latency => 1
- )
- port map (
- rst => st_rst,
- clk => st_clk,
+ generic map (
+ g_in_latency => g_snk_latency,
+ g_out_latency => 1
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
- snk_out => snk_out,
- snk_in => snk_in,
+ snk_out => snk_out,
+ snk_in => snk_in,
- src_out => snk_in_rl_1,
- src_in => snk_out_rl_1
- );
+ src_out => snk_in_rl_1,
+ src_in => snk_out_rl_1
+ );
u_dp_hdr_remove : entity work.dp_hdr_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_nof_words => g_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_nof_words => g_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- snk_out => snk_out_rl_1,
- snk_in => snk_in_rl_1,
+ snk_out => snk_out_rl_1,
+ snk_in => snk_in_rl_1,
- sla_in => sla_in,
- sla_out => sla_out,
+ sla_in => sla_in,
+ sla_out => sla_out,
- src_in => hdr_rem_siso,
- src_out => hdr_rem_sosi
- );
+ src_in => hdr_rem_siso,
+ src_out => hdr_rem_sosi
+ );
u_dp_tail_remove : entity work.dp_tail_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => c_tail_nof_symbols
- )
- port map (
- st_rst => st_rst,
- st_clk => st_clk,
-
- snk_out => hdr_rem_siso,
- snk_in => hdr_rem_sosi,
-
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => c_tail_nof_symbols
+ )
+ port map (
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ snk_out => hdr_rem_siso,
+ snk_in => hdr_rem_sosi,
+
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
index f730ceecbe..8286993ed8 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
@@ -22,8 +22,8 @@
-- Reuse from LOFAR rad_frame_repack.vhd and rad_frame_repack(rtl).vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity dp_frame_repack is
@@ -67,7 +67,7 @@ begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -75,67 +75,67 @@ begin
gen_pack : if g_in_nof_words /= g_out_nof_words generate
unframe : entity work.dp_unframe
- generic map (
- g_dat_w => g_in_dat_w,
- g_fsn_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_dat,
- in_val => in_val,
- in_sof => in_sof,
- in_eof => in_eof,
- out_fsn => pack_fsn,
- out_sync => OPEN,
- out_dat => pack_dat,
- out_val => pack_val,
- out_sof => pack_sof,
- out_eof => pack_eof,
- out_err => pack_err
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fsn_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_dat,
+ in_val => in_val,
+ in_sof => in_sof,
+ in_eof => in_eof,
+ out_fsn => pack_fsn,
+ out_sync => OPEN,
+ out_dat => pack_dat,
+ out_val => pack_val,
+ out_sof => pack_sof,
+ out_eof => pack_eof,
+ out_err => pack_err
+ );
repack : entity work.dp_repack_legacy
- generic map (
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_out_dat_w => g_out_dat_w,
- g_out_nof_words => g_out_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => pack_dat,
- in_val => pack_val,
- in_sof => pack_sof,
- in_eof => pack_eof,
- out_dat => repack_dat,
- out_val => repack_val,
- out_sof => repack_sof,
- out_eof => repack_eof
- );
+ generic map (
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_out_dat_w => g_out_dat_w,
+ g_out_nof_words => g_out_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => pack_dat,
+ in_val => pack_val,
+ in_sof => pack_sof,
+ in_eof => pack_eof,
+ out_dat => repack_dat,
+ out_val => repack_val,
+ out_sof => repack_sof,
+ out_eof => repack_eof
+ );
repack_fsn <= RESIZE_SVEC(pack_fsn,repack_fsn'length); -- pack_fsn remains valid
frame : entity work.dp_frame
- generic map (
- g_dat_w => g_out_dat_w,
- g_fsn_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_fsn => repack_fsn,
- in_dat => repack_dat,
- in_val => repack_val,
- in_sof => repack_sof,
- in_eof => repack_eof,
- in_err => pack_err, -- pack_err remains valid
- out_dat => out_dat,
- out_val => out_val,
- out_sof => out_sof,
- out_eof => out_eof
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fsn_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_fsn => repack_fsn,
+ in_dat => repack_dat,
+ in_val => repack_val,
+ in_sof => repack_sof,
+ in_eof => repack_eof,
+ in_err => pack_err, -- pack_err remains valid
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sof => out_sof,
+ out_eof => out_eof
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
index 6b03e09732..87c2af8e27 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
-- Reuse from LOFAR rad_frame_rx.vhd and rad_frame_rx(rtl).vhd
@@ -142,10 +142,11 @@ architecture rtl of dp_frame_rx is
signal nxt_flush_en : std_logic;
signal flush_val : std_logic;
- procedure proc_handle_rx_timeout(signal valid : in std_logic;
- signal timeout_evt : in std_logic;
- signal clr : out std_logic;
- variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
+ procedure proc_handle_rx_timeout (
+ signal valid : in std_logic;
+ signal timeout_evt : in std_logic;
+ signal clr : out std_logic;
+ variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
begin
if valid = '1' then
clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
@@ -215,15 +216,15 @@ begin
gen_timeout : if g_timeout_w > 0 generate
u_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_timeout_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => timeout_cnt_clr,
- count => timeout_cnt
- );
+ generic map (
+ g_width => c_timeout_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => timeout_cnt_clr,
+ count => timeout_cnt
+ );
timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
diff --git a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
index 9488c327fb..23b48c2c64 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
@@ -41,11 +41,11 @@
-- they are written into the input FIFO.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_frame_scheduler is
generic (
@@ -161,16 +161,16 @@ begin
wr_siso(I).xon <= not in_dis(I);
u_xonoff : entity work.dp_xonoff
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => OPEN,
- in_sosi => snk_in(I),
- -- Frame out
- out_siso => wr_siso(I), -- flush control via xon, ready is not used and only passed on
- out_sosi => wr_sosi(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => OPEN,
+ in_sosi => snk_in(I),
+ -- Frame out
+ out_siso => wr_siso(I), -- flush control via xon, ready is not used and only passed on
+ out_sosi => wr_sosi(I)
+ );
-- Input FIFO
rd_siso(I).ready <= rd_req(I);
@@ -181,31 +181,31 @@ begin
rd_eof(I) <= rd_sosi(I).eop;
u_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_dat_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_fifo_fill => c_fifo_fill(I),
- g_fifo_size => c_fifo_size(I),
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => wr_sosi(I),
- -- ST source
- src_in => rd_siso(I), -- IN = request from downstream ST sink
- src_out => rd_sosi(I),
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_dat_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_fifo_fill => c_fifo_fill(I),
+ g_fifo_size => c_fifo_size(I),
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => wr_sosi(I),
+ -- ST source
+ src_in => rd_siso(I), -- IN = request from downstream ST sink
+ src_out => rd_sosi(I),
- wr_ful => gp_out(I)
- );
+ wr_ful => gp_out(I)
+ );
end generate;
-- Output select
diff --git a/libraries/base/dp/src/vhdl/dp_frame_status.vhd b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
index f8562ab914..6b04ca8988 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_status.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
@@ -31,9 +31,9 @@
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity dp_frame_status is
generic (
@@ -130,33 +130,33 @@ begin
-- frame sync detection
u_fsync_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => fsync, -- frame sync
- switch_low => sync_dly, -- system sync
- out_level => fsync_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => fsync, -- frame sync
+ switch_low => sync_dly, -- system sync
+ out_level => fsync_det
+ );
-- any frame brc over fsync interval
u_brc_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => brc, -- frame brc
- switch_low => fsync, -- frame sync
- out_level => brc_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => brc, -- frame brc
+ switch_low => fsync, -- frame sync
+ out_level => brc_det
+ );
-- any frame discarded over fsync interval
u_dis_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_dis, -- frame discarded
- switch_low => fsync, -- frame sync
- out_level => dis_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_dis, -- frame discarded
+ switch_low => fsync, -- frame sync
+ out_level => dis_det
+ );
-- frame count over fsync interval
p_frame_cnt : process(cnt, fsync, in_eof)
diff --git a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
index a16930526b..bc6b552c64 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
-- Reuse from LOFAR rad_frame_tx.vhd and rad_frame_tx(rtl).vhd
diff --git a/libraries/base/dp/src/vhdl/dp_gap.vhd b/libraries/base/dp/src/vhdl/dp_gap.vhd
index 0c5e71520f..d3c46de91d 100644
--- a/libraries/base/dp/src/vhdl/dp_gap.vhd
+++ b/libraries/base/dp/src/vhdl/dp_gap.vhd
@@ -34,17 +34,17 @@
-- valid data work comes in.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
entity dp_gap is
generic (
g_dat_len : natural := 1000000;
g_gap_len : natural := 5;
g_gap_extend : boolean := false -- if TRUE, the first valid='0' cycle is extended to g_gap_len by de-assertion of snk_out.ready.
- ); -- This results in all gaps having a minimum length of g_gap_len.
+ ); -- This results in all gaps having a minimum length of g_gap_len.
port (
clk : in std_logic;
rst : in std_logic;
@@ -101,45 +101,45 @@ begin
case state is
- when s_wait_for_val => -- Wait for valid data to come in
- if snk_in.valid = '1' then
- nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w);
- nxt_gap_cnt <= (others => '0');
- nxt_state <= s_counting;
- end if;
-
- when s_counting => -- Start counting cycles
- nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
- if clk_cnt = TO_UVEC(g_dat_len - 1, c_dat_len_w) then -- time to force a gap
- nxt_state <= s_force_not_rdy;
- snk_out.ready <= '0';
- nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w); -- we already have 1 clk cycle with ready='0' here
- end if;
- if snk_in.valid = '0' then -- Also start counting any invalid cycles
- if g_gap_extend = true then
- snk_out.ready <= '0'; -- Keep ready de-asserted. Gap_cnt will increment so it will be released again after g_gap_len.
+ when s_wait_for_val => -- Wait for valid data to come in
+ if snk_in.valid = '1' then
+ nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w);
+ nxt_gap_cnt <= (others => '0');
+ nxt_state <= s_counting;
+ end if;
+
+ when s_counting => -- Start counting cycles
+ nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
+ if clk_cnt = TO_UVEC(g_dat_len - 1, c_dat_len_w) then -- time to force a gap
+ nxt_state <= s_force_not_rdy;
+ snk_out.ready <= '0';
+ nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w); -- we already have 1 clk cycle with ready='0' here
+ end if;
+ if snk_in.valid = '0' then -- Also start counting any invalid cycles
+ if g_gap_extend = true then
+ snk_out.ready <= '0'; -- Keep ready de-asserted. Gap_cnt will increment so it will be released again after g_gap_len.
+ end if;
+ nxt_gap_cnt <= INCR_UVEC(gap_cnt, 1);
+ else
+ nxt_gap_cnt <= (others => '0');
end if;
- nxt_gap_cnt <= INCR_UVEC(gap_cnt, 1);
- else
- nxt_gap_cnt <= (others => '0');
- end if;
- if gap_cnt = TO_UVEC(g_gap_len - 1, c_gap_len_w) and snk_in.valid = '0' then -- A gap of sufficient length occured by itself (or valid='0' was extended); no need to force gap
- -- We've counted g_gap_len-1, plus the current gap cycle = g_gap_len
- nxt_gap_cnt <= (others => '0');
- nxt_clk_cnt <= (others => '0');
- nxt_state <= s_wait_for_val;
- if g_gap_extend = true then
- snk_out.ready <= src_in.ready; -- Release the ready signal again if it was forced down because of gap extension
+ if gap_cnt = TO_UVEC(g_gap_len - 1, c_gap_len_w) and snk_in.valid = '0' then -- A gap of sufficient length occured by itself (or valid='0' was extended); no need to force gap
+ -- We've counted g_gap_len-1, plus the current gap cycle = g_gap_len
+ nxt_gap_cnt <= (others => '0');
+ nxt_clk_cnt <= (others => '0');
+ nxt_state <= s_wait_for_val;
+ if g_gap_extend = true then
+ snk_out.ready <= src_in.ready; -- Release the ready signal again if it was forced down because of gap extension
+ end if;
+ end if;
+
+ when s_force_not_rdy => -- Force snk_out.ready to '0' for g_gap_len clk cycles
+ snk_out.ready <= '0';
+ nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
+ if clk_cnt = TO_UVEC(g_gap_len - 1, c_dat_len_w) then
+ nxt_state <= s_wait_for_val;
+ nxt_clk_cnt <= (others => '0');
end if;
- end if;
-
- when s_force_not_rdy => -- Force snk_out.ready to '0' for g_gap_len clk cycles
- snk_out.ready <= '0';
- nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
- if clk_cnt = TO_UVEC(g_gap_len - 1, c_dat_len_w) then
- nxt_state <= s_wait_for_val;
- nxt_clk_cnt <= (others => '0');
- end if;
end case;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
index 2b8996552a..e60a2dc907 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
@@ -25,10 +25,10 @@
-- and g_symbol_w.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_hdr_insert is
generic (
@@ -71,25 +71,25 @@ begin
no_bypass: if g_internal_bypass = false generate
u_dp_ram_from_mm : entity work.mms_dp_ram_from_mm
- generic map (
- g_ram_wr_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
- g_ram_rd_dat_w => g_data_w,
- g_init_file => g_init_hdr,
- g_dp_on_at_init => g_dp_on_at_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- reg_mosi => reg_mosi,
- ram_mosi => ram_mosi,
-
- src_in => hdr_siso,
- src_out => hdr_sosi
- );
+ generic map (
+ g_ram_wr_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
+ g_ram_rd_dat_w => g_data_w,
+ g_init_file => g_init_hdr,
+ g_dp_on_at_init => g_dp_on_at_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ reg_mosi => reg_mosi,
+ ram_mosi => ram_mosi,
+
+ src_in => hdr_siso,
+ src_out => hdr_sosi
+ );
hdr_siso <= concat_siso_arr(0);
snk_out <= concat_siso_arr(1);
@@ -97,20 +97,20 @@ begin
concat_sosi_arr(1) <= snk_in;
u_dp_concat : entity work.dp_concat -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out_arr => concat_siso_arr,
- snk_in_arr => concat_sosi_arr,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out_arr => concat_siso_arr,
+ snk_in_arr => concat_sosi_arr,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
index dec86251ea..4c3a889758 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_hdr_remove is
generic (
@@ -61,42 +61,42 @@ architecture str of dp_hdr_remove is
begin
u_dp_ram_to_mm : entity work.dp_ram_to_mm
- generic map (
- g_ram_rd_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
- g_ram_wr_dat_w => g_data_w
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_out => sla_out,
- sla_in => sla_in,
-
- snk_in => split_sosi_arr(0),
- snk_out => split_siso_arr(0)
- );
+ generic map (
+ g_ram_rd_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
+ g_ram_wr_dat_w => g_data_w
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_out => sla_out,
+ sla_in => sla_in,
+
+ snk_in => split_sosi_arr(0),
+ snk_out => split_siso_arr(0)
+ );
split_siso_arr(1) <= src_in;
src_out <= split_sosi_arr(1);
u_split : entity work.dp_split -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => c_nof_symbols
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in_arr => split_siso_arr,
- src_out_arr => split_sosi_arr
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => c_nof_symbols
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in_arr => split_siso_arr,
+ src_out_arr => split_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
index 20e2217497..b9ee8deea3 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
-- Hold hld_ctrl active until next ready high when in_ctrl is active while
@@ -59,12 +59,12 @@ begin
lo_ctrl <= not in_ctrl and ready; -- release
u_hld_ctrl : entity common_lib.common_switch
- port map (
- rst => rst,
- clk => clk,
- switch_high => hi_ctrl,
- switch_low => lo_ctrl,
- out_level => hld_ctrl
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => hi_ctrl,
+ switch_low => lo_ctrl,
+ out_level => hld_ctrl
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_data.vhd b/libraries/base/dp/src/vhdl/dp_hold_data.vhd
index 98eeac0af0..f4b611937f 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_data.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
-- Hold the in_data value when in_en is inactive. The held data can then be
diff --git a/libraries/base/dp/src/vhdl/dp_hold_input.vhd b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
index 14ec716ede..f34dffeb4e 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_input.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Hold the sink input
@@ -94,40 +94,40 @@ begin
-- of a next packet to get pushed out.
u_hold_val : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.valid,
- hld_ctrl => hold_in.valid
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.valid,
+ hld_ctrl => hold_in.valid
+ );
u_hold_sync : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.sync,
- hld_ctrl => hold_in.sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.sync,
+ hld_ctrl => hold_in.sync
+ );
u_hold_sop : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.sop,
- hld_ctrl => hold_in.sop
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.sop,
+ hld_ctrl => hold_in.sop
+ );
u_hold_eop : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.eop,
- hld_ctrl => hold_in.eop
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.eop,
+ hld_ctrl => hold_in.eop
+ );
p_pend_src_out : process(snk_in, src_out_reg, hold_in)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
index 752ddb09a9..95a7ad28e4 100755
--- a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
+++ b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Eric Kooistra
@@ -193,18 +193,18 @@ begin
-- Pipeline output to easy timing closure
u_pipeline_output : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => out_siso,
- snk_in => out_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => out_siso,
+ snk_in => out_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
index c1f762e52f..d8aae69dc9 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Adapt the g_in_latency input ready to the g_out_latency output latency.
@@ -108,20 +108,20 @@ begin
no_fifo : if c_diff_latency > 0 generate -- g_out_latency > g_in_latency
-- Go from g_in_latency to required larger g_out_latency
u_latency : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => c_diff_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => i_snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => c_diff_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => i_snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate no_fifo;
@@ -181,10 +181,10 @@ begin
nxt_fifo_reg(c_high).sync <= '0';
nxt_fifo_reg(c_high).sop <= '0';
nxt_fifo_reg(c_high).eop <= '0';
- -- Forcing the nxt_fifo_reg[h] control fields to '0' is robust, but not
- -- strictly necessary, because the control fields in fifo_reg[h] will
- -- have been set to '0' already earlier due to the snk_in when
- -- ff_siso.ready was '0'.
+ -- Forcing the nxt_fifo_reg[h] control fields to '0' is robust, but not
+ -- strictly necessary, because the control fields in fifo_reg[h] will
+ -- have been set to '0' already earlier due to the snk_in when
+ -- ff_siso.ready was '0'.
end if;
-- Put input data at the first available location dependent on ff_siso.ready, no need to explicitly check snk_in.valid
@@ -241,20 +241,20 @@ begin
-- Go from 0 FIFO latency to required g_out_latency (only wires when g_out_latency=0)
u_latency : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => ff_siso,
- snk_in => ff_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => ff_siso,
+ snk_in => ff_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate gen_fifo;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
index dafab5c55e..bdf961839a 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose: Simple DP fifo in registers.
-- Description:
@@ -106,24 +106,24 @@ begin
wr_ful <= not i_snk_out.ready;
u_dp_latency_adapter : entity work.dp_latency_adapter
- generic map (
- g_in_latency => c_adapter_input_rl,
- g_out_latency => c_adapter_output_rl
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor internal FIFO filling
- fifo_usedw => i_usedw,
- fifo_ful => OPEN,
- fifo_emp => rd_emp,
- -- ST sink
- snk_out => fifo_snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => c_adapter_input_rl,
+ g_out_latency => c_adapter_output_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor internal FIFO filling
+ fifo_usedw => i_usedw,
+ fifo_ful => OPEN,
+ fifo_emp => rd_emp,
+ -- ST sink
+ snk_out => fifo_snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
index 60f10f3d20..145a525889 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Typically used in dp_latency_adapter.
diff --git a/libraries/base/dp/src/vhdl/dp_loopback.vhd b/libraries/base/dp/src/vhdl/dp_loopback.vhd
index 55a9436316..5779680798 100644
--- a/libraries/base/dp/src/vhdl/dp_loopback.vhd
+++ b/libraries/base/dp/src/vhdl/dp_loopback.vhd
@@ -19,10 +19,10 @@
--
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- General function:
-- =================
@@ -145,84 +145,84 @@ begin
demux_1_siso_arr(2) <= c_dp_siso_flush;
u_dp_demux_0: entity work.dp_demux
- generic map (
- g_mode => 2,
- g_nof_output => c_nof_demux_out,
- g_combined => false,
- g_sel_ctrl_invert => true,
- g_sel_ctrl_pkt => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => snk_out_arr(0),
- snk_in => snk_in_arr(0),
-
- src_in_arr => demux_0_siso_arr,
- src_out_arr => demux_0_sosi_arr,
-
- sel_ctrl => demux_0_sel_ctrl,
- sel_stat => demux_0_sel_stat
- );
+ generic map (
+ g_mode => 2,
+ g_nof_output => c_nof_demux_out,
+ g_combined => false,
+ g_sel_ctrl_invert => true,
+ g_sel_ctrl_pkt => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => snk_out_arr(0),
+ snk_in => snk_in_arr(0),
+
+ src_in_arr => demux_0_siso_arr,
+ src_out_arr => demux_0_sosi_arr,
+
+ sel_ctrl => demux_0_sel_ctrl,
+ sel_stat => demux_0_sel_stat
+ );
u_dp_demux_1: entity work.dp_demux
- generic map (
- g_mode => 2,
- g_nof_output => c_nof_demux_out,
- g_combined => false,
- g_sel_ctrl_invert => true,
- g_sel_ctrl_pkt => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => snk_out_arr(1),
- snk_in => snk_in_arr(1),
-
- src_in_arr => demux_1_siso_arr,
- src_out_arr => demux_1_sosi_arr,
-
- sel_ctrl => demux_1_sel_ctrl,
- sel_stat => demux_1_sel_stat
- );
+ generic map (
+ g_mode => 2,
+ g_nof_output => c_nof_demux_out,
+ g_combined => false,
+ g_sel_ctrl_invert => true,
+ g_sel_ctrl_pkt => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => snk_out_arr(1),
+ snk_in => snk_in_arr(1),
+
+ src_in_arr => demux_1_siso_arr,
+ src_out_arr => demux_1_sosi_arr,
+
+ sel_ctrl => demux_1_sel_ctrl,
+ sel_stat => demux_1_sel_stat
+ );
u_dp_mux_0 : entity work.dp_mux
- generic map (
- g_mode => 2,
- g_sel_ctrl_invert => true
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_mode => 2,
+ g_sel_ctrl_invert => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out_arr => mux_0_siso_arr,
- snk_in_arr => mux_0_sosi_arr,
+ snk_out_arr => mux_0_siso_arr,
+ snk_in_arr => mux_0_sosi_arr,
- src_in => src_in_arr(0),
- src_out => src_out_arr(0),
+ src_in => src_in_arr(0),
+ src_out => src_out_arr(0),
- sel_ctrl => mux_0_sel_ctrl
- );
+ sel_ctrl => mux_0_sel_ctrl
+ );
u_dp_mux_1 : entity work.dp_mux
- generic map (
- g_mode => 2,
- g_sel_ctrl_invert => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out_arr => mux_1_siso_arr,
- snk_in_arr => mux_1_sosi_arr,
-
- src_in => src_in_arr(1),
- src_out => src_out_arr(1),
-
- sel_ctrl => mux_1_sel_ctrl
- );
+ generic map (
+ g_mode => 2,
+ g_sel_ctrl_invert => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out_arr => mux_1_siso_arr,
+ snk_in_arr => mux_1_sosi_arr,
+
+ src_in => src_in_arr(1),
+ src_out => src_out_arr(1),
+
+ sel_ctrl => mux_1_sel_ctrl
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_mon.vhd b/libraries/base/dp/src/vhdl/dp_mon.vhd
index 69b0e55d70..0b312f5bb1 100644
--- a/libraries/base/dp/src/vhdl/dp_mon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mon.vhd
@@ -23,10 +23,10 @@
-- passing stream in any way - it monitors the stream and keeps useful stats.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_mon is
generic (
@@ -63,18 +63,18 @@ begin
snk_accept <= snk_in.valid when g_latency > 0 else snk_in.valid and src_in.ready;
u_word_cntr : entity common_lib.common_counter
- generic map (
- g_width => 32,
- g_step_size => 1,
- g_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => clr,
- cnt_en => snk_accept,
- count => word_cnt
- );
+ generic map (
+ g_width => 32,
+ g_step_size => 1,
+ g_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => clr,
+ cnt_en => snk_accept,
+ count => word_cnt
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index ce42b95054..a3ffaaf54f 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -79,11 +79,11 @@
-- use g_append_channel_lo=FALSE in combination with g_mode=2.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_mux is
generic (
@@ -215,34 +215,34 @@ begin
gen_input : for I in 0 to g_nof_input - 1 generate
gen_fifo : if g_use_fifo = true generate
u_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_in_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_in_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_fill => c_fifo_fill(I),
- g_fifo_size => c_fifo_size(I),
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => i_snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => rd_siso_arr(I),
- src_out => rd_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_in_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_in_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_fill => c_fifo_fill(I),
+ g_fifo_size => c_fifo_size(I),
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => i_snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => rd_siso_arr(I),
+ src_out => rd_sosi_arr(I)
+ );
end generate;
no_fifo : if g_use_fifo = false generate
i_snk_out_arr <= rd_siso_arr;
@@ -251,18 +251,18 @@ begin
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN, -- SISO ready
- snk_in => rd_sosi_arr(I), -- SOSI
- -- ST source
- src_in => hold_src_in_arr(I), -- SISO ready
- next_src_out => next_src_out_arr(I), -- SOSI
- pend_src_out => pend_src_out_arr(I),
- src_out_reg => src_out_hi
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN, -- SISO ready
+ snk_in => rd_sosi_arr(I), -- SOSI
+ -- ST source
+ src_in => hold_src_in_arr(I), -- SISO ready
+ next_src_out => next_src_out_arr(I), -- SOSI
+ pend_src_out => pend_src_out_arr(I),
+ src_out_reg => src_out_hi
+ );
end generate;
-- Register and adjust external MM sel_ctrl for g_sel_ctrl_invert
@@ -292,16 +292,16 @@ begin
gen_sel_ctrl_framed : if g_mode = 4 generate
u_dp_frame_busy_arr : entity work.dp_frame_busy_arr
- generic map (
- g_nof_inputs => g_nof_input,
- g_pipeline => 1 -- register snk_in_busy to ease timing closure
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in_arr => rd_sosi_arr,
- snk_in_busy_arr => rd_sosi_busy_arr
- );
+ generic map (
+ g_nof_inputs => g_nof_input,
+ g_pipeline => 1 -- register snk_in_busy to ease timing closure
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in_arr => rd_sosi_arr,
+ snk_in_busy_arr => rd_sosi_busy_arr
+ );
hold_src_in_arr <= (others => c_dp_siso_rdy); -- effectively bypass the dp_hold_input
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
index 42206bf7ba..6afc91c6c6 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
@@ -41,12 +41,12 @@
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx is
generic (
@@ -114,21 +114,21 @@ begin
---------------------------------------------------------------------------------------
gen_nof_streams: for i in 0 to g_nof_streams - 1 generate
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_symbol_w,
- g_nof_symbols => c_nof_header_symbols
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
-
- src_in_arr => dp_split_src_in_2arr(i),
- src_out_arr => dp_split_src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_symbol_w,
+ g_nof_symbols => c_nof_header_symbols
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+
+ src_in_arr => dp_split_src_in_2arr(i),
+ src_out_arr => dp_split_src_out_2arr(i)
+ );
-- In dp_split index 0 is head and index 1 is tail, but dp_split uses 0 TO
-- 1 range and dp_split_src_in_2arr()() uses 1 DOWNTO 0 range, so:
@@ -143,32 +143,32 @@ begin
---------------------------------------------------------------------------------------
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RO"),
- g_field_sel => c_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w, -- g_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w, -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
- g_in_symbol_w => c_symbol_w,
- g_out_symbol_w => c_symbol_w,
- g_mode => 2 -- sink mode
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RO"),
+ g_field_sel => c_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w, -- g_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w, -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
+ g_in_symbol_w => c_symbol_w,
+ g_out_symbol_w => c_symbol_w,
+ g_mode => 2 -- sink mode
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- snk_in => dp_split_src_out_2arr(i)(1),
+ snk_in => dp_split_src_out_2arr(i)(1),
- src_out => dp_field_blk_src_out_arr(i),
+ src_out => dp_field_blk_src_out_arr(i),
--- slv_out => dp_field_blk_slv_out(i)(field_slv_len(g_hdr_field_arr)-1 DOWNTO 0),
--- slv_out_val => dp_field_blk_slv_out_val(i),
+ -- slv_out => dp_field_blk_slv_out(i)(field_slv_len(g_hdr_field_arr)-1 DOWNTO 0),
+ -- slv_out_val => dp_field_blk_slv_out_val(i),
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_slv_out(i)(c_dp_field_blk_src_data_w - 1 downto 0) <= dp_field_blk_src_out_arr(i).data(c_dp_field_blk_src_data_w - 1 downto 0);
dp_field_blk_slv_out_val(i) <= dp_field_blk_src_out_arr(i).valid;
@@ -180,21 +180,21 @@ begin
---------------------------------------------------------------------------------------
gen_dp_tail_remove : for i in 0 to g_nof_streams - 1 generate
u_dp_tail_remove : entity work.dp_tail_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_symbol_w,
- g_nof_symbols => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
- )
- port map (
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- snk_out => dp_split_src_in_2arr(i)(0),
- snk_in => dp_split_src_out_2arr(i)(0), -- tail part
-
- src_in => dp_tail_remove_src_in_arr(i),
- src_out => dp_tail_remove_src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_symbol_w,
+ g_nof_symbols => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
+ )
+ port map (
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ snk_out => dp_split_src_in_2arr(i)(0),
+ snk_in => dp_split_src_out_2arr(i)(0), -- tail part
+
+ src_in => dp_tail_remove_src_in_arr(i),
+ src_out => dp_tail_remove_src_out_arr(i)
+ );
end generate;
src_out_arr <= dp_tail_remove_src_out_arr;
@@ -229,15 +229,15 @@ begin
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
index 4e55f098cd..a42657738b 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx_filter is
generic (
- g_bypass : boolean := false;
+ g_bypass : boolean := false;
g_nof_streams : positive := 1;
g_data_w : natural;
g_hdr_field_arr : t_common_field_arr;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
index 4a1a1bbd76..17fb7b72e7 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx_filter_mm is
generic (
@@ -68,9 +68,9 @@ architecture str of dp_offload_rx_filter_mm is
constant c_field_slv_out_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr , "RW"));
- constant c_nof_ena : natural := 4;
- constant c_reg_w : natural := c_nof_ena * c_word_w;
- constant c_adr_w : natural := ceil_log2(c_nof_ena);
+ constant c_nof_ena : natural := 4;
+ constant c_reg_w : natural := c_nof_ena * c_word_w;
+ constant c_adr_w : natural := ceil_log2(c_nof_ena);
constant c_ena_reg : t_c_mem := (1, c_adr_w, 32, c_nof_ena, '0');
subtype eth_dst_mac_range is natural range field_hi(g_hdr_field_arr, "eth_dst_mac" ) downto field_lo(g_hdr_field_arr, "eth_dst_mac");
@@ -87,13 +87,13 @@ architecture str of dp_offload_rx_filter_mm is
signal mult_streams_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal mult_streams_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
- signal common_mosi_arr : t_mem_mosi_arr(1 downto 0);
- signal common_miso_arr : t_mem_miso_arr(1 downto 0);
+ signal common_mosi_arr : t_mem_mosi_arr(1 downto 0);
+ signal common_miso_arr : t_mem_miso_arr(1 downto 0);
type t_bool_arr is array (integer range <>) of boolean;
type t_reg_sig_arr is array (integer range <>) of std_logic_vector(c_reg_w - 1 downto 0);
- signal reg_ena_sig : t_reg_sig_arr(g_nof_streams - 1 downto 0);
+ signal reg_ena_sig : t_reg_sig_arr(g_nof_streams - 1 downto 0);
signal eth_dst_mac_ena : t_bool_arr(g_nof_streams - 1 downto 0);
signal ip_dst_addr_ena : t_bool_arr(g_nof_streams - 1 downto 0);
@@ -174,84 +174,84 @@ begin
end process;
- -------------------------------------------
- -- mm_fields for MM access to each field --
- -------------------------------------------
+ -------------------------------------------
+ -- mm_fields for MM access to each field --
+ -------------------------------------------
u_mult_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w)) + 1
- )
- port map (
- mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
- miso => reg_dp_offload_rx_filter_hdr_fields_miso,
- mosi_arr => mult_streams_mosi_arr,
- miso_arr => mult_streams_miso_arr
- );
-
- gen_mm_fields : for i in 0 to g_nof_streams - 1 generate
-
- u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
- g_nof_mosi => 2,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w)) + 1
)
port map (
- mosi => mult_streams_mosi_arr(i),
- miso => mult_streams_miso_arr(i),
- mosi_arr => common_mosi_arr,
- miso_arr => common_miso_arr
+ mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
+ miso => reg_dp_offload_rx_filter_hdr_fields_miso,
+ mosi_arr => mult_streams_mosi_arr,
+ miso_arr => mult_streams_miso_arr
);
+ gen_mm_fields : for i in 0 to g_nof_streams - 1 generate
+
+ u_common_mem_mux : entity common_lib.common_mem_mux
+ generic map (
+ g_nof_mosi => 2,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => mult_streams_mosi_arr(i),
+ miso => mult_streams_miso_arr(i),
+ mosi_arr => common_mosi_arr,
+ miso_arr => common_miso_arr
+ );
+
eth_dst_mac_ena(i) <= is_true(reg_ena_sig(i)(0));
- ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
- ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
- udp_dst_port_ena(i) <= is_true(reg_ena_sig(i)(96));
+ ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
+ ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
+ udp_dst_port_ena(i) <= is_true(reg_ena_sig(i)(96));
cr : entity common_lib.common_reg_r_w_dc
- generic map(
- g_reg => c_ena_reg
- )
-
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
- st_rst => dp_rst, -- reset synchronous with st_clk
- st_clk => dp_clk, -- other clock domain clock
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
- sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => OPEN,
- in_reg => reg_ena_sig(i),
- out_reg => reg_ena_sig(i),
- out_new => open
- );
+ generic map(
+ g_reg => c_ena_reg
+ )
+
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+ st_rst => dp_rst, -- reset synchronous with st_clk
+ st_clk => dp_clk, -- other clock domain clock
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
+ sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => OPEN,
+ in_reg => reg_ena_sig(i),
+ out_reg => reg_ena_sig(i),
+ out_new => open
+ );
u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_mosi => common_mosi_arr(0),
- mm_miso => common_miso_arr(0),
-
- slv_clk => dp_clk,
- slv_rst => dp_rst,
-
- slv_in => mm_fields_slv_in_arr(i),
- slv_in_val => hdr_fields_val,
- slv_out => mm_fields_slv_out_arr(i)
- );
+ generic map(
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_mosi => common_mosi_arr(0),
+ mm_miso => common_miso_arr(0),
+
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
+
+ slv_in => mm_fields_slv_in_arr(i),
+ slv_in_val => hdr_fields_val,
+ slv_out => mm_fields_slv_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
index d9ac55a4e7..975dfaf6d1 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_offload_rx_legacy is
generic (
@@ -67,16 +67,16 @@ architecture str of dp_offload_rx_legacy is
begin
u_common_mem_mux_hdr_ram : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_remove_ram_addr_w
- )
- port map (
- mosi => ram_hdr_remove_mosi,
- miso => ram_hdr_remove_miso,
- mosi_arr => ram_hdr_remove_mosi_arr,
- miso_arr => ram_hdr_remove_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_remove_ram_addr_w
+ )
+ port map (
+ mosi => ram_hdr_remove_mosi,
+ miso => ram_hdr_remove_miso,
+ mosi_arr => ram_hdr_remove_mosi_arr,
+ miso_arr => ram_hdr_remove_miso_arr
+ );
gen_nof_streams: for i in 0 to g_nof_streams - 1 generate
@@ -84,47 +84,47 @@ begin
-- RX: Unframe: remove header (and CRC if phy link is used) from DP packets
---------------------------------------------------------------------------------------
u_frame_remove : entity dp_lib.dp_frame_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_nof_words => g_hdr_nof_words,
- g_tail_nof_words => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- snk_out => rx_siso_arr(i),
- snk_in => rx_sosi_arr(i),
-
- -- dp_frame_remove uses hdr_remove internally
- sla_in => ram_hdr_remove_mosi_arr(i),
- sla_out => ram_hdr_remove_miso_arr(i),
-
- src_in => rx_pkt_siso_arr(i),
- src_out => rx_pkt_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_nof_words => g_hdr_nof_words,
+ g_tail_nof_words => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ snk_out => rx_siso_arr(i),
+ snk_in => rx_sosi_arr(i),
+
+ -- dp_frame_remove uses hdr_remove internally
+ sla_in => ram_hdr_remove_mosi_arr(i),
+ sla_out => ram_hdr_remove_miso_arr(i),
+
+ src_in => rx_pkt_siso_arr(i),
+ src_out => rx_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- RX: Convert DP packets to DP stream
---------------------------------------------------------------------------------------
u_dp_packet_dec : entity dp_lib.dp_packet_dec
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => rx_pkt_siso_arr(i),
- snk_in => rx_pkt_sosi_arr(i),
-
- src_in => dp_siso_arr(i),
- src_out => dp_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => rx_pkt_siso_arr(i),
+ snk_in => rx_pkt_sosi_arr(i),
+
+ src_in => dp_siso_arr(i),
+ src_out => dp_sosi_arr(i)
+ );
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
index 791f83d7e5..6b34a61b70 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
@@ -41,13 +41,13 @@
-- Remarks:
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_offload_tx is
generic (
@@ -161,21 +161,21 @@ begin
snk_out_arr(i).xon <= src_in_arr(i).xon; -- Pass on XON from source side
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_nof_symbols => g_nof_words_per_block
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => dp_split_snk_out_arr(i),
- snk_in => dp_split_snk_in_arr(i),
-
- src_in_arr => dp_split_src_in_2arr(i),
- src_out_arr => dp_split_src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_nof_symbols => g_nof_words_per_block
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_split_snk_out_arr(i),
+ snk_in => dp_split_snk_in_arr(i),
+
+ src_in_arr => dp_split_src_in_2arr(i),
+ src_out_arr => dp_split_src_out_2arr(i)
+ );
dp_split_src_in_2arr(i)(0) <= c_dp_siso_rdy; -- Always ready to throw away the tail
@@ -183,58 +183,58 @@ begin
-- Introduce the same delay (as dp_plit) on the corresponding header fields
u_dp_pipeline_arr_dp_split : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_dp_split_val_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => dp_split_hdr_fields_snk_in_arr,
- snk_out_arr => OPEN, -- Flow control is already taken care of by dp_split
-
- src_out_arr => dp_split_hdr_fields_src_out_arr,
- src_in_arr => dp_split_hdr_fields_src_in_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_dp_split_val_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => dp_split_hdr_fields_snk_in_arr,
+ snk_out_arr => OPEN, -- Flow control is already taken care of by dp_split
+
+ src_out_arr => dp_split_hdr_fields_src_out_arr,
+ src_in_arr => dp_split_hdr_fields_src_in_arr
+ );
---------------------------------------------------------------------------------------
-- Merge nof_blocks_per_packet
---------------------------------------------------------------------------------------
gen_dp_packet_merge : for i in 0 to g_nof_streams - 1 generate
u_dp_packet_merge : entity work.dp_packet_merge
+ generic map (
+ g_nof_pkt => g_nof_blocks_per_packet,
+ g_align_at_sync => g_pkt_merge_align_at_sync
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_split_src_in_2arr(i)(1),
+ snk_in => dp_split_src_out_2arr(i)(1),
+
+ src_in => dp_packet_merge_src_in_arr(i),
+ src_out => dp_packet_merge_src_out_arr(i)
+ );
+ end generate;
+
+ -- Introduce the same delay (as dp_packet_merge) on the corresponding header fields
+ u_dp_pipeline_arr_dp_packet_merge : entity work.dp_pipeline_arr
generic map (
- g_nof_pkt => g_nof_blocks_per_packet,
- g_align_at_sync => g_pkt_merge_align_at_sync
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_dp_packet_merge_val_latency
)
port map (
rst => dp_rst,
clk => dp_clk,
- snk_out => dp_split_src_in_2arr(i)(1),
- snk_in => dp_split_src_out_2arr(i)(1),
+ snk_in_arr => dp_split_hdr_fields_src_out_arr,
+ snk_out_arr => dp_split_hdr_fields_src_in_arr,
- src_in => dp_packet_merge_src_in_arr(i),
- src_out => dp_packet_merge_src_out_arr(i)
+ src_out_arr => dp_packet_merge_hdr_fields_src_out_arr,
+ src_in_arr => dp_packet_merge_hdr_fields_src_in_arr
);
- end generate;
-
- -- Introduce the same delay (as dp_packet_merge) on the corresponding header fields
- u_dp_pipeline_arr_dp_packet_merge : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_dp_packet_merge_val_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => dp_split_hdr_fields_src_out_arr,
- snk_out_arr => dp_split_hdr_fields_src_in_arr,
-
- src_out_arr => dp_packet_merge_hdr_fields_src_out_arr,
- src_in_arr => dp_packet_merge_hdr_fields_src_in_arr
- );
-- dp_packet_merge_hdr_fields_src_out_arr contains a valid header for each block that was merged
-- into one packet. We want only the first valid header per merged block to be forwarded to
@@ -264,22 +264,22 @@ begin
---------------------------------------------------------------------------------------
gen_dp_fifo_fill : for i in 0 to sel_a_b(g_use_post_split_fifo, g_nof_streams, 0) - 1 generate
u_dp_fifo_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_fifo_fill => c_dp_fifo_fill,
- g_fifo_size => c_dp_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_packet_merge_src_out_arr(i),
- snk_out => dp_packet_merge_src_in_arr(i),
-
- src_out => dp_fifo_fill_src_out_arr(i),
- src_in => dp_fifo_fill_src_in_arr(i)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_fifo_fill => c_dp_fifo_fill,
+ g_fifo_size => c_dp_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_packet_merge_src_out_arr(i),
+ snk_out => dp_packet_merge_src_in_arr(i),
+
+ src_out => dp_fifo_fill_src_out_arr(i),
+ src_in => dp_fifo_fill_src_in_arr(i)
+ );
dp_fifo_fill_src_in_arr(i).ready <= dp_concat_snk_out_2arr(i)(0).ready;
dp_fifo_fill_src_in_arr(i).xon <= '1'; -- Prevents flushing of frames
@@ -299,61 +299,61 @@ begin
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_in => dp_concat_snk_out_2arr(i)(1),
- src_out => dp_concat_snk_in_2arr(i)(1),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_in => dp_concat_snk_out_2arr(i)(1),
+ src_out => dp_concat_snk_in_2arr(i)(1),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
end generate;
gen_dp_concat : for i in 0 to g_nof_streams - 1 generate
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
index b11bcefca2..26fcb2e409 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, work;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_offload_tx_legacy is
generic (
@@ -117,24 +117,24 @@ architecture str of dp_offload_tx_legacy is
begin
u_common_mem_mux_hdr_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_insert_reg_addr_w
- )
- port map (
- mosi => reg_hdr_insert_mosi,
- mosi_arr => reg_hdr_insert_mosi_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_insert_reg_addr_w
+ )
+ port map (
+ mosi => reg_hdr_insert_mosi,
+ mosi_arr => reg_hdr_insert_mosi_arr
+ );
u_common_mem_mux_hdr_ram : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_insert_ram_addr_w
- )
- port map (
- mosi => ram_hdr_insert_mosi,
- mosi_arr => ram_hdr_insert_mosi_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_insert_ram_addr_w
+ )
+ port map (
+ mosi => ram_hdr_insert_mosi,
+ mosi_arr => ram_hdr_insert_mosi_arr
+ );
gen_nof_streams0: for i in 0 to g_nof_streams - 1 generate
@@ -159,30 +159,30 @@ begin
---------------------------------------------------------------------------------------
gen_input_buffer : if g_use_input_fifo = true generate
u_buf : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => g_input_fifo_bsn_w,
- g_empty_w => g_input_fifo_empty_w,
- g_channel_w => g_input_fifo_channel_w,
- g_error_w => g_input_fifo_error_w,
- g_use_bsn => g_input_fifo_use_bsn,
- g_use_empty => g_input_fifo_use_empty,
- g_use_channel => g_input_fifo_use_channel,
- g_use_error => g_input_fifo_use_error,
- g_use_sync => g_input_fifo_use_sync,
- g_use_ctrl => true,
- g_fifo_size => 10 -- Use 10 as there's a FIFO margin
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_siso_arr(i),
- snk_in => dp_sel_sosi_arr(i),
-
- src_in => dp_to_split_siso_arr(i),
- src_out => dp_to_split_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => g_input_fifo_bsn_w,
+ g_empty_w => g_input_fifo_empty_w,
+ g_channel_w => g_input_fifo_channel_w,
+ g_error_w => g_input_fifo_error_w,
+ g_use_bsn => g_input_fifo_use_bsn,
+ g_use_empty => g_input_fifo_use_empty,
+ g_use_channel => g_input_fifo_use_channel,
+ g_use_error => g_input_fifo_use_error,
+ g_use_sync => g_input_fifo_use_sync,
+ g_use_ctrl => true,
+ g_fifo_size => 10 -- Use 10 as there's a FIFO margin
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_siso_arr(i),
+ snk_in => dp_sel_sosi_arr(i),
+
+ src_in => dp_to_split_siso_arr(i),
+ src_out => dp_to_split_sosi_arr(i)
+ );
end generate;
end generate;
@@ -191,28 +191,28 @@ begin
-- Throw away words 0..g_block_nof_sel_words-1 of block (0..g_block_size-1)
---------------------------------------------------------------------------------------
u_mms_dp_split : entity work.mms_dp_split
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_nof_symbols_max => g_block_nof_sel_words * (g_data_w / c_byte_w)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- snk_out_arr => dp_to_split_siso_arr,
- snk_in_arr => dp_to_split_sosi_arr,
-
- src_in_2arr => dp_from_split_siso_2arr,
- src_out_2arr => dp_from_split_sosi_2arr,
-
- reg_mosi => reg_dp_split_mosi,
- reg_miso => reg_dp_split_miso
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_nof_symbols_max => g_block_nof_sel_words * (g_data_w / c_byte_w)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ snk_out_arr => dp_to_split_siso_arr,
+ snk_in_arr => dp_to_split_sosi_arr,
+
+ src_in_2arr => dp_from_split_siso_2arr,
+ src_out_2arr => dp_from_split_sosi_2arr,
+
+ reg_mosi => reg_dp_split_mosi,
+ reg_miso => reg_dp_split_miso
+ );
gen_nof_streams1: for i in 0 to g_nof_streams - 1 generate
dp_from_split_siso_2arr(i)(0) <= c_dp_siso_rdy;
@@ -225,30 +225,30 @@ begin
---------------------------------------------------------------------------------------
gen_input_fifo : if g_use_input_fifo = true generate
u_input_fifo : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => g_input_fifo_bsn_w,
- g_empty_w => g_input_fifo_empty_w,
- g_channel_w => g_input_fifo_channel_w,
- g_error_w => g_input_fifo_error_w,
- g_use_bsn => g_input_fifo_use_bsn,
- g_use_empty => g_input_fifo_use_empty,
- g_use_channel => g_input_fifo_use_channel,
- g_use_error => g_input_fifo_use_error,
- g_use_sync => g_input_fifo_use_sync,
- g_use_ctrl => true,
- g_fifo_size => c_input_fifo_size
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_from_split_siso_2arr(i)(1),
- snk_in => dp_from_split_sosi_2arr(i)(1),
-
- src_in => dp_to_pkt_merge_siso_arr(i),
- src_out => dp_to_pkt_merge_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => g_input_fifo_bsn_w,
+ g_empty_w => g_input_fifo_empty_w,
+ g_channel_w => g_input_fifo_channel_w,
+ g_error_w => g_input_fifo_error_w,
+ g_use_bsn => g_input_fifo_use_bsn,
+ g_use_empty => g_input_fifo_use_empty,
+ g_use_channel => g_input_fifo_use_channel,
+ g_use_error => g_input_fifo_use_error,
+ g_use_sync => g_input_fifo_use_sync,
+ g_use_ctrl => true,
+ g_fifo_size => c_input_fifo_size
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_from_split_siso_2arr(i)(1),
+ snk_in => dp_from_split_sosi_2arr(i)(1),
+
+ src_in => dp_to_pkt_merge_siso_arr(i),
+ src_out => dp_to_pkt_merge_sosi_arr(i)
+ );
end generate;
no_input_fifo : if g_use_input_fifo = false generate
@@ -264,102 +264,102 @@ begin
-- G_nof_pkt packets are merged into 1.
---------------------------------------------------------------------------------------
u_dp_packet_merge : entity work.mms_dp_packet_merge
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_pkt => g_nof_words_per_pkt -- Support merging 360*1 word
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_pkt => g_nof_words_per_pkt -- Support merging 360*1 word
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
- snk_out_arr => dp_to_pkt_merge_siso_arr,
- snk_in_arr => dp_to_pkt_merge_sosi_arr,
+ snk_out_arr => dp_to_pkt_merge_siso_arr,
+ snk_in_arr => dp_to_pkt_merge_sosi_arr,
- src_in_arr => dp_merged_siso_arr,
- src_out_arr => dp_merged_sosi_arr,
+ src_in_arr => dp_merged_siso_arr,
+ src_out_arr => dp_merged_sosi_arr,
- reg_mosi => reg_dp_pkt_merge_mosi,
- reg_miso => reg_dp_pkt_merge_miso
- );
+ reg_mosi => reg_dp_pkt_merge_mosi,
+ reg_miso => reg_dp_pkt_merge_miso
+ );
gen_nof_streams3: for i in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
-- Convert DP to packetized DP
---------------------------------------------------------------------------------------
u_dp_packet_enc : entity work.dp_packet_enc
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
- snk_out => dp_merged_siso_arr(i),
- snk_in => dp_merged_sosi_arr(i),
+ snk_out => dp_merged_siso_arr(i),
+ snk_in => dp_merged_sosi_arr(i),
- src_in => udp_tx_pkt_siso_arr(i),
- src_out => udp_tx_pkt_sosi_arr(i)
- );
+ src_in => udp_tx_pkt_siso_arr(i),
+ src_out => udp_tx_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- Add header to DP packet
---------------------------------------------------------------------------------------
u_hdr_insert : entity work.dp_hdr_insert
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_nof_words => g_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_nof_words => g_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- reg_mosi => reg_hdr_insert_mosi_arr(i),
- ram_mosi => ram_hdr_insert_mosi_arr(i),
+ reg_mosi => reg_hdr_insert_mosi_arr(i),
+ ram_mosi => ram_hdr_insert_mosi_arr(i),
- snk_out => udp_tx_pkt_siso_arr(i),
- snk_in => udp_tx_pkt_sosi_arr(i),
+ snk_out => udp_tx_pkt_siso_arr(i),
+ snk_in => udp_tx_pkt_sosi_arr(i),
- src_in => udp_tx_hdr_pkt_siso_arr(i),
- src_out => udp_tx_hdr_pkt_sosi_arr(i)
- );
+ src_in => udp_tx_hdr_pkt_siso_arr(i),
+ src_out => udp_tx_hdr_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- FIFO so we can deliver packets to the ETH module fast enough
---------------------------------------------------------------------------------------
gen_output_fifo: if g_use_output_fifo = true generate
u_dp_fifo_fill : entity work.dp_fifo_fill
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => 0,
- g_empty_w => 0,
- g_channel_w => 0,
- g_error_w => 0,
- g_use_bsn => false, -- Don't forward these as all have been encoded by dp_packet_enc
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => false,
- g_fifo_fill => c_output_fifo_fill, -- Release packet only when available
- g_fifo_size => c_output_fifo_size,
- g_fifo_rl => 1
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => udp_tx_hdr_pkt_siso_arr(i),
- snk_in => udp_tx_hdr_pkt_sosi_arr(i),
-
- src_in => udp_tx_hdr_pkt_fifo_siso_arr(i),
- src_out => udp_tx_hdr_pkt_fifo_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 0,
+ g_empty_w => 0,
+ g_channel_w => 0,
+ g_error_w => 0,
+ g_use_bsn => false, -- Don't forward these as all have been encoded by dp_packet_enc
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => false,
+ g_fifo_fill => c_output_fifo_fill, -- Release packet only when available
+ g_fifo_size => c_output_fifo_size,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => udp_tx_hdr_pkt_siso_arr(i),
+ snk_in => udp_tx_hdr_pkt_sosi_arr(i),
+
+ src_in => udp_tx_hdr_pkt_fifo_siso_arr(i),
+ src_out => udp_tx_hdr_pkt_fifo_sosi_arr(i)
+ );
udp_tx_hdr_pkt_fifo_siso_arr(i) <= tx_siso_arr(i);
tx_sosi_arr(i) <= udp_tx_hdr_pkt_fifo_sosi_arr(i);
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
index fb1bdffd29..4d9bbad503 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
-- Purpose:
-- . Calculate UDP total length and IP total length fields
@@ -86,25 +86,25 @@ begin
-- Calculate number of payload words
---------------------------------------------------------------------------------------
u_common_mult: entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => nof_words_per_block'LENGTH,
- g_in_b_w => nof_blocks_per_packet'LENGTH,
- g_out_p_w => c_product_w,
- g_pipeline_input => 0,
- g_pipeline_product => 0,
- g_pipeline_output => 0,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_a => nof_words_per_block,
- in_b => nof_blocks_per_packet,
- out_p => nof_data_words
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => nof_words_per_block'LENGTH,
+ g_in_b_w => nof_blocks_per_packet'LENGTH,
+ g_out_p_w => c_product_w,
+ g_pipeline_input => 0,
+ g_pipeline_product => 0,
+ g_pipeline_output => 0,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_a => nof_words_per_block,
+ in_b => nof_blocks_per_packet,
+ out_p => nof_data_words
+ );
---------------------------------------------------------------------------------------
-- Calculate number of payload bytes by bit shifting to the left
@@ -117,18 +117,18 @@ begin
udp_adder_in <= RESIZE_UVEC(nof_data_bytes, c_adder_in_w) & TO_UVEC(c_udp_header_len, c_adder_in_w) & TO_UVEC(c_user_hdr_len, c_adder_in_w);
u_common_adder_tree_udp : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => 0,
- g_nof_inputs => 3,
- g_dat_w => c_adder_in_w,
- g_sum_w => c_adder_in_w + 2
- )
- port map (
- clk => clk,
- in_dat => udp_adder_in,
- sum => udp_adder_out
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => 0,
+ g_nof_inputs => 3,
+ g_dat_w => c_adder_in_w,
+ g_sum_w => c_adder_in_w + 2
+ )
+ port map (
+ clk => clk,
+ in_dat => udp_adder_in,
+ sum => udp_adder_out
+ );
udp_total_length <= udp_adder_out(c_adder_in_w - 1 downto 0);
@@ -138,18 +138,18 @@ begin
ip_adder_in <= RESIZE_UVEC(udp_adder_out, c_adder_in_w) & TO_UVEC(c_ip_header_len, c_adder_in_w);
u_common_adder_tree_ip : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => 0,
- g_nof_inputs => 2,
- g_dat_w => c_adder_in_w,
- g_sum_w => c_adder_in_w + 1
- )
- port map (
- clk => clk,
- in_dat => ip_adder_in,
- sum => ip_adder_out
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => 0,
+ g_nof_inputs => 2,
+ g_dat_w => c_adder_in_w,
+ g_sum_w => c_adder_in_w + 1
+ )
+ port map (
+ clk => clk,
+ in_dat => ip_adder_in,
+ sum => ip_adder_out
+ );
ip_total_length <= ip_adder_out(c_adder_in_w - 1 downto 0);
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
index f8a4288fe5..599f42d561 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
@@ -41,13 +41,13 @@
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_offload_tx_v3 is
generic (
@@ -158,51 +158,51 @@ begin
-- mm_fields for MM access to each field
---------------------------------------------------------------------------------------
u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_hdr_dat_mosi_arr(i),
- mm_miso => OPEN, -- Not used
+ mm_mosi => reg_hdr_dat_mosi_arr(i),
+ mm_miso => OPEN, -- Not used
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_slv_out_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0)
- );
+ slv_out => mm_fields_slv_out_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0)
+ );
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w,
- g_in_symbol_w => g_symbol_w,
- g_out_symbol_w => g_symbol_w,
- g_pipeline_ready => g_pipeline_ready,
- g_mode => 1 -- source mode
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_out => dp_field_blk_src_out_arr(i),
- src_in => dp_field_blk_src_in_arr(i),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w,
+ g_in_symbol_w => g_symbol_w,
+ g_out_symbol_w => g_symbol_w,
+ g_pipeline_ready => g_pipeline_ready,
+ g_mode => 1 -- source mode
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_out => dp_field_blk_src_out_arr(i),
+ src_in => dp_field_blk_src_in_arr(i),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
@@ -215,35 +215,35 @@ begin
dp_concat_snk_in_2arr(i)(1) <= dp_field_blk_src_out_arr(i);
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
index 026c8f5557..f32b4f5279 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packet_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packet_pkg.all;
-- Purpose: Decode DP packet to DP sosi.
-- Description:
@@ -181,18 +181,18 @@ begin
nxt_src_buf <= next_src_buf;
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => OPEN,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => OPEN,
+ src_out_reg => src_buf
+ );
-- State machine
p_state : process(state, src_in, channel, bsn, cnt, blk_sosi, next_src_buf)
@@ -288,25 +288,25 @@ begin
-- Handle output error field and eop
u_src_shift : entity work.dp_shiftreg
- generic map (
- g_output_reg => c_output_reg,
- g_flush_eop => true,
- g_modify_support => true,
- g_nof_words => c_shiftreg_len
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => blk_sosi,
- -- Control shift register contents
- cur_shiftreg_inputs => cur_src_out_inputs,
- new_shiftreg_inputs => new_src_out_inputs,
- -- ST source
- src_in => src_in,
- src_out => i_src_out
- );
+ generic map (
+ g_output_reg => c_output_reg,
+ g_flush_eop => true,
+ g_modify_support => true,
+ g_nof_words => c_shiftreg_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => blk_sosi,
+ -- Control shift register contents
+ cur_shiftreg_inputs => cur_src_out_inputs,
+ new_shiftreg_inputs => new_src_out_inputs,
+ -- ST source
+ src_in => src_in,
+ src_out => i_src_out
+ );
p_src_err : process(cur_src_out_inputs)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
index c85ee49113..1cf9f85bdd 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose: Decode sosi.channel low bits from the high part of the CHAN field
-- of a DP packet.
diff --git a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
index 8f9aead044..ecf53b1d34 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Assert output during a packet on the input:
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
index 75ec661c0b..19f52911c7 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packet_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packet_pkg.all;
-- Purpose: Encode DP sosi to DP packet.
-- Description:
@@ -155,18 +155,18 @@ begin
nxt_src_buf <= next_src_buf;
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => pend_src_buf,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => pend_src_buf,
+ src_out_reg => src_buf
+ );
-- State machine
p_state : process(state, cnt, src_in, pend_src_buf, i_src_out, in_err)
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
index 9d3955d30e..e0a1dc6387 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose: Encode sosi.channel low bit into the high part of the CHAN field of
-- a DP packet.
diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index 551460047f..9249c24ba0 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -178,10 +178,10 @@
-- through dp_pipeline to register it and to add the flow control.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_packet_merge is
generic (
@@ -237,7 +237,7 @@ begin
snk_out <= src_in;
src_out <= r.src_out;
- -- can put dp_hold_input here --
+ -- can put dp_hold_input here --
end generate;
gen_dp_latency_adapter : if c_use_dp_latency_adapter = true generate
@@ -245,20 +245,20 @@ begin
dp_latency_adapter_snk_in <= r.src_out;
u_dp_latency_adapter : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 2,
- g_out_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => dp_latency_adapter_snk_out,
- snk_in => dp_latency_adapter_snk_in,
- -- ST source
- src_in => dp_latency_adapter_src_in,
- src_out => dp_latency_adapter_src_out
- );
+ generic map (
+ g_in_latency => 2,
+ g_out_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => dp_latency_adapter_snk_out,
+ snk_in => dp_latency_adapter_snk_in,
+ -- ST source
+ src_in => dp_latency_adapter_src_in,
+ src_out => dp_latency_adapter_src_out
+ );
dp_latency_adapter_src_in <= src_in;
src_out <= dp_latency_adapter_src_out;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
index b9e33be549..5953bd9b66 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
@@ -20,8 +20,8 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package dp_packet_pkg is
@@ -54,14 +54,14 @@ package dp_packet_pkg is
constant c_dp_packet_bsn_hi : natural := c_dp_packet_bsn_w - 2; -- = use rest [62:0] of BSN field to transport the SOSI BSN
-- Determine the length in nof data words to fit the DP packet overhead fields
- function func_dp_packet_overhead_len(c_data_w : natural) return natural;
+ function func_dp_packet_overhead_len (c_data_w : natural) return natural;
end dp_packet_pkg;
package body dp_packet_pkg is
- function func_dp_packet_overhead_len(c_data_w : natural) return natural is
+ function func_dp_packet_overhead_len (c_data_w : natural) return natural is
begin
-- Calculate the total DP PACKET overhead length of header (channel and bsn words) + lenght of tail (error words).
return ceil_div(c_dp_packet_channel_w, c_data_w) +
diff --git a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
index 251466d022..a2403fb12f 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
@@ -33,10 +33,10 @@
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_packet_unmerge is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
index ca365bcda5..c39a519339 100644
--- a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
@@ -20,45 +20,45 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, easics_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-
-use easics_lib.RAD_CRC16_D16.all;
-use easics_lib.RAD_CRC18_D18.all;
-use easics_lib.RAD_CRC20_D20.all;
-
-use easics_lib.PCK_CRC16_D4.all;
-use easics_lib.PCK_CRC16_D8.all;
-use easics_lib.PCK_CRC16_D9.all;
-use easics_lib.PCK_CRC16_D10.all;
-use easics_lib.PCK_CRC16_D16.all;
-use easics_lib.PCK_CRC16_D18.all;
-use easics_lib.PCK_CRC16_D20.all;
-use easics_lib.PCK_CRC16_D32.all;
-use easics_lib.PCK_CRC16_D36.all;
-use easics_lib.PCK_CRC16_D48.all;
-use easics_lib.PCK_CRC16_D64.all;
-use easics_lib.PCK_CRC16_D72.all;
-
-use easics_lib.PCK_CRC32_D4.all;
-use easics_lib.PCK_CRC32_D8.all;
-use easics_lib.PCK_CRC32_D9.all;
-use easics_lib.PCK_CRC32_D10.all;
-use easics_lib.PCK_CRC32_D16.all;
-use easics_lib.PCK_CRC32_D18.all;
-use easics_lib.PCK_CRC32_D20.all;
-use easics_lib.PCK_CRC32_D32.all;
-use easics_lib.PCK_CRC32_D36.all;
-use easics_lib.PCK_CRC32_D48.all;
-use easics_lib.PCK_CRC32_D64.all;
-use easics_lib.PCK_CRC32_D72.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+
+ use easics_lib.RAD_CRC16_D16.all;
+ use easics_lib.RAD_CRC18_D18.all;
+ use easics_lib.RAD_CRC20_D20.all;
+
+ use easics_lib.PCK_CRC16_D4.all;
+ use easics_lib.PCK_CRC16_D8.all;
+ use easics_lib.PCK_CRC16_D9.all;
+ use easics_lib.PCK_CRC16_D10.all;
+ use easics_lib.PCK_CRC16_D16.all;
+ use easics_lib.PCK_CRC16_D18.all;
+ use easics_lib.PCK_CRC16_D20.all;
+ use easics_lib.PCK_CRC16_D32.all;
+ use easics_lib.PCK_CRC16_D36.all;
+ use easics_lib.PCK_CRC16_D48.all;
+ use easics_lib.PCK_CRC16_D64.all;
+ use easics_lib.PCK_CRC16_D72.all;
+
+ use easics_lib.PCK_CRC32_D4.all;
+ use easics_lib.PCK_CRC32_D8.all;
+ use easics_lib.PCK_CRC32_D9.all;
+ use easics_lib.PCK_CRC32_D10.all;
+ use easics_lib.PCK_CRC32_D16.all;
+ use easics_lib.PCK_CRC32_D18.all;
+ use easics_lib.PCK_CRC32_D20.all;
+ use easics_lib.PCK_CRC32_D32.all;
+ use easics_lib.PCK_CRC32_D36.all;
+ use easics_lib.PCK_CRC32_D48.all;
+ use easics_lib.PCK_CRC32_D64.all;
+ use easics_lib.PCK_CRC32_D72.all;
package dp_packetizing_pkg is
--<types>--
--<functions>--
- function func_dp_next_crc(c_lofar : boolean; dat, crc : std_logic_vector) return std_logic_vector;
+ function func_dp_next_crc (c_lofar : boolean; dat, crc : std_logic_vector) return std_logic_vector;
--<constants>--
constant c_dp_max_w : natural := 64;
@@ -90,7 +90,7 @@ package body dp_packetizing_pkg is
-- FUNCTION: Calculate next CRC for this data
------------------------------------------------------------------------------
- function func_dp_next_crc(c_lofar : boolean; dat, crc : std_logic_vector) return std_logic_vector is
+ function func_dp_next_crc (c_lofar : boolean; dat, crc : std_logic_vector) return std_logic_vector is
variable nxt_crc : std_logic_vector(crc'range);
begin
if c_lofar = true then
diff --git a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
index a0c31ed3d7..12c447c2c2 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Prepend one word with empty symbols at the head of a frame
@@ -111,18 +111,18 @@ begin
end process;
u_hold_snk_in : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => in_siso,
- next_src_out => next_in_sosi,
- pend_src_out => pend_in_sosi,
- src_out_reg => in_sosi
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => in_siso,
+ next_src_out => next_in_sosi,
+ pend_src_out => pend_in_sosi,
+ src_out_reg => in_sosi
+ );
-- Prepend the padding octets to snk_in
pad_siso <= concat_siso_arr(0);
@@ -131,20 +131,20 @@ begin
concat_sosi_arr(1) <= in_sosi; -- = tail frame with in_sosi eop info
u_concat : entity work.dp_concat -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => concat_siso_arr,
- snk_in_arr => concat_sosi_arr,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => concat_siso_arr,
+ snk_in_arr => concat_sosi_arr,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
index 09c049737d..77b3ce7722 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Remove padding octects from the head of a padded frame
@@ -70,21 +70,21 @@ begin
src_out <= split_sosi_arr(1);
u_split : entity work.dp_split -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => g_nof_padding
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in_arr => split_siso_arr,
- src_out_arr => split_sosi_arr
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => g_nof_padding
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in_arr => split_siso_arr,
+ src_out_arr => split_sosi_arr
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
diff --git a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
index 2a2eba1ee0..890bf805b2 100644
--- a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
@@ -40,10 +40,10 @@
-- - dp_block_gen_valid_arr
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_paged_sop_eop_reg is
generic (
@@ -75,69 +75,69 @@ begin
src_out.sync <= src_out_sync(0); -- convert slv to sl
u_paged_sync : entity common_lib.common_paged_reg
- generic map (
- g_data_w => 1,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in_sync,
- out_dat => src_out_sync
- );
+ generic map (
+ g_data_w => 1,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in_sync,
+ out_dat => src_out_sync
+ );
u_paged_bsn : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_bsn_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in.bsn,
- out_dat => src_out.bsn
- );
+ generic map (
+ g_data_w => c_dp_stream_bsn_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in.bsn,
+ out_dat => src_out.bsn
+ );
u_paged_channel : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_channel_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in.channel,
- out_dat => src_out.channel
- );
+ generic map (
+ g_data_w => c_dp_stream_channel_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in.channel,
+ out_dat => src_out.channel
+ );
-- Sosi info at eop
u_paged_empty : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_empty_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => eop_wr_en,
- wr_dat => snk_in.empty,
- out_dat => src_out.empty
- );
+ generic map (
+ g_data_w => c_dp_stream_empty_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => eop_wr_en,
+ wr_dat => snk_in.empty,
+ out_dat => src_out.empty
+ );
u_paged_err : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_error_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => eop_wr_en,
- wr_dat => snk_in.err,
- out_dat => src_out.err
- );
+ generic map (
+ g_data_w => c_dp_stream_error_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => eop_wr_en,
+ wr_dat => snk_in.err,
+ out_dat => src_out.err
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline.vhd b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
index 5a0fcfdae6..68e1ad1b15 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Pipeline the source output by one cycle or by g_pipeline cycles.
@@ -62,8 +62,8 @@ end dp_pipeline;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_pipeline_one is
port (
@@ -80,8 +80,8 @@ end dp_pipeline_one;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_pipeline is
@@ -100,24 +100,24 @@ begin
gen_p : for I in 1 to g_pipeline generate
u_p : entity work.dp_pipeline_one
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I - 1),
- snk_in => snk_in_arr(I - 1),
- -- ST source
- src_in => snk_out_arr(I),
- src_out => snk_in_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I - 1),
+ snk_in => snk_in_arr(I - 1),
+ -- ST source
+ src_in => snk_out_arr(I),
+ src_out => snk_in_arr(I)
+ );
end generate;
end str;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_pipeline_one is
@@ -140,17 +140,17 @@ begin
-- Input control
u_hold_input : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- next_src_out => nxt_src_out,
- pend_src_out => OPEN,
- src_out_reg => i_src_out
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ next_src_out => nxt_src_out,
+ pend_src_out => OPEN,
+ src_out_reg => i_src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
index 91d70de3fe..07407b945d 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Pipeline array of g_nof_streams by g_pipeline cycles.
@@ -53,19 +53,19 @@ begin
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_p : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
index d911589876..dba86186e1 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Pipeline the source input
@@ -66,92 +66,92 @@ begin
gen_out_incr_rl : if g_out_latency > g_in_latency generate
-- Register siso by incrementing the input RL first
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => g_out_latency - g_in_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => g_out_latency - g_in_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_out_rl_0 : if g_out_latency <= g_in_latency and g_out_latency = 0 generate
-- Register siso by incrementing the input RL first
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => internal_siso,
- src_out => internal_sosi
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => internal_siso,
+ src_out => internal_sosi
+ );
-- Input RL --> 0
u_adapt : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_in_latency + 1,
- g_out_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => internal_siso,
- snk_in => internal_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency + 1,
+ g_out_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => internal_siso,
+ snk_in => internal_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_out_rl : if g_out_latency <= g_in_latency and g_out_latency > 0 generate
-- First adapt the input RL --> 0
u_adapt : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_in_latency,
- g_out_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => internal_siso,
- src_out => internal_sosi
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_out_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => internal_siso,
+ src_out => internal_sosi
+ );
-- Register siso by incrementing the internal RL = 0 --> the output RL
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => internal_siso,
- snk_in => internal_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => internal_siso,
+ snk_in => internal_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
index 739b1db04a..70f67e8afc 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_ram_from_mm is
generic (
@@ -54,19 +54,23 @@ end dp_ram_from_mm;
architecture rtl of dp_ram_from_mm is
- constant c_mm_ram_wr : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_ram_wr_nof_words),
- dat_w => c_word_w,
- nof_dat => g_ram_wr_nof_words,
- init_sl => '0');
+ constant c_mm_ram_wr : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_ram_wr_nof_words),
+ dat_w => c_word_w,
+ nof_dat => g_ram_wr_nof_words,
+ init_sl => '0'
+ );
constant c_ram_rd_nof_words : natural := (c_word_w * g_ram_wr_nof_words) / g_ram_rd_dat_w;
- constant c_mm_ram_rd : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_rd_nof_words),
- dat_w => g_ram_rd_dat_w,
- nof_dat => c_ram_rd_nof_words,
- init_sl => '0');
+ constant c_mm_ram_rd : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_rd_nof_words),
+ dat_w => g_ram_rd_dat_w,
+ nof_dat => c_ram_rd_nof_words,
+ init_sl => '0'
+ );
type t_state_enum is (s_init, s_wait_for_rdy, s_read);
@@ -155,27 +159,27 @@ begin
end process;
u_ram : entity common_lib.common_ram_cr_cw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_wr => c_mm_ram_wr,
- g_ram_rd => c_mm_ram_rd,
- g_init_file => g_init_file
- )
- port map (
- -- Write port clock domain
- wr_rst => mm_rst,
- wr_clk => mm_clk,
- wr_en => mm_wr,
- wr_adr => mm_addr(c_mm_ram_wr.adr_w - 1 downto 0),
- wr_dat => mm_wrdata(c_mm_ram_wr.dat_w - 1 downto 0),
- -- Read port clock domain
- rd_rst => st_rst,
- rd_clk => st_clk,
- rd_en => rd_en,
- rd_adr => rd_addr,
- rd_dat => rd_data,
- rd_val => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_wr => c_mm_ram_wr,
+ g_ram_rd => c_mm_ram_rd,
+ g_init_file => g_init_file
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ wr_en => mm_wr,
+ wr_adr => mm_addr(c_mm_ram_wr.adr_w - 1 downto 0),
+ wr_dat => mm_wrdata(c_mm_ram_wr.dat_w - 1 downto 0),
+ -- Read port clock domain
+ rd_rst => st_rst,
+ rd_clk => st_clk,
+ rd_en => rd_en,
+ rd_adr => rd_addr,
+ rd_dat => rd_data,
+ rd_val => open
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
index c783a7a8e1..ae65e4719f 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_ram_from_mm_reg is
generic (
@@ -38,17 +38,19 @@ entity dp_ram_from_mm_reg is
sla_in : in t_mem_mosi;
dp_on : out std_logic
- );
+ );
end dp_ram_from_mm_reg;
architecture rtl of dp_ram_from_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0'
+ );
signal mm_dp_on : std_logic;
@@ -72,15 +74,15 @@ begin
end process;
u_async_dp_on : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- din => mm_dp_on,
- dout => dp_on
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ din => mm_dp_on,
+ dout => dp_on
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
index c2203adebf..4d7dc3d846 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_ram_to_mm is
generic (
@@ -50,19 +50,23 @@ end dp_ram_to_mm;
architecture rtl of dp_ram_to_mm is
- constant c_mm_ram_rd : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_ram_rd_nof_words),
- dat_w => c_word_w,
- nof_dat => g_ram_rd_nof_words,
- init_sl => '0');
+ constant c_mm_ram_rd : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_ram_rd_nof_words),
+ dat_w => c_word_w,
+ nof_dat => g_ram_rd_nof_words,
+ init_sl => '0'
+ );
constant c_ram_wr_nof_words : natural := (c_word_w * g_ram_rd_nof_words) / g_ram_wr_dat_w;
- constant c_mm_ram_wr : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_wr_nof_words),
- dat_w => g_ram_wr_dat_w,
- nof_dat => c_ram_wr_nof_words,
- init_sl => '0');
+ constant c_mm_ram_wr : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_wr_nof_words),
+ dat_w => g_ram_wr_dat_w,
+ nof_dat => c_ram_wr_nof_words,
+ init_sl => '0'
+ );
type t_state_enum is (s_init, s_wait_for_sop, s_write);
@@ -133,27 +137,27 @@ begin
end process;
u_ram : entity common_lib.common_ram_cr_cw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_wr => c_mm_ram_wr,
- g_ram_rd => c_mm_ram_rd,
- g_init_file => "UNUSED"
- )
- port map (
- -- Write port clock domain
- wr_rst => st_rst,
- wr_clk => st_clk,
- wr_en => snk_in.valid,
- wr_adr => wr_addr,
- wr_dat => snk_in.data(c_mm_ram_wr.dat_w - 1 downto 0),
- -- Read port clock domain
- rd_rst => mm_rst,
- rd_clk => mm_clk,
- rd_en => sla_in.rd,
- rd_adr => sla_in.address(c_mm_ram_rd.adr_w - 1 downto 0),
- rd_dat => sla_out.rddata(c_mm_ram_rd.dat_w - 1 downto 0),
- rd_val => sla_out.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_wr => c_mm_ram_wr,
+ g_ram_rd => c_mm_ram_rd,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => st_rst,
+ wr_clk => st_clk,
+ wr_en => snk_in.valid,
+ wr_adr => wr_addr,
+ wr_dat => snk_in.data(c_mm_ram_wr.dat_w - 1 downto 0),
+ -- Read port clock domain
+ rd_rst => mm_rst,
+ rd_clk => mm_clk,
+ rd_en => sla_in.rd,
+ rd_adr => sla_in.address(c_mm_ram_rd.adr_w - 1 downto 0),
+ rd_dat => sla_out.rddata(c_mm_ram_rd.dat_w - 1 downto 0),
+ rd_val => sla_out.rdval
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ready.vhd b/libraries/base/dp/src/vhdl/dp_ready.vhd
index 9e3bdb3aa8..1b13293b74 100644
--- a/libraries/base/dp/src/vhdl/dp_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ready.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- =======
diff --git a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
index 60a4f0f862..7cc5a9d4fa 100644
--- a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -111,24 +111,24 @@ begin
common_reinterleave_in_val <= snk_in_arr(0).valid;
u_common_reinterleave : entity common_lib.common_reinterleave
- generic map (
- g_nof_in => g_nof_in,
- g_deint_block_size => g_deint_block_size,
- g_nof_out => g_nof_out,
- g_inter_block_size => g_inter_block_size,
- g_dat_w => g_dat_w,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => common_reinterleave_in_dat,
- in_val => common_reinterleave_in_val,
-
- out_dat => common_reinterleave_out_dat,
- out_val => common_reinterleave_out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_deint_block_size => g_deint_block_size,
+ g_nof_out => g_nof_out,
+ g_inter_block_size => g_inter_block_size,
+ g_dat_w => g_dat_w,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => common_reinterleave_in_dat,
+ in_val => common_reinterleave_in_val,
+
+ out_dat => common_reinterleave_out_dat,
+ out_val => common_reinterleave_out_val
+ );
-----------------------------------------------------------------------------
-- Map output SLV to sosi_arr
@@ -158,19 +158,19 @@ begin
gen_ctrl : if g_use_ctrl = true generate
gen_dp_block_gen : for i in 0 to g_nof_out - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_block_size_output,
- g_preserve_sync => true,
- g_preserve_bsn => true
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => common_reinterleave_src_out_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_block_size_output,
+ g_preserve_sync => true,
+ g_preserve_bsn => true
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => common_reinterleave_src_out_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -184,20 +184,20 @@ begin
align_out : if g_use_sync_bsn = true generate
gen_dp_fifo_info: for i in 0 to g_nof_out - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_repack.vhd b/libraries/base/dp/src/vhdl/dp_repack.vhd
index 80ff6b55ca..d5e7c98671 100644
--- a/libraries/base/dp/src/vhdl/dp_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Reuse from LOFAR rad_repack.vhd and rad_repack(rtl).vhd
@@ -100,7 +100,7 @@ begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -153,11 +153,11 @@ begin
out_eof <= out_eof_vec(0);
buf_load <= '1' when signed(in_val_vec) = -1 else '0';
- -- in_val_vec=-1: input set complete, ready to be repacked
+ -- in_val_vec=-1: input set complete, ready to be repacked
buf_flush <= '1' when (unsigned(out_val_vec) = 1 or unsigned(out_val_vec) = 0) and buf_val = '1' else '0';
- -- out_val_vec=0: ready to repack first input set
- -- out_val_vec=1: ready to repack next input set
- -- buf_val: new input set available
+ -- out_val_vec=0: ready to repack first input set
+ -- out_val_vec=1: ready to repack next input set
+ -- buf_val: new input set available
p_in: process(in_sof, buf_load, in_val, in_val_vec, in_dat, in_dat_vec)
begin
@@ -222,11 +222,11 @@ begin
if g_ls_to_ms = true then
-- Push SLV to the right so new word appears at LS position
nxt_out_dat_vec <= std_logic_vector(to_unsigned(0,out_dat'length)) &
- out_dat_vec(out_dat_vec'high downto out_dat'length);
+ out_dat_vec(out_dat_vec'high downto out_dat'length);
else
-- Push SLV to the left so new word appears at MS position
nxt_out_dat_vec <= out_dat_vec(out_dat_vec'high - out_dat'length downto 0) &
- std_logic_vector(to_unsigned(0,out_dat'length));
+ std_logic_vector(to_unsigned(0,out_dat'length));
end if;
nxt_out_val_vec <= '0' & out_val_vec(out_val_vec'high downto 1);
diff --git a/libraries/base/dp/src/vhdl/dp_repack_data.vhd b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
index 24eb8308cf..5115238448 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
@@ -175,9 +175,9 @@
-- useful to be able to isolate a component for debugging.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_in is
generic (
@@ -394,9 +394,9 @@ end rtl;
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_out is
generic (
@@ -641,9 +641,9 @@ end rtl;
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_data is
generic (
@@ -694,16 +694,16 @@ begin
gen_dp_pipeline_ready: if g_pipeline_ready = true generate
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map (
- rst => rst,
- clk => clk,
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => snk_out,
- snk_in => snk_in,
+ snk_out => snk_out,
+ snk_in => snk_in,
- src_in => i_snk_out,
- src_out => i_snk_in
- );
+ src_in => i_snk_out,
+ src_out => i_snk_in
+ );
end generate;
gen_no_dp_pipeline_ready: if g_pipeline_ready = false generate
@@ -724,23 +724,23 @@ begin
gen_dp_repack_in : if g_enable_repack_in = true generate
u_dp_repack_in : entity work.dp_repack_in
- generic map (
- g_bypass => g_in_bypass,
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_in_symbol_w => g_in_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => i_snk_out,
- snk_in => i_snk_in,
-
- src_in => pack_siso,
- src_out => pack_sosi,
- src_out_data => pack_sosi_data
- );
+ generic map (
+ g_bypass => g_in_bypass,
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_in_symbol_w => g_in_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => i_snk_out,
+ snk_in => i_snk_in,
+
+ src_in => pack_siso,
+ src_out => pack_sosi,
+ src_out_data => pack_sosi_data
+ );
end generate;
no_dp_repack_out : if g_enable_repack_out = false generate
@@ -750,24 +750,24 @@ begin
gen_dp_repack_out : if g_enable_repack_out = true generate
u_dp_repack_out : entity work.dp_repack_out
- generic map (
- g_bypass => g_out_bypass,
- g_in_buf_dat_w => c_in_buf_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_out_nof_words => g_out_nof_words,
- g_out_symbol_w => g_out_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => pack_siso,
- snk_in => pack_sosi,
- snk_in_data => pack_sosi_data,
-
- src_in => src_in,
- src_out => i_src_out
- );
+ generic map (
+ g_bypass => g_out_bypass,
+ g_in_buf_dat_w => c_in_buf_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_out_nof_words => g_out_nof_words,
+ g_out_symbol_w => g_out_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => pack_siso,
+ snk_in => pack_sosi,
+ snk_in_data => pack_sosi_data,
+
+ src_in => src_in,
+ src_out => i_src_out
+ );
end generate;
-- Simulation only: internal stream RL verification
diff --git a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
index bbf5cac26c..224080a7d2 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Reuse from LOFAR rad_repack.vhd and rad_repack(rtl).vhd
@@ -100,7 +100,7 @@ begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack_legacy at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -153,11 +153,11 @@ begin
out_eof <= out_eof_vec(0);
buf_load <= '1' when signed(in_val_vec) = -1 else '0';
- -- in_val_vec=-1: input set complete, ready to be repacked
+ -- in_val_vec=-1: input set complete, ready to be repacked
buf_flush <= '1' when (unsigned(out_val_vec) = 1 or unsigned(out_val_vec) = 0) and buf_val = '1' else '0';
- -- out_val_vec=0: ready to repack first input set
- -- out_val_vec=1: ready to repack next input set
- -- buf_val: new input set available
+ -- out_val_vec=0: ready to repack first input set
+ -- out_val_vec=1: ready to repack next input set
+ -- buf_val: new input set available
p_in: process(in_sof, buf_load, in_val, in_val_vec, in_dat, in_dat_vec)
begin
@@ -222,11 +222,11 @@ begin
if g_ls_to_ms = true then
-- Push SLV to the right so new word appears at LS position
nxt_out_dat_vec <= std_logic_vector(to_unsigned(0,out_dat'length)) &
- out_dat_vec(out_dat_vec'high downto out_dat'length);
+ out_dat_vec(out_dat_vec'high downto out_dat'length);
else
-- Push SLV to the left so new word appears at MS position
nxt_out_dat_vec <= out_dat_vec(out_dat_vec'high - out_dat'length downto 0) &
- std_logic_vector(to_unsigned(0,out_dat'length));
+ std_logic_vector(to_unsigned(0,out_dat'length));
end if;
nxt_out_val_vec <= '0' & out_val_vec(out_val_vec'high downto 1);
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index 1c5547523a..5ee66152aa 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
-use common_lib.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.all;
+ use common_lib.common_pkg.all;
-- Purpose: Requantize the data in the re, im or data field of the sosi record.
-- Description:
@@ -37,14 +37,14 @@ entity dp_requantize is
g_complex : boolean := true; -- when TRUE, the re and im field are processed, when false, the data field is processed
g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_lsb_w : integer := 4; -- when > 0, number of LSbits to remove from in_dat
- -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
- -- when 0 then no effect
+ -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
+ -- when 0 then no effect
g_lsb_round : boolean := true; -- when TRUE round else truncate the input LSbits
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_even : boolean := true; -- when TRUE round half to even, else round half away from zero
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_gain_w : natural := 0; -- do not use, must be 0, use negative g_lsb_w instead
g_pipeline_remove_lsb : natural := 0; -- >= 0
g_pipeline_remove_msb : natural := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
@@ -85,25 +85,25 @@ begin
---------------------------------------------------------------
gen_requantize_data : if g_complex = false generate
u_requantize_data : entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.data,
- out_dat => quantized_data,
- out_ovr => out_ovr
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.data,
+ out_dat => quantized_data,
+ out_ovr => out_ovr
+ );
end generate;
---------------------------------------------------------------
@@ -111,46 +111,46 @@ begin
---------------------------------------------------------------
gen_requantize_complex : if g_complex = true generate
u_requantize_re: entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.re,
- out_dat => quantized_re,
- out_ovr => out_ovr_re
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.re,
+ out_dat => quantized_re,
+ out_ovr => out_ovr_re
+ );
u_requantize_im: entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.im,
- out_dat => quantized_im,
- out_ovr => out_ovr_im
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.im,
+ out_dat => quantized_im,
+ out_ovr => out_ovr_im
+ );
out_ovr <= out_ovr_re or out_ovr_im;
end generate;
@@ -160,17 +160,17 @@ begin
-- Pipeline to align the other sosi fields
--------------------------------------------------------------
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_piped
- );
+ generic map (
+ g_pipeline => c_pipeline -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_piped
+ );
process(snk_in_piped, quantized_data, quantized_re, quantized_im)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
index 2c9a6f8056..c9e06992da 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
@@ -19,10 +19,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Eric Kooistra, 14 Feb 2023
@@ -91,39 +91,39 @@ begin
end process;
u_common_reverse_n : entity common_lib.common_reverse_n_data
- generic map (
- -- Pipeline: 0 for combinatorial, > 0 for registers
- g_pipeline_demux_in => g_pipeline_demux_in, -- serial to parallel demux
- g_pipeline_demux_out => g_pipeline_demux_out,
- g_pipeline_mux_in => g_pipeline_mux_in, -- parallel to serial mux
- g_pipeline_mux_out => g_pipeline_mux_out,
- g_reverse_len => g_reverse_len,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data,
- in_val => snk_in.valid,
- in_eop => snk_in.eop,
- out_data => reversed_data,
- out_val => reversed_val -- = snk_in_delayed.valid
- );
+ generic map (
+ -- Pipeline: 0 for combinatorial, > 0 for registers
+ g_pipeline_demux_in => g_pipeline_demux_in, -- serial to parallel demux
+ g_pipeline_demux_out => g_pipeline_demux_out,
+ g_pipeline_mux_in => g_pipeline_mux_in, -- parallel to serial mux
+ g_pipeline_mux_out => g_pipeline_mux_out,
+ g_reverse_len => g_reverse_len,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data,
+ in_val => snk_in.valid,
+ in_eop => snk_in.eop,
+ out_data => reversed_data,
+ out_val => reversed_val -- = snk_in_delayed.valid
+ );
-- Pipeline other sosi fields
u_pipe_input : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline_total
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_delayed
- );
+ generic map (
+ g_pipeline => c_pipeline_total
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_delayed
+ );
p_src_out : process(snk_in_delayed, reversed_data)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
index 50335742ea..ce21d18fdb 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
@@ -19,10 +19,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Eric Kooistra, 14 Feb 2023
@@ -71,19 +71,19 @@ architecture str of dp_reverse_n_data_fc is
begin
u_demux_one_to_n : entity work.dp_deinterleave_one_to_n
- generic map (
- g_pipeline => g_pipeline_in,
- g_nof_outputs => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => g_pipeline_in,
+ g_nof_outputs => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => snk_out,
- snk_in => snk_in,
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
+ snk_out => snk_out,
+ snk_in => snk_in,
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
+ );
gen_reverse : for I in 0 to g_reverse_len - 1 generate
demux_siso_arr(g_reverse_len - 1 - I) <= reverse_siso_arr(I);
@@ -91,18 +91,18 @@ begin
end generate;
u_mux_n_to_one : entity work.dp_interleave_n_to_one
- generic map (
- g_pipeline => g_pipeline_out,
- g_nof_inputs => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => g_pipeline_out,
+ g_nof_inputs => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out_arr => reverse_siso_arr,
- snk_in_arr => reverse_sosi_arr,
- src_in => src_in,
- src_out => src_out
- );
+ snk_out_arr => reverse_siso_arr,
+ snk_in_arr => reverse_sosi_arr,
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
index d492b2fb9f..81db0bd2a8 100644
--- a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
@@ -62,10 +62,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_rsn_source is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_selector.vhd b/libraries/base/dp/src/vhdl/dp_selector.vhd
index 045ffea428..18dd3de1fa 100644
--- a/libraries/base/dp/src/vhdl/dp_selector.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector.vhd
@@ -29,12 +29,12 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_selector is
generic (
@@ -63,24 +63,24 @@ architecture str of dp_selector is
begin
u_dp_selector_arr : entity work.dp_selector_arr
- generic map (
- g_nof_arr => 1,
- g_pipeline => g_pipeline
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_nof_arr => 1,
+ g_pipeline => g_pipeline
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- reg_selector_mosi => reg_selector_mosi,
- reg_selector_miso => reg_selector_miso,
+ reg_selector_mosi => reg_selector_mosi,
+ reg_selector_miso => reg_selector_miso,
- pipe_sosi_arr(0) => pipe_sosi,
- ref_sosi_arr(0) => ref_sosi,
- out_sosi_arr(0) => out_sosi,
+ pipe_sosi_arr(0) => pipe_sosi,
+ ref_sosi_arr(0) => ref_sosi,
+ out_sosi_arr(0) => out_sosi,
- selector_en => selector_en
- );
+ selector_en => selector_en
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
index 82c747c200..0fe7998eb7 100644
--- a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
@@ -32,12 +32,12 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_selector_arr is
generic (
@@ -77,21 +77,21 @@ begin
selector_en <= reg_selector_en(0);
u_mms_common_reg : entity common_lib.mms_common_reg
- generic map (
- g_mm_reg => c_selector_mem_reg
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- reg_mosi => reg_selector_mosi,
- reg_miso => reg_selector_miso,
-
- in_reg => reg_selector_en,
- out_reg => reg_selector_en
- );
+ generic map (
+ g_mm_reg => c_selector_mem_reg
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ reg_mosi => reg_selector_mosi,
+ reg_miso => reg_selector_miso,
+
+ in_reg => reg_selector_en,
+ out_reg => reg_selector_en
+ );
n_en <= not reg_selector_en(0);
@@ -104,34 +104,34 @@ begin
switch_high => reg_selector_en(0),
switch_low => n_en,
out_level => switch_select
- );
+ );
u_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_arr,
- g_pipeline => g_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => pipe_sosi_arr,
- src_out_arr => pipelined_pipe_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_arr,
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => pipe_sosi_arr,
+ src_out_arr => pipelined_pipe_sosi_arr
+ );
select_sosi_arr <= pipelined_pipe_sosi_arr when switch_select = '1' else ref_sosi_arr;
u_pipeline_arr_out : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_arr,
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => select_sosi_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_arr,
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => select_sosi_arr,
+ src_out_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftram.vhd b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
index bbb1631e13..41499c6cb3 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftram.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
@@ -23,13 +23,13 @@
-- Description:
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_shiftram is
generic (
@@ -80,58 +80,58 @@ begin
-----------------------------------------------------------------------------
gen_common_shiftram : for i in 0 to g_nof_streams - 1 generate
u_common_shiftram : entity common_lib.common_shiftram
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_words => g_nof_words
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- data_in => snk_in_arr(i).data(g_data_w - 1 downto 0),
- data_in_val => snk_in_arr(i).valid,
- data_in_shift => common_shiftram_shift_in_arr(i),
-
- data_out => src_out_arr(i).data(g_data_w - 1 downto 0),
- data_out_val => src_out_arr(i).valid,
- data_out_shift => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_words => g_nof_words
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ data_in => snk_in_arr(i).data(g_data_w - 1 downto 0),
+ data_in_val => snk_in_arr(i).valid,
+ data_in_shift => common_shiftram_shift_in_arr(i),
+
+ data_out => src_out_arr(i).data(g_data_w - 1 downto 0),
+ data_out_val => src_out_arr(i).valid,
+ data_out_shift => open
+ );
end generate;
-----------------------------------------------------------------------------
-- MM control
-----------------------------------------------------------------------------
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_stream : for i in 0 to g_nof_streams - 1 generate
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi_arr(i),
- mm_miso => reg_miso_arr(i),
+ mm_mosi => reg_mosi_arr(i),
+ mm_miso => reg_miso_arr(i),
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out_arr(i)
- );
+ slv_out => mm_fields_out_arr(i)
+ );
gen_no_sync : if g_use_sync_in = false generate
common_shiftram_shift_in_arr(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "shift") downto field_lo(c_field_arr, "shift"));
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
index 5d65ca25fa..35090235ec 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Move the valid input data through a shift register to have access to
@@ -180,16 +180,16 @@ begin
gen_output_reg : if g_output_reg = true generate
u_output : entity work.dp_pipeline
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => shiftreg_out,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => shiftreg_out,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_split.vhd b/libraries/base/dp/src/vhdl/dp_split.vhd
index fff84c9cd8..8880f79e79 100644
--- a/libraries/base/dp/src/vhdl/dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Split one frame into two frames.
@@ -194,18 +194,18 @@ begin
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => OPEN,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => OPEN,
+ src_out_reg => src_buf
+ );
-- Hold input register
nxt_src_buf <= next_src_buf;
@@ -281,7 +281,7 @@ begin
-- preserve tail data information for next state
nxt_tail <= tail; -- keep the tail data part in case the split is at symbol boundary and not at word boundary,
- -- keep the sop of the tail output, the valid and eop of tail are not used.
+ -- keep the sop of the tail output, the valid and eop of tail are not used.
-- pass on output
nxt_state <= state;
@@ -368,7 +368,7 @@ begin
if next_src_buf.eop = '1' then
i_snk_out <= c_dp_siso_rst; -- no input request for at least one clock cycle, to allow change in nof_symbols_reg and/or for state s_eop
if TO_UINT(v_input_empty) >= TO_UINT(head_empty_reg) then
- -- this is the last tail output, the input eop marks the tail output eop
+ -- this is the last tail output, the input eop marks the tail output eop
nxt_src_out_arr(c_tail).empty <= RESIZE_DP_EMPTY(func_dp_empty_split(v_input_empty, head_empty_reg, c_nof_symbols_per_data));
nxt_state <= s_head;
else -- need one more tail word to output the last tail part
diff --git a/libraries/base/dp/src/vhdl/dp_split_reg.vhd b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
index 16c0abe596..43b6be468c 100644
--- a/libraries/base/dp/src/vhdl/dp_split_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
@@ -31,9 +31,9 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_split_reg is
generic (
@@ -58,11 +58,13 @@ end dp_split_reg;
architecture str of dp_split_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0'
+ );
signal mm_nof_symbols : std_logic_vector(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
@@ -86,7 +88,7 @@ begin
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
- mm_nof_symbols <= sla_in.wrdata(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
+ mm_nof_symbols <= sla_in.wrdata(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
when others => null; -- not used MM addresses
end case;
@@ -107,16 +109,16 @@ begin
end process;
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_nof_symbols,
+ in_dat => mm_nof_symbols,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => nof_symbols
- );
+ out_dat => nof_symbols
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
index 9b20a22580..86966e22c9 100644
--- a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
+++ b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- . Control a source's output rate by toggling its ready input.
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index e466a0ad04..578190d8c9 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
@@ -121,15 +121,33 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_bsn_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_dsp_data_w),
+ '1',
+ '1',
+ '1',
+ to_unsigned(
+ 1,
+ c_dp_stream_empty_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_channel_w),
+ to_unsigned(
+ 1,
+ c_dp_stream_error_w)
+ );
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -208,33 +226,37 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Reset only the control fields of the DP sosi record
- function RESET_DP_SOSI_CTRL(sosi : t_dp_sosi) return t_dp_sosi;
+ function RESET_DP_SOSI_CTRL (sosi : t_dp_sosi) return t_dp_sosi;
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -243,150 +265,150 @@ package dp_stream_pkg is
-- Typically the sosi data are treated as unsigned in the record field, so extended with '0'. However for interpretating
-- signed data in the simulation wave window it is easier to use sign extension in the record field. Therefore TO_DP_SDATA
-- and RESIZE_DP_SDATA are defined as well.
- function TO_DP_BSN( n : natural) return std_logic_vector;
- function TO_DP_DATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
- function TO_DP_SDATA( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
- function TO_DP_UDATA( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector; -- for re and im fields, signed data
- function TO_DP_DSP_UDATA(n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
- function TO_DP_EMPTY( n : natural) return std_logic_vector;
- function TO_DP_CHANNEL( n : natural) return std_logic_vector;
- function TO_DP_ERROR( n : natural) return std_logic_vector;
- function RESIZE_DP_BSN( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_DATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
- function RESIZE_DP_SDATA( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
- function RESIZE_DP_XDATA( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
- function RESIZE_DP_EMPTY( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_CHANNEL( vec : std_logic_vector) return std_logic_vector;
- function RESIZE_DP_ERROR( vec : std_logic_vector) return std_logic_vector;
-
- function INCR_DP_DATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_SDATA( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
- function INCR_DP_BSN( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
- function INCR_DP_CHANNEL( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
-
- function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
-
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
+ function TO_DP_BSN ( n : natural) return std_logic_vector;
+ function TO_DP_DATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range, so -1 = 0xFFFFFFFF = +2**32-1
+ function TO_DP_SDATA ( n : integer) return std_logic_vector; -- use integer to support 32 bit range and signed
+ function TO_DP_UDATA ( n : integer) return std_logic_vector; -- alias of TO_DP_DATA()
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector; -- for re and im fields, signed data
+ function TO_DP_DSP_UDATA (n: integer) return std_logic_vector; -- for re and im fields, unsigned data (useful to carry indices)
+ function TO_DP_EMPTY ( n : natural) return std_logic_vector;
+ function TO_DP_CHANNEL ( n : natural) return std_logic_vector;
+ function TO_DP_ERROR ( n : natural) return std_logic_vector;
+ function RESIZE_DP_BSN ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_DATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to '0'
+ function RESIZE_DP_SDATA ( vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits
+ function RESIZE_DP_XDATA ( vec : std_logic_vector) return std_logic_vector; -- set unused MSBits to 'X'
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector; -- sign extend unused MSBits of re and im fields
+ function RESIZE_DP_EMPTY ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_CHANNEL ( vec : std_logic_vector) return std_logic_vector;
+ function RESIZE_DP_ERROR ( vec : std_logic_vector) return std_logic_vector;
+
+ function INCR_DP_DATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
+ function INCR_DP_SDATA ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- signed vec(w-1:0) + dec
+ function INCR_DP_BSN ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
+ function INCR_DP_CHANNEL ( vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector; -- unsigned vec(w-1:0) + dec
+
+ function REPLICATE_DP_DATA ( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
+
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Map between array and single element
- function TO_DP_ARR(sosi : t_dp_sosi) return t_dp_sosi_arr;
- function TO_DP_ARR(siso : t_dp_siso) return t_dp_siso_arr;
- function TO_DP_ONE(sosi_arr : t_dp_sosi_arr) return t_dp_sosi;
- function TO_DP_ONE(siso_arr : t_dp_siso_arr) return t_dp_siso;
+ function TO_DP_ARR (sosi : t_dp_sosi) return t_dp_sosi_arr;
+ function TO_DP_ARR (siso : t_dp_siso) return t_dp_siso_arr;
+ function TO_DP_ONE (sosi_arr : t_dp_sosi_arr) return t_dp_sosi;
+ function TO_DP_ONE (siso_arr : t_dp_siso_arr) return t_dp_siso;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
-- Shift and combine part of previous data and this data, use the other sosi from prev_sosi
- function func_dp_data_shift( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
+ function func_dp_data_shift ( prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi;
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
+ function func_dp_data_shift_last ( tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi;
-- Determine resulting empty if two streams are concatenated or split
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector;
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi;
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi;
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_siso_arr; str : string) return std_logic;
- function func_dp_stream_arr_or( dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_siso_arr; str : string) return std_logic;
+ function func_dp_stream_arr_or ( dp : t_dp_sosi_arr; str : string) return std_logic;
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr; -- also support slv fields
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr; -- also support slv fields
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr;
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr;
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector;
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector;
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr;
-- Fix reversed buses due to connecting TO to DOWNTO range arrays.
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr;
-- Functions to combinatorially hold the data fields and to set or reset the control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_info( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_set_control( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
- function func_dp_stream_arr_reset_control( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_info ( dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_set_control ( dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr;
+ function func_dp_stream_arr_reset_control ( dp : t_dp_sosi_arr ) return t_dp_sosi_arr;
-- Reset sosi ctrl and preserve the sosi data (to avoid unnecessary data toggling and to ease data view in Wave window)
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector;
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector;
-- Function to copy the BSN of one valid stream to all output streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr;
-- Functions to combinatorially handle channels
-- Note that the *_select and *_remove function are equivalent to dp_demux with g_combined=TRUE
- function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, add the channel field
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- select channel nr, skip the channel field
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi; -- skip channel nr
-- Functions to combinatorially handle the error field
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi; -- force err = 0, is OK
-- Functions to combinatorially handle the BSN field
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi;
-- Functions to combine sosi fields
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi;
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi;
-- Functions to convert sosi fields
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer;
-- Functions to set the DATA, RE and IM field in a stream.
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
-
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
-
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string ) return t_dp_sosi;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
+
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
+
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural ) return t_dp_sosi_arr;
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural ) return t_dp_sosi_arr;
-- Concatenate the data and complex re,im fields from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi; -- Concat SOSI_ARR data into single SOSI
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr; -- Wire single SISO to SISO_ARR
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
-- . data_representation = "SIGNED" treat sosi.data field as signed
@@ -395,18 +417,18 @@ package dp_stream_pkg is
-- . data_order_im_re = TRUE then "COMPLEX" data = im&re
-- FALSE then "COMPLEX" data = re&im
-- ignore when data_representation /= "COMPLEX"
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr;
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string ) return t_dp_sosi_arr;
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
-- Return TRUE when the sosi.data of both streams matches (and is valid)
- function func_dp_data_match(snk_in_a, snk_in_b: t_dp_sosi; data_w: natural) return boolean;
- function func_dp_data_match(snk_in_a, snk_in_b, snk_in_c: t_dp_sosi; data_w: natural) return boolean;
+ function func_dp_data_match (snk_in_a, snk_in_b: t_dp_sosi; data_w: natural) return boolean;
+ function func_dp_data_match (snk_in_a, snk_in_b, snk_in_c: t_dp_sosi; data_w: natural) return boolean;
end dp_stream_pkg;
@@ -414,11 +436,12 @@ end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -432,20 +455,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -463,16 +488,17 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert (
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
-- Reset only the control fields of the DP sosi record
- function RESET_DP_SOSI_CTRL(sosi : t_dp_sosi) return t_dp_sosi is
+ function RESET_DP_SOSI_CTRL (sosi : t_dp_sosi) return t_dp_sosi is
variable v_sosi : t_dp_sosi := sosi;
begin
v_sosi.sync := '0';
@@ -483,120 +509,120 @@ package body dp_stream_pkg is
end RESET_DP_SOSI_CTRL;
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
- function TO_DP_BSN(n : natural) return std_logic_vector is
+ function TO_DP_BSN (n : natural) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_bsn_w);
end TO_DP_BSN;
- function TO_DP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_DATA;
- function TO_DP_SDATA(n : integer) return std_logic_vector is
+ function TO_DP_SDATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_data_w);
end TO_DP_SDATA;
- function TO_DP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_UDATA (n : integer) return std_logic_vector is
begin
return TO_DP_DATA(n);
end TO_DP_UDATA;
- function TO_DP_DSP_DATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_DATA (n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_DATA;
- function TO_DP_DSP_UDATA(n : integer) return std_logic_vector is
+ function TO_DP_DSP_UDATA (n : integer) return std_logic_vector is
begin
return RESIZE_UVEC(TO_SVEC(n, 32), c_dp_stream_dsp_data_w);
end TO_DP_DSP_UDATA;
- function TO_DP_EMPTY(n : natural) return std_logic_vector is
+ function TO_DP_EMPTY (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_empty_w);
end TO_DP_EMPTY;
- function TO_DP_CHANNEL(n : natural) return std_logic_vector is
+ function TO_DP_CHANNEL (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_channel_w);
end TO_DP_CHANNEL;
- function TO_DP_ERROR(n : natural) return std_logic_vector is
+ function TO_DP_ERROR (n : natural) return std_logic_vector is
begin
return TO_UVEC(n, c_dp_stream_error_w);
end TO_DP_ERROR;
- function RESIZE_DP_BSN(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_BSN (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_bsn_w);
end RESIZE_DP_BSN;
- function RESIZE_DP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_DATA;
- function RESIZE_DP_SDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_SDATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_data_w);
end RESIZE_DP_SDATA;
- function RESIZE_DP_XDATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_XDATA (vec : std_logic_vector) return std_logic_vector is
variable v_vec : std_logic_vector(c_dp_stream_data_w - 1 downto 0) := (others => 'X');
begin
v_vec(vec'length - 1 downto 0) := vec;
return v_vec;
end RESIZE_DP_XDATA;
- function RESIZE_DP_DSP_DATA(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_DSP_DATA (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_SVEC(vec, c_dp_stream_dsp_data_w);
end RESIZE_DP_DSP_DATA;
- function RESIZE_DP_EMPTY(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_EMPTY (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_empty_w);
end RESIZE_DP_EMPTY;
- function RESIZE_DP_CHANNEL(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_CHANNEL (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_channel_w);
end RESIZE_DP_CHANNEL;
- function RESIZE_DP_ERROR(vec : std_logic_vector) return std_logic_vector is
+ function RESIZE_DP_ERROR (vec : std_logic_vector) return std_logic_vector is
begin
return RESIZE_UVEC(vec, c_dp_stream_error_w);
end RESIZE_DP_ERROR;
- function INCR_DP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DATA(std_logic_vector(unsigned(vec(w - 1 downto 0)) + dec));
end INCR_DP_DATA;
- function INCR_DP_SDATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_SDATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_SDATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_SDATA;
- function INCR_DP_DSP_DATA(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_DSP_DATA (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_DSP_DATA(std_logic_vector(signed(vec(w - 1 downto 0)) + dec));
end INCR_DP_DSP_DATA;
- function INCR_DP_BSN(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_BSN (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_BSN(std_logic_vector(unsigned(vec(w - 1 downto 0)) + dec));
end INCR_DP_BSN;
- function INCR_DP_CHANNEL(vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
+ function INCR_DP_CHANNEL (vec : std_logic_vector; dec : integer; w : natural) return std_logic_vector is
begin
return RESIZE_DP_CHANNEL(std_logic_vector(unsigned(vec(w - 1 downto 0)) + dec));
end INCR_DP_CHANNEL;
- function REPLICATE_DP_DATA(seq : std_logic_vector) return std_logic_vector is
+ function REPLICATE_DP_DATA (seq : std_logic_vector) return std_logic_vector is
constant c_seq_w : natural := seq'length;
constant c_nof_replications : natural := ceil_div(c_dp_stream_data_w, c_seq_w);
constant c_vec_w : natural := ceil_value(c_dp_stream_data_w, c_seq_w);
@@ -608,7 +634,7 @@ package body dp_stream_pkg is
return v_vec(c_dp_stream_data_w - 1 downto 0);
end REPLICATE_DP_DATA;
- function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w :natural) return std_logic_vector is
+ function UNREPLICATE_DP_DATA (data : std_logic_vector; seq_w :natural) return std_logic_vector is
constant c_data_w : natural := data'length;
constant c_nof_replications : natural := ceil_div(c_data_w, seq_w);
constant c_vec_w : natural := ceil_value(c_data_w, seq_w);
@@ -627,7 +653,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_UNSIGNED(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_UNSIGNED (sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -645,31 +671,31 @@ package body dp_stream_pkg is
end TO_DP_SOSI_UNSIGNED;
-- Map between array and single element
- function TO_DP_ARR(sosi : t_dp_sosi) return t_dp_sosi_arr is
+ function TO_DP_ARR (sosi : t_dp_sosi) return t_dp_sosi_arr is
variable v_sosi_arr : t_dp_sosi_arr(0 downto 0) := (others => sosi);
begin
return v_sosi_arr;
end TO_DP_ARR;
- function TO_DP_ARR(siso : t_dp_siso) return t_dp_siso_arr is
+ function TO_DP_ARR (siso : t_dp_siso) return t_dp_siso_arr is
variable v_siso_arr : t_dp_siso_arr(0 downto 0) := (others => siso);
begin
return v_siso_arr;
end TO_DP_ARR;
- function TO_DP_ONE(sosi_arr : t_dp_sosi_arr) return t_dp_sosi is
+ function TO_DP_ONE (sosi_arr : t_dp_sosi_arr) return t_dp_sosi is
begin
return sosi_arr(0);
end TO_DP_ONE;
- function TO_DP_ONE(siso_arr : t_dp_siso_arr) return t_dp_siso is
+ function TO_DP_ONE (siso_arr : t_dp_siso_arr) return t_dp_siso is
begin
return siso_arr(0);
end TO_DP_ONE;
-- Keep part of head data and combine part of tail data
- function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
+ function func_dp_data_shift_first (head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
begin
@@ -686,7 +712,7 @@ package body dp_stream_pkg is
-- Shift and combine part of previous data and this data,
- function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
+ function func_dp_data_shift (prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
variable vN : natural := nof_symbols_per_data;
variable v_sosi : t_dp_sosi;
@@ -719,7 +745,7 @@ package body dp_stream_pkg is
-- Shift part of tail data and account for input empty
- function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
+ function func_dp_data_shift_last (tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
variable vL : natural := input_empty;
variable vN : natural := nof_symbols_per_data;
@@ -749,7 +775,7 @@ package body dp_stream_pkg is
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
- function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_concat (head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(head_empty);
@@ -761,7 +787,7 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_concat;
- function func_dp_empty_split(input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
+ function func_dp_empty_split (input_empty, head_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
variable v_a, v_b, v_empty : natural;
begin
v_a := TO_UINT(input_empty);
@@ -776,7 +802,7 @@ package body dp_stream_pkg is
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
- function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
+ function func_dp_sosi_arr_mux (dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
begin
for I in dp'range loop
@@ -790,7 +816,7 @@ package body dp_stream_pkg is
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -812,7 +838,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -836,19 +862,19 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_and(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_and (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_and(dp, c_mask, str);
end func_dp_stream_arr_and;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -870,7 +896,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '0'); -- set default v_vec such that unmasked input have no influence on operation result
variable v_any : std_logic := '0';
begin
@@ -894,13 +920,13 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_siso_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_siso_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
- function func_dp_stream_arr_or(dp : t_dp_sosi_arr; str : string) return std_logic is
+ function func_dp_stream_arr_or (dp : t_dp_sosi_arr; str : string) return std_logic is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_or(dp, c_mask, str);
@@ -908,7 +934,7 @@ package body dp_stream_pkg is
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
@@ -921,7 +947,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- default
variable v_slv : std_logic_vector(dp'range) := slv(dp'range); -- map to ensure same range as for dp
begin
@@ -942,19 +968,19 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
+ function func_dp_stream_arr_set (dp : t_dp_siso_arr; sl : std_logic; str : string) return t_dp_siso_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_set(dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set (dp : t_dp_sosi_arr; sl : std_logic; str : string) return t_dp_sosi_arr is
variable v_slv : std_logic_vector(dp'range) := (others => sl);
begin
return func_dp_stream_arr_set(dp, v_slv, str);
end func_dp_stream_arr_set;
- function func_dp_stream_arr_get(dp : t_dp_siso_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_siso_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -966,7 +992,7 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
- function func_dp_stream_arr_get(dp : t_dp_sosi_arr; str : string) return std_logic_vector is
+ function func_dp_stream_arr_get (dp : t_dp_sosi_arr; str : string) return std_logic_vector is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
@@ -982,7 +1008,7 @@ package body dp_stream_pkg is
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -995,7 +1021,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso_arr; b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -1008,7 +1034,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_siso; b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -1021,7 +1047,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_siso_arr) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
begin
for I in sel'range loop
@@ -1034,7 +1060,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1047,7 +1073,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi_arr; b : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1060,7 +1086,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a : t_dp_sosi; b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1073,7 +1099,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_select (sel : std_logic_vector; a, b : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(sel'range);
begin
for I in sel'range loop
@@ -1086,7 +1112,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_select;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_siso_arr) return t_dp_siso_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_siso_arr) return t_dp_siso_arr is
variable v_to_range : t_dp_siso_arr(0 to in_arr'high);
variable v_downto_range : t_dp_siso_arr(in_arr'high downto 0);
begin
@@ -1103,7 +1129,7 @@ package body dp_stream_pkg is
end if;
end func_dp_stream_arr_reverse_range;
- function func_dp_stream_arr_reverse_range(in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reverse_range (in_arr : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_to_range : t_dp_sosi_arr(0 to in_arr'high);
variable v_downto_range : t_dp_sosi_arr(in_arr'high downto 0);
begin
@@ -1121,7 +1147,7 @@ package body dp_stream_pkg is
end func_dp_stream_arr_reverse_range;
-- Functions to combinatorially hold the data fields and to set or reset the info and control fields in an sosi array
- function func_dp_stream_arr_combine_data_info_ctrl(dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_combine_data_info_ctrl (dp : t_dp_sosi_arr; info, ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
v_dp := func_dp_stream_arr_set_info( v_dp, info); -- set sosi info
@@ -1129,7 +1155,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_combine_data_info_ctrl;
- function func_dp_stream_arr_set_info(dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_info (dp : t_dp_sosi_arr; info : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi info
@@ -1141,7 +1167,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_info;
- function func_dp_stream_arr_set_control(dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
+ function func_dp_stream_arr_set_control (dp : t_dp_sosi_arr; ctrl : t_dp_sosi) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- set sosi control
@@ -1153,7 +1179,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_set_control;
- function func_dp_stream_arr_reset_control(dp : t_dp_sosi_arr) return t_dp_sosi_arr is
+ function func_dp_stream_arr_reset_control (dp : t_dp_sosi_arr) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
for I in dp'range loop -- reset sosi control
@@ -1165,7 +1191,7 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_reset_control;
- function func_dp_stream_reset_control(dp : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_reset_control (dp : t_dp_sosi) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp; -- hold sosi data
begin
-- reset sosi control
@@ -1177,7 +1203,7 @@ package body dp_stream_pkg is
end func_dp_stream_reset_control;
-- Functions to combinatorially determine the maximum and minimum sosi bsn[w-1:0] value in the sosi array (for all elements or only for the mask[]='1' elements)
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '0'); -- init max v_bsn with minimum value
begin
for I in dp'range loop
@@ -1190,13 +1216,13 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_max(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_max (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_max(dp, c_mask, w);
end func_dp_stream_arr_bsn_max;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; mask : std_logic_vector; w : natural) return std_logic_vector is
variable v_bsn : std_logic_vector(w - 1 downto 0) := (others => '1'); -- init min v_bsn with maximum value
begin
for I in dp'range loop
@@ -1209,14 +1235,14 @@ package body dp_stream_pkg is
return v_bsn;
end func_dp_stream_arr_bsn_min;
- function func_dp_stream_arr_bsn_min(dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
+ function func_dp_stream_arr_bsn_min (dp : t_dp_sosi_arr; w : natural) return std_logic_vector is
constant c_mask : std_logic_vector(dp'range) := (others => '1');
begin
return func_dp_stream_arr_bsn_min(dp, c_mask, w);
end func_dp_stream_arr_bsn_min;
-- Function to copy the BSN number of one valid stream to all other streams.
- function func_dp_stream_arr_copy_valid_bsn(dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_arr_copy_valid_bsn (dp : t_dp_sosi_arr; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
variable v_dp : t_dp_sosi_arr(dp'range) := dp; -- hold sosi data
begin
@@ -1233,14 +1259,14 @@ package body dp_stream_pkg is
-- Functions to combinatorially handle channels
- function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_set (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.channel := TO_UVEC(ch, c_dp_stream_channel_w);
return v_rec;
end func_dp_stream_channel_set;
- function func_dp_stream_channel_select(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_select (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) /= ch then
@@ -1251,7 +1277,7 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_select;
- function func_dp_stream_channel_remove(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
+ function func_dp_stream_channel_remove (st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
if unsigned(st_sosi.channel) = ch then
@@ -1263,7 +1289,7 @@ package body dp_stream_pkg is
end func_dp_stream_channel_remove;
- function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
+ function func_dp_stream_error_set (st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.err := TO_UVEC(n, c_dp_stream_error_w);
@@ -1271,7 +1297,7 @@ package body dp_stream_pkg is
end func_dp_stream_error_set;
- function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
+ function func_dp_stream_bsn_set (st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
v_rec.bsn := RESIZE_DP_BSN(bsn);
@@ -1279,7 +1305,7 @@ package body dp_stream_pkg is
end func_dp_stream_bsn_set;
- function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
+ function func_dp_stream_combine_info_and_data (info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
-- Combine sosi data with the sosi info fields
@@ -1292,7 +1318,7 @@ package body dp_stream_pkg is
end func_dp_stream_combine_info_and_data;
- function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
+ function func_dp_stream_slv_to_integer (slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
v_rec.sync := slv_sosi.sync;
@@ -1309,23 +1335,23 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_slv_to_integer;
- function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
+ function func_dp_stream_set_data (dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1334,7 +1360,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
+ function func_dp_stream_set_data (dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr is
variable v_dp : t_dp_sosi_arr(dp'range) := dp;
begin
for I in dp'range loop
@@ -1345,8 +1371,8 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_re : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1367,17 +1393,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_complex_to_data (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_complex_to_data(dp, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
variable v_hi : std_logic_vector(c_compl_data_w - 1 downto 0);
@@ -1400,17 +1426,17 @@ package body dp_stream_pkg is
return v_dp;
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural; nof_data : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_data_to_complex (dp : t_dp_sosi; data_w : natural) return t_dp_sosi is
begin
return func_dp_stream_data_to_complex(dp, data_w, 1, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1419,17 +1445,17 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_complex_to_data(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_complex_to_data (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_complex_to_data(dp_arr, data_w, 1, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_dp_arr : t_dp_sosi_arr(dp_arr'range);
begin
for i in dp_arr'range loop
@@ -1438,18 +1464,18 @@ package body dp_stream_pkg is
return v_dp_arr;
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural; nof_data : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, nof_data, true);
end;
- function func_dp_stream_data_to_complex(dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_data_to_complex (dp_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi_arr is
begin
return func_dp_stream_data_to_complex(dp_arr, data_w, 1, true);
end;
-- Concatenate the data (and complex fields) from a SOSI array into a single SOSI stream (assumes streams are in sync)
- function func_dp_stream_concat(snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
+ function func_dp_stream_concat (snk_in_arr : t_dp_sosi_arr; data_w : natural) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out : t_dp_sosi := snk_in_arr(0);
begin
@@ -1464,7 +1490,7 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_concat(src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
+ function func_dp_stream_concat (src_in : t_dp_siso; nof_streams : natural) return t_dp_siso_arr is -- Wire single SISO to SISO_ARR
variable v_snk_out_arr : t_dp_siso_arr(nof_streams - 1 downto 0);
begin
for i in v_snk_out_arr'range loop
@@ -1474,7 +1500,7 @@ package body dp_stream_pkg is
end;
-- Reconcatenate the data and complex re,im fields from a SOSI array from nof_data*in_w to nof_data*out_w
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_in_w : natural := in_w / 2;
constant c_compl_out_w : natural := out_w / 2;
variable v_src_out : t_dp_sosi := snk_in;
@@ -1512,12 +1538,12 @@ package body dp_stream_pkg is
return v_src_out;
end;
- function func_dp_stream_reconcat(snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
+ function func_dp_stream_reconcat (snk_in : t_dp_sosi; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi is
begin
return func_dp_stream_reconcat(snk_in, in_w, out_w, nof_data, data_representation, true);
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string; data_order_im_re : boolean) return t_dp_sosi_arr is
variable v_src_out_arr : t_dp_sosi_arr(snk_in_arr'range) := snk_in_arr;
begin
for i in v_src_out_arr'range loop
@@ -1526,13 +1552,13 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_reconcat(snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
+ function func_dp_stream_reconcat (snk_in_arr : t_dp_sosi_arr; in_w, out_w, nof_data : natural; data_representation : string) return t_dp_sosi_arr is
begin
return func_dp_stream_reconcat(snk_in_arr, in_w, out_w, nof_data, data_representation, true);
end;
-- Deconcatenate data from SOSI into SOSI array
- function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
+ function func_dp_stream_deconcat (snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr is
constant c_compl_data_w : natural := data_w / 2;
variable v_src_out_arr : t_dp_sosi_arr(nof_streams - 1 downto 0);
begin
@@ -1548,13 +1574,13 @@ package body dp_stream_pkg is
return v_src_out_arr;
end;
- function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
+ function func_dp_stream_deconcat (src_out_arr : t_dp_siso_arr) return t_dp_siso is -- Wire SISO_ARR(0) to single SISO
begin
return src_out_arr(0);
end;
-- Return TRUE when the sosi.data of both streams matches (and is valid)
- function func_dp_data_match(snk_in_a, snk_in_b: t_dp_sosi; data_w : natural) return boolean is
+ function func_dp_data_match (snk_in_a, snk_in_b: t_dp_sosi; data_w : natural) return boolean is
variable result : boolean;
begin
result := false;
@@ -1567,7 +1593,7 @@ package body dp_stream_pkg is
end;
-- Return TRUE when the sosi.data of all streams matches (and is valid)
- function func_dp_data_match(snk_in_a, snk_in_b, snk_in_c: t_dp_sosi; data_w : natural) return boolean is
+ function func_dp_data_match (snk_in_a, snk_in_b, snk_in_c: t_dp_sosi; data_w : natural) return boolean is
begin
return func_dp_data_match(snk_in_a, snk_in_b, data_w) and func_dp_data_match(snk_in_b, snk_in_c, data_w);
end;
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 211fc2020f..446d5e3579 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -74,11 +74,11 @@
-- ref_sync stopped already.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_components_pkg.all;
entity dp_strobe_total_count is
generic (
@@ -111,11 +111,13 @@ architecture rtl of dp_strobe_total_count is
constant c_flush_adr : natural := c_dp_strobe_total_count_reg_flush_adr;
-- Define the size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_dp_strobe_total_count_reg_adr_w,
- dat_w => g_mm_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_dp_strobe_total_count_reg_nof_words,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_dp_strobe_total_count_reg_adr_w,
+ dat_w => g_mm_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_dp_strobe_total_count_reg_nof_words,
+ init_sl => '0'
+ );
type t_cnt_arr is array (integer range <>) of std_logic_vector(g_count_w - 1 downto 0);
@@ -145,28 +147,28 @@ begin
mm_cnt_flush <= reg_mosi.wr when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_flush_adr else '0';
u_common_spulse_clear : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_cnt_clear,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_pulse => dp_cnt_clear
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_cnt_clear,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_pulse => dp_cnt_clear
+ );
-- Support cnt clear via either MM or via an input strobe, use register
-- to ease timing closure
cnt_clr <= dp_cnt_clear or in_clr when rising_edge(dp_clk);
u_common_spulse_flush : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_cnt_flush,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_pulse => dp_cnt_flush
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_cnt_flush,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_pulse => dp_cnt_flush
+ );
-- Register inputs to ease timing closure
-- . register ref_sync to ease timing closure for ref_sync fanout
@@ -202,18 +204,18 @@ begin
cnt_en_arr(I) <= cnt_en and in_strobe_reg2_arr(I);
u_counter : entity common_lib.common_counter
- generic map (
- g_width => g_count_w,
- g_clip => g_clip
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => g_count_w,
+ g_clip => g_clip
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en_arr(I),
- count => cnt_arr(I)
- );
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en_arr(I),
+ count => cnt_arr(I)
+ );
end generate;
-- Hold counter values at ref_sync_reg2 to have stable values for MM read
@@ -243,27 +245,27 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => rd_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => rd_reg, -- read only
+ out_reg => open -- no write
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_switch.vhd b/libraries/base/dp/src/vhdl/dp_switch.vhd
index 5ba1d4d7ad..dd0022438c 100644
--- a/libraries/base/dp/src/vhdl/dp_switch.vhd
+++ b/libraries/base/dp/src/vhdl/dp_switch.vhd
@@ -33,11 +33,11 @@
-- . So this does not work for continuous streams!
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_switch is
generic (
@@ -97,37 +97,37 @@ begin
-- A single MM register contains input to select
------------------------------------------------------------------------------
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
------------------------------------------------------------------------------
-- put dp_xonoff block inbetween data path to control data flow.
------------------------------------------------------------------------------
gen_dp_xonoff_arr : for i in 0 to g_nof_inputs - 1 generate
u_dp_xonoff: entity work.dp_xonoff
- port map (
- clk => dp_clk,
- rst => dp_rst,
- -- Frame in
- in_sosi => snk_in_arr(i),
- in_siso => snk_out_arr(i),
- -- Frame out
- out_siso => xonoff_src_in_arr(i), -- flush control done by dp_mux.snk_out_arr
- out_sosi => xonoff_src_out_arr(i)
- );
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+ -- Frame in
+ in_sosi => snk_in_arr(i),
+ in_siso => snk_out_arr(i),
+ -- Frame out
+ out_siso => xonoff_src_in_arr(i), -- flush control done by dp_mux.snk_out_arr
+ out_sosi => xonoff_src_out_arr(i)
+ );
end generate;
------------------------------------------------------------------------------
@@ -149,36 +149,36 @@ begin
-- DP mux forwards input based on dp_mux_sel_ctrl
------------------------------------------------------------------------------
u_dp_mux : entity work.dp_mux
- generic map (
- g_mode => 4, -- Use sel_ctrl
- g_sel_ctrl_invert => false, -- Dont invert, data is already reverse mapped from DOWNTO >> TO arrays.
- g_nof_input => g_nof_inputs,
- g_use_fifo => g_use_fifo,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_in_channel_w => g_in_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_in_channel => g_use_in_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_size => array_init(g_fifo_size, g_nof_inputs),
- g_fifo_fill => array_init(g_fifo_fill, g_nof_inputs)
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- sel_ctrl => dp_mux_sel_ctrl,
-
- snk_in_arr => inverted_snk_in_arr,
- snk_out_arr => inverted_snk_out_arr,
-
- src_out => src_out,
- src_in => src_in
- );
+ generic map (
+ g_mode => 4, -- Use sel_ctrl
+ g_sel_ctrl_invert => false, -- Dont invert, data is already reverse mapped from DOWNTO >> TO arrays.
+ g_nof_input => g_nof_inputs,
+ g_use_fifo => g_use_fifo,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_in_channel_w => g_in_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_in_channel => g_use_in_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_size => array_init(g_fifo_size, g_nof_inputs),
+ g_fifo_fill => array_init(g_fifo_fill, g_nof_inputs)
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ sel_ctrl => dp_mux_sel_ctrl,
+
+ snk_in_arr => inverted_snk_in_arr,
+ snk_out_arr => inverted_snk_out_arr,
+
+ src_out => src_out,
+ src_in => src_in
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
index bdd968f814..efa5b1b505 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
@@ -48,11 +48,11 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_checker is
generic(
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
index 6cfdc15935..9bb236cd2b 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
@@ -35,10 +35,10 @@
-- incoming data is perfectly aligned. Use a dp_sync_checker to assure the incoming data is perfect.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_insert is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
index 9532abac3f..e4188e18b2 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_insert_v2 is
generic (
@@ -125,28 +125,28 @@ begin
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_nof_blk_per_sync_mm_reg,
- g_init_reg => c_init_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => reg_nof_blk_per_sync,
- out_reg => reg_nof_blk_per_sync
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_nof_blk_per_sync_mm_reg,
+ g_init_reg => c_init_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => reg_nof_blk_per_sync,
+ out_reg => reg_nof_blk_per_sync
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
index 4a4dc90eb1..e78d021ac8 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
@@ -38,11 +38,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_recover is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
index 280865f0a5..3482be830e 100644
--- a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
@@ -29,18 +29,18 @@
-- remove 0 or more head data and 0 or more tail data from the input block.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_tail_remove is
generic (
g_data_w : natural;
g_symbol_w : natural;
g_nof_symbols : natural -- Nof symbols to be stripped from end of the packet,
- -- and accounting for the nof empty symbols.
+ -- and accounting for the nof empty symbols.
);
port (
st_rst : in std_logic;
@@ -72,25 +72,25 @@ begin
snk_out <= src_in;
u_src_shift : entity work.dp_shiftreg
- generic map (
- g_output_reg => c_output_reg,
- g_flush_eop => true,
- g_modify_support => true,
- g_nof_words => c_nof_shiftreg_words
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- Control shift register contents
- cur_shiftreg_inputs => rd_sosi_arr,
- new_shiftreg_inputs => wr_sosi_arr,
- -- ST source
- src_in => src_in, -- We correct the stream via new_shiftreg_inputs, so
- src_out => src_out -- the shiftreg sources everything but the tail.
- );
+ generic map (
+ g_output_reg => c_output_reg,
+ g_flush_eop => true,
+ g_modify_support => true,
+ g_nof_words => c_nof_shiftreg_words
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- Control shift register contents
+ cur_shiftreg_inputs => rd_sosi_arr,
+ new_shiftreg_inputs => wr_sosi_arr,
+ -- ST source
+ src_in => src_in, -- We correct the stream via new_shiftreg_inputs, so
+ src_out => src_out -- the shiftreg sources everything but the tail.
+ );
p_shift: process(rd_sosi_arr)
variable v_wr_sosi_arr : t_dp_sosi_arr(0 to c_nof_shiftreg_words - 1);
diff --git a/libraries/base/dp/src/vhdl/dp_throttle.vhd b/libraries/base/dp/src/vhdl/dp_throttle.vhd
index fa7dd4d811..84e2ec7175 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle is
generic (
g_dc_period : natural := 100; -- provides a resolution of 1% (1/100..100/100)
g_throttle_valid : boolean := false -- FALSE: Stream passes through, snk_out.ready is AND'ed with pulse
- -- TRUE : Throttles src_out.valid instead of snk_out.ready; Onther entity I/O unused.
+ -- TRUE : Throttles src_out.valid instead of snk_out.ready; Onther entity I/O unused.
);
port (
rst : in std_logic;
@@ -64,22 +64,22 @@ begin
end generate;
u_common_duty_cycle : entity common_lib.common_duty_cycle
- generic map (
- g_rst_lvl => '0', -- Start with '0' on the output so our connected sink is not maxed out after reset
- g_dis_lvl => '0', -- Don't care - dc_out_en is not used.
- g_act_lvl => '1',
- g_per_cnt => g_dc_period,
- g_act_cnt => 0 -- After init, stay in idle state until we write a new DC value
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_rst_lvl => '0', -- Start with '0' on the output so our connected sink is not maxed out after reset
+ g_dis_lvl => '0', -- Don't care - dc_out_en is not used.
+ g_act_lvl => '1',
+ g_per_cnt => g_dc_period,
+ g_act_cnt => 0 -- After init, stay in idle state until we write a new DC value
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- dc_act_cnt => throttle,
+ dc_act_cnt => throttle,
- dc_out_en => '1', -- We can also disable the output by writing zero to dc_act_cnt.
- dc_out => dc_out
- );
+ dc_out_en => '1', -- We can also disable the output by writing zero to dc_act_cnt.
+ dc_out => dc_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
index 10d5e4a7ce..b7884110b1 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_throttle_reg is
generic (
@@ -48,11 +48,13 @@ end dp_throttle_reg;
architecture rtl of dp_throttle_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0'
+ );
signal mm_throttle : std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0);
@@ -63,7 +65,7 @@ begin
if mm_rst = '1' then
-- Access event, register values
mm_throttle <= (others => '0');
- elsif rising_edge(mm_clk) then
+ elsif rising_edge(mm_clk) then
-- Read access defaults
sla_out.rdval <= '0';
@@ -83,15 +85,15 @@ begin
end process;
u_common_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_throttle,
- in_done => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => throttle,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_throttle,
+ in_done => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => throttle,
+ out_new => open
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
index 2a769f7a58..963c4050ec 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
@@ -26,9 +26,9 @@
-- . g_period is
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle_sop is
generic (
@@ -60,34 +60,34 @@ begin
snk_out.xon <= '1';
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cycle_cnt
- );
+ generic map (
+ g_width => c_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cycle_cnt
+ );
cnt_en <= '1' when TO_UINT(cycle_cnt) < g_period - 2 else '0';
cnt_clr <= snk_in.sop;
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => false,
- g_or_high => true,
- g_and_low => true
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => switch_high,
- switch_low => switch_low,
- out_level => switch_out
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => false,
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => switch_high,
+ switch_low => switch_low,
+ out_level => switch_out
+ );
switch_high <= not cnt_en;
switch_low <= snk_in.eop;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
index 48ca4a6a11..ffb88add3b 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
@@ -29,9 +29,9 @@
-- * (1/'data valid duty_cycle').
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle_xon is
diff --git a/libraries/base/dp/src/vhdl/dp_unfolder.vhd b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
index 6d6bb3c5bb..e52e1268ec 100644
--- a/libraries/base/dp/src/vhdl/dp_unfolder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -145,8 +145,8 @@ begin
-- Wire the 2D demux output array to 1D array to match entity I/O type
-----------------------------------------------------------------------------
gen_demux_inputs_0: for i in 0 to c_nof_demuxes - 1 generate
- demux_src_out_arr(2 * i) <= demux_src_out_2arr_2(i)(0);
- demux_src_out_arr(2 * i + 1) <= demux_src_out_2arr_2(i)(1);
+ demux_src_out_arr(2 * i) <= demux_src_out_2arr_2(i)(0);
+ demux_src_out_arr(2 * i + 1) <= demux_src_out_2arr_2(i)(1);
end generate;
-----------------------------------------------------------------------------
@@ -154,21 +154,21 @@ begin
-----------------------------------------------------------------------------
gen_dp_unfolder: if g_nof_unfolds > 1 generate
u_dp_unfolder : dp_unfolder
- generic map (
- g_nof_inputs => c_nof_demuxes * 2, -- Next stage has all our demux outputs as inputs
- g_nof_unfolds => g_nof_unfolds - 1,
- g_output_block_size => g_output_block_size,
- g_fwd_sync_bsn => g_fwd_sync_bsn,
- g_use_channel => g_use_channel,
- g_output_align => g_output_align
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in_arr => demux_src_out_arr,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_inputs => c_nof_demuxes * 2, -- Next stage has all our demux outputs as inputs
+ g_nof_unfolds => g_nof_unfolds - 1,
+ g_output_block_size => g_output_block_size,
+ g_fwd_sync_bsn => g_fwd_sync_bsn,
+ g_use_channel => g_use_channel,
+ g_output_align => g_output_align
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in_arr => demux_src_out_arr,
+ src_out_arr => src_out_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -184,16 +184,16 @@ begin
-----------------------------------------------------------------------------
gen_dp_pipeline : for i in 0 to c_nof_outputs - 1 generate
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 0 + (pow2(g_nof_unfolds) - i rem pow2(g_nof_unfolds) - 1)
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => dp_pipeline_snk_in_arr(i),
- src_out => dp_block_gen_snk_in_arr(i)
- );
+ generic map (
+ g_pipeline => 0 + (pow2(g_nof_unfolds) - i rem pow2(g_nof_unfolds) - 1)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_pipeline_snk_in_arr(i),
+ src_out => dp_block_gen_snk_in_arr(i)
+ );
end generate;
end generate;
@@ -207,20 +207,20 @@ begin
gen_ctrl : if g_output_block_size > 0 generate
gen_dp_block_gen : for i in 0 to c_nof_outputs - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_output_block_size,
- g_preserve_sync => true,
- g_preserve_bsn => true,
- g_preserve_channel => g_use_channel
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => dp_block_gen_snk_in_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_output_block_size,
+ g_preserve_sync => true,
+ g_preserve_bsn => true,
+ g_preserve_channel => g_use_channel
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_block_gen_snk_in_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -234,20 +234,20 @@ begin
gen_sync_bsn : if g_fwd_sync_bsn = true generate
gen_dp_fifo_info: for i in 0 to c_nof_outputs - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
@@ -255,9 +255,9 @@ begin
src_out_arr <= dp_block_gen_src_out_arr;
end generate;
- end generate;
+ end generate;
- end generate;
+ end generate;
-----------------------------------------------------------------------------
-- Wire output to input if g_nof_unfolds=0
diff --git a/libraries/base/dp/src/vhdl/dp_unframe.vhd b/libraries/base/dp/src/vhdl/dp_unframe.vhd
index 1164b21af8..51039cde2d 100644
--- a/libraries/base/dp/src/vhdl/dp_unframe.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unframe.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
-- Reuse from LOFAR rad_unframe.vhd and rad_unframe(rtl).vhd
@@ -74,10 +74,10 @@ entity dp_unframe is
out_err : out std_logic
);
begin
--- synthesis translate_off
+ -- synthesis translate_off
assert g_fsn_w <= g_dat_w
report "g_fsn_w must be smaller than or equal to g_dat_w"
- severity ERROR;
+ severity ERROR;
-- synthesis translate_on
end dp_unframe;
diff --git a/libraries/base/dp/src/vhdl/dp_validate.vhd b/libraries/base/dp/src/vhdl/dp_validate.vhd
index 7db309c9bf..b52e319f68 100644
--- a/libraries/base/dp/src/vhdl/dp_validate.vhd
+++ b/libraries/base/dp/src/vhdl/dp_validate.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Assert valid, sop and eop only when they are valid.
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
index ed719fde55..ed7d5a7a8b 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
@@ -48,10 +48,10 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_wideband_sp_arr_scope is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
index ac4ac46a7e..6c02653cca 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
@@ -41,9 +41,9 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_wideband_wb_arr_scope is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff.vhd b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
index c85d77fe4c..0df6465e3e 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
@@ -92,8 +92,8 @@
-- . Originally based on rad_frame_onoff from LOFAR RSP firmware
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_xonoff is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
index c64bf88f1b..4d97a8b6a8 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
@@ -33,9 +33,9 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_xonoff_reg is
generic (
@@ -60,11 +60,13 @@ end dp_xonoff_reg;
architecture str of dp_xonoff_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => g_default_value);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => g_default_value
+ );
signal mm_xonoff_reg : std_logic_vector(0 downto 0);
@@ -88,7 +90,7 @@ begin
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
- mm_xonoff_reg(0) <= sla_in.wrdata(0);
+ mm_xonoff_reg(0) <= sla_in.wrdata(0);
when others => null; -- not used MM addresses
end case;
@@ -109,16 +111,16 @@ begin
end process;
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_xonoff_reg,
+ in_dat => mm_xonoff_reg,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => xonoff_reg
- );
+ out_dat => xonoff_reg
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
index 1edae2143b..3ff79eb2e5 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
@@ -33,9 +33,9 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_xonoff_reg_timeout is
generic (
@@ -62,11 +62,13 @@ end dp_xonoff_reg_timeout;
architecture str of dp_xonoff_reg_timeout is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => g_default_value);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => g_default_value
+ );
constant c_mm_max_counter : natural := sel_a_b(g_sim, g_mm_timeout * 50, g_mm_timeout * (50 * 10**6)); -- @50MHz
@@ -106,8 +108,8 @@ begin
when 0 =>
mm_xonoff_reg(0) <= sla_in.wrdata(0);
if sla_in.wrdata(0) = '1' then
- cnt_clr <= '1';
- cnt_en <= '1';
+ cnt_clr <= '1';
+ cnt_en <= '1';
end if;
when others => null; -- not used MM addresses
@@ -131,28 +133,28 @@ begin
u_counter : entity common_lib.common_counter
- generic map (
- g_latency => 0
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => counter
- );
+ generic map (
+ g_latency => 0
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => counter
+ );
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_xonoff_reg_out,
+ in_dat => mm_xonoff_reg_out,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => xonoff_reg
- );
+ out_dat => xonoff_reg
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
index 5f5977b064..4f49fd19f7 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
@@ -35,11 +35,11 @@
-- https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+BSN+aligner+v2
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_align_v2 is
@@ -121,29 +121,29 @@ begin
-- MM control of BSN aligner
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => (others => '1') -- Default all g_nof_streams are enabled.
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_bsn_align_copi,
- sla_out => reg_bsn_align_cipo,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_wr, -- readback via ST clock domain
- in_reg => reg_rd
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => (others => '1') -- Default all g_nof_streams are enabled.
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_bsn_align_copi,
+ sla_out => reg_bsn_align_cipo,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_wr, -- readback via ST clock domain
+ in_reg => reg_rd
+ );
gen_reg : for I in 0 to g_nof_streams - 1 generate
stream_en_arr(I) <= sl(reg_wr(2 * I * c_word_w downto 2 * I * c_word_w));
@@ -161,58 +161,58 @@ begin
-- . all input streams (g_nof_input_bsn_monitors = g_nof_streams).
gen_bsn_mon_input : if g_nof_input_bsn_monitors > 0 generate
u_bsn_mon_input : entity work.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => g_nof_input_bsn_monitors,
- g_cross_clock_domain => true,
- g_sync_timeout => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_input_monitor_copi,
- reg_miso => reg_input_monitor_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr => in_sosi_arr(g_nof_input_bsn_monitors - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_input_bsn_monitors,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_input_monitor_copi,
+ reg_miso => reg_input_monitor_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr => in_sosi_arr(g_nof_input_bsn_monitors - 1 downto 0)
+ );
end generate;
gen_bsn_mon_output : if g_use_bsn_output_monitor generate
u_bsn_mon_output : entity work.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1, -- all outputs have same BSN monitor information
- g_cross_clock_domain => true,
- g_sync_timeout => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_output_monitor_copi,
- reg_miso => reg_output_monitor_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr => mon_out_sosi_arr
- );
+ generic map (
+ g_nof_streams => 1, -- all outputs have same BSN monitor information
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_output_monitor_copi,
+ reg_miso => reg_output_monitor_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr => mon_out_sosi_arr
+ );
end generate;
-- Use mm_sosi or out_sosi_arr(0) from BSN aligner for output BSN monitor
@@ -223,35 +223,35 @@ begin
out_sosi_arr <= i_out_sosi_arr;
u_bsn_align : entity work.dp_bsn_align_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_bsn_latency_max => g_bsn_latency_max,
- g_nof_aligners_max => g_nof_aligners_max,
- g_block_size => g_block_size,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_data_replacement_value => g_data_replacement_value,
- g_use_mm_output => g_use_mm_output,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_rd_latency => g_rd_latency
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- node_index => node_index,
- -- MM control
- stream_en_arr => stream_en_arr,
- stream_replaced_cnt_arr => stream_replaced_cnt_arr,
- -- Streaming input
- in_sosi_arr => in_sosi_arr,
- -- Output via local MM in dp_clk domain
- mm_sosi => i_mm_sosi,
- mm_copi => mm_copi,
- mm_cipo_arr => mm_cipo_arr,
- -- Output via streaming DP interface, when g_use_mm_output = TRUE.
- out_sosi_arr => i_out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_bsn_latency_max => g_bsn_latency_max,
+ g_nof_aligners_max => g_nof_aligners_max,
+ g_block_size => g_block_size,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_data_replacement_value => g_data_replacement_value,
+ g_use_mm_output => g_use_mm_output,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_rd_latency => g_rd_latency
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ node_index => node_index,
+ -- MM control
+ stream_en_arr => stream_en_arr,
+ stream_replaced_cnt_arr => stream_replaced_cnt_arr,
+ -- Streaming input
+ in_sosi_arr => in_sosi_arr,
+ -- Output via local MM in dp_clk domain
+ mm_sosi => i_mm_sosi,
+ mm_copi => mm_copi,
+ mm_cipo_arr => mm_cipo_arr,
+ -- Output via streaming DP interface, when g_use_mm_output = TRUE.
+ out_sosi_arr => i_out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 114045c44f..9d5706825f 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -55,10 +55,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_sync_scheduler is
@@ -131,23 +131,23 @@ begin
-- . Write
wr_ctrl_enable <= reg_wr( 0);
ctrl_interval_size <= TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) when
- g_ctrl_interval_size_min < TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) else g_ctrl_interval_size_min;
+ g_ctrl_interval_size_min < TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) else g_ctrl_interval_size_min;
wr_start_bsn_64( c_word_w - 1 downto 0) <= reg_wr( 3 * c_word_w - 1 downto 2 * c_word_w); -- low word
wr_start_bsn_64(2 * c_word_w - 1 downto 1 * c_word_w) <= reg_wr( 4 * c_word_w - 1 downto 3 * c_word_w); -- high word
-- Derive ctrl_enable_evt from change in wr_ctrl_enable, instead of using
-- reg_wr_arr(0), see description
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_sig => wr_ctrl_enable,
- out_evt => wr_ctrl_enable_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_sig => wr_ctrl_enable,
+ out_evt => wr_ctrl_enable_evt
+ );
ctrl_enable <= wr_ctrl_enable when rising_edge(dp_clk) and wr_ctrl_enable_evt = '1';
ctrl_enable_evt <= wr_ctrl_enable_evt when rising_edge(dp_clk);
@@ -167,58 +167,58 @@ begin
reg_rd(12 * c_word_w - 1 downto 11 * c_word_w) <= TO_UVEC(g_block_size, c_word_w);
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => OPEN,
- out_reg => reg_wr, -- readback via ST clock domain
- in_reg => reg_rd
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => OPEN,
+ out_reg => reg_wr, -- readback via ST clock domain
+ in_reg => reg_rd
+ );
u_dp_bsn_sync_scheduler : entity work.dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min,
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- M&C
- ctrl_enable => ctrl_enable,
- ctrl_enable_evt => ctrl_enable_evt,
- ctrl_interval_size => ctrl_interval_size,
- ctrl_start_bsn => ctrl_start_bsn,
- mon_current_input_bsn => mon_current_input_bsn,
- mon_input_bsn_at_sync => mon_input_bsn_at_sync,
- mon_output_enable => mon_output_enable,
- mon_output_interval_size => mon_output_interval_size,
- mon_output_sync_bsn => mon_output_sync_bsn,
-
- -- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_start_interval => out_start_interval,
- out_enable => out_enable
- );
+ generic map (
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min,
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- M&C
+ ctrl_enable => ctrl_enable,
+ ctrl_enable_evt => ctrl_enable_evt,
+ ctrl_interval_size => ctrl_interval_size,
+ ctrl_start_bsn => ctrl_start_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
+ mon_input_bsn_at_sync => mon_input_bsn_at_sync,
+ mon_output_enable => mon_output_enable,
+ mon_output_interval_size => mon_output_interval_size,
+ mon_output_sync_bsn => mon_output_sync_bsn,
+
+ -- Streaming
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_start_interval => out_start_interval,
+ out_enable => out_enable
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
index 571927de27..131424d6d1 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
@@ -25,10 +25,10 @@
-- Remarks: See mmp_dp_bsn_sync_scheduler.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_sync_scheduler_arr is
@@ -68,42 +68,42 @@ begin
-- dp_bsn_sync_scheduler
u_mmp_dp_bsn_sync_scheduler : entity work.mmp_dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
- in_sosi => in_sosi_arr(0),
- out_sosi => single_src_out,
+ in_sosi => in_sosi_arr(0),
+ out_sosi => single_src_out,
- out_start => out_start,
- out_start_interval => out_start_interval,
- out_enable => out_enable
- );
+ out_start => out_start,
+ out_start_interval => out_start_interval,
+ out_enable => out_enable
+ );
-- Pipeline in_sosi_arr to compensate for the latency in mmp_dp_bsn_sync_scheduler
u_dp_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_out_arr => in_sosi_arr_piped
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_out_arr => in_sosi_arr_piped
+ );
p_streams : process(in_sosi_arr_piped, single_src_out)
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
index 24912d4a41..7be6e1153e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
@@ -30,12 +30,12 @@
-- The index_lo and index_hi can be read and set via the MM interface.
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_block_select is
generic (
@@ -65,7 +65,7 @@ end mms_dp_block_select;
architecture str of mms_dp_block_select is
constant c_field_arr : t_common_field_arr(1 downto 0) := ( (field_name_pad("index_hi"), "RW", 32, field_default(g_index_hi) ),
- (field_name_pad("index_lo"), "RW", 32, field_default(g_index_lo) ));
+ (field_name_pad("index_lo"), "RW", 32, field_default(g_index_lo) ));
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -76,46 +76,46 @@ begin
-- Use same control for all streams
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
index_lo <= TO_UINT(mm_fields_out(field_hi(c_field_arr, "index_lo") downto field_lo(c_field_arr, "index_lo")));
index_hi <= TO_UINT(mm_fields_out(field_hi(c_field_arr, "index_hi") downto field_lo(c_field_arr, "index_hi")));
gen_dp_block_select : for I in 0 to g_nof_streams - 1 generate
u_dp_block_select : entity work.dp_block_select
- generic map (
- g_nof_blocks_per_sync => g_nof_blocks_per_sync,
- g_index_lo => g_index_lo,
- g_index_hi => g_index_hi
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Control
- index_lo => index_lo,
- index_hi => index_hi,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_nof_blocks_per_sync => g_nof_blocks_per_sync,
+ g_index_lo => g_index_lo,
+ g_index_hi => g_index_hi
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Control
+ index_lo => index_lo,
+ index_hi => index_hi,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
index 564443cdaa..cf32f9b71d 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : MMS for dp_bsn_aligner
-- Description: See dp_bsn_aligner.vhd
@@ -68,49 +68,49 @@ architecture str of mms_dp_bsn_align is
begin
u_align : entity work.dp_bsn_align
- generic map(
- g_block_size => g_block_size,
- g_block_period => g_block_period,
- g_nof_input => g_nof_input,
- g_xoff_timeout => g_xoff_timeout,
- g_sop_timeout => g_sop_timeout,
- g_bsn_latency => g_bsn_latency,
- g_bsn_request_pipeline => g_bsn_request_pipeline
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr,
- -- MM
- in_en_evt => en_evt,
- in_en_arr => en_arr
- );
+ generic map(
+ g_block_size => g_block_size,
+ g_block_period => g_block_period,
+ g_nof_input => g_nof_input,
+ g_xoff_timeout => g_xoff_timeout,
+ g_sop_timeout => g_sop_timeout,
+ g_bsn_latency => g_bsn_latency,
+ g_bsn_request_pipeline => g_bsn_request_pipeline
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ -- MM
+ in_en_evt => en_evt,
+ in_en_arr => en_arr
+ );
u_reg : entity work.dp_bsn_align_reg
- generic map (
- g_nof_input => g_nof_input,
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_nof_input => g_nof_input,
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- out_en_evt => en_evt,
- out_en_arr => en_arr
- );
+ -- MM registers in st_clk domain
+ out_en_evt => en_evt,
+ out_en_arr => en_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
index a9f4549ae4..d180e52ebd 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : MMS for dp_bsn_monitor
-- Description: See dp_bsn_monitor.vhd
@@ -85,83 +85,83 @@ architecture str of mms_dp_bsn_monitor is
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
-
- gen_stream : for i in 0 to g_nof_streams - 1 generate
-
- u_reg : entity work.dp_bsn_monitor_reg
generic map (
- g_cross_clock_domain => g_cross_clock_domain
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- mon_evt => mon_evt_arr(i),
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
-
- mon_bsn_first => mon_bsn_first_arr(i),
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
);
+ gen_stream : for i in 0 to g_nof_streams - 1 generate
+
+ u_reg : entity work.dp_bsn_monitor_reg
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ mon_evt => mon_evt_arr(i),
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+
+ mon_bsn_first => mon_bsn_first_arr(i),
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ );
+
u_mon : entity work.dp_bsn_monitor
- generic map (
- g_sync_timeout => g_sync_timeout,
- g_error_bi => g_error_bi,
- g_log_first_bsn => g_log_first_bsn
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- ST interface
- in_siso => in_siso_arr(i),
- in_sosi => in_sosi_arr(i),
- sync_in => sync_in,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
- mon_sync => OPEN,
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
-
- mon_bsn_first => mon_bsn_first_arr(i),
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
- );
+ generic map (
+ g_sync_timeout => g_sync_timeout,
+ g_error_bi => g_error_bi,
+ g_log_first_bsn => g_log_first_bsn
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- ST interface
+ in_siso => in_siso_arr(i),
+ in_sosi => in_sosi_arr(i),
+ sync_in => sync_in,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
+ mon_sync => OPEN,
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+
+ mon_bsn_first => mon_bsn_first_arr(i),
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ );
end generate;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
index d99687e507..61b4951577 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
@@ -24,12 +24,12 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_components_pkg.all;
entity mms_dp_bsn_monitor_v2 is
generic (
@@ -87,78 +87,78 @@ architecture str of mms_dp_bsn_monitor_v2 is
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
-
- gen_stream : for i in 0 to g_nof_streams - 1 generate
-
- u_reg : entity work.dp_bsn_monitor_reg_v2
generic map (
- g_cross_clock_domain => g_cross_clock_domain
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- mon_evt => mon_evt_arr(i),
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
- mon_latency => mon_latency_arr(i)
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
);
+ gen_stream : for i in 0 to g_nof_streams - 1 generate
+
+ u_reg : entity work.dp_bsn_monitor_reg_v2
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ mon_evt => mon_evt_arr(i),
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+ mon_latency => mon_latency_arr(i)
+ );
+
u_mon : entity work.dp_bsn_monitor_v2
- generic map (
- g_sync_timeout => g_sync_timeout,
- g_error_bi => g_error_bi
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- ST interface
- in_siso => in_siso_arr(i),
- in_sosi => in_sosi_arr(i),
- ref_sync => ref_sync,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
- mon_sync => OPEN,
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
- mon_latency => mon_latency_arr(i)
- );
+ generic map (
+ g_sync_timeout => g_sync_timeout,
+ g_error_bi => g_error_bi
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- ST interface
+ in_siso => in_siso_arr(i),
+ in_sosi => in_sosi_arr(i),
+ ref_sync => ref_sync,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
+ mon_sync => OPEN,
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+ mon_latency => mon_latency_arr(i)
+ );
end generate;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
index 5a78c9c27b..8d4428a775 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : MMS for dp_bsn_scheduler
-- Description: See dp_bsn_scheduler.vhd
@@ -59,38 +59,38 @@ architecture str of mms_dp_bsn_scheduler is
begin
u_mm_reg : entity work.dp_bsn_scheduler_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in dp_clk domain
- st_current_bsn => snk_in.bsn,
- st_scheduled_bsn => scheduled_bsn
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in dp_clk domain
+ st_current_bsn => snk_in.bsn,
+ st_scheduled_bsn => scheduled_bsn
+ );
u_bsn_scheduler : entity work.dp_bsn_scheduler
- generic map (
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- scheduled_bsn => scheduled_bsn,
- -- Streaming
- snk_in => snk_in,
- trigger_out => trigger_out
- );
+ generic map (
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ scheduled_bsn => scheduled_bsn,
+ -- Streaming
+ snk_in => snk_in,
+ trigger_out => trigger_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
index 7cbfb893d1..0833d42ec4 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
@@ -23,10 +23,10 @@
-- Description: See dp_bsn_source.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_bsn_source is
@@ -72,49 +72,49 @@ begin
bs_sosi <= i_bs_sosi;
u_mm_reg : entity work.dp_bsn_source_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_block_per_sync => g_nof_block_per_sync
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- st_on => dp_on,
- st_on_pps => dp_on_pps,
- st_on_status => dp_on_status,
- st_nof_block_per_sync => nof_block_per_sync,
- st_init_bsn => init_bsn,
- st_current_bsn => capture_bsn
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_block_per_sync => g_nof_block_per_sync
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ st_on => dp_on,
+ st_on_pps => dp_on_pps,
+ st_on_status => dp_on_status,
+ st_nof_block_per_sync => nof_block_per_sync,
+ st_init_bsn => init_bsn,
+ st_current_bsn => capture_bsn
+ );
u_bsn_source : entity work.dp_bsn_source
- generic map (
- g_block_size => g_block_size,
- g_nof_block_per_sync => g_nof_block_per_sync,
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- pps => dp_pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status,
- init_bsn => init_bsn,
- nof_block_per_sync => nof_block_per_sync,
- -- Streaming
- src_out => i_bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_block_per_sync => g_nof_block_per_sync,
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ pps => dp_pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ dp_on_status => dp_on_status,
+ init_bsn => init_bsn,
+ nof_block_per_sync => nof_block_per_sync,
+ -- Streaming
+ src_out => i_bs_sosi
+ );
--capture_bsn <= i_bs_sosi.bsn; -- capture current BSN
--capture_bsn <= i_bs_sosi.bsn WHEN rising_edge(dp_clk) AND dp_pps='1'; -- capture BSN at external PPS
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 8aab344a1d..f0d7266ed8 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -23,10 +23,10 @@
-- Description: See dp_bsn_source.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_bsn_source_v2 is
@@ -79,53 +79,53 @@ begin
bs_nof_clk_per_sync <= nof_clk_per_sync;
u_mm_reg : entity work.dp_bsn_source_reg_v2
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_clk_per_sync => g_nof_clk_per_sync
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- st_on => dp_on,
- st_on_pps => dp_on_pps,
- st_on_status => dp_on_status,
- st_nof_clk_per_sync => nof_clk_per_sync,
- st_bsn_init => bsn_init,
- st_current_bsn => capture_bsn,
- st_bsn_time_offset => bsn_time_offset
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_clk_per_sync => g_nof_clk_per_sync
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ st_on => dp_on,
+ st_on_pps => dp_on_pps,
+ st_on_status => dp_on_status,
+ st_nof_clk_per_sync => nof_clk_per_sync,
+ st_bsn_init => bsn_init,
+ st_current_bsn => capture_bsn,
+ st_bsn_time_offset => bsn_time_offset
+ );
u_bsn_source : entity work.dp_bsn_source_v2
- generic map (
- g_block_size => g_block_size,
- g_nof_clk_per_sync => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- pps => dp_pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status,
- bs_restart => bs_restart,
- bs_new_interval => bs_new_interval,
- bsn_init => bsn_init,
- nof_clk_per_sync => nof_clk_per_sync,
- bsn_time_offset => bsn_time_offset,
- -- Streaming
- src_out => i_bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_clk_per_sync => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ pps => dp_pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ dp_on_status => dp_on_status,
+ bs_restart => bs_restart,
+ bs_new_interval => bs_new_interval,
+ bsn_init => bsn_init,
+ nof_clk_per_sync => nof_clk_per_sync,
+ bsn_time_offset => bsn_time_offset,
+ -- Streaming
+ src_out => i_bs_sosi
+ );
capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
index a038a376b6..7af1d8630d 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
@@ -27,12 +27,12 @@
-- Remarks:
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_fifo_fill is
generic (
@@ -67,9 +67,9 @@ entity mms_dp_fifo_fill is
dp_clk : in std_logic;
-- Monitor FIFO filling
--- wr_ful : OUT STD_LOGIC;
--- usedw : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
--- rd_emp : OUT STD_LOGIC;
+ -- wr_ful : OUT STD_LOGIC;
+ -- usedw : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- rd_emp : OUT STD_LOGIC;
-- ST sink
snk_out_arr : out t_dp_siso_arr(g_nof_streams - 1 downto 0);
@@ -93,60 +93,60 @@ begin
gen_fifos : for I in 0 to g_nof_streams - 1 generate
dp_fifo_sc : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful_reg(I),
- usedw => fifo_usedw_reg(I * c_word_w + c_usedw_w - 1 downto I * c_word_w),
- rd_emp => rd_emp_reg(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful_reg(I),
+ usedw => fifo_usedw_reg(I * c_word_w + c_usedw_w - 1 downto I * c_word_w),
+ rd_emp => rd_emp_reg(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
u_reg : entity work.dp_fifo_fill_reg
- generic map(
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- used_w => fifo_usedw_reg,
- rd_emp => rd_emp_reg,
- wr_ful => wr_ful_reg
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ used_w => fifo_usedw_reg,
+ rd_emp => rd_emp_reg,
+ wr_ful => wr_ful_reg
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
index 45027c7c90..69bd51c931 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_fifo_from_mm is
generic (
@@ -58,33 +58,33 @@ architecture str of mms_dp_fifo_from_mm is
begin
u_dp_fifo_from_mm : entity dp_lib.dp_fifo_from_mm
- generic map(
- g_fifo_size => g_wr_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- src_out => wr_sosi,
- usedw => wr_usedw, -- used words from rd FIFO
-
- mm_wr => mm_wr,
- mm_wrdata => mm_wr_data,
- mm_usedw => mm_wr_usedw, -- resized to 32 bits
- mm_availw => mm_wr_availw -- resized to 32 bits
- );
+ generic map(
+ g_fifo_size => g_wr_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ src_out => wr_sosi,
+ usedw => wr_usedw, -- used words from rd FIFO
+
+ mm_wr => mm_wr,
+ mm_wrdata => mm_wr_data,
+ mm_usedw => mm_wr_usedw, -- resized to 32 bits
+ mm_availw => mm_wr_availw -- resized to 32 bits
+ );
u_dp_fifo_from_mm_reg: entity work.dp_fifo_from_mm_reg
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
- mm_wr_usedw => mm_wr_usedw,
- mm_wr_availw => mm_wr_availw
- );
+ mm_wr_usedw => mm_wr_usedw,
+ mm_wr_availw => mm_wr_availw
+ );
mm_wr_data <= data_mosi.wrdata(c_word_w - 1 downto 0);
mm_wr <= data_mosi.wr;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
index 7d5c3baf6a..47b15c6a2a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_fifo_to_mm is
generic (
@@ -60,33 +60,33 @@ architecture str of mms_dp_fifo_to_mm is
begin
u_dp_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => g_rd_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- snk_out => rd_siso,
- snk_in => rd_sosi,
- usedw => rd_usedw, -- used words from rd FIFO
-
- mm_rd => mm_rd,
- mm_rddata => mm_rd_data,
- mm_rdval => mm_rd_val,
- mm_usedw => mm_rd_usedw -- resized to 32 bits
- );
+ generic map(
+ g_fifo_size => g_rd_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ usedw => rd_usedw, -- used words from rd FIFO
+
+ mm_rd => mm_rd,
+ mm_rddata => mm_rd_data,
+ mm_rdval => mm_rd_val,
+ mm_usedw => mm_rd_usedw -- resized to 32 bits
+ );
u_dp_fifo_to_mm_reg: entity work.dp_fifo_to_mm_reg
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
- mm_rd_usedw => mm_rd_usedw
- );
+ mm_rd_usedw => mm_rd_usedw
+ );
data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
data_miso.rdval <= mm_rd_val;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
index 271f59d2e7..e1a8554616 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
@@ -33,10 +33,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_parallel is
@@ -106,60 +106,60 @@ begin
reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto 3 * c_mm_reg.dat_w) <= reg_force_data_wr(4 * c_mm_reg.dat_w - 1 downto 3 * c_mm_reg.dat_w);
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_force_data_mosi,
- sla_out => reg_force_data_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_force_data_mosi,
+ sla_out => reg_force_data_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_force_data_wr, -- readback via ST clock domain
- in_reg => reg_force_data_rd
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_force_data_wr, -- readback via ST clock domain
+ in_reg => reg_force_data_rd
+ );
u_dp_force_data_parallel : entity work.dp_force_data_parallel
- generic map (
- g_dat_w => g_dat_w,
- g_increment_data => g_increment_data,
- g_increment_re => g_increment_re,
- g_increment_im => g_increment_im,
- g_increment_data_on_sop => g_increment_data_on_sop,
- g_increment_re_on_sop => g_increment_re_on_sop,
- g_increment_im_on_sop => g_increment_im_on_sop,
- g_restart_data_on_sync => g_restart_data_on_sync,
- g_restart_re_on_sync => g_restart_re_on_sync,
- g_restart_im_on_sync => g_restart_im_on_sync,
- g_restart_data_on_sop => g_restart_data_on_sop,
- g_restart_re_on_sop => g_restart_re_on_sop,
- g_restart_im_on_sop => g_restart_im_on_sop
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- force_en => force_en,
- force_data => force_data,
- force_re => force_re,
- force_im => force_im,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_dat_w => g_dat_w,
+ g_increment_data => g_increment_data,
+ g_increment_re => g_increment_re,
+ g_increment_im => g_increment_im,
+ g_increment_data_on_sop => g_increment_data_on_sop,
+ g_increment_re_on_sop => g_increment_re_on_sop,
+ g_increment_im_on_sop => g_increment_im_on_sop,
+ g_restart_data_on_sync => g_restart_data_on_sync,
+ g_restart_re_on_sync => g_restart_re_on_sync,
+ g_restart_im_on_sync => g_restart_im_on_sync,
+ g_restart_data_on_sop => g_restart_data_on_sop,
+ g_restart_re_on_sop => g_restart_re_on_sop,
+ g_restart_im_on_sop => g_restart_im_on_sop
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ force_en => force_en,
+ force_data => force_data,
+ force_re => force_re,
+ force_im => force_im,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
index 04a13556ca..99d7b81a1a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
@@ -34,10 +34,10 @@
-- etc.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_parallel_arr is
@@ -86,49 +86,49 @@ architecture str of mms_dp_force_data_parallel_arr is
begin
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg_adr_w
- )
- port map (
- mosi => reg_force_data_mosi,
- miso => reg_force_data_miso,
- mosi_arr => reg_force_data_mosi_arr,
- miso_arr => reg_force_data_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- u_mms_dp_force_data_parallel : entity work.mms_dp_force_data_parallel
generic map (
- g_dat_w => g_dat_w,
- g_increment_data => g_increment_data,
- g_increment_re => g_increment_re,
- g_increment_im => g_increment_im,
- g_increment_data_on_sop => g_increment_data_on_sop,
- g_increment_re_on_sop => g_increment_re_on_sop,
- g_increment_im_on_sop => g_increment_im_on_sop,
- g_restart_data_on_sync => g_restart_data_on_sync,
- g_restart_re_on_sync => g_restart_re_on_sync,
- g_restart_im_on_sync => g_restart_im_on_sync,
- g_restart_data_on_sop => g_restart_data_on_sop,
- g_restart_re_on_sop => g_restart_re_on_sop,
- g_restart_im_on_sop => g_restart_im_on_sop
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg_adr_w
)
port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi_arr(I),
- reg_force_data_miso => reg_force_data_miso_arr(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ mosi => reg_force_data_mosi,
+ miso => reg_force_data_miso,
+ mosi_arr => reg_force_data_mosi_arr,
+ miso_arr => reg_force_data_miso_arr
);
+
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ u_mms_dp_force_data_parallel : entity work.mms_dp_force_data_parallel
+ generic map (
+ g_dat_w => g_dat_w,
+ g_increment_data => g_increment_data,
+ g_increment_re => g_increment_re,
+ g_increment_im => g_increment_im,
+ g_increment_data_on_sop => g_increment_data_on_sop,
+ g_increment_re_on_sop => g_increment_re_on_sop,
+ g_increment_im_on_sop => g_increment_im_on_sop,
+ g_restart_data_on_sync => g_restart_data_on_sync,
+ g_restart_re_on_sync => g_restart_re_on_sync,
+ g_restart_im_on_sync => g_restart_im_on_sync,
+ g_restart_data_on_sop => g_restart_data_on_sop,
+ g_restart_re_on_sop => g_restart_re_on_sop,
+ g_restart_im_on_sop => g_restart_im_on_sop
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi_arr(I),
+ reg_force_data_miso => reg_force_data_miso_arr(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
index 3f19c86b90..c687e45ba4 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
@@ -37,10 +37,10 @@
-- See description of dp_force_data_serial.vhd.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_serial is
@@ -111,64 +111,64 @@ begin
-- read unused bits as '0' to save logic
reg_force_data_rd(1 * c_mm_reg.dat_w - 1 downto 2 + 0 * c_mm_reg.dat_w) <= (others => '0');
if c_index_w < c_mm_reg.dat_w then
- reg_force_data_rd(2 * c_mm_reg.dat_w - 1 downto c_index_w + 1 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(2 * c_mm_reg.dat_w - 1 downto c_index_w + 1 * c_mm_reg.dat_w) <= (others => '0');
end if;
if g_dat_w < c_mm_reg.dat_w then
- reg_force_data_rd(3 * c_mm_reg.dat_w - 1 downto g_dat_w + 2 * c_mm_reg.dat_w) <= (others => '0');
- reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto g_dat_w + 3 * c_mm_reg.dat_w) <= (others => '0');
- reg_force_data_rd(5 * c_mm_reg.dat_w - 1 downto g_dat_w + 4 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(3 * c_mm_reg.dat_w - 1 downto g_dat_w + 2 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto g_dat_w + 3 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(5 * c_mm_reg.dat_w - 1 downto g_dat_w + 4 * c_mm_reg.dat_w) <= (others => '0');
end if;
end process;
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_force_data_mosi,
- sla_out => reg_force_data_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_force_data_wr, -- readback via ST clock domain
- in_reg => reg_force_data_rd
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_force_data_mosi,
+ sla_out => reg_force_data_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_force_data_wr, -- readback via ST clock domain
+ in_reg => reg_force_data_rd
+ );
u_dp_force_data_serial : entity work.dp_force_data_serial
- generic map (
- g_dat_w => g_dat_w,
- g_index_period => g_index_period,
- g_index_sample_block_n => g_index_sample_block_n
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- force_en => force_en,
- force_value => force_value,
- force_zero_n => force_zero_n,
- force_data => force_data ,
- force_re => force_re,
- force_im => force_im,
- force_index => force_index,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_dat_w => g_dat_w,
+ g_index_period => g_index_period,
+ g_index_sample_block_n => g_index_sample_block_n
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ force_en => force_en,
+ force_value => force_value,
+ force_zero_n => force_zero_n,
+ force_data => force_data ,
+ force_re => force_re,
+ force_im => force_im,
+ force_index => force_index,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
index a999fcdc8d..6e82fa3846 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
@@ -34,10 +34,10 @@
-- See description of mms_dp_force_data_serial.vhd.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_serial_arr is
@@ -76,40 +76,40 @@ architecture str of mms_dp_force_data_serial_arr is
begin
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg_adr_w
- )
- port map (
- mosi => reg_force_data_mosi,
- miso => reg_force_data_miso,
- mosi_arr => reg_force_data_mosi_arr,
- miso_arr => reg_force_data_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- u_mms_dp_force_data_serial : entity work.mms_dp_force_data_serial
generic map (
- g_dat_w => g_dat_w,
- g_index_period => g_index_period,
- g_index_sample_block_n => g_index_sample_block_n
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi_arr(I),
- reg_force_data_miso => reg_force_data_miso_arr(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ mosi => reg_force_data_mosi,
+ miso => reg_force_data_miso,
+ mosi_arr => reg_force_data_mosi_arr,
+ miso_arr => reg_force_data_miso_arr
);
+
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ u_mms_dp_force_data_serial : entity work.mms_dp_force_data_serial
+ generic map (
+ g_dat_w => g_dat_w,
+ g_index_period => g_index_period,
+ g_index_sample_block_n => g_index_sample_block_n
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi_arr(I),
+ reg_force_data_miso => reg_force_data_miso_arr(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
index fe0950141c..0ec8f8223f 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
@@ -27,11 +27,11 @@
-- . See tb_mms_dp_gain_arr which also tests this mms_dp_gain
library IEEE, common_lib, common_mult_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain is
@@ -90,47 +90,47 @@ begin
out_sosi <= out_sosi_arr(0);
u_one : entity work.mms_dp_gain_arr
- generic map (
- g_technology => g_technology,
- -- functional
- g_nof_streams => 1,
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_init_re => g_gain_init_re,
- g_gain_init_im => g_gain_init_im,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- -- pipelining (typically use defaults)
- -- . real multiplier
- g_pipeline_real_mult_input => g_pipeline_real_mult_input,
- g_pipeline_real_mult_product => g_pipeline_real_mult_product,
- g_pipeline_real_mult_output => g_pipeline_real_mult_output,
- -- . complex multiplier
- g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
- g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
- g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
- g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM access to gain
- reg_gain_re_mosi => reg_gain_re_mosi,
- reg_gain_re_miso => reg_gain_re_miso,
- reg_gain_im_mosi => reg_gain_im_mosi,
- reg_gain_im_miso => reg_gain_im_miso,
-
- reg_gain_re => reg_gain_re,
- reg_gain_im => reg_gain_im,
- -- ST
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_technology => g_technology,
+ -- functional
+ g_nof_streams => 1,
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_init_re => g_gain_init_re,
+ g_gain_init_im => g_gain_init_im,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ -- pipelining (typically use defaults)
+ -- . real multiplier
+ g_pipeline_real_mult_input => g_pipeline_real_mult_input,
+ g_pipeline_real_mult_product => g_pipeline_real_mult_product,
+ g_pipeline_real_mult_output => g_pipeline_real_mult_output,
+ -- . complex multiplier
+ g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
+ g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
+ g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM access to gain
+ reg_gain_re_mosi => reg_gain_re_mosi,
+ reg_gain_re_miso => reg_gain_re_miso,
+ reg_gain_im_mosi => reg_gain_im_mosi,
+ reg_gain_im_miso => reg_gain_im_miso,
+
+ reg_gain_re => reg_gain_re,
+ reg_gain_im => reg_gain_im,
+ -- ST
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
index f338e6da00..795db6ec95 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
@@ -52,11 +52,11 @@
-- . A dp_pipeline is used to pass through the dp_control_fields.
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain_arr is
@@ -138,65 +138,65 @@ begin
reg_gain_im <= i_reg_gain_im;
u_common_reg_r_w_dc_re : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init_re
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_gain_re_mosi,
- sla_out => reg_gain_re_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => i_reg_gain_re,
- out_reg => i_reg_gain_re -- readback via ST clock domain
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init_re
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_gain_re_mosi,
+ sla_out => reg_gain_re_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => i_reg_gain_re,
+ out_reg => i_reg_gain_re -- readback via ST clock domain
+ );
gen_real_multiply : if c_real_multiply = true generate
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_common_mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_nof_mult => 1,
- g_pipeline_input => g_pipeline_real_mult_input,
- g_pipeline_product => g_pipeline_real_mult_product,
- g_pipeline_output => g_pipeline_real_mult_output,
- g_representation => "SIGNED" -- or "UNSIGNED"
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_a => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_b => in_sosi_arr(I).data(g_in_dat_w - 1 downto 0),
- in_val => in_sosi_arr(I).valid,
- out_p => mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0),
- out_val => mult_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_nof_mult => 1,
+ g_pipeline_input => g_pipeline_real_mult_input,
+ g_pipeline_product => g_pipeline_real_mult_product,
+ g_pipeline_output => g_pipeline_real_mult_output,
+ g_representation => "SIGNED" -- or "UNSIGNED"
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_a => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_b => in_sosi_arr(I).data(g_in_dat_w - 1 downto 0),
+ in_val => in_sosi_arr(I).valid,
+ out_p => mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0),
+ out_val => mult_sosi_arr(I).valid
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_real_multiply_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(I),
- src_out => pipelined_in_sosi_arr(I)
- );
+ generic map (
+ g_pipeline => c_real_multiply_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(I),
+ src_out => pipelined_in_sosi_arr(I)
+ );
p_out_sosi_arr : process(mult_sosi_arr, pipelined_in_sosi_arr)
begin
@@ -211,69 +211,69 @@ begin
gen_complex_multiply : if c_real_multiply = false generate
gen_complex_gain : if g_complex_gain = true generate
u_common_reg_r_w_dc_im : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init_im
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_gain_im_mosi,
- sla_out => reg_gain_im_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => i_reg_gain_im,
- out_reg => i_reg_gain_im -- readback via ST clock domain
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init_im
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_gain_im_mosi,
+ sla_out => reg_gain_im_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => i_reg_gain_im,
+ out_reg => i_reg_gain_im -- readback via ST clock domain
+ );
end generate gen_complex_gain;
-- ELSE: if g_complex_gain=FALSE then use default i_reg_gain_im, which is then typically g_gain_init_im=0 for all streams.
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_conjugate_b => false,
- g_pipeline_input => g_pipeline_complex_mult_input,
- g_pipeline_product => g_pipeline_complex_mult_product,
- g_pipeline_adder => g_pipeline_complex_mult_adder,
- g_pipeline_output => g_pipeline_complex_mult_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_ar => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_ai => i_reg_gain_im((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_br => in_sosi_arr(I).re(g_in_dat_w - 1 downto 0),
- in_bi => in_sosi_arr(I).im(g_in_dat_w - 1 downto 0),
- in_val => in_sosi_arr(I).valid, -- only propagate valid, not used internally
- out_pr => mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0),
- out_pi => mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0),
- out_val => mult_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_conjugate_b => false,
+ g_pipeline_input => g_pipeline_complex_mult_input,
+ g_pipeline_product => g_pipeline_complex_mult_product,
+ g_pipeline_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_ar => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_ai => i_reg_gain_im((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_br => in_sosi_arr(I).re(g_in_dat_w - 1 downto 0),
+ in_bi => in_sosi_arr(I).im(g_in_dat_w - 1 downto 0),
+ in_val => in_sosi_arr(I).valid, -- only propagate valid, not used internally
+ out_pr => mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0),
+ out_pi => mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0),
+ out_val => mult_sosi_arr(I).valid
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_complex_multiply_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(I),
- src_out => pipelined_in_sosi_arr(I)
- );
+ generic map (
+ g_pipeline => c_complex_multiply_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(I),
+ src_out => pipelined_in_sosi_arr(I)
+ );
p_out_sosi_arr : process(mult_sosi_arr, pipelined_in_sosi_arr)
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
index 3992244b9a..14c8010b62 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
@@ -27,11 +27,11 @@
-- . See tb_mms_dp_gain_serial_arr which also tests this mms_dp_gain_serial
library IEEE, common_lib, common_mult_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain_serial is
@@ -88,46 +88,46 @@ begin
out_sosi <= out_sosi_arr(0);
u_one : entity work.mms_dp_gain_serial_arr
- generic map (
- g_technology => g_technology,
- g_nof_streams => 1,
- g_nof_gains => g_nof_gains,
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_gains_file_name => g_gains_file_name,
- g_gains_write_only => g_gains_write_only,
-
- -- pipelining (typically use defaults)
- -- . real multiplier
- g_pipeline_real_mult_input => g_pipeline_real_mult_input,
- g_pipeline_real_mult_product => g_pipeline_real_mult_product,
- g_pipeline_real_mult_output => g_pipeline_real_mult_output,
- -- . complex multiplier
- g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
- g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
- g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
- g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => 1,
+ g_nof_gains => g_nof_gains,
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_gains_file_name => g_gains_file_name,
+ g_gains_write_only => g_gains_write_only,
+
+ -- pipelining (typically use defaults)
+ -- . real multiplier
+ g_pipeline_real_mult_input => g_pipeline_real_mult_input,
+ g_pipeline_real_mult_product => g_pipeline_real_mult_product,
+ g_pipeline_real_mult_output => g_pipeline_real_mult_output,
+ -- . complex multiplier
+ g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
+ g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
+ g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address,
+
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index c3fc8bfb18..a4f5b1e91a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -40,13 +40,13 @@
-- choose the correct avs_common_mm_readlatency2 when creating the qsys system.
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib, technology_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_gain_serial_arr is
generic (
@@ -102,22 +102,24 @@ architecture str of mms_dp_gain_serial_arr is
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
- constant c_mm_ram : t_c_mem := (latency => 2, -- set latency to 2 to ease timing
- adr_w => ceil_log2(g_nof_gains),
- dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
- nof_dat => g_nof_gains,
- init_sl => '0');
+ constant c_mm_ram : t_c_mem := (
+ latency => 2, -- set latency to 2 to ease timing
+ adr_w => ceil_log2(g_nof_gains),
+ dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
+ nof_dat => g_nof_gains,
+ init_sl => '0'
+ );
constant c_pipeline_real_latency : natural := g_pipeline_real_mult_input
- + g_pipeline_real_mult_product
- + g_pipeline_real_mult_output
- + c_mm_ram.latency;
+ + g_pipeline_real_mult_product
+ + g_pipeline_real_mult_output
+ + c_mm_ram.latency;
constant c_pipeline_complex_latency : natural := g_pipeline_complex_mult_input
- + g_pipeline_complex_mult_product
- + g_pipeline_complex_mult_adder
- + g_pipeline_complex_mult_output
- + c_mm_ram.latency;
+ + g_pipeline_complex_mult_product
+ + g_pipeline_complex_mult_adder
+ + g_pipeline_complex_mult_output
+ + c_mm_ram.latency;
constant c_pipeline_latency : natural := sel_a_b(c_real_multiply, c_pipeline_real_latency, c_pipeline_complex_latency);
@@ -147,72 +149,72 @@ begin
-- pipeline in_sosi_arr to align it with gains_rd_data_arr
u_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_mm_ram.latency -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => in_sosi_arr,
- src_out_arr => in_sosi_arr_pipe
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_mm_ram.latency -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => in_sosi_arr,
+ src_out_arr => in_sosi_arr_pipe
+ );
-- pipeline in_sosi_arr to add sop, eop and sync back in out_sosi_arr
u_pipeline_arr_ctrl : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_pipeline_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => in_sosi_arr,
- src_out_arr => in_sosi_arr_pipe_ctrl
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_pipeline_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => in_sosi_arr,
+ src_out_arr => in_sosi_arr_pipe_ctrl
+ );
u_mem_mux_gains : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(g_nof_gains)
- )
- port map (
- mosi => ram_gains_mosi,
- miso => ram_gains_miso,
- mosi_arr => mm_gains_mosi_arr,
- miso_arr => mm_gains_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- -- Instantiate a gains memory for each input stream:
- u_common_ram_crw_crw : entity common_lib.common_ram_crw_crw
generic map (
- g_technology => g_technology,
- g_ram => c_mm_ram,
- g_init_file => sel_a_b(g_gains_file_name = "UNUSED", g_gains_file_name, g_gains_file_name & "_" & natural'image(I) & ".hex"),
- g_true_dual_port => not(g_gains_write_only)
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(g_nof_gains)
)
port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => mm_gains_mosi_arr(I).wr,
- wr_dat_a => mm_gains_mosi_arr(I).wrdata(c_mm_ram.dat_w - 1 downto 0),
- adr_a => mm_gains_mosi_arr(I).address(c_mm_ram.adr_w - 1 downto 0),
- rd_en_a => mm_gains_mosi_arr(I).rd,
- rd_dat_a => mm_gains_miso_arr(I).rddata(c_mm_ram.dat_w - 1 downto 0),
- rd_val_a => mm_gains_miso_arr(I).rdval,
- -- ST side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => gains_rd_address,
- rd_en_b => '1',
- rd_dat_b => gains_rd_data_arr(I)(c_mm_ram.dat_w - 1 downto 0),
- rd_val_b => open
+ mosi => ram_gains_mosi,
+ miso => ram_gains_miso,
+ mosi_arr => mm_gains_mosi_arr,
+ miso_arr => mm_gains_miso_arr
);
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ -- Instantiate a gains memory for each input stream:
+ u_common_ram_crw_crw : entity common_lib.common_ram_crw_crw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_ram,
+ g_init_file => sel_a_b(g_gains_file_name = "UNUSED", g_gains_file_name, g_gains_file_name & "_" & natural'image(I) & ".hex"),
+ g_true_dual_port => not(g_gains_write_only)
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => mm_gains_mosi_arr(I).wr,
+ wr_dat_a => mm_gains_mosi_arr(I).wrdata(c_mm_ram.dat_w - 1 downto 0),
+ adr_a => mm_gains_mosi_arr(I).address(c_mm_ram.adr_w - 1 downto 0),
+ rd_en_a => mm_gains_mosi_arr(I).rd,
+ rd_dat_a => mm_gains_miso_arr(I).rddata(c_mm_ram.dat_w - 1 downto 0),
+ rd_val_a => mm_gains_miso_arr(I).rdval,
+ -- ST side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => gains_rd_address,
+ rd_en_b => '1',
+ rd_dat_b => gains_rd_data_arr(I)(c_mm_ram.dat_w - 1 downto 0),
+ rd_val_b => open
+ );
+
gen_real_multiply : if c_real_multiply = true generate
gains_re_arr(I) <= gains_rd_data_arr(I)(g_gain_w - 1 downto 0);
@@ -220,27 +222,27 @@ begin
in_val_arr(I) <= in_sosi_arr_pipe(I).valid;
u_common_mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_nof_mult => 1,
- g_pipeline_input => g_pipeline_real_mult_input,
- g_pipeline_product => g_pipeline_real_mult_product,
- g_pipeline_output => g_pipeline_real_mult_output,
- g_representation => "SIGNED" -- or "UNSIGNED"
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_a => gains_re_arr(I),
- in_b => in_dat_re_arr(I),
- in_val => in_val_arr(I),
- out_p => out_dat_re_arr(I),
- out_val => out_val_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_nof_mult => 1,
+ g_pipeline_input => g_pipeline_real_mult_input,
+ g_pipeline_product => g_pipeline_real_mult_product,
+ g_pipeline_output => g_pipeline_real_mult_output,
+ g_representation => "SIGNED" -- or "UNSIGNED"
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_a => gains_re_arr(I),
+ in_b => in_dat_re_arr(I),
+ in_val => in_val_arr(I),
+ out_p => out_dat_re_arr(I),
+ out_val => out_val_arr(I)
+ );
p_out_sosi_arr : process(out_val_arr, out_dat_re_arr, in_sosi_arr_pipe_ctrl)
begin
@@ -270,30 +272,30 @@ begin
in_val_arr(I) <= in_sosi_arr_pipe(I).valid;
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_conjugate_b => c_conjugate,
- g_pipeline_input => g_pipeline_complex_mult_input,
- g_pipeline_product => g_pipeline_complex_mult_product,
- g_pipeline_adder => g_pipeline_complex_mult_adder,
- g_pipeline_output => g_pipeline_complex_mult_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_ar => gains_re_arr(I),
- in_ai => gains_im_arr(I),
- in_br => in_dat_re_arr(I),
- in_bi => in_dat_im_arr(I),
- in_val => in_val_arr(I),
- out_pr => out_dat_re_arr(I),
- out_pi => out_dat_im_arr(I),
- out_val => out_val_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_conjugate_b => c_conjugate,
+ g_pipeline_input => g_pipeline_complex_mult_input,
+ g_pipeline_product => g_pipeline_complex_mult_product,
+ g_pipeline_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_ar => gains_re_arr(I),
+ in_ai => gains_im_arr(I),
+ in_br => in_dat_re_arr(I),
+ in_bi => in_dat_im_arr(I),
+ in_val => in_val_arr(I),
+ out_pr => out_dat_re_arr(I),
+ out_pi => out_dat_im_arr(I),
+ out_val => out_val_arr(I)
+ );
p_out_sosi_arr : process(out_val_arr, out_dat_re_arr, out_dat_im_arr, in_sosi_arr_pipe_ctrl)
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
index d498b85797..e27f4c0581 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
@@ -24,12 +24,12 @@
-- Remarks:
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_packet_merge is
generic (
@@ -74,51 +74,51 @@ architecture str of mms_dp_packet_merge is
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_stream : for i in 0 to g_nof_streams - 1 generate
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi_arr(i),
- mm_miso => reg_miso_arr(i),
+ mm_mosi => reg_mosi_arr(i),
+ mm_miso => reg_miso_arr(i),
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out_arr(i)
- );
+ slv_out => mm_fields_out_arr(i)
+ );
nof_pkt(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "nof_pkt") downto field_lo(c_field_arr, "nof_pkt"));
u_dp_merge : entity work.dp_packet_merge
- generic map (
- g_nof_pkt => g_nof_pkt
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- nof_pkt => nof_pkt(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_nof_pkt => g_nof_pkt
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ nof_pkt => nof_pkt(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
index fa15b23d32..4a2e25ac1e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_ram_from_mm is
generic (
@@ -50,47 +50,47 @@ end mms_dp_ram_from_mm;
architecture str of mms_dp_ram_from_mm is
- signal dp_on : std_logic;
+ signal dp_on : std_logic;
begin
- u_dp_ram_from_mm : entity dp_lib.dp_ram_from_mm
- generic map(
- g_ram_wr_nof_words => g_ram_wr_nof_words,
- g_ram_rd_dat_w => g_ram_rd_dat_w,
- g_init_file => g_init_file
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ u_dp_ram_from_mm : entity dp_lib.dp_ram_from_mm
+ generic map(
+ g_ram_wr_nof_words => g_ram_wr_nof_words,
+ g_ram_rd_dat_w => g_ram_rd_dat_w,
+ g_init_file => g_init_file
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- mm_addr => ram_mosi.address,
- mm_wr => ram_mosi.wr,
- mm_wrdata => ram_mosi.wrdata,
+ mm_addr => ram_mosi.address,
+ mm_wr => ram_mosi.wr,
+ mm_wrdata => ram_mosi.wrdata,
- dp_on => dp_on,
+ dp_on => dp_on,
- src_in => src_in,
- src_out => src_out
- );
+ src_in => src_in,
+ src_out => src_out
+ );
u_dp_ram_from_mm_reg: entity work.dp_ram_from_mm_reg
- generic map(
- g_dp_on_at_init => g_dp_on_at_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map(
+ g_dp_on_at_init => g_dp_on_at_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- sla_in => reg_mosi,
+ sla_in => reg_mosi,
- dp_on => dp_on
- );
+ dp_on => dp_on
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
index 75bf826fe2..ab191dc85e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
@@ -29,10 +29,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_scale is
generic (
@@ -51,7 +51,7 @@ entity mms_dp_scale is
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false -- when TRUE CLIP signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
);
port (
-- System
@@ -87,56 +87,56 @@ begin
-- Gain
---------------------------------------------------------------
u_mms_dp_gain : entity work.mms_dp_gain
- generic map (
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_init_re => g_gain_init_re,
- g_gain_init_im => g_gain_init_im,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_gain_out_dat_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_init_re => g_gain_init_re,
+ g_gain_init_im => g_gain_init_im,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_gain_out_dat_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM interface
- reg_gain_re_mosi => reg_gain_re_mosi,
- reg_gain_re_miso => reg_gain_re_miso,
- reg_gain_im_mosi => reg_gain_im_mosi,
- reg_gain_im_miso => reg_gain_im_miso,
+ -- MM interface
+ reg_gain_re_mosi => reg_gain_re_mosi,
+ reg_gain_re_miso => reg_gain_re_miso,
+ reg_gain_im_mosi => reg_gain_im_mosi,
+ reg_gain_im_miso => reg_gain_im_miso,
- reg_gain_re => reg_gain_re,
- reg_gain_im => reg_gain_im,
+ reg_gain_re => reg_gain_re,
+ reg_gain_im => reg_gain_im,
- in_sosi => in_sosi,
- out_sosi => dp_gain_out_sosi
- );
+ in_sosi => in_sosi,
+ out_sosi => dp_gain_out_sosi
+ );
---------------------------------------------------------------
-- Requantize
---------------------------------------------------------------
u_dp_requantize : entity work.dp_requantize
- generic map (
- g_complex => c_dp_requantize_complex,
- g_representation => "SIGNED",
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => dp_gain_out_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_complex => c_dp_requantize_complex,
+ g_representation => "SIGNED",
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => dp_gain_out_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_split.vhd b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
index a0d0915298..7e06454d81 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_split is
generic (
@@ -71,56 +71,56 @@ architecture str of mms_dp_split is
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_stream : for i in 0 to g_nof_streams - 1 generate
out_nof_symbols(i) <= TO_UINT(nof_symbols(i));
u_reg : entity work.dp_split_reg
- generic map (
- g_nof_symbols => g_nof_symbols_max
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- nof_symbols => nof_symbols(i)
- );
+ generic map (
+ g_nof_symbols => g_nof_symbols_max
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ nof_symbols => nof_symbols(i)
+ );
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => g_nof_symbols_max
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- nof_symbols => nof_symbols(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
- src_in_arr => src_in_2arr(i),
- src_out_arr => src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => g_nof_symbols_max
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ nof_symbols => nof_symbols(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+ src_in_arr => src_in_2arr(i),
+ src_out_arr => src_out_2arr(i)
+ );
end generate;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
index 628f50a26a..2c57bd5c09 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
@@ -48,11 +48,11 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_sync_checker is
generic(
@@ -84,11 +84,13 @@ architecture str of mms_dp_sync_checker is
-- Define the actual size of the MM slave register
constant c_nof_regs : positive := 2;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w,
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w,
+ nof_dat => c_nof_regs,
+ init_sl => '0'
+ );
signal read_register : std_logic_vector(c_nof_regs * c_word_w - 1 downto 0);
signal nof_early_syncs : std_logic_vector(c_word_w - 1 downto 0);
@@ -98,50 +100,50 @@ architecture str of mms_dp_sync_checker is
begin
u_dp_sync_checker : entity work.dp_sync_checker
- generic map(
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- snk_out => snk_out,
- snk_in => snk_in,
- src_in => src_in,
- src_out => src_out,
- nof_early_syncs => nof_early_syncs,
- nof_late_syncs => nof_late_syncs,
- clear_nof_early_syncs => reg_rd_arr(0),
- clear_nof_late_syncs => reg_rd_arr(1)
- );
+ generic map(
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ snk_out => snk_out,
+ snk_in => snk_in,
+ src_in => src_in,
+ src_out => src_out,
+ nof_early_syncs => nof_early_syncs,
+ nof_late_syncs => nof_late_syncs,
+ clear_nof_early_syncs => reg_rd_arr(0),
+ clear_nof_late_syncs => reg_rd_arr(1)
+ );
read_register <= nof_late_syncs & nof_early_syncs;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_dp_sync_checker_mosi,
- sla_out => reg_dp_sync_checker_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => reg_rd_arr,
- in_new => OPEN,
- in_reg => read_register,
- out_reg => OPEN,
- out_new => open
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_dp_sync_checker_mosi,
+ sla_out => reg_dp_sync_checker_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
+ in_new => OPEN,
+ in_reg => read_register,
+ out_reg => OPEN,
+ out_new => open
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
index a5f96ef3e1..2b223aecdf 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
@@ -28,9 +28,9 @@
-- share the same sync as input 0, as is the case e.g. after a dp_bsn_aligner.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_sync_checker_arr is
generic(
@@ -74,43 +74,43 @@ begin
-- Check sync on input stream 0
u_mms_dp_sync_checker : entity work.mms_dp_sync_checker
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- ST sinks
- snk_out => sync_checker_snk_out,
- snk_in => snk_in_arr(0),
- -- ST source
- src_in => src_in_arr(0),
- src_out => sync_checker_src_out,
-
- -- Memory Mapped
- reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
- reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- ST sinks
+ snk_out => sync_checker_snk_out,
+ snk_in => snk_in_arr(0),
+ -- ST source
+ src_in => src_in_arr(0),
+ src_out => sync_checker_src_out,
+
+ -- Memory Mapped
+ reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
+ reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
+ );
-- Pipeline all input streams with same latency as mms_dp_sync_checker
u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => snk_in_arr,
- -- ST source
- src_out_arr => pipeline_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => snk_in_arr,
+ -- ST source
+ src_out_arr => pipeline_src_out_arr
+ );
-- copy sync_checker control to all output streams, pass on the pipelined data
p_copy_sync_checker_controls : process(sync_checker_src_out, pipeline_src_out_arr)
diff --git a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
index 13f6ba742a..df694c0798 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_throttle is
@@ -57,40 +57,40 @@ architecture str of mms_dp_throttle is
begin
u_dp_throttle_reg : entity work.dp_throttle_reg
- generic map (
- g_dc_period => g_dc_period
- )
- port map (
+ generic map (
+ g_dc_period => g_dc_period
+ )
+ port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- throttle => throttle
- );
+ throttle => throttle
+ );
u_dp_throttle : entity work.dp_throttle
- generic map (
- g_dc_period => g_dc_period,
- g_throttle_valid => g_throttle_valid
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => snk_out,
- snk_in => snk_in,
-
- src_in => src_in,
- src_out => src_out,
-
- throttle => throttle
- );
+ generic map (
+ g_dc_period => g_dc_period,
+ g_throttle_valid => g_throttle_valid
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => snk_out,
+ snk_in => snk_in,
+
+ src_in => src_in,
+ src_out => src_out,
+
+ throttle => throttle
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
index a12560736e..e7c488181b 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_xonoff is
generic (
@@ -75,62 +75,62 @@ architecture str of mms_dp_xonoff is
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_ctrl_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_ctrl_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_reg : for i in 0 to c_nof_ctrl_streams - 1 generate
gen_no_timeout : if g_timeout_time = 0 generate
u_reg : entity work.dp_xonoff_reg
- generic map(
- g_default_value => g_default_value
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- xonoff_reg => xonoff_reg(i downto i)
- );
+ generic map(
+ g_default_value => g_default_value
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ xonoff_reg => xonoff_reg(i downto i)
+ );
end generate;
gen_with_timeout : if g_timeout_time > 0 generate
u_reg : entity work.dp_xonoff_reg_timeout
- generic map(
- g_default_value => g_default_value,
- g_mm_timeout => g_timeout_time,
- g_sim => g_sim
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- xonoff_reg => xonoff_reg(i downto i)
- );
+ generic map(
+ g_default_value => g_default_value,
+ g_mm_timeout => g_timeout_time,
+ g_sim => g_sim
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ xonoff_reg => xonoff_reg(i downto i)
+ );
end generate;
end generate;
@@ -142,20 +142,20 @@ begin
src_in_arr_i(i).xon <= src_in_arr(i).xon and xonoff_reg_i(i);
u_dp_xonoff : entity work.dp_xonoff
- generic map (
- g_bypass => g_bypass
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_bypass => g_bypass
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- in_siso => snk_out_arr(i),
- in_sosi => snk_in_arr(i),
- out_siso => src_in_arr_i(i),
- out_sosi => src_out_arr(i),
+ in_siso => snk_out_arr(i),
+ in_sosi => snk_in_arr(i),
+ out_siso => src_in_arr_i(i),
+ out_sosi => src_out_arr(i),
- force_xoff => force_xoff_arr(i)
- );
+ force_xoff => force_xoff_arr(i)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/tb/vhdl/dp_phy_link.vhd b/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
index e88d9c87c3..ede34a56c4 100644
--- a/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
-- Model a transceiver link.
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
index f33e7e29f8..8315a66079 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
-- Purpose:
-- . Like dp_sosi_recorder.vhd, but records an array to a file.
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
index b337797dae..4bf1a7190b 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
-- Purpose:
-- . Record the DP record fields to a file for later playback by
diff --git a/libraries/base/dp/tb/vhdl/dp_statistics.vhd b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
index c0e16cf02f..8f0c2c3105 100644
--- a/libraries/base/dp/tb/vhdl/dp_statistics.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
@@ -36,13 +36,13 @@
--
library IEEE, common_lib, work, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_statistics is
generic (
@@ -51,7 +51,7 @@ entity dp_statistics is
g_check_nof_valid : boolean := false; -- True enables valid count checking at dp_done. Reports Failure in case of mismatch.
g_check_nof_valid_ref : natural := 0; -- Reference (= expected) valid count
g_dp_word_w : natural := 32 -- Used to calculate data rate
- );
+ );
port (
dp_clk : in std_logic := '0';
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
index 100854294c..e115de322a 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
-- Purpose:
-- . Play back a stream recorded by dp_stream_recorder.
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd b/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
index 659ca1a745..f716529c5f 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- . Combine dp_stream_recorder and dp_stream_player.
@@ -42,7 +42,7 @@ entity dp_stream_rec_play is
g_rec_not_play : boolean := true;
g_rec_play_file : string := "dp_stream_recorder.rec";
g_record_invalid : boolean := true
- );
+ );
port (
dp_clk : in std_logic;
snk_in : in t_dp_sosi;
@@ -64,26 +64,26 @@ begin
gen_dp_sosi_recorder : if g_sim = true and g_rec_not_play = true generate
u_dp_sosi_recorder : entity work.dp_sosi_recorder
- generic map (
- g_record_file => g_rec_play_file,
- g_record_invalid => g_record_invalid
- )
- port map (
- dp_clk => dp_clk,
- snk_in => snk_in
- );
+ generic map (
+ g_record_file => g_rec_play_file,
+ g_record_invalid => g_record_invalid
+ )
+ port map (
+ dp_clk => dp_clk,
+ snk_in => snk_in
+ );
end generate;
gen_dp_stream_player : if g_sim = true and g_pass_through = false and g_rec_not_play = false generate
u_dp_stream_player : entity work.dp_stream_player
- generic map (
- g_playback_file => g_rec_play_file
- )
- port map (
- dp_clk => dp_clk,
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_playback_file => g_rec_play_file
+ )
+ port map (
+ dp_clk => dp_clk,
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
end str;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
index a59de84082..c7312b1ceb 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity dp_stream_stimuli is
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
index 18f1cdcd87..b84e950bad 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
@@ -39,13 +39,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity dp_stream_verify is
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
index b26e59d13f..954a090e46 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
@@ -45,13 +45,13 @@
-- . Observe out_* signals in Wave Window
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb2_dp_demux is
generic (
@@ -201,56 +201,56 @@ begin
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_mode => g_mode_demux,
- g_nof_output => g_nof_streams,
- g_remove_channel_lo => g_use_channel_lo,
- g_combined => g_combined_demux
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => g_in_channel,
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
+ generic map (
+ g_mode => g_mode_demux,
+ g_nof_output => g_nof_streams,
+ g_remove_channel_lo => g_use_channel_lo,
+ g_combined => g_combined_demux
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => g_in_channel,
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
+ );
------------------------------------------------------------------------------
-- DUT dp_mux
------------------------------------------------------------------------------
mux : entity work.dp_mux
- generic map (
- g_data_w => c_dp_data_w,
- g_empty_w => c_dp_empty_w,
- g_in_channel_w => c_dp_data_w,
- g_error_w => 1,
- g_use_empty => true,
- g_use_in_channel => true,
- g_use_error => false,
- g_mode => g_mode_mux,
- g_nof_input => g_nof_streams,
- g_append_channel_lo => g_use_channel_lo,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_streams), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_streams) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => g_in_channel,
- -- ST sinks
- snk_out_arr => demux_siso_arr,
- snk_in_arr => demux_sosi_arr,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_empty_w => c_dp_empty_w,
+ g_in_channel_w => c_dp_data_w,
+ g_error_w => 1,
+ g_use_empty => true,
+ g_use_in_channel => true,
+ g_use_error => false,
+ g_mode => g_mode_mux,
+ g_nof_input => g_nof_streams,
+ g_append_channel_lo => g_use_channel_lo,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_streams), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_streams) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => g_in_channel,
+ -- ST sinks
+ snk_out_arr => demux_siso_arr,
+ snk_in_arr => demux_sosi_arr,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
index 8333435a04..77bdd927ba 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
@@ -50,13 +50,13 @@
-- . Observe out_* signals in Wave Window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb2_dp_mux is
@@ -259,60 +259,60 @@ begin
-- Input level multiplexing
gen_mux : for I in 0 to c_nof_type-1 generate
u_input_mux : entity dp_lib.dp_mux
+ generic map (
+ -- MUX
+ g_mode => g_mode_mux,
+ g_nof_input => c_nof_input,
+ g_append_channel_lo => c_use_channel_lo,
+ -- Input FIFO
+ g_use_fifo => g_mux_use_fifo,
+ g_bsn_w => c_data_w,
+ g_data_w => c_data_w,
+ g_use_bsn => c_use_bsn,
+ g_use_sync => c_use_sync,
+ g_fifo_size => array_init( 1024, c_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_2arr(I),
+ snk_in_arr => in_sosi_2arr(I),
+ -- ST source
+ src_in => mux_siso_arr(I),
+ src_out => mux_sosi_arr(I)
+ );
+ end generate;
+
+ -- Second level multiplexing
+ u_type_mux : entity dp_lib.dp_mux
generic map (
-- MUX
g_mode => g_mode_mux,
- g_nof_input => c_nof_input,
+ g_nof_input => c_nof_type,
g_append_channel_lo => c_use_channel_lo,
-- Input FIFO
g_use_fifo => g_mux_use_fifo,
g_bsn_w => c_data_w,
g_data_w => c_data_w,
+ g_in_channel_w => c_channel_input_w, -- pass channel due to u_input_mux
+ g_use_in_channel => g_mux_use_fifo,
g_use_bsn => c_use_bsn,
g_use_sync => c_use_sync,
- g_fifo_size => array_init( 1024, c_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init( 1024, c_nof_type), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_type) -- must match g_nof_input, even when g_use_fifo=FALSE
)
port map (
rst => rst,
clk => clk,
-- ST sinks
- snk_out_arr => in_siso_2arr(I),
- snk_in_arr => in_sosi_2arr(I),
+ snk_out_arr => mux_siso_arr,
+ snk_in_arr => mux_sosi_arr,
-- ST source
- src_in => mux_siso_arr(I),
- src_out => mux_sosi_arr(I)
+ src_in => mux_siso,
+ src_out => mux_sosi
);
- end generate;
-
- -- Second level multiplexing
- u_type_mux : entity dp_lib.dp_mux
- generic map (
- -- MUX
- g_mode => g_mode_mux,
- g_nof_input => c_nof_type,
- g_append_channel_lo => c_use_channel_lo,
- -- Input FIFO
- g_use_fifo => g_mux_use_fifo,
- g_bsn_w => c_data_w,
- g_data_w => c_data_w,
- g_in_channel_w => c_channel_input_w, -- pass channel due to u_input_mux
- g_use_in_channel => g_mux_use_fifo,
- g_use_bsn => c_use_bsn,
- g_use_sync => c_use_sync,
- g_fifo_size => array_init( 1024, c_nof_type), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_type) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => mux_siso_arr,
- snk_in_arr => mux_sosi_arr,
- -- ST source
- src_in => mux_siso,
- src_out => mux_sosi
- );
-- Map to slv to ease monitoring in wave window
mux_data <= mux_sosi.data(c_data_w - 1 downto 0);
@@ -329,28 +329,9 @@ begin
------------------------------------------------------------------------------
u_type_demux: entity dp_lib.dp_demux
- generic map (
- g_mode => c_mode_demux,
- g_nof_output => c_nof_type,
- g_remove_channel_lo => c_use_channel_lo,
- g_combined => g_combined_demux
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => mux_siso,
- snk_in => mux_sosi,
- -- ST source
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
-
- gen_demux : for I in 0 to c_nof_type-1 generate
- u_output_demux : entity dp_lib.dp_demux
generic map (
g_mode => c_mode_demux,
- g_nof_output => c_nof_input,
+ g_nof_output => c_nof_type,
g_remove_channel_lo => c_use_channel_lo,
g_combined => g_combined_demux
)
@@ -358,13 +339,32 @@ begin
rst => rst,
clk => clk,
-- ST sinks
- snk_out => demux_siso_arr(I),
- snk_in => demux_sosi_arr(I),
+ snk_out => mux_siso,
+ snk_in => mux_sosi,
-- ST source
- src_in_arr => out_siso_2arr(I),
- src_out_arr => out_sosi_2arr(I)
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
);
+ gen_demux : for I in 0 to c_nof_type-1 generate
+ u_output_demux : entity dp_lib.dp_demux
+ generic map (
+ g_mode => c_mode_demux,
+ g_nof_output => c_nof_input,
+ g_remove_channel_lo => c_use_channel_lo,
+ g_combined => g_combined_demux
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => demux_siso_arr(I),
+ snk_in => demux_sosi_arr(I),
+ -- ST source
+ src_in_arr => out_siso_2arr(I),
+ src_out_arr => out_sosi_2arr(I)
+ );
+
gen_output : for J in 0 to c_nof_input - 1 generate
out_data(I, J) <= out_sosi_2arr(I)(J).data(c_data_w - 1 downto 0);
out_bsn( I, J) <= out_sosi_2arr(I)(J).bsn(c_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
index ce92600ab4..f98fd9f41c 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
@@ -36,13 +36,13 @@
-- . interrupted.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb3_dp_demux is
generic (
@@ -196,25 +196,25 @@ begin
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_mode => c_mode_demux,
- g_nof_output => g_nof_outputs,
- g_remove_channel_lo => c_use_channel_lo,
- g_combined => c_combined_demux,
- g_sel_ctrl_pkt => c_sel_ctrl_pkt
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => sel_ctrl,
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_mode => c_mode_demux,
+ g_nof_output => g_nof_outputs,
+ g_remove_channel_lo => c_use_channel_lo,
+ g_combined => c_combined_demux,
+ g_sel_ctrl_pkt => c_sel_ctrl_pkt
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => sel_ctrl,
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
-- Use same ready stimuli for all outputs to ease verification
out_siso_arr <= (others => out_siso);
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
index 365c95c0d1..4fd1c2671c 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
@@ -33,13 +33,13 @@
-- . The verify procedures check the correct output
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb3_dp_mux is
generic (
@@ -199,27 +199,27 @@ begin
------------------------------------------------------------------------------
mux : entity work.dp_mux
- generic map (
- -- MUX
- g_mode => c_mode_mux,
- g_nof_input => g_nof_inputs,
- g_append_channel_lo => c_use_channel_lo,
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_inputs), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_inputs) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => sel_ctrl,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ -- MUX
+ g_mode => c_mode_mux,
+ g_nof_input => g_nof_inputs,
+ g_append_channel_lo => c_use_channel_lo,
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_inputs), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_inputs) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => sel_ctrl,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index 7d3d9319bb..f709a46370 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -42,13 +42,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_from_mm is
@@ -207,71 +207,71 @@ begin
------------------------------------------------------------------------------
-- RAM with test data
u_ram_rd: entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => ram_wr_en,
- wr_adr => ram_wr_adr,
- wr_dat => ram_wr_dat,
- rd_en => rd_mosi.rd,
- rd_adr => rd_mosi.address(c_ram.adr_w - 1 downto 0),
- rd_dat => rd_miso.rddata(c_ram.dat_w - 1 downto 0),
- rd_val => rd_miso.rdval
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => ram_wr_en,
+ wr_adr => ram_wr_adr,
+ wr_dat => ram_wr_dat,
+ rd_en => rd_mosi.rd,
+ rd_adr => rd_mosi.address(c_ram.adr_w - 1 downto 0),
+ rd_dat => rd_miso.rddata(c_ram.dat_w - 1 downto 0),
+ rd_val => rd_miso.rdval
+ );
-- DUT, dp_block_from_mm
u_dp_block_from_mm: entity work.dp_block_from_mm
- generic map (
- g_user_size => g_data_size,
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
- start_pulse => start_pulse,
- start_address => start_address,
- mm_done => block_done,
- mm_mosi => rd_mosi,
- mm_miso => rd_miso,
- out_sosi => blk_sosi,
- out_siso => blk_siso
- );
+ generic map (
+ g_user_size => g_data_size,
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ start_pulse => start_pulse,
+ start_address => start_address,
+ mm_done => block_done,
+ mm_mosi => rd_mosi,
+ mm_miso => rd_miso,
+ out_sosi => blk_sosi,
+ out_siso => blk_siso
+ );
-- DUT, dp_block_to_mm
u_dp_block_to_mm: entity work.dp_block_to_mm
- generic map (
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
- start_address => start_address_dly,
- mm_mosi => wr_mosi,
- in_sosi => blk_sosi
- );
+ generic map (
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ start_address => start_address_dly,
+ mm_mosi => wr_mosi,
+ in_sosi => blk_sosi
+ );
-- RAM with transferred data
u_ram_wr: entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_mosi.wr,
- wr_adr => wr_mosi.address(c_ram.adr_w - 1 downto 0),
- wr_dat => wr_mosi.wrdata(c_ram.dat_w - 1 downto 0),
- rd_en => ram_rd_en,
- rd_adr => ram_rd_adr,
- rd_dat => ram_rd_dat,
- rd_val => ram_rd_val
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_mosi.wr,
+ wr_adr => wr_mosi.address(c_ram.adr_w - 1 downto 0),
+ wr_dat => wr_mosi.wrdata(c_ram.dat_w - 1 downto 0),
+ rd_en => ram_rd_en,
+ rd_adr => ram_rd_adr,
+ rd_dat => ram_rd_dat,
+ rd_val => ram_rd_val
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
index d6e6335fe5..d074308447 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
@@ -27,13 +27,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_gen is
@@ -183,27 +183,27 @@ begin
------------------------------------------------------------------------------
u_dut: entity work.dp_block_gen
- generic map (
- g_use_src_in => g_use_src_in,
- g_nof_data => g_nof_data_per_block,
- g_nof_blk_per_sync => g_nof_blk_per_sync,
- g_empty => 1,
- g_channel => 2,
- g_error => 3,
- g_bsn => c_bsn_init,
- g_preserve_sync => false,
- g_preserve_bsn => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming sink
- snk_in => ref_sosi,
- -- Streaming source
- src_in => out_siso,
- src_out => out_sosi,
- -- MM control
- en => enable
- );
+ generic map (
+ g_use_src_in => g_use_src_in,
+ g_nof_data => g_nof_data_per_block,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_empty => 1,
+ g_channel => 2,
+ g_error => 3,
+ g_bsn => c_bsn_init,
+ g_preserve_sync => false,
+ g_preserve_bsn => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming sink
+ snk_in => ref_sosi,
+ -- Streaming source
+ src_in => out_siso,
+ src_out => out_sosi,
+ -- MM control
+ en => enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
index e086efbfa8..870ea51864 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
@@ -28,13 +28,13 @@
-- Observe out_sosi in wave window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_gen_valid_arr is
@@ -140,49 +140,49 @@ begin
-- input data
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_flow_control => g_flow_control, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => g_nof_blk_per_sync,
- g_sync_offset => c_sync_offset,
- g_data_init => 0,
- g_bsn_init => TO_DP_BSN(c_bsn_init),
- g_err_init => c_err_init,
- g_err_incr => 0,
- g_channel_init => c_channel_init,
- g_channel_incr => 0,
- -- specific
- g_in_dat_w => 32,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_nof_data_per_block,
- g_pkt_gap => 0
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- last_snk_in => OPEN, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => OPEN, -- trigger verify to verify the last_snk_in
- tb_end => tb_input_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_flow_control => g_flow_control, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => g_nof_blk_per_sync,
+ g_sync_offset => c_sync_offset,
+ g_data_init => 0,
+ g_bsn_init => TO_DP_BSN(c_bsn_init),
+ g_err_init => c_err_init,
+ g_err_incr => 0,
+ g_channel_init => c_channel_init,
+ g_channel_incr => 0,
+ -- specific
+ g_in_dat_w => 32,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_nof_data_per_block,
+ g_pkt_gap => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ last_snk_in => OPEN, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => OPEN, -- trigger verify to verify the last_snk_in
+ tb_end => tb_input_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
-- Use dp_pipeline to model the latency introduced by upstream DSP components
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dsp_latency -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => stimuli_sosi,
- -- ST source
- src_out => dsp_sosi
- );
+ generic map (
+ g_pipeline => c_dsp_latency -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_out => dsp_sosi
+ );
p_in_sosi : process(dsp_sosi, stimuli_sosi)
begin
@@ -269,24 +269,24 @@ begin
------------------------------------------------------------------------------
u_dut: entity work.dp_block_gen_valid_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_data_per_block => g_nof_data_per_block,
- g_nof_blk_per_sync => g_nof_blk_per_sync,
- g_check_input_sync => g_check_input_sync,
- g_nof_pages_bsn => g_nof_pages_bsn,
- g_restore_global_bsn => g_restore_global_bsn
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming sink
- snk_in => in_sosi,
- snk_in_arr => in_sosi_arr,
- -- Streaming source
- src_out_arr => out_sosi_arr,
- -- MM control
- enable => enable
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_data_per_block => g_nof_data_per_block,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_check_input_sync => g_check_input_sync,
+ g_nof_pages_bsn => g_nof_pages_bsn,
+ g_restore_global_bsn => g_restore_global_bsn
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming sink
+ snk_in => in_sosi,
+ snk_in_arr => in_sosi_arr,
+ -- Streaming source
+ src_out_arr => out_sosi_arr,
+ -- MM control
+ enable => enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
index 20a72c57ba..4c75db4f53 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
@@ -42,14 +42,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_reshape is
generic (
@@ -102,64 +102,64 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => c_input_nof_blk_per_sync,
- g_nof_repeat => c_input_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => c_input_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => c_input_nof_blk_per_sync,
+ g_nof_repeat => c_input_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => c_input_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_reshape : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
- g_reshape_nof_data_per_blk => c_reshape_nof_data_per_blk,
- g_pipeline_src_out => g_pipeline,
- g_pipeline_src_in => 0
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => stimuli_sosi,
- snk_out => stimuli_siso,
-
- src_out => reshape_sosi,
- src_in => reshape_siso,
- src_index_arr => reshape_index_arr -- [1] sop index, [0] valid index
- );
+ generic map (
+ g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
+ g_reshape_nof_data_per_blk => c_reshape_nof_data_per_blk,
+ g_pipeline_src_out => g_pipeline,
+ g_pipeline_src_in => 0
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => stimuli_sosi,
+ snk_out => stimuli_siso,
+
+ src_out => reshape_sosi,
+ src_in => reshape_siso,
+ src_index_arr => reshape_index_arr -- [1] sop index, [0] valid index
+ );
u_reshape_back : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
- g_reshape_nof_data_per_blk => c_input_nof_data_per_blk,
- g_pipeline_src_out => 0,
- g_pipeline_src_in => g_pipeline
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => reshape_sosi,
- snk_out => reshape_siso,
-
- src_out => verify_sosi,
- src_in => verify_siso,
- src_index_arr => verify_index_arr -- [1] sop index, [0] valid index
- );
+ generic map (
+ g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
+ g_reshape_nof_data_per_blk => c_input_nof_data_per_blk,
+ g_pipeline_src_out => 0,
+ g_pipeline_src_in => g_pipeline
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => reshape_sosi,
+ snk_out => reshape_siso,
+
+ src_out => verify_sosi,
+ src_in => verify_siso,
+ src_index_arr => verify_index_arr -- [1] sop index, [0] valid index
+ );
------------------------------------------------------------------------------
@@ -167,19 +167,19 @@ begin
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_siso,
- src_out => pipeline_sosi
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_siso,
+ src_out => pipeline_sosi
+ );
p_verify : process(clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
index f2ddb10f0c..a65ef664cf 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
@@ -38,14 +38,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_reshape_sync is
generic (
@@ -104,64 +104,64 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_input_nof_blk_per_sync,
- g_nof_repeat => g_input_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => g_input_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_input_nof_blk_per_sync,
+ g_nof_repeat => g_input_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => g_input_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_reshape_dut : entity work.dp_block_reshape_sync
- generic map (
- g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
- g_reshape_nof_blk_per_sync => g_reshape_nof_blk_per_sync,
- g_reshape_bsn => g_reshape_bsn,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => stimuli_sosi,
- snk_out => stimuli_siso,
-
- src_out => reshape_sosi,
- src_in => reshape_siso
- );
+ generic map (
+ g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
+ g_reshape_nof_blk_per_sync => g_reshape_nof_blk_per_sync,
+ g_reshape_bsn => g_reshape_bsn,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => stimuli_sosi,
+ snk_out => stimuli_siso,
+
+ src_out => reshape_sosi,
+ src_in => reshape_siso
+ );
u_reshape_back : entity work.dp_block_reshape_sync
- generic map (
- g_reshape_nof_data_per_blk => g_input_nof_data_per_blk,
- g_reshape_nof_blk_per_sync => g_input_nof_blk_per_sync,
- g_reshape_bsn => g_reshape_bsn,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => reshape_sosi,
- snk_out => reshape_siso,
-
- src_out => verify_sosi,
- src_in => verify_siso
- );
+ generic map (
+ g_reshape_nof_data_per_blk => g_input_nof_data_per_blk,
+ g_reshape_nof_blk_per_sync => g_input_nof_blk_per_sync,
+ g_reshape_bsn => g_reshape_bsn,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => reshape_sosi,
+ snk_out => reshape_siso,
+
+ src_out => verify_sosi,
+ src_in => verify_siso
+ );
------------------------------------------------------------------------------
@@ -169,34 +169,34 @@ begin
------------------------------------------------------------------------------
u_pipeline_dut : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline -- = c_pipeline in u_reshape_dut
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_dut_siso,
- src_out => pipeline_dut_sosi
- );
+ generic map (
+ g_pipeline => c_pipeline -- = c_pipeline in u_reshape_dut
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_dut_siso,
+ src_out => pipeline_dut_sosi
+ );
u_pipeline_total : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline * 2 -- = c_pipeline in u_reshape_dut + c_pipeline in u_reshape_back
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_total_siso,
- src_out => pipeline_total_sosi
- );
+ generic map (
+ g_pipeline => c_pipeline * 2 -- = c_pipeline in u_reshape_dut + c_pipeline in u_reshape_back
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_total_siso,
+ src_out => pipeline_total_sosi
+ );
prev_reshape_sosi <= reshape_sosi when rising_edge(clk);
prev_verify_sosi <= verify_sosi when rising_edge(clk);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
index 9390dbd121..e55a5aacf2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
@@ -37,14 +37,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_select is
generic (
@@ -97,47 +97,47 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => c_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => c_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_select : entity work.dp_block_select
- generic map (
- g_pipeline => g_dut_pipeline,
- g_nof_blocks_per_sync => g_nof_blocks_per_sync,
- g_index_lo => g_index_lo,
- g_index_hi => g_index_hi
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- index_lo => g_index_lo,
- index_hi => g_index_hi,
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi
- );
+ generic map (
+ g_pipeline => g_dut_pipeline,
+ g_nof_blocks_per_sync => g_nof_blocks_per_sync,
+ g_index_lo => g_index_lo,
+ g_index_hi => g_index_hi
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ index_lo => g_index_lo,
+ index_hi => g_index_hi,
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi
+ );
------------------------------------------------------------------------------
@@ -145,19 +145,19 @@ begin
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_dut_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => g_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
stimuli_blk_cnt_reg <= stimuli_blk_cnt when rising_edge(clk);
stimuli_blk_cnt <= 0 when stimuli_sosi.sync = '1' else
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
index b3b2baea76..63b911042e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
@@ -31,16 +31,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_bsn_at_sync is
generic (
@@ -105,69 +105,69 @@ begin
-- Generate in_sosi with data frames
u_stimuli_in : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => c_nof_blk,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_channel_init => 0,
- g_bsn_init => TO_DP_BSN(0)
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => c_nof_blk,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_channel_init => 0,
+ g_bsn_init => TO_DP_BSN(0)
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
-- Generate bs_sosi with data frames
u_stimuli_bs : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => c_nof_blk,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_channel_init => 0,
- g_bsn_init => TO_DP_BSN(g_bsn_init)
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => bs_siso,
- src_out => bs_sosi,
-
- -- End of stimuli
- tb_end => open
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => c_nof_blk,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_channel_init => 0,
+ g_bsn_init => TO_DP_BSN(g_bsn_init)
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => bs_siso,
+ src_out => bs_sosi,
+
+ -- End of stimuli
+ tb_end => open
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_bsn_at_sync
- generic map (
- g_check_channel => c_check_channel
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- mm_rst => rst,
- mm_clk => mm_clk,
- -- ST sink
- in_sosi => stimuli_sosi,
- bs_sosi => bs_sosi,
- -- ST source
- out_sosi => verify_sosi,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso
- );
+ generic map (
+ g_check_channel => c_check_channel
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+ -- ST sink
+ in_sosi => stimuli_sosi,
+ bs_sosi => bs_sosi,
+ -- ST source
+ out_sosi => verify_sosi,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
+ );
------------------------------------------------------------------------------
@@ -175,25 +175,25 @@ begin
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
reference_cnt_reg <= reference_cnt when rising_edge(dp_clk);
reference_cnt <= reference_cnt_reg + 1 when reference_sosi.sync = '1' else reference_cnt_reg;
p_verify : process(dp_clk)
- variable v_valid_blk : boolean := true;
+ variable v_valid_blk : boolean := true;
begin
if rising_edge(dp_clk) then
if reference_sosi.sop = '1' then -- Decide for each block if it should be valid.
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
index e5c9a0f944..2fced5c094 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
@@ -31,16 +31,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_channel is
generic (
@@ -90,43 +90,43 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => g_gap_size
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => g_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_channel
- generic map (
- g_mode => g_mode
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- -- ST sink
- in_sosi => stimuli_sosi,
- -- ST source
- out_keep_sosi => keep_sosi,
- out_remove_sosi => remove_sosi,
-
- remove_channel => TO_UVEC(g_remove_channel, 32)
- );
+ generic map (
+ g_mode => g_mode
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ -- ST sink
+ in_sosi => stimuli_sosi,
+ -- ST source
+ out_keep_sosi => keep_sosi,
+ out_remove_sosi => remove_sosi,
+
+ remove_channel => TO_UVEC(g_remove_channel, 32)
+ );
------------------------------------------------------------------------------
@@ -134,19 +134,19 @@ begin
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
p_verify : process(dp_clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
index 235e95b15b..f0808d2b14 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
@@ -34,16 +34,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_err is
generic (
@@ -118,63 +118,63 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => g_gap_size,
- g_err_init => 0,
- g_err_incr => 1
- )
- port map (
- rst => stimuli_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => g_gap_size,
+ g_err_init => 0,
+ g_err_incr => 1
+ )
+ port map (
+ rst => stimuli_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_err
- generic map (
- g_cnt_w => g_cnt_w,
- g_blk_cnt_w => g_cnt_w,
- g_max_block_size => g_max_block_size,
- g_nof_err_counts => g_nof_err_counts,
- g_data_w => c_word_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_sync => true
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- ref_sync => stimuli_sosi.sync,
-
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi,
-
- mm_rst => rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso
- );
+ generic map (
+ g_cnt_w => g_cnt_w,
+ g_blk_cnt_w => g_cnt_w,
+ g_max_block_size => g_max_block_size,
+ g_nof_err_counts => g_nof_err_counts,
+ g_data_w => c_word_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_sync => true
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ ref_sync => stimuli_sosi.sync,
+
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
+ );
------------------------------------------------------------------------------
@@ -182,24 +182,24 @@ begin
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
reference_cnt_reg <= reference_cnt when rising_edge(dp_clk);
reference_cnt <= 0 when reference_sosi.eop = '1' and ((reference_cnt_reg + 1) mod 2**g_nof_err_counts) = 0 else
- reference_cnt_reg + 1 when reference_sosi.eop = '1' else
- reference_cnt_reg;
+ reference_cnt_reg + 1 when reference_sosi.eop = '1' else
+ reference_cnt_reg;
p_verify : process(dp_clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
index 5ae417b6fb..beb0f23b33 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
@@ -29,14 +29,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_length is
generic (
@@ -89,44 +89,44 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_err_init => 0,
- g_err_incr => 0
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_err_init => 0,
+ g_err_incr => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_length
- generic map (
- g_err_bi => g_err_bi,
- g_expected_length => g_expected_length
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi
- );
+ generic map (
+ g_err_bi => g_err_bi,
+ g_expected_length => g_expected_length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi
+ );
------------------------------------------------------------------------------
@@ -134,24 +134,24 @@ begin
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
stimuli_cnt_reg <= stimuli_cnt when rising_edge(clk);
stimuli_cnt <= 0 when stimuli_sosi.sop = '1' else
- stimuli_cnt_reg + 1 when stimuli_sosi.valid = '1' else
- stimuli_cnt_reg;
+ stimuli_cnt_reg + 1 when stimuli_sosi.valid = '1' else
+ stimuli_cnt_reg;
reference_cnt <= stimuli_cnt when rising_edge(clk);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
index 9f775c733b..0eb6591a08 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
@@ -34,13 +34,13 @@
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_align is
@@ -292,7 +292,7 @@ begin
verify_dis_arr <= (others => '0');
proc_common_wait_some_cycles(clk, 1000);
--- verify_dis_arr <= (OTHERS=>'1');
+ -- verify_dis_arr <= (OTHERS=>'1');
-- . enforce large BSN misalignment
tb_state <= s_large_bsn_diff;
@@ -301,8 +301,8 @@ begin
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
-- expect no output, because difference remains too large, so do not restart verify_en here and leave it commented:
--- proc_common_wait_some_cycles(clk, 100);
--- verify_dis_arr <= (OTHERS=>'0');
+ -- proc_common_wait_some_cycles(clk, 100);
+ -- verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
verify_dis_arr <= (others => '1');
@@ -413,26 +413,26 @@ begin
------------------------------------------------------------------------------
u_bsn_align : entity work.dp_bsn_align
- generic map (
- g_block_size => g_block_size,
- g_nof_input => g_nof_input,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => g_bsn_latency,
- g_bsn_request_pipeline => g_bsn_request_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr,
- -- MM
- in_en_evt => in_en_event,
- in_en_arr => in_en_arr
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_input => g_nof_input,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => g_bsn_latency,
+ g_bsn_request_pipeline => g_bsn_request_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+ -- MM
+ in_en_evt => in_en_event,
+ in_en_arr => in_en_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
index 2bf2549ee0..f3c531eb85 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
@@ -72,14 +72,14 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_align_v2 is
@@ -104,7 +104,7 @@ entity tb_dp_bsn_align_v2 is
-- TB
g_tb_diff_delay : integer := 0; -- 0 = aligned inputs, -1 = max input delay for no loss,
- -- >~ g_bsn_latency_max * g_block_period will give loss
+ -- >~ g_bsn_latency_max * g_block_period will give loss
g_tb_nof_restart : natural := 2; -- number of times to restart the input stimuli
g_tb_nof_blocks : natural := 20 -- number of input blocks per restart
);
@@ -129,7 +129,7 @@ architecture tb of tb_dp_bsn_align_v2 is
constant c_diff_delay : natural := sel_a_b(g_tb_diff_delay < 0, c_diff_delay_max, g_tb_diff_delay);
-- Return input delay as function of inputs stream index I
- function func_input_delay(I : natural) return natural is
+ function func_input_delay (I : natural) return natural is
variable v : natural;
begin
if g_nof_streams > 1 then
@@ -452,45 +452,45 @@ begin
dbg_verify_no_lost_flag_arr(I) <= '0';
dbg_verify_lost_flag_arr(I) <= '0';
if verify_sosi_en_arr(I) = '1' and out_sosi_arr_exp(I).valid = '1' then
- -- Verify sosi control fields
- dbg_verify_sosi_control_arr(I) <= '1';
- assert out_sosi_arr(I).sync = out_sosi_arr_exp(I).sync report "Wrong sync for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).sop = out_sosi_arr_exp(I).sop report "Wrong sop for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).eop = out_sosi_arr_exp(I).eop report "Wrong eop for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).valid = out_sosi_arr_exp(I).valid report "Wrong valid for output " & int_to_str(I) severity ERROR;
-
- -- Verify data field
- if stream_en_arr(I) = '1' and stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
- -- verify passed on data
- dbg_verify_passed_on_data_arr(I) <= '1';
- assert out_sosi_arr(I).data = out_sosi_arr_exp(I).data report "Wrong data for output stream " & int_to_str(I) & " : "
+ -- Verify sosi control fields
+ dbg_verify_sosi_control_arr(I) <= '1';
+ assert out_sosi_arr(I).sync = out_sosi_arr_exp(I).sync report "Wrong sync for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).sop = out_sosi_arr_exp(I).sop report "Wrong sop for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).eop = out_sosi_arr_exp(I).eop report "Wrong eop for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).valid = out_sosi_arr_exp(I).valid report "Wrong valid for output " & int_to_str(I) severity ERROR;
+
+ -- Verify data field
+ if stream_en_arr(I) = '1' and stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
+ -- verify passed on data
+ dbg_verify_passed_on_data_arr(I) <= '1';
+ assert out_sosi_arr(I).data = out_sosi_arr_exp(I).data report "Wrong data for output stream " & int_to_str(I) & " : "
& int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
& int_to_str(TO_UINT(out_sosi_arr_exp(I).data)) severity ERROR;
- else
- -- verify lost data stream at g_disable_stream_id or g_lost_stream_id or g_lost_bsn_id
- dbg_verify_replaced_data_arr(I) <= '1';
- assert TO_UINT(out_sosi_arr(I).data) = g_data_replacement_value report "Wrong replacement data for output stream " & int_to_str(I) & " : "
+ else
+ -- verify lost data stream at g_disable_stream_id or g_lost_stream_id or g_lost_bsn_id
+ dbg_verify_replaced_data_arr(I) <= '1';
+ assert TO_UINT(out_sosi_arr(I).data) = g_data_replacement_value report "Wrong replacement data for output stream " & int_to_str(I) & " : "
& int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
& int_to_str(g_data_replacement_value) severity ERROR;
- end if;
-
- -- Verify sop info fields
- if out_sosi_arr_exp(I).sop = '1' then
- -- bsn field
- dbg_verify_bsn_arr(I) <= '1';
- assert out_sosi_arr(I).bsn = out_sosi_arr_exp(I).bsn report "Wrong bsn for output " & int_to_str(I) severity ERROR;
-
- -- channel field with lost flag bit 0
- if stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
- -- verify no lost stream
- dbg_verify_no_lost_flag_arr(I) <= '1';
- assert out_sosi_arr(I).channel = TO_DP_CHANNEL(0) report "Wrong lost flag bit in channel /= 0 for output " & int_to_str(I) severity ERROR;
- else
- -- verify lost stream g_lost_stream_id or lost block g_lost_bsn_id
- dbg_verify_lost_flag_arr(I) <= '1';
- assert out_sosi_arr(I).channel = TO_DP_CHANNEL(1) report "Wrong lost flag bit channel /= 1 for output " & int_to_str(I) severity ERROR;
- end if;
- end if;
+ end if;
+
+ -- Verify sop info fields
+ if out_sosi_arr_exp(I).sop = '1' then
+ -- bsn field
+ dbg_verify_bsn_arr(I) <= '1';
+ assert out_sosi_arr(I).bsn = out_sosi_arr_exp(I).bsn report "Wrong bsn for output " & int_to_str(I) severity ERROR;
+
+ -- channel field with lost flag bit 0
+ if stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
+ -- verify no lost stream
+ dbg_verify_no_lost_flag_arr(I) <= '1';
+ assert out_sosi_arr(I).channel = TO_DP_CHANNEL(0) report "Wrong lost flag bit in channel /= 0 for output " & int_to_str(I) severity ERROR;
+ else
+ -- verify lost stream g_lost_stream_id or lost block g_lost_bsn_id
+ dbg_verify_lost_flag_arr(I) <= '1';
+ assert out_sosi_arr(I).channel = TO_DP_CHANNEL(1) report "Wrong lost flag bit channel /= 1 for output " & int_to_str(I) severity ERROR;
+ end if;
+ end if;
end if;
end if;
end process;
@@ -504,35 +504,35 @@ begin
dut_in_sosi_2arr(0) <= in_sosi_arr;
u_bsn_align : entity work.dp_bsn_align_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_bsn_latency_max => g_bsn_latency_max,
- g_nof_aligners_max => c_nof_aligners_max,
- g_block_size => g_block_size,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_data_replacement_value => g_data_replacement_value,
- g_use_mm_output => g_use_mm_output,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_rd_latency => g_rd_latency
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
- -- Control
- node_index => node_index_arr(0),
- stream_en_arr => stream_en_arr,
- -- Streaming input
- in_sosi_arr => dut_in_sosi_2arr(0),
- -- Output via local MM interface in dp_clk domain
- mm_copi => mm_copi,
- mm_cipo_arr => mm_cipo_arr,
- mm_sosi => mm_sosi,
-
- -- Output via streaming DP interface
- out_sosi_arr => dut_out_sosi_2arr(0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_bsn_latency_max => g_bsn_latency_max,
+ g_nof_aligners_max => c_nof_aligners_max,
+ g_block_size => g_block_size,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_data_replacement_value => g_data_replacement_value,
+ g_use_mm_output => g_use_mm_output,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_rd_latency => g_rd_latency
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+ -- Control
+ node_index => node_index_arr(0),
+ stream_en_arr => stream_en_arr,
+ -- Streaming input
+ in_sosi_arr => dut_in_sosi_2arr(0),
+ -- Output via local MM interface in dp_clk domain
+ mm_copi => mm_copi,
+ mm_cipo_arr => mm_cipo_arr,
+ mm_sosi => mm_sosi,
+
+ -- Output via streaming DP interface
+ out_sosi_arr => dut_out_sosi_2arr(0)
+ );
-- Simulate series of DUT, when g_use_mm_output = FALSE and
-- g_nof_aligners_max > 1. Use same local in_sosi_arr(0) input for all BSN
@@ -556,30 +556,30 @@ begin
--
gen_bsn_align_chain : for I in 1 to c_nof_aligners_max - 1 generate
u_bsn_align : entity work.dp_bsn_align_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_bsn_latency_max => g_bsn_latency_max,
- g_nof_aligners_max => c_nof_aligners_max,
- g_block_size => g_block_size,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_data_replacement_value => g_data_replacement_value,
- g_use_mm_output => g_use_mm_output,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_rd_latency => g_rd_latency
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
- -- Control
- node_index => node_index_arr(I),
- stream_en_arr => stream_en_arr,
- -- Streaming input
- in_sosi_arr => dut_in_sosi_2arr(I),
- -- Output via streaming DP interface
- out_sosi_arr => dut_out_sosi_2arr(I)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_bsn_latency_max => g_bsn_latency_max,
+ g_nof_aligners_max => c_nof_aligners_max,
+ g_block_size => g_block_size,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_data_replacement_value => g_data_replacement_value,
+ g_use_mm_output => g_use_mm_output,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_rd_latency => g_rd_latency
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+ -- Control
+ node_index => node_index_arr(I),
+ stream_en_arr => stream_en_arr,
+ -- Streaming input
+ in_sosi_arr => dut_in_sosi_2arr(I),
+ -- Output via streaming DP interface
+ out_sosi_arr => dut_out_sosi_2arr(I)
+ );
-- Connect remote and local between DUTs in the chain of DUTs
p_connect : process(dut_out_sosi_2arr, in_sosi_arr)
@@ -608,26 +608,26 @@ begin
gen_mm_to_dp : for I in 0 to g_nof_streams - 1 generate
u_mm_to_dp: entity work.dp_block_from_mm
- generic map (
- g_user_size => 1,
- g_data_size => 1,
- g_step_size => 1,
- g_nof_data => g_block_size,
- g_word_w => g_data_w,
- g_mm_rd_latency => g_rd_latency,
- g_reverse_word_order => false
- )
- port map (
- rst => rst,
- clk => clk,
- start_pulse => mm_sosi.sop,
- start_address => 0,
- mm_done => mm_done_arr(I),
- mm_mosi => mm_copi_arr(I),
- mm_miso => mm_cipo_arr(I),
- out_sosi => mm_sosi_arr(I),
- out_siso => c_dp_siso_rdy
- );
+ generic map (
+ g_user_size => 1,
+ g_data_size => 1,
+ g_step_size => 1,
+ g_nof_data => g_block_size,
+ g_word_w => g_data_w,
+ g_mm_rd_latency => g_rd_latency,
+ g_reverse_word_order => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ start_pulse => mm_sosi.sop,
+ start_address => 0,
+ mm_done => mm_done_arr(I),
+ mm_mosi => mm_copi_arr(I),
+ mm_miso => mm_cipo_arr(I),
+ out_sosi => mm_sosi_arr(I),
+ out_siso => c_dp_siso_rdy
+ );
end generate;
p_comb : process(r, mm_sosi, mm_sosi_arr)
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
index e4b19609be..2d06833610 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -28,13 +28,13 @@
-- . The verify procedures check the correct input and monitor results
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_monitor is
@@ -314,35 +314,35 @@ begin
-- Tap the stream to the monitor
dut : entity work.dp_bsn_monitor
- generic map (
- g_log_first_bsn => false,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- ST interface
- in_siso => out_siso,
- in_sosi => in_sosi,
- sync_in => sync_in,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt,
- mon_sync => mon_sync,
- mon_sync_timeout => mon_sync_timeout,
- -- . siso
- mon_ready_stable => mon_ready_stable,
- mon_xon_stable => mon_xon_stable,
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync,
- mon_nof_sop => mon_nof_sop,
- mon_nof_err => mon_nof_err,
- mon_nof_valid => mon_nof_valid,
-
- mon_bsn_first => mon_bsn_first,
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt
- );
+ generic map (
+ g_log_first_bsn => false,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- ST interface
+ in_siso => out_siso,
+ in_sosi => in_sosi,
+ sync_in => sync_in,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt,
+ mon_sync => mon_sync,
+ mon_sync_timeout => mon_sync_timeout,
+ -- . siso
+ mon_ready_stable => mon_ready_stable,
+ mon_xon_stable => mon_xon_stable,
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync,
+ mon_nof_sop => mon_nof_sop,
+ mon_nof_err => mon_nof_err,
+ mon_nof_valid => mon_nof_valid,
+
+ mon_bsn_first => mon_bsn_first,
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
index e013906e0b..968aed6702 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
@@ -28,13 +28,13 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_monitor_v2 is
@@ -314,32 +314,32 @@ begin
-- Tap the stream to the monitor
dut : entity work.dp_bsn_monitor_v2
- generic map (
- g_sync_timeout => c_sync_timeout
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- ST interface
- in_siso => out_siso,
- in_sosi => in_sosi,
- ref_sync => ref_sync,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt,
- mon_sync => mon_sync,
- mon_sync_timeout => mon_sync_timeout,
- -- . siso
- mon_ready_stable => mon_ready_stable,
- mon_xon_stable => mon_xon_stable,
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync,
- mon_nof_sop => mon_nof_sop,
- mon_nof_err => mon_nof_err,
- mon_nof_valid => mon_nof_valid,
- mon_latency => mon_latency
- );
+ generic map (
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- ST interface
+ in_siso => out_siso,
+ in_sosi => in_sosi,
+ ref_sync => ref_sync,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt,
+ mon_sync => mon_sync,
+ mon_sync_timeout => mon_sync_timeout,
+ -- . siso
+ mon_ready_stable => mon_ready_stable,
+ mon_xon_stable => mon_xon_stable,
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync,
+ mon_nof_sop => mon_nof_sop,
+ mon_nof_err => mon_nof_err,
+ mon_nof_valid => mon_nof_valid,
+ mon_latency => mon_latency
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
index 1d21b09efd..47e991edb6 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
@@ -27,12 +27,12 @@
-- and then manually verify on/off in Wave window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_source is
end tb_dp_bsn_source;
@@ -160,21 +160,21 @@ begin
-----------------------------------------------------------------------------
dut : entity work.dp_bsn_source
- generic map (
- g_block_size => c_block_size,
- g_nof_block_per_sync => c_sync_period,
- g_bsn_w => c_bsn_w
- )
- port map (
- rst => rst,
- clk => clk,
- pps => pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- init_bsn => init_bsn,
- -- Streaming
- src_out => bs_sosi
- );
+ generic map (
+ g_block_size => c_block_size,
+ g_nof_block_per_sync => c_sync_period,
+ g_bsn_w => c_bsn_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pps => pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ init_bsn => init_bsn,
+ -- Streaming
+ src_out => bs_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
index 69c2a55e5b..69249c2a66 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
@@ -43,12 +43,12 @@
-- . sync and bsn are verified automatically using the ref_grid
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_source_v2 is
generic (
@@ -328,29 +328,29 @@ begin
-----------------------------------------------------------------------------
dut : entity work.dp_bsn_source_v2
- generic map (
- g_block_size => g_block_size,
- g_nof_clk_per_sync => g_pps_interval,
- g_bsn_w => c_bsn_w,
- g_bsn_time_offset_w => c_bsn_time_offset_w
- )
- port map (
- rst => rst,
- clk => clk,
- pps => ref_grid.pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
-
- dp_on_status => dp_on_status, -- = src_out.valid
- bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
- bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
-
- bsn_init => bsn_init,
- bsn_time_offset => bsn_time_offset,
-
- -- Streaming
- src_out => bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_clk_per_sync => g_pps_interval,
+ g_bsn_w => c_bsn_w,
+ g_bsn_time_offset_w => c_bsn_time_offset_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pps => ref_grid.pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+
+ dp_on_status => dp_on_status, -- = src_out.valid
+ bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
+ bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
+
+ bsn_init => bsn_init,
+ bsn_time_offset => bsn_time_offset,
+
+ -- Streaming
+ src_out => bs_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
index 5165a0f848..2e277cc897 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
@@ -69,13 +69,13 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_sync_scheduler is
generic (
@@ -191,14 +191,15 @@ architecture tb of tb_dp_bsn_sync_scheduler is
signal dbg_expected_bsn : natural := 0;
-- Local procedures
- procedure proc_output_enable(signal clk : in std_logic;
- signal cnt : in integer;
- signal sync : in std_logic;
- signal mon_input_bsn_at_sync : in std_logic_vector(c_bsn_w - 1 downto 0);
- signal stimuli_state : out t_stimuli_state_enum;
- signal ctrl_start_bsn : out std_logic_vector(c_bsn_w - 1 downto 0);
- signal ctrl_enable : out std_logic;
- signal ctrl_enable_evt : out std_logic) is
+ procedure proc_output_enable (
+ signal clk : in std_logic;
+ signal cnt : in integer;
+ signal sync : in std_logic;
+ signal mon_input_bsn_at_sync : in std_logic_vector(c_bsn_w - 1 downto 0);
+ signal stimuli_state : out t_stimuli_state_enum;
+ signal ctrl_start_bsn : out std_logic_vector(c_bsn_w - 1 downto 0);
+ signal ctrl_enable : out std_logic;
+ signal ctrl_enable_evt : out std_logic) is
begin
proc_common_wait_until_hi_lo(clk, sync); -- (re)enable at begin of sync interval
stimuli_state <= e_en;
@@ -209,21 +210,23 @@ architecture tb of tb_dp_bsn_sync_scheduler is
ctrl_enable_evt <= '0';
end proc_output_enable;
- procedure proc_output_re_enable(signal clk : in std_logic;
- signal cnt : in integer;
- signal mon_input_bsn_at_sync : in std_logic_vector(c_bsn_w - 1 downto 0);
- signal stimuli_state : out t_stimuli_state_enum;
- signal ctrl_start_bsn : out std_logic_vector(c_bsn_w - 1 downto 0);
- signal ctrl_enable : out std_logic;
- signal ctrl_enable_evt : out std_logic) is
+ procedure proc_output_re_enable (
+ signal clk : in std_logic;
+ signal cnt : in integer;
+ signal mon_input_bsn_at_sync : in std_logic_vector(c_bsn_w - 1 downto 0);
+ signal stimuli_state : out t_stimuli_state_enum;
+ signal ctrl_start_bsn : out std_logic_vector(c_bsn_w - 1 downto 0);
+ signal ctrl_enable : out std_logic;
+ signal ctrl_enable_evt : out std_logic) is
begin
proc_output_enable(clk, cnt, in_sync, mon_input_bsn_at_sync, stimuli_state, ctrl_start_bsn, ctrl_enable, ctrl_enable_evt);
stimuli_state <= e_re;
end proc_output_re_enable;
- procedure proc_output_disable(signal stimuli_state : out t_stimuli_state_enum;
- signal ctrl_enable : out std_logic;
- signal ctrl_enable_evt : out std_logic) is
+ procedure proc_output_disable (
+ signal stimuli_state : out t_stimuli_state_enum;
+ signal ctrl_enable : out std_logic;
+ signal ctrl_enable_evt : out std_logic) is
begin
stimuli_state <= e_dis;
ctrl_enable <= '0';
@@ -316,26 +319,26 @@ begin
-- Generate data blocks with input sync
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_block_per_input_sync,
- g_err_init => 0,
- g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
- g_channel_init => 0,
- g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
- g_nof_repeat => c_sim_nof_blocks,
- g_pkt_len => g_block_size,
- g_pkt_gap => g_input_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => tb_end
- );
+ generic map (
+ g_sync_period => g_nof_block_per_input_sync,
+ g_err_init => 0,
+ g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ g_channel_init => 0,
+ g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ g_nof_repeat => c_sim_nof_blocks,
+ g_pkt_len => g_block_size,
+ g_pkt_gap => g_input_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => tb_end
+ );
-- Input with option to loose data blocks
p_in_sosi : process(stimuli_sosi, in_lost)
@@ -558,8 +561,8 @@ begin
assert TO_UINT(mon_output_sync_bsn) <= v_bsn_max
report "Wrong: mon_output_sync_bsn is too far ahead (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " > " & int_to_str(v_bsn_max) & ")" severity ERROR;
- --Debug report used to investigate v_bsn_min and v_bsn_max assert conditions
- --REPORT int_to_str(TO_UINT(mon_output_sync_bsn)) & " : " & int_to_str(TO_UINT(mon_current_input_bsn)) SEVERITY NOTE;
+ --Debug report used to investigate v_bsn_min and v_bsn_max assert conditions
+ --REPORT int_to_str(TO_UINT(mon_output_sync_bsn)) & " : " & int_to_str(TO_UINT(mon_current_input_bsn)) SEVERITY NOTE;
end if;
end if;
end if;
@@ -571,31 +574,31 @@ begin
-----------------------------------------------------------------------------
dut : entity work.dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => c_bsn_w,
- g_block_size => g_block_size,
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- M&C
- ctrl_enable => ctrl_enable,
- ctrl_enable_evt => ctrl_enable_evt,
- ctrl_interval_size => ctrl_interval_size,
- ctrl_start_bsn => ctrl_start_bsn,
- mon_current_input_bsn => mon_current_input_bsn,
- mon_input_bsn_at_sync => mon_input_bsn_at_sync,
- mon_output_enable => mon_output_enable,
- mon_output_sync_bsn => mon_output_sync_bsn,
-
- -- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_start_interval => out_start_interval,
- out_enable => out_enable
- );
+ generic map (
+ g_bsn_w => c_bsn_w,
+ g_block_size => g_block_size,
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- M&C
+ ctrl_enable => ctrl_enable,
+ ctrl_enable_evt => ctrl_enable_evt,
+ ctrl_interval_size => ctrl_interval_size,
+ ctrl_start_bsn => ctrl_start_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
+ mon_input_bsn_at_sync => mon_input_bsn_at_sync,
+ mon_output_enable => mon_output_enable,
+ mon_output_sync_bsn => mon_output_sync_bsn,
+
+ -- Streaming
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_start_interval => out_start_interval,
+ out_enable => out_enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
index 1db8875e84..a418093ee5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
@@ -31,14 +31,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_calculate_crc is
generic (
@@ -89,22 +89,22 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => c_nof_blk_per_sync,
- g_nof_repeat => c_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => c_nof_data_per_blk,
- g_pkt_gap => g_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => c_nof_blk_per_sync,
+ g_nof_repeat => c_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => c_nof_data_per_blk,
+ g_pkt_gap => g_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
-- Use same dat for every block to verify restart of CRC calculation
p_snk_in : process(stimuli_sosi)
@@ -117,17 +117,17 @@ begin
-- DUT
------------------------------------------------------------------------------
u_crc : entity work.dp_calculate_crc
- generic map (
- g_data_w => g_data_w,
- g_crc_w => g_crc_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- blk_crc => blk_crc
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_crc_w => g_crc_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ blk_crc => blk_crc
+ );
------------------------------------------------------------------------------
-- Verifycation
@@ -139,12 +139,12 @@ begin
if rising_edge(clk) then
if new_crc = '1' then
--IF g_data_w = 28 AND g_crc_w = 28 AND c_nof_data_per_blk = 9 THEN
- if blk_crc = exp_crc_28 then
- report "OK CRC value." severity NOTE;
- else
- report "Wrong CRC value." severity ERROR;
- end if;
- --END IF;
+ if blk_crc = exp_crc_28 then
+ report "OK CRC value." severity NOTE;
+ else
+ report "Wrong CRC value." severity ERROR;
+ end if;
+ --END IF;
end if;
end if;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
index d8aeb34095..ef6dca6b5b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_concat is
generic (
@@ -152,18 +152,18 @@ begin
end process;
dut : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi_arr,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
-- Input data
in_data_0 <= in_sosi_arr(0).data(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
index a4504c4175..ea88ea71d1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
@@ -36,15 +36,15 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_concat_field_blk is
@@ -97,28 +97,28 @@ architecture tb of tb_dp_concat_field_blk is
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
-- From apertif_unb1_fn_beamformer_udp_offload.vhd:
-- Override ('1') only the Ethernet fields so we can use MM defaults there.
@@ -199,36 +199,36 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- -- specific
- g_in_dat_w => g_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_wait_last_evt
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_wait_last_evt
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
@@ -263,37 +263,37 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_data_w,
- g_pkt_len => c_expected_pkt_len
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_pkt_len => c_expected_pkt_len
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT offload Tx
@@ -303,23 +303,23 @@ begin
-- Use FIFO to mimic apertif_unb1_fn_beamformer_udp_offload.vhd, without FIFO dp_stream_stimuli
-- would handle the back pressure
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => 64,
- g_use_sync => true,
- g_use_bsn => true,
- g_fifo_size => 1024
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => OPEN, -- stimuli_src_in
- snk_in => stimuli_src_out,
-
- src_in => dp_fifo_sc_src_in,
- src_out => dp_fifo_sc_src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_use_bsn => true,
+ g_fifo_size => 1024
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => OPEN, -- stimuli_src_in
+ snk_in => stimuli_src_out,
+
+ src_in => dp_fifo_sc_src_in,
+ src_out => dp_fifo_sc_src_out
+ );
dp_offload_tx_snk_in_arr(0) <= dp_fifo_sc_src_out;
dp_fifo_sc_src_in <= dp_offload_tx_snk_out_arr(0);
@@ -338,31 +338,31 @@ begin
tx_hdr_fields_in_arr(0)(field_hi(c_udp_offload_hdr_field_arr, "dp_bsn" ) downto field_lo(c_udp_offload_hdr_field_arr, "dp_bsn" )) <= dp_offload_tx_snk_in_arr(0).bsn(63 downto 0);
u_tx : entity work.dp_concat_field_blk
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => dp_offload_tx_snk_out_arr,
-
- src_out_arr => tx_offload_sosi_arr,
- src_in_arr => tx_offload_siso_arr,
-
- hdr_fields_in_arr => tx_hdr_fields_in_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => tx_offload_sosi_arr,
+ src_in_arr => tx_offload_siso_arr,
+
+ hdr_fields_in_arr => tx_hdr_fields_in_arr
+ );
------------------------------------------------------------------------------
-- Link
@@ -386,32 +386,32 @@ begin
------------------------------------------------------------------------------
u_rx : entity work.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => link_offload_sosi_arr,
- snk_out_arr => link_offload_siso_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => rx_hdr_fields_out_arr,
- hdr_fields_raw_arr => rx_hdr_fields_raw_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => link_offload_sosi_arr,
+ snk_out_arr => link_offload_siso_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => rx_hdr_fields_out_arr,
+ hdr_fields_raw_arr => rx_hdr_fields_raw_arr
+ );
p_restore_sync_bsn : process(dp_offload_rx_src_out_arr, rx_hdr_fields_out_arr)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
index 1443301e5a..e56f57af29 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
@@ -32,14 +32,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_counter is
generic (
@@ -84,7 +84,7 @@ architecture tb of tb_dp_counter is
signal count_src_out_arr : t_dp_sosi_arr(g_nof_counters - 1 downto 0);
signal period : natural;
- function calculate_period(g_counter : natural) return natural is
+ function calculate_period (g_counter : natural) return natural is
variable v_range_period : t_nat_natural_arr(g_counter downto 0);
variable v_period : natural := 1;
begin
@@ -173,26 +173,26 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => g_range_start,
- g_range_stop => g_range_stop,
- g_range_step => g_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in,
-
- count_src_out_arr => count_src_out_arr
- );
+ generic map (
+ g_nof_counters => g_nof_counters,
+ g_range_start => g_range_start,
+ g_range_stop => g_range_stop,
+ g_range_step => g_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => src_out,
+ src_in => src_in,
+
+ count_src_out_arr => count_src_out_arr
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
index 2e20614d26..c885d2ae5f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
@@ -37,14 +37,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_counter_func is
generic (
@@ -94,7 +94,7 @@ architecture tb of tb_dp_counter_func is
signal tb_count_arr : t_count_arr := (others => 0);
signal tb_last_count_arr : t_count_arr := (others => 0);
- begin
+begin
------------------------------------------------------------------------------
-- Clock & reset
@@ -107,7 +107,7 @@ architecture tb of tb_dp_counter_func is
------------------------------------------------------------------------------
p_stimuli : process
- variable run_clk_cnt: natural := 1;
+ variable run_clk_cnt: natural := 1;
begin
-- wait for reset
proc_common_wait_until_low(clk, rst);
@@ -148,20 +148,20 @@ architecture tb of tb_dp_counter_func is
-- dp_counter_func
------------------------------------------------------------------------------
u_dp_counter_func : entity work.dp_counter_func
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => g_range_start,
- g_range_stop => g_range_stop,
- g_range_step => g_range_step
- )
- port map (
- rst => rst,
- clk => clk,
-
- count_en => dp_counter_func_count_en,
-
- count_src_out_arr => dp_counter_func_count_src_out_arr
- );
+ generic map (
+ g_nof_counters => g_nof_counters,
+ g_range_start => g_range_start,
+ g_range_stop => g_range_stop,
+ g_range_step => g_range_step
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ count_en => dp_counter_func_count_en,
+
+ count_src_out_arr => dp_counter_func_count_src_out_arr
+ );
-- Add pipeline to removed combinatorial glitches for viewing in the wave window
dp_counter_func_count_src_out_arr_p <= dp_counter_func_count_src_out_arr when rising_edge(clk);
@@ -197,7 +197,7 @@ architecture tb of tb_dp_counter_func is
end loop;
-- the last counter should hold the start value + step
assert tb_count_arr(g_nof_counters - 1) = g_range_start(g_nof_counters - 1) + g_range_step(g_nof_counters - 1)
- report "DP : Wrong carryover, counter:" & int_to_str(g_nof_counters - 1) severity ERROR;
+ report "DP : Wrong carryover, counter:" & int_to_str(g_nof_counters - 1) severity ERROR;
end if;
-- check counter values on sop and eop
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
index b78741a463..ec9294c71d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
@@ -32,14 +32,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_counter_offset is
generic (
@@ -85,7 +85,7 @@ architecture tb of tb_dp_counter_offset is
signal count_src_out_arr : t_dp_sosi_arr(g_nof_counters - 1 downto 0);
signal period : natural;
- function calculate_period(g_counter : natural) return natural is
+ function calculate_period (g_counter : natural) return natural is
variable v_range_period : t_nat_natural_arr(g_counter downto 0);
variable v_period : natural := 1;
begin
@@ -176,27 +176,27 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => g_range_start,
- g_range_stop => g_range_stop,
- g_range_step => g_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in,
-
- count_offset_in_arr => count_offset_in_arr,
- count_src_out_arr => count_src_out_arr
- );
+ generic map (
+ g_nof_counters => g_nof_counters,
+ g_range_start => g_range_start,
+ g_range_stop => g_range_stop,
+ g_range_step => g_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => src_out,
+ src_in => src_in,
+
+ count_offset_in_arr => count_offset_in_arr,
+ count_src_out_arr => count_src_out_arr
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
index db0399479c..00a2ec353e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.tb_dp_pkg.all;
-- Purpose: Test bench to check deinterleave function on DP level
-- Usage:
@@ -41,7 +41,7 @@ entity tb_dp_deinterleave is
g_nof_out : natural := 2;
g_block_size : natural := 3;
g_use_complex : boolean := true
- );
+ );
end;
architecture tb of tb_dp_deinterleave is
@@ -111,26 +111,26 @@ begin
proc_common_wait_some_cycles(clk, c_input_inval);
v_bsn := INCR_UVEC(v_bsn, 1);
end loop;
- end process;
+ end process;
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
u_deinterleave : entity work.dp_deinterleave
- generic map (
- g_nof_out => g_nof_out,
- g_block_size_int => g_block_size,
- g_block_size_output => g_block_size,
- g_dat_w => g_dat_w,
- g_use_complex => g_use_complex
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_block_size_int => g_block_size,
+ g_block_size_output => g_block_size,
+ g_dat_w => g_dat_w,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ src_out_arr => src_out_arr
+ );
-----------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
index 2eeac9a7e2..347792f105 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
@@ -43,14 +43,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_deinterleave_interleave_to_one is
generic (
@@ -146,43 +146,43 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => g_use_complex,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => g_use_complex,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
-- Throttle stimuli to ensure active = 1, period = 3, level '1'
--proc_common_gen_pulse(1, 3, '1', rst, clk, stimuli_src_in.ready);
@@ -219,108 +219,108 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => c_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_out_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => c_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_out_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: 1 to N
------------------------------------------------------------------------------
u_dp_deinterleave : entity work.dp_deinterleave
- generic map (
- g_dat_w => c_data_w,
- g_nof_out => g_nof_streams,
- g_block_size_int => 1,
- g_block_size_output => c_par_pkt_len, -- Output block size: The number of samles in the blocks at the output
- g_use_ctrl => true, -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
- g_use_sync_bsn => true, -- forwards (stored) input Sync+BSN to all output streams
- g_use_complex => g_use_complex,
- g_align_out => true -- Aligns the output streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => stimuli_src_out,
- src_out_arr => parallel_snk_in_arr
- );
-
- -- Use FIFO to break flow control between one to N and N to one, so that stimuli see ready = '1'
- gen_fifos : for I in 0 to g_nof_streams - 1 generate
- u_dp_fifo_sc : entity work.dp_fifo_sc
generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_dp_stream_dsp_data_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true, -- sop & eop
- g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_dat_w => c_data_w,
+ g_nof_out => g_nof_streams,
+ g_block_size_int => 1,
+ g_block_size_output => c_par_pkt_len, -- Output block size: The number of samles in the blocks at the output
+ g_use_ctrl => true, -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
+ g_use_sync_bsn => true, -- forwards (stored) input Sync+BSN to all output streams
+ g_use_complex => g_use_complex,
+ g_align_out => true -- Aligns the output streams
)
port map (
rst => rst,
clk => clk,
- -- Monitor FIFO filling
- -- ST sink
- snk_out => parallel_snk_out_arr(I),
- snk_in => parallel_snk_in_arr(I),
- -- ST source
- src_in => parallel_src_in_arr(I),
- src_out => parallel_src_out_arr(I)
+
+ snk_in => stimuli_src_out,
+ src_out_arr => parallel_snk_in_arr
);
+
+ -- Use FIFO to break flow control between one to N and N to one, so that stimuli see ready = '1'
+ gen_fifos : for I in 0 to g_nof_streams - 1 generate
+ u_dp_fifo_sc : entity work.dp_fifo_sc
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_dp_stream_dsp_data_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true, -- sop & eop
+ g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ -- ST sink
+ snk_out => parallel_snk_out_arr(I),
+ snk_in => parallel_snk_in_arr(I),
+ -- ST source
+ src_in => parallel_src_in_arr(I),
+ src_out => parallel_src_out_arr(I)
+ );
end generate;
------------------------------------------------------------------------------
-- DUT: N to 1
------------------------------------------------------------------------------
u_n_to_one: entity work.dp_interleave_n_to_one
- generic map (
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out_arr => parallel_src_in_arr,
- snk_in_arr => parallel_src_out_arr,
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_streams
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out_arr => parallel_src_in_arr,
+ snk_in_arr => parallel_src_out_arr,
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- Auxiliary
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
index 0efefa875c..1499ac42f2 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -37,14 +37,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_deinterleave_one_to_n_to_one is
generic (
@@ -138,43 +138,43 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => g_use_complex,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => g_use_complex,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
@@ -209,55 +209,55 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_out_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_out_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: 1 to N
------------------------------------------------------------------------------
u_one_to_n : entity work.dp_deinterleave_one_to_n
- generic map (
- g_pipeline => g_pipeline,
- g_nof_outputs => g_nof_streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- src_in_arr => parallel_snk_out_arr,
- src_out_arr => parallel_snk_in_arr
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_outputs => g_nof_streams
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ src_in_arr => parallel_snk_out_arr,
+ src_out_arr => parallel_snk_in_arr
+ );
no_fifo : if g_use_fifo = false generate
parallel_snk_out_arr <= parallel_src_in_arr;
@@ -268,32 +268,32 @@ begin
use_fifo : if g_use_fifo = true generate
gen_fifos : for I in 0 to g_nof_streams - 1 generate
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_dp_stream_dsp_data_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true, -- sop & eop
- g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- -- ST sink
- snk_out => parallel_snk_out_arr(I),
- snk_in => parallel_snk_in_arr(I),
- -- ST source
- src_in => parallel_src_in_arr(I),
- src_out => parallel_src_out_arr(I)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_dp_stream_dsp_data_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true, -- sop & eop
+ g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ -- ST sink
+ snk_out => parallel_snk_out_arr(I),
+ snk_in => parallel_snk_in_arr(I),
+ -- ST source
+ src_in => parallel_src_in_arr(I),
+ src_out => parallel_src_out_arr(I)
+ );
end generate;
end generate;
@@ -301,19 +301,19 @@ begin
-- DUT: N to 1
------------------------------------------------------------------------------
u_n_to_one: entity work.dp_interleave_n_to_one
- generic map (
- g_pipeline => g_pipeline,
- g_nof_inputs => g_nof_streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out_arr => parallel_src_in_arr,
- snk_in_arr => parallel_src_out_arr,
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_inputs => g_nof_streams
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out_arr => parallel_src_in_arr,
+ snk_in_arr => parallel_src_out_arr,
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- Auxiliary
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
index bbdf5573bf..225c99bf9d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_demux is
generic (
@@ -165,8 +165,8 @@ begin
in_channel_vec((I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w) <= in_channel(I);
-- Stimuli control
--- proc_dp_count_en(rst, clk, sync, lfsr1(I)(c_random_w-1 DOWNTO 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en behave the same
--- proc_dp_out_ready(rst, clk, sync, lfsr2(I)(c_random_w DOWNTO 0), out_ready(I)); -- all out_ready behave the same
+ -- proc_dp_count_en(rst, clk, sync, lfsr1(I)(c_random_w-1 DOWNTO 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en behave the same
+ -- proc_dp_out_ready(rst, clk, sync, lfsr2(I)(c_random_w DOWNTO 0), out_ready(I)); -- all out_ready behave the same
proc_dp_count_en(rst, clk, sync_dly(I), lfsr1(I)(c_random_w - 1 downto 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en are relatively delayed
proc_dp_out_ready(rst, clk, sync_dly(I), lfsr2(I)(c_random_w downto 0), out_ready(I)); -- all out_ready are relatively delayed
@@ -225,48 +225,48 @@ begin
end process;
mux : entity work.dp_mux
- generic map (
- g_data_w => c_dp_data_w,
- g_empty_w => c_dp_empty_w,
- g_in_channel_w => c_dp_data_w,
- g_error_w => 1,
- g_use_empty => true,
- g_use_in_channel => true,
- g_use_error => false,
- g_nof_input => g_dut_nof_output,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_dut_nof_output), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_dut_nof_output) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi,
- -- ST source
- src_in => mux_siso, -- IN = request from downstream ST sink
- src_out => mux_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_empty_w => c_dp_empty_w,
+ g_in_channel_w => c_dp_data_w,
+ g_error_w => 1,
+ g_use_empty => true,
+ g_use_in_channel => true,
+ g_use_error => false,
+ g_nof_input => g_dut_nof_output,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_dut_nof_output), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_dut_nof_output) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi,
+ -- ST source
+ src_in => mux_siso, -- IN = request from downstream ST sink
+ src_out => mux_sosi
+ );
------------------------------------------------------------------------------
-- DUT dp_demux
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_nof_output => g_dut_nof_output,
- g_combined => g_combined
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => mux_siso, -- OUT = request to upstream ST source
- snk_in => mux_sosi,
- -- ST source
- src_in_arr => demux_siso, -- IN = request from downstream ST sink
- src_out_arr => demux_sosi
- );
+ generic map (
+ g_nof_output => g_dut_nof_output,
+ g_combined => g_combined
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => mux_siso, -- OUT = request to upstream ST source
+ snk_in => mux_sosi,
+ -- ST source
+ src_in_arr => demux_siso, -- IN = request from downstream ST sink
+ src_out_arr => demux_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
index f300446af5..80957b705f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
@@ -39,13 +39,13 @@
-- would need to use DP packet encoder and decoders.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_distribute is
generic (
@@ -248,72 +248,72 @@ begin
-- n --> m
tx : entity work.dp_distribute
- generic map (
- -- Distribution IO
- g_tx => true,
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_serial,
- g_transpose => g_transpose,
- g_code_channel_lo => g_code_channel_lo,
- g_data_w => c_data_w,
- -- Input FIFO
- g_use_fifo => g_tx_use_fifo,
- g_bsn_w => c_data_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_bsn => g_tx_use_fifo,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => g_tx_use_fifo,
- g_fifo_fill => g_tx_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => serial_siso_arr,
- src_out_arr => serial_sosi_arr
- );
+ generic map (
+ -- Distribution IO
+ g_tx => true,
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_serial,
+ g_transpose => g_transpose,
+ g_code_channel_lo => g_code_channel_lo,
+ g_data_w => c_data_w,
+ -- Input FIFO
+ g_use_fifo => g_tx_use_fifo,
+ g_bsn_w => c_data_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_bsn => g_tx_use_fifo,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => g_tx_use_fifo,
+ g_fifo_fill => g_tx_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => serial_siso_arr,
+ src_out_arr => serial_sosi_arr
+ );
-- m --> n
rx : entity work.dp_distribute
- generic map (
- -- Distribution IO
- g_tx => false,
- g_nof_input => g_nof_serial,
- g_nof_output => g_nof_input,
- g_transpose => g_transpose,
- g_code_channel_lo => g_code_channel_lo,
- g_data_w => c_data_w,
- -- Input FIFO
- g_use_fifo => g_rx_use_fifo,
- g_bsn_w => c_data_w,
- g_empty_w => 1,
- g_channel_w => c_link_channel_lo, -- c_link_channel_lo-1 DOWNTO 0
- g_error_w => 1,
- g_use_bsn => g_rx_use_fifo,
- g_use_empty => false,
- g_use_channel => c_rx_use_fifo_link_channel_lo,
- g_use_error => false,
- g_use_sync => g_rx_use_fifo,
- g_fifo_fill => g_rx_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => serial_siso_arr,
- snk_in_arr => serial_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ -- Distribution IO
+ g_tx => false,
+ g_nof_input => g_nof_serial,
+ g_nof_output => g_nof_input,
+ g_transpose => g_transpose,
+ g_code_channel_lo => g_code_channel_lo,
+ g_data_w => c_data_w,
+ -- Input FIFO
+ g_use_fifo => g_rx_use_fifo,
+ g_bsn_w => c_data_w,
+ g_empty_w => 1,
+ g_channel_w => c_link_channel_lo, -- c_link_channel_lo-1 DOWNTO 0
+ g_error_w => 1,
+ g_use_bsn => g_rx_use_fifo,
+ g_use_empty => false,
+ g_use_channel => c_rx_use_fifo_link_channel_lo,
+ g_use_error => false,
+ g_use_sync => g_rx_use_fifo,
+ g_fifo_fill => g_rx_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => serial_siso_arr,
+ snk_in_arr => serial_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
index d200c08db4..8e4ea252bf 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
@@ -120,13 +120,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_example_dut is
@@ -203,39 +203,39 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => g_dat_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => g_dat_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
@@ -270,37 +270,37 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_dat_w,
- g_pkt_len => g_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_dat_w,
+ g_pkt_len => g_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT
@@ -318,16 +318,16 @@ begin
-- DUT function
gen_dut : if g_no_dut = false generate
u_dut : entity work.dp_example_dut
- port map (
- rst => rst,
- clk => clk,
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => dut_snk_out,
- snk_in => dut_snk_in,
+ snk_out => dut_snk_out,
+ snk_in => dut_snk_in,
- src_in => dut_src_in,
- src_out => dut_src_out
- );
+ src_in => dut_src_in,
+ src_out => dut_src_out
+ );
end generate;
-- Connect DUT source output stream to verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
index 296ac0eab6..41c2b1e924 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
@@ -111,13 +111,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_example_no_dut is
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
index aa85d51adb..cd62fd3b60 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_dc is
generic (
@@ -200,32 +200,32 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_dc
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_ctrl => g_dut_use_ctrl,
- g_fifo_size => c_dut_fifo_size,
- g_fifo_rl => g_dut_out_latency
- )
- port map (
- wr_rst => rst,
- wr_clk => wr_clk,
- rd_rst => rst,
- rd_clk => rd_clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- wr_usedw => usedw,
- rd_usedw => OPEN,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
index cfce57389f..5fe366868f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -26,11 +26,11 @@
-- Verifies output data and ctrl signals of DUT. This is configurable using generics.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_dc_arr is
generic (
@@ -215,37 +215,37 @@ begin
out_eop <= out_sosi_arr(0).eop;
dut : entity work.dp_fifo_dc_arr
- generic map (
- g_nof_streams => g_dut_nof_streams,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_aux_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_aux => g_dut_use_aux,
- g_use_ctrl => g_dut_use_ctrl,
- g_fifo_size => c_dut_fifo_size,
- g_fifo_rl => g_dut_out_latency
- )
- port map (
- wr_rst => rst,
- wr_clk => wr_clk,
- rd_rst => rst,
- rd_clk => rd_clk,
- snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi_arr,
- in_aux(0) => in_aux,
- wr_usedw => usedw,
- rd_usedw => OPEN,
- src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
- src_out_arr => out_sosi_arr,
- out_aux(0) => out_aux
- );
+ generic map (
+ g_nof_streams => g_dut_nof_streams,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_aux_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_aux => g_dut_use_aux,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ in_aux(0) => in_aux,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
+ src_out_arr => out_sosi_arr,
+ out_aux(0) => out_aux
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
index a3d7ed7ebd..586bf75014 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
-- run 50 us
@@ -196,74 +196,74 @@ begin
-- Narrow to wide FIFO
u_dut_n2w : entity work.dp_fifo_dc_mixed_widths
- generic map (
- g_wr_data_w => g_narrow_w,
- g_rd_data_w => c_wide_w,
- g_use_ctrl => g_use_ctrl,
- g_wr_fifo_size => c_wr_fifo_size,
- g_rd_fifo_rl => g_read_rl
- )
- port map (
- wr_rst => narrow_rst,
- wr_clk => narrow_clk,
- rd_rst => wide_rst,
- rd_clk => wide_clk,
- -- ST sink
- snk_out => in_siso,
- snk_in => in_sosi,
- -- Monitor FIFO filling
- wr_usedw => fifo_n2w_wr_usedw,
- rd_usedw => fifo_n2w_rd_usedw,
- rd_emp => fifo_n2w_rd_emp,
- -- ST source
- src_in => wide_siso,
- src_out => wide_sosi
- );
+ generic map (
+ g_wr_data_w => g_narrow_w,
+ g_rd_data_w => c_wide_w,
+ g_use_ctrl => g_use_ctrl,
+ g_wr_fifo_size => c_wr_fifo_size,
+ g_rd_fifo_rl => g_read_rl
+ )
+ port map (
+ wr_rst => narrow_rst,
+ wr_clk => narrow_clk,
+ rd_rst => wide_rst,
+ rd_clk => wide_clk,
+ -- ST sink
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- Monitor FIFO filling
+ wr_usedw => fifo_n2w_wr_usedw,
+ rd_usedw => fifo_n2w_rd_usedw,
+ rd_emp => fifo_n2w_rd_emp,
+ -- ST source
+ src_in => wide_siso,
+ src_out => wide_sosi
+ );
-- Adapt for wide to narrow FIFO input RL=1 in case g_read_rl=0
u_rl : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_read_rl,
- g_out_latency => c_rl
- )
- port map (
- rst => wide_rst,
- clk => wide_clk,
- -- ST sink
- snk_out => wide_siso,
- snk_in => wide_sosi,
- -- ST source
- src_in => wide_siso_rl1,
- src_out => wide_sosi_rl1
- );
+ generic map (
+ g_in_latency => g_read_rl,
+ g_out_latency => c_rl
+ )
+ port map (
+ rst => wide_rst,
+ clk => wide_clk,
+ -- ST sink
+ snk_out => wide_siso,
+ snk_in => wide_sosi,
+ -- ST source
+ src_in => wide_siso_rl1,
+ src_out => wide_sosi_rl1
+ );
-- Wide to narrow FIFO
u_dut_w2n : entity work.dp_fifo_dc_mixed_widths
- generic map (
- g_wr_data_w => c_wide_w,
- g_rd_data_w => g_narrow_w,
- g_use_ctrl => g_use_ctrl,
- g_wr_fifo_size => c_wr_fifo_size,
- g_rd_fifo_rl => g_read_rl
- )
- port map (
- wr_rst => wide_rst,
- wr_clk => wide_clk,
- rd_rst => narrow_rst,
- rd_clk => narrow_clk,
- -- ST sink
- snk_out => wide_siso_rl1,
- snk_in => wide_sosi_rl1,
- -- Monitor FIFO filling
- wr_usedw => fifo_w2n_wr_usedw,
- rd_usedw => fifo_w2n_rd_usedw,
- rd_emp => fifo_w2n_rd_emp,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_wr_data_w => c_wide_w,
+ g_rd_data_w => g_narrow_w,
+ g_use_ctrl => g_use_ctrl,
+ g_wr_fifo_size => c_wr_fifo_size,
+ g_rd_fifo_rl => g_read_rl
+ )
+ port map (
+ wr_rst => wide_rst,
+ wr_clk => wide_clk,
+ rd_rst => narrow_rst,
+ rd_clk => narrow_clk,
+ -- ST sink
+ snk_out => wide_siso_rl1,
+ snk_in => wide_sosi_rl1,
+ -- Monitor FIFO filling
+ wr_usedw => fifo_w2n_wr_usedw,
+ rd_usedw => fifo_w2n_rd_usedw,
+ rd_emp => fifo_w2n_rd_emp,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
-- 1) Verify intermediate wide data
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
index 2678bf711e..4f7398c323 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
@@ -35,11 +35,11 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill is
generic (
@@ -214,29 +214,29 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- wr_ful => wr_ful,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_ful => wr_ful,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
index b2ce169ff9..89daa75b5a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
@@ -37,12 +37,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill_eop is
generic (
@@ -190,7 +190,7 @@ begin
in_channel <= INCR_UVEC(in_data, c_channel_offset);
-- Stimuli control
- proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
+ proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
gen_random_ctrl : if g_dut_use_random_ctrl generate
proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
end generate;
@@ -269,34 +269,34 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill_eop
- generic map (
- g_use_dual_clock => g_dut_use_dual_clock,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rd_rst => rst,
- rd_clk => clk,
- wr_rst => rst,
- wr_clk => clk,
- wr_ful => wr_ful,
- rd_usedw => rd_usedw,
- rd_fill_32b => rd_fill_32b,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_use_dual_clock => g_dut_use_dual_clock,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rd_rst => rst,
+ rd_clk => clk,
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_ful => wr_ful,
+ rd_usedw => rd_usedw,
+ rd_fill_32b => rd_fill_32b,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
index 4f38f19304..6f6c470251 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
@@ -35,12 +35,12 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill_sc is
generic (
@@ -244,31 +244,31 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill_sc
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- wr_ful => wr_ful,
- usedw => rd_usedw,
- rd_fill_32b => rd_fill_32b,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_ful => wr_ful,
+ usedw => rd_usedw,
+ rd_fill_32b => rd_fill_32b,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
index 2b872e5856..4d619b2ea0 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_info is
generic (
@@ -193,51 +193,51 @@ begin
-- Stimuli data delay
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_data_delay
- )
- port map (
- rst => rst,
- clk =>