From ee6648975628b40f1a404f1f63f96a43bd3a43d3 Mon Sep 17 00:00:00 2001 From: Eric Kooistra <kooistra@astron.nl> Date: Wed, 16 Nov 2022 16:17:08 +0100 Subject: [PATCH] Register cnt_en to avoid combinational loop. --- .../dp/src/vhdl/dp_strobe_total_count.vhd | 31 +++++++++++++------ 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd index 2a08ade625..730c83b37f 100644 --- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd +++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd @@ -113,15 +113,15 @@ ARCHITECTURE rtl OF dp_strobe_total_count IS TYPE t_cnt_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_count_w-1 DOWNTO 0); -- Registers in dp_clk domain - SIGNAL ref_sync_reg : STD_LOGIC := '0'; - SIGNAL in_strobe_reg_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0'); - SIGNAL rd_reg : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); - SIGNAL mm_cnt_clr : STD_LOGIC; - SIGNAL cnt_clr : STD_LOGIC; - SIGNAL cnt_en : STD_LOGIC := '0'; - SIGNAL cnt_en_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0); - SIGNAL cnt_arr : t_cnt_arr(g_nof_counts-1 DOWNTO 0); - SIGNAL hold_cnt_arr : t_cnt_arr(g_nof_counts-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0')); + SIGNAL ref_sync_reg : STD_LOGIC := '0'; + SIGNAL in_strobe_reg_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0'); + SIGNAL rd_reg : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + SIGNAL mm_cnt_clr : STD_LOGIC; + SIGNAL cnt_clr : STD_LOGIC; + SIGNAL cnt_en : STD_LOGIC := '0'; + SIGNAL cnt_en_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0); + SIGNAL cnt_arr : t_cnt_arr(g_nof_counts-1 DOWNTO 0); + SIGNAL hold_cnt_arr : t_cnt_arr(g_nof_counts-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0')); BEGIN @@ -149,7 +149,18 @@ BEGIN -- . clear strobe counters immediately at cnt_clr -- . start strobe counters after ref_sync, e.g. to align strobe counters in different nodes in -- case the input was (already) active during the cnt_clr - cnt_en <= '0' WHEN cnt_clr = '1' ELSE '1' WHEN ref_sync_reg = '1' ELSE cnt_en; + p_cnt_en : PROCESS(dp_rst, dp_clk) + BEGIN + IF dp_rst = '1' THEN + cnt_en <= '0'; + ELSIF rising_edge(dp_clk) THEN + IF cnt_clr = '1' THEN + cnt_en <= '0'; + ELSIF ref_sync = '1' THEN -- use ref_sync have cnt_en aligned with ref_sync_reg + cnt_en <= '1'; + END IF; + END IF; + END PROCESS; -- strobe counters gen_counters : FOR I IN 0 TO g_nof_counts-1 GENERATE -- GitLab