diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..87c0b0f7ef2fcca0f763c79bcc2638e713407e21 --- /dev/null +++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg @@ -0,0 +1,67 @@ +hdl_lib_name = unb2b_minimal_125m +hdl_library_clause_name = unb2b_minimal_125m_lib +hdl_lib_uses_synth = common mm technology unb2b_minimal +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg +hdl_lib_include_ip = + +synth_files = + unb2b_minimal_125m.vhd + +test_bench_files = + + +[modelsim_project_file] +modelsim_copy_files = + + +[quartus_project_file] +synth_top_level_entity = + +quartus_copy_files = + ../../quartus . + +quartus_qsf_files = + $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf + +quartus_sdc_pre_files = + quartus/unb2b_test_10GbE.sdc + $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc + +quartus_sdc_files = + $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc + +quartus_tcl_files = + ../../quartus/unb2b_minimal_pins.tcl + +quartus_vhdl_files = + +quartus_qip_files = + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal_125m/qsys_unb2b_minimal/qsys_unb2b_minimal.qip + +quartus_ip_files = + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip + +nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2 + diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd new file mode 100644 index 0000000000000000000000000000000000000000..0e4de21d22dbe759991389097aed876dfbc47c5d --- /dev/null +++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd @@ -0,0 +1,122 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_minimal_lib, technology_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE technology_lib.technology_pkg.ALL; + + +ENTITY unb2b_minimal_125m IS + GENERIC ( + g_design_name : STRING := "unb2b_minimal_125m"; + g_design_note : STRING := "UNUSED"; + g_technology : NATURAL := c_tech_arria10_e1sg; + g_sim : BOOLEAN := FALSE; --Overridden by TB + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF + g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF + g_revision_id : STRING := ""; -- revision id -- set by QSF + g_factory_image : BOOLEAN := TRUE; + g_protect_addr_range: BOOLEAN := FALSE + ); + PORT ( + -- GENERAL + CLK : IN STD_LOGIC; -- System Clock + PPS : IN STD_LOGIC; -- System Sync + WDI : OUT STD_LOGIC; -- Watchdog Clear + INTA : INOUT STD_LOGIC; -- FPGA interconnect line + INTB : INOUT STD_LOGIC; -- FPGA interconnect line + + -- Others + VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0); + ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0); + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0); + + -- I2C Interface to Sensors + SENS_SC : INOUT STD_LOGIC; + SENS_SD : INOUT STD_LOGIC; + + PMBUS_SC : INOUT STD_LOGIC; + PMBUS_SD : INOUT STD_LOGIC; + PMBUS_ALERT : IN STD_LOGIC := '0'; + + -- 1GbE Control Interface + ETH_CLK : IN STD_LOGIC; + ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + + QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0) + ); +END unb2b_minimal_125m; + + +ARCHITECTURE str OF unb2b_minimal_125m IS + +BEGIN + u_revision : ENTITY unb2b_minimal_lib.unb2b_minimal + GENERIC MAP ( + g_design_name => g_design_name, + g_design_note => g_design_note, + g_technology => g_technology, + g_sim => g_sim, + g_sim_unb_nr => g_sim_unb_nr, + g_sim_node_nr => g_sim_node_nr, + g_stamp_date => g_stamp_date, + g_stamp_time => g_stamp_time, + g_revision_id => g_revision_id, + g_factory_image => g_factory_image, + g_protect_addr_range => g_protect_addr_range + ) + PORT MAP ( + -- GENERAL + CLK => CLK, + PPS => PPS, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + -- Others + VERSION => VERSION, + ID => ID, + TESTIO => TESTIO, + + -- I2C Interface to Sensors + SENS_SC => SENS_SC, + SENS_SD => SENS_SD, + + -- 1GbE Control Interface + ETH_clk => ETH_clk, + ETH_SGIN => ETH_SGIN, + ETH_SGOUT => ETH_SGOUT, + + -- pmbus + PMBUS_SC => PMBUS_SC, + PMBUS_SD => PMBUS_SD, + PMBUS_ALERT => PMBUS_ALERT, + + QSFP_LED => QSFP_LED + ); +END str; diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd index c3ec18ff881ecf5685ec6422f3ab6a90eb93608f..bd5005bfe3983d9ca9962771c61455d836b51ff4 100644 --- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd +++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd @@ -1,392 +1,393 @@ -------------------------------------------------------------------------------- --- --- Copyright (C) 2015 --- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> --- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> --- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see <http://www.gnu.org/licenses/>. --- -------------------------------------------------------------------------------- - -LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE common_lib.common_pkg.ALL; -USE common_lib.common_mem_pkg.ALL; -USE technology_lib.technology_pkg.ALL; -USE unb2b_board_lib.unb2b_board_pkg.ALL; - -ENTITY unb2b_minimal IS - GENERIC ( - g_design_name : STRING := "unb2b_minimal"; - g_design_note : STRING := "UNUSED"; - g_technology : NATURAL := c_tech_arria10_e1sg; - g_sim : BOOLEAN := FALSE; --Overridden by TB - g_sim_unb_nr : NATURAL := 0; - g_sim_node_nr : NATURAL := 0; - g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF - g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF - g_revision_id : STRING := ""; -- revision id -- set by QSF - g_factory_image : BOOLEAN := TRUE; - g_protect_addr_range: BOOLEAN := FALSE - ); - PORT ( - -- GENERAL - CLK : IN STD_LOGIC; -- System Clock - PPS : IN STD_LOGIC; -- System Sync - WDI : OUT STD_LOGIC; -- Watchdog Clear - INTA : INOUT STD_LOGIC; -- FPGA interconnect line - INTB : INOUT STD_LOGIC; -- FPGA interconnect line - - -- Others - VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0); - ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0); - TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0); - - -- I2C Interface to Sensors - SENS_SC : INOUT STD_LOGIC; - SENS_SD : INOUT STD_LOGIC; - - PMBUS_SC : INOUT STD_LOGIC; - PMBUS_SD : INOUT STD_LOGIC; - PMBUS_ALERT : IN STD_LOGIC := '0'; - - -- 1GbE Control Interface - ETH_CLK : IN STD_LOGIC; - ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); - ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); - - QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0) - ); -END unb2b_minimal; - - -ARCHITECTURE str OF unb2b_minimal IS - - -- Firmware version x.y - CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1); - CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_50M; - - -- System - SIGNAL cs_sim : STD_LOGIC; - SIGNAL xo_ethclk : STD_LOGIC; - SIGNAL xo_rst : STD_LOGIC; - SIGNAL xo_rst_n : STD_LOGIC; - SIGNAL mm_clk : STD_LOGIC; - SIGNAL mm_rst : STD_LOGIC; - - SIGNAL st_rst : STD_LOGIC; - SIGNAL st_clk : STD_LOGIC; - - -- PIOs - SIGNAL pout_wdi : STD_LOGIC; - - -- WDI override - SIGNAL reg_wdi_mosi : t_mem_mosi; - SIGNAL reg_wdi_miso : t_mem_miso; - - -- PPSH - SIGNAL reg_ppsh_mosi : t_mem_mosi; - SIGNAL reg_ppsh_miso : t_mem_miso; - - -- UniBoard system info - SIGNAL reg_unb_system_info_mosi : t_mem_mosi; - SIGNAL reg_unb_system_info_miso : t_mem_miso; - SIGNAL rom_unb_system_info_mosi : t_mem_mosi; - SIGNAL rom_unb_system_info_miso : t_mem_miso; - - -- UniBoard I2C sens - SIGNAL reg_unb_sens_mosi : t_mem_mosi; - SIGNAL reg_unb_sens_miso : t_mem_miso; - - -- pm bus - SIGNAL reg_unb_pmbus_mosi : t_mem_mosi; - SIGNAL reg_unb_pmbus_miso : t_mem_miso; - - -- FPGA sensors - SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi; - SIGNAL reg_fpga_temp_sens_miso : t_mem_miso; - SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi; - SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso; - - -- eth1g - SIGNAL eth1g_mm_rst : STD_LOGIC; - SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers - SIGNAL eth1g_tse_miso : t_mem_miso; - SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers - SIGNAL eth1g_reg_miso : t_mem_miso; - SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt - SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory - SIGNAL eth1g_ram_miso : t_mem_miso; - - -- EPCS read - SIGNAL reg_dpmm_data_mosi : t_mem_mosi; - SIGNAL reg_dpmm_data_miso : t_mem_miso; - SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi; - SIGNAL reg_dpmm_ctrl_miso : t_mem_miso; - - -- EPCS write - SIGNAL reg_mmdp_data_mosi : t_mem_mosi; - SIGNAL reg_mmdp_data_miso : t_mem_miso; - SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi; - SIGNAL reg_mmdp_ctrl_miso : t_mem_miso; - - -- EPCS status/control - SIGNAL reg_epcs_mosi : t_mem_mosi; - SIGNAL reg_epcs_miso : t_mem_miso; - - -- Remote Update - SIGNAL reg_remu_mosi : t_mem_mosi; - SIGNAL reg_remu_miso : t_mem_miso; - - -- Scrap RAM - SIGNAL ram_scrap_mosi : t_mem_mosi; - SIGNAL ram_scrap_miso : t_mem_miso; - - -- QSFP leds - SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); - SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------------- - -- General control function - ----------------------------------------------------------------------------- - u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board - GENERIC MAP ( - g_sim => g_sim, - g_technology => g_technology, - g_design_name => g_design_name, - g_design_note => g_design_note, - g_stamp_date => g_stamp_date, - g_stamp_time => g_stamp_time, - g_revision_id => g_revision_id, - g_fw_version => c_fw_version, - g_mm_clk_freq => c_mm_clk_freq, - g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M, - g_aux => c_unb2b_board_aux, - g_factory_image => g_factory_image, - g_protect_addr_range => g_protect_addr_range - ) - PORT MAP ( - -- Clock an reset signals - cs_sim => cs_sim, - xo_ethclk => xo_ethclk, - xo_rst => xo_rst, - xo_rst_n => xo_rst_n, - - mm_clk => mm_clk, - mm_rst => mm_rst, - - dp_rst => st_rst, - dp_clk => st_clk, - dp_pps => OPEN, - dp_rst_in => st_rst, - dp_clk_in => st_clk, - - -- Toggle WDI - pout_wdi => pout_wdi, - - -- MM buses - -- REMU - reg_remu_mosi => reg_remu_mosi, - reg_remu_miso => reg_remu_miso, - - -- EPCS read - reg_dpmm_data_mosi => reg_dpmm_data_mosi, - reg_dpmm_data_miso => reg_dpmm_data_miso, - reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi, - reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso, - - -- EPCS write - reg_mmdp_data_mosi => reg_mmdp_data_mosi, - reg_mmdp_data_miso => reg_mmdp_data_miso, - reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi, - reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso, - - -- EPCS status/control - reg_epcs_mosi => reg_epcs_mosi, - reg_epcs_miso => reg_epcs_miso, - - -- . Manual WDI override - reg_wdi_mosi => reg_wdi_mosi, - reg_wdi_miso => reg_wdi_miso, - - -- . System_info - reg_unb_system_info_mosi => reg_unb_system_info_mosi, - reg_unb_system_info_miso => reg_unb_system_info_miso, - rom_unb_system_info_mosi => rom_unb_system_info_mosi, - rom_unb_system_info_miso => rom_unb_system_info_miso, - - -- . UniBoard I2C sensors - reg_unb_sens_mosi => reg_unb_sens_mosi, - reg_unb_sens_miso => reg_unb_sens_miso, - - -- . FPGA sensors - reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi, - reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso, - reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi, - reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso, - - reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, - reg_unb_pmbus_miso => reg_unb_pmbus_miso, - - -- . PPSH - reg_ppsh_mosi => reg_ppsh_mosi, - reg_ppsh_miso => reg_ppsh_miso, - - -- eth1g - eth1g_mm_rst => eth1g_mm_rst, - eth1g_tse_mosi => eth1g_tse_mosi, - eth1g_tse_miso => eth1g_tse_miso, - eth1g_reg_mosi => eth1g_reg_mosi, - eth1g_reg_miso => eth1g_reg_miso, - eth1g_reg_interrupt => eth1g_reg_interrupt, - eth1g_ram_mosi => eth1g_ram_mosi, - eth1g_ram_miso => eth1g_ram_miso, - - -- scrap ram - ram_scrap_mosi => ram_scrap_mosi, - ram_scrap_miso => ram_scrap_miso, - - -- FPGA pins - -- . General - CLK => CLK, - PPS => PPS, - WDI => WDI, - INTA => INTA, - INTB => INTB, - -- . Others - VERSION => VERSION, - ID => ID, - TESTIO => TESTIO, - -- . I2C Interface to Sensors - SENS_SC => SENS_SC, - SENS_SD => SENS_SD, - -- PM bus - PMBUS_SC => PMBUS_SC, - PMBUS_SD => PMBUS_SD, - PMBUS_ALERT => PMBUS_ALERT, - - -- . 1GbE Control Interface - ETH_clk => ETH_CLK, - ETH_SGIN => ETH_SGIN, - ETH_SGOUT => ETH_SGOUT - ); - - ----------------------------------------------------------------------------- - -- MM master - ----------------------------------------------------------------------------- - u_mmm : ENTITY work.mmm_unb2b_minimal - GENERIC MAP ( - g_sim => g_sim, - g_sim_unb_nr => g_sim_unb_nr, - g_sim_node_nr => g_sim_node_nr - ) - PORT MAP( - mm_rst => mm_rst, - mm_clk => mm_clk, - - -- PIOs - pout_wdi => pout_wdi, - - -- Manual WDI override - reg_wdi_mosi => reg_wdi_mosi, - reg_wdi_miso => reg_wdi_miso, - - -- system_info - reg_unb_system_info_mosi => reg_unb_system_info_mosi, - reg_unb_system_info_miso => reg_unb_system_info_miso, - rom_unb_system_info_mosi => rom_unb_system_info_mosi, - rom_unb_system_info_miso => rom_unb_system_info_miso, - - -- UniBoard I2C sensors - reg_unb_sens_mosi => reg_unb_sens_mosi, - reg_unb_sens_miso => reg_unb_sens_miso, - - reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, - reg_unb_pmbus_miso => reg_unb_pmbus_miso, - - -- FPGA sensors - reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi, - reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso, - reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi, - reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso, - - -- PPSH - reg_ppsh_mosi => reg_ppsh_mosi, - reg_ppsh_miso => reg_ppsh_miso, - - -- eth1g - eth1g_mm_rst => eth1g_mm_rst, - eth1g_tse_mosi => eth1g_tse_mosi, - eth1g_tse_miso => eth1g_tse_miso, - eth1g_reg_mosi => eth1g_reg_mosi, - eth1g_reg_miso => eth1g_reg_miso, - eth1g_reg_interrupt => eth1g_reg_interrupt, - eth1g_ram_mosi => eth1g_ram_mosi, - eth1g_ram_miso => eth1g_ram_miso, - - -- EPCS read - reg_dpmm_data_mosi => reg_dpmm_data_mosi, - reg_dpmm_data_miso => reg_dpmm_data_miso, - reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi, - reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso, - - -- EPCS write - reg_mmdp_data_mosi => reg_mmdp_data_mosi, - reg_mmdp_data_miso => reg_mmdp_data_miso, - reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi, - reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso, - - -- EPCS status/control - reg_epcs_mosi => reg_epcs_mosi, - reg_epcs_miso => reg_epcs_miso, - - -- Remote Update - reg_remu_mosi => reg_remu_mosi, - reg_remu_miso => reg_remu_miso, - - -- Scrap RAM - ram_scrap_mosi => ram_scrap_mosi, - ram_scrap_miso => ram_scrap_miso - ); - - u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds - GENERIC MAP ( - g_sim => g_sim, - g_factory_image => g_factory_image, - g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus, - g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period - ) - PORT MAP ( - rst => mm_rst, - clk => mm_clk, - green_led_arr => qsfp_green_led_arr, - red_led_arr => qsfp_red_led_arr - ); - - u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io - GENERIC MAP ( - g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus - ) - PORT MAP ( - green_led_arr => qsfp_green_led_arr, - red_led_arr => qsfp_red_led_arr, - QSFP_LED => QSFP_LED - ); - -END str; - +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; + +ENTITY unb2b_minimal IS + GENERIC ( + g_design_name : STRING := "unb2b_minimal"; + g_design_note : STRING := "UNUSED"; + g_technology : NATURAL := c_tech_arria10_e1sg; + g_sim : BOOLEAN := FALSE; --Overridden by TB + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF + g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF + g_revision_id : STRING := ""; -- revision id -- set by QSF + g_factory_image : BOOLEAN := TRUE; + g_protect_addr_range: BOOLEAN := FALSE + ); + PORT ( + -- GENERAL + CLK : IN STD_LOGIC; -- System Clock + PPS : IN STD_LOGIC; -- System Sync + WDI : OUT STD_LOGIC; -- Watchdog Clear + INTA : INOUT STD_LOGIC; -- FPGA interconnect line + INTB : INOUT STD_LOGIC; -- FPGA interconnect line + + -- Others + VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0); + ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0); + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0); + + -- I2C Interface to Sensors + SENS_SC : INOUT STD_LOGIC; + SENS_SD : INOUT STD_LOGIC; + + PMBUS_SC : INOUT STD_LOGIC; + PMBUS_SD : INOUT STD_LOGIC; + PMBUS_ALERT : IN STD_LOGIC := '0'; + + -- 1GbE Control Interface + ETH_CLK : IN STD_LOGIC; + ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + + QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0) + ); +END unb2b_minimal; + + +ARCHITECTURE str OF unb2b_minimal IS + + -- Firmware version x.y + CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1); + CONSTANT c_use_125m : BOOLEAN := g_design_name="unb2b_minimal_125m"; + CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(c_use_125m, c_unb2b_board_mm_clk_freq_125M, c_unb2b_board_mm_clk_freq_50M); + + -- System + SIGNAL cs_sim : STD_LOGIC; + SIGNAL xo_ethclk : STD_LOGIC; + SIGNAL xo_rst : STD_LOGIC; + SIGNAL xo_rst_n : STD_LOGIC; + SIGNAL mm_clk : STD_LOGIC; + SIGNAL mm_rst : STD_LOGIC; + + SIGNAL st_rst : STD_LOGIC; + SIGNAL st_clk : STD_LOGIC; + + -- PIOs + SIGNAL pout_wdi : STD_LOGIC; + + -- WDI override + SIGNAL reg_wdi_mosi : t_mem_mosi; + SIGNAL reg_wdi_miso : t_mem_miso; + + -- PPSH + SIGNAL reg_ppsh_mosi : t_mem_mosi; + SIGNAL reg_ppsh_miso : t_mem_miso; + + -- UniBoard system info + SIGNAL reg_unb_system_info_mosi : t_mem_mosi; + SIGNAL reg_unb_system_info_miso : t_mem_miso; + SIGNAL rom_unb_system_info_mosi : t_mem_mosi; + SIGNAL rom_unb_system_info_miso : t_mem_miso; + + -- UniBoard I2C sens + SIGNAL reg_unb_sens_mosi : t_mem_mosi; + SIGNAL reg_unb_sens_miso : t_mem_miso; + + -- pm bus + SIGNAL reg_unb_pmbus_mosi : t_mem_mosi; + SIGNAL reg_unb_pmbus_miso : t_mem_miso; + + -- FPGA sensors + SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi; + SIGNAL reg_fpga_temp_sens_miso : t_mem_miso; + SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi; + SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso; + + -- eth1g + SIGNAL eth1g_mm_rst : STD_LOGIC; + SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers + SIGNAL eth1g_tse_miso : t_mem_miso; + SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers + SIGNAL eth1g_reg_miso : t_mem_miso; + SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt + SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory + SIGNAL eth1g_ram_miso : t_mem_miso; + + -- EPCS read + SIGNAL reg_dpmm_data_mosi : t_mem_mosi; + SIGNAL reg_dpmm_data_miso : t_mem_miso; + SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi; + SIGNAL reg_dpmm_ctrl_miso : t_mem_miso; + + -- EPCS write + SIGNAL reg_mmdp_data_mosi : t_mem_mosi; + SIGNAL reg_mmdp_data_miso : t_mem_miso; + SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi; + SIGNAL reg_mmdp_ctrl_miso : t_mem_miso; + + -- EPCS status/control + SIGNAL reg_epcs_mosi : t_mem_mosi; + SIGNAL reg_epcs_miso : t_mem_miso; + + -- Remote Update + SIGNAL reg_remu_mosi : t_mem_mosi; + SIGNAL reg_remu_miso : t_mem_miso; + + -- Scrap RAM + SIGNAL ram_scrap_mosi : t_mem_mosi; + SIGNAL ram_scrap_miso : t_mem_miso; + + -- QSFP leds + SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); + SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- General control function + ----------------------------------------------------------------------------- + u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board + GENERIC MAP ( + g_sim => g_sim, + g_technology => g_technology, + g_design_name => g_design_name, + g_design_note => g_design_note, + g_stamp_date => g_stamp_date, + g_stamp_time => g_stamp_time, + g_revision_id => g_revision_id, + g_fw_version => c_fw_version, + g_mm_clk_freq => c_mm_clk_freq, + g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M, + g_aux => c_unb2b_board_aux, + g_factory_image => g_factory_image, + g_protect_addr_range => g_protect_addr_range + ) + PORT MAP ( + -- Clock an reset signals + cs_sim => cs_sim, + xo_ethclk => xo_ethclk, + xo_rst => xo_rst, + xo_rst_n => xo_rst_n, + + mm_clk => mm_clk, + mm_rst => mm_rst, + + dp_rst => st_rst, + dp_clk => st_clk, + dp_pps => OPEN, + dp_rst_in => st_rst, + dp_clk_in => st_clk, + + -- Toggle WDI + pout_wdi => pout_wdi, + + -- MM buses + -- REMU + reg_remu_mosi => reg_remu_mosi, + reg_remu_miso => reg_remu_miso, + + -- EPCS read + reg_dpmm_data_mosi => reg_dpmm_data_mosi, + reg_dpmm_data_miso => reg_dpmm_data_miso, + reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi, + reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso, + + -- EPCS write + reg_mmdp_data_mosi => reg_mmdp_data_mosi, + reg_mmdp_data_miso => reg_mmdp_data_miso, + reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi, + reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso, + + -- EPCS status/control + reg_epcs_mosi => reg_epcs_mosi, + reg_epcs_miso => reg_epcs_miso, + + -- . Manual WDI override + reg_wdi_mosi => reg_wdi_mosi, + reg_wdi_miso => reg_wdi_miso, + + -- . System_info + reg_unb_system_info_mosi => reg_unb_system_info_mosi, + reg_unb_system_info_miso => reg_unb_system_info_miso, + rom_unb_system_info_mosi => rom_unb_system_info_mosi, + rom_unb_system_info_miso => rom_unb_system_info_miso, + + -- . UniBoard I2C sensors + reg_unb_sens_mosi => reg_unb_sens_mosi, + reg_unb_sens_miso => reg_unb_sens_miso, + + -- . FPGA sensors + reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi, + reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso, + reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi, + reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso, + + reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, + reg_unb_pmbus_miso => reg_unb_pmbus_miso, + + -- . PPSH + reg_ppsh_mosi => reg_ppsh_mosi, + reg_ppsh_miso => reg_ppsh_miso, + + -- eth1g + eth1g_mm_rst => eth1g_mm_rst, + eth1g_tse_mosi => eth1g_tse_mosi, + eth1g_tse_miso => eth1g_tse_miso, + eth1g_reg_mosi => eth1g_reg_mosi, + eth1g_reg_miso => eth1g_reg_miso, + eth1g_reg_interrupt => eth1g_reg_interrupt, + eth1g_ram_mosi => eth1g_ram_mosi, + eth1g_ram_miso => eth1g_ram_miso, + + -- scrap ram + ram_scrap_mosi => ram_scrap_mosi, + ram_scrap_miso => ram_scrap_miso, + + -- FPGA pins + -- . General + CLK => CLK, + PPS => PPS, + WDI => WDI, + INTA => INTA, + INTB => INTB, + -- . Others + VERSION => VERSION, + ID => ID, + TESTIO => TESTIO, + -- . I2C Interface to Sensors + SENS_SC => SENS_SC, + SENS_SD => SENS_SD, + -- PM bus + PMBUS_SC => PMBUS_SC, + PMBUS_SD => PMBUS_SD, + PMBUS_ALERT => PMBUS_ALERT, + + -- . 1GbE Control Interface + ETH_clk => ETH_CLK, + ETH_SGIN => ETH_SGIN, + ETH_SGOUT => ETH_SGOUT + ); + + ----------------------------------------------------------------------------- + -- MM master + ----------------------------------------------------------------------------- + u_mmm : ENTITY work.mmm_unb2b_minimal + GENERIC MAP ( + g_sim => g_sim, + g_sim_unb_nr => g_sim_unb_nr, + g_sim_node_nr => g_sim_node_nr + ) + PORT MAP( + mm_rst => mm_rst, + mm_clk => mm_clk, + + -- PIOs + pout_wdi => pout_wdi, + + -- Manual WDI override + reg_wdi_mosi => reg_wdi_mosi, + reg_wdi_miso => reg_wdi_miso, + + -- system_info + reg_unb_system_info_mosi => reg_unb_system_info_mosi, + reg_unb_system_info_miso => reg_unb_system_info_miso, + rom_unb_system_info_mosi => rom_unb_system_info_mosi, + rom_unb_system_info_miso => rom_unb_system_info_miso, + + -- UniBoard I2C sensors + reg_unb_sens_mosi => reg_unb_sens_mosi, + reg_unb_sens_miso => reg_unb_sens_miso, + + reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, + reg_unb_pmbus_miso => reg_unb_pmbus_miso, + + -- FPGA sensors + reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi, + reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso, + reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi, + reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso, + + -- PPSH + reg_ppsh_mosi => reg_ppsh_mosi, + reg_ppsh_miso => reg_ppsh_miso, + + -- eth1g + eth1g_mm_rst => eth1g_mm_rst, + eth1g_tse_mosi => eth1g_tse_mosi, + eth1g_tse_miso => eth1g_tse_miso, + eth1g_reg_mosi => eth1g_reg_mosi, + eth1g_reg_miso => eth1g_reg_miso, + eth1g_reg_interrupt => eth1g_reg_interrupt, + eth1g_ram_mosi => eth1g_ram_mosi, + eth1g_ram_miso => eth1g_ram_miso, + + -- EPCS read + reg_dpmm_data_mosi => reg_dpmm_data_mosi, + reg_dpmm_data_miso => reg_dpmm_data_miso, + reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi, + reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso, + + -- EPCS write + reg_mmdp_data_mosi => reg_mmdp_data_mosi, + reg_mmdp_data_miso => reg_mmdp_data_miso, + reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi, + reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso, + + -- EPCS status/control + reg_epcs_mosi => reg_epcs_mosi, + reg_epcs_miso => reg_epcs_miso, + + -- Remote Update + reg_remu_mosi => reg_remu_mosi, + reg_remu_miso => reg_remu_miso, + + -- Scrap RAM + ram_scrap_mosi => ram_scrap_mosi, + ram_scrap_miso => ram_scrap_miso + ); + + u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds + GENERIC MAP ( + g_sim => g_sim, + g_factory_image => g_factory_image, + g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus, + g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period + ) + PORT MAP ( + rst => mm_rst, + clk => mm_clk, + green_led_arr => qsfp_green_led_arr, + red_led_arr => qsfp_red_led_arr + ); + + u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io + GENERIC MAP ( + g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus + ) + PORT MAP ( + green_led_arr => qsfp_green_led_arr, + red_led_arr => qsfp_red_led_arr, + QSFP_LED => QSFP_LED + ); + +END str; +