diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index 466402977456e901e901f5242903aca817c99e95..f99a130b80b589f0a82b7120404d6c8267d09205 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -156,7 +156,7 @@ ARCHITECTURE rtl OF st_histogram IS
   -------------------------------------------------------------------------------
   -- 2x RAM (common_ram_r_w) instances
   -------------------------------------------------------------------------------
-  CONSTANT c_nof_common_ram_r_w     : NATURAL := 2;
+  CONSTANT c_nof_ram_pages     : NATURAL := 2;
 
   CONSTANT c_ram                    : t_c_mem := (latency  => 1,
                                                   adr_w    => c_ram_adr_w, 
@@ -351,7 +351,7 @@ BEGIN
   bin_arbiter_rd_miso  <= common_ram_r_w_rd_miso_arr(0) WHEN prv_bin_arbiter_rd_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(1);
   histogram_rd_miso    <= common_ram_r_w_rd_miso_arr(1) WHEN prv_bin_arbiter_rd_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(0);
 
-  gen_common_ram_r_w : FOR i IN 0 TO c_nof_common_ram_r_w-1 GENERATE
+  gen_common_ram_r_w : FOR i IN 0 TO c_nof_ram_pages-1 GENERATE
     u_common_ram_r_w : ENTITY common_lib.common_ram_r_w
     GENERIC MAP (
       g_technology     => c_tech_select_default,