diff --git a/libraries/technology/ip_stratixiv/hdllib.cfg b/libraries/technology/ip_stratixiv/hdllib.cfg
index 8f242deb87a263a854c98e7235d6755c4088f701..d9ec4755c68f8736bbd7fa65bd1bf5399f981348 100644
--- a/libraries/technology/ip_stratixiv/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/hdllib.cfg
@@ -35,7 +35,7 @@ synth_files =
ip_stratixiv_gxb_reconfig_v101.vhd
ip_stratixiv_gxb_reconfig_v111_4.vhd
- ip_stratixiv_gxb_reconfig_v111_soft_4.vhd
+ ip_stratixiv_gxb_reconfig_v111_16.vhd
ip_stratixiv_gxb_reconfig_v111.vhd
ip_stratixiv_hssi_gx_32b_generic.vhd
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111.vhd
index 24d4842582c6647e4698741132733c051a6d932c..4819fb0e7bf37e182dd277e79da58f14a1a21902 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111.vhd
@@ -56,8 +56,8 @@ BEGIN
);
END GENERATE;
- gen_gxb_reconfig_soft_4 : IF g_nof_gx <= 4 AND g_soft = TRUE GENERATE
- u_gxb_reconfig_soft_4 : ENTITY work.ip_stratixiv_gxb_reconfig_v111_soft_4
+ gen_gxb_reconfig_16 : IF g_nof_gx > 12 AND g_nof_gx <= 16 AND g_soft = TRUE GENERATE
+ u_gxb_reconfig_16 : ENTITY work.ip_stratixiv_gxb_reconfig_v111_16
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
diff --git a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111_soft_4.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111_16.vhd
similarity index 97%
rename from libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111_soft_4.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111_16.vhd
index 230e746213d16581a71db58c16e8a2cca1dd7fae..36ff8e8f0802e2e86c26dfdaf16aef0c23bf9938 100644
--- a/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111_soft_4.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_v111_16.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_stratixiv_gxb_reconfig_v111_soft_4.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_v111_16.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_v111_soft_4_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_v111_16_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_stratixiv_gxb_reconfig_v111_soft_4_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_v111_16_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_soft_4_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_16_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state226w230w231w(0) OR (wire_pre_amble_cmpr_w_lg_agb227w(0) AND wire_dprio_w_lg_wr_addr_state226w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state341w342w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb227w339w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state406w407w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb227w404w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_stratixiv_gxb_reconfig_v111_soft_4_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_v111_16_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=4 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_v111_soft_4_mux_76a IS
+ ENTITY ip_stratixiv_gxb_reconfig_v111_16_mux_76a IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0')
);
- END ip_stratixiv_gxb_reconfig_v111_soft_4_mux_76a;
+ END ip_stratixiv_gxb_reconfig_v111_16_mux_76a;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_soft_4_mux_76a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_16_mux_76a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL wire_l1_w0_n1_mux_dataout : STD_LOGIC;
@@ -1263,7 +1263,7 @@
wire_l1_w0_n1_mux_dataout <= data_wire(3) WHEN sel_wire(0) = '1' ELSE data_wire(2);
wire_l2_w0_n0_mux_dataout <= data_wire(5) WHEN sel_wire(3) = '1' ELSE data_wire(4);
- END RTL; --ip_stratixiv_gxb_reconfig_v111_soft_4_mux_76a
+ END RTL; --ip_stratixiv_gxb_reconfig_v111_16_mux_76a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1272,7 +1272,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_stratixiv_gxb_reconfig_v111_soft_4_alt2gxb_reconfig_9im IS
+ ENTITY ip_stratixiv_gxb_reconfig_v111_16_alt2gxb_reconfig_9im IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1280,9 +1280,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (67 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_stratixiv_gxb_reconfig_v111_soft_4_alt2gxb_reconfig_9im;
+ END ip_stratixiv_gxb_reconfig_v111_16_alt2gxb_reconfig_9im;
- ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_soft_4_alt2gxb_reconfig_9im IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_16_alt2gxb_reconfig_9im IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1363,7 +1363,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_v111_soft_4_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_v111_16_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1382,7 +1382,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_stratixiv_gxb_reconfig_v111_soft_4_mux_76a
+ COMPONENT ip_stratixiv_gxb_reconfig_v111_16_mux_76a
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
@@ -1441,7 +1441,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_stratixiv_gxb_reconfig_v111_soft_4_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_v111_16_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1464,21 +1464,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_stratixiv_gxb_reconfig_v111_soft_4_mux_76a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_v111_16_mux_76a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(1 DOWNTO 0)
);
- END RTL; --ip_stratixiv_gxb_reconfig_v111_soft_4_alt2gxb_reconfig_9im
+ END RTL; --ip_stratixiv_gxb_reconfig_v111_16_alt2gxb_reconfig_9im
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_stratixiv_gxb_reconfig_v111_soft_4 IS
+ENTITY ip_stratixiv_gxb_reconfig_v111_16 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1486,10 +1486,10 @@ ENTITY ip_stratixiv_gxb_reconfig_v111_soft_4 IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_stratixiv_gxb_reconfig_v111_soft_4;
+END ip_stratixiv_gxb_reconfig_v111_16;
-ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_soft_4 IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_16 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1502,7 +1502,7 @@ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_v111_soft_4 IS
- COMPONENT ip_stratixiv_gxb_reconfig_v111_soft_4_alt2gxb_reconfig_9im
+ COMPONENT ip_stratixiv_gxb_reconfig_v111_16_alt2gxb_reconfig_9im
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1515,7 +1515,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_stratixiv_gxb_reconfig_v111_soft_4_alt2gxb_reconfig_9im_component : ip_stratixiv_gxb_reconfig_v111_soft_4_alt2gxb_reconfig_9im
+ ip_stratixiv_gxb_reconfig_v111_16_alt2gxb_reconfig_9im_component : ip_stratixiv_gxb_reconfig_v111_16_alt2gxb_reconfig_9im
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1552,10 +1552,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 68 0 reconfig_fromgxb 0 0 68 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_soft_4.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_soft_4.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_soft_4.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_soft_4.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_soft_4_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_16.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_16.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_16.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_16.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_v111_16_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm