From edb2c90e3097b7890bb8dc013739083f1fea985c Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 25 Jun 2015 11:44:59 +0000
Subject: [PATCH] Removed clock domain crossing logic for this control
register, because that is done by io_ddr_cross_domain.vhd in io_ddr.vhd.
Removed cal_fail and cal_ok, because these are already available via the
io_ddr status register.
---
libraries/io/ddr/src/vhdl/io_ddr_reg.vhd | 183 +++++------------------
1 file changed, 39 insertions(+), 144 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd b/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
index 1c00111eaa..c2c8c3186e 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2011
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -19,26 +19,35 @@
--
-------------------------------------------------------------------------------
--- RO read only (no VHDL present to access HW in write mode)
--- WO write only (no VHDL present to access HW in read mode)
--- WE write event (=WO)
--- WR write control, read control
--- RW read status, write control
--- RC read, clear on read
--- FR FIFO read
--- FW FIFO write
--
--- wi Bits R/W Name Default Description |REG_DDR3|
+-- Register definition:
+--
+-- wi Bits R/W Name Default Description
-- =============================================================================
-- 0 [0] WE burstbegin 0x0
-- 1 [0] WO wr_not_rd 0x0
-- 2 [0] RO done 0x1
--- 3 [1..0] RO cal_result 0x1 cal_fail & cal_ok
--- 4 [0] RO waitrequest_n 0x1
+-- 3 not used
+-- 4 not used
-- 5 [31..0] WO address 0x0
-- 6 [31..0] WO burstsize 0x0
-- 7 [0] WR flush 0x0
-- =============================================================================
+--
+-- Legenda:
+--
+-- RO read only (no VHDL present to access HW in write mode)
+-- WO write only (no VHDL present to access HW in read mode)
+-- WE write event (=WO)
+-- WR write control, read control
+-- RW read status, write control
+-- RC read, clear on read
+-- FR FIFO read
+-- FW FIFO write
+--
+-- Remarks:
+-- . Clock domain crossing between mm_clk and the DDR controller clock domain
+-- needs to be done by io_ddr_cross_domain.vhd in io_ddr.
LIBRARY IEEE, common_lib, diag_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -52,8 +61,6 @@ ENTITY io_ddr_reg IS
-- Clocks and reset
mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
- dp_rst : IN STD_LOGIC; -- reset synchronous with dp_clk
- dp_clk : IN STD_LOGIC; -- other clock domain clock
-- Memory Mapped Slave in mm_clk domain
sla_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
@@ -72,13 +79,14 @@ ARCHITECTURE rtl OF io_ddr_reg IS
adr_w => ceil_log2(8),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => 8,
- init_sl => '0');
- -- Registers in mm_clk domain
- SIGNAL mm_dvr_miso : t_mem_ctlr_miso;
- SIGNAL mm_dvr_mosi : t_mem_ctlr_mosi;
-
+ init_sl => '0');
+
+ SIGNAL i_dvr_mosi : t_mem_ctlr_mosi;
+
BEGIN
+ dvr_mosi <= i_dvr_mosi;
+
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -90,29 +98,30 @@ BEGIN
p_mm_reg : PROCESS (mm_rst, mm_clk)
BEGIN
IF mm_rst = '1' THEN
- sla_out <= c_mem_miso_rst;
- mm_dvr_mosi <= c_mem_ctlr_mosi_rst;
+ sla_out <= c_mem_miso_rst;
+ i_dvr_mosi <= c_mem_ctlr_mosi_rst;
ELSIF rising_edge(mm_clk) THEN
-- Read access defaults
sla_out.rdval <= '0';
- mm_dvr_mosi.burstbegin <= '0';
+
+ -- Write access defaults
+ i_dvr_mosi.burstbegin <= '0';
-- Write access: set register value
IF sla_in.wr = '1' THEN
CASE TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
-- Write Block Sync
WHEN 0 =>
- mm_dvr_mosi.burstbegin <= sla_in.wrdata(0);
+ i_dvr_mosi.burstbegin <= sla_in.wrdata(0); -- default to '0' so MM write '1' will yield a pulse of one mm_clk clock cycle
WHEN 1 =>
- mm_dvr_mosi.wr <= sla_in.wrdata(0);
- mm_dvr_mosi.rd <= NOT(sla_in.wrdata(0));
+ i_dvr_mosi.wr <= sla_in.wrdata(0); -- = wr_not_rd, so no need to control i_dvr_mosi.rd
WHEN 5 =>
- mm_dvr_mosi.address <= sla_in.wrdata(c_mem_ctlr_address_w-1 DOWNTO 0);
+ i_dvr_mosi.address <= sla_in.wrdata(c_mem_ctlr_address_w-1 DOWNTO 0);
WHEN 6 =>
- mm_dvr_mosi.burstsize <= sla_in.wrdata(c_mem_ctlr_burstsize_w-1 DOWNTO 0);
+ i_dvr_mosi.burstsize <= sla_in.wrdata(c_mem_ctlr_burstsize_w-1 DOWNTO 0);
WHEN 7 =>
- mm_dvr_mosi.flush <= sla_in.wrdata(0);
+ i_dvr_mosi.flush <= sla_in.wrdata(0);
WHEN OTHERS => NULL; -- unused MM addresses
END CASE;
@@ -123,128 +132,14 @@ BEGIN
CASE TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
-- Read Block Sync
WHEN 2 =>
- sla_out.rddata(0) <= mm_dvr_miso.done;
- WHEN 3 =>
- sla_out.rddata(1 DOWNTO 0) <= mm_dvr_miso.cal_fail & mm_dvr_miso.cal_ok;
- WHEN 4 =>
- sla_out.rddata(0) <= mm_dvr_miso.waitrequest_n;
+ sla_out.rddata(0) <= dvr_miso.done; -- read only
WHEN 7 =>
- sla_out.rddata(0) <= mm_dvr_mosi.flush;
+ sla_out.rddata(0) <= i_dvr_mosi.flush; -- readback
WHEN OTHERS => NULL; -- unused MM addresses
END CASE;
END IF;
END IF;
END PROCESS;
- ------------------------------------------------------------------------------
- -- Transfer register value between mm_clk and st_clk domain.
- -- If the function of the register ensures that the value will not be used
- -- immediately when it was set, then the transfer between the clock domains
- -- can be done by wires only. Otherwise if the change in register value can
- -- have an immediate effect then the bit or word value needs to be transfered
- -- using:
- --
- -- . common_async --> for single-bit level signal
- -- . common_spulse --> for single-bit pulse signal
- -- . common_reg_cross_domain --> for a multi-bit (a word) signal
- --
- -- Typically always use a crossing component for the single bit signals (to
- -- be on the safe side) and only use a crossing component for the word
- -- signals if it is necessary (to avoid using more logic than necessary).
- ------------------------------------------------------------------------------
-
- u_spulse_en_evt : ENTITY common_lib.common_spulse
- PORT MAP (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_dvr_mosi.burstbegin,
- in_busy => OPEN,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_pulse => dvr_mosi.burstbegin
- );
-
- u_async_wr : ENTITY common_lib.common_async
- GENERIC MAP (
- g_rst_level => '0'
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- din => mm_dvr_mosi.wr,
- dout => dvr_mosi.wr
- );
-
- u_async_rd : ENTITY common_lib.common_async
- GENERIC MAP (
- g_rst_level => '0'
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- din => mm_dvr_mosi.rd,
- dout => dvr_mosi.rd
- );
-
- u_async_flush : ENTITY common_lib.common_async
- GENERIC MAP (
- g_rst_level => '0'
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- din => mm_dvr_mosi.flush,
- dout => dvr_mosi.flush
- );
-
- u_async_done : ENTITY common_lib.common_async
- GENERIC MAP (
- g_rst_level => '0'
- )
- PORT MAP (
- rst => mm_rst,
- clk => mm_clk,
- din => dvr_miso.done,
- dout => mm_dvr_miso.done
- );
-
- u_async_waitrequest_n : ENTITY common_lib.common_async
- GENERIC MAP (
- g_rst_level => '0'
- )
- PORT MAP (
- rst => mm_rst,
- clk => mm_clk,
- din => dvr_miso.waitrequest_n,
- dout => mm_dvr_miso.waitrequest_n
- );
-
- mm_dvr_miso.cal_fail <= dvr_miso.cal_fail;
- mm_dvr_miso.cal_ok <= dvr_miso.cal_ok;
-
- u_cross_domain_addr : ENTITY common_lib.common_reg_cross_domain
- PORT MAP (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_dvr_mosi.address,
- in_done => OPEN,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_dat => dvr_mosi.address,
- out_new => OPEN
- );
-
- u_cross_domain_burstsize : ENTITY common_lib.common_reg_cross_domain
- PORT MAP (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_dvr_mosi.burstsize,
- in_done => OPEN,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_dat => dvr_mosi.burstsize,
- out_new => OPEN
- );
-
END rtl;
--
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