From ed82dce7ace6afc476b9ef88d27f812b401f5f1a Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 11 Mar 2015 14:58:44 +0000
Subject: [PATCH] splitted the terminationcontrol lines from the record types
 't_tech_ddr_phy_in' and 't_tech_ddr_phy_ou'

---
 libraries/technology/ddr/hdllib.cfg           |  2 +-
 libraries/technology/ddr/tech_ddr.vhd         |  5 ++++-
 libraries/technology/ddr/tech_ddr_pkg.vhd     | 19 ++++++++++++-------
 .../technology/ddr/tech_ddr_stratixiv.vhd     | 11 +++++++----
 4 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index bd487ba61f..7d7e2f3573 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = tech_ddr
 hdl_library_clause_name = tech_ddr_lib
 hdl_lib_uses_synth = ip_stratixiv_ddr3_uphy_4g_800_master
-               ip_stratixiv_ddr3_uphy_4g_800_slave
+#               ip_stratixiv_ddr3_uphy_4g_800_slave
                ip_stratixiv_ddr3_mem_model
                ip_arria10_ddr4_4g_1600
                ip_arria10_ddr4_8g_2400
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index 8d97133720..578924ddf5 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -55,6 +55,9 @@ ENTITY tech_ddr IS
     ctlr_mosi         : IN    t_mem_ctlr_mosi;
     ctlr_miso         : OUT   t_mem_ctlr_miso;
 
+    term_ctrl_out     : OUT   t_tech_ddr_phy_terminationcontrol;
+    term_ctrl_in      : IN    t_tech_ddr_phy_terminationcontrol := c_tech_ddr_phy_terminationcontrol_rst;
+
     -- PHY interface
     phy_in            : IN    t_tech_ddr_phy_in;
     phy_io            : INOUT t_tech_ddr_phy_io;
@@ -74,7 +77,7 @@ BEGIN
     GENERIC MAP (g_tech_ddr)
     PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
               ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
-              ctlr_mosi, ctlr_miso,
+              ctlr_mosi, ctlr_miso, term_ctrl_out, term_ctrl_in,
               phy_in, phy_io, i_phy_ou);
   END GENERATE;
   
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index fabf6331e6..9a9259508a 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -79,10 +79,8 @@ PACKAGE tech_ddr_pkg IS
     oct_rzqin                  : STD_LOGIC;                                                         --    -    +  DDR4 PHY has On Chip Termination OCT inputs
     oct_rup                    : STD_LOGIC;                                                         --    +    -  only master DDR3 PHY has On Chip Termination OCT inputs
     oct_rdn                    : STD_LOGIC;                                                         --    +    -  only master DDR3 PHY has On Chip Termination OCT inputs
-    seriesterminationcontrol   : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0);  --    +    -  termination control to slave from master DDR3 PHY (internal signal in FPGA)
-    parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0);  --    +    -  termination control to slave from master DDR3 PHY (internal signal in FPGA)
   END RECORD;
-  
+
   TYPE t_tech_ddr_phy_io IS RECORD                                                                  -- DDR3 DDR4  Description
     dq               : STD_LOGIC_VECTOR(c_tech_ddr_max.dq_w-1 DOWNTO 0);                            --    +    +  data bus
     dqs              : STD_LOGIC_VECTOR(c_tech_ddr_max.dqs_w-1 DOWNTO 0);                           --    +    +  data strobe bus
@@ -108,20 +106,27 @@ PACKAGE tech_ddr_pkg IS
     cke                        : STD_LOGIC_VECTOR(c_tech_ddr_max.cke_w-1 DOWNTO 0);                 --    +    +  clock enable
     cs_n                       : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w-1 DOWNTO 0);                  --    +    +  chip select
     odt                        : STD_LOGIC_VECTOR(c_tech_ddr_max.odt_w-1 DOWNTO 0);                 --    +    +  on-die termination control signal
+  END RECORD;
+
+  TYPE t_tech_ddr_phy_terminationcontrol IS RECORD                                                  -- DDR3 DDR4  Termination control
     seriesterminationcontrol   : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0);  --    +    -  termination control from master to slave DDR3 PHY (internal signal in FPGA)
     parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0);  --    +    -  termination control from master to slave DDR3 PHY (internal signal in FPGA)
   END RECORD;
 
-  CONSTANT c_tech_ddr_phy_in_x     : t_tech_ddr_phy_in := ('X', 'X', 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'));
-  CONSTANT c_tech_ddr_phy_in_rst   : t_tech_ddr_phy_in := ('0', '1', 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'));
+  CONSTANT c_tech_ddr_phy_terminationcontrol_x   : t_tech_ddr_phy_terminationcontrol := ((OTHERS=>'X'), (OTHERS=>'X'));
+  CONSTANT c_tech_ddr_phy_terminationcontrol_rst : t_tech_ddr_phy_terminationcontrol := ((OTHERS=>'0'), (OTHERS=>'0'));
+
+  CONSTANT c_tech_ddr_phy_in_x     : t_tech_ddr_phy_in := ('X', 'X', 'X', 'X', 'X');
+  CONSTANT c_tech_ddr_phy_in_rst   : t_tech_ddr_phy_in := ('0', '1', 'X', 'X', 'X');
   CONSTANT c_tech_ddr_phy_io_x     : t_tech_ddr_phy_io := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X');
   CONSTANT c_tech_ddr_phy_io_rst   : t_tech_ddr_phy_io := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0');
-  CONSTANT c_tech_ddr_phy_ou_x     : t_tech_ddr_phy_ou := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X', 'X', 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'));
-  CONSTANT c_tech_ddr_phy_ou_rst   : t_tech_ddr_phy_ou := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', '0', '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
+  CONSTANT c_tech_ddr_phy_ou_x     : t_tech_ddr_phy_ou := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X', 'X', 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'));
+  CONSTANT c_tech_ddr_phy_ou_rst   : t_tech_ddr_phy_ou := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', '0', '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
 
   TYPE t_tech_ddr_phy_in_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_in;
   TYPE t_tech_ddr_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_io; 
   TYPE t_tech_ddr_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_ou;
+  TYPE t_tech_ddr_phy_terminationcontrol_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_terminationcontrol;
 
 END tech_ddr_pkg;
 
diff --git a/libraries/technology/ddr/tech_ddr_stratixiv.vhd b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
index f95ae40138..106ad8901a 100644
--- a/libraries/technology/ddr/tech_ddr_stratixiv.vhd
+++ b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
@@ -59,6 +59,9 @@ ENTITY tech_ddr_stratixiv IS
     ctlr_mosi         : IN    t_mem_ctlr_mosi;
     ctlr_miso         : OUT   t_mem_ctlr_miso;
 
+    term_ctrl_out     : OUT   t_tech_ddr_phy_terminationcontrol;
+    term_ctrl_in      : IN    t_tech_ddr_phy_terminationcontrol := c_tech_ddr_phy_terminationcontrol_rst;
+
     -- PHY interface
     phy_in            : IN    t_tech_ddr_phy_in;
     phy_io            : INOUT t_tech_ddr_phy_io;
@@ -124,8 +127,8 @@ BEGIN
       local_cal_fail             => OPEN,                                                                           --             .local_cal_fail
       oct_rdn                    => phy_in.oct_rdn,                                                                 --          oct.rdn
       oct_rup                    => phy_in.oct_rup,                                                                 --             .rup
-      seriesterminationcontrol   => phy_ou.seriesterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0),    --  oct_sharing.seriesterminationcontrol
-      parallelterminationcontrol => phy_ou.parallelterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0),  --             .parallelterminationcontrol
+      seriesterminationcontrol   => term_ctrl_out.seriesterminationcontrol,                                         --  oct_sharing.seriesterminationcontrol
+      parallelterminationcontrol => term_ctrl_out.parallelterminationcontrol,                                       --             .parallelterminationcontrol
       pll_mem_clk                => i_ctlr_gen_clk_2x,                                                              --  pll_sharing.pll_mem_clk
       pll_write_clk              => OPEN,                                                                           --             .pll_write_clk
       pll_write_clk_pre_phy_clk  => OPEN,                                                                           --             .pll_write_clk_pre_phy_clk
@@ -174,8 +177,8 @@ BEGIN
       local_init_done            => ctlr_miso.done,                                                                 --       status.local_init_done
       local_cal_success          => OPEN,                                                                           --             .local_cal_success
       local_cal_fail             => OPEN,                                                                           --             .local_cal_fail
-      seriesterminationcontrol   => phy_in.seriesterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0),    --  oct_sharing.seriesterminationcontrol
-      parallelterminationcontrol => phy_in.parallelterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0),  --             .parallelterminationcontrol
+      seriesterminationcontrol   => term_ctrl_in.seriesterminationcontrol,                                          --  oct_sharing.seriesterminationcontrol
+      parallelterminationcontrol => term_ctrl_in.parallelterminationcontrol,                                        --             .parallelterminationcontrol
       pll_mem_clk                => i_ctlr_gen_clk_2x,                                                              --  pll_sharing.pll_mem_clk
       pll_write_clk              => OPEN,                                                                           --             .pll_write_clk
       pll_write_clk_pre_phy_clk  => OPEN,                                                                           --             .pll_write_clk_pre_phy_clk
-- 
GitLab