diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index f375d1057d5b38b46c5bd10fcfd9594c1a977fb4..580cbfe0248120c71dfb70b60eb91ebb6bf7a325 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -140,24 +140,6 @@ ARCHITECTURE str OF mmm_unb1_ddr3 IS
   SIGNAL i_tse_clk       : STD_LOGIC := '1';
   SIGNAL i_cal_clk       : STD_LOGIC := '1';
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
   CONSTANT c_dut_src_mac       : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"002286080001";
   SIGNAL eth_psc_access        : STD_LOGIC;
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index a2c70e43a2b731f5700271dd1bfb18167510cfca..bc69bb0c4972a5b6679cabe570d6b68acbdddb5d 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -150,24 +150,6 @@ ARCHITECTURE str OF mmm_unb1_ddr3_reorder IS
   SIGNAL i_tse_clk                   : STD_LOGIC := '1';
   SIGNAL i_cal_clk                   : STD_LOGIC := '1';
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;               
-
   CONSTANT c_dut_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
 
   SIGNAL i_eth1g_reg_mosi      : t_mem_mosi;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 28b71acba3fe03bfe7fd676af98769c45d74d7b3..b7a80e485d4124e2b7daaf952a1b60bf2d724260 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -128,24 +128,6 @@ ARCHITECTURE str OF mmm_unb_ddr3_transpose IS
 
   SIGNAL i_mm_clk : STD_LOGIC := '1';
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   mm_clk <= i_mm_clk;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 76ebefd9d4ea498a33c36e41d16ad85a3d3a1588..8d90ce298d29d74d33fece71f9bee40216093704 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -118,24 +118,6 @@ ARCHITECTURE str OF mmm_unb1_fn_terminal_db IS
   SIGNAL i_mm_clk  : STD_LOGIC := '1';
   SIGNAL i_tse_clk : STD_LOGIC := '1';
   
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;               
-
   CONSTANT c_dut_src_mac           : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"002286080001";
   SIGNAL eth_psc_access            : STD_LOGIC;
                                    
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index 8aaf71720d4f74eec3150c6404ddc026c34af77c..d9185ca3e9f7b9cb98090dfddb7b44ab7fc5925a 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -194,23 +194,6 @@ ARCHITECTURE tb OF tb_mmf_node_fn_terminal_db IS
   SIGNAL fn_in_mesh_serial_4arr  : t_unb_mesh_sl_4arr;
   SIGNAL fn_out_mesh_serial_4arr : t_unb_mesh_sl_4arr;
  
-  ----------------------------------------------------------------------------
-  -- Component declaration of mm_file (many instances in this TB)
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index cc3461abb50de08317fb5e53df7c29449f30bbcc..d770b309cb47bfa8167a5d214353bcd4347f299f 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -115,24 +115,6 @@ ARCHITECTURE str OF mmm_unb1_heater IS
   SIGNAL i_mm_clk   : STD_LOGIC := '1';
   SIGNAL i_epcs_clk : STD_LOGIC := '1';
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   mm_clk   <= i_mm_clk;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 0aac10f8d2398d81cdac6db7decd1225d029621e..d983de6e64d20c38c75cd801e22ec6d6b1ea5a34 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -119,24 +119,6 @@ ARCHITECTURE str OF mmm_unb1_minimal_qsys_wo_pll IS
 
   CONSTANT c_mm_clk_period : TIME := 1000 ms / g_mm_clk_freq;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index f9397879995603722b848250e20a0082485b7247..36ec44d5226f9b612d377644cf349224feb6cd14 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -113,24 +113,6 @@ ARCHITECTURE str OF mmm_unb1_minimal IS
   SIGNAL i_mm_clk   : STD_LOGIC := '1';
   SIGNAL i_epcs_clk : STD_LOGIC := '1';
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
   ----------------------------------------------------------------------------
   -- MM arbiter
   -- . In the NIOS-only (plus 1GbE actually) QSYS, all devices are below 0x4000.
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 75ac881e2fa840a071d5006a4cef33ffd14d5bd0..60ac564fd37bc6811e8ac60a9c3beab10f2bbc56 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -145,21 +145,6 @@ ARCHITECTURE str OF mmm_unb1_terminal_bg_mesh_db IS
   SIGNAL mm_rst_n              : STD_LOGIC ;
   SIGNAL sim_eth1g_reg_mosi    : t_mem_mosi;
 
-  COMPONENT mm_file IS
-    GENERIC (
-      g_file_prefix      : STRING ;
-      g_mm_clk_period    : TIME    := 8 ns;
-      g_update_on_change : BOOLEAN := FALSE;
-      g_mm_rd_latency    : NATURAL := 1
-    );
-    PORT (
-      mm_rst        : IN  STD_LOGIC;
-      mm_clk        : IN  STD_LOGIC;
-      mm_master_out : OUT t_mem_mosi := c_mem_mosi_rst;
-      mm_master_in  : IN  t_mem_miso := c_mem_miso_rst
-    );
-  END COMPONENT mm_file;
-  
   COMPONENT qsys_unb1_terminal_bg_mesh_db IS
     PORT (
       reg_diag_bg_reset_export                : out std_logic;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 47b4396ba78962aaf3ea570e512f9a3ecdebb8f0..adc210b9f66a6aa8c4ddbdb05edbf54d2575f209 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -254,23 +254,6 @@ ARCHITECTURE str OF mmm_unb1_test IS
 
   SIGNAL i_reset_n                                       : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------