From ed30ebb1df279887dcf79bcd72475b085bee3d75 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 12 Feb 2020 15:43:16 +0100
Subject: [PATCH] Update on g_sim and MM bus mux.
---
.../lofar2/doc/prestudy/station2_to_do_erko.txt | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/applications/lofar2/doc/prestudy/station2_to_do_erko.txt b/applications/lofar2/doc/prestudy/station2_to_do_erko.txt
index 76043159f7..36f4c6c73b 100755
--- a/applications/lofar2/doc/prestudy/station2_to_do_erko.txt
+++ b/applications/lofar2/doc/prestudy/station2_to_do_erko.txt
@@ -59,6 +59,18 @@ Vijf principes:
- data buffer on output beamlets --> histogram
. buffer all beamlets per T_sub at sync
. buffer one beamlet for some T_sub time series after sync
+- Created common_mem_bus and common_mem_master_mux to replace Qsys
+ . considered using Wishbone, but for our M&C using common_mem_bus is easier than wrapping a Wishbone bus
+ . add a common_arbiter to make a common_mem_master_arbiter using miso.waitrequest, however then it may
+ be necessary to reconsider wrapping a Wishbone bus.
+- Add support generating MM bus by wiring common_mem_bus to named mosi/miso slaves or arrays of slaves
+ from yaml with ARGS
+- g_sim
+ . define g_sim record
+ . use g_sim or consider sim models as a technology
+- lofar2_unb2c structure with design_name revisions and node_<> per device: bsp, ring_(bf, xc, tb, so),
+ node_(bf, xc, tb, so, tdet, adc, fb), ddr4_(0,1) for tb, offload_10g
+
- Use GIT
- Understand AXI4 streaming (versus avalon, RL =0)
--
GitLab