diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index a211be7af742b38f7a3d00928c13626e634c6ea8..effc6fdee45f3be59d313cc0c8b881c0a0797397 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,8 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR_IN "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/generated_in/"
- set IP_DIR_OUT "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/generated_out/"
+ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/ddio/generated/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151 ./work/
@@ -41,14 +40,14 @@ if {$IPMODEL=="PHY"} {
#vmap ip_arria10_e3sge3_ddio_in_1 ./work/
#vmap ip_arria10_e3sge3_ddio_out_1 ./work/
- vlog -sv "$IP_DIR_IN/../altera_gpio_core20_151/sim/mentor/altera_gpio.sv" -work ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151
- vlog -sv "$IP_DIR_OUT/../altera_gpio_core20_151/sim/mentor/altera_gpio.sv" -work ip_arria10_e3sge3_ddio_out_1_altera_gpio_core_151
+ vlog -sv "$IP_DIR/../altera_gpio_core20_151/sim/mentor/altera_gpio.sv" -work ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151
+ vlog -sv "$IP_DIR/../altera_gpio_core20_151/sim/mentor/altera_gpio.sv" -work ip_arria10_e3sge3_ddio_out_1_altera_gpio_core_151
- vcom "$IP_DIR_IN/../altera_gpio_151/sim/ip_arria10_e3sge3_ddio_in_1_altera_gpio_151_ia6gnqq.vhd" -work ip_arria10_e3sge3_ddio_in_1_altera_gpio_151
- vcom "$IP_DIR_IN/ip_arria10_e3sge3_ddio_in_1.vhd"
+ vcom "$IP_DIR/../altera_gpio_151/sim/ip_arria10_e3sge3_ddio_in_1_altera_gpio_151_ia6gnqq.vhd" -work ip_arria10_e3sge3_ddio_in_1_altera_gpio_151
+ vcom "$IP_DIR/ip_arria10_e3sge3_ddio_in_1.vhd"
- vcom "$IP_DIR_OUT/../altera_gpio_151/sim/ip_arria10_e3sge3_ddio_out_1_altera_gpio_151_pqwimxi.vhd" -work ip_arria10_e3sge3_ddio_out_1_altera_gpio_151
- vcom "$IP_DIR_OUT/ip_arria10_e3sge3_ddio_out_1.vhd"
+ vcom "$IP_DIR/../altera_gpio_151/sim/ip_arria10_e3sge3_ddio_out_1_altera_gpio_151_pqwimxi.vhd" -work ip_arria10_e3sge3_ddio_out_1_altera_gpio_151
+ vcom "$IP_DIR/ip_arria10_e3sge3_ddio_out_1.vhd"
} else {
@@ -60,3 +59,5 @@ if {$IPMODEL=="PHY"} {
vcom "$SIM_DIR/tb_ip_arria10_e3sge3_ddio_1.vhd"
}
+
+
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
index 361db703aa0f36e8d302cc30bb31b039ff3c8102..03a3952849ec9bceb03b4d36233664baa97de349 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/generate_ip.sh
@@ -39,5 +39,5 @@
#qsys-generate --help
# Only generate the source IP
-qsys-generate ip_arria10_e3sge3_ddio_in_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated_in
-qsys-generate ip_arria10_e3sge3_ddio_out_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated_out
+qsys-generate ip_arria10_e3sge3_ddio_in_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_e3sge3_ddio_out_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index 39992bea6f8b17ce89f0ff2dc2e09fd412c06edb..7cd200e2a02739befc8219e71717431d7e9f912c 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -60,8 +60,8 @@ vmap ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151 ./wor
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_151/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_151/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_151/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_151/sim/ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151_htqgx4q.sv" -L altera_common_sv_packages -work ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_151/sim/alt_xcvr_native_rcfg_opt_logic_htqgx4q.sv" -L altera_common_sv_packages -work ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_151/sim/ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151_iy2mgzi.sv" -L altera_common_sv_packages -work ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_151/sim/alt_xcvr_native_rcfg_opt_logic_iy2mgzi.sv" -L altera_common_sv_packages -work ip_arria10_e3sge3_tse_sgmii_gx_altera_xcvr_native_a10_151
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_151/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_151
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_151/sim/mentor/altera_tse_align_sync.v" -work ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_151
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_151/sim/mentor/altera_tse_dec10b8b.v" -work ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_151
@@ -249,5 +249,5 @@ vmap ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151 ./wor
vlog "$IP_DIR/../altera_eth_tse_mac_151/sim/mentor/altera_tse_ecc_enc_x30.v" -work ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_mac_151
vlog "$IP_DIR/../altera_eth_tse_mac_151/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_mac_151
vlog "$IP_DIR/../altera_eth_tse_mac_151/sim/mentor/altera_tse_ecc_status_crosser.v" -work ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_mac_151
- vlog "$IP_DIR/../altera_eth_tse_151/sim/ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151_ixscpxa.v" -work ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
+ vlog "$IP_DIR/../altera_eth_tse_151/sim/ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151_w6pypty.v" -work ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
vcom "$IP_DIR/ip_arria10_e3sge3_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index 6bae35fba1f0e3f6fea4c57259b2e46dee679c48..08b93719dc0476c7c07404d2e49af4de685e5daf 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_tse_sgmii_gx
-hdl_library_clause_name = ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_150
+hdl_library_clause_name = ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index 587e93ec3e9c43caac6daf722f1ab1479a02b95c..e87dac9068b20dd85899eef7ec96310ee4803226 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -39,10 +39,11 @@ vmap ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_avalon_arbiter_151 ./wo
vmap ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_mac_151 ./work/
vmap ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151 ./work/
- vlog -sv "$IP_DIR/../altera_lvds_core20_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151_lnpe55i.sv" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151
+
+ vlog -sv "$IP_DIR/../altera_lvds_core20_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151_56nfjoq.sv" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151
vlog -sv "$IP_DIR/../altera_lvds_core20_151/sim/altera_lvds_core20.sv" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151
vlog "$IP_DIR/../altera_lvds_core20_151/sim/altera_lvds_core20_pll.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151
- vlog -sv "$IP_DIR/../altera_lvds_core20_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151_gpbqs4y.sv" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151
+ vlog -sv "$IP_DIR/../altera_lvds_core20_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151_lgv7ceq.sv" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151
vlog -sv "$IP_DIR/../altera_lvds_core20_151/sim/altera_lvds_core20.sv" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151
vlog "$IP_DIR/../altera_lvds_core20_151/sim/altera_lvds_core20_pll.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_core20_151
vlog "$IP_DIR/../altera_reset_controller_151/sim/altera_reset_controller.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_reset_controller_151
@@ -51,8 +52,8 @@ vmap ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151 ./wo
vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_151/sim/mentor/altera_tse_reset_synchronizer.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_nf_lvds_terminator_151
vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_151/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_nf_lvds_terminator_151
vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_151/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_nf_lvds_terminator_151
- vlog "$IP_DIR/../altera_lvds_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_151_c7jevba.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_151
- vlog "$IP_DIR/../altera_lvds_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_151_lae6doy.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_151
+ vlog "$IP_DIR/../altera_lvds_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_151_4n7sgkq.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_151
+ vlog "$IP_DIR/../altera_lvds_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_151_6qqk7py.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_lvds_151
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_151/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_pcs_pma_nf_lvds_151
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_151/sim/mentor/altera_tse_align_sync.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_pcs_pma_nf_lvds_151
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_151/sim/mentor/altera_tse_dec10b8b.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_pcs_pma_nf_lvds_151
@@ -241,5 +242,5 @@ vmap ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151 ./wo
vlog "$IP_DIR/../altera_eth_tse_mac_151/sim/mentor/altera_tse_ecc_enc_x30.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_mac_151
vlog "$IP_DIR/../altera_eth_tse_mac_151/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_mac_151
vlog "$IP_DIR/../altera_eth_tse_mac_151/sim/mentor/altera_tse_ecc_status_crosser.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_mac_151
- vlog "$IP_DIR/../altera_eth_tse_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_jjd52za.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
+ vlog "$IP_DIR/../altera_eth_tse_151/sim/ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq.v" -work ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
vcom "$IP_DIR/ip_arria10_e3sge3_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index 25c96095a0b279937690a462cb7a7e943d45ced5..e8b3d4351add0c8fd7b030a896d9ee64a79eabdf 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e3sge3_tse_sgmii_lvds
-hdl_library_clause_name = ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_150
+hdl_library_clause_name = ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 5a499a051328fb15579076ab5732a31f740309b5..5795b280e8a92747ba4fee5345162ff33c01d52b 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram
+hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram
hdl_lib_uses_sim =
hdl_lib_technology =
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index ba20fd2824ad181920e61841115628bf8effd9c9..c256264184796041d180a79632bf4d224a4a62c7 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -234,4 +234,98 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e3sge3
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e3sge3_ram_crwk_crw IS
+ GENERIC (
+ g_adr_a_w : NATURAL := 5;
+ g_dat_a_w : NATURAL := 32;
+ g_adr_b_w : NATURAL := 4;
+ g_dat_b_w : NATURAL := 64;
+ g_nof_words_a : NATURAL := 2**5;
+ g_nof_words_b : NATURAL := 2**4;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_ram_crw_crw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_ram_cr_cw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ wrclk : IN STD_LOGIC := '1';
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e3sge3_ram_r_w IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT (
+ clk : IN STD_LOGIC := '1';
+ data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_memory_component_pkg;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 9b8ed180c25c4a65092235fbf4e0788ce63ac246..b29ac59a5f18abfb91f756120df0e4184a8b9edf 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -68,10 +68,10 @@ BEGIN
PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
END GENERATE;
--- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
--- u0 : ip_arria10_e3sge3_ram_cr_cw
--- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
--- PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
--- END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_ram_cr_cw
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index f41db436d04ec5570163b0b8f4cee07cb4631ef0..097ccb328963f92ca96c45e7e7565a5b3d0fa55c 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -75,10 +75,10 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
--- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
--- u0 : ip_arria10_e3sge3_ram_crw_crw
--- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
--- PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
--- END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_ram_crw_crw
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index b76b5635f2d8b561bd70000a62b595dfa25974ef..33cff6d845eb84c7cbd712e7549df4bae429785a 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -77,10 +77,10 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
--- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
--- u0 : ip_arria10_e3sge3_ram_crwk_crw
--- GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
--- PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
--- END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_ram_crwk_crw
+ GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
+ PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 5d57f377e18e85117209e2c94932aa2774c295ee..088235bcbaf441e55edf0a71c6f8e014f60ebc90 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -65,10 +65,10 @@ BEGIN
PORT MAP (clock, data, rdaddress, wraddress, wren, q);
END GENERATE;
--- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
--- u0 : ip_arria10_e3sge3_ram_r_w
--- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
--- PORT MAP (clock, data, rdaddress, wraddress, wren, q);
--- END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_ram_r_w
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ PORT MAP (clock, data, rdaddress, wraddress, wren, q);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 998e0ad2d00dad0b9345404af94c50c865d3615a..4a9d4ffc5da853ab3416942a45f03e54b673daa3 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -69,18 +69,18 @@ BEGIN
);
END GENERATE;
--- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
--- -- use ip_arria10_e3sge3_ram_r_w as ROM
--- u0 : ip_arria10_e3sge3_ram_r_w
--- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
--- PORT MAP (
--- clk => clock,
--- --data => ,
--- rdaddress => address,
--- --wraddress => ,
--- --wren => ,
--- q => q
--- );
--- END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ -- use ip_arria10_e3sge3_ram_r_w as ROM
+ u0 : ip_arria10_e3sge3_ram_r_w
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ PORT MAP (
+ clk => clock,
+ --data => ,
+ rdaddress => address,
+ --wraddress => ,
+ --wren => ,
+ q => q
+ );
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 4ddb613a83f1db2a3cd11bebf65c5841f251aa0c..6f10a65cf0c14be5d70a1c6ff6de618c6dd3882f 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -14,6 +14,7 @@ synth_files =
tech_tse_pkg.vhd
tech_tse_stratixiv.vhd
tech_tse_arria10.vhd
+ tech_tse_arria10_e3sge3.vhd
tech_tse.vhd
tb_tech_tse_pkg.vhd
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 9678f33b4953d0a6bfcfa02e14f8436da176e1fd..f91fa4c3690d2d3dfce1b2a8bc72bf280c209267 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -102,5 +102,18 @@ BEGIN
eth_txp, eth_rxp,
tse_led);
END GENERATE;
+
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ENTITY work.tech_tse_arria10_e3sge3
+ GENERIC MAP (g_ETH_PHY)
+ PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+ mm_sla_in, mm_sla_out,
+ tx_snk_in, tx_snk_out,
+ tx_mac_in, tx_mac_out,
+ rx_src_in, rx_src_out,
+ rx_mac_out,
+ eth_txp, eth_rxp,
+ tse_led);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed5297387bfbddf8f28a4fca964b7349bff04d5b
--- /dev/null
+++ b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
@@ -0,0 +1,256 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.tech_tse_component_pkg.ALL;
+USE work.tech_tse_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151;
+LIBRARY ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151;
+
+ENTITY tech_tse_arria10_e3sge3 IS
+ GENERIC (
+ g_ETH_PHY : STRING := "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb2_board, "XCVR": uses tranceiver PHY
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ eth_clk : IN STD_LOGIC;
+ tx_snk_clk : IN STD_LOGIC;
+ rx_src_clk : IN STD_LOGIC;
+
+ -- Memory Mapped Slave
+ mm_sla_in : IN t_mem_mosi;
+ mm_sla_out : OUT t_mem_miso;
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
+ -- . MAC specific
+ tx_mac_in : IN t_tech_tse_tx_mac;
+ tx_mac_out : OUT t_tech_tse_tx_mac;
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in : IN t_dp_siso;
+ rx_src_out : OUT t_dp_sosi;
+ -- . MAC specific
+ rx_mac_out : OUT t_tech_tse_rx_mac;
+
+ -- PHY interface
+ eth_txp : OUT STD_LOGIC;
+ eth_rxp : IN STD_LOGIC;
+
+ tse_led : OUT t_tech_tse_led
+ );
+END tech_tse_arria10_e3sge3;
+
+ARCHITECTURE str OF tech_tse_arria10_e3sge3 IS
+
+ SIGNAL ff_tx_mod : STD_LOGIC_VECTOR(c_tech_tse_empty_w-1 DOWNTO 0);
+
+ SIGNAL ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ -- Default frame level flow control
+ tx_snk_out.xon <= '1';
+
+ -- Force empty = 0 when eop = '0' to avoid TSE MAC bug of missing two bytes when empty = 2 (observed with v9.1)
+ ff_tx_mod <= tx_snk_in.empty(c_tech_tse_empty_w-1 DOWNTO 0) WHEN tx_snk_in.eop='1' ELSE (OTHERS=>'0');
+
+ -- Force unused bits and fields in rx_src_out to c_dp_sosi_rst to avoid confusing 'X' in wave window
+ rx_src_out <= ff_rx_out;
+
+ u_LVDS_tse: IF g_ETH_PHY = "LVDS" GENERATE
+
+ u_tse : ip_arria10_e3sge3_tse_sgmii_lvds
+ -- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ING_FIFO = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ENABLE_SGMII = 0 : PHY access 1000BASE-X
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => tx_snk_clk,
+ ff_tx_rdy => tx_snk_out.ready,
+ ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_tx_wren => tx_snk_in.valid,
+ ff_tx_sop => tx_snk_in.sop,
+ ff_tx_eop => tx_snk_in.eop,
+ ff_tx_mod => ff_tx_mod,
+ ff_tx_err => tx_snk_in.err(0),
+ -- . MAC specific
+ ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon ST
+ ff_rx_clk => rx_src_clk,
+ ff_rx_rdy => rx_src_in.ready,
+ ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_rx_dval => ff_rx_out.valid,
+ ff_rx_sop => ff_rx_out.sop,
+ ff_rx_eop => ff_rx_out.eop,
+ ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
+ rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk,
+ reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_rd => mm_sla_in.rd,
+ reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_wr => mm_sla_in.wr,
+ reg_busy => mm_sla_out.waitrequest,
+ -- Status LEDs
+ led_an => tse_led.an, -- '1' = autonegation completed
+ led_link => tse_led.link, -- '1' = successful link synchronisation
+ led_disp_err => tse_led.disp_err, -- TBI character error
+ led_char_err => tse_led.char_err, -- TBI disparity error
+ -- crs and col are only available with the SGMII bridge
+ led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
+ led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN,
+ ref_clk => eth_clk,
+ txp => eth_txp,
+ rxp => eth_rxp
+ );
+
+ END GENERATE;
+
+ u_XCVR_tse: IF g_ETH_PHY = "XCVR" GENERATE
+
+ u_tse : ip_arria10_e3sge3_tse_sgmii_gx
+ -- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 2048 : Tx FIFO depth in nof 32 bit words (2048 --> 4 M9K)
+ -- . ING_FIFO = 2048 : Rx FIFO depth in nof 32 bit words (2048 --> 4 M9K)
+ -- . ENABLE_SGMII = 0 : PHY access 1000BASE-X
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => tx_snk_clk,
+ ff_tx_rdy => tx_snk_out.ready,
+ ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_tx_wren => tx_snk_in.valid,
+ ff_tx_sop => tx_snk_in.sop,
+ ff_tx_eop => tx_snk_in.eop,
+ ff_tx_mod => ff_tx_mod,
+ ff_tx_err => tx_snk_in.err(0),
+ -- . MAC specific
+ ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon ST
+ ff_rx_clk => rx_src_clk,
+ ff_rx_rdy => rx_src_in.ready,
+ ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_rx_dval => ff_rx_out.valid,
+ ff_rx_sop => ff_rx_out.sop,
+ ff_rx_eop => ff_rx_out.eop,
+ ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
+ rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk,
+ reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_rd => mm_sla_in.rd,
+ reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_wr => mm_sla_in.wr,
+ reg_busy => mm_sla_out.waitrequest,
+ -- Status LEDs
+ led_an => tse_led.an, -- '1' = autonegation completed
+ led_link => tse_led.link, -- '1' = successful link synchronisation
+ led_disp_err => tse_led.disp_err, -- TBI character error
+ led_char_err => tse_led.char_err, -- TBI disparity error
+ -- crs and col are only available with the SGMII bridge
+ led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
+ led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN,
+ ref_clk => eth_clk,
+ txp => eth_txp,
+ rxp => eth_rxp,
+
+ -- GX connections ????
+ tx_serial_clk => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ rx_cdr_refclk => '0', -- : in std_logic := '0'; -- rx_cdr_refclk.clk
+ tx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_set_locktodata => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => OPEN -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ );
+
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 459beec99fffc3ca8e580e558dd082d974442614..f01da8f8fc86d9e2a948d7fd41cfdc0d8290c0d4 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -260,4 +260,124 @@ PACKAGE tech_tse_component_pkg IS
);
END COMPONENT;
+
+ ------------------------------------------------------------------------------
+ -- ip_arria10
+ ------------------------------------------------------------------------------
+
+ -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/generated/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+ COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
+ PORT (
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ rxp : in std_logic := '0'; -- serial_connection.rxp_0
+ txp : out std_logic; -- .txp_0
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_clk : in std_logic := '0' -- transmit_clock_connection.clk
+ );
+ END COMPONENT;
+
+
+ -- Copied from $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/generated/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+ COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
+ PORT (
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk : in std_logic := '0'; -- rx_cdr_refclk.clk
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_set_locktodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ rxp : in std_logic := '0'; -- serial_connection.rxp
+ txp : out std_logic; -- .txp
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_panel_link : out std_logic; -- .panel_link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_clk : in std_logic := '0'; -- transmit_clock_connection.clk
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_serial_clk : in std_logic_vector(0 downto 0) := (others => '0') -- tx_serial_clk.clk
+ );
+ END COMPONENT;
+
+
END tech_tse_component_pkg;