diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index 5e2cfb3acbd2645d6c1b80f366df7b047cc79793..f700018f3ee9a5a8c590845627059bc1d66ee35e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -115,12 +115,14 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
CONSTANT c_nof_block_per_sync : NATURAL := 16;
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync * c_sdp_N_fft;
+ CONSTANT c_speed : NATURAL := 4;
+
-- WG
CONSTANT c_wg_phase : REAL := 0.0; -- WG phase in degrees
CONSTANT c_wg_freq : REAL := 160.0; -- WG freq
CONSTANT c_wg_ampl : NATURAL := NATURAL(1.0*REAL(c_sdp_FS_adc)); -- in number of lsb
CONSTANT c_bsn_start_wg : NATURAL := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- CONSTANT c_subband : REAL := 1.0;
+ CONSTANT c_subband : REAL := 1.0*(2**c_speed);
-- DUT
SIGNAL st_clk : STD_LOGIC := '0';
@@ -273,20 +275,19 @@ BEGIN
WAIT FOR c_mm_clk_period*50000;
+ assert false report "1. read whole memory!" severity note;
FOR I IN 0 TO c_bim-1 LOOP
FOR J IN 0 TO c_nof_streams-1 LOOP
- FOR K IN 0 TO c_block_size-1 LOOP
+ FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J*c_block_size)+K , sosi_out_data(c_rd_data_w-1 DOWNTO 0), tb_clk);
sosi_out_data_sin(c_data_w-1 DOWNTO 0) <= sosi_out_data(c_data_w-1 DOWNTO 0);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2 , sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1, sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
END LOOP;
END LOOP;
- WAIT FOR c_st_clk_period*1024;
WAIT FOR c_st_clk_period*5;
END LOOP;
- WAIT FOR c_mm_clk_period*3000;
WAIT FOR c_mm_clk_period*2400;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -295,20 +296,39 @@ BEGIN
WAIT FOR c_mm_clk_period*55000;
+ assert false report "2. read whole memory!" severity note;
FOR I IN 0 TO c_bim-1 LOOP
FOR J IN 0 TO c_nof_streams-1 LOOP
- FOR K IN 0 TO c_block_size-1 LOOP
+ FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J*c_block_size)+K , sosi_out_data(c_rd_data_w-1 DOWNTO 0), tb_clk);
sosi_out_data_sin(c_data_w-1 DOWNTO 0) <= sosi_out_data(c_data_w-1 DOWNTO 0);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2 , sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1, sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
END LOOP;
END LOOP;
- WAIT FOR c_st_clk_period*2024;
- WAIT FOR c_st_clk_period*9;
+ WAIT FOR c_st_clk_period*2;
END LOOP;
- WAIT FOR c_mm_clk_period*3000;
+
+ WAIT FOR c_mm_clk_period*2200;
+ mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
+ WAIT FOR c_mm_clk_period*300;
+ mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
+ WAIT FOR c_mm_clk_period*5500;
+
+
+ assert false report "3. read whole memory!" severity note;
+ FOR I IN 0 TO c_bim-1 LOOP
+ FOR J IN 0 TO c_nof_streams-1 LOOP
+ FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
+ mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J*c_block_size)+K , sosi_out_data(c_rd_data_w-1 DOWNTO 0), tb_clk);
+ sosi_out_data_sin(c_data_w-1 DOWNTO 0) <= sosi_out_data(c_data_w-1 DOWNTO 0);
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2 , sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1, sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+ END LOOP;
+ END LOOP;
+ WAIT FOR c_st_clk_period*1;
+ END LOOP;
tb_end <= '1';
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index e11ca04a0ece82e967e53ea6639f7ce199318f7a..c203779dc90592cad0c92cedb4dd904cd8c7f4b8 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -234,9 +234,9 @@ BEGIN
WHEN SET_STOP =>
-- this state sets a stop address dependend on the g_stop_percentage.
IF inp_adr-c_pof_ma >= 0 THEN
- v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
+ v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w);
ELSE
- v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+g_max_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO 0);
+ v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+g_max_adr-c_pof_ma, c_adr_w);
END IF;
v.ready_for_set_stop := '0';
v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w) := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index 4992fcc141926bda32f9525f6887cc4951cb37aa..58872d4250b5cdbfda251c72b7aa484db09956d8 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -145,28 +145,32 @@ BEGIN
-- src_out => fifo_src_out_sosi
-- );
- sosi.sop <= sosi.valid AND sosi.sop;
- sosi.eop <= sosi.valid AND sosi.eop;
p_out_siso_ready : PROCESS(out_siso, clk, out_sosi, q_out_siso)
+ VARIABLE sosi_valid : STD_LOGIC := '0';
+
BEGIN
IF out_siso.ready = '0' AND NOT (q_out_siso.ready = out_siso.ready) THEN
sosi <= out_sosi;
- sosi.valid <= '0';
+ sosi_valid := '0';
-- assert false report "sosi.valid = '0'" severity note;
ELSIF q_out_siso.ready = '1' AND NOT (q_q_out_siso.ready = q_out_siso.ready) AND unpack_state_off = '0' THEN
sosi <= out_sosi;
- sosi.valid <= '1';
+ sosi_valid := '1';
-- assert false report "sosi.valid = '1'" severity note;
ELSE
sosi <= out_sosi;
+ sosi_valid := out_sosi.valid;
END IF;
IF rising_edge(clk) THEN
q_q_out_siso <= q_out_siso;
q_out_siso <= out_siso;
END IF;
+ sosi.valid <= sosi_valid;
+ sosi.sop <= sosi_valid AND out_sosi.sop;
+ sosi.eop <= sosi_valid AND out_sosi.eop;
END PROCESS;
END str;