diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..05054e25f56d15e5fac7c66f4d0d8f5faac554f2 --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl @@ -0,0 +1,43 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2015 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generated/sim" + +#vlib ./work/ ;# Assume library work already exists + +vmap ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/altera_xcvr_functions.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/alt_xcvr_resync.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/altera_xcvr_reset_control.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 + vcom "$IP_DIR/ip_arria10_e3sge3_transceiver_reset_controller_12.vhd" diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh new file mode 100755 index 0000000000000000000000000000000000000000..2ee36221e7c7aaaa857a448f5de411d49b76722a --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/generate_ip.sh @@ -0,0 +1,44 @@ +#!/bin/bash +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2015 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# -------------------------------------------------------------------------- # +# +# Purpose: Generate IP with Qsys +# Description: +# Generate the IP in a separate generated/ subdirectory. +# +# Usage: +# +# ./generate_ip.sh +# + +# Tool settings for selected target "unb2" with arria10 +. ${RADIOHDL}/tools/quartus/set_quartus unb2a + +#qsys-generate --help + +# Only generate the source IP +# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard +qsys-generate ip_arria10_e3sge3_transceiver_reset_controller_12.qsys \ + --synthesis=VHDL \ + --simulation=VHDL \ + --output-directory=generated \ + --allow-mixed-language-simulation diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..90ac370efd1619feeac0d86266e2d26b339a6d82 --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e3sge3_transceiver_reset_controller_12 +hdl_library_clause_name = ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151 +hdl_lib_uses_synth = +hdl_lib_uses_sim = + +hdl_lib_technology = ip_arria10_e3sge3 + +modelsim_compile_ip_files = + $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl + +synth_files = + +test_bench_files = + +quartus_qip_files = + generated/ip_arria10_e3sge3_transceiver_reset_controller_12.qip diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/ip_arria10_e3sge3_transceiver_reset_controller_12.qsys b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/ip_arria10_e3sge3_transceiver_reset_controller_12.qsys new file mode 100644 index 0000000000000000000000000000000000000000..84162716091966ad47ec8a9753880af03db8e665 --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/ip_arria10_e3sge3_transceiver_reset_controller_12.qsys @@ -0,0 +1,178 @@ +<?xml version="1.0" encoding="UTF-8"?> +<system name="$${FILENAME}"> + <component + name="$${FILENAME}" + displayName="$${FILENAME}" + version="1.0" + description="" + tags="INTERNAL_COMPONENT=true" + categories="System" /> + <parameter name="bonusData"><![CDATA[bonusData +{ + element $${FILENAME} + { + datum _originalDeviceFamily + { + value = "Arria 10"; + type = "String"; + } + } + element transceiver_reset_controller_inst + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +]]></parameter> + <parameter name="clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="device" value="10AX115U4F45E3SGE3" /> + <parameter name="deviceFamily" value="Arria 10" /> + <parameter name="deviceSpeedGrade" value="3" /> + <parameter name="fabricMode" value="QSYS" /> + <parameter name="generateLegacySim" value="false" /> + <parameter name="generationId" value="0" /> + <parameter name="globalResetBus" value="false" /> + <parameter name="hdlLanguage" value="VERILOG" /> + <parameter name="hideFromIPCatalog" value="true" /> + <parameter name="lockedInterfaceDefinition" value="" /> + <parameter name="maxAdditionalLatency" value="1" /> + <parameter name="projectName" value="" /> + <parameter name="sopcBorderPoints" value="false" /> + <parameter name="systemHash" value="0" /> + <parameter name="testBenchDutName" value="" /> + <parameter name="timeStamp" value="0" /> + <parameter name="useTestBenchNamingPattern" value="false" /> + <instanceScript></instanceScript> + <interface + name="clock" + internal="transceiver_reset_controller_inst.clock" + type="clock" + dir="end"> + <port name="clock" internal="clock" /> + </interface> + <interface + name="pll_locked" + internal="transceiver_reset_controller_inst.pll_locked" + type="conduit" + dir="end"> + <port name="pll_locked" internal="pll_locked" /> + </interface> + <interface + name="pll_powerdown" + internal="transceiver_reset_controller_inst.pll_powerdown" + type="conduit" + dir="end"> + <port name="pll_powerdown" internal="pll_powerdown" /> + </interface> + <interface + name="pll_select" + internal="transceiver_reset_controller_inst.pll_select" + type="conduit" + dir="end"> + <port name="pll_select" internal="pll_select" /> + </interface> + <interface + name="reset" + internal="transceiver_reset_controller_inst.reset" + type="reset" + dir="end"> + <port name="reset" internal="reset" /> + </interface> + <interface + name="rx_analogreset" + internal="transceiver_reset_controller_inst.rx_analogreset" + type="conduit" + dir="end"> + <port name="rx_analogreset" internal="rx_analogreset" /> + </interface> + <interface + name="rx_cal_busy" + internal="transceiver_reset_controller_inst.rx_cal_busy" + type="conduit" + dir="end"> + <port name="rx_cal_busy" internal="rx_cal_busy" /> + </interface> + <interface + name="rx_digitalreset" + internal="transceiver_reset_controller_inst.rx_digitalreset" + type="conduit" + dir="end"> + <port name="rx_digitalreset" internal="rx_digitalreset" /> + </interface> + <interface + name="rx_is_lockedtodata" + internal="transceiver_reset_controller_inst.rx_is_lockedtodata" + type="conduit" + dir="end"> + <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" /> + </interface> + <interface + name="rx_ready" + internal="transceiver_reset_controller_inst.rx_ready" + type="conduit" + dir="end"> + <port name="rx_ready" internal="rx_ready" /> + </interface> + <interface + name="tx_analogreset" + internal="transceiver_reset_controller_inst.tx_analogreset" + type="conduit" + dir="end"> + <port name="tx_analogreset" internal="tx_analogreset" /> + </interface> + <interface + name="tx_cal_busy" + internal="transceiver_reset_controller_inst.tx_cal_busy" + type="conduit" + dir="end"> + <port name="tx_cal_busy" internal="tx_cal_busy" /> + </interface> + <interface + name="tx_digitalreset" + internal="transceiver_reset_controller_inst.tx_digitalreset" + type="conduit" + dir="end"> + <port name="tx_digitalreset" internal="tx_digitalreset" /> + </interface> + <interface + name="tx_ready" + internal="transceiver_reset_controller_inst.tx_ready" + type="conduit" + dir="end"> + <port name="tx_ready" internal="tx_ready" /> + </interface> + <module + name="transceiver_reset_controller_inst" + kind="altera_xcvr_reset_control" + version="15.0" + enabled="1" + autoexport="1"> + <parameter name="CHANNELS" value="12" /> + <parameter name="PLLS" value="1" /> + <parameter name="REDUCED_SIM_TIME" value="1" /> + <parameter name="RX_ENABLE" value="1" /> + <parameter name="RX_PER_CHANNEL" value="1" /> + <parameter name="SYNCHRONIZE_PLL_RESET" value="0" /> + <parameter name="SYNCHRONIZE_RESET" value="1" /> + <parameter name="SYS_CLK_IN_MHZ" value="156" /> + <parameter name="TX_ENABLE" value="1" /> + <parameter name="TX_PER_CHANNEL" value="0" /> + <parameter name="TX_PLL_ENABLE" value="1" /> + <parameter name="T_PLL_LOCK_HYST" value="100" /> + <parameter name="T_PLL_POWERDOWN" value="1000" /> + <parameter name="T_RX_ANALOGRESET" value="40" /> + <parameter name="T_RX_DIGITALRESET" value="400000" /> + <parameter name="T_TX_DIGITALRESET" value="20" /> + <parameter name="device_family" value="Arria 10" /> + <parameter name="gui_pll_cal_busy" value="0" /> + <parameter name="gui_rx_auto_reset" value="0" /> + <parameter name="gui_split_interfaces" value="0" /> + <parameter name="gui_tx_auto_reset" value="0" /> + </module> + <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> +</system> diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c6b6ace326bce5c38f8e2362498a9bf8e90fee6a --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl @@ -0,0 +1,43 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2015 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generated/sim" + +#vlib ./work/ ;# Assume library work already exists + +vmap ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/altera_xcvr_functions.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/alt_xcvr_resync.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/altera_xcvr_reset_control.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 + vcom "$IP_DIR/ip_arria10_e3sge3_transceiver_reset_controller_24.vhd" diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh new file mode 100755 index 0000000000000000000000000000000000000000..87585ed5ebe85eeff6073d768c2f89d6bf0b3355 --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/generate_ip.sh @@ -0,0 +1,44 @@ +#!/bin/bash +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2015 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# -------------------------------------------------------------------------- # +# +# Purpose: Generate IP with Qsys +# Description: +# Generate the IP in a separate generated/ subdirectory. +# +# Usage: +# +# ./generate_ip.sh +# + +# Tool settings for selected target "unb2" with arria10 +. ${RADIOHDL}/tools/quartus/set_quartus unb2a + +#qsys-generate --help + +# Only generate the source IP +# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard +qsys-generate ip_arria10_e3sge3_transceiver_reset_controller_24.qsys \ + --synthesis=VHDL \ + --simulation=VHDL \ + --output-directory=generated \ + --allow-mixed-language-simulation diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..46a59f7ae1c748b427c4bbd2e649fa81e28c38a4 --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e3sge3_transceiver_reset_controller_24 +hdl_library_clause_name = ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151 +hdl_lib_uses_synth = +hdl_lib_uses_sim = + +hdl_lib_technology = ip_arria10_e3sge3 + +modelsim_compile_ip_files = + $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl + +synth_files = + +test_bench_files = + +quartus_qip_files = + generated/ip_arria10_e3sge3_transceiver_reset_controller_24.qip diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/ip_arria10_e3sge3_transceiver_reset_controller_24.qsys b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/ip_arria10_e3sge3_transceiver_reset_controller_24.qsys new file mode 100644 index 0000000000000000000000000000000000000000..618946dc70382f3a6fcacf620e332b3319a60aa4 --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/ip_arria10_e3sge3_transceiver_reset_controller_24.qsys @@ -0,0 +1,178 @@ +<?xml version="1.0" encoding="UTF-8"?> +<system name="$${FILENAME}"> + <component + name="$${FILENAME}" + displayName="$${FILENAME}" + version="1.0" + description="" + tags="INTERNAL_COMPONENT=true" + categories="System" /> + <parameter name="bonusData"><![CDATA[bonusData +{ + element $${FILENAME} + { + datum _originalDeviceFamily + { + value = "Arria 10"; + type = "String"; + } + } + element transceiver_reset_controller_inst + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +]]></parameter> + <parameter name="clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="device" value="10AX115U4F45E3SGE3" /> + <parameter name="deviceFamily" value="Arria 10" /> + <parameter name="deviceSpeedGrade" value="3" /> + <parameter name="fabricMode" value="QSYS" /> + <parameter name="generateLegacySim" value="false" /> + <parameter name="generationId" value="0" /> + <parameter name="globalResetBus" value="false" /> + <parameter name="hdlLanguage" value="VERILOG" /> + <parameter name="hideFromIPCatalog" value="true" /> + <parameter name="lockedInterfaceDefinition" value="" /> + <parameter name="maxAdditionalLatency" value="1" /> + <parameter name="projectName" value="" /> + <parameter name="sopcBorderPoints" value="false" /> + <parameter name="systemHash" value="0" /> + <parameter name="testBenchDutName" value="" /> + <parameter name="timeStamp" value="0" /> + <parameter name="useTestBenchNamingPattern" value="false" /> + <instanceScript></instanceScript> + <interface + name="clock" + internal="transceiver_reset_controller_inst.clock" + type="clock" + dir="end"> + <port name="clock" internal="clock" /> + </interface> + <interface + name="pll_locked" + internal="transceiver_reset_controller_inst.pll_locked" + type="conduit" + dir="end"> + <port name="pll_locked" internal="pll_locked" /> + </interface> + <interface + name="pll_powerdown" + internal="transceiver_reset_controller_inst.pll_powerdown" + type="conduit" + dir="end"> + <port name="pll_powerdown" internal="pll_powerdown" /> + </interface> + <interface + name="pll_select" + internal="transceiver_reset_controller_inst.pll_select" + type="conduit" + dir="end"> + <port name="pll_select" internal="pll_select" /> + </interface> + <interface + name="reset" + internal="transceiver_reset_controller_inst.reset" + type="reset" + dir="end"> + <port name="reset" internal="reset" /> + </interface> + <interface + name="rx_analogreset" + internal="transceiver_reset_controller_inst.rx_analogreset" + type="conduit" + dir="end"> + <port name="rx_analogreset" internal="rx_analogreset" /> + </interface> + <interface + name="rx_cal_busy" + internal="transceiver_reset_controller_inst.rx_cal_busy" + type="conduit" + dir="end"> + <port name="rx_cal_busy" internal="rx_cal_busy" /> + </interface> + <interface + name="rx_digitalreset" + internal="transceiver_reset_controller_inst.rx_digitalreset" + type="conduit" + dir="end"> + <port name="rx_digitalreset" internal="rx_digitalreset" /> + </interface> + <interface + name="rx_is_lockedtodata" + internal="transceiver_reset_controller_inst.rx_is_lockedtodata" + type="conduit" + dir="end"> + <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" /> + </interface> + <interface + name="rx_ready" + internal="transceiver_reset_controller_inst.rx_ready" + type="conduit" + dir="end"> + <port name="rx_ready" internal="rx_ready" /> + </interface> + <interface + name="tx_analogreset" + internal="transceiver_reset_controller_inst.tx_analogreset" + type="conduit" + dir="end"> + <port name="tx_analogreset" internal="tx_analogreset" /> + </interface> + <interface + name="tx_cal_busy" + internal="transceiver_reset_controller_inst.tx_cal_busy" + type="conduit" + dir="end"> + <port name="tx_cal_busy" internal="tx_cal_busy" /> + </interface> + <interface + name="tx_digitalreset" + internal="transceiver_reset_controller_inst.tx_digitalreset" + type="conduit" + dir="end"> + <port name="tx_digitalreset" internal="tx_digitalreset" /> + </interface> + <interface + name="tx_ready" + internal="transceiver_reset_controller_inst.tx_ready" + type="conduit" + dir="end"> + <port name="tx_ready" internal="tx_ready" /> + </interface> + <module + name="transceiver_reset_controller_inst" + kind="altera_xcvr_reset_control" + version="15.0" + enabled="1" + autoexport="1"> + <parameter name="CHANNELS" value="24" /> + <parameter name="PLLS" value="1" /> + <parameter name="REDUCED_SIM_TIME" value="1" /> + <parameter name="RX_ENABLE" value="1" /> + <parameter name="RX_PER_CHANNEL" value="1" /> + <parameter name="SYNCHRONIZE_PLL_RESET" value="0" /> + <parameter name="SYNCHRONIZE_RESET" value="1" /> + <parameter name="SYS_CLK_IN_MHZ" value="156" /> + <parameter name="TX_ENABLE" value="1" /> + <parameter name="TX_PER_CHANNEL" value="0" /> + <parameter name="TX_PLL_ENABLE" value="1" /> + <parameter name="T_PLL_LOCK_HYST" value="100" /> + <parameter name="T_PLL_POWERDOWN" value="1000" /> + <parameter name="T_RX_ANALOGRESET" value="40" /> + <parameter name="T_RX_DIGITALRESET" value="400000" /> + <parameter name="T_TX_DIGITALRESET" value="20" /> + <parameter name="device_family" value="Arria 10" /> + <parameter name="gui_pll_cal_busy" value="0" /> + <parameter name="gui_rx_auto_reset" value="0" /> + <parameter name="gui_split_interfaces" value="0" /> + <parameter name="gui_tx_auto_reset" value="0" /> + </module> + <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> +</system> diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c11c7f1b14b0d078ff3db10a233488f5b41dd3f0 --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl @@ -0,0 +1,43 @@ +#------------------------------------------------------------------------------ +# +# Copyright (C) 2015 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +#------------------------------------------------------------------------------ + +# This file is based on generated file mentor/msim_setup.tcl. +# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl +# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl +# - replace QSYS_SIMDIR by IP_DIR +# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files. + +set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generated/sim" + +#vlib ./work/ ;# Assume library work already exists + +vmap ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 ./work/ + + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/altera_xcvr_functions.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/alt_xcvr_resync.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/altera_xcvr_reset_control.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 + vlog -sv "$IP_DIR/../altera_xcvr_reset_control_151/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 + vcom "$IP_DIR/ip_arria10_e3sge3_transceiver_reset_controller_48.vhd" diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh new file mode 100755 index 0000000000000000000000000000000000000000..6b0e35088a911424c9563647f976d42facc6fbdd --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/generate_ip.sh @@ -0,0 +1,44 @@ +#!/bin/bash +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2015 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# -------------------------------------------------------------------------- # +# +# Purpose: Generate IP with Qsys +# Description: +# Generate the IP in a separate generated/ subdirectory. +# +# Usage: +# +# ./generate_ip.sh +# + +# Tool settings for selected target "unb2" with arria10 +. ${RADIOHDL}/tools/quartus/set_quartus unb2a + +#qsys-generate --help + +# Only generate the source IP +# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard +qsys-generate ip_arria10_e3sge3_transceiver_reset_controller_48.qsys \ + --synthesis=VHDL \ + --simulation=VHDL \ + --output-directory=generated \ + --allow-mixed-language-simulation diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..a677a2d9dfb1220cbe6e79273c3336414219856b --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg @@ -0,0 +1,16 @@ +hdl_lib_name = ip_arria10_e3sge3_transceiver_reset_controller_48 +hdl_library_clause_name = ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151 +hdl_lib_uses_synth = +hdl_lib_uses_sim = + +hdl_lib_technology = ip_arria10_e3sge3 + +modelsim_compile_ip_files = + $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl + +synth_files = + +test_bench_files = + +quartus_qip_files = + generated/ip_arria10_e3sge3_transceiver_reset_controller_48.qip diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/ip_arria10_e3sge3_transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/ip_arria10_e3sge3_transceiver_reset_controller_48.qsys new file mode 100644 index 0000000000000000000000000000000000000000..7e55942346afad2056343e7bdbbb2c764e579005 --- /dev/null +++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/ip_arria10_e3sge3_transceiver_reset_controller_48.qsys @@ -0,0 +1,178 @@ +<?xml version="1.0" encoding="UTF-8"?> +<system name="$${FILENAME}"> + <component + name="$${FILENAME}" + displayName="$${FILENAME}" + version="1.0" + description="" + tags="INTERNAL_COMPONENT=true" + categories="System" /> + <parameter name="bonusData"><![CDATA[bonusData +{ + element $${FILENAME} + { + datum _originalDeviceFamily + { + value = "Arria 10"; + type = "String"; + } + } + element transceiver_reset_controller_inst + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +]]></parameter> + <parameter name="clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="device" value="10AX115U4F45E3SGE3" /> + <parameter name="deviceFamily" value="Arria 10" /> + <parameter name="deviceSpeedGrade" value="3" /> + <parameter name="fabricMode" value="QSYS" /> + <parameter name="generateLegacySim" value="false" /> + <parameter name="generationId" value="0" /> + <parameter name="globalResetBus" value="false" /> + <parameter name="hdlLanguage" value="VERILOG" /> + <parameter name="hideFromIPCatalog" value="true" /> + <parameter name="lockedInterfaceDefinition" value="" /> + <parameter name="maxAdditionalLatency" value="1" /> + <parameter name="projectName" value="" /> + <parameter name="sopcBorderPoints" value="false" /> + <parameter name="systemHash" value="0" /> + <parameter name="testBenchDutName" value="" /> + <parameter name="timeStamp" value="0" /> + <parameter name="useTestBenchNamingPattern" value="false" /> + <instanceScript></instanceScript> + <interface + name="clock" + internal="transceiver_reset_controller_inst.clock" + type="clock" + dir="end"> + <port name="clock" internal="clock" /> + </interface> + <interface + name="pll_locked" + internal="transceiver_reset_controller_inst.pll_locked" + type="conduit" + dir="end"> + <port name="pll_locked" internal="pll_locked" /> + </interface> + <interface + name="pll_powerdown" + internal="transceiver_reset_controller_inst.pll_powerdown" + type="conduit" + dir="end"> + <port name="pll_powerdown" internal="pll_powerdown" /> + </interface> + <interface + name="pll_select" + internal="transceiver_reset_controller_inst.pll_select" + type="conduit" + dir="end"> + <port name="pll_select" internal="pll_select" /> + </interface> + <interface + name="reset" + internal="transceiver_reset_controller_inst.reset" + type="reset" + dir="end"> + <port name="reset" internal="reset" /> + </interface> + <interface + name="rx_analogreset" + internal="transceiver_reset_controller_inst.rx_analogreset" + type="conduit" + dir="end"> + <port name="rx_analogreset" internal="rx_analogreset" /> + </interface> + <interface + name="rx_cal_busy" + internal="transceiver_reset_controller_inst.rx_cal_busy" + type="conduit" + dir="end"> + <port name="rx_cal_busy" internal="rx_cal_busy" /> + </interface> + <interface + name="rx_digitalreset" + internal="transceiver_reset_controller_inst.rx_digitalreset" + type="conduit" + dir="end"> + <port name="rx_digitalreset" internal="rx_digitalreset" /> + </interface> + <interface + name="rx_is_lockedtodata" + internal="transceiver_reset_controller_inst.rx_is_lockedtodata" + type="conduit" + dir="end"> + <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" /> + </interface> + <interface + name="rx_ready" + internal="transceiver_reset_controller_inst.rx_ready" + type="conduit" + dir="end"> + <port name="rx_ready" internal="rx_ready" /> + </interface> + <interface + name="tx_analogreset" + internal="transceiver_reset_controller_inst.tx_analogreset" + type="conduit" + dir="end"> + <port name="tx_analogreset" internal="tx_analogreset" /> + </interface> + <interface + name="tx_cal_busy" + internal="transceiver_reset_controller_inst.tx_cal_busy" + type="conduit" + dir="end"> + <port name="tx_cal_busy" internal="tx_cal_busy" /> + </interface> + <interface + name="tx_digitalreset" + internal="transceiver_reset_controller_inst.tx_digitalreset" + type="conduit" + dir="end"> + <port name="tx_digitalreset" internal="tx_digitalreset" /> + </interface> + <interface + name="tx_ready" + internal="transceiver_reset_controller_inst.tx_ready" + type="conduit" + dir="end"> + <port name="tx_ready" internal="tx_ready" /> + </interface> + <module + name="transceiver_reset_controller_inst" + kind="altera_xcvr_reset_control" + version="15.0" + enabled="1" + autoexport="1"> + <parameter name="CHANNELS" value="48" /> + <parameter name="PLLS" value="1" /> + <parameter name="REDUCED_SIM_TIME" value="1" /> + <parameter name="RX_ENABLE" value="1" /> + <parameter name="RX_PER_CHANNEL" value="1" /> + <parameter name="SYNCHRONIZE_PLL_RESET" value="0" /> + <parameter name="SYNCHRONIZE_RESET" value="1" /> + <parameter name="SYS_CLK_IN_MHZ" value="156" /> + <parameter name="TX_ENABLE" value="1" /> + <parameter name="TX_PER_CHANNEL" value="0" /> + <parameter name="TX_PLL_ENABLE" value="1" /> + <parameter name="T_PLL_LOCK_HYST" value="100" /> + <parameter name="T_PLL_POWERDOWN" value="1000" /> + <parameter name="T_RX_ANALOGRESET" value="40" /> + <parameter name="T_RX_DIGITALRESET" value="400000" /> + <parameter name="T_TX_DIGITALRESET" value="20" /> + <parameter name="device_family" value="Arria 10" /> + <parameter name="gui_pll_cal_busy" value="0" /> + <parameter name="gui_rx_auto_reset" value="0" /> + <parameter name="gui_split_interfaces" value="0" /> + <parameter name="gui_tx_auto_reset" value="0" /> + </module> + <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> +</system>