diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index df033c185178a5281d5daf02b90a45030cda8f84..8965e03a921531a664ee9aee8e1d5394a47e397e 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -103,7 +103,7 @@ BEGIN
v.out_of := q_reg.s_in_of;
v.s_in_sosi := in_sosi;
v.s_in_of := in_of;
- IF in_bsn_wr = '1' THEN
+ IF in_bsn_wr = '0' THEN
v.s_bsn_wr := '1';
END IF;
@@ -112,7 +112,7 @@ BEGIN
WHEN RESET =>
v.s_adr := c_max_adr-1; -- when there is a reset the fifo in io_ddr always needs the first out_sosi.valid to stop flushing the data so the first data word always gets lost. if s_adr is set to 0 after a restart the word from s_adr 1 will be put at address 0 in memory.
- IF q_reg.s_bsn_wr = '1' THEN
+ IF in_bsn_wr = '1' AND v.s_bsn_wr = '1' THEN
v.out_bsn_adr := v.s_adr;
v.s_bsn_wr := '0';
END IF;
@@ -121,7 +121,7 @@ BEGIN
WHEN COUNTING =>
v.s_adr := q_reg.s_adr+1;
- IF q_reg.s_bsn_wr = '1' THEN
+ IF in_bsn_wr = '1' AND v.s_bsn_wr = '1' THEN
v.out_bsn_adr := v.s_adr;
v.s_bsn_wr := '0';
END IF;
@@ -130,7 +130,7 @@ BEGIN
WHEN MAX =>
v.s_adr := 0;
- IF q_reg.s_bsn_wr = '1' THEN
+ IF in_bsn_wr = '1' AND v.s_bsn_wr = '1' THEN
v.out_bsn_adr := v.s_adr;
v.s_bsn_wr := '0';
END IF;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 7ed26c2b13a0638b4ea733f32d1604979f59fdac..1816f41494c2e4058037c02eb47b921c18cb6547 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -45,7 +45,7 @@ ENTITY ddrctrl_input_repack IS
in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); -- input data
in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); -- input bsn
in_stop : IN STD_LOGIC := '0';
- in_adr : IN NATURAL;
+ in_adr : IN NATURAL;
out_of : OUT NATURAL := 0; -- amount of internal overflow this output
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
out_bsn_ds : OUT NATURAL := 0;
@@ -70,11 +70,11 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
c_v : STD_LOGIC_VECTOR(k_c_v_w-1 DOWNTO 0); -- the vector that stores the input data until the data is put into the output data vector
c_v_count : NATURAL; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
out_data_count : NATURAL; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
- out_bsn_written : STD_LOGIC;
- out_of : NATURAL;
- out_sosi : t_dp_sosi;
- out_bsn_ds : NATURAL;
- out_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ out_bsn_written : STD_LOGIC; -- this signal gets high ones the out_bsn signal is updated, this is so in ddrctrl_input_address_counter the right address can be linked with the out_bsn signal
+ out_of : NATURAL; -- this is the amount of bits that the first data word(168) is shifted from the first bit in the data word(576)
+ out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
+ out_bsn_ds : NATURAL; -- this is the amount of bits that the data corresponding to out_bsn is shifted from the first bit in that data word
+ out_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); -- this is the bsn corresponding to the data in memory
END RECORD;
CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, '0', 0, c_dp_sosi_init, 0, (OTHERS => '0'));
@@ -105,13 +105,13 @@ BEGIN
-- BSN_INPUT
IF in_adr = 0 AND q_reg.out_bsn_written = '0' THEN
- v.out_bsn := in_bsn;
+ v.out_bsn := in_bsn; -- a bsn number is saved when adr ~ 0
IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
- v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;
+ v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
ELSE
- v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of;
+ v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
END IF;
- v.out_bsn_written := '1';
+ v.out_bsn_written := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
END IF;
IF rst = '1' THEN
@@ -134,14 +134,15 @@ BEGIN
v.out_sosi.valid := '1'; -- out_sosi.valid 1
v.out_data_count := q_reg.out_data_count+1; -- increase the counter of out_sosi.data with 1
+ -- BSN_INPUT
IF in_adr = 0 AND q_reg.out_bsn_written = '0' THEN
- v.out_bsn := in_bsn;
+ v.out_bsn := in_bsn; -- a bsn number is saved when adr ~ 0
IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
- v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;
+ v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
ELSE
- v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of;
+ v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
END IF;
- v.out_bsn_written := '1';
+ v.out_bsn_written := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
END IF;
IF rst = '1' THEN
@@ -166,13 +167,13 @@ BEGIN
-- BSN_INPUT
IF in_adr = 0 AND q_reg.out_bsn_written = '0' THEN
- v.out_bsn := in_bsn;
+ v.out_bsn := in_bsn; -- a bsn number is saved when adr ~ 0
IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
- v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w;
+ v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
ELSE
- v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of;
+ v.out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
END IF;
- v.out_bsn_written := '1';
+ v.out_bsn_written := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
END IF;
IF rst = '1' THEN