diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index c3fe47955074424a962d7a848e96d48ac05ce5f4..74a150e78b3b1876fdf0ad8c23d5de54c90c067f 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -132,6 +132,7 @@ test_bench_files =
$UNB/Firmware/modules/dp/tb/vhdl/tb_dp_deinterleave.vhd
$UNB/Firmware/modules/dp/tb/vhdl/tb_dp_distribute.vhd
$UNB/Firmware/modules/dp/tb/vhdl/tb_dp_fifo_fill.vhd
+ tb/vhdl/tb_dp_fifo_fill_sc.vhd
$UNB/Firmware/modules/dp/tb/vhdl/tb_dp_fifo_info.vhd
$UNB/Firmware/modules/dp/tb/vhdl/tb_dp_fifo_dc.vhd
$UNB/Firmware/modules/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e5253fa3ab3339cdf87479beffbcb8ed33a52e68
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
@@ -0,0 +1,242 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Test bench for dp_fifo_fill_sc
+-- Description:
+-- The tb verifies the DUT using the old style proc_dp_count_en() with
+-- various stimuli for cnt_en and out_siso.ready.
+-- Remark:
+-- The frame level flow control via out_siso.xon is not tested, because it is
+-- fixed at '1'.
+-- Usage:
+-- > as 10
+-- > run -all
+-- . signal tb_end will stop the simulation by stopping the clk
+-- . the tb is self checking
+--
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+ENTITY tb_dp_fifo_fill_sc IS
+ GENERIC (
+ -- Try FIFO settings
+ g_dut_use_bsn : BOOLEAN := FALSE;
+ g_dut_use_empty : BOOLEAN := FALSE;
+ g_dut_use_channel : BOOLEAN := FALSE;
+ g_dut_use_sync : BOOLEAN := FALSE;
+ g_dut_fifo_rl : NATURAL := 1; -- internal RL, use 0 for look ahead FIFO, default 1 for normal FIFO
+ g_dut_fifo_size : NATURAL := 64;
+ g_dut_fifo_fill : NATURAL := 64 -- selectable >= 0 for dp_fifo_fill
+ );
+END tb_dp_fifo_fill_sc;
+
+
+ARCHITECTURE tb OF tb_dp_fifo_fill_sc IS
+
+ -- See tb_dp_pkg.vhd for explanation and run time
+
+ -- DUT
+ CONSTANT c_dut_in_latency : NATURAL := 1; -- fixed for dp_fifo_fill
+ CONSTANT c_dut_out_latency : NATURAL := 1; -- fixed for dp_fifo_fill, only internally dp_fifo_fill may use RL=0 or 1 dependent on g_dut_fifo_rl
+
+ -- Stimuli
+ CONSTANT c_tx_latency : NATURAL := c_dut_in_latency; -- TX ready latency of TB
+ CONSTANT c_tx_void : NATURAL := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ CONSTANT c_tx_offset_sop : NATURAL := 3;
+ CONSTANT c_tx_period_sop : NATURAL := 7; -- sop in data valid cycle 3, 10, 17, ...
+ CONSTANT c_tx_offset_eop : NATURAL := 9; -- eop in data valid cycle 9, 16, 23, ...
+ CONSTANT c_tx_period_eop : NATURAL := c_tx_period_sop;
+ CONSTANT c_tx_offset_sync : NATURAL := 3; -- sync in data valid cycle 3, 20, 37, ...
+ CONSTANT c_tx_period_sync : NATURAL := 17;
+ CONSTANT c_rx_latency : NATURAL := c_dut_out_latency; -- RX ready latency from DUT
+ CONSTANT c_verify_en_wait : NATURAL := 20+g_dut_fifo_fill; -- wait some cycles before asserting verify enable
+ CONSTANT c_verify_data_en : BOOLEAN := c_tx_offset_eop-c_tx_offset_sop = c_tx_period_sop-1;
+
+ CONSTANT c_bsn_offset : NATURAL := 1;
+ CONSTANT c_empty_offset : NATURAL := 2;
+ CONSTANT c_channel_offset : NATURAL := 3;
+
+ CONSTANT c_random_w : NATURAL := 19;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC;
+ SIGNAL sync : STD_LOGIC;
+ SIGNAL lfsr1 : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL lfsr2 : STD_LOGIC_VECTOR(c_random_w DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL cnt_dat : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
+ SIGNAL cnt_val : STD_LOGIC;
+ SIGNAL cnt_en : STD_LOGIC;
+
+ SIGNAL tx_data : t_dp_data_arr(0 TO c_tx_latency + c_tx_void) := (OTHERS=>(OTHERS=>'0'));
+ SIGNAL tx_val : STD_LOGIC_VECTOR(0 TO c_tx_latency + c_tx_void) := (OTHERS=>'0');
+
+ SIGNAL in_ready : STD_LOGIC;
+ SIGNAL in_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_bsn : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_sync : STD_LOGIC;
+ SIGNAL in_val : STD_LOGIC;
+ SIGNAL in_sop : STD_LOGIC;
+ SIGNAL in_eop : STD_LOGIC;
+
+ SIGNAL wr_ful : STD_LOGIC;
+ SIGNAL in_siso : t_dp_siso;
+ SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL out_siso : t_dp_siso;
+ SIGNAL out_sosi : t_dp_sosi;
+
+ SIGNAL out_ready : STD_LOGIC;
+ SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rx_latency);
+ SIGNAL out_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
+ SIGNAL out_bsn : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_sync : STD_LOGIC;
+ SIGNAL out_val : STD_LOGIC;
+ SIGNAL out_sop : STD_LOGIC;
+ SIGNAL out_eop : STD_LOGIC;
+ SIGNAL prev_out_data : STD_LOGIC_VECTOR(out_data'RANGE);
+
+ SIGNAL state : t_dp_state_enum;
+
+ SIGNAL verify_en : STD_LOGIC;
+ SIGNAL verify_done : STD_LOGIC;
+
+ SIGNAL exp_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := TO_UVEC(15000, c_dp_data_w);
+
+BEGIN
+
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
+ rst <= '1', '0' AFTER clk_period*7;
+
+ -- Sync interval
+ proc_dp_sync_interval(clk, sync);
+
+ -- Input data
+ cnt_val <= in_ready AND cnt_en;
+
+ proc_dp_cnt_dat(rst, clk, cnt_val, cnt_dat);
+ proc_dp_tx_data(c_tx_latency, rst, clk, cnt_val, cnt_dat, tx_data, tx_val, in_data, in_val);
+ proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync);
+ proc_dp_tx_ctrl(c_tx_offset_sop, c_tx_period_sop, in_data, in_val, in_sop);
+ proc_dp_tx_ctrl(c_tx_offset_eop, c_tx_period_eop, in_data, in_val, in_eop);
+
+ in_bsn <= INCR_UVEC(in_data, c_bsn_offset);
+ in_empty <= INCR_UVEC(in_data, c_empty_offset);
+ in_channel <= INCR_UVEC(in_data, c_channel_offset);
+
+ -- Stimuli control
+ proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_end, cnt_en);
+ proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
+
+ -- Output verify
+ proc_dp_verify_en(c_verify_en_wait, rst, clk, sync, verify_en);
+
+ gen_verify_data : IF c_verify_data_en=TRUE GENERATE
+ proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
+ END GENERATE;
+ ASSERT c_verify_data_en=TRUE REPORT "proc_dp_verify_data() can not verify the data if it is not continuous" SEVERITY WARNING;
+
+ proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
+ proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
+ proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data, out_val, out_eop);
+
+ gen_verify_sync : IF g_dut_use_sync=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", clk, verify_en, out_data, out_val, out_sync);
+ END GENERATE;
+
+ gen_verify_bsn : IF g_dut_use_bsn=TRUE GENERATE
+ proc_dp_verify_other_sosi("bsn", INCR_UVEC(out_data, c_bsn_offset), clk, verify_en, out_bsn);
+ END GENERATE;
+
+ gen_verify_empty : IF g_dut_use_empty=TRUE GENERATE
+ proc_dp_verify_other_sosi("empty", INCR_UVEC(out_data, c_empty_offset), clk, verify_en, out_empty);
+ END GENERATE;
+
+ gen_verify_channel : IF g_dut_use_channel=TRUE GENERATE
+ proc_dp_verify_other_sosi("channel", INCR_UVEC(out_data, c_channel_offset), clk, verify_en, out_channel);
+ END GENERATE;
+
+ -- Check that the test has ran at all
+ proc_dp_verify_value(e_at_least, clk, verify_done, exp_data, out_data);
+
+ ------------------------------------------------------------------------------
+ -- DUT dp_fifo_fill
+ ------------------------------------------------------------------------------
+
+ -- map sl, slv to record
+ in_ready <= in_siso.ready; -- SISO
+ in_sosi.data(c_dp_data_w-1 DOWNTO 0) <= in_data; -- SOSI
+ in_sosi.bsn(c_dp_bsn_w-1 DOWNTO 0) <= in_bsn(c_dp_bsn_w-1 DOWNTO 0);
+ in_sosi.empty <= in_empty(c_dp_empty_w-1 DOWNTO 0);
+ in_sosi.channel <= in_channel(c_dp_channel_w-1 DOWNTO 0);
+ in_sosi.sync <= in_sync;
+ in_sosi.valid <= in_val;
+ in_sosi.sop <= in_sop;
+ in_sosi.eop <= in_eop;
+
+ out_siso.ready <= out_ready; -- SISO
+ out_siso.xon <= '1';
+ out_data <= out_sosi.data(c_dp_data_w-1 DOWNTO 0); -- SOSI
+ out_bsn(c_dp_bsn_w-1 DOWNTO 0) <= out_sosi.bsn(c_dp_bsn_w-1 DOWNTO 0);
+ out_empty(c_dp_empty_w-1 DOWNTO 0) <= out_sosi.empty;
+ out_channel(c_dp_channel_w-1 DOWNTO 0) <= out_sosi.channel;
+ out_sync <= out_sosi.sync;
+ out_val <= out_sosi.valid;
+ out_sop <= out_sosi.sop;
+ out_eop <= out_sosi.eop;
+
+ dut : ENTITY work.dp_fifo_fill_sc
+ GENERIC MAP (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => FALSE,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ wr_ful => wr_ful,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
+
+END tb;