diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
index c783900be7f683fbbad037a998ad68f9805a8af3..6d72d4555e4dd97312560a7867b771fb13e7a85b 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
@@ -99,6 +99,7 @@ ARCHITECTURE tb OF tb_tr_10GbE IS
-- Clocks and reset
SIGNAL tx_end_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL tx_end : STD_LOGIC;
SIGNAL rx_end : STD_LOGIC;
SIGNAL cal_clk : STD_LOGIC := '1'; -- calibration clock
SIGNAL mm_clk : STD_LOGIC; -- memory-mapped bus clock
@@ -354,25 +355,20 @@ BEGIN
rx_end => rx_end
);
END GENERATE;
-
- p_tb_end : PROCESS
- BEGIN
- tb_end <= '0';
- rx_end <= '0';
- WAIT UNTIL andv(tx_end_arr)='1';
- proc_common_wait_some_cycles(dp_clk, 1000);
- rx_end <= '1';
- proc_common_wait_some_cycles(dp_clk, 100);
- --proc_common_wait_some_cycles(dp_clk, 10000); -- uncomment to simulate somewhat longer without tx packet data
-
- -- Stop the simulation
- tb_end <= '1';
- IF g_tb_end=FALSE THEN
- REPORT "Tb Simulation finished." SEVERITY NOTE;
- ELSE
- REPORT "Tb Simulation finished." SEVERITY FAILURE;
- END IF;
- WAIT;
- END PROCESS;
+ -- Stop the simulation
+ tx_end <= andv(tx_end_arr);
+
+ u_simulation_end : ENTITY tech_mac_10g_lib.tb_tech_mac_10g_simulation_end
+ GENERIC MAP (
+ g_tb_end => g_tb_end,
+ g_nof_clk_to_rx_end => 1000
+ )
+ PORT MAP (
+ clk => dp_clk,
+ tx_end => tx_end,
+ rx_end => rx_end,
+ tb_end => tb_end
+ );
+
END tb;
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
index f57363aeda3bca856bee79381ee88cd3087e4a8e..c4b39e6dd8c5e46c50c91368b4135a69a405e03f 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
@@ -101,6 +101,7 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
SIGNAL total_header : t_network_total_header := c_network_total_header_ones; -- default fill all fields with value 1
-- Clocks and reset
+ SIGNAL tx_end : STD_LOGIC := '0';
SIGNAL rx_end : STD_LOGIC := '0';
SIGNAL cal_clk : STD_LOGIC := '1'; -- calibration clock
SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock
@@ -208,7 +209,7 @@ BEGIN
tx_siso => tx_siso,
tx_sosi => tx_sosi,
link_fault => link_fault,
- tx_end => rx_end
+ tx_end => tx_end
);
-- Generate reference clocks
@@ -392,21 +393,17 @@ BEGIN
rx_end => rx_end
);
- p_tb_end : PROCESS
- BEGIN
- tb_end <= '0';
- WAIT UNTIL rx_end='1';
- proc_common_wait_some_cycles(tb_tx_clk, 100);
- --proc_common_wait_some_cycles(tb_tx_clk, 10000); -- uncomment to simulate somewhat longer without tx packet data
-
- -- Stop the simulation
- tb_end <= '1';
- IF g_tb_end=FALSE THEN
- REPORT "Tb Simulation finished." SEVERITY NOTE;
- ELSE
- REPORT "Tb Simulation finished." SEVERITY FAILURE;
- END IF;
- WAIT;
- END PROCESS;
+ -- Stop the simulation
+ u_simulation_end : ENTITY tech_mac_10g_lib.tb_tech_mac_10g_simulation_end
+ GENERIC MAP (
+ g_tb_end => g_tb_end,
+ g_nof_clk_to_rx_end => 1000
+ )
+ PORT MAP (
+ clk => tb_tx_clk,
+ tx_end => tx_end,
+ rx_end => rx_end,
+ tb_end => tb_end
+ );
END tb;
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index bfb3906b3b06722b25beba1f9aef6ee8b92cf55e..c94bb8f787060af40746225a03e231bdc15bb63a 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -20,6 +20,7 @@ test_bench_files =
tb_tech_mac_10g_link_connect.vhd
tb_tech_mac_10g_verify_rx_at_eop.vhd
tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
+ tb_tech_mac_10g_simulation_end.vhd
tb_tech_mac_10g.vhd
tb_tb_tech_mac_10g.vhd
diff --git a/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd b/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
index 188fab316ae974d3466162dcbb831bd3e01fd87c..cc1c453bc81f1b3582bfb58f3d766b84a2635711 100644
--- a/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
@@ -37,17 +37,27 @@ END tb_tb_tech_mac_10g;
ARCHITECTURE tb OF tb_tb_tech_mac_10g IS
+ CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
BEGIN
-- g_technology : NATURAL := c_tech_select_default;
+-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
-- g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols
-- c_tb_tech_mac_10g_data_type_counter
- u_no_dut_counter : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, TRUE, c_tb_tech_mac_10g_data_type_counter);
- u_no_dut_symbols : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, TRUE, c_tb_tech_mac_10g_data_type_symbols);
+ u_no_dut_counter : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, FALSE, TRUE, c_tb_tech_mac_10g_data_type_counter) PORT MAP (tb_end_vec(0));
+ u_no_dut_symbols : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, FALSE, TRUE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(1));
- u_tech_mac_10g_counter : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, FALSE, c_tb_tech_mac_10g_data_type_counter);
- u_tech_mac_10g_symbols : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, FALSE, c_tb_tech_mac_10g_data_type_symbols);
+ u_tech_mac_10g_counter : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, c_tb_tech_mac_10g_data_type_counter) PORT MAP (tb_end_vec(2));
+ u_tech_mac_10g_symbols : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(3));
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end_vec=c_tb_end_vec;
+ REPORT "Multi tb simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
END tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
index ba696723ac5da8dc98216cc547fad7d8084caf1d..71d50f9d60c9b0458afe34def809b08ac7ffe273 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
@@ -48,11 +48,15 @@ ENTITY tb_tech_mac_10g IS
-- Test bench control parameters
GENERIC (
g_technology : NATURAL := c_tech_select_default;
+ g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
-- g_data_type = c_tb_tech_mac_10g_data_type_symbols = 0
-- g_data_type = c_tb_tech_mac_10g_data_type_counter = 1
g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_counter --c_tb_tech_mac_10g_data_type_symbols
);
+ PORT (
+ tb_end : OUT STD_LOGIC
+ );
END tb_tech_mac_10g;
@@ -79,8 +83,8 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
SIGNAL total_header : t_network_total_header := c_network_total_header_ones; -- default fill all fields with value 1
-- Clocks and reset
+ SIGNAL tx_end : STD_LOGIC := '0';
SIGNAL rx_end : STD_LOGIC := '0';
- SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock
SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk
SIGNAL clk_312 : STD_LOGIC := '1'; -- 312.5 MHz
@@ -124,8 +128,8 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
BEGIN
- clk_156 <= NOT clk_156 OR tb_end AFTER clk_156_period/2;
- clk_312 <= NOT clk_312 OR tb_end AFTER clk_156_period/4;
+ clk_156 <= NOT clk_156 AFTER clk_156_period/2;
+ clk_312 <= NOT clk_312 AFTER clk_156_period/4;
tx_ref_clk_156 <= clk_156; -- mac_10g tx reference clock
tx_ref_clk_312 <= clk_312;
rx_phy_clk_156 <= clk_156; -- use clk_156 to model PHY
@@ -151,7 +155,7 @@ BEGIN
g_src_mac => c_src_mac
)
PORT MAP (
- tb_end => tb_end,
+ tb_end => rx_end,
mm_clk => mm_clk,
mm_rst => mm_rst,
mm_init => mm_init,
@@ -172,7 +176,7 @@ BEGIN
tx_siso => tx_siso,
tx_sosi => tx_sosi,
link_fault => OPEN,
- tx_end => rx_end
+ tx_end => tx_end
);
no_dut : IF g_no_dut=TRUE GENERATE
@@ -268,13 +272,16 @@ BEGIN
);
-- Stop the simulation
- p_tb_end : PROCESS
- BEGIN
- WAIT UNTIL rx_end='1';
- proc_common_wait_some_cycles(clk_156, 100);
- tb_end <= '1';
- ASSERT FALSE REPORT "Simulation finished." SEVERITY NOTE;
- WAIT;
- END PROCESS;
+ u_simulation_end : ENTITY work.tb_tech_mac_10g_simulation_end
+ GENERIC MAP (
+ g_tb_end => g_tb_end,
+ g_nof_clk_to_rx_end => 1000
+ )
+ PORT MAP (
+ clk => clk_156,
+ tx_end => tx_end,
+ rx_end => rx_end,
+ tb_end => tb_end
+ );
END tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8c4e47d9c06cb1dc32aef02ce93c74cd7e7eee44
--- /dev/null
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
@@ -0,0 +1,68 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Reusable test bench end control.
+-- Description:
+-- Especially suitable for the tb that reuse the tb_tech_mac_10g_* stimuli
+-- components and verification components.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+
+ENTITY tb_tech_mac_10g_simulation_end IS
+ GENERIC (
+ g_tb_end : BOOLEAN := TRUE;
+ g_nof_clk_to_rx_end : NATURAL := 1000
+ );
+ PORT (
+ clk : IN STD_LOGIC;
+ tx_end : IN STD_LOGIC;
+ rx_end : OUT STD_LOGIC;
+ tb_end : OUT STD_LOGIC
+ );
+END tb_tech_mac_10g_simulation_end;
+
+ARCHITECTURE tb OF tb_tech_mac_10g_simulation_end IS
+BEGIN
+
+ p_tb_end : PROCESS
+ BEGIN
+ tb_end <= '0';
+ rx_end <= '0';
+ WAIT UNTIL tx_end='1';
+ proc_common_wait_some_cycles(clk, g_nof_clk_to_rx_end);
+ rx_end <= '1';
+ proc_common_wait_some_cycles(clk, 100);
+
+ -- Stop the simulation
+ tb_end <= '1';
+ IF g_tb_end=FALSE THEN
+ REPORT "Tb simulation finished." SEVERITY NOTE;
+ ELSE
+ REPORT "Tb simulation finished." SEVERITY FAILURE;
+ END IF;
+ WAIT;
+ END PROCESS;
+
+END tb;