diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd index 00f3c7f77902d0396c647efcc8e936c4eeeec3e6..713a076bafdea9b2bc0346797ea45a4e1551446c 100644 --- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd +++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd @@ -757,9 +757,9 @@ BEGIN -- derive MAC, IP and UDP Port from ID id_backplane <= RESIZE_UVEC(ID(c_sdp_W_gn_id-1 DOWNTO 2), c_byte_w); id_eth <= RESIZE_UVEC(ID(1 DOWNTO 0) & TO_UVEC(0, 2), c_byte_w); - eth_src_mac <= x"00228608" & id_backplane & INCR_UVEC(id_eth, 0); -- Interface id = 0 - ip_src_addr <= x"C0A8" & id_backplane & INCR_UVEC(id_eth, 1); -- Interface id = 0 - udp_src_port <= x"D0" & ID; + eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & id_backplane & INCR_UVEC(id_eth, 0); -- Interface id = 0 + ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_eth, 1); -- Interface id = 0 + udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID; -- Beamformers gen_bf : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd index 34652ab6913ec7f30af4538f59f3c8e142464ccd..025eed1369793e16dee78c209f41eb8fb9758064 100644 --- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd +++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd @@ -76,6 +76,9 @@ ARCHITECTURE str OF sdp_beamformer_output IS CONSTANT c_data_w : NATURAL := c_nof_complex*c_sdp_W_beamlet; --16b CONSTANT c_beamlet_id : NATURAL := g_beamset_id * c_sdp_S_sub_bf; + + -- c_fifo_fill must be the exact size of a packet such that no packet gets stuck in the FIFO or the FIFO gets read out too soon. + -- For packets of variable length, dp_fifo_fill_eop must be used. In this case we can use the standard fill fifo. CONSTANT c_fifo_fill : NATURAL := c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block / 4; -- Size of packet: 4 beamlets fit in 1 64bit longword CONSTANT c_fifo_size : NATURAL := c_fifo_fill*2; -- Make fifo size large enough for adding header and muxing beamsets. diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd index f62cfa0e4480fb2d312ee6818b9baa181a4ee04d..2668b93b27041cb0af04bc4e7c717d0028f6279d 100644 --- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd +++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd @@ -143,7 +143,11 @@ PACKAGE sdp_pkg is CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1; CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz)); - -- 10GbE offload + -- 10GbE offload (cep = central processor) + CONSTANT c_sdp_cep_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node + CONSTANT c_sdp_cep_ip_src_addr_31_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"C0A8"; -- 31:16, 15:8 = backplane, 7:0 = node + 1 = 192.168.xx.yy + CONSTANT c_sdp_cep_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D0"; -- 15:8, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0]) + CONSTANT c_sdp_cep_nof_blocks_per_packet : NATURAL := 4; CONSTANT c_sdp_cep_nof_beamlets_per_block : NATURAL := c_sdp_N_pol * c_sdp_S_sub_bf; CONSTANT c_sdp_cep_nof_hdr_fields : NATURAL := 3+12+4+18+1; -- 592b; 9.25 64b words diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd index 2b2f4c0b71fcaf11fde263baa4781262131a1905..b84e35a07c23a3a4c48d95ecd22b51c2b2e00254 100644 --- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd +++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd @@ -252,8 +252,8 @@ BEGIN exp_size <= g_pkt_len; proc_dp_verify_block_size(exp_size, clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, cnt_size); - - -- Verify output ready latency + + -- Verify output ready latency between dut siso ready and sink in valid. proc_dp_verify_valid(clk, verify_en_valid, stimuli_src_in.ready, prev_verify_snk_out.ready, verify_snk_in.valid); p_verify_xonoff : PROCESS