From e78e0cec8846390e416df70b285027b0da75c460 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 10 Mar 2020 14:13:43 +0100
Subject: [PATCH] Added Ring interface Two 40 GbE IPs are now added and
connected to RING_0 and RING_1
---
.../hardware/unb2b/board_spec.xml | 7 +
.../ta2_unb2b_bsp/hardware/unb2b/flat.qsf | 198 ++++++
.../ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg | 37 +
.../hardware/unb2b/ip/freeze_wrapper.v | 33 +-
.../hardware/unb2b/ip/pr_region.v | 34 +-
.../ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd | 2 +-
.../ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl | 200 ------
.../ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl~ | 200 ------
.../ta2_unb2b_10GbE_ip_wrapper.vhd | 114 ---
.../unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg | 32 +
.../ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd | 673 +++++++++---------
.../ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl | 213 ------
.../ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl~ | 213 ------
.../ta2_unb2b_40GbE_ip_wrapper.vhd | 114 ---
.../ta2_unb2b_bsp/hardware/unb2b/top.vhd | 179 +++--
.../hardware/unb2b/top_components_pkg.vhd | 16 +-
16 files changed, 813 insertions(+), 1452 deletions(-)
create mode 100644 applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg
delete mode 100644 applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl
delete mode 100644 applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl~
delete mode 100644 applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_ip_wrapper.vhd
create mode 100644 applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg
delete mode 100644 applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl
delete mode 100644 applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl~
delete mode 100644 applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_ip_wrapper.vhd
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml
index 05341e43b5..e77390839e 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml
@@ -31,6 +31,13 @@
<interface name="board" port="kernel_stream_snk_10GbE" type="streamsink" width="72" chan_id="kernel_output_10GbE"/>
<interface name="board" port="kernel_stream_src_40GbE" type="streamsource" width="264" chan_id="kernel_input_40GbE"/>
<interface name="board" port="kernel_stream_snk_40GbE" type="streamsink" width="264" chan_id="kernel_output_40GbE"/>
+
+ <!-- Ring interface, ring_0 is to PN to the left. Ring_1 is to PN to the right -->
+ <interface name="board" port="kernel_stream_src_40GbE_ring_0" type="streamsource" width="264" chan_id="kernel_input_40GbE_ring_0"/>
+ <interface name="board" port="kernel_stream_snk_40GbE_ring_0" type="streamsink" width="264" chan_id="kernel_output_40GbE_ring_0"/>
+ <interface name="board" port="kernel_stream_src_40GbE_ring_1" type="streamsource" width="264" chan_id="kernel_input_40GbE_ring_1"/>
+ <interface name="board" port="kernel_stream_snk_40GbE_ring_1" type="streamsink" width="264" chan_id="kernel_output_40GbE_ring_1"/>
+
<interface name="board" port="kernel_stream_src_ADC" type="streamsource" width="16" chan_id="kernel_input_ADC"/>
</channels>
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf
index fa25d1956c..51a771c578 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf
@@ -492,4 +492,202 @@ set_location_assignment PIN_U12 -to JESD204B_SYNC[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[0]
+set_location_assignment PIN_AP40 -to RING_0_RX[0]
+set_location_assignment PIN_AR38 -to RING_0_RX[1]
+set_location_assignment PIN_AT40 -to RING_0_RX[2]
+set_location_assignment PIN_AU38 -to RING_0_RX[3]
+set_location_assignment PIN_AP44 -to RING_0_TX[0]
+set_location_assignment PIN_AR42 -to RING_0_TX[1]
+set_location_assignment PIN_AT44 -to RING_0_TX[2]
+set_location_assignment PIN_AU42 -to RING_0_TX[3]
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_F44 -to RING_1_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
+
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
+
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
+
+
set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_jesd204b.ip
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg
new file mode 100644
index 0000000000..5e76341e8e
--- /dev/null
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg
@@ -0,0 +1,37 @@
+hdl_lib_name = ta2_unb2b_top
+hdl_library_clause_name = ta2_unb2b_top_lib
+hdl_lib_uses_synth = common technology dp unb2b_board ta2_unb2b_40GbE ta2_unb2b_10GbE ta2_unb2b_1GbE_mc ta2_unb2b_jesd204b
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip =
+
+synth_files =
+ top_components_pkg.vhd
+ ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+ ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+ ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
+ ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+ top.vhd
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+
+
+quartus_vhdl_files =
+
+quartus_qip_files =
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v
index 22508e8dc2..cd44bb01ca 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v
@@ -62,6 +62,20 @@ module freeze_wrapper(
output wire [263:0] board_kernel_stream_snk_40GbE_data,
output wire board_kernel_stream_snk_40GbE_valid,
input wire board_kernel_stream_snk_40GbE_ready,
+
+ input wire [263:0] board_kernel_stream_src_40GbE_ring_0_data,
+ input wire board_kernel_stream_src_40GbE_ring_0_valid,
+ output wire board_kernel_stream_src_40GbE_ring_0_ready,
+ output wire [263:0] board_kernel_stream_snk_40GbE_ring_0_data,
+ output wire board_kernel_stream_snk_40GbE_ring_0_valid,
+ input wire board_kernel_stream_snk_40GbE_ring_0_ready,
+
+ input wire [263:0] board_kernel_stream_src_40GbE_ring_1_data,
+ input wire board_kernel_stream_src_40GbE_ring_1_valid,
+ output wire board_kernel_stream_src_40GbE_ring_1_ready,
+ output wire [263:0] board_kernel_stream_snk_40GbE_ring_1_data,
+ output wire board_kernel_stream_snk_40GbE_ring_1_valid,
+ input wire board_kernel_stream_snk_40GbE_ring_1_ready,
output [6:0] board_kernel_register_mem_address,
output board_kernel_register_mem_clken,
@@ -187,28 +201,45 @@ pr_region pr_region_inst
.kernel_cra_debugaccess(board_kernel_cra_debugaccess),
-
.kernel_stream_src_40GbE_data(board_kernel_stream_src_40GbE_data),
.kernel_stream_src_40GbE_ready(board_kernel_stream_src_40GbE_ready),
.kernel_stream_src_40GbE_valid(board_kernel_stream_src_40GbE_valid),
.kernel_stream_snk_40GbE_data(board_kernel_stream_snk_40GbE_data),
.kernel_stream_snk_40GbE_ready(board_kernel_stream_snk_40GbE_ready),
.kernel_stream_snk_40GbE_valid(board_kernel_stream_snk_40GbE_valid),
+
+ .kernel_stream_src_40GbE_ring_0_data(board_kernel_stream_src_40GbE_ring_0_data),
+ .kernel_stream_src_40GbE_ring_0_ready(board_kernel_stream_src_40GbE_ring_0_ready),
+ .kernel_stream_src_40GbE_ring_0_valid(board_kernel_stream_src_40GbE_ring_0_valid),
+ .kernel_stream_snk_40GbE_ring_0_data(board_kernel_stream_snk_40GbE_ring_0_data),
+ .kernel_stream_snk_40GbE_ring_0_ready(board_kernel_stream_snk_40GbE_ring_0_ready),
+ .kernel_stream_snk_40GbE_ring_0_valid(board_kernel_stream_snk_40GbE_ring_0_valid),
+
+ .kernel_stream_src_40GbE_ring_1_data(board_kernel_stream_src_40GbE_ring_1_data),
+ .kernel_stream_src_40GbE_ring_1_ready(board_kernel_stream_src_40GbE_ring_1_ready),
+ .kernel_stream_src_40GbE_ring_1_valid(board_kernel_stream_src_40GbE_ring_1_valid),
+ .kernel_stream_snk_40GbE_ring_1_data(board_kernel_stream_snk_40GbE_ring_1_data),
+ .kernel_stream_snk_40GbE_ring_1_ready(board_kernel_stream_snk_40GbE_ring_1_ready),
+ .kernel_stream_snk_40GbE_ring_1_valid(board_kernel_stream_snk_40GbE_ring_1_valid),
+
.kernel_stream_src_10GbE_data(board_kernel_stream_src_10GbE_data),
.kernel_stream_src_10GbE_ready(board_kernel_stream_src_10GbE_ready),
.kernel_stream_src_10GbE_valid(board_kernel_stream_src_10GbE_valid),
.kernel_stream_snk_10GbE_data(board_kernel_stream_snk_10GbE_data),
.kernel_stream_snk_10GbE_ready(board_kernel_stream_snk_10GbE_ready),
.kernel_stream_snk_10GbE_valid(board_kernel_stream_snk_10GbE_valid),
+
.kernel_stream_src_1GbE_data(board_kernel_stream_src_1GbE_data),
.kernel_stream_src_1GbE_ready(board_kernel_stream_src_1GbE_ready),
.kernel_stream_src_1GbE_valid(board_kernel_stream_src_1GbE_valid),
.kernel_stream_snk_1GbE_data(board_kernel_stream_snk_1GbE_data),
.kernel_stream_snk_1GbE_ready(board_kernel_stream_snk_1GbE_ready),
.kernel_stream_snk_1GbE_valid(board_kernel_stream_snk_1GbE_valid),
+
.kernel_stream_src_ADC_data(board_kernel_stream_src_ADC_data),
.kernel_stream_src_ADC_ready(board_kernel_stream_src_ADC_ready),
.kernel_stream_src_ADC_valid(board_kernel_stream_src_ADC_valid),
+
.kernel_register_mem_address(board_kernel_register_mem_address),
.kernel_register_mem_clken(board_kernel_register_mem_clken),
.kernel_register_mem_chipselect(board_kernel_register_mem_chipselect),
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v
index f0ea3b6263..3b9130301f 100755
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v
@@ -66,7 +66,21 @@ module pr_region (
output wire kernel_stream_src_40GbE_ready,
output wire [263:0] kernel_stream_snk_40GbE_data,
output wire kernel_stream_snk_40GbE_valid,
- input wire kernel_stream_snk_40GbE_ready
+ input wire kernel_stream_snk_40GbE_ready,
+
+ input wire [263:0] kernel_stream_src_40GbE_ring_0_data,
+ input wire kernel_stream_src_40GbE_ring_0_valid,
+ output wire kernel_stream_src_40GbE_ring_0_ready,
+ output wire [263:0] kernel_stream_snk_40GbE_ring_0_data,
+ output wire kernel_stream_snk_40GbE_ring_0_valid,
+ input wire kernel_stream_snk_40GbE_ring_0_ready,
+
+ input wire [263:0] kernel_stream_src_40GbE_ring_1_data,
+ input wire kernel_stream_src_40GbE_ring_1_valid,
+ output wire kernel_stream_src_40GbE_ring_1_ready,
+ output wire [263:0] kernel_stream_snk_40GbE_ring_1_data,
+ output wire kernel_stream_snk_40GbE_ring_1_valid,
+ input wire kernel_stream_snk_40GbE_ring_1_ready
// input wire kernel_mem0_waitrequest,
@@ -179,6 +193,24 @@ kernel_system kernel_system_inst
.kernel_output_40GbE_valid(kernel_stream_snk_40GbE_valid),
+ .kernel_input_40GbE_ring_0_data(kernel_stream_src_40GbE_ring_0_data),
+ .kernel_input_40GbE_ring_0_ready(kernel_stream_src_40GbE_ring_0_ready),
+ .kernel_input_40GbE_ring_0_valid(kernel_stream_src_40GbE_ring_0_valid),
+
+ .kernel_output_40GbE_ring_0_data(kernel_stream_snk_40GbE_ring_0_data),
+ .kernel_output_40GbE_ring_0_ready(kernel_stream_snk_40GbE_ring_0_ready),
+ .kernel_output_40GbE_ring_0_valid(kernel_stream_snk_40GbE_ring_0_valid),
+
+
+ .kernel_input_40GbE_ring_1_data(kernel_stream_src_40GbE_ring_1_data),
+ .kernel_input_40GbE_ring_1_ready(kernel_stream_src_40GbE_ring_1_ready),
+ .kernel_input_40GbE_ring_1_valid(kernel_stream_src_40GbE_ring_1_valid),
+
+ .kernel_output_40GbE_ring_1_data(kernel_stream_snk_40GbE_ring_1_data),
+ .kernel_output_40GbE_ring_1_ready(kernel_stream_snk_40GbE_ring_1_ready),
+ .kernel_output_40GbE_ring_1_valid(kernel_stream_snk_40GbE_ring_1_valid),
+
+
.kernel_input_10GbE_data(kernel_stream_src_10GbE_data),
.kernel_input_10GbE_ready(kernel_stream_src_10GbE_ready),
.kernel_input_10GbE_valid(kernel_stream_src_10GbE_valid),
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index 5bde0464e4..34f7db0034 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -200,7 +200,7 @@ BEGIN
dp_latency_adapter_tx_snk_in.valid <= kernel_snk_valid;
kernel_snk_ready <= dp_latency_adapter_tx_snk_out.ready; -- Flow control towards source (kernel)
- rx_status <= dp_latency_adapter_tx_snk_out.xon;
+ rx_status <= dp_xonoff_src_in.xon; -- use xonoff_src_in for status as xonoff_snk_out is always '1'
tx_serial_r <= unb2_board_front_io_serial_tx_arr(0);
unb2_board_front_io_serial_rx_arr(0) <= rx_serial_r;
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl
deleted file mode 100644
index 072933051d..0000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl
+++ /dev/null
@@ -1,200 +0,0 @@
-# TCL File Generated by Component Editor 18.0
-# Mon Jan 13 11:25:28 CET 2020
-# DO NOT MODIFY
-
-
-#
-# ta2_unb2b_10GbE "ta2_unb2b_10GbE" v1.0
-# 2020.01.13.11:25:28
-#
-#
-
-#
-# request TCL package from ACDS 18.0
-#
-package require -exact qsys 18.0
-
-
-#
-# module ta2_unb2b_10GbE
-#
-set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_10GbE
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_10GbE
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-#
-# file sets
-#
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_10GbE_ip_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_10GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_10GbE_ip_wrapper.vhd TOP_LEVEL_FILE
-
-
-#
-# parameters
-#
-
-
-#
-# display items
-#
-
-
-#
-# connection point kernel_snk
-#
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 72
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
-#
-# connection point kernel_src
-#
-add_interface kernel_src avalon_streaming start
-set_interface_property kernel_src associatedClock kernel_clk
-set_interface_property kernel_src associatedReset kernel_reset
-set_interface_property kernel_src dataBitsPerSymbol 8
-set_interface_property kernel_src errorDescriptor ""
-set_interface_property kernel_src firstSymbolInHighOrderBits true
-set_interface_property kernel_src maxChannel 0
-set_interface_property kernel_src readyAllowance 0
-set_interface_property kernel_src readyLatency 0
-set_interface_property kernel_src ENABLED true
-set_interface_property kernel_src EXPORT_OF ""
-set_interface_property kernel_src PORT_NAME_MAP ""
-set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_src SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_src kernel_src_data data Output 72
-add_interface_port kernel_src kernel_src_ready ready Input 1
-add_interface_port kernel_src kernel_src_valid valid Output 1
-
-
-#
-# connection point kernel_clk
-#
-add_interface kernel_clk clock end
-set_interface_property kernel_clk ENABLED true
-set_interface_property kernel_clk EXPORT_OF ""
-set_interface_property kernel_clk PORT_NAME_MAP ""
-set_interface_property kernel_clk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_clk kernel_clk clk Input 1
-
-
-#
-# connection point refclk
-#
-add_interface refclk clock end
-set_interface_property refclk ENABLED true
-set_interface_property refclk EXPORT_OF ""
-set_interface_property refclk PORT_NAME_MAP ""
-set_interface_property refclk CMSIS_SVD_VARIABLES ""
-set_interface_property refclk SVD_ADDRESS_GROUP ""
-
-add_interface_port refclk clk_ref_r clk Input 1
-
-
-#
-# connection point rx_serial_data
-#
-add_interface rx_serial_data conduit end
-set_interface_property rx_serial_data associatedClock ""
-set_interface_property rx_serial_data associatedReset ""
-set_interface_property rx_serial_data ENABLED true
-set_interface_property rx_serial_data EXPORT_OF ""
-set_interface_property rx_serial_data PORT_NAME_MAP ""
-set_interface_property rx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property rx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_serial_data rx_serial_r conduit Input 1
-
-
-#
-# connection point tx_serial_data
-#
-add_interface tx_serial_data conduit end
-set_interface_property tx_serial_data associatedClock ""
-set_interface_property tx_serial_data associatedReset ""
-set_interface_property tx_serial_data ENABLED true
-set_interface_property tx_serial_data EXPORT_OF ""
-set_interface_property tx_serial_data PORT_NAME_MAP ""
-set_interface_property tx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property tx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port tx_serial_data tx_serial_r conduit Output 1
-
-
-#
-# connection point config_reset
-#
-add_interface config_reset reset end
-set_interface_property config_reset associatedClock ""
-set_interface_property config_reset synchronousEdges NONE
-set_interface_property config_reset ENABLED true
-set_interface_property config_reset EXPORT_OF ""
-set_interface_property config_reset PORT_NAME_MAP ""
-set_interface_property config_reset CMSIS_SVD_VARIABLES ""
-set_interface_property config_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port config_reset config_reset reset Input 1
-
-
-#
-# connection point kernel_reset
-#
-add_interface kernel_reset reset end
-set_interface_property kernel_reset associatedClock kernel_clk
-set_interface_property kernel_reset synchronousEdges DEASSERT
-set_interface_property kernel_reset ENABLED true
-set_interface_property kernel_reset EXPORT_OF ""
-set_interface_property kernel_reset PORT_NAME_MAP ""
-set_interface_property kernel_reset CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_reset kernel_reset reset Input 1
-
-
-#
-# connection point rx_status
-#
-add_interface rx_status conduit end
-set_interface_property rx_status associatedClock ""
-set_interface_property rx_status associatedReset ""
-set_interface_property rx_status ENABLED true
-set_interface_property rx_status EXPORT_OF ""
-set_interface_property rx_status PORT_NAME_MAP ""
-set_interface_property rx_status CMSIS_SVD_VARIABLES ""
-set_interface_property rx_status SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_status rx_status rx_status Output 1
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl~ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl~
deleted file mode 100644
index ea4cf697bb..0000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_hw.tcl~
+++ /dev/null
@@ -1,200 +0,0 @@
-# TCL File Generated by Component Editor 18.0
-# Mon Jan 13 09:28:21 CET 2020
-# DO NOT MODIFY
-
-
-#
-# ta2_unb2b_10GbE "ta2_unb2b_10GbE" v1.0
-# 2020.01.13.09:28:21
-#
-#
-
-#
-# request TCL package from ACDS 18.0
-#
-package require -exact qsys 18.0
-
-
-#
-# module ta2_unb2b_10GbE
-#
-set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_10GbE
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_10GbE
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-#
-# file sets
-#
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_10GbE_ip_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_10GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_10GbE_ip_wrapper.vhd TOP_LEVEL_FILE
-
-
-#
-# parameters
-#
-
-
-#
-# display items
-#
-
-
-#
-# connection point kernel_snk
-#
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 72
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
-#
-# connection point kernel_src
-#
-add_interface kernel_src avalon_streaming start
-set_interface_property kernel_src associatedClock kernel_clk
-set_interface_property kernel_src associatedReset kernel_reset
-set_interface_property kernel_src dataBitsPerSymbol 8
-set_interface_property kernel_src errorDescriptor ""
-set_interface_property kernel_src firstSymbolInHighOrderBits true
-set_interface_property kernel_src maxChannel 0
-set_interface_property kernel_src readyAllowance 0
-set_interface_property kernel_src readyLatency 0
-set_interface_property kernel_src ENABLED true
-set_interface_property kernel_src EXPORT_OF ""
-set_interface_property kernel_src PORT_NAME_MAP ""
-set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_src SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_src kernel_src_data data Output 72
-add_interface_port kernel_src kernel_src_ready ready Input 1
-add_interface_port kernel_src kernel_src_valid valid Output 1
-
-
-#
-# connection point kernel_clk
-#
-add_interface kernel_clk clock end
-set_interface_property kernel_clk ENABLED true
-set_interface_property kernel_clk EXPORT_OF ""
-set_interface_property kernel_clk PORT_NAME_MAP ""
-set_interface_property kernel_clk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_clk kernel_clk clk Input 1
-
-
-#
-# connection point refclk
-#
-add_interface refclk clock end
-set_interface_property refclk ENABLED true
-set_interface_property refclk EXPORT_OF ""
-set_interface_property refclk PORT_NAME_MAP ""
-set_interface_property refclk CMSIS_SVD_VARIABLES ""
-set_interface_property refclk SVD_ADDRESS_GROUP ""
-
-add_interface_port refclk clk_ref_r clk Input 1
-
-
-#
-# connection point rx_serial_data
-#
-add_interface rx_serial_data conduit end
-set_interface_property rx_serial_data associatedClock ""
-set_interface_property rx_serial_data associatedReset ""
-set_interface_property rx_serial_data ENABLED true
-set_interface_property rx_serial_data EXPORT_OF ""
-set_interface_property rx_serial_data PORT_NAME_MAP ""
-set_interface_property rx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property rx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_serial_data rx_serial_r conduit Input 1
-
-
-#
-# connection point tx_serial_data
-#
-add_interface tx_serial_data conduit end
-set_interface_property tx_serial_data associatedClock ""
-set_interface_property tx_serial_data associatedReset ""
-set_interface_property tx_serial_data ENABLED true
-set_interface_property tx_serial_data EXPORT_OF ""
-set_interface_property tx_serial_data PORT_NAME_MAP ""
-set_interface_property tx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property tx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port tx_serial_data tx_serial_r conduit Output 1
-
-
-#
-# connection point config_reset
-#
-add_interface config_reset reset end
-set_interface_property config_reset associatedClock ""
-set_interface_property config_reset synchronousEdges NONE
-set_interface_property config_reset ENABLED true
-set_interface_property config_reset EXPORT_OF ""
-set_interface_property config_reset PORT_NAME_MAP ""
-set_interface_property config_reset CMSIS_SVD_VARIABLES ""
-set_interface_property config_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port config_reset config_reset reset Input 1
-
-
-#
-# connection point kernel_reset
-#
-add_interface kernel_reset reset end
-set_interface_property kernel_reset associatedClock kernel_clk
-set_interface_property kernel_reset synchronousEdges DEASSERT
-set_interface_property kernel_reset ENABLED true
-set_interface_property kernel_reset EXPORT_OF ""
-set_interface_property kernel_reset PORT_NAME_MAP ""
-set_interface_property kernel_reset CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_reset kernel_reset reset Input 1
-
-
-#
-# connection point rx_status
-#
-add_interface rx_status conduit end
-set_interface_property rx_status associatedClock ""
-set_interface_property rx_status associatedReset ""
-set_interface_property rx_status ENABLED true
-set_interface_property rx_status EXPORT_OF ""
-set_interface_property rx_status PORT_NAME_MAP ""
-set_interface_property rx_status CMSIS_SVD_VARIABLES ""
-set_interface_property rx_status SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_status rx_status rx_status Output 1
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_ip_wrapper.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_ip_wrapper.vhd
deleted file mode 100644
index b2c09951e8..0000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE_ip_wrapper.vhd
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2019
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Author:
--- . Reinier van der Walle
--- Purpose:
--- . Instantiates ta2_unb2b_10GbE component
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY ta2_unb2b_10GbE_ip_wrapper IS
- PORT (
- --config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
-
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 10G MAC reference clock
-
- tx_serial_r : OUT STD_LOGIC; -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC; -- Serial RX lanes from QSFP cage
-
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
-
- kernel_src_data : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(71 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
- );
-END ta2_unb2b_10GbE_ip_wrapper;
-
-
-ARCHITECTURE str OF ta2_unb2b_10GbE_ip_wrapper IS
- ----------------------------------------------------------------------------
- -- ta2_unb2b_10GbE Component
- ----------------------------------------------------------------------------
- COMPONENT ta2_unb2b_10GbE IS
- PORT (
- --config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
-
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 10G MAC reference clock
-
- tx_serial_r : OUT STD_LOGIC; -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC; -- Serial RX lanes from QSFP cage
-
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
-
- kernel_src_data : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(71 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
- );
- END COMPONENT ta2_unb2b_10GbE;
-
-BEGIN
-
- u_ta2_unb2b_10GbE : ta2_unb2b_10GbE
- PORT MAP (
- --config_clk => config_clk,
- config_reset => config_reset,
-
- clk_ref_r => clk_ref_r,
-
- tx_serial_r => tx_serial_r,
- rx_serial_r => rx_serial_r,
-
- kernel_clk => kernel_clk,
- kernel_reset => kernel_reset,
-
- kernel_src_data => kernel_src_data,
- kernel_src_valid => kernel_src_valid,
- kernel_src_ready => kernel_src_ready,
-
- kernel_snk_data => kernel_snk_data,
- kernel_snk_valid => kernel_snk_valid,
- kernel_snk_ready => kernel_snk_ready,
-
- rx_status => rx_status
-
- );
-
-
-
-END str;
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg
new file mode 100644
index 0000000000..e51ddb0cc1
--- /dev/null
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/hdllib.cfg
@@ -0,0 +1,32 @@
+hdl_lib_name = ta2_unb2b_40GbE
+hdl_library_clause_name = ta2_unb2b_40GbE_lib
+hdl_lib_uses_synth = common technology dp
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip =
+
+synth_files =
+ ta2_unb2b_40GbE.vhd
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+
+
+quartus_vhdl_files =
+
+quartus_qip_files =
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 83f8851193..0bbee7f131 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -55,28 +55,27 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-ENTITY ta2_unb2b_40GbE IS
+ENTITY ta2_unb2b_40GbE IS
+ GENERIC (
+ g_nof_mac : NATURAL := 1
+ );
PORT (
config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
config_reset : IN STD_LOGIC;
clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 40G MAC reference clock
- tx_serial_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial RX lanes from QSFP cage
+ tx_serial_r : OUT STD_LOGIC_VECTOR(4*g_nof_mac-1 DOWNTO 0); -- Serial TX lanes towards QSFP cage
+ rx_serial_r : IN STD_LOGIC_VECTOR(4*g_nof_mac-1 DOWNTO 0); -- Serial RX lanes from QSFP cage
kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
kernel_reset : IN STD_LOGIC;
- kernel_src_data : OUT STD_LOGIC_VECTOR(263 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(263 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ src_in_arr : IN t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0)
+
);
END ta2_unb2b_40GbE;
@@ -93,74 +92,64 @@ ARCHITECTURE str OF ta2_unb2b_40GbE IS
----------------------------------------------------------------------------
-- Reset signals
----------------------------------------------------------------------------
- SIGNAL rst_txmac : STD_LOGIC;
- SIGNAL rst_rxmac : STD_LOGIC;
+ SIGNAL rst_txmac_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
+ SIGNAL rst_rxmac_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- dp_xonoff
----------------------------------------------------------------------------
- SIGNAL dp_xonoff_src_out : t_dp_sosi;
- SIGNAL dp_xonoff_src_in : t_dp_siso;
+ SIGNAL dp_xonoff_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_xonoff_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- Latency adapter tx a
----------------------------------------------------------------------------
- SIGNAL dp_latency_adapter_tx_a_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_tx_a_src_in : t_dp_siso;
- SIGNAL dp_latency_adapter_tx_a_snk_in : t_dp_sosi;
- SIGNAL dp_latency_adapter_tx_a_snk_out : t_dp_siso;
+ SIGNAL dp_latency_adapter_tx_a_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_a_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_a_snk_in_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_a_snk_out_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- Latency adapter tx b
----------------------------------------------------------------------------
- SIGNAL dp_latency_adapter_tx_b_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_tx_b_src_in : t_dp_siso;
+ SIGNAL dp_latency_adapter_tx_b_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_b_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- Latency adapter rx
----------------------------------------------------------------------------
- SIGNAL dp_latency_adapter_rx_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_rx_src_in : t_dp_siso;
+ SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- TX FIFO
----------------------------------------------------------------------------
- SIGNAL dp_fifo_fill_eop_src_out : t_dp_sosi;
- SIGNAL dp_fifo_fill_eop_src_in : t_dp_siso;
+ SIGNAL dp_fifo_fill_eop_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_eop_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- 40G MAC IP
----------------------------------------------------------------------------
- SIGNAL serial_clk : STD_LOGIC;
- SIGNAL serial_clk_arr : STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL serial_clk_2arr : t_slv_4_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL serial_clk_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
- SIGNAL pll_locked : STD_LOGIC;
+ SIGNAL pll_locked_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
- SIGNAL tx_lanes_stable : STD_LOGIC;
- SIGNAL rx_pcs_ready : STD_LOGIC;
+ SIGNAL rx_pcs_ready_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
- SIGNAL clk_txmac : STD_LOGIC; -- MAC + PCS clock - at least 312.5Mhz
- SIGNAL clk_rxmac : STD_LOGIC; -- MAC + PCS clock - at least 312.5Mhz
+ SIGNAL clk_txmac_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- MAC + PCS clock - at least 312.5Mhz
+ SIGNAL clk_rxmac_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- MAC + PCS clock - at least 312.5Mhz
- SIGNAL l4_tx_data : STD_LOGIC_VECTOR(255 DOWNTO 0);
- SIGNAL l4_tx_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
- SIGNAL l4_tx_endofpacket : STD_LOGIC;
- SIGNAL l4_tx_ready : STD_LOGIC;
- SIGNAL l4_tx_startofpacket : STD_LOGIC;
- SIGNAL l4_tx_valid : STD_LOGIC;
- SIGNAL l4_rx_data : STD_LOGIC_VECTOR(255 DOWNTO 0);
- SIGNAL l4_rx_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
- SIGNAL l4_rx_endofpacket : STD_LOGIC;
- SIGNAL l4_rx_startofpacket : STD_LOGIC;
- SIGNAL l4_rx_valid : STD_LOGIC;
+ SIGNAL l4_tx_sosi_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL l4_tx_siso_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL l4_rx_sosi_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL l4_rx_siso_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- RX FIFO
----------------------------------------------------------------------------
- SIGNAL dp_fifo_dc_snk_in : t_dp_sosi;
-
- SIGNAL dp_fifo_dc_src_out : t_dp_sosi;
- SIGNAL dp_fifo_dc_src_in : t_dp_siso;
+ SIGNAL dp_fifo_dc_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
----------------------------------------------------------------------------
-- ATX PLL Component
@@ -284,333 +273,321 @@ ARCHITECTURE str OF ta2_unb2b_40GbE IS
BEGIN
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order
- gen_tx_bytes: FOR I IN 0 TO 31 GENERATE
- dp_latency_adapter_tx_a_snk_in.data(8*(32-I) -1 DOWNTO 8*(31-I)) <= kernel_snk_data(8*(I+1) -1 DOWNTO 8*I);
- END GENERATE;
+ gen_mac: FOR mac IN 0 TO g_nof_mac-1 GENERATE
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order
+ gen_tx_bytes: FOR I IN 0 TO 31 GENERATE
+ dp_latency_adapter_tx_a_snk_in_arr(mac).data(8*(32-I) -1 DOWNTO 8*(31-I)) <= snk_in_arr(mac).data(8*(I+1) -1 DOWNTO 8*I);
+ END GENERATE;
+
+ -- Assign correct data fields to control signals.
+ dp_latency_adapter_tx_a_snk_in_arr(mac).sop <= snk_in_arr(mac).data(256);
+ dp_latency_adapter_tx_a_snk_in_arr(mac).eop <= snk_in_arr(mac).data(257);
+ dp_latency_adapter_tx_a_snk_in_arr(mac).empty(4 DOWNTO 0) <= snk_in_arr(mac).data(263 DOWNTO 259);
+ dp_latency_adapter_tx_a_snk_in_arr(mac).valid <= snk_in_arr(mac).valid;
+ snk_out_arr(mac).ready <= dp_latency_adapter_tx_a_snk_out_arr(mac).ready; -- Flow control towards source (kernel)
+ snk_out_arr(mac).xon <= rx_pcs_ready_arr(mac);
+
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (downstream).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_tx_a : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
- -- Assign correct data fields to control signals.
- dp_latency_adapter_tx_a_snk_in.sop <= kernel_snk_data(256);
- dp_latency_adapter_tx_a_snk_in.eop <= kernel_snk_data(257);
- dp_latency_adapter_tx_a_snk_in.empty(4 DOWNTO 0) <= kernel_snk_data(263 DOWNTO 259);
+ snk_in => dp_latency_adapter_tx_a_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_a_snk_out_arr(mac),
- dp_latency_adapter_tx_a_snk_in.valid <= kernel_snk_valid;
- kernel_snk_ready <= dp_latency_adapter_tx_a_snk_out.ready; -- Flow control towards source (kernel)
+ src_out => dp_latency_adapter_tx_a_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_a_src_in_arr(mac)
+ );
+
+ ----------------------------------------------------------------------------
+ -- dp_xonoff: discard all TX frames until 40G MAC TX side is ready
+ ----------------------------------------------------------------------------
+ u_dp_xonoff : ENTITY dp_lib.dp_xonoff
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
+ in_sosi => dp_latency_adapter_tx_a_src_out_arr(mac),
+ in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (downstream).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_tx_a : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 0,
- g_out_latency => 1
- )
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_latency_adapter_tx_a_snk_in,
- snk_out => dp_latency_adapter_tx_a_snk_out,
-
- src_out => dp_latency_adapter_tx_a_src_out,
- src_in => dp_latency_adapter_tx_a_src_in
- );
-
- ----------------------------------------------------------------------------
- -- dp_xonoff: discard all TX frames until 40G MAC TX side is ready
- ----------------------------------------------------------------------------
- u_dp_xonoff : ENTITY dp_lib.dp_xonoff
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
+ out_sosi => dp_xonoff_src_out_arr(mac),
+ out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
+ );
- in_sosi => dp_latency_adapter_tx_a_src_out,
- in_siso => dp_latency_adapter_tx_a_src_in,
+ ----------------------------------------------------------------------------
+ -- TX FIFO
+ ----------------------------------------------------------------------------
+ u_dp_fifo_fill_eop : ENTITY dp_lib.dp_fifo_fill_eop
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_use_dual_clock => TRUE,
+ g_empty_w => 8,
+ g_use_empty => TRUE,
+ g_use_bsn => FALSE,
+ g_bsn_w => 64,
+ g_use_channel => FALSE,
+ g_use_sync => FALSE,
+ g_fifo_size => c_tx_fifo_size,
+ g_fifo_fill => c_tx_fifo_fill
+ )
+ PORT MAP (
+ wr_clk => kernel_clk,
+ wr_rst => kernel_reset,
- out_sosi => dp_xonoff_src_out,
- out_siso => dp_xonoff_src_in -- flush control via out_siso.xon
- );
+ rd_clk => clk_txmac_arr(mac),
+ rd_rst => rst_txmac_arr(mac),
- ----------------------------------------------------------------------------
- -- TX FIFO
- ----------------------------------------------------------------------------
- u_dp_fifo_fill_eop : ENTITY dp_lib.dp_fifo_fill_eop
- GENERIC MAP (
- g_data_w => c_data_w,
- g_use_dual_clock => TRUE,
- g_empty_w => 8,
- g_use_empty => TRUE,
- g_use_bsn => FALSE,
- g_bsn_w => 64,
- g_use_channel => FALSE,
- g_use_sync => FALSE,
- g_fifo_size => c_tx_fifo_size,
- g_fifo_fill => c_tx_fifo_fill
- )
- PORT MAP (
- wr_clk => kernel_clk,
- wr_rst => kernel_reset,
-
- rd_clk => clk_txmac,
- rd_rst => rst_txmac,
-
- snk_in => dp_xonoff_src_out,
- snk_out => dp_xonoff_src_in,
-
- src_out => dp_fifo_fill_eop_src_out,
- src_in => dp_fifo_fill_eop_src_in
- );
+ snk_in => dp_xonoff_src_out_arr(mac),
+ snk_out => dp_xonoff_src_in_arr(mac),
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=1 (upstream) to RL=0 (MAC TX interface).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_tx_b : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 1,
- g_out_latency => 0
- )
- PORT MAP (
- clk => clk_txmac,
- rst => rst_txmac,
-
- snk_in => dp_fifo_fill_eop_src_out,
- snk_out => dp_fifo_fill_eop_src_in,
-
- src_out => dp_latency_adapter_tx_b_src_out,
- src_in => dp_latency_adapter_tx_b_src_in
- );
+ src_out => dp_fifo_fill_eop_src_out_arr(mac),
+ src_in => dp_fifo_fill_eop_src_in_arr(mac)
+ );
- ----------------------------------------------------------------------------
- -- 40G MAC IP
- ----------------------------------------------------------------------------
- l4_tx_data <= dp_latency_adapter_tx_b_src_out.data(c_data_w-1 DOWNTO 0);
- l4_tx_valid <= dp_latency_adapter_tx_b_src_out.valid;
- l4_tx_empty <= dp_latency_adapter_tx_b_src_out.empty(4 DOWNTO 0);
- l4_tx_startofpacket <= dp_latency_adapter_tx_b_src_out.sop;
- l4_tx_endofpacket <= dp_latency_adapter_tx_b_src_out.eop;
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=1 (upstream) to RL=0 (MAC TX interface).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_tx_b : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ PORT MAP (
+ clk => clk_txmac_arr(mac),
+ rst => rst_txmac_arr(mac),
- dp_latency_adapter_tx_b_src_in.ready <= l4_tx_ready;
- dp_latency_adapter_tx_b_src_in.xon <= tx_lanes_stable;
+ snk_in => dp_fifo_fill_eop_src_out_arr(mac),
+ snk_out => dp_fifo_fill_eop_src_in_arr(mac),
- u_arria10_40g_mac : arria10_40g_mac
- PORT MAP (
- reset_async(0) => config_reset,
- clk_txmac(0) => clk_txmac, -- MAC + PCS clock - at least 312.5Mhz
- clk_rxmac(0) => clk_rxmac, -- MAC + PCS clock - at least 312.5Mhz
- clk_ref(0) => clk_ref_r,
- rx_pcs_ready(0) => rx_pcs_ready,
-
- tx_serial_clk => serial_clk_arr,
- tx_pll_locked(0) => pll_locked,
-
- clk_status(0) => config_clk,
- reset_status(0) => config_reset,
- status_addr => (OTHERS=>'0'),
- status_read => (OTHERS=>'0'),
- status_write => (OTHERS=>'0'),
- status_writedata => (OTHERS=>'0'),
+ src_out => dp_latency_adapter_tx_b_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_b_src_in_arr(mac)
+ );
+
+ ----------------------------------------------------------------------------
+ -- 40G MAC IP
+ ----------------------------------------------------------------------------
+ l4_tx_sosi_arr(mac) <= dp_latency_adapter_tx_b_src_out_arr(mac);
+ dp_latency_adapter_tx_b_src_in_arr(mac) <= l4_tx_siso_arr(mac);
+
+ u_arria10_40g_mac : arria10_40g_mac
+ PORT MAP (
+ reset_async(0) => config_reset,
+ clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_ref(0) => clk_ref_r,
+ rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
+
+ tx_serial_clk => serial_clk_2arr(mac),
+ tx_pll_locked(0) => pll_locked_arr(mac),
+
+ clk_status(0) => config_clk,
+ reset_status(0) => config_reset,
+ status_addr => (OTHERS=>'0'),
+ status_read => (OTHERS=>'0'),
+ status_write => (OTHERS=>'0'),
+ status_writedata => (OTHERS=>'0'),
-- status_readdata => status_readdata_eth,
-- status_read_timeout => status_read_timeout,
-- status_readdata_valid => status_readdata_valid_eth,
-
- reconfig_clk(0) => config_clk,
- reconfig_reset(0) => config_reset,
- reconfig_write => (OTHERS=>'0'),
- reconfig_read => (OTHERS=>'0'),
- reconfig_address => (OTHERS=>'0'),
- reconfig_writedata => (OTHERS=>'0'),
+
+ reconfig_clk(0) => config_clk,
+ reconfig_reset(0) => config_reset,
+ reconfig_write => (OTHERS=>'0'),
+ reconfig_read => (OTHERS=>'0'),
+ reconfig_address => (OTHERS=>'0'),
+ reconfig_writedata => (OTHERS=>'0'),
-- reconfig_readdata => reco_readdata[31:0],
-- reconfig_waitrequest => reco_waitrequest,
-
- l4_tx_data => l4_tx_data,
- l4_tx_empty => l4_tx_empty,
- l4_tx_startofpacket => l4_tx_startofpacket,
- l4_tx_endofpacket => l4_tx_endofpacket,
- l4_tx_ready => l4_tx_ready,
- l4_tx_valid => l4_tx_valid,
- l4_tx_error => '0',
-
- l4_rx_data => l4_rx_data,
- l4_rx_empty => l4_rx_empty,
- l4_rx_startofpacket => l4_rx_startofpacket,
- l4_rx_endofpacket => l4_rx_endofpacket,
--- l4_rx_error => ,
- l4_rx_valid => l4_rx_valid,
-
--- l4_rx_status (),
--- l4_rx_fcs_error (),
--- l4_rx_fcs_valid (),
--- rx_inc_octetsOK (),
--- rx_inc_octetsOK_valid (),
--- rx_inc_runt (),
--- rx_inc_64 (),
--- rx_inc_127 (),
--- rx_inc_255 (),
--- rx_inc_511 (),
--- rx_inc_1023 (),
--- rx_inc_1518 (),
--- rx_inc_max (),
--- rx_inc_over (),
--- rx_inc_mcast_data_err (),
--- rx_inc_mcast_data_ok (),
--- rx_inc_bcast_data_err (),
--- rx_inc_bcast_data_ok (),
--- rx_inc_ucast_data_err (),
--- rx_inc_ucast_data_ok (),
--- rx_inc_mcast_ctrl (),
--- rx_inc_bcast_ctrl (),
--- rx_inc_ucast_ctrl (),
--- rx_inc_pause (),
--- rx_inc_fcs_err (),
--- rx_inc_fragment (),
--- rx_inc_jabber (),
--- rx_inc_sizeok_fcserr (),
--- rx_inc_pause_ctrl_err (),
--- rx_inc_mcast_ctrl_err (),
--- rx_inc_bcast_ctrl_err (),
--- rx_inc_ucast_ctrl_err (),
--- status_waitrequest (),
- tx_lanes_stable(0) => tx_lanes_stable,
--- tx_inc_octetsOK (),
--- tx_inc_octetsOK_valid (),
--- tx_inc_64 (),
--- tx_inc_127 (),
--- tx_inc_255 (),
--- tx_inc_511 (),
--- tx_inc_1023 (),
--- tx_inc_1518 (),
--- tx_inc_max (),
--- tx_inc_over (),
--- tx_inc_mcast_data_err (),
--- tx_inc_mcast_data_ok (),
--- tx_inc_bcast_data_err (),
--- tx_inc_bcast_data_ok (),
--- tx_inc_ucast_data_err (),
--- tx_inc_ucast_data_ok (),
--- tx_inc_mcast_ctrl (),
--- tx_inc_bcast_ctrl (),
--- tx_inc_ucast_ctrl (),
--- tx_inc_pause (),
--- tx_inc_fcs_err (),
--- tx_inc_fragment (),
--- tx_inc_jabber (),
--- tx_inc_sizeok_fcserr (),
-
- tx_serial => tx_serial_r,
- rx_serial => rx_serial_r
- );
+
+ l4_tx_data => l4_tx_sosi_arr(mac).data(255 DOWNTO 0),
+ l4_tx_empty => l4_tx_sosi_arr(mac).empty(4 DOWNTO 0),
+ l4_tx_startofpacket => l4_tx_sosi_arr(mac).sop,
+ l4_tx_endofpacket => l4_tx_sosi_arr(mac).eop,
+ l4_tx_ready => l4_tx_siso_arr(mac).ready,
+ l4_tx_valid => l4_tx_sosi_arr(mac).valid,
+ l4_tx_error => '0',
+
+ l4_rx_data => l4_rx_sosi_arr(mac).data(255 DOWNTO 0),
+ l4_rx_empty => l4_rx_sosi_arr(mac).empty(4 DOWNTO 0),
+ l4_rx_startofpacket => l4_rx_sosi_arr(mac).sop,
+ l4_rx_endofpacket => l4_rx_sosi_arr(mac).eop,
+ -- l4_rx_error => ,
+ l4_rx_valid => l4_rx_sosi_arr(mac).valid,
+
+ -- l4_rx_status (),
+ -- l4_rx_fcs_error (),
+ -- l4_rx_fcs_valid (),
+ -- rx_inc_octetsOK (),
+ -- rx_inc_octetsOK_valid (),
+ -- rx_inc_runt (),
+ -- rx_inc_64 (),
+ -- rx_inc_127 (),
+ -- rx_inc_255 (),
+ -- rx_inc_511 (),
+ -- rx_inc_1023 (),
+ -- rx_inc_1518 (),
+ -- rx_inc_max (),
+ -- rx_inc_over (),
+ -- rx_inc_mcast_data_err (),
+ -- rx_inc_mcast_data_ok (),
+ -- rx_inc_bcast_data_err (),
+ -- rx_inc_bcast_data_ok (),
+ -- rx_inc_ucast_data_err (),
+ -- rx_inc_ucast_data_ok (),
+ -- rx_inc_mcast_ctrl (),
+ -- rx_inc_bcast_ctrl (),
+ -- rx_inc_ucast_ctrl (),
+ -- rx_inc_pause (),
+ -- rx_inc_fcs_err (),
+ -- rx_inc_fragment (),
+ -- rx_inc_jabber (),
+ -- rx_inc_sizeok_fcserr (),
+ -- rx_inc_pause_ctrl_err (),
+ -- rx_inc_mcast_ctrl_err (),
+ -- rx_inc_bcast_ctrl_err (),
+ -- rx_inc_ucast_ctrl_err (),
+ -- status_waitrequest (),
+ tx_lanes_stable(0) => l4_tx_siso_arr(mac).xon,
+ -- tx_inc_octetsOK (),
+ -- tx_inc_octetsOK_valid (),
+ -- tx_inc_64 (),
+ -- tx_inc_127 (),
+ -- tx_inc_255 (),
+ -- tx_inc_511 (),
+ -- tx_inc_1023 (),
+ -- tx_inc_1518 (),
+ -- tx_inc_max (),
+ -- tx_inc_over (),
+ -- tx_inc_mcast_data_err (),
+ -- tx_inc_mcast_data_ok (),
+ -- tx_inc_bcast_data_err (),
+ -- tx_inc_bcast_data_ok (),
+ -- tx_inc_ucast_data_err (),
+ -- tx_inc_ucast_data_ok (),
+ -- tx_inc_mcast_ctrl (),
+ -- tx_inc_bcast_ctrl (),
+ -- tx_inc_ucast_ctrl (),
+ -- tx_inc_pause (),
+ -- tx_inc_fcs_err (),
+ -- tx_inc_fragment (),
+ -- tx_inc_jabber (),
+ -- tx_inc_sizeok_fcserr (),
+
+ tx_serial => tx_serial_r(4*(mac+1)-1 DOWNTO 4*mac),
+ rx_serial => rx_serial_r(4*(mac+1)-1 DOWNTO 4*mac)
+ );
+
+
+ -- No latency adapter needed as the RX MAC does not have a ready input
+ ----------------------------------------------------------------------------
+ -- RX FIFO
+ ----------------------------------------------------------------------------
+ rst_rxmac_arr(mac) <= NOT rx_pcs_ready_arr(mac);
+ u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_empty_w => 8,
+ g_use_empty => TRUE,
+ g_use_bsn => FALSE,
+ g_bsn_w => 64,
+ g_use_channel => FALSE,
+ g_use_sync => FALSE,
+ g_fifo_size => c_rx_fifo_size
+ )
+ PORT MAP (
+ wr_clk => clk_rxmac_arr(mac),
+ wr_rst => rst_rxmac_arr(mac),
+ rd_clk => kernel_clk,
+ rd_rst => kernel_reset,
- -- No latency adapter needed as the RX MAC does not have a ready input
- ----------------------------------------------------------------------------
- -- RX FIFO
- ----------------------------------------------------------------------------
- rst_rxmac <= NOT rx_pcs_ready;
- rx_status <= rx_pcs_ready;
-
- dp_fifo_dc_snk_in.data(c_data_w-1 DOWNTO 0) <= l4_rx_data;
- dp_fifo_dc_snk_in.valid <= l4_rx_valid;
- dp_fifo_dc_snk_in.sop <= l4_rx_startofpacket;
- dp_fifo_dc_snk_in.eop <= l4_rx_endofpacket;
- dp_fifo_dc_snk_in.empty(4 DOWNTO 0) <= l4_rx_empty;
-
- u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
- GENERIC MAP (
- g_data_w => c_data_w,
- g_empty_w => 8,
- g_use_empty => TRUE,
- g_use_bsn => FALSE,
- g_bsn_w => 64,
- g_use_channel => FALSE,
- g_use_sync => FALSE,
- g_fifo_size => c_rx_fifo_size
- )
- PORT MAP (
- wr_clk => clk_rxmac,
- wr_rst => rst_rxmac,
-
- rd_clk => kernel_clk,
- rd_rst => kernel_reset,
-
- snk_in => dp_fifo_dc_snk_in,
- snk_out => OPEN,
-
- src_out => dp_fifo_dc_src_out,
- src_in => dp_fifo_dc_src_in
- );
+ snk_in => l4_rx_sosi_arr(mac),
+ snk_out => OPEN,
+ src_out => dp_fifo_dc_src_out_arr(mac),
+ src_in => dp_fifo_dc_src_in_arr(mac)
+ );
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=1 (dp_fifo_dc) to RL=0 (OpenCL kernel).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 1,
- g_out_latency => 0
- )
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_src_out,
- snk_out => dp_fifo_dc_src_in,
-
- src_out => dp_latency_adapter_rx_src_out,
- src_in => dp_latency_adapter_rx_src_in
- );
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order
- gen_rx_bytes: FOR I IN 0 TO 31 GENERATE
- kernel_src_data(8*(32-I) -1 DOWNTO 8*(31-I)) <= dp_latency_adapter_rx_src_out.data(8*(I+1) -1 DOWNTO 8*I);
- END GENERATE;
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=1 (dp_fifo_dc) to RL=0 (OpenCL kernel).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_src_out_arr(mac),
+ snk_out => dp_fifo_dc_src_in_arr(mac),
+
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
- -- Assign control signals to correct data fields.
- kernel_src_data(256) <= dp_latency_adapter_rx_src_out.sop;
- kernel_src_data(257) <= dp_latency_adapter_rx_src_out.eop;
- kernel_src_data(263 DOWNTO 259) <= dp_latency_adapter_rx_src_out.empty(4 DOWNTO 0);
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order
+ gen_rx_bytes: FOR I IN 0 TO 31 GENERATE
+ src_out_arr(mac).data(8*(32-I) -1 DOWNTO 8*(31-I)) <= dp_latency_adapter_rx_src_out_arr(mac).data(8*(I+1) -1 DOWNTO 8*I);
+ END GENERATE;
+
+ -- Assign control signals to correct data fields.
+ src_out_arr(mac).data(256) <= dp_latency_adapter_rx_src_out_arr(mac).sop;
+ src_out_arr(mac).data(257) <= dp_latency_adapter_rx_src_out_arr(mac).eop;
+ src_out_arr(mac).data(263 DOWNTO 259) <= dp_latency_adapter_rx_src_out_arr(mac).empty(4 DOWNTO 0);
+ src_out_arr(mac).valid <= dp_latency_adapter_rx_src_out_arr(mac).valid;
+ dp_latency_adapter_rx_src_in_arr(mac).ready <= src_in_arr(mac).ready;
+ dp_latency_adapter_rx_src_in_arr(mac).xon <= '1';
+
+ -------------------------------------------------------------------------------
+ -- Reset signal generation
+ -------------------------------------------------------------------------------
+ u_common_areset_txmac : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ PORT MAP (
+ in_rst => kernel_reset,
+ clk => clk_txmac_arr(mac),
+ out_rst => rst_txmac_arr(mac)
+ );
- kernel_src_valid <= dp_latency_adapter_rx_src_out.valid;
- dp_latency_adapter_rx_src_in.ready <= kernel_src_ready;
- dp_latency_adapter_rx_src_in.xon <= '1';
-
- -------------------------------------------------------------------------------
- -- PLL for clock generation
- -------------------------------------------------------------------------------
- u_arria10_40g_atx_pll : arria10_40g_atx_pll
- port map (
- pll_cal_busy => OPEN,
- pll_locked => pll_locked,
- pll_powerdown => config_reset,
- pll_refclk0 => clk_ref_r,
- tx_serial_clk => serial_clk
- );
- gen_serial_clk_arr : FOR i IN 0 TO 3 GENERATE
- serial_clk_arr(i) <= serial_clk;
+ -------------------------------------------------------------------------------
+ -- PLL for clock generation, every mac needs its own, due to clock nework limitations
+ -------------------------------------------------------------------------------
+ u_arria10_40g_atx_pll : arria10_40g_atx_pll
+ port map (
+ pll_cal_busy => OPEN,
+ pll_locked => pll_locked_arr(mac),
+ pll_powerdown => config_reset,
+ pll_refclk0 => clk_ref_r,
+ tx_serial_clk => serial_clk_arr(mac)
+ );
+
+ gen_serial_clk_arr : FOR i IN 0 TO 3 GENERATE
+ serial_clk_2arr(mac)(i) <= serial_clk_arr(mac);
+ END GENERATE;
+
END GENERATE;
- -------------------------------------------------------------------------------
- -- Reset signal generation
- -------------------------------------------------------------------------------
-
- u_common_areset_txmac : ENTITY common_lib.common_areset
- GENERIC MAP (
- g_rst_level => '1',
- g_delay_len => 3
- )
- PORT MAP (
- in_rst => kernel_reset,
- clk => clk_txmac,
- out_rst => rst_txmac
- );
END str;
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl
deleted file mode 100644
index 255db44967..0000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl
+++ /dev/null
@@ -1,213 +0,0 @@
-# TCL File Generated by Component Editor 18.0
-# Fri Jan 10 16:11:08 CET 2020
-# DO NOT MODIFY
-
-
-#
-# ta2_unb2b_40GbE "ta2_unb2b_40GbE" v1.0
-# 2020.01.10.16:11:08
-#
-#
-
-#
-# request TCL package from ACDS 18.0
-#
-package require -exact qsys 18.0
-
-
-#
-# module ta2_unb2b_40GbE
-#
-set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_40GbE
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_40GbE
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-#
-# file sets
-#
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_40GbE_ip_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_40GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_40GbE_ip_wrapper.vhd TOP_LEVEL_FILE
-
-
-#
-# parameters
-#
-
-
-#
-# display items
-#
-
-
-#
-# connection point kernel_snk
-#
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 264
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
-#
-# connection point kernel_src
-#
-add_interface kernel_src avalon_streaming start
-set_interface_property kernel_src associatedClock kernel_clk
-set_interface_property kernel_src associatedReset kernel_reset
-set_interface_property kernel_src dataBitsPerSymbol 8
-set_interface_property kernel_src errorDescriptor ""
-set_interface_property kernel_src firstSymbolInHighOrderBits true
-set_interface_property kernel_src maxChannel 0
-set_interface_property kernel_src readyAllowance 0
-set_interface_property kernel_src readyLatency 0
-set_interface_property kernel_src ENABLED true
-set_interface_property kernel_src EXPORT_OF ""
-set_interface_property kernel_src PORT_NAME_MAP ""
-set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_src SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_src kernel_src_data data Output 264
-add_interface_port kernel_src kernel_src_ready ready Input 1
-add_interface_port kernel_src kernel_src_valid valid Output 1
-
-
-#
-# connection point config_clk
-#
-add_interface config_clk clock end
-set_interface_property config_clk ENABLED true
-set_interface_property config_clk EXPORT_OF ""
-set_interface_property config_clk PORT_NAME_MAP ""
-set_interface_property config_clk CMSIS_SVD_VARIABLES ""
-set_interface_property config_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port config_clk config_clk clk Input 1
-
-
-#
-# connection point kernel_clk
-#
-add_interface kernel_clk clock end
-set_interface_property kernel_clk ENABLED true
-set_interface_property kernel_clk EXPORT_OF ""
-set_interface_property kernel_clk PORT_NAME_MAP ""
-set_interface_property kernel_clk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_clk kernel_clk clk Input 1
-
-
-#
-# connection point refclk
-#
-add_interface refclk clock end
-set_interface_property refclk ENABLED true
-set_interface_property refclk EXPORT_OF ""
-set_interface_property refclk PORT_NAME_MAP ""
-set_interface_property refclk CMSIS_SVD_VARIABLES ""
-set_interface_property refclk SVD_ADDRESS_GROUP ""
-
-add_interface_port refclk clk_ref_r clk Input 1
-
-
-#
-# connection point rx_serial_data
-#
-add_interface rx_serial_data conduit end
-set_interface_property rx_serial_data associatedClock ""
-set_interface_property rx_serial_data associatedReset ""
-set_interface_property rx_serial_data ENABLED true
-set_interface_property rx_serial_data EXPORT_OF ""
-set_interface_property rx_serial_data PORT_NAME_MAP ""
-set_interface_property rx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property rx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_serial_data rx_serial_r conduit Input 4
-
-
-#
-# connection point tx_serial_data
-#
-add_interface tx_serial_data conduit end
-set_interface_property tx_serial_data associatedClock ""
-set_interface_property tx_serial_data associatedReset ""
-set_interface_property tx_serial_data ENABLED true
-set_interface_property tx_serial_data EXPORT_OF ""
-set_interface_property tx_serial_data PORT_NAME_MAP ""
-set_interface_property tx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property tx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port tx_serial_data tx_serial_r conduit Output 4
-
-
-#
-# connection point config_reset
-#
-add_interface config_reset reset end
-set_interface_property config_reset associatedClock config_clk
-set_interface_property config_reset synchronousEdges DEASSERT
-set_interface_property config_reset ENABLED true
-set_interface_property config_reset EXPORT_OF ""
-set_interface_property config_reset PORT_NAME_MAP ""
-set_interface_property config_reset CMSIS_SVD_VARIABLES ""
-set_interface_property config_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port config_reset config_reset reset Input 1
-
-
-#
-# connection point kernel_reset
-#
-add_interface kernel_reset reset end
-set_interface_property kernel_reset associatedClock kernel_clk
-set_interface_property kernel_reset synchronousEdges DEASSERT
-set_interface_property kernel_reset ENABLED true
-set_interface_property kernel_reset EXPORT_OF ""
-set_interface_property kernel_reset PORT_NAME_MAP ""
-set_interface_property kernel_reset CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_reset kernel_reset reset Input 1
-
-
-#
-# connection point rx_status
-#
-add_interface rx_status conduit end
-set_interface_property rx_status associatedClock ""
-set_interface_property rx_status associatedReset ""
-set_interface_property rx_status ENABLED true
-set_interface_property rx_status EXPORT_OF ""
-set_interface_property rx_status PORT_NAME_MAP ""
-set_interface_property rx_status CMSIS_SVD_VARIABLES ""
-set_interface_property rx_status SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_status rx_status rx_status Output 1
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl~ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl~
deleted file mode 100644
index 169117a331..0000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_hw.tcl~
+++ /dev/null
@@ -1,213 +0,0 @@
-# TCL File Generated by Component Editor 18.0
-# Fri Jan 10 15:53:26 CET 2020
-# DO NOT MODIFY
-
-
-#
-# ta2_unb2b_40GbE "ta2_unb2b_40GbE" v1.0
-# 2020.01.10.15:53:26
-#
-#
-
-#
-# request TCL package from ACDS 18.0
-#
-package require -exact qsys 18.0
-
-
-#
-# module ta2_unb2b_40GbE
-#
-set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_40GbE
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_40GbE
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-#
-# file sets
-#
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_40GbE_ip_wrapper
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_40GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_40GbE_ip_wrapper.vhd TOP_LEVEL_FILE
-
-
-#
-# parameters
-#
-
-
-#
-# display items
-#
-
-
-#
-# connection point kernel_snk
-#
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 264
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
-#
-# connection point kernel_src
-#
-add_interface kernel_src avalon_streaming start
-set_interface_property kernel_src associatedClock kernel_clk
-set_interface_property kernel_src associatedReset kernel_reset
-set_interface_property kernel_src dataBitsPerSymbol 8
-set_interface_property kernel_src errorDescriptor ""
-set_interface_property kernel_src firstSymbolInHighOrderBits true
-set_interface_property kernel_src maxChannel 0
-set_interface_property kernel_src readyAllowance 0
-set_interface_property kernel_src readyLatency 0
-set_interface_property kernel_src ENABLED true
-set_interface_property kernel_src EXPORT_OF ""
-set_interface_property kernel_src PORT_NAME_MAP ""
-set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_src SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_src kernel_src_data data Output 264
-add_interface_port kernel_src kernel_src_ready ready Input 1
-add_interface_port kernel_src kernel_src_valid valid Output 1
-
-
-#
-# connection point config_clk
-#
-add_interface config_clk clock end
-set_interface_property config_clk ENABLED true
-set_interface_property config_clk EXPORT_OF ""
-set_interface_property config_clk PORT_NAME_MAP ""
-set_interface_property config_clk CMSIS_SVD_VARIABLES ""
-set_interface_property config_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port config_clk config_clk clk Input 1
-
-
-#
-# connection point kernel_clk
-#
-add_interface kernel_clk clock end
-set_interface_property kernel_clk ENABLED true
-set_interface_property kernel_clk EXPORT_OF ""
-set_interface_property kernel_clk PORT_NAME_MAP ""
-set_interface_property kernel_clk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_clk kernel_clk clk Input 1
-
-
-#
-# connection point refclk
-#
-add_interface refclk clock end
-set_interface_property refclk ENABLED true
-set_interface_property refclk EXPORT_OF ""
-set_interface_property refclk PORT_NAME_MAP ""
-set_interface_property refclk CMSIS_SVD_VARIABLES ""
-set_interface_property refclk SVD_ADDRESS_GROUP ""
-
-add_interface_port refclk clk_ref_r clk Input 1
-
-
-#
-# connection point rx_serial_data
-#
-add_interface rx_serial_data conduit end
-set_interface_property rx_serial_data associatedClock ""
-set_interface_property rx_serial_data associatedReset ""
-set_interface_property rx_serial_data ENABLED true
-set_interface_property rx_serial_data EXPORT_OF ""
-set_interface_property rx_serial_data PORT_NAME_MAP ""
-set_interface_property rx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property rx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_serial_data rx_serial_r conduit Input 4
-
-
-#
-# connection point tx_serial_data
-#
-add_interface tx_serial_data conduit end
-set_interface_property tx_serial_data associatedClock ""
-set_interface_property tx_serial_data associatedReset ""
-set_interface_property tx_serial_data ENABLED true
-set_interface_property tx_serial_data EXPORT_OF ""
-set_interface_property tx_serial_data PORT_NAME_MAP ""
-set_interface_property tx_serial_data CMSIS_SVD_VARIABLES ""
-set_interface_property tx_serial_data SVD_ADDRESS_GROUP ""
-
-add_interface_port tx_serial_data tx_serial_r conduit Output 4
-
-
-#
-# connection point config_reset
-#
-add_interface config_reset reset end
-set_interface_property config_reset associatedClock config_clk
-set_interface_property config_reset synchronousEdges DEASSERT
-set_interface_property config_reset ENABLED true
-set_interface_property config_reset EXPORT_OF ""
-set_interface_property config_reset PORT_NAME_MAP ""
-set_interface_property config_reset CMSIS_SVD_VARIABLES ""
-set_interface_property config_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port config_reset config_reset reset Input 1
-
-
-#
-# connection point kernel_reset
-#
-add_interface kernel_reset reset end
-set_interface_property kernel_reset associatedClock kernel_clk
-set_interface_property kernel_reset synchronousEdges DEASSERT
-set_interface_property kernel_reset ENABLED true
-set_interface_property kernel_reset EXPORT_OF ""
-set_interface_property kernel_reset PORT_NAME_MAP ""
-set_interface_property kernel_reset CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_reset kernel_reset reset Input 1
-
-
-#
-# connection point rx_status
-#
-add_interface rx_status conduit end
-set_interface_property rx_status associatedClock ""
-set_interface_property rx_status associatedReset ""
-set_interface_property rx_status ENABLED true
-set_interface_property rx_status EXPORT_OF ""
-set_interface_property rx_status PORT_NAME_MAP ""
-set_interface_property rx_status CMSIS_SVD_VARIABLES ""
-set_interface_property rx_status SVD_ADDRESS_GROUP ""
-
-add_interface_port rx_status rx_status rx_status Output 1
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_ip_wrapper.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_ip_wrapper.vhd
deleted file mode 100644
index c6c086f03b..0000000000
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE_ip_wrapper.vhd
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2019
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Author:
--- . Reinier van der Walle
--- Purpose:
--- . Instantiates ta2_unb2b_40GbE component
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY ta2_unb2b_40GbE_ip_wrapper IS
- PORT (
- config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
-
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 40G MAC reference clock
-
- tx_serial_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial RX lanes from QSFP cage
-
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
-
- kernel_src_data : OUT STD_LOGIC_VECTOR(263 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(263 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
- );
-END ta2_unb2b_40GbE_ip_wrapper;
-
-
-ARCHITECTURE str OF ta2_unb2b_40GbE_ip_wrapper IS
- ----------------------------------------------------------------------------
- -- ta2_unb2b_40GbE Component
- ----------------------------------------------------------------------------
- COMPONENT ta2_unb2b_40GbE IS
- PORT (
- config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
-
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 40G MAC reference clock
-
- tx_serial_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Serial RX lanes from QSFP cage
-
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
-
- kernel_src_data : OUT STD_LOGIC_VECTOR(263 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(263 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
- );
- END COMPONENT ta2_unb2b_40GbE;
-
-BEGIN
-
- u_ta2_unb2b_40GbE : ta2_unb2b_40GbE
- PORT MAP (
- config_clk => config_clk,
- config_reset => config_reset,
-
- clk_ref_r => clk_ref_r,
-
- tx_serial_r => tx_serial_r,
- rx_serial_r => rx_serial_r,
-
- kernel_clk => kernel_clk,
- kernel_reset => kernel_reset,
-
- kernel_src_data => kernel_src_data,
- kernel_src_valid => kernel_src_valid,
- kernel_src_ready => kernel_src_ready,
-
- kernel_snk_data => kernel_snk_data,
- kernel_snk_valid => kernel_snk_valid,
- kernel_snk_ready => kernel_snk_ready,
-
- rx_status => rx_status
-
- );
-
-
-
-END str;
-
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
index c46698e643..42ce5312d6 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
@@ -75,10 +75,16 @@ ENTITY top IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS => '0');
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -106,7 +112,13 @@ ARCHITECTURE str OF top IS
-- 10GbE
CONSTANT c_nof_qsfp_bus : NATURAL := 2;
- CONSTANT c_nof_streams_qsfp : NATURAL := c_quad*c_nof_qsfp_bus;
+ CONSTANT c_nof_ring_bus : NATURAL := 2;
+ CONSTANT c_ring_bus_w : NATURAL := c_unb2b_board_tr_ring.bus_w;
+ CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus;
+ CONSTANT c_nof_streams_ring : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus;
+
+ -- 40GbE
+ CONSTANT c_nof_40GbE_IP : NATURAL := 3;
-- System
SIGNAL cs_sim : STD_LOGIC;
@@ -193,14 +205,21 @@ ARCHITECTURE str OF top IS
-- 10GbE
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
-
+
+ SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+
SIGNAL unb2b_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL unb2b_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
+
+ SIGNAL unb2b_board_ring_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL unb2b_board_ring_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0);
-- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus-1 DOWNTO 0);
- SIGNAL unb2b_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr(c_nof_qsfp_bus*c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus+c_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus+c_nof_ring_bus-1 DOWNTO 0);
+ --SIGNAL unb2b_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr(c_nof_qsfp_bus*c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL unb2b_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr((c_nof_qsfp_bus+c_nof_qsfp_bus)*c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL i_reset_n : STD_LOGIC;
SIGNAL i_kernel_rst : STD_LOGIC;
@@ -209,6 +228,7 @@ ARCHITECTURE str OF top IS
SIGNAL board_kernel_clk_clk : std_logic;
SIGNAL board_kernel_clk2x_clk : std_logic;
SIGNAL board_kernel_reset_reset_n : std_logic;
+ SIGNAL board_kernel_reset_reset_n_in : std_logic;
SIGNAL board_kernel_cra_waitrequest : std_logic;
SIGNAL board_kernel_cra_readdata : std_logic_vector(63 downto 0);
@@ -231,13 +251,12 @@ ARCHITECTURE str OF top IS
SIGNAL board_kernel_register_mem_writedata : std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0); -- := (others => 'X'); -- byteenable
- SIGNAL board_kernel_stream_snk_40GbE_data : std_logic_vector(263 downto 0) := (others => 'X'); -- data
- SIGNAL board_kernel_stream_snk_40GbE_ready : std_logic; -- ready
- SIGNAL board_kernel_stream_snk_40GbE_valid : std_logic := 'X'; -- valid
- SIGNAL board_kernel_stream_src_40GbE_data : std_logic_vector(263 downto 0); -- data
- SIGNAL board_kernel_stream_src_40GbE_ready : std_logic := 'X'; -- ready
- SIGNAL board_kernel_stream_src_40GbE_valid : std_logic; -- valid
- SIGNAL ta2_unb2b_40gbe_rx_status_rx_status : std_logic; -- rx_status
+ SIGNAL ta2_unb2b_40GbE_src_out_arr : t_dp_sosi_arr(c_nof_40GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_src_in_arr : t_dp_siso_arr(c_nof_40GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_snk_out_arr : t_dp_siso_arr(c_nof_40GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_snk_in_arr : t_dp_sosi_arr(c_nof_40GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_tx_serial_r : STD_LOGIC_VECTOR(4*c_nof_40GbE_IP -1 DOWNTO 0);
+ SIGNAL ta2_unb2b_40GbE_rx_serial_r : STD_LOGIC_VECTOR(4*c_nof_40GbE_IP -1 DOWNTO 0);
SIGNAL board_kernel_stream_src_10GbE_data : std_logic_vector(71 downto 0);
SIGNAL board_kernel_stream_src_10GbE_valid : std_logic;
@@ -278,25 +297,29 @@ BEGIN
serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_TX => i_QSFP_TX --,
- QSFP_LED => QSFP_LED
+ --QSFP_LED => QSFP_LED
);
------------------------
-- qsfp LEDs controller
------------------------
- unb2b_board_qsfp_leds_tx_src_in_arr(4).xon <= ta2_unb2b_40gbe_rx_status_rx_status;
unb2b_board_qsfp_leds_tx_src_in_arr(0).xon <= ta2_unb2b_10gbe_rx_status_rx_status;
+ unb2b_board_qsfp_leds_tx_src_in_arr(4).xon <= ta2_unb2b_40GbE_snk_out_arr(0).xon;
+ -- ring LED indicator
+ unb2b_board_qsfp_leds_tx_src_in_arr(8).xon <= ta2_unb2b_40GbE_snk_out_arr(1).xon;
+ unb2b_board_qsfp_leds_tx_src_in_arr(12).xon <= ta2_unb2b_40GbE_snk_out_arr(2).xon;
+
u_unb2b_board_qsfp_leds : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
+ g_nof_qsfp => c_nof_qsfp_bus+c_nof_ring_bus,
g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
)
PORT MAP (
@@ -305,35 +328,71 @@ BEGIN
tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0)
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus+c_nof_ring_bus-1 DOWNTO 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus+c_nof_ring_bus-1 DOWNTO 0)
);
- ----------
- -- 40GbE
- ----------
+ gen_leds : FOR i IN 0 TO c_nof_qsfp_bus+c_nof_ring_bus-1 GENERATE
+ QSFP_LED(i*2) <= qsfp_green_led_arr(i);
+ QSFP_LED(i*2+1) <= qsfp_red_led_arr(i);
+ END GENERATE;
+
+
+
+ ------------
+ -- RING IO
+ ------------
+ i_RING_RX(0) <= RING_0_RX;
+ i_RING_RX(1) <= RING_1_RX;
+ RING_0_TX <= i_RING_TX(0);
+ RING_1_TX <= i_RING_TX(1);
+
+ u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
+ GENERIC MAP (
+ g_nof_ring_bus => c_nof_ring_bus
+ )
+ PORT MAP (
+ serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
+ RING_RX => i_RING_RX,
+ RING_TX => i_RING_TX
+ );
+
+ ---------
+ -- 40GbE
+ ---------
+ -- Front QSFP 1 40GbE Interface, IP index = 0
+ unb2b_board_front_io_serial_tx_arr(7 DOWNTO 4) <= ta2_unb2b_40GbE_tx_serial_r(3 DOWNTO 0);
+ ta2_unb2b_40GbE_rx_serial_r(3 DOWNTO 0) <= unb2b_board_front_io_serial_rx_arr(7 DOWNTO 4);
+
+ -- Ring 0 (to the left), IP index = 1
+ unb2b_board_ring_io_serial_tx_arr(3 DOWNTO 0) <= ta2_unb2b_40GbE_tx_serial_r(7 DOWNTO 4);
+ ta2_unb2b_40GbE_rx_serial_r(7 DOWNTO 4) <= unb2b_board_ring_io_serial_rx_arr(3 DOWNTO 0);
+
+ -- Ring 1 (to the right), IP index = 2
+ unb2b_board_ring_io_serial_tx_arr(3+c_ring_bus_w DOWNTO c_ring_bus_w) <= ta2_unb2b_40GbE_tx_serial_r(11 DOWNTO 8);
+ ta2_unb2b_40GbE_rx_serial_r(11 DOWNTO 8) <= unb2b_board_ring_io_serial_rx_arr(3+c_ring_bus_w DOWNTO c_ring_bus_w);
+
u_ta2_unb2b_40GbE : ENTITY work.ta2_unb2b_40GbE
+ GENERIC MAP (
+ g_nof_mac => c_nof_40GbE_IP
+ )
PORT MAP (
config_clk => mm_clk,
config_reset => mm_rst,
clk_ref_r => SA_CLK,
- tx_serial_r => unb2b_board_front_io_serial_tx_arr(7 DOWNTO 4),
- rx_serial_r => unb2b_board_front_io_serial_rx_arr(7 DOWNTO 4),
+ tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_reset => i_kernel_rst,
- kernel_src_data => board_kernel_stream_src_40GbE_data,
- kernel_src_valid => board_kernel_stream_src_40GbE_valid,
- kernel_src_ready => board_kernel_stream_src_40GbE_ready,
-
- kernel_snk_data => board_kernel_stream_snk_40GbE_data,
- kernel_snk_valid => board_kernel_stream_snk_40GbE_valid,
- kernel_snk_ready => board_kernel_stream_snk_40GbE_ready,
-
- rx_status => ta2_unb2b_40gbe_rx_status_rx_status
+ src_out_arr => ta2_unb2b_40GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_40GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
);
----------
@@ -423,7 +482,7 @@ BEGIN
PORT MAP(
board_kernel_clk_clk => board_kernel_clk_clk,
board_kernel_clk2x_clk => board_kernel_clk2x_clk,
- board_kernel_reset_reset_n => board_kernel_reset_reset_n,
+ board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
board_kernel_irq_irq => board_kernel_irq_irq,
board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
board_kernel_cra_readdata => board_kernel_cra_readdata,
@@ -443,12 +502,26 @@ BEGIN
board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
- board_kernel_stream_src_40GbE_data => board_kernel_stream_src_40GbE_data,
- board_kernel_stream_src_40GbE_valid => board_kernel_stream_src_40GbE_valid,
- board_kernel_stream_src_40GbE_ready => board_kernel_stream_src_40GbE_ready,
- board_kernel_stream_snk_40GbE_data => board_kernel_stream_snk_40GbE_data,
- board_kernel_stream_snk_40GbE_valid => board_kernel_stream_snk_40GbE_valid,
- board_kernel_stream_snk_40GbE_ready => board_kernel_stream_snk_40GbE_ready,
+ board_kernel_stream_src_40GbE_data => ta2_unb2b_40GbE_src_out_arr(0).data(263 DOWNTO 0),
+ board_kernel_stream_src_40GbE_valid => ta2_unb2b_40GbE_src_out_arr(0).valid,
+ board_kernel_stream_src_40GbE_ready => ta2_unb2b_40GbE_src_in_arr(0).ready,
+ board_kernel_stream_snk_40GbE_data => ta2_unb2b_40GbE_snk_in_arr(0).data(263 DOWNTO 0),
+ board_kernel_stream_snk_40GbE_valid => ta2_unb2b_40GbE_snk_in_arr(0).valid,
+ board_kernel_stream_snk_40GbE_ready => ta2_unb2b_40GbE_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_40GbE_ring_0_data => ta2_unb2b_40GbE_src_out_arr(1).data(263 DOWNTO 0),
+ board_kernel_stream_src_40GbE_ring_0_valid => ta2_unb2b_40GbE_src_out_arr(1).valid,
+ board_kernel_stream_src_40GbE_ring_0_ready => ta2_unb2b_40GbE_src_in_arr(1).ready,
+ board_kernel_stream_snk_40GbE_ring_0_data => ta2_unb2b_40GbE_snk_in_arr(1).data(263 DOWNTO 0),
+ board_kernel_stream_snk_40GbE_ring_0_valid => ta2_unb2b_40GbE_snk_in_arr(1).valid,
+ board_kernel_stream_snk_40GbE_ring_0_ready => ta2_unb2b_40GbE_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_40GbE_ring_1_data => ta2_unb2b_40GbE_src_out_arr(2).data(263 DOWNTO 0),
+ board_kernel_stream_src_40GbE_ring_1_valid => ta2_unb2b_40GbE_src_out_arr(2).valid,
+ board_kernel_stream_src_40GbE_ring_1_ready => ta2_unb2b_40GbE_src_in_arr(2).ready,
+ board_kernel_stream_snk_40GbE_ring_1_data => ta2_unb2b_40GbE_snk_in_arr(2).data(263 DOWNTO 0),
+ board_kernel_stream_snk_40GbE_ring_1_valid => ta2_unb2b_40GbE_snk_in_arr(2).valid,
+ board_kernel_stream_snk_40GbE_ring_1_ready => ta2_unb2b_40GbE_snk_out_arr(2).ready,
board_kernel_stream_src_10GbE_data => board_kernel_stream_src_10GbE_data,
board_kernel_stream_src_10GbE_valid => board_kernel_stream_src_10GbE_valid,
@@ -472,6 +545,20 @@ BEGIN
i_reset_n <= NOT mm_rst;
i_kernel_rst <= NOT board_kernel_reset_reset_n;
+
+ -- Kernel should start later than BSP
+ u_common_areset : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '0',
+ g_delay_len => 9
+ )
+ PORT MAP (
+ in_rst => i_kernel_rst,
+ clk => board_kernel_clk_clk,
+ out_rst => board_kernel_reset_reset_n_in
+ );
+
+
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top_components_pkg.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top_components_pkg.vhd
index 748b2e5a8d..a84c59fdcd 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top_components_pkg.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top_components_pkg.vhd
@@ -212,7 +212,21 @@ PACKAGE top_components_pkg IS
board_kernel_stream_snk_40GbE_data : out std_logic_vector(263 downto 0);
board_kernel_stream_snk_40GbE_valid : out std_logic;
board_kernel_stream_snk_40GbE_ready : in std_logic;
-
+
+ board_kernel_stream_src_40GbE_ring_0_data : in std_logic_vector(263 downto 0);
+ board_kernel_stream_src_40GbE_ring_0_valid : in std_logic;
+ board_kernel_stream_src_40GbE_ring_0_ready : out std_logic;
+ board_kernel_stream_snk_40GbE_ring_0_data : out std_logic_vector(263 downto 0);
+ board_kernel_stream_snk_40GbE_ring_0_valid : out std_logic;
+ board_kernel_stream_snk_40GbE_ring_0_ready : in std_logic;
+
+ board_kernel_stream_src_40GbE_ring_1_data : in std_logic_vector(263 downto 0);
+ board_kernel_stream_src_40GbE_ring_1_valid : in std_logic;
+ board_kernel_stream_src_40GbE_ring_1_ready : out std_logic;
+ board_kernel_stream_snk_40GbE_ring_1_data : out std_logic_vector(263 downto 0);
+ board_kernel_stream_snk_40GbE_ring_1_valid : out std_logic;
+ board_kernel_stream_snk_40GbE_ring_1_ready : in std_logic;
+
board_kernel_stream_src_10GbE_data : in std_logic_vector(71 downto 0);
board_kernel_stream_src_10GbE_valid : in std_logic;
board_kernel_stream_src_10GbE_ready : out std_logic;
--
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