diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
index 1fc9befefb64f95e626b59894d0a2e94830d2eef..6ce8ab3ad0c35044bf61dab3bb03a52eb2bcde9e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
@@ -40,9 +40,9 @@
--
-- Development steps:
-- . Step 1 ~1 day work (idea started earlier, so requirements were clear),
--- steps 2,5 ~1.5 days work (fixing details and verifying all features),
--- steps 3,4 ~0.5 day work,
--- total ~3 days work spent in ~ 1 week.
+-- steps 2,5 ~2 days work (fixing details and verifying all features),
+-- steps 3,4 ~1 day work,
+-- total ~4 days work spent in ~ 1 week.
-- 1a Draft design description of dp_bsn_sync_scheduler
-- b Initial implementation that compiles
-- 2a Initial tb using u_stimuli to generate in_sosi and using p_stimuli
@@ -130,7 +130,7 @@ ARCHITECTURE tb OF tb_dp_bsn_sync_scheduler IS
SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
SIGNAL ctrl_interval_size : NATURAL := g_nof_samples_per_output_sync;
SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL mon_input_current_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
+ SIGNAL mon_current_input_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL mon_input_bsn_at_sync : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL mon_output_enable : STD_LOGIC;
SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
@@ -161,7 +161,6 @@ ARCHITECTURE tb OF tb_dp_bsn_sync_scheduler IS
SIGNAL verifying_sync_equal : STD_LOGIC := '0';
SIGNAL prev_out_enable : STD_LOGIC := '0';
- SIGNAL pending_out_enable : STD_LOGIC := '0';
SIGNAL pending_out_disable : STD_LOGIC := '0';
SIGNAL expected_out_enable : STD_LOGIC := '0';
SIGNAL expecting_out_start : STD_LOGIC := '0';
@@ -358,56 +357,39 @@ BEGIN
END IF;
END PROCESS;
- p_expected_out_enable : PROCESS(ctrl_enable, ctrl_enable_evt, in_sosi, ctrl_start_bsn, out_enable, pending_out_enable, pending_out_disable, hold_out_eop)
+ -- Determine expected out_enable
+ p_expected_out_enable : PROCESS(ctrl_enable, ctrl_enable_evt, in_sosi, ctrl_start_bsn, out_enable, pending_out_disable, hold_out_eop)
BEGIN
- -- Determine expected out_enable
- IF ctrl_enable = '1' THEN
- -- Detect output enable event
- IF ctrl_enable_evt = '1' THEN
- -- Determine whether the output enable event is scheduled in the future
- IF UNSIGNED(in_sosi.bsn) < UNSIGNED(ctrl_start_bsn) THEN
- pending_out_enable <= '1';
-
- -- Detect output re-enable event, to plan output disable before re-enable
- IF out_enable = '1' THEN
- IF hold_out_eop = '1' THEN
- expected_out_enable <= '0';
- ELSE
- pending_out_disable <= '1';
- END IF;
- END IF;
- END IF; -- else ignore output enable event in the past
- END IF;
+ -- Expect output disable after ctrl_enable_evt
+ IF ctrl_enable_evt = '1' THEN
+ IF out_enable = '0' THEN
+ -- Output is already disabled
+ expected_out_enable <= '0';
+ ELSE
+ -- Output is enabled, so this is a re-enable event.
+ IF hold_out_eop = '1' THEN
+ expected_out_enable <= '0'; -- end of block, so output can disable immediately
+ ELSE
+ pending_out_disable <= '1'; -- plan output disable before re-enable
+ END IF;
+ END IF;
+ END IF;
- -- Enable expected_out_enable at start BSN (and at in_sosi.sop)
- IF pending_out_enable = '1' THEN
- IF UNSIGNED(in_sosi.bsn) >= UNSIGNED(ctrl_start_bsn) THEN
- expected_out_enable <= '1';
- pending_out_enable <= '0';
- END IF;
- END IF;
- ELSE
- -- Immediately remove any pending output enable
- pending_out_enable <= '0';
-
- -- Detect output disable event, to plan output disable
- IF ctrl_enable_evt = '1' THEN
- IF hold_out_eop = '1' THEN
- expected_out_enable <= '0';
- ELSE
- pending_out_disable <= '1';
- END IF;
+ IF pending_out_disable <= '1' THEN
+ IF hold_out_eop = '1' THEN
+ expected_out_enable <= '0'; -- end of block, so output can disable
+ pending_out_disable <= '0';
END IF;
END IF;
- -- Expected out_enable disabled between block boundaries
- IF pending_out_disable = '1' AND hold_out_eop = '1' THEN
- expected_out_enable <= '0';
- pending_out_disable <= '0';
+ -- Expect output enable at start BSN
+ IF ctrl_enable = '1' THEN
+ IF UNSIGNED(in_sosi.bsn) >= UNSIGNED(ctrl_start_bsn) THEN
+ expected_out_enable <= '1';
+ END IF;
END IF;
END PROCESS;
-
p_verify_out_enable : PROCESS(clk)
BEGIN
-- Use registered values to compare, to avoid combinatorial differences
@@ -470,7 +452,7 @@ BEGIN
REPORT "Unexpected out_start" SEVERITY ERROR;
END IF;
- -- Check when out_enable goes high whether out_start is missed
+ -- Check that out_start is active when out_enable goes high
IF out_start = '0' AND out_enable = '1' AND prev_out_enable = '0' THEN
REPORT "Missed out_start" SEVERITY ERROR;
END IF;
@@ -509,20 +491,7 @@ BEGIN
-----------------------------------------------------------------------------
-- . Verify out_sosi.sync interval
-----------------------------------------------------------------------------
- p_verify_sync : PROCESS(clk)
- BEGIN
- IF rising_edge(clk) THEN
- IF ctrl_enable = '1' AND ctrl_enable_evt = '1' THEN
- verify_sync <= '0'; -- request for new sync interval
- ELSIF out_start = '1' THEN
- verify_sync <= '1'; -- new sync interval has started;
- END IF;
-
- IF recover_from_in_lost = '1' THEN
- verify_sync <= '0'; -- after long input lost, first output_sync may get lost during catch up
- END IF;
- END IF;
- END PROCESS;
+ verify_sync <= NOT recover_from_in_lost;
proc_dp_verify_sync(TO_UINT(ctrl_start_bsn),
ctrl_interval_size,
@@ -553,8 +522,8 @@ BEGIN
IF rising_edge(clk) THEN
IF recover_from_in_lost = '0' THEN
IF out_sop_dly = '1' THEN
- v_bsn_min := TO_UINT(mon_input_current_bsn) - 1;
- v_bsn_max := TO_UINT(mon_input_current_bsn) + c_output_nof_blocks_min + 1;
+ v_bsn_min := TO_UINT(mon_current_input_bsn) - 1;
+ v_bsn_max := TO_UINT(mon_current_input_bsn) + c_output_nof_blocks_min + 1;
ASSERT TO_UINT(mon_output_sync_bsn) >= v_bsn_min
REPORT "Wrong: mon_output_sync_bsn is behind (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " < " & int_to_str(v_bsn_min) & ")" SEVERITY ERROR;
@@ -562,7 +531,7 @@ BEGIN
REPORT "Wrong: mon_output_sync_bsn is too far ahead (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " > " & int_to_str(v_bsn_max) & ")" SEVERITY ERROR;
--Debug report used to investigate v_bsn_min and v_bsn_max assert conditions
- --REPORT int_to_str(TO_UINT(mon_output_sync_bsn)) & " : " & int_to_str(TO_UINT(mon_input_current_bsn)) SEVERITY NOTE;
+ --REPORT int_to_str(TO_UINT(mon_output_sync_bsn)) & " : " & int_to_str(TO_UINT(mon_current_input_bsn)) SEVERITY NOTE;
END IF;
END IF;
END IF;
@@ -588,7 +557,7 @@ BEGIN
ctrl_enable_evt => ctrl_enable_evt,
ctrl_interval_size => ctrl_interval_size,
ctrl_start_bsn => ctrl_start_bsn,
- mon_input_current_bsn => mon_input_current_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
mon_input_bsn_at_sync => mon_input_bsn_at_sync,
mon_output_enable => mon_output_enable,
mon_output_sync_bsn => mon_output_sync_bsn,