diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
index 4da60d79b3503244bdcbcc2bba437d62e4f7c352..9376a133bfadee22b4e81be3194ac42cb2c943a3 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
@@ -516,7 +516,14 @@ begin
   -- Simulation end
   ------------------------------------------------------------------------------
 
-  sim_done <= '1' when dp_sosi_arr(0).valid = '1' and dp_sosi_arr(1).valid = '1' and dp_sosi_arr(2).valid = '1' else '0';
+  -- Wait long enough, until jesd204b_rx_link_valid = '1' in the JESD204B IP.
+  -- Cannot use dp_sosi_valid, because the dp_sosi_valid already becomes '1' as
+  -- soon as the rxlink_clk and dp_clk are active, because then the
+  -- dp_sosi_data is already synchronous with the sysref and can be passed on
+  -- via the rxlink_clk - dp_clk FIFO. The content of the dp_sosi_data is
+  -- then not yet correct, but it will be as soon as the
+  -- jesd204b_rx_link_valid_arr(i) for that input i is '1'
+  sim_done <= '1' after 60 us;  -- >~ 50 us obtained from Wave Window
 
   p_tb_end : process
   begin