From e6db3b3c1819d6f978d89da4213c4eefbcd126ce Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Thu, 9 Dec 2021 08:59:16 +0100 Subject: [PATCH] added new revision TBs --- .../tb_lofar2_unb2b_ring_full.vhd | 164 ++++++++++++++++++ .../tb_lofar2_unb2b_ring_one.vhd | 164 ++++++++++++++++++ .../tb_lofar2_unb2c_ring_full.vhd | 150 ++++++++++++++++ .../tb_lofar2_unb2c_ring_one.vhd | 150 ++++++++++++++++ 4 files changed, 628 insertions(+) create mode 100644 applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd create mode 100644 applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd create mode 100644 applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd create mode 100644 applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd new file mode 100644 index 0000000000..e123b12a47 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +-- Author: Reinier vd Walle +-- Purpose: Tb to show that lofar2_unb2b_ring_full can simulate +-- Description: +-- This is a compile-only test bench +-- Usage: +-- Load sim # check that design can load in vsim +-- > as 10 # check that the hierarchy for g_design_name is complete +-- > run -a # check that design can simulate some us without error + +LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, tech_pll_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; +USE tech_pll_lib.tech_pll_component_pkg.ALL; + +ENTITY tb_lofar2_unb2b_ring_full IS +END tb_lofar2_unb2b_ring_full; + +ARCHITECTURE tb OF tb_lofar2_unb2b_ring_full IS + + CONSTANT c_sim : BOOLEAN := TRUE; + CONSTANT c_unb_nr : NATURAL := 0; + CONSTANT c_node_nr : NATURAL := 0; + CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; + CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0); + + CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard + CONSTANT c_ext_clk_period : TIME := 5 ns; + CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz + CONSTANT c_pps_period : NATURAL := 1000; + + -- Tb + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL sim_done : STD_LOGIC := '0'; + + -- DUT + SIGNAL ext_clk : STD_LOGIC := '0'; + SIGNAL pps : STD_LOGIC := '0'; + + SIGNAL WDI : STD_LOGIC; + SIGNAL INTA : STD_LOGIC; + SIGNAL INTB : STD_LOGIC; + + SIGNAL eth_clk : STD_LOGIC := '0'; + SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); + SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); + + SIGNAL sens_scl : STD_LOGIC; + SIGNAL sens_sda : STD_LOGIC; + SIGNAL pmbus_scl : STD_LOGIC; + SIGNAL pmbus_sda : STD_LOGIC; + + SIGNAL SA_CLK : STD_LOGIC := '1'; + + SIGNAL i_QSFP_0_TX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_QSFP_0_RX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_0_TX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_0_RX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_1_TX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_1_RX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + + +BEGIN + + + ---------------------------------------------------------------------------- + -- System setup + ---------------------------------------------------------------------------- + ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz) + eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) + SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz) + + INTA <= 'H'; -- pull up + INTB <= 'H'; -- pull up + + sens_scl <= 'H'; -- pull up + sens_sda <= 'H'; -- pull up + pmbus_scl <= 'H'; -- pull up + pmbus_sda <= 'H'; -- pull up + + ------------------------------------------------------------------------------ + -- DUT + ------------------------------------------------------------------------------ + u_lofar_unb2b_ring_full : ENTITY work.lofar2_unb2b_ring_full + GENERIC MAP ( + g_sim => c_sim, + g_sim_unb_nr => c_unb_nr, + g_sim_node_nr => c_node_nr + ) + PORT MAP ( + -- GENERAL + CLK => ext_clk, + PPS => pps, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + -- Others + VERSION => c_version, + ID => c_id, + TESTIO => open, + + -- I2C Interface to Sensors + SENS_SC => sens_scl, + SENS_SD => sens_sda, + + PMBUS_SC => pmbus_scl, + PMBUS_SD => pmbus_sda, + PMBUS_ALERT => open, + + -- 1GbE Control Interface + ETH_CLK => eth_clk, + ETH_SGIN => eth_rxp, + ETH_SGOUT => eth_txp, + + -- Transceiver clocks + SA_CLK => SA_CLK, + + -- front transceivers + QSFP_0_RX => i_QSFP_0_RX, + QSFP_0_TX => i_QSFP_0_TX, + + -- ring transceivers + RING_0_RX => i_RING_0_RX, + RING_0_TX => i_RING_0_TX, + RING_1_RX => i_RING_1_RX, + RING_1_TX => i_RING_1_TX, + + -- LEDs + QSFP_LED => OPEN + ); + + + ------------------------------------------------------------------------------ + -- Simulation end + ------------------------------------------------------------------------------ + sim_done <= '0', '1' AFTER 1 us; + + proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end); + +END tb; diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd new file mode 100644 index 0000000000..df58228220 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +-- Author: Reinier vd Walle +-- Purpose: Tb to show that lofar2_unb2b_ring_one can simulate +-- Description: +-- This is a compile-only test bench +-- Usage: +-- Load sim # check that design can load in vsim +-- > as 10 # check that the hierarchy for g_design_name is complete +-- > run -a # check that design can simulate some us without error + +LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, tech_pll_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; +USE tech_pll_lib.tech_pll_component_pkg.ALL; + +ENTITY tb_lofar2_unb2b_ring_one IS +END tb_lofar2_unb2b_ring_one; + +ARCHITECTURE tb OF tb_lofar2_unb2b_ring_one IS + + CONSTANT c_sim : BOOLEAN := TRUE; + CONSTANT c_unb_nr : NATURAL := 0; + CONSTANT c_node_nr : NATURAL := 0; + CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; + CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0); + + CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard + CONSTANT c_ext_clk_period : TIME := 5 ns; + CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz + CONSTANT c_pps_period : NATURAL := 1000; + + -- Tb + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL sim_done : STD_LOGIC := '0'; + + -- DUT + SIGNAL ext_clk : STD_LOGIC := '0'; + SIGNAL pps : STD_LOGIC := '0'; + + SIGNAL WDI : STD_LOGIC; + SIGNAL INTA : STD_LOGIC; + SIGNAL INTB : STD_LOGIC; + + SIGNAL eth_clk : STD_LOGIC := '0'; + SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); + SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); + + SIGNAL sens_scl : STD_LOGIC; + SIGNAL sens_sda : STD_LOGIC; + SIGNAL pmbus_scl : STD_LOGIC; + SIGNAL pmbus_sda : STD_LOGIC; + + SIGNAL SA_CLK : STD_LOGIC := '1'; + + SIGNAL i_QSFP_0_TX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_QSFP_0_RX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_0_TX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_0_RX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_1_TX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_1_RX : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + + +BEGIN + + + ---------------------------------------------------------------------------- + -- System setup + ---------------------------------------------------------------------------- + ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz) + eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) + SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz) + + INTA <= 'H'; -- pull up + INTB <= 'H'; -- pull up + + sens_scl <= 'H'; -- pull up + sens_sda <= 'H'; -- pull up + pmbus_scl <= 'H'; -- pull up + pmbus_sda <= 'H'; -- pull up + + ------------------------------------------------------------------------------ + -- DUT + ------------------------------------------------------------------------------ + u_lofar_unb2b_ring_one : ENTITY work.lofar2_unb2b_ring_one + GENERIC MAP ( + g_sim => c_sim, + g_sim_unb_nr => c_unb_nr, + g_sim_node_nr => c_node_nr + ) + PORT MAP ( + -- GENERAL + CLK => ext_clk, + PPS => pps, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + -- Others + VERSION => c_version, + ID => c_id, + TESTIO => open, + + -- I2C Interface to Sensors + SENS_SC => sens_scl, + SENS_SD => sens_sda, + + PMBUS_SC => pmbus_scl, + PMBUS_SD => pmbus_sda, + PMBUS_ALERT => open, + + -- 1GbE Control Interface + ETH_CLK => eth_clk, + ETH_SGIN => eth_rxp, + ETH_SGOUT => eth_txp, + + -- Transceiver clocks + SA_CLK => SA_CLK, + + -- front transceivers + QSFP_0_RX => i_QSFP_0_RX, + QSFP_0_TX => i_QSFP_0_TX, + + -- ring transceivers + RING_0_RX => i_RING_0_RX, + RING_0_TX => i_RING_0_TX, + RING_1_RX => i_RING_1_RX, + RING_1_TX => i_RING_1_TX, + + -- LEDs + QSFP_LED => OPEN + ); + + + ------------------------------------------------------------------------------ + -- Simulation end + ------------------------------------------------------------------------------ + sim_done <= '0', '1' AFTER 1 us; + + proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end); + +END tb; diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd new file mode 100644 index 0000000000..634281c919 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd @@ -0,0 +1,150 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +-- Author: Reinier vd Walle +-- Purpose: Tb to show that lofar2_unb2c_ring_full can simulate +-- Description: +-- This is a compile-only test bench +-- Usage: +-- Load sim # check that design can load in vsim +-- > as 10 # check that the hierarchy for g_design_name is complete +-- > run -a # check that design can simulate some us without error + +LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, tech_pll_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE unb2c_board_lib.unb2c_board_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; +USE tech_pll_lib.tech_pll_component_pkg.ALL; + +ENTITY tb_lofar2_unb2c_ring_full IS +END tb_lofar2_unb2c_ring_full; + +ARCHITECTURE tb OF tb_lofar2_unb2c_ring_full IS + + CONSTANT c_sim : BOOLEAN := TRUE; + CONSTANT c_unb_nr : NATURAL := 0; + CONSTANT c_node_nr : NATURAL := 0; + CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; + CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0); + + CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard + CONSTANT c_ext_clk_period : TIME := 5 ns; + CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz + CONSTANT c_pps_period : NATURAL := 1000; + + -- Tb + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL sim_done : STD_LOGIC := '0'; + + -- DUT + SIGNAL ext_clk : STD_LOGIC := '0'; + SIGNAL pps : STD_LOGIC := '0'; + + SIGNAL WDI : STD_LOGIC; + SIGNAL INTA : STD_LOGIC; + SIGNAL INTB : STD_LOGIC; + + SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0'); + SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0); + SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0); + + SIGNAL sens_scl : STD_LOGIC; + SIGNAL sens_sda : STD_LOGIC; + SIGNAL pmbus_scl : STD_LOGIC; + SIGNAL pmbus_sda : STD_LOGIC; + + SIGNAL SA_CLK : STD_LOGIC := '1'; + + SIGNAL i_QSFP_0_TX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_QSFP_0_RX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_0_TX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_0_RX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_1_TX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_1_RX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + + +BEGIN + + + ---------------------------------------------------------------------------- + -- System setup + ---------------------------------------------------------------------------- + ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz) + eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) + SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz) + + INTA <= 'H'; -- pull up + INTB <= 'H'; -- pull up + ------------------------------------------------------------------------------ + -- DUT + ------------------------------------------------------------------------------ + u_lofar_unb2c_ring_full : ENTITY work.lofar2_unb2c_ring_full + GENERIC MAP ( + g_sim => c_sim, + g_sim_unb_nr => c_unb_nr, + g_sim_node_nr => c_node_nr + ) + PORT MAP ( + -- GENERAL + CLK => ext_clk, + PPS => pps, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + -- Others + VERSION => c_version, + ID => c_id, + TESTIO => open, + + -- 1GbE Control Interface + ETH_CLK => eth_clk, + ETH_SGIN => eth_rxp, + ETH_SGOUT => eth_txp, + + -- Transceiver clocks + SA_CLK => SA_CLK, + + -- front transceivers + QSFP_0_RX => i_QSFP_0_RX, + QSFP_0_TX => i_QSFP_0_TX, + + -- ring transceivers + RING_0_RX => i_RING_0_RX, + RING_0_TX => i_RING_0_TX, + RING_1_RX => i_RING_1_RX, + RING_1_TX => i_RING_1_TX, + + -- LEDs + QSFP_LED => OPEN + ); + + + ------------------------------------------------------------------------------ + -- Simulation end + ------------------------------------------------------------------------------ + sim_done <= '0', '1' AFTER 1 us; + + proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end); + +END tb; diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd new file mode 100644 index 0000000000..afa9c39b3f --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd @@ -0,0 +1,150 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +-- Author: Reinier vd Walle +-- Purpose: Tb to show that lofar2_unb2c_ring_one can simulate +-- Description: +-- This is a compile-only test bench +-- Usage: +-- Load sim # check that design can load in vsim +-- > as 10 # check that the hierarchy for g_design_name is complete +-- > run -a # check that design can simulate some us without error + +LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, tech_pll_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE unb2c_board_lib.unb2c_board_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; +USE tech_pll_lib.tech_pll_component_pkg.ALL; + +ENTITY tb_lofar2_unb2c_ring_one IS +END tb_lofar2_unb2c_ring_one; + +ARCHITECTURE tb OF tb_lofar2_unb2c_ring_one IS + + CONSTANT c_sim : BOOLEAN := TRUE; + CONSTANT c_unb_nr : NATURAL := 0; + CONSTANT c_node_nr : NATURAL := 0; + CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; + CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0); + + CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard + CONSTANT c_ext_clk_period : TIME := 5 ns; + CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz + CONSTANT c_pps_period : NATURAL := 1000; + + -- Tb + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL sim_done : STD_LOGIC := '0'; + + -- DUT + SIGNAL ext_clk : STD_LOGIC := '0'; + SIGNAL pps : STD_LOGIC := '0'; + + SIGNAL WDI : STD_LOGIC; + SIGNAL INTA : STD_LOGIC; + SIGNAL INTB : STD_LOGIC; + + SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0'); + SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0); + SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0); + + SIGNAL sens_scl : STD_LOGIC; + SIGNAL sens_sda : STD_LOGIC; + SIGNAL pmbus_scl : STD_LOGIC; + SIGNAL pmbus_sda : STD_LOGIC; + + SIGNAL SA_CLK : STD_LOGIC := '1'; + + SIGNAL i_QSFP_0_TX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_QSFP_0_RX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_0_TX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_0_RX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_1_TX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL i_RING_1_RX : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0'); + + +BEGIN + + + ---------------------------------------------------------------------------- + -- System setup + ---------------------------------------------------------------------------- + ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz) + eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) + SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz) + + INTA <= 'H'; -- pull up + INTB <= 'H'; -- pull up + ------------------------------------------------------------------------------ + -- DUT + ------------------------------------------------------------------------------ + u_lofar_unb2c_ring_one : ENTITY work.lofar2_unb2c_ring_one + GENERIC MAP ( + g_sim => c_sim, + g_sim_unb_nr => c_unb_nr, + g_sim_node_nr => c_node_nr + ) + PORT MAP ( + -- GENERAL + CLK => ext_clk, + PPS => pps, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + -- Others + VERSION => c_version, + ID => c_id, + TESTIO => open, + + -- 1GbE Control Interface + ETH_CLK => eth_clk, + ETH_SGIN => eth_rxp, + ETH_SGOUT => eth_txp, + + -- Transceiver clocks + SA_CLK => SA_CLK, + + -- front transceivers + QSFP_0_RX => i_QSFP_0_RX, + QSFP_0_TX => i_QSFP_0_TX, + + -- ring transceivers + RING_0_RX => i_RING_0_RX, + RING_0_TX => i_RING_0_TX, + RING_1_RX => i_RING_1_RX, + RING_1_TX => i_RING_1_TX, + + -- LEDs + QSFP_LED => OPEN + ); + + + ------------------------------------------------------------------------------ + -- Simulation end + ------------------------------------------------------------------------------ + sim_done <= '0', '1' AFTER 1 us; + + proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end); + +END tb; -- GitLab