diff --git a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..b02941d9d7053d1b7f6870d07711a78c449dc14b --- /dev/null +++ b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg @@ -0,0 +1,34 @@ +hdl_lib_name = unb2a_led +hdl_library_clause_name = unb2a_led_lib +hdl_lib_uses_synth = common technology unb2a_board +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e3sge3 + +synth_files = + src/vhdl/unb2a_led.vhd + +test_bench_files = + tb/vhdl/tb_unb2a_led.vhd + + +[modelsim_project_file] + + +[quartus_project_file] +synth_top_level_entity = + +quartus_copy_files = + +quartus_qsf_files = + $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf + +quartus_sdc_files = + $RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc + +quartus_tcl_files = + quartus/unb2a_minimal_pins.tcl + +quartus_vhdl_files = + +quartus_qip_files = + diff --git a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl new file mode 100644 index 0000000000000000000000000000000000000000..f0e1fcbcc2838bca140bbe67dfdcb1c17ac639ec --- /dev/null +++ b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl @@ -0,0 +1,22 @@ +############################################################################### +# +# Copyright (C) 2014 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +############################################################################### + +source $::env(RADIOHDL)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl diff --git a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd new file mode 100644 index 0000000000000000000000000000000000000000..77283d0e6b17101c6b337204f2720d6398ac079e --- /dev/null +++ b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd @@ -0,0 +1,232 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2016 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, unb2a_board_lib, technology_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE unb2a_board_lib.unb2_board_pkg.ALL; + +ENTITY unb2a_led IS + GENERIC ( + g_design_name : STRING := "unb2a_led"; + g_design_note : STRING := "UNUSED"; + g_technology : NATURAL := c_tech_arria10_e3sge3; + g_sim : BOOLEAN := FALSE; --Overridden by TB + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF + g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF + g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF + g_factory_image : BOOLEAN := TRUE + ); + PORT ( + ETH_CLK : IN STD_LOGIC; -- 125 MHz + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0); + QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0) + ); +END unb2a_led; + + +ARCHITECTURE str OF unb2a_led IS + + -- Firmware version x.y + CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1); + CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg + CONSTANT c_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_50M; + + -- System + SIGNAL i_xo_ethclk : STD_LOGIC; + SIGNAL i_xo_rst : STD_LOGIC; + SIGNAL i_mm_rst : STD_LOGIC; + SIGNAL i_mm_clk : STD_LOGIC; + SIGNAL mm_locked : STD_LOGIC; + + SIGNAL clk125 : STD_LOGIC := '1'; + SIGNAL clk100 : STD_LOGIC := '1'; + SIGNAL clk50 : STD_LOGIC := '1'; + + SIGNAL cs_sim : STD_LOGIC; + SIGNAL xo_ethclk : STD_LOGIC; + SIGNAL xo_rst : STD_LOGIC; + SIGNAL xo_rst_n : STD_LOGIC; + SIGNAL mm_clk : STD_LOGIC; + SIGNAL mm_rst : STD_LOGIC; + + SIGNAL pulse_10Hz : STD_LOGIC; + SIGNAL pulse_10Hz_extended : STD_LOGIC; + SIGNAL mm_pulse_ms : STD_LOGIC; + SIGNAL mm_pulse_s : STD_LOGIC; + + SIGNAL led_toggle : STD_LOGIC; + SIGNAL led_flash : STD_LOGIC; + SIGNAL led_flash_red : STD_LOGIC; + SIGNAL led_flash_green : STD_LOGIC; + + -- QSFP leds + SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0); + SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0); + +BEGIN + xo_ethclk <= i_xo_ethclk; + xo_rst <= i_xo_rst; + xo_rst_n <= NOT i_xo_rst; + mm_clk <= i_mm_clk; + mm_rst <= i_mm_rst; + + ----------------------------------------------------------------------------- + -- xo_ethclk = ETH_CLK + ----------------------------------------------------------------------------- + + i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk + + u_common_areset_xo : ENTITY common_lib.common_areset + GENERIC MAP ( + g_rst_level => '1', -- power up default will be inferred in FPGA + g_delay_len => c_reset_len + ) + PORT MAP ( + in_rst => '0', -- release reset after some clock cycles + clk => i_xo_ethclk, + out_rst => i_xo_rst + ); + + ----------------------------------------------------------------------------- + -- mm_clk + -- . use mm_sim_clk in sim + -- . derived from ETH_CLK via PLL on hardware + ----------------------------------------------------------------------------- + + i_mm_clk <= clk50; + + gen_mm_clk_sim: IF g_sim = TRUE GENERATE + clk50 <= NOT clk50 AFTER 10 ns; -- 50 MHz, 20ns/2 + mm_locked <= '0', '1' AFTER 70 ns; + END GENERATE; + + gen_mm_clk_hardware: IF g_sim = FALSE GENERATE + u_unb2a_board_clk125_pll : ENTITY unb2a_board_lib.unb2_board_clk125_pll + GENERIC MAP ( + g_use_fpll => TRUE, + g_technology => g_technology + ) + PORT MAP ( + arst => i_xo_rst, + clk125 => i_xo_ethclk, + c1_clk50 => clk50, + pll_locked => mm_locked + ); + END GENERATE; + + u_unb2a_board_node_ctrl : ENTITY unb2a_board_lib.unb2_board_node_ctrl + GENERIC MAP ( + g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6 + ) + PORT MAP ( + -- MM clock domain reset + mm_clk => i_mm_clk, + mm_locked => mm_locked, + mm_rst => i_mm_rst, + -- WDI extend + mm_wdi_in => mm_pulse_s, + -- Pulses + mm_pulse_us => OPEN, + mm_pulse_ms => mm_pulse_ms, + mm_pulse_s => mm_pulse_s -- could be used to toggle a LED + ); + + ------------------------------------------------------------------------------ + -- Toggle red LED when unb2a_minimal is running, green LED for other designs. + ------------------------------------------------------------------------------ + led_flash_red <= sel_a_b(g_factory_image=TRUE, led_flash, '0'); + led_flash_green <= sel_a_b(g_factory_image=FALSE, led_flash, '0'); + + + u_extend : common_lib.common_pulse_extend + GENERIC MAP ( + g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec + ) + PORT MAP ( + rst => i_mm_rst, + clk => i_mm_clk, + p_in => mm_pulse_s, + ep_out => led_flash + ); + + + + + -- Red LED control + TESTIO(c_unb2_board_testio_led_red) <= led_flash_red; + + -- Green LED control + TESTIO(c_unb2_board_testio_led_green) <= led_flash_green; + + + + u_common_pulser_10Hz : ENTITY common_lib.common_pulser + GENERIC MAP ( + g_pulse_period => 100, + g_pulse_phase => 100-1 + ) + PORT MAP ( + rst => i_mm_rst, + clk => i_mm_clk, + clken => '1', + pulse_en => mm_pulse_ms, + pulse_out => pulse_10Hz + ); + + u_extend_10Hz : common_lib.common_pulse_extend + GENERIC MAP ( + g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec + ) + PORT MAP ( + rst => i_mm_rst, + clk => i_mm_clk, + p_in => pulse_10Hz, + ep_out => pulse_10Hz_extended + ); + + u_toggle : ENTITY common_lib.common_toggle + PORT MAP ( + rst => i_mm_rst, + clk => i_mm_clk, + in_dat => mm_pulse_s, + out_dat => led_toggle + ); + + QSFP_LED(2) <= pulse_10Hz_extended; + QSFP_LED(6) <= led_toggle; + QSFP_LED(7) <= NOT led_toggle; + QSFP_LED(10) <= led_toggle; + QSFP_LED(11) <= NOT led_toggle; + + -- red LEDs on bottom + QSFP_LED(1) <= '1'; + QSFP_LED(5) <= '1'; + QSFP_LED(9) <= '1'; + +END str; + diff --git a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a5704acc232e7ff02fe517c17739a659987df11f --- /dev/null +++ b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd @@ -0,0 +1,94 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2012 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: Test bench for unb2a_led. +-- Description: +-- The DUT can be targeted at unb 0, node 3 with the same Python scripts +-- that are used on hardware. +-- Usage: +-- On command line do: +-- > run_modelsim & (to start Modeslim) +-- +-- In Modelsim do: +-- > lp unb2a_led +-- > mk clean all (only first time to clean all libraries) +-- > mk all (to compile all libraries that are needed for unb2a_led) +-- . load tb_unb2a_led simulation by double clicking the tb_unb2a_led icon +-- > as 10 (to view signals in Wave Window) +-- > run 100 us (or run -all) +-- +-- + +LIBRARY IEEE, common_lib, unb2a_board_lib, ; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE unb2a_board_lib.unb2_board_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; + +ENTITY tb_unb2a_led IS + GENERIC ( + g_design_name : STRING := "unb2a_led"; + g_sim_unb_nr : NATURAL := 0; -- UniBoard 0 + g_sim_node_nr : NATURAL := 3 -- Node 3 + ); +END tb_unb2a_led; + +ARCHITECTURE tb OF tb_unb2a_led IS + + CONSTANT c_sim : BOOLEAN := TRUE; + + CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0 + CONSTANT c_node_nr : NATURAL := 3; -- Node 3 + + CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard + + -- DUT + SIGNAL eth_clk : STD_LOGIC := '0'; + SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0); + SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0); + +BEGIN + + ---------------------------------------------------------------------------- + -- System setup + ---------------------------------------------------------------------------- + eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz) + + ------------------------------------------------------------------------------ + -- DUT + ------------------------------------------------------------------------------ + u_unb2a_led : ENTITY work.unb2a_led + GENERIC MAP ( + g_sim => c_sim, + g_sim_unb_nr => c_unb_nr, + g_sim_node_nr => c_node_nr, + g_design_name => g_design_name + ) + PORT MAP ( + -- GENERAL + ETH_CLK => eth_clk, + TESTIO => TESTIO, + QSFP_LED => qsfp_led + ); + +END tb;