From e63a361bf3760ccc03b4042c9e7777403f6e8089 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Wed, 11 Feb 2015 09:13:39 +0000
Subject: [PATCH] -Cleaned the code.
---
.../correlator/src/vhdl/corr_accumulator.vhd | 3 ---
.../dsp/correlator/src/vhdl/corr_adder.vhd | 22 +------------------
2 files changed, 1 insertion(+), 24 deletions(-)
diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index 3c6b56e302..e148e80e3d 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -50,7 +50,6 @@ END corr_accumulator;
ARCHITECTURE str OF corr_accumulator IS
-- Complex accumulator data width: wide enough to support g_integration_period accumulations
--- CONSTANT c_acc_data_w : NATURAL := ceil_log2(g_integration_period*(pow2(g_data_w)-1));
CONSTANT c_acc_data_w : NATURAL := g_data_w + ceil_log2(g_integration_period);
-- c_shiftram_delay is such that common_shiftram output aligns exactly with snk_in_arr. Functionally this
@@ -163,8 +162,6 @@ BEGIN
-- of zeros initially.
-----------------------------------------------------------------------------
gen_src_out_arr : FOR i IN 0 TO g_nof_inputs-1 GENERATE
--- nxt_src_out_arr(i).re(c_acc_data_w-1 DOWNTO 0) <= common_shiftram_src_out_arr(i).data(2*c_acc_data_w-1 DOWNTO c_acc_data_w);
--- nxt_src_out_arr(i).im(c_acc_data_w-1 DOWNTO 0) <= common_shiftram_src_out_arr(i).data( c_acc_data_w-1 DOWNTO 0);
nxt_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_shiftram_src_out_arr(i).data(2*c_acc_data_w-1 DOWNTO c_acc_data_w));
nxt_src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_shiftram_src_out_arr(i).data( c_acc_data_w-1 DOWNTO 0));
diff --git a/libraries/dsp/correlator/src/vhdl/corr_adder.vhd b/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
index 53a162fe89..bfd22cf7d6 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
@@ -101,27 +101,7 @@ BEGIN
END GENERATE;
-----------------------------------------------------------------------------
- -- Wire the adder output of g_data_w+1 to output with g_data_w.
- -- We already have the needed bit width at the adder INPUTS, so we don't need
- -- an additional output bit.
- -- . g_data_w is already wide enough to carry the full adder output
- -- range (we don't need an extra bit for that).
- -- . We do need the extra bit itself though, as it is the sign bit.
- -----------------------------------------------------------------------------
--- gen_output_range : FOR i IN 0 TO g_nof_inputs-1 GENERATE
--- -- Wire the adder output to ranged_common_complex_add_sub_src_out_arr, minus the two MSbits
--- ranged_common_complex_add_sub_src_out_arr(i).re(g_data_w-1-1 DOWNTO 0) <= common_complex_add_sub_src_out_arr(i).re(g_data_w-1-1 DOWNTO 0);
--- ranged_common_complex_add_sub_src_out_arr(i).im(g_data_w-1-1 DOWNTO 0) <= common_complex_add_sub_src_out_arr(i).im(g_data_w-1-1 DOWNTO 0);
--- -- Don't assign the adder's MSbit-1 as it shouldn't toggle (because our adder input width is already wide enough)
--- -- NC <= common_complex_add_sub_src_out_arr(i).re(g_data_w-1);
--- -- NC <= common_complex_add_sub_src_out_arr(i).im(g_data_w-1);
--- -- Wire up the adder's MSbit (sign) bit
--- ranged_common_complex_add_sub_src_out_arr(i).re(g_data_w-1) <= common_complex_add_sub_src_out_arr(i).re(g_data_w);
--- ranged_common_complex_add_sub_src_out_arr(i).im(g_data_w-1) <= common_complex_add_sub_src_out_arr(i).im(g_data_w);
--- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- Finally, extend the sign bit for human readability
+ -- Extend the sign bit
-----------------------------------------------------------------------------
gen_sign_extend : FOR i IN 0 TO g_nof_inputs-1 GENERATE
src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_complex_add_sub_src_out_arr(i).re(g_data_w-1 DOWNTO 0));
--
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