diff --git a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd index f4389a0c568e6ced7a58b6b6fce7a9495b8b6827..d5c2aa8bae4fb3f648880ec3c3c3fe58640e2d41 100644 --- a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd +++ b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd @@ -41,14 +41,14 @@ USE work.dp_stream_pkg.ALL; ENTITY dp_reinterleave IS GENERIC ( - g_dat_w : NATURAL; - g_nof_in : NATURAL; - g_deint_block_size : NATURAL; -- Inputs streams will be de-interleaved using this block size. Should match block_size_out when g_use_ctrl=TRUE - g_nof_out : NATURAL; + g_dat_w : NATURAL; -- Width of the data. Either the width of the datafield or the re and im field combined. + g_nof_in : NATURAL; -- Number of input streams + g_deint_block_size : NATURAL; -- Inputs streams will be de-interleaved using this block size. Should match block_size_out when g_use_ctrl=TRUE + g_nof_out : NATURAL; -- The number of output streams g_inter_block_size : NATURAL; -- Outputs streams will be interleaved using this block size. Should match block_size_in when g_use_ctrl=TRUE - g_use_ctrl : BOOLEAN := TRUE; - g_use_complex : BOOLEAN; - g_align_out : BOOLEAN := FALSE + g_use_ctrl : BOOLEAN := TRUE; + g_use_complex : BOOLEAN; + g_align_out : BOOLEAN := FALSE ); PORT ( rst : IN STD_LOGIC; @@ -100,12 +100,12 @@ BEGIN u_reinterleave : ENTITY common_lib.common_reinterleave GENERIC MAP ( - g_nof_in => g_nof_in, - g_deint_block_size => g_deint_block_size, - g_nof_out => g_nof_out, + g_nof_in => g_nof_in, + g_deint_block_size => g_deint_block_size, + g_nof_out => g_nof_out, g_inter_block_size => g_inter_block_size, - g_dat_w => g_dat_w, - g_align_out => g_align_out + g_dat_w => g_dat_w, + g_align_out => g_align_out ) PORT MAP ( rst => rst,