diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
index c6ea92794f33cd936adbcc890e040ebef90a66bb..63fcf15acd7d14b54d2ccaaee3523c73a32a68a7 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
@@ -158,8 +158,8 @@ ARCHITECTURE str OF node_unb1_terminal_bg_mesh_db IS
-- BSN Aligner
-----------------------------------------------------------------------------
CONSTANT c_bsn_align_nof_streams : NATURAL := c_bg_nof_streams;
- CONSTANT c_block_size : NATURAL := 176; --FIXME: current fn_beamformer output block size.
- CONSTANT c_block_period : NATURAL := 256;
+ CONSTANT c_block_size : NATURAL := 128; --FIXME: current fn_beamformer output block size.
+ CONSTANT c_block_period : NATURAL := 192;
CONSTANT c_bsn_align_latency : NATURAL := 3;
CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
@@ -262,41 +262,41 @@ BEGIN
u_mesh_terminal : ENTITY unb1_board_lib.unb1_board_terminals_mesh
GENERIC MAP(
- g_sim => g_sim, -- : BOOLEAN := FALSE;
- g_sim_level => g_sim_level, -- : NATURAL := 0;
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
-- System
- g_node_type => g_node_type, -- : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
- g_nof_bus => g_nof_bus, -- : NATURAL := 4; -- one bus to each of the 4 nodes on the other side of the mesh
+ g_node_type => g_node_type,
+ g_nof_bus => g_nof_bus,
-- User
- g_usr_use_complex => g_usr_use_complex, -- : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
- g_usr_data_w => g_usr_data_w, -- : NATURAL := 32; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
- g_usr_frame_len => g_usr_frame_len, -- : NATURAL := 20;
- g_usr_nof_streams => g_usr_nof_streams, -- : NATURAL := 4; -- number of user streams per bus
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ g_usr_nof_streams => g_usr_nof_streams,
-- Phy
- g_phy_nof_serial => g_phy_nof_serial, -- : NATURAL := 3; -- up to 4 serial lanes per bus
- g_phy_gx_mbps => g_phy_gx_mbps, -- : NATURAL := 5000;
- g_phy_rx_fifo_size => g_phy_rx_fifo_size, -- : NATURAL := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
- g_phy_ena_reorder => g_phy_ena_reorder, -- : BOOLEAN := TRUE;
+ g_phy_nof_serial => g_phy_nof_serial,
+ g_phy_gx_mbps => g_phy_gx_mbps,
+ g_phy_rx_fifo_size => g_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_phy_ena_reorder,
-- Tx
- g_use_tx => g_use_tx, -- : BOOLEAN := TRUE;
- g_tx_input_use_fifo => g_tx_input_use_fifo, -- : BOOLEAN := TRUE; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- g_tx_input_fifo_size => g_tx_input_fifo_size, -- : NATURAL := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
- g_tx_input_fifo_fill => g_tx_input_fifo_fill, -- : NATURAL := 0;
+ g_use_tx => g_use_tx,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
-- Rx
- g_use_rx => g_use_tx, -- : BOOLEAN := TRUE;
- g_rx_output_use_fifo => g_tx_input_use_fifo, -- : BOOLEAN := TRUE; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size => g_tx_input_fifo_size, -- : NATURAL := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
- g_rx_output_fifo_fill => g_tx_input_fifo_fill, -- : NATURAL := 0;
- g_rx_timeout_w => g_rx_timeout_w, -- : NATURAL := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
-- Monitoring
- g_mon_select => g_mon_select, -- : NATURAL := 0;
- g_mon_nof_words => g_mon_nof_words, -- : NATURAL := 1024;
- g_mon_use_sync => g_mon_use_sync, -- : BOOLEAN := TRUE;
+ g_mon_select => g_mon_select,
+ g_mon_nof_words => g_mon_nof_words,
+ g_mon_use_sync => g_mon_use_sync,
-- UTH
- g_uth_len_max => g_uth_len_max, -- : NATURAL := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
- g_uth_typ_ofs => g_uth_typ_ofs -- : NATURAL := 256 -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
)
PORT MAP (
chip_id => chip_id,