diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index 343b11f03712661b8ad04fcdbc5c9c78bca826df..29b4559fc98488a16a2c25c9fc1ad5c3178fa4d1 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -27,11 +27,33 @@ synth_files =
src/vhdl/unb1_board_wdi_reg.vhd
src/vhdl/unb1_board_control.vhd
- $UNB/Firmware/designs/unb_common/src/vhdl/unb_mesh_reorder_tx.vhd
- $UNB/Firmware/designs/unb_common/src/vhdl/unb_mesh_reorder_rx.vhd
- $UNB/Firmware/designs/unb_common/src/vhdl/unb_mesh_reorder_bidir.vhd
- $UNB/Firmware/designs/unb_common/src/vhdl/unb_mesh_io.vhd
+ src/vhdl/unb1_board_front_io.vhd
+
+ src/vhdl/unb1_board_mesh_io.vhd
+ src/vhdl/unb1_board_mesh_reorder_tx.vhd
+ src/vhdl/unb1_board_mesh_reorder_rx.vhd
+ src/vhdl/unb1_board_mesh_reorder_bidir.vhd
+ src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
+
+ src/vhdl/unb1_board_back_io.vhd
+ src/vhdl/unb1_board_back_select.vhd
+ src/vhdl/unb1_board_back_reorder.vhd
+ src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
+
+ src/vhdl/unb1_board_terminals_mesh.vhd
+ src/vhdl/unb1_board_terminals_back.vhd
test_bench_files =
- $UNB/Firmware/designs/unb_common/tb/vhdl/unb_mesh_model_sosi.vhd
- $UNB/Firmware/designs/unb_common/tb/vhdl/unb_mesh_model_siso.vhd
+ tb/vhdl/tb_unb1_board_pkg.vhd
+
+ tb/vhdl/tb_mms_unb1_board_sens.vhd
+ tb/vhdl/tb_unb1_board_clk200_pll.vhd
+ tb/vhdl/tb_unb1_board_node_ctrl.vhd
+
+ tb/vhdl/unb1_board_mesh_model_sosi.vhd
+ tb/vhdl/unb1_board_mesh_model_siso.vhd
+ tb/vhdl/unb1_board_mesh_model_sl.vhd
+ tb/vhdl/unb1_board_back_model_sosi.vhd
+ tb/vhdl/unb1_board_back_model_sl.vhd
+
+ tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..88a30c35c09518cbccbc6d16183e980fec49fdce
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
@@ -0,0 +1,78 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb_common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE unb_common_lib.unb_common_pkg.ALL;
+
+
+ENTITY unb_back_io IS
+ GENERIC (
+ g_bus_w : NATURAL := 4
+ );
+ PORT (
+ tx_serial_2arr : IN t_unb_back_sl_2arr := (OTHERS=>(OTHERS=>'0'));
+ rx_serial_2arr : OUT t_unb_back_sl_2arr;
+
+ -- Serial I/O
+ -- . hard IP transceivers busses
+ BN_BI_0_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
+ BN_BI_0_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ BN_BI_1_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
+ BN_BI_1_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ BN_BI_2_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
+ BN_BI_2_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ -- . soft IP transceivers bus (typically not used on UniBoard)
+ BN_BI_3_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
+ BN_BI_3_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0')
+ );
+END unb_back_io;
+
+
+ARCHITECTURE str OF unb_back_io IS
+BEGIN
+
+ -- Map the serial streams to the back
+ wires : FOR I IN 0 TO g_bus_w-1 GENERATE
+ BN_BI_0_TX(I) <= tx_serial_2arr(0)(I);
+ BN_BI_1_TX(I) <= tx_serial_2arr(1)(I);
+ BN_BI_2_TX(I) <= tx_serial_2arr(2)(I);
+ BN_BI_3_TX(I) <= tx_serial_2arr(3)(I);
+
+ rx_serial_2arr(0)(I) <= BN_BI_0_RX(I);
+ rx_serial_2arr(1)(I) <= BN_BI_1_RX(I);
+ rx_serial_2arr(2)(I) <= BN_BI_2_RX(I);
+ rx_serial_2arr(3)(I) <= BN_BI_3_RX(I);
+ END GENERATE;
+
+END;
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5337bb0edb18d37519ff50b31f4c6cfd5ddf17f0
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
@@ -0,0 +1,169 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Map usr bus to phy bus and compensate for the backplane PCB reordering.
+-- Description:
+-- The backplane has 4 UniBoards and each board can connect to 3 other
+-- boards. Therefore at the phy side busses 2:0 are used to connect to the
+-- other 3 UniBoards and bus 3 is not used. At the usr side the usr bus
+-- index indicates the tx destination Uniboard and the rx source UniBoard.
+-- The usr bus index can be 3:0, so including this UniBoard itself that is
+-- indicated by usr bus index bck_id. The other 3 usr busses each connect to
+-- the corresponding Uniboard.
+-- The unb_back_reorder has to map the usr index 3:0 (excluding its own index
+-- bck_id) on to the phy index 2:0. The logical mapping is:
+--
+-- UniBoard bck_id=3 connects to UniBoards 2,1,0 via phy busses 2,1,0
+-- 2 3,1,0 2,1,0
+-- 1 3,2,0 2,1,0
+-- 0 3,2,1 2,1,0
+--
+-- However the Apertif beamformer backplane uses a different phy bus mapping
+-- to ease the PCB routing. The Apertif beamformer backplane mapping is:
+--
+-- UniBoard bck_id=3 connects to UniBoards 2,1,0 via phy busses 2,1,0
+-- 2 3,1,0 1,0,2
+-- 1 3,2,0 0,1,2
+-- 0 3,2,1 0,2,1
+--
+-- The mapping is the same for all BN on the UniBoard. The unb_back_reorder
+-- maps for the Apertif beamformer backplane with 4 UniBoards.
+-- Remark:
+-- . See unb_back_model_sl.vhd for the Apertif backplane model
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+
+
+ENTITY unb_back_reorder IS
+ PORT (
+ bck_id : IN STD_LOGIC_VECTOR(c_unb_nof_uniboard_w-1 DOWNTO 0);
+ clk : IN STD_LOGIC;
+
+ -- usr side interface
+ tx_usr_sosi_2arr : IN t_unb_back_sosi_2arr;
+ tx_usr_siso_2arr : OUT t_unb_back_siso_2arr;
+
+ rx_usr_sosi_2arr : OUT t_unb_back_sosi_2arr;
+ rx_usr_siso_2arr : IN t_unb_back_siso_2arr;
+
+ -- phy side interface
+ tx_phy_sosi_2arr : OUT t_unb_back_sosi_2arr;
+ tx_phy_siso_2arr : IN t_unb_back_siso_2arr;
+
+ rx_phy_sosi_2arr : IN t_unb_back_sosi_2arr;
+ rx_phy_siso_2arr : OUT t_unb_back_siso_2arr
+ );
+END unb_back_reorder;
+
+
+ARCHITECTURE rtl OF unb_back_reorder IS
+
+BEGIN
+
+ p_comb : PROCESS(bck_id, tx_usr_sosi_2arr, rx_phy_sosi_2arr, rx_usr_siso_2arr, tx_phy_siso_2arr)
+ BEGIN
+ -- Default set all IO to not used:
+ -- . usr bus with index bck_id of this UniBoard remains not used
+ -- . phy bus 3 remains not used
+ tx_phy_sosi_2arr <= (OTHERS=>(OTHERS=>c_dp_sosi_x));
+ tx_usr_siso_2arr <= (OTHERS=>(OTHERS=>c_dp_siso_x));
+
+ rx_usr_sosi_2arr <= (OTHERS=>(OTHERS=>c_dp_sosi_x));
+ rx_phy_siso_2arr <= (OTHERS=>(OTHERS=>c_dp_siso_x));
+
+ -- Map the usr busses for the other UniBoards to the phy busses 2:0
+ CASE TO_UINT(bck_id) IS
+ WHEN 0 =>
+ -- UniBoard 0 connects to UniBoards 3,2,1 via phy busses 0,2,1
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ WHEN 1 =>
+ -- UniBoard 1 connects to UniBoards 3,2,0 via phy busses 0,1,2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1); -- from unb 2
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ WHEN 2 =>
+ -- UniBoard 2 connects to UniBoards 3,1,0 via phy busses 1,0,2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0); -- from unb 1
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1); -- from unb 3
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
+ WHEN 3 =>
+ -- UniBoard 3 connects to UniBoards 2,1,0 via phy busses 2,1,0
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0); -- from unb 0
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+ WHEN OTHERS => NULL;
+ END CASE;
+ END PROCESS;
+
+END rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a4e9268415367352e2d8c079d16d1ae907342bb6
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
@@ -0,0 +1,90 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Loopback the bus selected by bck_id and pass on the other busses.
+-- Description:
+-- The tx_*_2arr have index [destination UniBoards][lanes].
+-- The rx_*_2arr have index [source UniBoards][lanes].
+-- The bus with destination = source = bck_id has to remain on this UniBoard
+-- and is therefore directly looped back between tx_usr and rx_usr. The other
+-- busses are passed on from tx_usr to tx_phy and from rx_phy to rx_usr.
+-- Remark:
+-- . The tx sosi and rx siso outputs of the bus that is not used at the phy
+-- side, due to the loopback, are forced to 'X'. This is not strictly
+-- necessary but avoids unintentional usage and eases recognition in the
+-- simulation Wave Window.
+-- . The tx_siso adn rx_sosi inputs of the bus that is not used at the phy side
+-- are ignored.
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+
+ENTITY unb_back_select IS
+ PORT (
+ bck_id : IN STD_LOGIC_VECTOR(c_unb_nof_uniboard_w-1 DOWNTO 0);
+ clk : IN STD_LOGIC;
+
+ -- usr side interface
+ tx_usr_sosi_2arr : IN t_unb_back_sosi_2arr;
+ tx_usr_siso_2arr : OUT t_unb_back_siso_2arr;
+
+ rx_usr_sosi_2arr : OUT t_unb_back_sosi_2arr;
+ rx_usr_siso_2arr : IN t_unb_back_siso_2arr;
+
+ -- phy side interface
+ tx_phy_sosi_2arr : OUT t_unb_back_sosi_2arr;
+ tx_phy_siso_2arr : IN t_unb_back_siso_2arr;
+
+ rx_phy_sosi_2arr : IN t_unb_back_sosi_2arr;
+ rx_phy_siso_2arr : OUT t_unb_back_siso_2arr
+ );
+END unb_back_select;
+
+
+ARCHITECTURE rtl OF unb_back_select IS
+
+BEGIN
+
+ p_sel: PROCESS(tx_usr_sosi_2arr, rx_usr_siso_2arr, tx_phy_siso_2arr, rx_phy_sosi_2arr, bck_id)
+ BEGIN
+ -- Default pass on all busses between usr and phy...
+ tx_phy_sosi_2arr <= tx_usr_sosi_2arr;
+ tx_usr_siso_2arr <= tx_phy_siso_2arr;
+ rx_usr_sosi_2arr <= rx_phy_sosi_2arr;
+ rx_phy_siso_2arr <= rx_usr_siso_2arr;
+
+ -- ...except the user TX bus that matches the board ID. Loop it back as user RX:
+
+ -- . Loop back this bus from user TX to user RX
+ rx_usr_sosi_2arr(TO_UINT(bck_id)) <= tx_usr_sosi_2arr(TO_UINT(bck_id));
+ tx_usr_siso_2arr(TO_UINT(bck_id)) <= rx_usr_siso_2arr(TO_UINT(bck_id));
+
+ -- . Force not using the phy side of this bus
+ tx_phy_sosi_2arr(TO_UINT(bck_id)) <= (OTHERS=>c_dp_sosi_x);
+ rx_phy_siso_2arr(TO_UINT(bck_id)) <= (OTHERS=>c_dp_siso_x);
+ END PROCESS;
+
+END rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..eeceb6ca3420a3828083a706b2f1ff0ad7e786b0
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
@@ -0,0 +1,137 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Instantiate uthernet TX and/or RX terminals for UniBoard back
+-- Description:
+-- Remark: This file is identical to unb_mesh_terminals.vhd except for the
+-- SOSI entity I/O types and the monitor outputs.
+
+LIBRARY IEEE, common_lib, dp_lib, uth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.dp_packet_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+USE uth_lib.uth_pkg.ALL;
+
+ENTITY unb_back_terminals IS
+ GENERIC (
+ -- User
+ g_usr_nof_streams : NATURAL := 4; -- number of user streams per bus
+ g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_data_w : NATURAL := 32;
+ g_usr_frame_len : NATURAL := 20;
+ -- DP/UTH packet
+ g_packet_data_w : NATURAL := 32; -- packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ -- Phy
+ g_phy_nof_serial : NATURAL := 4; -- up to 4 serial lanes per bus
+ -- Tx
+ g_use_tx : BOOLEAN := TRUE;
+ g_tx_input_use_fifo : BOOLEAN := TRUE; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_fill : NATURAL := 0;
+ -- Rx
+ g_use_rx : BOOLEAN := TRUE;
+ g_rx_output_use_fifo : BOOLEAN := TRUE; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_fill : NATURAL := 0;
+ g_rx_timeout_w : NATURAL := 0 -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ );
+ PORT (
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- User
+ tx_dp_sosi_2arr : IN t_unb_back_sosi_2arr;
+ tx_dp_siso_2arr : OUT t_unb_back_siso_2arr;
+
+ rx_dp_sosi_2arr : OUT t_unb_back_sosi_2arr;
+ rx_dp_siso_2arr : IN t_unb_back_siso_2arr;
+
+ -- Phy
+ tx_uth_sosi_2arr : OUT t_unb_back_sosi_2arr;
+ tx_uth_siso_2arr : IN t_unb_back_siso_2arr;
+
+ rx_uth_sosi_2arr : IN t_unb_back_sosi_2arr;
+ rx_uth_siso_2arr : OUT t_unb_back_siso_2arr
+ );
+END unb_back_terminals;
+
+
+ARCHITECTURE str OF unb_back_terminals IS
+
+ CONSTANT c_tx_mux_mode : NATURAL := 1; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
+ CONSTANT c_rx_mux_mode : NATURAL := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
+
+BEGIN
+
+ gen_bus : FOR I IN 0 TO c_unb_tr_back.nof_bus-1 GENERATE
+ u_uth_terminal_bidir : ENTITY uth_lib.uth_terminal_bidir
+ GENERIC MAP (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => g_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_mux_mode => c_tx_mux_mode,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- usr side interface
+ tx_dp_sosi_arr => tx_dp_sosi_2arr(I),
+ tx_dp_siso_arr => tx_dp_siso_2arr(I),
+
+ rx_dp_sosi_arr => rx_dp_sosi_2arr(I),
+ rx_dp_siso_arr => rx_dp_siso_2arr(I),
+
+ -- phy side interface
+ tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+ tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+
+ rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+ rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+
+ -- monitoring interface
+ rx_mon_pkt_sosi_arr => OPEN,
+ rx_mon_dist_sosi_arr => OPEN
+ );
+ END GENERATE;
+
+END str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..518ec38c548da1a7d71c2c4e73046a1605a0a82c
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
@@ -0,0 +1,131 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb_common_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE unb_common_lib.unb_common_pkg.ALL;
+
+
+ENTITY unb_front_io IS
+ GENERIC (
+ g_nof_xaui : NATURAL
+ );
+ PORT (
+ xaui_tx_arr : IN t_unb_xaui_sl_2arr(g_nof_xaui-1 DOWNTO 0);
+ xaui_rx_arr : OUT t_unb_xaui_sl_2arr(g_nof_xaui-1 DOWNTO 0);
+
+ mdio_mdc_arr : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+ mdio_mdat_in_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+ mdio_mdat_oen_arr : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+
+ -- Serial I/O
+ -- . hard IP transceivers busses
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ -- . soft IP transceivers bus (typically not used on UniBoard)
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0)
+ );
+END unb_front_io;
+
+ARCHITECTURE str OF unb_front_io IS
+
+ -- help signals so we can iterate through buses
+ SIGNAL si_fn_tx_arr : t_unb_xaui_sl_2arr(c_unb_tr_xaui.bus_w-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ SIGNAL si_fn_rx_arr : t_unb_xaui_sl_2arr(c_unb_tr_xaui.bus_w-1 DOWNTO 0);
+
+BEGIN
+
+ -- XAUI buses
+ SI_FN_0_TX <= si_fn_tx_arr(0);
+ SI_FN_1_TX <= si_fn_tx_arr(1);
+ SI_FN_2_TX <= si_fn_tx_arr(2);
+ SI_FN_3_TX <= si_fn_tx_arr(3);
+
+ si_fn_rx_arr(0) <= SI_FN_0_RX;
+ si_fn_rx_arr(1) <= SI_FN_1_RX;
+ si_fn_rx_arr(2) <= SI_FN_2_RX;
+ si_fn_rx_arr(3) <= SI_FN_3_RX;
+
+ wires : FOR i IN 0 TO g_nof_xaui-1 GENERATE
+ si_fn_tx_arr(i) <= xaui_tx_arr(i);
+ xaui_rx_arr(i) <= si_fn_rx_arr(i);
+ END GENERATE;
+
+ -- MDIO buffers
+ gen_iobuf_0 : IF g_nof_xaui>0 GENERATE
+ u_iobuf_0 : ENTITY common_lib.common_inout
+ PORT MAP (
+ dat_inout => SI_FN_0_CNTRL(c_unb_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(0),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(0)
+ );
+
+ SI_FN_0_CNTRL(c_unb_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(0);
+ END GENERATE;
+
+ gen_iobuf_1 : IF g_nof_xaui>1 GENERATE
+ u_iobuf_1 : ENTITY common_lib.common_inout
+ PORT MAP (
+ dat_inout => SI_FN_1_CNTRL(c_unb_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(1),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(1)
+ );
+
+ SI_FN_1_CNTRL(c_unb_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(1);
+ END GENERATE;
+
+ gen_iobuf_2 : IF g_nof_xaui>2 GENERATE
+ u_iobuf_2 : ENTITY common_lib.common_inout
+ PORT MAP (
+ dat_inout => SI_FN_2_CNTRL(c_unb_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(2),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(2)
+ );
+
+ SI_FN_2_CNTRL(c_unb_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(2);
+ END GENERATE;
+
+ gen_iobuf_3 : IF g_nof_xaui>3 GENERATE
+ u_iobuf_3 : ENTITY common_lib.common_inout
+ PORT MAP (
+ dat_inout => SI_FN_3_CNTRL(c_unb_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(3),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(3)
+ );
+
+ SI_FN_3_CNTRL(c_unb_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(3);
+ END GENERATE;
+
+END;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..896961461126c4341fba05f3a0a34ea4109dddc5
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
@@ -0,0 +1,76 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb_common_pkg.ALL;
+
+
+ENTITY unb_mesh_io IS
+ GENERIC (
+ g_bus_w : NATURAL := 3 -- use 4 to include the CMU transceives at port (3) else use 3 to only use the HW transceivers on port (2:0)
+ );
+ PORT (
+ tx_serial_2arr : IN t_unb_mesh_sl_2arr := (OTHERS=>(OTHERS=>'0'));
+ rx_serial_2arr : OUT t_unb_mesh_sl_2arr;
+
+ -- Serial I/O
+ FN_BN_0_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
+ FN_BN_0_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_1_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
+ FN_BN_1_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_2_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
+ FN_BN_2_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_3_TX : OUT STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0);
+ FN_BN_3_RX : IN STD_LOGIC_VECTOR(g_bus_w-1 DOWNTO 0) := (OTHERS=>'0')
+ );
+END unb_mesh_io;
+
+
+ARCHITECTURE str OF unb_mesh_io IS
+BEGIN
+
+ -- Map the serial streams to the mesh
+ wires : FOR I IN 0 TO g_bus_w-1 GENERATE
+ FN_BN_0_TX(I) <= tx_serial_2arr(0)(I);
+ FN_BN_1_TX(I) <= tx_serial_2arr(1)(I);
+ FN_BN_2_TX(I) <= tx_serial_2arr(2)(I);
+ FN_BN_3_TX(I) <= tx_serial_2arr(3)(I);
+
+ rx_serial_2arr(0)(I) <= FN_BN_0_RX(I);
+ rx_serial_2arr(1)(I) <= FN_BN_1_RX(I);
+ rx_serial_2arr(2)(I) <= FN_BN_2_RX(I);
+ rx_serial_2arr(3)(I) <= FN_BN_3_RX(I);
+ END GENERATE;
+
+END;
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..946257f12ab8c96efab15adad9024f2827815625
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
@@ -0,0 +1,198 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Compensate for the mesh reorder between FN and BN on UniBoard
+-- Description:
+--
+-- 0) The unb_mesh_reorder_* reorders combinatorially to preserve the RL.
+-- 1) The unb_mesh_reorder_tx maps the usr bus index for each node chip_id on
+-- the phy bus, so:
+--
+-- usr phy phy usr phy phy
+-- FN bus bus mesh bus BN BN bus bus mesh bus FN
+-- 0 0 0 -----> 3 0 0 0 3 -----> 0 0
+-- 0 1 3 -----> 3 1 0 1 2 -----> 0 1
+-- 0 2 2 -----> 2 2 0 2 1 -----> 0 2
+-- 0 3 1 -----> 1 3 0 3 0 -----> 1 3
+--
+-- 1 0 0 -----> 2 0 1 0 3 -----> 3 0
+-- 1 1 1 -----> 2 1 1 1 2 -----> 1 1
+-- 1 2 3 -----> 3 2 1 2 1 -----> 1 2
+-- 1 3 2 -----> 3 3 1 3 0 -----> 0 3
+--
+-- 2 0 0 -----> 1 0 2 0 2 -----> 2 0
+-- 2 1 1 -----> 1 1 2 1 3 -----> 3 1
+-- 2 2 2 -----> 1 2 2 2 1 -----> 2 2
+-- 2 3 3 -----> 2 3 2 3 0 -----> 2 3
+--
+-- 3 0 1 -----> 0 0 3 0 1 -----> 1 0
+-- 3 1 0 -----> 0 1 3 1 3 -----> 2 1
+-- 3 2 2 -----> 0 2 3 2 2 -----> 3 2
+-- 3 3 3 -----> 0 3 3 3 0 -----> 3 3
+--
+-- 2) The unb_mesh_reorder_rx maps the phy bus index for each node chip_id on
+-- the usr bus, so:
+--
+-- phy usr phy phy usr phy
+-- FN bus bus mesh bus BN BN bus bus mesh bus FN
+-- 0 0 0 <----- 3 0 0 0 3 <----- 1 3
+-- 0 1 3 <----- 1 3 0 1 2 <----- 0 2
+-- 0 2 2 <----- 2 2 0 2 1 <----- 0 1
+-- 0 3 1 <----- 3 1 0 3 0 <----- 0 0
+--
+-- 1 0 0 <----- 2 0 1 0 3 <----- 0 3
+-- 1 1 1 <----- 2 1 1 1 2 <----- 1 2
+-- 1 2 3 <----- 3 3 1 2 1 <----- 1 1
+-- 1 3 2 <----- 3 2 1 3 0 <----- 3 0
+--
+-- 2 0 0 <----- 1 0 2 0 3 <----- 2 3
+-- 2 1 1 <----- 1 1 2 1 2 <----- 2 2
+-- 2 2 2 <----- 1 2 2 2 0 <----- 2 0
+-- 2 3 3 <----- 2 3 2 3 1 <----- 3 1
+--
+-- 3 0 1 <----- 0 1 3 0 3 <----- 3 3
+-- 3 1 0 <----- 0 0 3 1 0 <----- 1 0
+-- 3 2 2 <----- 0 2 3 2 2 <----- 3 2
+-- 3 3 3 <----- 0 3 3 3 1 <----- 2 1
+--
+-- 3) In summary input bus 0,1,2,3 maps on output bus:
+--
+-- For TX For RX
+-- FN0 0,3,2,1 0,3,2,1
+-- FN1 0,1,3,2 0,1,3,2
+-- FN2 0,1,2,3 0,1,2,3
+-- FN3 1,0,2,3 1,0,2,3
+-- BN0 3,2,1,0 3,2,1,0
+-- BN1 3,2,1,0 3,2,1,0
+-- BN2 2,3,1,0 3,2,0,1 -- ! different for Tx and Rx
+-- BN3 1,0,2,3 3,0,2,1 -- ! different for Tx and Rx
+--
+-- 4) The UniBoard mesh is modelled by unb_mesh_model. In summary the UniBoard
+-- mesh is wired as:
+--
+-- phy phy phy phy
+-- FN bus mesh bus BN BN bus mesh bus FN
+-- 0 0 ------ 3 0 0 0 ------ 1 3
+-- 0 1 ------ 1 3 0 1 ------ 0 2
+-- 0 2 ------ 2 2 0 2 ------ 0 1
+-- 0 3 ------ 3 1 0 3 ------ 0 0
+--
+-- 1 0 ------ 2 0 1 0 ------ 0 3
+-- 1 1 ------ 2 1 1 1 ------ 1 2
+-- 1 2 ------ 3 3 1 2 ------ 1 1
+-- 1 3 ------ 3 2 1 3 ------ 3 0
+--
+-- 2 0 ------ 1 0 2 0 ------ 2 3
+-- 2 1 ------ 1 1 2 1 ------ 2 2
+-- 2 2 ------ 1 2 2 2 ------ 2 0
+-- 2 3 ------ 2 3 2 3 ------ 3 1
+--
+-- 3 0 ------ 0 1 3 0 ------ 3 3
+-- 3 1 ------ 0 0 3 1 ------ 1 0
+-- 3 2 ------ 0 2 3 2 ------ 3 2
+-- 3 3 ------ 0 3 3 3 ------ 2 1
+--
+-- Remark:
+-- . The indexing of the t_unb_mesh_*_2arr is (node id 0,1,2,3)(tr lane 3,2,1,0)
+-- . Use fixed c_unb_tr.nof_bus=4, because the nodes connect always to 4 other
+-- nodes accross the UniBoard mesh.
+-- . Use fixed c_unb_tr.bus_w=4 transceivers per node-to-node bus, because the
+-- UniBoard mesh does have 4 transceiver lanes per bus. It is possible to
+-- use less then 4 transceivers per bus in the mesh. Typically use <= 3 via
+-- index 2,1,0 to only use the 12 full-featured transceivers (so without the
+-- 4 less-featured CMU ones).
+-- . Both the SOSI and SISO signals are supported, because the transceiver PHY
+-- (e.g. tr_nonbonded) does support SISO.
+-- . For the SOSI and SISO interfaces there is also a corresponding UniBoard
+-- mesh model (unb_mesh_model_sosi and unb_mesh_model_siso). Therefor there
+-- is no need for an unb_mesh_reorder_bidir at serial std_logic level.
+-- The serial std_logic level can be simulated, but that requires using the
+-- TR PHY module (e.g. tr_nonbonded) to convert between SOSI/SISO and serial.
+-- Hence for simulating the UniBoard mesh at serial TR PHY level there is
+-- the serial UniBoard mesh model unb_mesh_model_sl.
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+
+
+ENTITY unb_mesh_reorder_bidir IS
+ GENERIC (
+ g_node_type : t_e_unb_node := e_any; -- or e_fn, or e_bn
+ g_reorder : BOOLEAN := TRUE
+ );
+ PORT (
+ chip_id : IN STD_LOGIC_VECTOR(c_unb_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
+
+ -- Transmit clock domain --> output data to node across the mesh
+ tx_clk : IN STD_LOGIC;
+ tx_usr_sosi_2arr : IN t_unb_mesh_sosi_2arr; -- user side
+ tx_usr_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ tx_phy_sosi_2arr : OUT t_unb_mesh_sosi_2arr; -- phy side
+ tx_phy_siso_2arr : IN t_unb_mesh_siso_2arr := c_unb_mesh_siso_2arr_rst;
+
+ -- Receive clock domain --> input data from node across the mesh
+ rx_clk : IN STD_LOGIC;
+ rx_phy_sosi_2arr : IN t_unb_mesh_sosi_2arr; -- phy side
+ rx_phy_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ rx_usr_sosi_2arr : OUT t_unb_mesh_sosi_2arr; -- user side
+ rx_usr_siso_2arr : IN t_unb_mesh_siso_2arr := c_unb_mesh_siso_2arr_rst
+ );
+END unb_mesh_reorder_bidir;
+
+
+ARCHITECTURE str OF unb_mesh_reorder_bidir IS
+BEGIN
+
+ u_tx : ENTITY work.unb_mesh_reorder_tx
+ GENERIC MAP (
+ g_node_type => g_node_type,
+ g_reorder => g_reorder
+ )
+ PORT MAP (
+ chip_id => chip_id,
+ clk => tx_clk,
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ tx_phy_sosi_2arr => tx_phy_sosi_2arr,
+ rx_phy_siso_2arr => rx_phy_siso_2arr
+ );
+
+ u_rx : ENTITY work.unb_mesh_reorder_rx
+ GENERIC MAP (
+ g_node_type => g_node_type,
+ g_reorder => g_reorder
+ )
+ PORT MAP (
+ chip_id => chip_id,
+ clk => rx_clk,
+ rx_phy_sosi_2arr => rx_phy_sosi_2arr,
+ tx_phy_siso_2arr => tx_phy_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+ tx_usr_siso_2arr => tx_usr_siso_2arr
+ );
+
+END str;
+
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bea2c182d94f8acae30cbe8f5000b8a205859f4b
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
@@ -0,0 +1,138 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Compensate for the mesh reorder between FN and BN on UniBoard
+-- Description: See unb_mesh_reorder_bidir.vhd
+-- This unb_mesh_reorder_rx performs mesh reordering for user receive, so
+-- for the rx_usr_sosi and the tx_usr_siso. Note that these belong to
+-- different streams. The rx_usr_sosi carries the user Rx data input stream
+-- and the tx_usr_siso belongs to the user Tx data stream and carries the
+-- input flow control for the Tx data stream.
+-- Remark:
+-- . Indexing for *_2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+
+
+ENTITY unb_mesh_reorder_rx IS
+ GENERIC (
+ g_node_type : t_e_unb_node := e_any;
+ g_reorder : BOOLEAN := TRUE
+ );
+ PORT (
+ chip_id : IN STD_LOGIC_VECTOR(c_unb_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
+ clk : IN STD_LOGIC;
+ rx_phy_sosi_2arr : IN t_unb_mesh_sosi_2arr; -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+ tx_phy_siso_2arr : IN t_unb_mesh_siso_2arr := c_unb_mesh_siso_2arr_rst;
+ rx_usr_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ tx_usr_siso_2arr : OUT t_unb_mesh_siso_2arr
+ );
+END unb_mesh_reorder_rx;
+
+
+ARCHITECTURE rtl OF unb_mesh_reorder_rx IS
+
+ SIGNAL chip_id_i : STD_LOGIC_VECTOR(chip_id'RANGE);
+
+BEGIN
+
+ -- force chip_id(2) to '0' or '1' to reduce the case options in p_comb if the design will run only on a FN or only on a BN
+ chip_id_i <= func_unb_chip_id(chip_id, g_node_type);
+
+ p_comb : PROCESS(chip_id_i, rx_phy_sosi_2arr, tx_phy_siso_2arr)
+ BEGIN
+ -- default connect to node 0,1,2,3 via port 0,1,2,3
+ rx_usr_sosi_2arr <= rx_phy_sosi_2arr;
+ tx_usr_siso_2arr <= tx_phy_siso_2arr;
+ IF g_reorder=TRUE THEN
+ -- make the reordering to compensate for the reordering of the UniBoard mesh
+ CASE TO_UINT(chip_id_i) IS
+ WHEN 0 => -- this is FN0, connect phy bus 0,1,2,3 to usr bus 0,3,2,1
+ -- sosi
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(3);
+ -- siso
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(3);
+ WHEN 1 => -- this is FN1, connect phy bus 0,1,2,3 to usr bus 0,1,3,2
+ -- sosi
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(3);
+ -- siso
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(2);
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(3);
+ WHEN 2 => -- this is FN2, connect phy bus 0,1,2,3 to usr bus 0,1,2,3
+ WHEN 3 => -- this is FN3, connect phy bus 0,1,2,3 to usr bus 1,0,2,3
+ -- sosi
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(1);
+ -- siso
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(1);
+ WHEN 4 |
+ 5 => -- this is BN0
+ -- or BN1, connect phy bus 0,1,2,3 to usr bus 3,2,1,0
+ -- sosi
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(3);
+ -- siso
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(2);
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(3);
+ WHEN 6 => -- this is BN2, connect phy bus 0,1,2,3 to usr bus 3,2,0,1
+ -- sosi
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(3);
+ -- siso
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(3);
+ WHEN 7 => -- this is BN3, connect phy bus 0,1,2,3 to usr bus 3,0,2,1
+ -- sosi
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(1);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(3);
+ -- siso
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(1);
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(3);
+ WHEN OTHERS => NULL;
+ END CASE;
+ END IF;
+ END PROCESS;
+
+END rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3a5cd19c4fd4a9387794931e1149f6067f321502
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
@@ -0,0 +1,156 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Compensate for the mesh reorder between FN and BN on UniBoard
+-- Description: See unb_mesh_reorder_bidir.vhd
+-- This unb_mesh_reorder_tx performs mesh reordering for user transmit, so
+-- for the tx_usr_sosi and the rx_usr_siso. Note that these belong to
+-- different streams. The tx_usr_sosi carries the user Tx data output stream
+-- and the rx_usr_siso belongs to the user Rx data stream and carries the
+-- output flow control for the Rx data stream.
+-- Remark:
+-- . Indexing for *_2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+
+
+ENTITY unb_mesh_reorder_tx IS
+ GENERIC (
+ g_node_type : t_e_unb_node := e_any;
+ g_reorder : BOOLEAN := TRUE
+ );
+ PORT (
+ chip_id : IN STD_LOGIC_VECTOR(c_unb_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
+ clk : IN STD_LOGIC;
+ tx_usr_sosi_2arr : IN t_unb_mesh_sosi_2arr; -- _2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
+ rx_usr_siso_2arr : IN t_unb_mesh_siso_2arr := c_unb_mesh_siso_2arr_rst;
+ tx_phy_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ rx_phy_siso_2arr : OUT t_unb_mesh_siso_2arr
+ );
+END unb_mesh_reorder_tx;
+
+
+ARCHITECTURE rtl OF unb_mesh_reorder_tx IS
+
+ SIGNAL chip_id_reg : STD_LOGIC_VECTOR(chip_id'RANGE);
+ SIGNAL chip_id_i : STD_LOGIC_VECTOR(chip_id'RANGE);
+
+BEGIN
+
+ -- Register the chip_id from FPGA pins to ease timing closure.
+ -- . Alternatively these registers may better be removed and pin input chip_id[] set as false path for timing closure
+ u_chip_id : ENTITY common_lib.common_pipeline
+ GENERIC MAP (
+ g_representation => "UNSIGNED",
+ g_pipeline => c_meta_delay_len,
+ g_reset_value => 0,
+ g_in_dat_w => chip_id'LENGTH,
+ g_out_dat_w => chip_id'LENGTH
+ )
+ PORT MAP (
+ rst => '0',
+ clk => clk,
+ in_dat => chip_id,
+ out_dat => chip_id_reg
+ );
+
+ -- force chip_id(2) to '0' or '1' to reduce the case options in p_comb if the design will run only on a FN or only on a BN
+ chip_id_i <= func_unb_chip_id(chip_id_reg, g_node_type);
+
+ p_comb : PROCESS(chip_id_i, tx_usr_sosi_2arr, rx_usr_siso_2arr)
+ BEGIN
+ -- default connect to node 0,1,2,3 via port 0,1,2,3
+ tx_phy_sosi_2arr <= tx_usr_sosi_2arr;
+ rx_phy_siso_2arr <= rx_usr_siso_2arr;
+ IF g_reorder=TRUE THEN
+ -- make the reordering to compensate for the reordering of the UniBoard mesh
+ CASE TO_UINT(chip_id_i) IS
+ WHEN 0 => -- this is FN0, connect usr bus 0,1,2,3 to phy bus 0,3,2,1
+ -- sosi
+ tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(1);
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2);
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3);
+ -- siso
+ rx_phy_siso_2arr(3) <= rx_usr_siso_2arr(1);
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
+ WHEN 1 => -- this is FN1, connect usr bus 0,1,2,3 to phy bus 0,1,3,2
+ -- sosi
+ tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(2);
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(3);
+ -- siso
+ rx_phy_siso_2arr(3) <= rx_usr_siso_2arr(2);
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(3);
+ WHEN 2 => -- this is FN2, connect usr bus 0,1,2,3 to phy bus 0,1,2,3
+ WHEN 3 => -- this is FN3, connect usr bus 0,1,2,3 to phy bus 1,0,2,3
+ -- sosi
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(0);
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1);
+ -- siso
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(0);
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
+ WHEN 4 |
+ 5 => -- this is BN0
+ -- or BN1, connect usr bus 0,1,2,3 to phy bus 3,2,1,0
+ -- sosi
+ tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(0);
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(1);
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2);
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3);
+ -- siso
+ rx_phy_siso_2arr(3) <= rx_usr_siso_2arr(0);
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(1);
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ WHEN 6 => -- this is BN2, connect usr bus 0,1,2,3 to phy bus 2,3,1,0
+ -- sosi
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0);
+ tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(1);
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2);
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3);
+ -- siso
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+ rx_phy_siso_2arr(3) <= rx_usr_siso_2arr(1);
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ WHEN 7 => -- this is BN3, connect usr bus 0,1,2,3 to phy bus 1,3,2,0
+ -- sosi
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(0);
+ tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(1);
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2);
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3);
+ -- siso
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(0);
+ rx_phy_siso_2arr(3) <= rx_usr_siso_2arr(1);
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ WHEN OTHERS => NULL;
+ END CASE;
+ END IF;
+ END PROCESS;
+
+END rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b94a59fb1f41d111f2aa42c5c5bf7d73fbf05109
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
@@ -0,0 +1,147 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Instantiate uthernet TX and/or RX terminals for UniBoard mesh
+-- Description:
+-- Remark: This file is identical to unb_back_terminals.vhd except for the
+-- SOSI entity I/O types and the monitor outputs.
+
+LIBRARY IEEE, common_lib, dp_lib, uth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.dp_packet_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+USE uth_lib.uth_pkg.ALL;
+
+ENTITY unb_mesh_terminals IS
+ GENERIC (
+ -- User
+ g_usr_nof_streams : NATURAL := 4; -- number of user streams per bus
+ g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_data_w : NATURAL := 32;
+ g_usr_frame_len : NATURAL := 20;
+ -- DP/UTH packet
+ g_packet_data_w : NATURAL := 32; -- packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+ -- Phy
+ g_phy_nof_serial : NATURAL := 4; -- up to 4 serial lanes per bus
+ -- Tx
+ g_use_tx : BOOLEAN := TRUE;
+ g_tx_input_use_fifo : BOOLEAN := TRUE; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_fill : NATURAL := 0;
+ -- Rx
+ g_use_rx : BOOLEAN := TRUE;
+ g_rx_output_use_fifo : BOOLEAN := TRUE; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_fill : NATURAL := 0;
+ g_rx_timeout_w : NATURAL := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- UTH
+ g_uth_len_max : NATURAL := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_typ_ofs : NATURAL := 256 -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ );
+ PORT (
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- User
+ tx_dp_sosi_2arr : IN t_unb_mesh_sosi_2arr;
+ tx_dp_siso_2arr : OUT t_unb_mesh_siso_2arr;
+
+ rx_dp_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ rx_dp_siso_2arr : IN t_unb_mesh_siso_2arr;
+
+ -- Phy
+ tx_uth_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ tx_uth_siso_2arr : IN t_unb_mesh_siso_2arr;
+
+ rx_uth_sosi_2arr : IN t_unb_mesh_sosi_2arr;
+ rx_uth_siso_2arr : OUT t_unb_mesh_siso_2arr;
+
+ -- Monitoring
+ rx_mon_pkt_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ rx_mon_dist_sosi_2arr : OUT t_unb_mesh_sosi_2arr
+ );
+END unb_mesh_terminals;
+
+
+ARCHITECTURE str OF unb_mesh_terminals IS
+
+ CONSTANT c_tx_mux_mode : NATURAL := 0; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
+ CONSTANT c_rx_mux_mode : NATURAL := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
+
+BEGIN
+
+ gen_uth_terminal_bidir : FOR I IN 0 TO c_unb_tr_mesh.nof_bus-1 GENERATE
+ u_uth_terminal_bidir : ENTITY uth_lib.uth_terminal_bidir
+ GENERIC MAP (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => g_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_mux_mode => c_tx_mux_mode,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- usr side interface
+ tx_dp_sosi_arr => tx_dp_sosi_2arr(I),
+ tx_dp_siso_arr => tx_dp_siso_2arr(I),
+
+ rx_dp_sosi_arr => rx_dp_sosi_2arr(I),
+ rx_dp_siso_arr => rx_dp_siso_2arr(I),
+
+ -- phy side interface
+ tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+ tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+
+ rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+ rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+
+ -- monitoring interface
+ rx_mon_pkt_sosi_arr => rx_mon_pkt_sosi_2arr(I)(g_phy_nof_serial-1 DOWNTO 0),
+ rx_mon_dist_sosi_arr => rx_mon_dist_sosi_2arr(I)
+ );
+ END GENERATE;
+
+END str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..57f445fcd91768090277d0bec313bb8c9a87ef24
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
@@ -0,0 +1,278 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Provide the user with an array of streaming interfaces that can
+-- be indexed using a global UniBoard number 3..0.
+-- Description:
+-- As one of the global UniBoard numbers will be itself, the streams with that
+-- particaular array index will be looped back (user TX to user RX).
+-- Remark:
+-- Main differences with unb_mesh_terminals:
+-- - UniBoard-indexing instead of node indexing;
+-- - One array index (mathcin board ID) is sourced by hosting node.
+-- - Always use the GX in both directions between the BN, so no need for
+-- g_use_tx and g_use_rx because they are both TRUE.
+
+LIBRARY IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.dp_packet_pkg.ALL;
+USE uth_lib.uth_pkg.ALL;
+USE tr_nonbonded_lib.tr_nonbonded_pkg.ALL;
+
+
+ENTITY unb_terminals_back IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0;
+ -- System
+ g_nof_bus : NATURAL := c_unb_nof_uniboard; -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ -- User
+ g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_data_w : NATURAL := 32;
+ g_usr_frame_len : NATURAL := 20;
+ g_usr_nof_streams : NATURAL := 4; -- number of user streams per bus
+ -- Phy
+ g_phy_nof_serial : NATURAL := 4; -- up to 4 serial lanes per bus
+ g_phy_gx_mbps : NATURAL := 5000;
+ g_phy_rx_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ -- Tx
+ g_tx_input_use_fifo : BOOLEAN := TRUE; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_fill : NATURAL := 0;
+ -- Rx
+ g_rx_output_use_fifo : BOOLEAN := FALSE; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_fill : NATURAL := 0;
+ g_rx_timeout_w : NATURAL := 0 -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ );
+ PORT (
+ bck_id : IN STD_LOGIC_VECTOR(c_unb_nof_uniboard_w-1 DOWNTO 0); -- [7:3]; only [1:0] required to index boards 3:0 in a subrack
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+ tr_clk : IN STD_LOGIC;
+ cal_clk : IN STD_LOGIC;
+
+ -- User interface
+ tx_usr_siso_2arr : OUT t_unb_back_siso_2arr;
+ tx_usr_sosi_2arr : IN t_unb_back_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ rx_usr_siso_2arr : IN t_unb_back_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy));
+ rx_usr_sosi_2arr : OUT t_unb_back_sosi_2arr;
+
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr : OUT t_unb_back_sl_2arr;
+ rx_serial_2arr : IN t_unb_back_sl_2arr := (OTHERS=>(OTHERS=>'0'));
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_tr_nonbonded_miso : OUT t_mem_miso;
+ reg_diagnostics_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_diagnostics_miso : OUT t_mem_miso
+
+ );
+END unb_terminals_back;
+
+
+ARCHITECTURE str OF unb_terminals_back IS
+
+ -- DP/UTH packet
+ CONSTANT c_packet_data_w : NATURAL := g_usr_data_w; -- = 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
+
+ CONSTANT c_nof_bus_logical : NATURAL := g_nof_bus; -- Indexing 3:0 so each UniBoard can be indexed by logical index
+ CONSTANT c_nof_bus_serial : NATURAL := g_nof_bus-1; -- Indexing 2:0, only the 'other' UniBoards can be indexed
+ CONSTANT c_nof_gx : NATURAL := c_nof_bus_serial*g_phy_nof_serial;
+
+ -- unb_back_select
+ SIGNAL tx_sel_siso_2arr : t_unb_back_siso_2arr;
+ SIGNAL tx_sel_sosi_2arr : t_unb_back_sosi_2arr;
+
+ SIGNAL rx_sel_siso_2arr : t_unb_back_siso_2arr;
+ SIGNAL rx_sel_sosi_2arr : t_unb_back_sosi_2arr;
+
+ -- unb_back_reorder
+ SIGNAL tx_term_siso_2arr : t_unb_back_siso_2arr;
+ SIGNAL tx_term_sosi_2arr : t_unb_back_sosi_2arr;
+
+ SIGNAL rx_term_siso_2arr : t_unb_back_siso_2arr;
+ SIGNAL rx_term_sosi_2arr : t_unb_back_sosi_2arr;
+
+ -- unb_back_terminals
+ SIGNAL tx_phy_siso_2arr : t_unb_back_siso_2arr;
+ SIGNAL tx_phy_sosi_2arr : t_unb_back_sosi_2arr;
+ SIGNAL rx_phy_siso_2arr : t_unb_back_siso_2arr;
+ SIGNAL rx_phy_sosi_2arr : t_unb_back_sosi_2arr;
+
+ -- mms_tr_nonbonded
+ SIGNAL tx_phy_siso_arr : t_dp_siso_arr(c_nof_gx-1 DOWNTO 0);
+ SIGNAL tx_phy_sosi_arr : t_dp_sosi_arr(c_nof_gx-1 DOWNTO 0);
+ SIGNAL rx_phy_siso_arr : t_dp_siso_arr(c_nof_gx-1 DOWNTO 0);
+ SIGNAL rx_phy_sosi_arr : t_dp_sosi_arr(c_nof_gx-1 DOWNTO 0);
+
+ SIGNAL tx_serial_arr : STD_LOGIC_VECTOR(c_nof_gx-1 DOWNTO 0);
+ SIGNAL rx_serial_arr : STD_LOGIC_VECTOR(c_nof_gx-1 DOWNTO 0);
+
+BEGIN
+
+ u_back_select: ENTITY work.unb_back_select
+ PORT MAP (
+ bck_id => bck_id,
+ clk => dp_clk,
+
+ -- User side
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ tx_usr_siso_2arr => tx_usr_siso_2arr,
+
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+
+ -- Phy side
+ tx_phy_sosi_2arr => tx_sel_sosi_2arr,
+ tx_phy_siso_2arr => tx_sel_siso_2arr,
+
+ rx_phy_sosi_2arr => rx_sel_sosi_2arr,
+ rx_phy_siso_2arr => rx_sel_siso_2arr
+ );
+
+ u_back_reorder : ENTITY work.unb_back_reorder
+ PORT MAP (
+ bck_id => bck_id,
+ clk => dp_clk,
+
+ -- User side
+ tx_usr_sosi_2arr => tx_sel_sosi_2arr,
+ tx_usr_siso_2arr => tx_sel_siso_2arr,
+
+ rx_usr_sosi_2arr => rx_sel_sosi_2arr,
+ rx_usr_siso_2arr => rx_sel_siso_2arr,
+
+ -- Phy side
+ tx_phy_sosi_2arr => tx_term_sosi_2arr,
+ tx_phy_siso_2arr => tx_term_siso_2arr,
+
+ rx_phy_sosi_2arr => rx_term_sosi_2arr,
+ rx_phy_siso_2arr => rx_term_siso_2arr
+ );
+
+ u_back_terminals : ENTITY work.unb_back_terminals
+ GENERIC MAP (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => c_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ -- Rx
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_timeout_w => g_rx_timeout_w
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- User
+ tx_dp_sosi_2arr => tx_term_sosi_2arr,
+ tx_dp_siso_2arr => tx_term_siso_2arr,
+
+ rx_dp_sosi_2arr => rx_term_sosi_2arr,
+ rx_dp_siso_2arr => rx_term_siso_2arr,
+
+ -- Phy
+ tx_uth_sosi_2arr => tx_phy_sosi_2arr,
+ tx_uth_siso_2arr => tx_phy_siso_2arr,
+
+ rx_uth_sosi_2arr => rx_phy_sosi_2arr,
+ rx_uth_siso_2arr => rx_phy_siso_2arr
+ );
+
+ ------------------------------------------------------------------------------
+ -- GX serial interface level (g_sim_level)
+ ------------------------------------------------------------------------------
+
+ -- Map 1-dim array on 2-dim array
+ gen_bus : FOR i IN c_nof_bus_serial-1 DOWNTO 0 GENERATE
+ gen_lane : FOR j IN g_phy_nof_serial-1 DOWNTO 0 GENERATE
+ -- SOSI
+ tx_phy_sosi_arr(i*g_phy_nof_serial + j) <= tx_phy_sosi_2arr(i)(j);
+ tx_phy_siso_2arr(i)(j) <= tx_phy_siso_arr(i*g_phy_nof_serial + j);
+
+ rx_phy_sosi_2arr(i)(j) <= rx_phy_sosi_arr(i*g_phy_nof_serial + j);
+ rx_phy_siso_arr(i*g_phy_nof_serial + j) <= rx_phy_siso_2arr(i)(j);
+
+ -- Serial
+ tx_serial_2arr(i)(j) <= tx_serial_arr(i*g_phy_nof_serial + j);
+ rx_serial_arr(i*g_phy_nof_serial + j) <= rx_serial_2arr(i)(j);
+ END GENERATE;
+ END GENERATE;
+
+ u_tr_nonbonded : ENTITY tr_nonbonded_lib.mms_tr_nonbonded
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_gx => c_nof_gx,
+ g_mbps => g_phy_gx_mbps,
+ g_tx => TRUE,
+ g_rx => TRUE,
+ g_rx_fifo_depth => g_phy_rx_fifo_size
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ tr_clk => tr_clk,
+ cal_rec_clk => cal_clk,
+
+ --Serial data I/O
+ tx_dataout => tx_serial_arr,
+ rx_datain => rx_serial_arr,
+
+ --Streaming I/O
+ snk_out_arr => tx_phy_siso_arr,
+ snk_in_arr => tx_phy_sosi_arr,
+
+ src_in_arr => rx_phy_siso_arr,
+ src_out_arr => rx_phy_sosi_arr,
+
+ tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
+ tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
+
+ diagnostics_mm_mosi => reg_diagnostics_mosi,
+ diagnostics_mm_miso => reg_diagnostics_miso
+ );
+
+END str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0bca78d269a534c7d46dbec47a6117afbd3eeb91
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -0,0 +1,415 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Provide streaming access to and from the nodes on the other side
+-- of the UniBoard mesh.
+-- Description:
+-- Data flow:
+-- * g_use_tx=TRUE
+-- tx_usr_sosi_2arr--> uth_terminal_tx
+-- tx_term_sosi_2arr--> unb_mesh_reorder_tx
+-- tx_phy_sosi_2arr--> map(I)(J) to (I*g_phy_nof_serial + J)
+-- tx_phy_sosi_arr--> mms_tr_nonbonded
+-- tx_serial_arr--> map(I*g_phy_nof_serial + J) to (I)(J)
+-- -->tx_serial_2arr
+-- * g_use_rx=TRUE
+-- rx_serial_2arr--> map(I)(J) to (I*g_phy_nof_serial + J)
+-- rx_serial_arr--> mms_tr_nonbonded
+-- rx_phy_sosi_arr--> map(I*g_phy_nof_serial + J) to (I)(J)
+-- rx_phy_sosi_2arr--> unb_mesh_reorder_rx
+-- rx_term_sosi_2arr--> uth_terminal_rx
+-- -->rx_usr_sosi_2arr
+--
+-- Remark:
+-- . The number of user input streams is defined by the width of the mesh bus,
+-- so g_usr_nof_streams = c_unb_tr.bus_w = 4 to be able to use
+-- t_unb_mesh_sosi_2arr.
+-- . The mesh reorder logic is always instantiated, but when g_phy_ena_reorder
+-- = FALSE then no reodering is done. In simulation the g_phy_ena_reorder
+-- must match the g_reorder setting for unb_mesh_model_*.vhd. On hardware
+-- use the default g_phy_ena_reorder = TRUE.
+
+
+LIBRARY IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.dp_packet_pkg.ALL;
+USE uth_lib.uth_pkg.ALL;
+USE tr_nonbonded_lib.tr_nonbonded_pkg.ALL;
+
+
+ENTITY unb_terminals_mesh IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0;
+ -- System
+ g_node_type : t_e_unb_node := e_any; -- or e_fn, or e_bn
+ g_nof_bus : NATURAL := 4; -- one bus to each of the 4 nodes on the other side of the mesh
+ -- User
+ g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ g_usr_data_w : NATURAL := 32; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+ g_usr_frame_len : NATURAL := 20;
+ g_usr_nof_streams : NATURAL := 4; -- number of user streams per bus
+ -- Phy
+ g_phy_nof_serial : NATURAL := 3; -- up to 4 serial lanes per bus
+ g_phy_gx_mbps : NATURAL := 5000;
+ g_phy_rx_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+ g_phy_ena_reorder : BOOLEAN := TRUE;
+ -- Tx
+ g_use_tx : BOOLEAN := TRUE;
+ g_tx_input_use_fifo : BOOLEAN := TRUE; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ g_tx_input_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+ g_tx_input_fifo_fill : NATURAL := 0;
+ -- Rx
+ g_use_rx : BOOLEAN := TRUE;
+ g_rx_output_use_fifo : BOOLEAN := TRUE; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+ g_rx_output_fifo_fill : NATURAL := 0;
+ g_rx_timeout_w : NATURAL := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+ -- Monitoring
+ g_mon_select : NATURAL := 0; -- 0 = no SOSI data buffers monitor via MM
+ -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
+ -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
+ -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
+ -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
+ -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
+ -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
+ g_mon_nof_words : NATURAL := 1024;
+ g_mon_use_sync : BOOLEAN := TRUE;
+ -- UTH
+ g_uth_len_max : NATURAL := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ g_uth_typ_ofs : NATURAL := 256 -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+ );
+ PORT (
+ chip_id : IN STD_LOGIC_VECTOR(c_unb_aux.chip_id_w-1 DOWNTO 0) := (OTHERS=>'0'); -- [2:0]
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+ dp_sync : IN STD_LOGIC := '0';
+ tr_clk : IN STD_LOGIC;
+ cal_clk : IN STD_LOGIC;
+
+ -- User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ tx_usr_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst)); -- Tx
+ rx_usr_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy));
+ rx_usr_sosi_2arr : OUT t_unb_mesh_sosi_2arr; -- Rx
+
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr : OUT t_unb_mesh_sl_2arr; -- Tx
+ rx_serial_2arr : IN t_unb_mesh_sl_2arr := (OTHERS=>(OTHERS=>'0')); -- Rx
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_tr_nonbonded_miso : OUT t_mem_miso;
+ reg_diagnostics_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_diagnostics_miso : OUT t_mem_miso;
+
+ -- . monitor data buffer
+ ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_diag_data_buf_miso : OUT t_mem_miso
+ );
+END unb_terminals_mesh;
+
+
+ARCHITECTURE str OF unb_terminals_mesh IS
+
+ -- DP/UTH packet
+ CONSTANT c_packet_data_w : NATURAL := 32; -- fixed 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w to avoid need for data packing
+
+ -- tr_nonbonded
+ CONSTANT c_phy_data_w : NATURAL := 32; -- fixed 32, tr_nonbonded supports 32b for generic g_phy_gx_mbps, must be >= c_packet_data_w to avoid loosing the higher bits
+ CONSTANT c_phy_nof_gx : NATURAL := g_nof_bus*g_phy_nof_serial;
+
+ -- g_mon_select
+ CONSTANT c_usr_nof_streams : NATURAL := g_nof_bus*g_usr_nof_streams;
+ CONSTANT c_mon_nof_streams : NATURAL := sel_n(g_mon_select, c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_usr_nof_streams,
+ c_phy_nof_gx,
+ c_phy_nof_gx);
+ CONSTANT c_mon_data_w : NATURAL := sel_n(g_mon_select, c_packet_data_w,
+ c_packet_data_w,
+ c_packet_data_w,
+ c_packet_data_w,
+ g_usr_data_w,
+ c_packet_data_w,
+ c_packet_data_w);
+
+ -- uth terminals
+ SIGNAL tx_term_siso_2arr : t_unb_mesh_siso_2arr;
+ SIGNAL tx_term_sosi_2arr : t_unb_mesh_sosi_2arr; -- Tx
+ SIGNAL rx_term_siso_2arr : t_unb_mesh_siso_2arr;
+ SIGNAL rx_term_sosi_2arr : t_unb_mesh_sosi_2arr; -- Rx
+
+ -- g_mon_select
+ SIGNAL mon_sosi_arr : t_dp_sosi_arr(c_mon_nof_streams-1 DOWNTO 0); -- selected sosi for the SOSI data monitor
+ SIGNAL mon_rx_term_pkt_sosi_2arr : t_unb_mesh_sosi_2arr;
+ SIGNAL mon_rx_term_dist_sosi_2arr : t_unb_mesh_sosi_2arr;
+
+ -- g_phy_ena_reorder
+ SIGNAL tx_phy_siso_2arr : t_unb_mesh_siso_2arr;
+ SIGNAL tx_phy_sosi_2arr : t_unb_mesh_sosi_2arr; -- Tx
+ SIGNAL rx_phy_siso_2arr : t_unb_mesh_siso_2arr;
+ SIGNAL rx_phy_sosi_2arr : t_unb_mesh_sosi_2arr; -- Rx
+
+ -- tr_nonbonded
+ SIGNAL tx_phy_siso_arr : t_dp_siso_arr(c_phy_nof_gx-1 DOWNTO 0);
+ SIGNAL tx_phy_sosi_arr : t_dp_sosi_arr(c_phy_nof_gx-1 DOWNTO 0); -- Tx
+ SIGNAL rx_phy_siso_arr : t_dp_siso_arr(c_phy_nof_gx-1 DOWNTO 0);
+ SIGNAL rx_phy_sosi_arr : t_dp_sosi_arr(c_phy_nof_gx-1 DOWNTO 0); -- Rx
+
+ SIGNAL tx_serial_arr : STD_LOGIC_VECTOR(c_phy_nof_gx-1 DOWNTO 0);
+ SIGNAL rx_serial_arr : STD_LOGIC_VECTOR(c_phy_nof_gx-1 DOWNTO 0);
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+ -- g_mon_select
+ ------------------------------------------------------------------------------
+
+ mon_rx_mesh : IF g_mon_select=1 GENERATE
+ gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
+ mon_sosi_arr(I*g_phy_nof_serial+J) <= rx_phy_sosi_2arr(I)(J);
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+ mon_rx_term_uth : IF g_mon_select=2 GENERATE
+ gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
+ mon_sosi_arr(I*g_phy_nof_serial+J) <= rx_term_sosi_2arr(I)(J);
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+ mon_rx_term_pkt : IF g_mon_select=3 GENERATE
+ gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
+ mon_sosi_arr(I*g_phy_nof_serial+J) <= mon_rx_term_pkt_sosi_2arr(I)(J);
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+ mon_rx_term_dist : IF g_mon_select=4 GENERATE
+ gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_j : FOR J IN 0 TO g_usr_nof_streams-1 GENERATE
+ mon_sosi_arr(I*g_usr_nof_streams+J) <= mon_rx_term_dist_sosi_2arr(I)(J);
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+ mon_tx_mesh : IF g_mon_select=5 GENERATE
+ gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
+ mon_sosi_arr(I*g_phy_nof_serial+J) <= tx_phy_sosi_2arr(I)(J);
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+ mon_tx_term_uth : IF g_mon_select=6 GENERATE
+ gen_i : FOR I IN 0 TO c_unb_tr.nof_bus-1 GENERATE
+ gen_j : FOR J IN 0 TO g_phy_nof_serial-1 GENERATE
+ mon_sosi_arr(I*g_phy_nof_serial+J) <= tx_term_sosi_2arr(I)(J);
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+
+ no_monitor : IF g_mon_select = 0 GENERATE
+ ram_diag_data_buf_miso <= c_mem_miso_rst;
+ END GENERATE;
+
+ gen_monitor : IF g_mon_select >= 1 GENERATE
+ u_data_buf : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_mon_nof_streams,
+ g_data_w => c_mon_data_w, -- stream data width must be <= c_word_w = 32b, the MM word width
+ g_buf_nof_data => g_mon_nof_words, -- nof words per data buffer
+ g_buf_use_sync => g_mon_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ )
+ PORT MAP (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ -- ST interface
+ in_sync => dp_sync, -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ in_sosi_arr => mon_sosi_arr
+ );
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- Terminals
+ ------------------------------------------------------------------------------
+
+ u_mesh_terminals : ENTITY work.unb_mesh_terminals
+ GENERIC MAP (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => c_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- User
+ tx_dp_sosi_2arr => tx_usr_sosi_2arr,
+ tx_dp_siso_2arr => tx_usr_siso_2arr,
+
+ rx_dp_sosi_2arr => rx_usr_sosi_2arr,
+ rx_dp_siso_2arr => rx_usr_siso_2arr,
+
+ -- Phy
+ tx_uth_sosi_2arr => tx_term_sosi_2arr,
+ tx_uth_siso_2arr => tx_term_siso_2arr,
+
+ rx_uth_sosi_2arr => rx_term_sosi_2arr,
+ rx_uth_siso_2arr => rx_term_siso_2arr,
+
+ -- Monitoring
+ rx_mon_pkt_sosi_2arr => mon_rx_term_pkt_sosi_2arr,
+ rx_mon_dist_sosi_2arr => mon_rx_term_dist_sosi_2arr
+ );
+
+ ------------------------------------------------------------------------------
+ -- Compensate for mesh reorder (g_phy_ena_reorder)
+ ------------------------------------------------------------------------------
+
+ u_tx : ENTITY work.unb_mesh_reorder_tx
+ GENERIC MAP (
+ g_node_type => g_node_type,
+ g_reorder => g_phy_ena_reorder
+ )
+ PORT MAP (
+ chip_id => chip_id,
+ clk => dp_clk,
+ tx_usr_sosi_2arr => tx_term_sosi_2arr, -- g_use_tx
+ rx_usr_siso_2arr => rx_term_siso_2arr, -- g_use_rx
+ tx_phy_sosi_2arr => tx_phy_sosi_2arr,
+ rx_phy_siso_2arr => rx_phy_siso_2arr
+ );
+
+ u_rx : ENTITY work.unb_mesh_reorder_rx
+ GENERIC MAP (
+ g_node_type => g_node_type,
+ g_reorder => g_phy_ena_reorder
+ )
+ PORT MAP (
+ chip_id => chip_id,
+ clk => dp_clk,
+ rx_phy_sosi_2arr => rx_phy_sosi_2arr,
+ tx_phy_siso_2arr => tx_phy_siso_2arr,
+ rx_usr_sosi_2arr => rx_term_sosi_2arr, -- g_use_rx
+ tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- GX serial interface level (g_sim_level)
+ ------------------------------------------------------------------------------
+
+ -- Map 1-dim array on 2-dim array
+ gen_bus : FOR I IN g_nof_bus-1 DOWNTO 0 GENERATE
+ gen_lane : FOR J IN g_phy_nof_serial-1 DOWNTO 0 GENERATE
+ -- SOSI
+ tx_phy_sosi_arr(I*g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
+ tx_phy_siso_2arr(I)(J) <= tx_phy_siso_arr(I*g_phy_nof_serial + J);
+
+ rx_phy_sosi_2arr(I)(J) <= rx_phy_sosi_arr(I*g_phy_nof_serial + J);
+ rx_phy_siso_arr(I*g_phy_nof_serial + J) <= rx_phy_siso_2arr(I)(J);
+
+ -- Serial
+ tx_serial_2arr(I)(J) <= tx_serial_arr(I*g_phy_nof_serial + J);
+ rx_serial_arr(I*g_phy_nof_serial + J) <= rx_serial_2arr(I)(J);
+ END GENERATE;
+ END GENERATE;
+
+ u_tr_nonbonded : ENTITY tr_nonbonded_lib.mms_tr_nonbonded
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_data_w => c_phy_data_w,
+ g_nof_gx => c_phy_nof_gx,
+ g_mbps => g_phy_gx_mbps,
+ g_tx => g_use_tx,
+ g_rx => g_use_rx,
+ g_rx_fifo_depth => g_phy_rx_fifo_size
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ tr_clk => tr_clk,
+ cal_rec_clk => cal_clk,
+
+ --Serial data I/O
+ tx_dataout => tx_serial_arr,
+ rx_datain => rx_serial_arr,
+
+ --Streaming I/O
+ snk_out_arr => tx_phy_siso_arr,
+ snk_in_arr => tx_phy_sosi_arr,
+
+ src_in_arr => rx_phy_siso_arr,
+ src_out_arr => rx_phy_sosi_arr,
+
+ tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
+ tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
+
+ diagnostics_mm_mosi => reg_diagnostics_mosi,
+ diagnostics_mm_miso => reg_diagnostics_miso
+ );
+
+END str;
+
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5b1d2a6795ae9165cd36830d417e87fc0b875b9a
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -0,0 +1,212 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for mms_unb_sens
+--
+-- Features:
+-- . Verify that the UniBoard sensors are read.
+--
+-- Usage:
+-- . > as 10
+-- . > run -all
+
+ENTITY tb_mms_unb_sens IS
+END tb_mms_unb_sens;
+
+LIBRARY IEEE, common_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+
+
+ARCHITECTURE tb OF tb_mms_unb_sens IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE; --FALSE;
+ CONSTANT c_repeat : NATURAL := 2;
+ CONSTANT c_clk_freq : NATURAL := 100*10**6;
+ CONSTANT c_clk_period : TIME := (10**9/c_clk_freq) * 1 ns;
+ CONSTANT c_rst_period : TIME := 4 * c_clk_period;
+
+ -- Model I2C sensor slaves as on the UniBoard
+ CONSTANT c_temp_high : NATURAL := 85;
+ CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
+ CONSTANT c_fpga_temp : INTEGER := 60;
+ CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW
+ CONSTANT c_eth_temp : INTEGER := 40;
+ CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L
+ CONSTANT c_hot_swap_R_sense : REAL := 0.01; -- = 10 mOhm on UniBoard
+
+ CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard --> hot swap = 5010 mAmpere (167)
+ CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard --> hot swap = 48000 mVolt (120)
+ CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
+
+ CONSTANT c_sens_nof_result : NATURAL := 4 + 1;
+ CONSTANT c_sens_expected : t_natural_arr(0 TO c_sens_nof_result-1) := (60, 40, 167, 120, 0); -- 4 bytes as read by c_SEQ in unb_sens_ctrl + sens_err
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL start : STD_LOGIC;
+
+ SIGNAL reg_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_miso : t_mem_miso;
+
+ SIGNAL sens_val : STD_LOGIC;
+ SIGNAL sens_dat : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+
+ SIGNAL scl_stretch : STD_LOGIC := 'Z';
+ SIGNAL scl : STD_LOGIC;
+ SIGNAL sda : STD_LOGIC;
+
+BEGIN
+
+ rst <= '0' AFTER 4*c_clk_period;
+ clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+
+ -- I2C bus
+ scl <= 'H'; -- model I2C pull up
+ sda <= 'H'; -- model I2C pull up, use '0' and '1' to verify sens_err
+
+ scl <= scl_stretch;
+
+ sens_clk_stretch : PROCESS (scl)
+ BEGIN
+ IF falling_edge(scl) THEN
+ scl_stretch <= '0', 'Z' AFTER 50 ns; -- < 10 ns to effectively disable stretching, >= 50 ns to enable it
+ END IF;
+ END PROCESS;
+
+ p_mm_reg_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE vI : NATURAL;
+ VARIABLE vJ : NATURAL;
+ BEGIN
+ start <= '0';
+ reg_mosi <= c_mem_mosi_rst;
+
+ proc_common_wait_until_low(clk, rst);
+ proc_common_wait_some_cycles(clk, 10);
+
+ FOR I IN 0 TO c_repeat-1 LOOP
+ -- start I2C access
+ start <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ start <= '0';
+
+ -- wait for I2C access to have finished
+ proc_common_wait_some_cycles(clk, sel_a_b(c_sim, 5000, 500000));
+
+ -- read I2C result data
+ FOR I IN 0 TO c_sens_nof_result-1 LOOP
+ proc_mem_mm_bus_rd(I, clk, reg_miso, reg_mosi); -- read sens_data
+ END LOOP;
+
+ proc_common_wait_some_cycles(clk, 1000);
+ END LOOP;
+
+ proc_common_wait_some_cycles(clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ sens_val <= reg_miso.rdval;
+ sens_dat <= reg_miso.rddata(c_byte_w-1 DOWNTO 0);
+
+ -- Verify sensor data
+ p_verify : PROCESS
+ BEGIN
+ WAIT UNTIL rising_edge(clk); -- Added this line to avoid warning: (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+
+ proc_common_wait_until_high(clk, sens_val);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(0) REPORT "Wrong FPGA temperature value" SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(1) REPORT "Wrong ETH temperature value" SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(2) REPORT "Wrong hot swap V sense value" SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(3) REPORT "Wrong hot swap V source value" SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(sens_dat)=c_sens_expected(4) REPORT "An I2C error occurred" SEVERITY ERROR;
+
+ END PROCESS;
+
+
+ -- I2C sensors master
+ u_mms_unb_sens : ENTITY work.mms_unb_sens
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
+
+ -- I2C slaves that are available for each FPGA
+ u_fpga_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_fpga_temp_address
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
+
+ -- I2C slaves that are available only via FPGA back node 3
+ u_eth_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_eth_temp_address
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
+
+ u_power : ENTITY i2c_lib.dev_ltc4260
+ GENERIC MAP (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ PORT MAP (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
+
+END tb;
+
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1c985b7a597b2f0663f65181672f598bc3ad832c
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
@@ -0,0 +1,167 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+-- Purpose: Simulate phase behaviour of PLL in normal mode
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_unb_clk200_pll IS
+END tb_unb_clk200_pll;
+
+
+ARCHITECTURE tb OF tb_unb_clk200_pll IS
+
+ CONSTANT c_ext_clk_period : TIME := 5 ns; -- 200 MHz
+ CONSTANT c_clk_vec_w : NATURAL := 6;
+ CONSTANT c_clk_div : NATURAL := 32;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL ext_rst : STD_LOGIC;
+
+ SIGNAL st_clk200_0 : STD_LOGIC;
+ SIGNAL st_rst200_0 : STD_LOGIC;
+
+ SIGNAL st_clk200p0 : STD_LOGIC;
+ SIGNAL st_rst200p0 : STD_LOGIC;
+
+ SIGNAL st_clk200_45 : STD_LOGIC;
+ SIGNAL st_rst200_45 : STD_LOGIC;
+
+ SIGNAL st_clk200p45 : STD_LOGIC;
+ SIGNAL st_rst200p45 : STD_LOGIC;
+
+ SIGNAL st_clk400 : STD_LOGIC;
+ SIGNAL st_rst400 : STD_LOGIC;
+
+ SIGNAL dp_clk200 : STD_LOGIC;
+ SIGNAL dp_rst200 : STD_LOGIC;
+ SIGNAL dp_clkp : STD_LOGIC;
+ SIGNAL dp_clkq : STD_LOGIC;
+
+ SIGNAL st_clk_vec : STD_LOGIC_VECTOR(c_clk_vec_w-1 DOWNTO 0); -- PLL c6-c1
+
+BEGIN
+
+ tb_end <= '0', '1' AFTER c_ext_clk_period*5000;
+
+ ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;
+ ext_rst <= '1', '0' AFTER c_ext_clk_period*7;
+
+ dut_0 : ENTITY work.unb_clk200_pll
+ GENERIC MAP (
+ g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "0",
+ g_clk200p_phase_shift => "0"
+ )
+ PORT MAP (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
+
+ dut_45 : ENTITY work.unb_clk200_pll
+ GENERIC MAP (
+ g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ PORT MAP (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => OPEN
+ );
+
+ dut_p6 : ENTITY work.unb_clk200_pll
+ GENERIC MAP (
+ g_sel => 1, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=1 for clk200_pll_p6.vhd
+ -- g_sel=2 for clk200_pll_pq.vhd
+ g_clk200_phase_shift => "0",
+ -- g_sel=2 for clk200_pll_p6.vhd
+ g_clk0_phase_shift => "0",
+ g_clk_vec_w => c_clk_vec_w,
+ g_clk1_phase_shift => "0",
+ g_clk2_phase_shift => "156",
+ g_clk3_phase_shift => "313",
+ g_clk4_phase_shift => "469",
+ g_clk5_phase_shift => "625",
+ g_clk6_phase_shift => "938",
+ g_clk1_divide_by => c_clk_div,
+ g_clk2_divide_by => c_clk_div,
+ g_clk3_divide_by => c_clk_div,
+ g_clk4_divide_by => c_clk_div,
+ g_clk5_divide_by => c_clk_div,
+ g_clk6_divide_by => c_clk_div
+ )
+ PORT MAP (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200,
+ -- . g_sel=2
+ st_clk_vec => st_clk_vec
+ );
+
+ dut_pq : ENTITY work.unb_clk200_pll
+ GENERIC MAP (
+ g_sel => 2, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=1 for clk200_pll_p6.vhd
+ -- g_sel=2 for clk200_pll_pq.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "0",
+ -- g_sel=1 for clk200_pll_pq.vhd
+ g_clkp_divide_by => c_clk_div,
+ g_clkq_divide_by => c_clk_div,
+ g_clkp_phase_shift => "0", -- = 0; -- = 000 for st_clkp relative to c0 = st_clk200
+ g_clkq_phase_shift => "1250" -- = 1250; -- = 090 for st_clkq relative to c0 = st_clk200
+ )
+ PORT MAP (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200,
+ st_clkp => dp_clkp,
+ st_clkq => dp_clkq
+ );
+
+END tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a6f128f6a221a49953a238c6312a11092a56ed9b
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -0,0 +1,401 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+-- Purpose:
+-- 1) Verify unb_mesh_reorder_bidir for SOSI using the unb_mesh_model_sosi
+-- 2) Verify unb_mesh_reorder_bidir for SISO using the unb_mesh_model_siso
+-- 3) Verify the serial unb_mesh_model_sl
+-- Usage:
+-- > do wave_unb_mesh_reorder_bidir.do
+-- > run -all
+-- 1) Self check SOSI should report no bn_rx_valid[] or fn_rx_valid[] error
+-- 2) Self check SISO should report no bn_tx_ready[] or fn_tx_ready[] error
+-- 3) Self check unb_mesh_model_sl operates at PHY level using the SOSI.valid
+-- as stimuli and the SOSI.valid result as reference and should report no
+-- error.
+-- . Manually observe that bn_rx_valid and fn_rx_valid show a series of pulses
+-- Description:
+-- . See unb_mesh_reorder_bidir.vhd
+-- . Use c_reorder=FALSE for a default FN to BN and BN to BN transpose without
+-- reordering on the PCB. Default use c_reorder=TRUE to also model the
+-- transceiver bus reorderings on UniBoard PCB.
+
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+USE work.tb_unb_common_pkg.ALL;
+
+
+ENTITY tb_unb_mesh_reorder_bidir IS
+END tb_unb_mesh_reorder_bidir;
+
+
+ARCHITECTURE tb OF tb_unb_mesh_reorder_bidir IS
+
+ CONSTANT c_reorder : BOOLEAN := TRUE;
+
+ CONSTANT c_chip_id_w : NATURAL := c_unb_aux.chip_id_w; -- = 3 to fit 8 fpgas in [2:0]
+ CONSTANT c_nof_node : NATURAL := c_unb_nof_node; -- = 4
+ CONSTANT c_nof_bus : NATURAL := c_unb_tr.nof_bus; -- = 4
+ CONSTANT c_bus_w : NATURAL := c_unb_tr.bus_w; -- = 4
+
+ CONSTANT c_repeat : NATURAL := 3;
+ CONSTANT c_clk_period : TIME := 10 ns;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '0';
+
+ ------------------------------------------------------------------------------
+ -- SL
+ ------------------------------------------------------------------------------
+ -- . PHY signals to mesh
+ SIGNAL fn_tx_phy_sl_3arr : t_unb_mesh_sl_3arr;
+ SIGNAL bn_tx_phy_sl_3arr : t_unb_mesh_sl_3arr;
+
+ -- . PHY signals from mesh
+ SIGNAL fn_rx_phy_sl_3arr : t_unb_mesh_sl_3arr;
+ SIGNAL fn_rx_phy_sl : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL fn_rx_phy_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL bn_rx_phy_sl_3arr : t_unb_mesh_sl_3arr;
+ SIGNAL bn_rx_phy_sl : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL bn_rx_phy_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+
+ ------------------------------------------------------------------------------
+ -- SOSI
+ ------------------------------------------------------------------------------
+ -- . Monitoring signals
+ SIGNAL fn_tx_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL bn_tx_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL fn_rx_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL bn_rx_valid : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+
+ -- . User domain driving stimuli signals
+ SIGNAL fn_tx_usr_sosi_3arr : t_unb_mesh_sosi_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_sosi_rst)));
+ SIGNAL bn_tx_usr_sosi_3arr : t_unb_mesh_sosi_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_sosi_rst)));
+
+ -- . PHY signals to mesh
+ SIGNAL fn_tx_phy_sosi_3arr : t_unb_mesh_sosi_3arr;
+ SIGNAL bn_tx_phy_sosi_3arr : t_unb_mesh_sosi_3arr;
+
+ -- . PHY signals from mesh
+ SIGNAL fn_rx_phy_sosi_3arr : t_unb_mesh_sosi_3arr;
+ SIGNAL bn_rx_phy_sosi_3arr : t_unb_mesh_sosi_3arr;
+
+ -- . User domain result signals
+ SIGNAL fn_rx_usr_sosi_3arr : t_unb_mesh_sosi_3arr;
+ SIGNAL bn_rx_usr_sosi_3arr : t_unb_mesh_sosi_3arr;
+
+ ------------------------------------------------------------------------------
+ -- SISO
+ ------------------------------------------------------------------------------
+ -- . Monitoring signals
+ SIGNAL fn_rx_ready : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL bn_rx_ready : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL fn_tx_ready : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+ SIGNAL bn_tx_ready : STD_LOGIC_VECTOR(c_nof_node*c_nof_bus*c_bus_w-1 DOWNTO 0);
+
+ -- . User domain result signals
+ SIGNAL fn_tx_usr_siso_3arr : t_unb_mesh_siso_3arr;
+ SIGNAL bn_tx_usr_siso_3arr : t_unb_mesh_siso_3arr;
+
+ -- . PHY signals from mesh
+ SIGNAL fn_tx_phy_siso_3arr : t_unb_mesh_siso_3arr;
+ SIGNAL bn_tx_phy_siso_3arr : t_unb_mesh_siso_3arr;
+
+ -- . PHY signals to mesh
+ SIGNAL fn_rx_phy_siso_3arr : t_unb_mesh_siso_3arr;
+ SIGNAL bn_rx_phy_siso_3arr : t_unb_mesh_siso_3arr;
+
+ -- . User domain driving stimuli signals
+ SIGNAL fn_rx_usr_siso_3arr : t_unb_mesh_siso_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_siso_rst)));
+ SIGNAL bn_rx_usr_siso_3arr : t_unb_mesh_siso_3arr := (OTHERS=>(OTHERS=>(OTHERS=>c_dp_siso_rst)));
+
+BEGIN
+
+ clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+
+ ------------------------------------------------------------------------------
+ -- Stimuli
+ ------------------------------------------------------------------------------
+
+ p_stimuli : PROCESS
+ BEGIN
+ proc_common_wait_some_cycles(clk, 100);
+ FOR R IN 0 TO c_repeat-1 LOOP
+ -- Sequentially set a '1' pulse on every sosi.valid and and every
+ -- siso.ready then check that these get accross the UniBoard mesh in the
+ -- correct order by comparing the output pattern with the (delayed)
+ -- input pattern.
+
+ -- FN
+ FOR I IN 0 TO c_nof_node-1 LOOP
+ FOR J IN 0 TO c_nof_bus-1 LOOP
+ FOR K IN 0 TO c_bus_w-1 LOOP
+ fn_tx_usr_sosi_3arr(I)(J)(K).valid <= '1';
+ fn_rx_usr_siso_3arr(I)(J)(K).ready <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ fn_tx_usr_sosi_3arr(I)(J)(K).valid <= '0';
+ fn_rx_usr_siso_3arr(I)(J)(K).ready <= '0';
+ END LOOP;
+ END LOOP;
+ END LOOP;
+
+ -- BN
+ FOR I IN 0 TO c_nof_node-1 LOOP
+ FOR J IN 0 TO c_nof_bus-1 LOOP
+ FOR K IN 0 TO c_bus_w-1 LOOP
+ bn_tx_usr_sosi_3arr(I)(J)(K).valid <= '1';
+ bn_rx_usr_siso_3arr(I)(J)(K).ready <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ bn_tx_usr_sosi_3arr(I)(J)(K).valid <= '0';
+ bn_rx_usr_siso_3arr(I)(J)(K).ready <= '0';
+ END LOOP;
+ END LOOP;
+ END LOOP;
+
+ END LOOP;
+
+ proc_common_wait_some_cycles(clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+
+ ------------------------------------------------------------------------------
+ -- Monitor and verify
+ ------------------------------------------------------------------------------
+
+ gen_node : FOR I IN 0 TO c_nof_node-1 GENERATE
+ gen_bus : FOR J IN 0 TO c_nof_bus-1 GENERATE
+ gen_lanes : FOR K IN c_bus_w-1 DOWNTO 0 GENERATE
+ -- SOSI
+ -- . Transmit order
+ fn_tx_valid((I*c_nof_bus+J)*c_bus_w+K) <= fn_tx_usr_sosi_3arr(I)(J)(K).valid; -- FN
+ bn_tx_valid((I*c_nof_bus+J)*c_bus_w+K) <= bn_tx_usr_sosi_3arr(I)(J)(K).valid; -- BN
+ -- . Receive order (compensate for the transpose)
+ fn_rx_valid((J*c_nof_bus+I)*c_bus_w+K) <= fn_rx_usr_sosi_3arr(I)(J)(K).valid; -- FN
+ bn_rx_valid((J*c_nof_bus+I)*c_bus_w+K) <= bn_rx_usr_sosi_3arr(I)(J)(K).valid; -- BN
+
+ -- SISO
+ -- . Transmit order
+ fn_rx_ready((I*c_nof_bus+J)*c_bus_w+K) <= fn_rx_usr_siso_3arr(I)(J)(K).ready; -- FN
+ bn_rx_ready((I*c_nof_bus+J)*c_bus_w+K) <= bn_rx_usr_siso_3arr(I)(J)(K).ready; -- BN
+ -- . Receive order (compensate for the transpose)
+ fn_tx_ready((J*c_nof_bus+I)*c_bus_w+K) <= fn_tx_usr_siso_3arr(I)(J)(K).ready; -- FN
+ bn_tx_ready((J*c_nof_bus+I)*c_bus_w+K) <= bn_tx_usr_siso_3arr(I)(J)(K).ready; -- BN
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+
+ p_verify : PROCESS(clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ -- SOSI
+ ASSERT fn_tx_valid = bn_rx_valid REPORT "Mesh bn_rx_valid error" SEVERITY ERROR;
+ ASSERT bn_tx_valid = fn_rx_valid REPORT "Mesh fn_rx_valid error" SEVERITY ERROR;
+ -- SISO
+ ASSERT fn_rx_ready = bn_tx_ready REPORT "Mesh bn_tx_ready error" SEVERITY ERROR;
+ ASSERT bn_rx_ready = fn_tx_ready REPORT "Mesh fn_tx_ready error" SEVERITY ERROR;
+ END IF;
+ END PROCESS;
+
+
+ ------------------------------------------------------------------------------
+ -- UniBoard FN0,1,2,3
+ ------------------------------------------------------------------------------
+
+ gen_fn : FOR I IN 0 TO c_nof_node-1 GENERATE
+ u_order : ENTITY work.unb_mesh_reorder_bidir
+ GENERIC MAP (
+ g_node_type => e_fn,
+ g_reorder => c_reorder
+ )
+ PORT MAP (
+ chip_id => TO_UVEC(I, c_chip_id_w), -- chip id 0, 1, 2, 3
+
+ -- Transmit clock domain
+ tx_clk => clk,
+ tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from FN user
+ tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to FN user
+ tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
+ tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I), -- phy siso from mesh
+
+ -- Receive clock domain
+ rx_clk => clk,
+ rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
+ rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I), -- phy siso to mesh
+ rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to FN user
+ rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from FN user
+ );
+ END GENERATE;
+
+
+ ------------------------------------------------------------------------------
+ -- Mesh between FN0,1,2,3 and BN0,1,2,3 as it is wired on the UniBoard PCB
+ ------------------------------------------------------------------------------
+
+ -- >>> unb_mesh_model_sl
+
+ -- Use tx_phy SOSI.valid stimuli for input to unb_mesh_model_sl
+ gen_tx_serial : FOR I IN 0 TO c_nof_node-1 GENERATE
+ gen_bus : FOR J IN 0 TO c_nof_bus-1 GENERATE
+ gen_lanes : FOR K IN c_bus_w-1 DOWNTO 0 GENERATE
+ fn_tx_phy_sl_3arr(I)(J)(K) <= fn_tx_phy_sosi_3arr(I)(J)(K).valid;
+ bn_tx_phy_sl_3arr(I)(J)(K) <= bn_tx_phy_sosi_3arr(I)(J)(K).valid;
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+
+ u_pcb_mesh_serial : ENTITY work.unb_mesh_model_sl
+ GENERIC MAP (
+ g_reorder => c_reorder
+ )
+ PORT MAP (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_tx_phy_sl_3arr,
+ bn_rx_sl_3arr => bn_rx_phy_sl_3arr,
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_tx_phy_sl_3arr,
+ fn_rx_sl_3arr => fn_rx_phy_sl_3arr
+ );
+
+ -- Use rx_phy SOSI.valid as reference output to verify output of unb_mesh_model_sl
+ mon_rx_serial : FOR I IN 0 TO c_nof_node-1 GENERATE
+ gen_bus : FOR J IN 0 TO c_nof_bus-1 GENERATE
+ gen_lanes : FOR K IN c_bus_w-1 DOWNTO 0 GENERATE
+ -- Monitor SOSI valids in SLV
+ bn_rx_phy_valid((I*c_nof_bus+J)*c_bus_w+K) <= bn_rx_phy_sosi_3arr(I)(J)(K).valid;
+ fn_rx_phy_valid((I*c_nof_bus+J)*c_bus_w+K) <= fn_rx_phy_sosi_3arr(I)(J)(K).valid;
+ -- Monitor SL valids in SLV
+ bn_rx_phy_sl((I*c_nof_bus+J)*c_bus_w+K) <= bn_rx_phy_sl_3arr(I)(J)(K);
+ fn_rx_phy_sl((I*c_nof_bus+J)*c_bus_w+K) <= fn_rx_phy_sl_3arr(I)(J)(K);
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+
+ p_verify_serial : PROCESS(clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ ASSERT bn_rx_phy_sl=bn_rx_phy_valid REPORT "unb_mesh_model_sl FN->BN error" SEVERITY ERROR;
+ ASSERT fn_rx_phy_sl=fn_rx_phy_valid REPORT "unb_mesh_model_sl BN->FN error" SEVERITY ERROR;
+ END IF;
+ END PROCESS;
+
+
+ -- >>> unb_mesh_model_sosi
+
+ u_pcb_mesh_sosi : ENTITY work.unb_mesh_model_sosi
+ GENERIC MAP (
+ g_reorder => c_reorder
+ )
+ PORT MAP (
+ -- FN to BN
+ fn0_tx_sosi_2arr => fn_tx_phy_sosi_3arr(0),
+ fn1_tx_sosi_2arr => fn_tx_phy_sosi_3arr(1),
+ fn2_tx_sosi_2arr => fn_tx_phy_sosi_3arr(2),
+ fn3_tx_sosi_2arr => fn_tx_phy_sosi_3arr(3),
+
+ bn0_rx_sosi_2arr => bn_rx_phy_sosi_3arr(0),
+ bn1_rx_sosi_2arr => bn_rx_phy_sosi_3arr(1),
+ bn2_rx_sosi_2arr => bn_rx_phy_sosi_3arr(2),
+ bn3_rx_sosi_2arr => bn_rx_phy_sosi_3arr(3),
+
+ -- BN to FN
+ bn0_tx_sosi_2arr => bn_tx_phy_sosi_3arr(0),
+ bn1_tx_sosi_2arr => bn_tx_phy_sosi_3arr(1),
+ bn2_tx_sosi_2arr => bn_tx_phy_sosi_3arr(2),
+ bn3_tx_sosi_2arr => bn_tx_phy_sosi_3arr(3),
+
+ fn0_rx_sosi_2arr => fn_rx_phy_sosi_3arr(0),
+ fn1_rx_sosi_2arr => fn_rx_phy_sosi_3arr(1),
+ fn2_rx_sosi_2arr => fn_rx_phy_sosi_3arr(2),
+ fn3_rx_sosi_2arr => fn_rx_phy_sosi_3arr(3)
+ );
+
+
+ -- >>> unb_mesh_model_siso
+
+ u_pcb_mesh_siso : ENTITY work.unb_mesh_model_siso
+ GENERIC MAP (
+ g_reorder => c_reorder
+ )
+ PORT MAP (
+ -- FN to BN
+ fn0_rx_siso_2arr => fn_rx_phy_siso_3arr(0),
+ fn1_rx_siso_2arr => fn_rx_phy_siso_3arr(1),
+ fn2_rx_siso_2arr => fn_rx_phy_siso_3arr(2),
+ fn3_rx_siso_2arr => fn_rx_phy_siso_3arr(3),
+
+ bn0_tx_siso_2arr => bn_tx_phy_siso_3arr(0),
+ bn1_tx_siso_2arr => bn_tx_phy_siso_3arr(1),
+ bn2_tx_siso_2arr => bn_tx_phy_siso_3arr(2),
+ bn3_tx_siso_2arr => bn_tx_phy_siso_3arr(3),
+
+ -- BN to FN
+ bn0_rx_siso_2arr => bn_rx_phy_siso_3arr(0),
+ bn1_rx_siso_2arr => bn_rx_phy_siso_3arr(1),
+ bn2_rx_siso_2arr => bn_rx_phy_siso_3arr(2),
+ bn3_rx_siso_2arr => bn_rx_phy_siso_3arr(3),
+
+ fn0_tx_siso_2arr => fn_tx_phy_siso_3arr(0),
+ fn1_tx_siso_2arr => fn_tx_phy_siso_3arr(1),
+ fn2_tx_siso_2arr => fn_tx_phy_siso_3arr(2),
+ fn3_tx_siso_2arr => fn_tx_phy_siso_3arr(3)
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- UniBoard BN0,1,2,3
+ ------------------------------------------------------------------------------
+
+ gen_bn : FOR I IN 0 TO c_nof_node-1 GENERATE
+ u_order : ENTITY work.unb_mesh_reorder_bidir
+ GENERIC MAP (
+ g_node_type => e_bn,
+ g_reorder => c_reorder
+ )
+ PORT MAP (
+ chip_id => TO_UVEC(c_nof_node+I, c_chip_id_w), -- chip id 4, 5, 6, 7
+
+ -- Transmit clock domain
+ tx_clk => clk,
+ tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from BN user
+ tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to BN user
+ tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
+ tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I), -- phy siso from mesh
+
+ -- Receive clock domain
+ rx_clk => clk,
+ rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
+ rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I), -- phy siso to mesh
+ rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to BN user
+ rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from BN user
+ );
+ END GENERATE;
+
+END tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2ef100eeb43d7b8160444ac310ff4564e3e39678
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
@@ -0,0 +1,103 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_unb_node_ctrl IS
+END tb_unb_node_ctrl;
+
+
+ARCHITECTURE tb OF tb_unb_node_ctrl IS
+
+ CONSTANT c_scale : NATURAL := 100; -- scale to speed up simulation
+
+ CONSTANT c_xo_clk_period : TIME := 1 us; -- 1 MHz XO, slow XO to speed up simulation
+ CONSTANT c_sys_clk_period : TIME := c_xo_clk_period/5; -- 5 MHz PLL output from XO reference
+ CONSTANT c_sys_locked_time : TIME := 10 us;
+
+ CONSTANT c_pulse_us : NATURAL := 5; -- nof 5 MHz clk cycles to get us period
+ CONSTANT c_pulse_ms : NATURAL := 1000/c_scale; -- nof pulse_us pulses to get ms period
+ CONSTANT c_pulse_s : NATURAL := 1000; -- nof pulse_ms pulses to get s period
+
+ CONSTANT c_wdi_extend_w : NATURAL := 14; -- extend wdi by about 2**(14-1)= 8 s (as defined by c_pulse_ms)
+ CONSTANT c_wdi_period : TIME := 1000 ms; -- wdi toggle after c_wdi_period
+
+ -- Use c_sw_period=40000 ms to show that the c_wdi_extend_w=5 is not enough, the WD will kick in when the sw is off during reload
+ CONSTANT c_sw_period : TIME := 40000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+ -- Use c_sw_period=10000 ms to show that the c_wdi_extend_w=5 is enough, the WD will not kick in when the sw is off during reload
+ --CONSTANT c_sw_period : TIME := 6000 ms; -- sw active for c_sw_period then inactive during reload for c_sw_period, etc.
+
+ SIGNAL xo_clk : STD_LOGIC := '0';
+ SIGNAL xo_rst_n : STD_LOGIC;
+
+ SIGNAL sys_clk : STD_LOGIC := '0';
+ SIGNAL sys_locked : STD_LOGIC := '0';
+ SIGNAL sys_rst : STD_LOGIC;
+
+ SIGNAL wdi : STD_LOGIC := '0';
+ SIGNAL wdi_in : STD_LOGIC;
+ SIGNAL wdi_out : STD_LOGIC;
+
+ SIGNAL sw : STD_LOGIC := '0';
+
+ SIGNAL pulse_us : STD_LOGIC;
+ SIGNAL pulse_ms : STD_LOGIC;
+ SIGNAL pulse_s : STD_LOGIC;
+
+BEGIN
+
+ -- run 2000 ms
+
+ xo_clk <= NOT xo_clk AFTER c_xo_clk_period/2;
+
+ sys_clk <= NOT sys_clk AFTER c_sys_clk_period/2;
+ sys_locked <= '0', '1' AFTER c_sys_locked_time;
+
+ wdi <= NOT wdi AFTER c_wdi_period/c_scale; -- wd interrupt
+ sw <= NOT sw AFTER c_sw_period/c_scale; -- sw active / reload
+
+ wdi_in <= wdi AND sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
+
+ dut : ENTITY work.unb_node_ctrl
+ GENERIC MAP (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ PORT MAP (
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => sys_rst,
+ wdi_in => wdi_in,
+ wdi_out => wdi_out,
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s
+ );
+
+END tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6c0e9cf01a1bc520b449fac7568b2743d6684c73
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
@@ -0,0 +1,60 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+
+PACKAGE tb_unb_common_pkg IS
+
+ -- Aggregate types to contain all TR for all nodes on one side of the mesh or backplane interface
+
+ -- UniBoard TR mesh IO for 4 to 4 nodes : [node][bus][lane]
+ TYPE t_unb_mesh_sosi_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_mesh_sosi_2arr;
+ TYPE t_unb_mesh_siso_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_mesh_siso_2arr;
+ TYPE t_unb_mesh_sl_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_mesh_sl_2arr;
+
+ -- Subrack with mesh IO for 4 UniBoards, each with TR mesh for 4 to 4 nodes : [unb][node][bus][lane]
+ TYPE t_unb_mesh_sosi_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_mesh_sosi_3arr;
+ TYPE t_unb_mesh_siso_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_mesh_siso_3arr;
+ TYPE t_unb_mesh_sl_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_mesh_sl_3arr;
+
+ -- UniBoard TR backplane IO for 4 BN, each BN with TR to 3 BN each on the 3 other UniBoards [bn][bus][lane]
+ TYPE t_unb_back_sosi_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_back_sosi_2arr;
+ TYPE t_unb_back_siso_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_back_siso_2arr;
+ TYPE t_unb_back_sl_3arr IS ARRAY (c_unb_nof_node-1 DOWNTO 0) OF t_unb_back_sl_2arr;
+
+ -- UniBoard TR backplane IO for 4 UniBoards * 3 buses to other uniboards : [unb][bn][bus][lane]
+ TYPE t_unb_back_sosi_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_back_sosi_3arr;
+ TYPE t_unb_back_siso_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_back_siso_3arr;
+ TYPE t_unb_back_sl_4arr IS ARRAY (c_unb_nof_uniboard-1 DOWNTO 0) OF t_unb_back_sl_3arr;
+
+ TYPE t_unb_id_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0);
+END tb_unb_common_pkg;
+
+
+PACKAGE BODY tb_unb_common_pkg IS
+
+END tb_unb_common_pkg;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..55606000d8de6bdfa132812cc356c49834d81872
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
@@ -0,0 +1,86 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Model the UniBoard backplane of the Apertif beamformer
+-- Description:
+-- The Apertif backplane connects 4 UniBoards using serial links. All BN0 are
+-- connected to all other BN0 in a full mesh of transceiver lanes. Idem for
+-- all BN1, for all BN2 and for all BN3. Each point to point bus between two
+-- BN contains 4 transceiver lanes.
+--
+-- UniBoard bck_id=3 connects to UniBoards 2,1,0 via phy busses 2,1,0
+-- 2 3,1,0 1,0,2
+-- 1 3,2,0 0,1,2
+-- 0 3,2,1 0,2,1
+-- Remark:
+-- . Phy bus 3 is not used and left not connected on the backplane.
+
+LIBRARY IEEE, common_lib, unb_common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+USE work.tb_unb_common_pkg.ALL;
+
+ENTITY unb_back_model_sl IS
+ PORT (
+ backplane_in_serial_4arr : IN t_unb_back_sl_4arr; -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
+ backplane_out_serial_4arr : OUT t_unb_back_sl_4arr
+ );
+END unb_back_model_sl;
+
+
+ARCHITECTURE beh OF unb_back_model_sl IS
+
+BEGIN
+
+ gen_bn : FOR BN IN 0 TO c_unb_nof_bn-1 GENERATE
+
+ ----------------------------------------------------------------------------
+ -- Interconnect BN --> BN streaming with actual backplane routing
+ ----------------------------------------------------------------------------
+
+ backplane_out_serial_4arr(0)(BN)(0) <= backplane_in_serial_4arr(3)(BN)(0);
+ backplane_out_serial_4arr(0)(BN)(1) <= backplane_in_serial_4arr(1)(BN)(2);
+ backplane_out_serial_4arr(0)(BN)(2) <= backplane_in_serial_4arr(2)(BN)(2);
+
+ backplane_out_serial_4arr(1)(BN)(0) <= backplane_in_serial_4arr(3)(BN)(1);
+ backplane_out_serial_4arr(1)(BN)(1) <= backplane_in_serial_4arr(2)(BN)(0);
+ backplane_out_serial_4arr(1)(BN)(2) <= backplane_in_serial_4arr(0)(BN)(1);
+
+ backplane_out_serial_4arr(2)(BN)(0) <= backplane_in_serial_4arr(1)(BN)(1);
+ backplane_out_serial_4arr(2)(BN)(1) <= backplane_in_serial_4arr(3)(BN)(2);
+ backplane_out_serial_4arr(2)(BN)(2) <= backplane_in_serial_4arr(0)(BN)(2);
+
+ backplane_out_serial_4arr(3)(BN)(0) <= backplane_in_serial_4arr(0)(BN)(0);
+ backplane_out_serial_4arr(3)(BN)(1) <= backplane_in_serial_4arr(1)(BN)(0);
+ backplane_out_serial_4arr(3)(BN)(2) <= backplane_in_serial_4arr(2)(BN)(1);
+ -- ^ ^ ^ ^ ^
+ -- | | | | |
+ -- | | BN_BI RX phy bus | BN_BI TX phy bus
+ -- | | Transmitting UniBoard
+ -- | Same scheme applies to all back nodes
+ -- Receiving UniBoard
+
+ END GENERATE;
+
+END beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..21361766c8b9699ab9a561d548e028d28611ba28
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
@@ -0,0 +1,77 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Model the UniBoard backplane of the Apertif beamformer
+-- Description:
+-- Model the backplane at sosi level. See unb_back_model_sl for more details.
+
+
+LIBRARY IEEE, common_lib, unb_common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+USE work.tb_unb_common_pkg.ALL;
+
+ENTITY unb_back_model_sosi IS
+ PORT (
+ backplane_in_sosi_4arr : IN t_unb_back_sosi_4arr; -- _4arr = (UNB 3,2,1,0)(BN 3,2,1,0)(phy bus 2,1,0)(tr lane 3,2,1,0)
+ backplane_out_sosi_4arr : OUT t_unb_back_sosi_4arr
+ );
+END unb_back_model_sosi;
+
+
+ARCHITECTURE beh OF unb_back_model_sosi IS
+
+BEGIN
+
+ gen_bn : FOR BN IN 0 TO c_unb_nof_bn-1 GENERATE
+
+ ----------------------------------------------------------------------------
+ -- Interconnect BN --> BN streaming with actual backplane routing
+ ----------------------------------------------------------------------------
+
+ backplane_out_sosi_4arr(0)(BN)(0) <= backplane_in_sosi_4arr(3)(BN)(0);
+ backplane_out_sosi_4arr(0)(BN)(1) <= backplane_in_sosi_4arr(1)(BN)(2);
+ backplane_out_sosi_4arr(0)(BN)(2) <= backplane_in_sosi_4arr(2)(BN)(2);
+
+ backplane_out_sosi_4arr(1)(BN)(0) <= backplane_in_sosi_4arr(3)(BN)(1);
+ backplane_out_sosi_4arr(1)(BN)(1) <= backplane_in_sosi_4arr(2)(BN)(0);
+ backplane_out_sosi_4arr(1)(BN)(2) <= backplane_in_sosi_4arr(0)(BN)(1);
+
+ backplane_out_sosi_4arr(2)(BN)(0) <= backplane_in_sosi_4arr(1)(BN)(1);
+ backplane_out_sosi_4arr(2)(BN)(1) <= backplane_in_sosi_4arr(3)(BN)(2);
+ backplane_out_sosi_4arr(2)(BN)(2) <= backplane_in_sosi_4arr(0)(BN)(2);
+
+ backplane_out_sosi_4arr(3)(BN)(0) <= backplane_in_sosi_4arr(0)(BN)(0);
+ backplane_out_sosi_4arr(3)(BN)(1) <= backplane_in_sosi_4arr(1)(BN)(0);
+ backplane_out_sosi_4arr(3)(BN)(2) <= backplane_in_sosi_4arr(2)(BN)(1);
+ -- ^ ^ ^ ^ ^
+ -- | | | | |
+ -- | | BN_BI RX phy bu | BN_BI TX phy bus
+ -- | | Transmitting UniBoard
+ -- | Same scheme applies to all back nodes
+ -- Receiving UniBoard
+
+ END GENERATE;
+
+END beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c088fd12fb1dfbc7d87b809531ab083b0ee75b1a
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
@@ -0,0 +1,157 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Model the links between the FN and BN in the UniBoard TR mesh
+-- Description: See unb_mesh_reorder_bidir.vhd
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+
+
+ENTITY unb_mesh_model_siso IS
+ GENERIC (
+ g_reorder : BOOLEAN := TRUE
+ );
+ PORT (
+ -- FN to BN
+ fn0_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst)); -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
+ fn1_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ fn2_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ fn3_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+
+ bn0_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ bn1_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ bn2_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ bn3_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
+
+ -- BN to FN
+ bn0_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ bn1_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ bn2_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+ bn3_rx_siso_2arr : IN t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rst));
+
+ fn0_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ fn1_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ fn2_tx_siso_2arr : OUT t_unb_mesh_siso_2arr;
+ fn3_tx_siso_2arr : OUT t_unb_mesh_siso_2arr
+ );
+END unb_mesh_model_siso;
+
+
+ARCHITECTURE beh OF unb_mesh_model_siso IS
+BEGIN
+
+ -- Functional mesh connect for transpose
+ no_reorder : IF g_reorder=FALSE GENERATE
+ -- BN(i)(j) <= FN(j)(i)
+ bn0_tx_siso_2arr(0) <= fn0_rx_siso_2arr(0);
+ bn0_tx_siso_2arr(1) <= fn1_rx_siso_2arr(0);
+ bn0_tx_siso_2arr(2) <= fn2_rx_siso_2arr(0);
+ bn0_tx_siso_2arr(3) <= fn3_rx_siso_2arr(0);
+
+ bn1_tx_siso_2arr(0) <= fn0_rx_siso_2arr(1);
+ bn1_tx_siso_2arr(1) <= fn1_rx_siso_2arr(1);
+ bn1_tx_siso_2arr(2) <= fn2_rx_siso_2arr(1);
+ bn1_tx_siso_2arr(3) <= fn3_rx_siso_2arr(1);
+
+ bn2_tx_siso_2arr(0) <= fn0_rx_siso_2arr(2);
+ bn2_tx_siso_2arr(1) <= fn1_rx_siso_2arr(2);
+ bn2_tx_siso_2arr(2) <= fn2_rx_siso_2arr(2);
+ bn2_tx_siso_2arr(3) <= fn3_rx_siso_2arr(2);
+
+ bn3_tx_siso_2arr(0) <= fn0_rx_siso_2arr(3);
+ bn3_tx_siso_2arr(1) <= fn1_rx_siso_2arr(3);
+ bn3_tx_siso_2arr(2) <= fn2_rx_siso_2arr(3);
+ bn3_tx_siso_2arr(3) <= fn3_rx_siso_2arr(3);
+
+ -- FN(i)(j) <= BN(j)(i)
+ fn0_tx_siso_2arr(0) <= bn0_rx_siso_2arr(0);
+ fn0_tx_siso_2arr(1) <= bn1_rx_siso_2arr(0);
+ fn0_tx_siso_2arr(2) <= bn2_rx_siso_2arr(0);
+ fn0_tx_siso_2arr(3) <= bn3_rx_siso_2arr(0);
+
+ fn1_tx_siso_2arr(0) <= bn0_rx_siso_2arr(1);
+ fn1_tx_siso_2arr(1) <= bn1_rx_siso_2arr(1);
+ fn1_tx_siso_2arr(2) <= bn2_rx_siso_2arr(1);
+ fn1_tx_siso_2arr(3) <= bn3_rx_siso_2arr(1);
+
+ fn2_tx_siso_2arr(0) <= bn0_rx_siso_2arr(2);
+ fn2_tx_siso_2arr(1) <= bn1_rx_siso_2arr(2);
+ fn2_tx_siso_2arr(2) <= bn2_rx_siso_2arr(2);
+ fn2_tx_siso_2arr(3) <= bn3_rx_siso_2arr(2);
+
+ fn3_tx_siso_2arr(0) <= bn0_rx_siso_2arr(3);
+ fn3_tx_siso_2arr(1) <= bn1_rx_siso_2arr(3);
+ fn3_tx_siso_2arr(2) <= bn2_rx_siso_2arr(3);
+ fn3_tx_siso_2arr(3) <= bn3_rx_siso_2arr(3);
+ END GENERATE;
+
+ -- Actual UniBoard PCB mesh connect for transpose
+ gen_reorder : IF g_reorder=TRUE GENERATE
+ -- BN, phy <= FN, phy
+ bn0_tx_siso_2arr(0) <= fn3_rx_siso_2arr(1); -- 0,0 <= 3,1
+ bn0_tx_siso_2arr(1) <= fn2_rx_siso_2arr(0); -- 0,1 <= 2,0
+ bn0_tx_siso_2arr(2) <= fn1_rx_siso_2arr(0); -- 0,2 <= 1,0
+ bn0_tx_siso_2arr(3) <= fn0_rx_siso_2arr(0); -- 0,3 <= 0,0
+
+ bn1_tx_siso_2arr(0) <= fn3_rx_siso_2arr(0); -- 1,0 <= 3,0
+ bn1_tx_siso_2arr(1) <= fn2_rx_siso_2arr(1); -- 1,1 <= 2,1
+ bn1_tx_siso_2arr(2) <= fn1_rx_siso_2arr(1); -- 1,2 <= 1,1
+ bn1_tx_siso_2arr(3) <= fn0_rx_siso_2arr(3); -- 1,3 <= 0,3
+
+ bn2_tx_siso_2arr(0) <= fn3_rx_siso_2arr(2); -- 2,0 <= 3,2
+ bn2_tx_siso_2arr(1) <= fn2_rx_siso_2arr(2); -- 2,1 <= 2,2
+ bn2_tx_siso_2arr(2) <= fn0_rx_siso_2arr(2); -- 2,2 <= 0,2
+ bn2_tx_siso_2arr(3) <= fn1_rx_siso_2arr(3); -- 2,3 <= 1,3
+
+ bn3_tx_siso_2arr(0) <= fn3_rx_siso_2arr(3); -- 3,0 <= 3,3
+ bn3_tx_siso_2arr(1) <= fn0_rx_siso_2arr(1); -- 3,1 <= 0,1
+ bn3_tx_siso_2arr(2) <= fn2_rx_siso_2arr(3); -- 3,2 <= 2,3
+ bn3_tx_siso_2arr(3) <= fn1_rx_siso_2arr(2); -- 3,3 <= 1,2
+
+ -- FN, phy <= BN, phy
+ fn0_tx_siso_2arr(0) <= bn0_rx_siso_2arr(3); -- 0,0 <= 0,3
+ fn0_tx_siso_2arr(1) <= bn3_rx_siso_2arr(1); -- 0,1 <= 3,1
+ fn0_tx_siso_2arr(2) <= bn2_rx_siso_2arr(2); -- 0,2 <= 2,2
+ fn0_tx_siso_2arr(3) <= bn1_rx_siso_2arr(3); -- 0,3 <= 1,3
+
+ fn1_tx_siso_2arr(0) <= bn0_rx_siso_2arr(2); -- 1,0 <= 0,2
+ fn1_tx_siso_2arr(1) <= bn1_rx_siso_2arr(2); -- 1,1 <= 1,2
+ fn1_tx_siso_2arr(2) <= bn3_rx_siso_2arr(3); -- 1,2 <= 3,3
+ fn1_tx_siso_2arr(3) <= bn2_rx_siso_2arr(3); -- 1,3 <= 2,3
+
+ fn2_tx_siso_2arr(0) <= bn0_rx_siso_2arr(1); -- 2,0 <= 0,1
+ fn2_tx_siso_2arr(1) <= bn1_rx_siso_2arr(1); -- 2,1 <= 1,1
+ fn2_tx_siso_2arr(2) <= bn2_rx_siso_2arr(1); -- 2,2 <= 2,1
+ fn2_tx_siso_2arr(3) <= bn3_rx_siso_2arr(2); -- 2,3 <= 3,2
+
+ fn3_tx_siso_2arr(0) <= bn1_rx_siso_2arr(0); -- 3,0 <= 1,0
+ fn3_tx_siso_2arr(1) <= bn0_rx_siso_2arr(0); -- 3,1 <= 0,0
+ fn3_tx_siso_2arr(2) <= bn2_rx_siso_2arr(0); -- 3,2 <= 2,0
+ fn3_tx_siso_2arr(3) <= bn3_rx_siso_2arr(0); -- 3,3 <= 3,0
+ END GENERATE;
+
+END beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..71351c3a439dcc6e61251707e908bdd9ba7227e9
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
@@ -0,0 +1,112 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Model the links between the FN and BN in the UniBoard TR mesh at
+-- serial transceiver STD_LOGIC level.
+-- Description: See unb_mesh_reorder_bidir.vhd
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+USE work.tb_unb_common_pkg.ALL;
+
+
+ENTITY unb_mesh_model_sl IS
+ GENERIC (
+ g_reorder : BOOLEAN := TRUE
+ );
+ PORT (
+ -- FN to BN
+ fn_tx_sl_3arr : IN t_unb_mesh_sl_3arr := (OTHERS=>(OTHERS=>(OTHERS=>'0'))); -- _3arr = (node id 3,2,1,0)(bus id 3,2,1,0)(tr lane 3,2,1,0)
+ bn_rx_sl_3arr : OUT t_unb_mesh_sl_3arr;
+
+ -- BN to FN
+ bn_tx_sl_3arr : IN t_unb_mesh_sl_3arr := (OTHERS=>(OTHERS=>(OTHERS=>'0')));
+ fn_rx_sl_3arr : OUT t_unb_mesh_sl_3arr
+ );
+END unb_mesh_model_sl;
+
+
+ARCHITECTURE beh OF unb_mesh_model_sl IS
+BEGIN
+
+ -- Functional mesh connect for transpose
+ no_reorder : IF g_reorder=FALSE GENERATE
+ -- BN(i)(j) <= FN(j)(i)
+ -- FN(i)(j) <= BN(j)(i)
+ gen_i : FOR i IN 0 TO 3 GENERATE
+ gen_j : FOR j IN 0 TO 3 GENERATE
+ bn_rx_sl_3arr(i)(j) <= fn_tx_sl_3arr(j)(i);
+ fn_rx_sl_3arr(i)(j) <= bn_tx_sl_3arr(j)(i);
+ END GENERATE;
+ END GENERATE;
+ END GENERATE;
+
+ -- Actual UniBoard PCB mesh connect for transpose
+ gen_reorder : IF g_reorder=TRUE GENERATE
+ -- BN, phy <= FN, phy
+ bn_rx_sl_3arr(0)(0) <= fn_tx_sl_3arr(3)(1); -- 0,0 <= 3,1
+ bn_rx_sl_3arr(0)(1) <= fn_tx_sl_3arr(2)(0); -- 0,1 <= 2,0
+ bn_rx_sl_3arr(0)(2) <= fn_tx_sl_3arr(1)(0); -- 0,2 <= 1,0
+ bn_rx_sl_3arr(0)(3) <= fn_tx_sl_3arr(0)(0); -- 0,3 <= 0,0
+
+ bn_rx_sl_3arr(1)(0) <= fn_tx_sl_3arr(3)(0); -- 1,0 <= 3,0
+ bn_rx_sl_3arr(1)(1) <= fn_tx_sl_3arr(2)(1); -- 1,1 <= 2,1
+ bn_rx_sl_3arr(1)(2) <= fn_tx_sl_3arr(1)(1); -- 1,2 <= 1,1
+ bn_rx_sl_3arr(1)(3) <= fn_tx_sl_3arr(0)(3); -- 1,3 <= 0,3
+
+ bn_rx_sl_3arr(2)(0) <= fn_tx_sl_3arr(3)(2); -- 2,0 <= 3,2
+ bn_rx_sl_3arr(2)(1) <= fn_tx_sl_3arr(2)(2); -- 2,1 <= 2,2
+ bn_rx_sl_3arr(2)(2) <= fn_tx_sl_3arr(0)(2); -- 2,2 <= 0,2
+ bn_rx_sl_3arr(2)(3) <= fn_tx_sl_3arr(1)(3); -- 2,3 <= 1,3
+
+ bn_rx_sl_3arr(3)(0) <= fn_tx_sl_3arr(3)(3); -- 3,0 <= 3,3
+ bn_rx_sl_3arr(3)(1) <= fn_tx_sl_3arr(0)(1); -- 3,1 <= 0,1
+ bn_rx_sl_3arr(3)(2) <= fn_tx_sl_3arr(2)(3); -- 3,2 <= 2,3
+ bn_rx_sl_3arr(3)(3) <= fn_tx_sl_3arr(1)(2); -- 3,3 <= 1,2
+
+ -- FN, phy <= BN, phy
+ fn_rx_sl_3arr(0)(0) <= bn_tx_sl_3arr(0)(3); -- 0,0 <= 0,3
+ fn_rx_sl_3arr(0)(1) <= bn_tx_sl_3arr(3)(1); -- 0,1 <= 3,1
+ fn_rx_sl_3arr(0)(2) <= bn_tx_sl_3arr(2)(2); -- 0,2 <= 2,2
+ fn_rx_sl_3arr(0)(3) <= bn_tx_sl_3arr(1)(3); -- 0,3 <= 1,3
+
+ fn_rx_sl_3arr(1)(0) <= bn_tx_sl_3arr(0)(2); -- 1,0 <= 0,2
+ fn_rx_sl_3arr(1)(1) <= bn_tx_sl_3arr(1)(2); -- 1,1 <= 1,2
+ fn_rx_sl_3arr(1)(2) <= bn_tx_sl_3arr(3)(3); -- 1,2 <= 3,3
+ fn_rx_sl_3arr(1)(3) <= bn_tx_sl_3arr(2)(3); -- 1,3 <= 2,3
+
+ fn_rx_sl_3arr(2)(0) <= bn_tx_sl_3arr(0)(1); -- 2,0 <= 0,1
+ fn_rx_sl_3arr(2)(1) <= bn_tx_sl_3arr(1)(1); -- 2,1 <= 1,1
+ fn_rx_sl_3arr(2)(2) <= bn_tx_sl_3arr(2)(1); -- 2,2 <= 2,1
+ fn_rx_sl_3arr(2)(3) <= bn_tx_sl_3arr(3)(2); -- 2,3 <= 3,2
+
+ fn_rx_sl_3arr(3)(0) <= bn_tx_sl_3arr(1)(0); -- 3,0 <= 1,0
+ fn_rx_sl_3arr(3)(1) <= bn_tx_sl_3arr(0)(0); -- 3,1 <= 0,0
+ fn_rx_sl_3arr(3)(2) <= bn_tx_sl_3arr(2)(0); -- 3,2 <= 2,0
+ fn_rx_sl_3arr(3)(3) <= bn_tx_sl_3arr(3)(0); -- 3,3 <= 3,0
+ END GENERATE;
+
+END beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bb72f50a2ff8cebb0222f2a4ca5418b11f93f279
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
@@ -0,0 +1,157 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Model the links between the FN and BN in the UniBoard TR mesh
+-- Description: See unb_mesh_reorder_bidir.vhd
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb_common_pkg.ALL;
+
+
+ENTITY unb_mesh_model_sosi IS
+ GENERIC (
+ g_reorder : BOOLEAN := TRUE
+ );
+ PORT (
+ -- FN to BN
+ fn0_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst)); -- _2arr = (node id 3,2,1,0)(tr lane 3,2,1,0)
+ fn1_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ fn2_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ fn3_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+
+ bn0_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ bn1_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ bn2_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ bn3_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+
+ -- BN to FN
+ bn0_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ bn1_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ bn2_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+ bn3_tx_sosi_2arr : IN t_unb_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst));
+
+ fn0_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ fn1_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ fn2_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr;
+ fn3_rx_sosi_2arr : OUT t_unb_mesh_sosi_2arr
+ );
+END unb_mesh_model_sosi;
+
+
+ARCHITECTURE beh OF unb_mesh_model_sosi IS
+BEGIN
+
+ -- Functional mesh connect for transpose
+ no_reorder : IF g_reorder=FALSE GENERATE
+ -- BN(i)(j) <= FN(j)(i)
+ bn0_rx_sosi_2arr(0) <= fn0_tx_sosi_2arr(0);
+ bn0_rx_sosi_2arr(1) <= fn1_tx_sosi_2arr(0);
+ bn0_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(0);
+ bn0_rx_sosi_2arr(3) <= fn3_tx_sosi_2arr(0);
+
+ bn1_rx_sosi_2arr(0) <= fn0_tx_sosi_2arr(1);
+ bn1_rx_sosi_2arr(1) <= fn1_tx_sosi_2arr(1);
+ bn1_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(1);
+ bn1_rx_sosi_2arr(3) <= fn3_tx_sosi_2arr(1);
+
+ bn2_rx_sosi_2arr(0) <= fn0_tx_sosi_2arr(2);
+ bn2_rx_sosi_2arr(1) <= fn1_tx_sosi_2arr(2);
+ bn2_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(2);
+ bn2_rx_sosi_2arr(3) <= fn3_tx_sosi_2arr(2);
+
+ bn3_rx_sosi_2arr(0) <= fn0_tx_sosi_2arr(3);
+ bn3_rx_sosi_2arr(1) <= fn1_tx_sosi_2arr(3);
+ bn3_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(3);
+ bn3_rx_sosi_2arr(3) <= fn3_tx_sosi_2arr(3);
+
+ -- FN(i)(j) <= BN(j)(i)
+ fn0_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(0);
+ fn0_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(0);
+ fn0_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(0);
+ fn0_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(0);
+
+ fn1_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(1);
+ fn1_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(1);
+ fn1_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(1);
+ fn1_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(1);
+
+ fn2_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(2);
+ fn2_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(2);
+ fn2_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(2);
+ fn2_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(2);
+
+ fn3_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(3);
+ fn3_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(3);
+ fn3_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(3);
+ fn3_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(3);
+ END GENERATE;
+
+ -- Actual UniBoard PCB mesh connect for transpose
+ gen_reorder : IF g_reorder=TRUE GENERATE
+ -- BN, phy <= FN, phy
+ bn0_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(1); -- 0,0 <= 3,1
+ bn0_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(0); -- 0,1 <= 2,0
+ bn0_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(0); -- 0,2 <= 1,0
+ bn0_rx_sosi_2arr(3) <= fn0_tx_sosi_2arr(0); -- 0,3 <= 0,0
+
+ bn1_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(0); -- 1,0 <= 3,0
+ bn1_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(1); -- 1,1 <= 2,1
+ bn1_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(1); -- 1,2 <= 1,1
+ bn1_rx_sosi_2arr(3) <= fn0_tx_sosi_2arr(3); -- 1,3 <= 0,3
+
+ bn2_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(2); -- 2,0 <= 3,2
+ bn2_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(2); -- 2,1 <= 2,2
+ bn2_rx_sosi_2arr(2) <= fn0_tx_sosi_2arr(2); -- 2,2 <= 0,2
+ bn2_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(3); -- 2,3 <= 1,3
+
+ bn3_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(3); -- 3,0 <= 3,3
+ bn3_rx_sosi_2arr(1) <= fn0_tx_sosi_2arr(1); -- 3,1 <= 0,1
+ bn3_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(3); -- 3,2 <= 2,3
+ bn3_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(2); -- 3,3 <= 1,2
+
+ -- FN, phy <= BN, phy
+ fn0_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(3); -- 0,0 <= 0,3
+ fn0_rx_sosi_2arr(1) <= bn3_tx_sosi_2arr(1); -- 0,1 <= 3,1
+ fn0_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(2); -- 0,2 <= 2,2
+ fn0_rx_sosi_2arr(3) <= bn1_tx_sosi_2arr(3); -- 0,3 <= 1,3
+
+ fn1_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(2); -- 1,0 <= 0,2
+ fn1_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(2); -- 1,1 <= 1,2
+ fn1_rx_sosi_2arr(2) <= bn3_tx_sosi_2arr(3); -- 1,2 <= 3,3
+ fn1_rx_sosi_2arr(3) <= bn2_tx_sosi_2arr(3); -- 1,3 <= 2,3
+
+ fn2_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(1); -- 2,0 <= 0,1
+ fn2_rx_sosi_2arr(1) <= bn1_tx_sosi_2arr(1); -- 2,1 <= 1,1
+ fn2_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(1); -- 2,2 <= 2,1
+ fn2_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(2); -- 2,3 <= 3,2
+
+ fn3_rx_sosi_2arr(0) <= bn1_tx_sosi_2arr(0); -- 3,0 <= 1,0
+ fn3_rx_sosi_2arr(1) <= bn0_tx_sosi_2arr(0); -- 3,1 <= 0,0
+ fn3_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(0); -- 3,2 <= 2,0
+ fn3_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(0); -- 3,3 <= 3,0
+ END GENERATE;
+
+END beh;