diff --git a/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd b/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
index 46e268c3d319a47535bd7027492c6f2f91aa2b3d..b33b43c3a07e08e9bec67bae81e933d2ace63a8a 100644
--- a/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
@@ -27,7 +27,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE tech_transceiver_component_pkg IS
------------------------------------------------------------------------------
- -- stratixiv_hssi
+ -- ip_stratixiv
------------------------------------------------------------------------------
COMPONENT ip_stratixiv_hssi_gx_generic IS
@@ -111,11 +111,7 @@ PACKAGE tech_transceiver_component_pkg IS
END COMPONENT;
- ------------------------------------------------------------------------------
- -- altera_mf
- ------------------------------------------------------------------------------
-
- COMPONENT ip_altera_mf_gxb_reconfig_12_stratixiv IS
+ COMPONENT ip_stratixiv_gxb_reconfig_12 IS
PORT (
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (203 DOWNTO 0);
@@ -124,7 +120,7 @@ PACKAGE tech_transceiver_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_8_stratixiv IS
+ COMPONENT ip_stratixiv_gxb_reconfig_8 IS
PORT (
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (135 DOWNTO 0);
@@ -133,7 +129,7 @@ PACKAGE tech_transceiver_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_4_stratixiv IS
+ COMPONENT ip_stratixiv_gxb_reconfig_4 IS
PORT (
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (67 DOWNTO 0);
@@ -142,7 +138,7 @@ PACKAGE tech_transceiver_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_2_stratixiv IS
+ COMPONENT ip_stratixiv_gxb_reconfig_2 IS
PORT (
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (33 DOWNTO 0);
diff --git a/libraries/technology/transceiver/tech_transceiver_gx.vhd b/libraries/technology/transceiver/tech_transceiver_gx.vhd
index 292c5ccd54868c9c3c62301bd32e1c7dca75602f..c4c21fb5cb1aaee7de858c19529f7826b8c1208a 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx.vhd
@@ -70,7 +70,7 @@ END tech_transceiver_gx;
ARCHITECTURE str OF tech_transceiver_gx IS
BEGIN
- gen_stratixiv_hssi : IF g_technology=c_tech_stratixiv GENERATE
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_transceiver_gx_stratix_iv
GENERIC MAP (g_data_w, g_nof_gx, g_mbps, g_sim, g_tx, g_rx)
PORT MAP (cal_rec_clk, tr_clk, rx_clk, rx_rst, rx_sosi_arr, rx_siso_arr, tx_clk, tx_rst, tx_sosi_arr, tx_siso_arr, rx_datain, tx_dataout, tx_state, tx_align_en, rx_state, rx_align_en);
diff --git a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
index 598b0e1b6a1c655f5672f4ba20e4985caf56f6e7..b69ea408b902f875743b0156c9ab167d140a65dd 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
@@ -28,8 +28,7 @@ USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
-LIBRARY ip_stratixiv_hssi_lib;
+LIBRARY ip_stratixiv_lib;
ENTITY tech_transceiver_gx_stratix_iv IS
GENERIC(
@@ -136,7 +135,7 @@ BEGIN
gen_tr : IF g_tx = TRUE AND g_rx = TRUE GENERATE --Generate duplex transceivers
gen_32b : IF g_data_w = 32 GENERATE
- u_gx: ENTITY ip_stratixiv_hssi_lib.ip_stratixiv_hssi_gx_generic
+ u_gx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_gx_generic
GENERIC MAP (
g_mbps => g_mbps,
starting_channel_number => i*4 --Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
@@ -182,7 +181,7 @@ BEGIN
END GENERATE;
gen_16b : IF g_data_w = 16 GENERATE
- u_gx: ENTITY ip_stratixiv_hssi_lib.ip_stratixiv_hssi_gx_16b
+ u_gx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_gx_16b
GENERIC MAP (
starting_channel_number => i*4 --Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
) --Reconfig megawizard: regenerate with 'number of channels' = 4*nof_gx
@@ -226,7 +225,7 @@ BEGIN
gen_rx : IF g_tx = FALSE AND g_rx = TRUE GENERATE --Generate receivers only
gen_32b : IF g_data_w = 32 GENERATE
- u_rx: ENTITY ip_stratixiv_hssi_lib.ip_stratixiv_hssi_rx_generic
+ u_rx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_rx_generic
GENERIC MAP (
g_mbps => g_mbps,
starting_channel_number => i*4 --Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
@@ -252,7 +251,7 @@ BEGIN
END GENERATE;
gen_16b : IF g_data_w = 16 GENERATE
- u_rx: ENTITY ip_stratixiv_hssi_lib.ip_stratixiv_hssi_rx_16b
+ u_rx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_rx_16b
GENERIC MAP (
starting_channel_number => i*4 --Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
) --Reconfig megawizard: regenerate with 'number of channels' = 4*nof_gx
@@ -290,7 +289,7 @@ BEGIN
gen_tx : IF g_tx = TRUE AND g_rx = FALSE GENERATE
gen_32b : IF g_data_w = 32 GENERATE
- u_tx: ENTITY ip_stratixiv_hssi_lib.ip_stratixiv_hssi_tx_generic
+ u_tx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_tx_generic
GENERIC MAP (
g_mbps => g_mbps
)
@@ -309,7 +308,7 @@ BEGIN
END GENERATE;
gen_16b : IF g_data_w = 16 GENERATE
- u_tx: ENTITY ip_stratixiv_hssi_lib.ip_stratixiv_hssi_tx_16b
+ u_tx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_tx_16b
PORT MAP (
-- Clocks, in
pll_inclk => tr_clk,
@@ -488,7 +487,7 @@ BEGIN
------------------------------------------------------------------------------
gen_cond_reconfig : IF g_nof_gx = 12 GENERATE
- u_reconfig : ENTITY ip_altera_mf_lib.ip_altera_mf_gxb_reconfig_12_stratixiv --Create one reconfig module for all ALTGX instances
+ u_reconfig : ENTITY ip_stratixiv_lib.ip_stratixiv_gxb_reconfig_12 --Create one reconfig module for all ALTGX instances
PORT MAP (
reconfig_clk => cal_rec_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -498,7 +497,7 @@ BEGIN
END GENERATE;
gen_cond_reconfig_8 : IF g_nof_gx = 8 GENERATE
- u_reconfig : ENTITY ip_altera_mf_lib.ip_altera_mf_gxb_reconfig_8_stratixiv --Create one reconfig module for all ALTGX instances
+ u_reconfig : ENTITY ip_stratixiv_lib.ip_stratixiv_gxb_reconfig_8 --Create one reconfig module for all ALTGX instances
PORT MAP (
reconfig_clk => cal_rec_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -508,7 +507,7 @@ BEGIN
END GENERATE;
gen_cond_reconfig_4 : IF g_nof_gx = 4 GENERATE
- u_reconfig : ENTITY ip_altera_mf_lib.ip_altera_mf_gxb_reconfig_4_stratixiv --Create one reconfig module for all ALTGX instances
+ u_reconfig : ENTITY ip_stratixiv_lib.ip_stratixiv_gxb_reconfig_4 --Create one reconfig module for all ALTGX instances
PORT MAP (
reconfig_clk => cal_rec_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -518,7 +517,7 @@ BEGIN
END GENERATE;
gen_cond_reconfig_sim : IF g_nof_gx = 2 GENERATE
- u_reconfig_sim : ENTITY ip_altera_mf_lib.ip_altera_mf_gxb_reconfig_2_stratixiv -- The sim version is meant for 2 transceivers
+ u_reconfig_sim : ENTITY ip_stratixiv_lib.ip_stratixiv_gxb_reconfig_2 -- The sim version is meant for 2 transceivers
PORT MAP (
reconfig_clk => cal_rec_clk,
reconfig_fromgxb => reconfig_fromgxb,