diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 049d49e757afc23cc41cd45851f0291976895032..696629eeab95d5fb2b1c99da91dcbd4c97b9f431 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -21,7 +21,7 @@ parameters:
- { name: c_N_taps, value: 16 }
- { name: c_W_adc_jesd, value: 16 }
- { name: c_W_adc, value: 14 }
- - { name: c_R_os, value: 2 }
+ - { name: c_R_os, value: 2 }
- { name: c_V_sample_delay, value: 4096 }
- { name: c_V_si_db_large, value: 131072 }
- { name: c_V_si_db, value: 1024 }
@@ -222,7 +222,8 @@ peripherals:
- { name: P_pfb, value: c_R_os * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_EQUALIZER_GAINS
-
+ - RAM_EQUALIZER_GAINS_CROSS
+
- peripheral_name: dp/dp_selector
mm_port_names:
- REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 3bbe9c203ef9726a41b99ea2576ebdebda0813be..52404f9735568534d163cbb0f803266f06215680 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -273,6 +273,8 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Equalizer gains
SIGNAL ram_equalizer_gains_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL ram_equalizer_gains_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL ram_equalizer_gains_cross_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_equalizer_gains_cross_cipo : t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
SIGNAL reg_dp_selector_copi : t_mem_copi := c_mem_copi_rst;
@@ -707,7 +709,9 @@ BEGIN
reg_si_cipo => reg_si_cipo,
ram_equalizer_gains_copi => ram_equalizer_gains_copi,
ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
reg_dp_selector_cipo => reg_dp_selector_cipo,
reg_sdp_info_copi => reg_sdp_info_copi,
reg_sdp_info_cipo => reg_sdp_info_cipo,
@@ -885,6 +889,8 @@ BEGIN
ram_fil_coefs_cipo => ram_fil_coefs_cipo,
ram_equalizer_gains_copi => ram_equalizer_gains_copi,
ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
reg_dp_selector_copi => reg_dp_selector_copi,
reg_dp_selector_cipo => reg_dp_selector_cipo,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index cb7a197ecec74c7e8ca28de2c24cba95f84afb87..92ee9e4b79968d6fb2498ae2c342c646d29ebcff 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -153,6 +153,8 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
-- Equalizer gains
ram_equalizer_gains_copi : OUT t_mem_copi;
ram_equalizer_gains_cipo : IN t_mem_cipo;
+ ram_equalizer_gains_cross_copi : OUT t_mem_copi;
+ ram_equalizer_gains_cross_cipo : IN t_mem_cipo;
-- DP Selector
reg_dp_selector_copi : OUT t_mem_copi;
@@ -421,6 +423,8 @@ BEGIN
u_mm_file_ram_equalizer_gains : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
+ u_mm_file_ram_equalizer_gains_cross : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
+ PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
u_mm_file_reg_dp_selector : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
PORT MAP(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
@@ -838,6 +842,14 @@ BEGIN
ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_cross_clk_export => OPEN,
+ ram_equalizer_gains_cross_reset_export => OPEN,
+ ram_equalizer_gains_cross_address_export => ram_equalizer_gains_cross_copi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
+ ram_equalizer_gains_cross_write_export => ram_equalizer_gains_cross_copi.wr,
+ ram_equalizer_gains_cross_writedata_export => ram_equalizer_gains_cross_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_cross_read_export => ram_equalizer_gains_cross_copi.rd,
+ ram_equalizer_gains_cross_readdata_export => ram_equalizer_gains_cross_cipo.rddata(c_word_w-1 DOWNTO 0),
+
reg_dp_selector_clk_export => OPEN,
reg_dp_selector_reset_export => OPEN,
reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index b156b4c6a05e253dd1b19676589277f604fa6b53..1bed8e386bc1c3cf89891d0a0ed37a1f9923f389 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -98,6 +98,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
ram_equalizer_gains_reset_export : out std_logic; -- export
ram_equalizer_gains_write_export : out std_logic; -- export
ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
ram_fil_coefs_clk_export : out std_logic; -- export
ram_fil_coefs_read_export : out std_logic; -- export
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index b350714e1ecfbd8ff5c857721530b21153f03412..094c157891d89105d8b296d010c6e380ad3933ac 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -222,7 +222,8 @@ peripherals:
- { name: P_pfb, value: c_R_os * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_EQUALIZER_GAINS
-
+ - RAM_EQUALIZER_GAINS_CROSS
+
- peripheral_name: dp/dp_selector
mm_port_names:
- REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 032a29e62fdffac0ad0b4bed69e0a9599d4aee7d..d419d5eb41e225dc7eb53e2d3789b391e93de56b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -257,6 +257,8 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
-- Equalizer gains
SIGNAL ram_equalizer_gains_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL ram_equalizer_gains_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL ram_equalizer_gains_cross_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_equalizer_gains_cross_cipo : t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
SIGNAL reg_dp_selector_copi : t_mem_copi := c_mem_copi_rst;
@@ -673,7 +675,9 @@ BEGIN
reg_si_cipo => reg_si_cipo,
ram_equalizer_gains_copi => ram_equalizer_gains_copi,
ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
reg_dp_selector_cipo => reg_dp_selector_cipo,
reg_sdp_info_copi => reg_sdp_info_copi,
reg_sdp_info_cipo => reg_sdp_info_cipo,
@@ -849,6 +853,8 @@ BEGIN
ram_fil_coefs_cipo => ram_fil_coefs_cipo,
ram_equalizer_gains_copi => ram_equalizer_gains_copi,
ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
reg_dp_selector_copi => reg_dp_selector_copi,
reg_dp_selector_cipo => reg_dp_selector_cipo,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index e00b83112f2f0664da42844f6f7231ba8733bccc..e45477e43043854d0f0db267964378df9dd5f915 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -146,6 +146,8 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
-- Equalizer gains
ram_equalizer_gains_copi : OUT t_mem_copi;
ram_equalizer_gains_cipo : IN t_mem_cipo;
+ ram_equalizer_gains_cross_copi : OUT t_mem_copi;
+ ram_equalizer_gains_cross_cipo : IN t_mem_cipo;
-- DP Selector
reg_dp_selector_copi : OUT t_mem_copi;
@@ -408,6 +410,8 @@ BEGIN
u_mm_file_ram_equalizer_gains : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
+ u_mm_file_ram_equalizer_gains_cross : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
+ PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
u_mm_file_reg_dp_selector : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
PORT MAP(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
@@ -809,6 +813,14 @@ BEGIN
ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_cross_clk_export => OPEN,
+ ram_equalizer_gains_cross_reset_export => OPEN,
+ ram_equalizer_gains_cross_address_export => ram_equalizer_gains_cross_copi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
+ ram_equalizer_gains_cross_write_export => ram_equalizer_gains_cross_copi.wr,
+ ram_equalizer_gains_cross_writedata_export => ram_equalizer_gains_cross_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_cross_read_export => ram_equalizer_gains_cross_copi.rd,
+ ram_equalizer_gains_cross_readdata_export => ram_equalizer_gains_cross_cipo.rddata(c_word_w-1 DOWNTO 0),
+
reg_dp_selector_clk_export => OPEN,
reg_dp_selector_reset_export => OPEN,
reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index c8f7511c6e9e19f71e91ec67d526c2f11eecb18a..9617f9ba57b5dbc9a64cf9cc0f74184b7883b369 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -99,6 +99,13 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
ram_equalizer_gains_reset_export : out std_logic; -- export
ram_equalizer_gains_write_export : out std_logic; -- export
ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
ram_fil_coefs_clk_export : out std_logic; -- export
ram_fil_coefs_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index 17ecf33f68ea58c091536657741177c6ea315f25..3e7c08ebe5df00af900ae232a8be65ddea673054 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -80,8 +80,24 @@ peripherals:
fields:
- - field_name: coef
field_description: |
- "Complex coefficient to calibrate the gain and phase per subband. Packed as imaginary in high part,
- real in low part of mm_width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
+ "Complex coefficient to calibrate the co-polarization gain and phase per subband.
+ Packed as imaginary in high part, real in low part of mm_width =
+ N_complex * W_sub_weight = 2 * 16 = 32 bit."
+ number_of_fields: Q_fft * N_sub # = 1024 = 2 signal inputs * 512 subbands
+ address_offset: 0x0
+ mm_width: 32 # = N_complex * W_sub_weight
+ radix: cint16_ir
+ - mm_port_name: RAM_EQUALIZER_GAINS_CROSS
+ mm_port_type: RAM
+ mm_port_span: ceil_pow2(Q_fft * N_sub) * MM_BUS_SIZE
+ mm_port_description: |
+ "Idem as RAM_EQUALIZER_GAINS, but for cross polarization."
+ number_of_mm_ports: P_pfb
+ fields:
+ - - field_name: coef
+ field_description: |
+ "Complex coefficient to calibrate the cross-polarization gain and phase per subband.
+ Packed idem as RAM_EQUALIZER_GAINS."
number_of_fields: Q_fft * N_sub # = 1024 = 2 signal inputs * 512 subbands
address_offset: 0x0
mm_width: 32 # = N_complex * W_sub_weight
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index ee1504f8af13ccc6c7e19fb2212ee6e9aabc2fa2..fb33891a243a3bf0afb3ef243ec5717234e858d8 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -95,6 +95,8 @@ ENTITY node_sdp_filterbank IS
ram_fil_coefs_miso : OUT t_mem_miso;
ram_gains_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_gains_miso : OUT t_mem_miso;
+ ram_gains_cross_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_gains_cross_miso : OUT t_mem_miso;
reg_selector_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_selector_miso : OUT t_mem_miso;
reg_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
@@ -269,8 +271,10 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
+ ram_gains_cross_mosi => ram_gains_cross_mosi,
+ ram_gains_cross_miso => ram_gains_cross_miso
);
-- Output fsub streams
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
index 49932ca1ecab1e776d8c41ca53574746e4992d1e..c5e3babf49bcb77568dc796923ab222233061423 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
@@ -79,6 +79,8 @@ ENTITY node_sdp_oversampled_filterbank IS
ram_fil_coefs_miso : OUT t_mem_miso;
ram_gains_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_gains_miso : OUT t_mem_miso;
+ ram_gains_cross_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_gains_cross_miso : OUT t_mem_miso;
reg_selector_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_selector_miso : OUT t_mem_miso;
reg_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
@@ -557,8 +559,10 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
+ ram_gains_cross_mosi => ram_gains_cross_mosi,
+ ram_gains_cross_miso => ram_gains_cross_miso
);
-- Output fsub streams
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 10852948b277c0f473de373c932034c7ca30027d..63edbd9b6185ffb6ffb728d8fba75d823e2ccf3d 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -232,7 +232,7 @@ PACKAGE sdp_pkg is
-----------------------------------------------------------------------------
-- Subband Equalizer
-----------------------------------------------------------------------------
- CONSTANT c_sdp_subband_equalizer_latency : NATURAL := 7;
+ CONSTANT c_sdp_subband_equalizer_latency : NATURAL := 11;
-----------------------------------------------------------------------------
-- Statistics offload
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 08ede03ff0d1dd72d00546aba4555cdc750a1234..699b97ea192af7d23dd7ae9d0bfcc25790144c84 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -167,6 +167,8 @@ ENTITY sdp_station IS
-- Equalizer gains
ram_equalizer_gains_copi : IN t_mem_copi := c_mem_copi_rst;
ram_equalizer_gains_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ ram_equalizer_gains_cross_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_equalizer_gains_cross_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
reg_dp_selector_copi : IN t_mem_copi := c_mem_copi_rst;
@@ -747,7 +749,9 @@ BEGIN
ram_fil_coefs_miso => ram_fil_coefs_cipo,
ram_gains_mosi => ram_equalizer_gains_copi,
ram_gains_miso => ram_equalizer_gains_cipo,
- reg_selector_mosi => reg_dp_selector_copi,
+ ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
+ ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
reg_selector_miso => reg_dp_selector_cipo,
reg_enable_mosi => reg_stat_enable_sst_copi,
@@ -806,7 +810,9 @@ BEGIN
ram_fil_coefs_miso => ram_fil_coefs_cipo,
ram_gains_mosi => ram_equalizer_gains_copi,
ram_gains_miso => ram_equalizer_gains_cipo,
- reg_selector_mosi => reg_dp_selector_copi,
+ ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
+ ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
reg_selector_miso => reg_dp_selector_cipo,
reg_enable_mosi => reg_stat_enable_sst_copi,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index 69f6daea5876037e6e19ee2b6be75c98bf1c20da..0d1486c0ae3b67cd1f2d5d09edffbc1f0417d925 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -25,13 +25,26 @@
-- . Implements the functionality of the subband equalizer in the subband
-- filterbank (Fsub) of the LOFAR2 SDPFW design.
-- Description:
+-- . Block diagram:
+--
+-- in_raw ----> pipeline --> * co-pol weights --+-----> Q --> out_raw
+-- \-> reverse pol --> * cross-pol weights --/ \--> Q --> out_quant
+--
-- . The sdp_subband_equalizer.vhd consists of mms_dp_gain_serial_arr.vhd and
-- some address counter logic to select the address of the subband weight
-- and a dp_requantize.vhd component.
+-- . The subband equalizer can calibrate for co-polarization using only the
+-- co-polarization weights from ram_gains_mosi. Or it can do full Jones
+-- matrix calibration using also the cross polarization weights from
+-- ram_gains_cross_mosi.
+-- . Default the co-polarization weights are read from g_gains_file_name and
+-- default the cross polarization weights are 0.
-- . Subband widths:
-- - raw_sosi : g_raw_dat_w bits
-- - quant_sosi : c_quant_dat_w = g_raw_dat_w - g_raw_fraction_w bits
-- Remark:
+-- . If the latency of sdp_subband_equalizer.vhd is changed, then
+-- c_sdp_subband_equalizer_latency in sdp_pkg.vhd needs to be updated.
--
-------------------------------------------------------------------------------
@@ -44,7 +57,7 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_subband_equalizer IS
GENERIC (
- g_gains_file_name : STRING := "UNUSED";
+ g_gains_file_name : STRING := "UNUSED"; -- for co-polarization
g_nof_streams : NATURAL := c_sdp_P_pfb;
-- Use no default raw width, to force instance to set it
g_raw_dat_w : NATURAL; -- default: c_sdp_W_subband;
@@ -62,7 +75,10 @@ ENTITY sdp_subband_equalizer IS
mm_clk : IN STD_LOGIC;
ram_gains_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_gains_miso : OUT t_mem_miso
+ ram_gains_miso : OUT t_mem_miso;
+
+ ram_gains_cross_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_gains_cross_miso : OUT t_mem_miso
);
END sdp_subband_equalizer;
@@ -75,95 +91,128 @@ ARCHITECTURE str OF sdp_subband_equalizer IS
CONSTANT c_quant_dat_w : NATURAL := g_raw_dat_w - g_raw_fraction_w;
- -- Pipeline requantization to easy timing closure
+ -- Pipeline to easy timing closure
CONSTANT c_pipeline_remove_lsb : NATURAL := 1;
CONSTANT c_pipeline_remove_msb : NATURAL := 1;
- SIGNAL in_sosi : t_dp_sosi;
- SIGNAL cnt : NATURAL RANGE 0 TO c_sdp_Q_fft * c_sdp_N_sub-1;
- SIGNAL gains_rd_address : STD_LOGIC_VECTOR(c_gain_addr_w-1 DOWNTO 0);
- SIGNAL weighted_raw_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL in_pipe_raw_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL in_cross_raw_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL in_raw_sosi_2arr_2 : t_dp_sosi_2arr_2(g_nof_streams-1 DOWNTO 0);
-BEGIN
+ SIGNAL weighted_raw_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL weighted_cross_raw_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- in_sosi <= in_raw_sosi_arr(0); -- use ctrl from input [0]
+ SIGNAL sum_raw_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+
+BEGIN
-----------------------------------------------------------------------------
- -- Counter
+ -- Prepare co and cross input
-----------------------------------------------------------------------------
- -- The subband weigths per PN are stored as
- -- (cint16)subband_weights[S_pn/Q_fft]_[Q_fft][N_sub], but have
- -- to be applied according the subband data order
- -- fsub[S_pn/Q_fft]_[N_sub][Q_fft]. Therefore the counter in
- -- sdp_subband_equalizer.vhd has to account for this difference in order.
- p_cnt : PROCESS(dp_clk, dp_rst)
- -- Use short index variables v_Q, v_SUB names in capitals, to ease
- -- recognizing them as (loop) indices.
- VARIABLE v_Q, v_SUB : NATURAL;
- BEGIN
- IF dp_rst = '1' THEN
- cnt <= 0;
- v_Q := 0;
- v_SUB := 0;
- ELSIF rising_edge(dp_clk) THEN
- IF in_sosi.valid = '1' THEN
- IF in_sosi.eop = '1' THEN
- v_Q := 0;
- v_SUB := 0;
- ELSE
- IF v_Q >= c_sdp_Q_fft-1 THEN
- v_Q := 0;
- IF v_SUB >= c_sdp_N_sub-1 THEN
- v_SUB := 0;
- ELSE
- v_SUB := v_SUB + 1;
- END IF;
- ELSE
- v_Q := v_Q + 1;
- END IF;
- END IF;
- cnt <= v_Q * c_sdp_N_sub + v_SUB;
- END IF;
- END IF;
- END PROCESS;
- gains_rd_address <= TO_UVEC(cnt, c_gain_addr_w);
+
+ -- Total pipeline of u_reverse_pol is:
+ -- g_pipeline_demux_in + g_pipeline_demux_out +
+ -- g_reverse_len - 1 +
+ -- g_pipeline_mux_in + g_pipeline_mux_out = 1 + 0 + 2-1 + 0 + 1 = 3
+ u_pipeline_co_pol : ENTITY dp_lib.dp_pipeline_arr
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => 3
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_raw_sosi_arr,
+ -- ST source
+ src_out_arr => in_pipe_raw_sosi_arr
+ );
+
+ -- The input subband data order is fsub[S_pn/Q_fft]_[N_sub][Q_fft] and
+ -- the [Q_fft] = [N_pol] index contains the X and Y polarizations.
+ -- Reverse the serial [N_pol] input polarizations to have the cross
+ -- polarization aligned with the co polarizations in
+ -- in_pipeline_raw_sosi_arr.
+ gen_cross_pol : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ u_cross_pol : ENTITY dp_lib.dp_reverse_n_data
+ GENERIC MAP (
+ g_pipeline_demux_in => 1, -- serial to parallel section
+ g_pipeline_demux_out => 0,
+ g_pipeline_mux_in => 0, -- parallel to serial section
+ g_pipeline_mux_out => 1,
+ g_reverse_len => c_sdp_N_pol, -- = 2
+ g_data_w => 16,
+ g_signed => TRUE
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => in_raw_sosi_arr(I),
+ src_out => in_cross_raw_sosi_arr(I)
+ );
+ END GENERATE;
-----------------------------------------------------------------------------
- -- Gain
+ -- Apply co and cross weights
-----------------------------------------------------------------------------
- u_mms_dp_gain_serial_arr : ENTITY dp_lib.mms_dp_gain_serial_arr
+ -- Total pipeline of sdp_subband_weights is: 5
+ u_sdp_subband_weigths : ENTITY work.sdp_subband_weights
GENERIC MAP (
+ g_gains_file_name => g_gains_file_name, -- for co polarization
g_nof_streams => g_nof_streams,
- g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
- g_complex_data => TRUE,
- g_complex_gain => TRUE,
- g_gain_w => c_sdp_W_sub_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name
+ g_raw_dat_w => g_raw_dat_w
)
PORT MAP (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_raw_sosi_arr,
- out_sosi_arr => weighted_raw_sosi_arr
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_raw_sosi_arr => in_pipe_raw_sosi_arr,
+ in_cross_raw_sosi_arr => in_cross_raw_sosi_arr,
+
+ weighted_raw_sosi_arr => weighted_raw_sosi_arr,
+ weighted_cross_raw_sosi_arr => weighted_cross_raw_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
+
+ ram_gains_cross_mosi => ram_gains_cross_mosi,
+ ram_gains_cross_miso => ram_gains_cross_miso
);
+ -----------------------------------------------------------------------------
+ -- Sum co + cross
+ -----------------------------------------------------------------------------
+ -- Total pipeline of u_dp_complex_add is: 1
+
+ gen_dp_complex_add : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ in_raw_sosi_2arr_2(I)(0) <= weighted_raw_sosi_arr(I);
+ in_raw_sosi_2arr_2(I)(1) <= weighted_cross_raw_sosi_arr(I);
+
+ u_dp_complex_add : ENTITY dp_lib.dp_complex_add
+ GENERIC MAP(
+ g_nof_inputs => c_sdp_N_pol,
+ g_data_w => g_raw_dat_w
+ )
+ PORT MAP(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => in_raw_sosi_2arr_2(I),
+ src_out => sum_raw_sosi_arr(I)
+ );
+ END GENERATE;
+
-----------------------------------------------------------------------------
-- Requantize
-----------------------------------------------------------------------------
+ -- Total pipeline of requantize is:
+ -- c_pipeline_remove_lsb + c_pipeline_remove_lsb = 1 + 1 = 2
+
gen_dp_requantize : FOR I IN 0 TO g_nof_streams-1 GENERATE
-- For raw output only round the c_sdp_W_sub_weight_fraction, and keep the
-- g_raw_fraction_w, so that the output width remains the same as the input
@@ -186,7 +235,7 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
-- ST sink
- snk_in => weighted_raw_sosi_arr(I),
+ snk_in => sum_raw_sosi_arr(I),
-- ST source
src_out => out_raw_sosi_arr(I)
);
@@ -211,7 +260,7 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
-- ST sink
- snk_in => weighted_raw_sosi_arr(I),
+ snk_in => sum_raw_sosi_arr(I),
-- ST source
src_out => out_quant_sosi_arr(I)
);