diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
index d239de22d488f3daf92923290539548c5a685235..39674944233af5cbf6209bccf971009d597bd083 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -105,7 +105,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
-- Tb
SIGNAL sim_done : STD_LOGIC := '0';
- SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL i_tb_end : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
SIGNAL i_QSFP_0_TX : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -142,9 +143,12 @@ BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+ tb_clk <= NOT tb_clk OR i_tb_end AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ ext_clk <= NOT ext_clk OR i_tb_end AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk OR i_tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK OR i_tb_end AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+
pps_rst <= '0' AFTER c_ext_clk_period*2;
INTA <= 'H'; -- pull up
@@ -232,8 +236,6 @@ BEGIN
------------------------------------------------------------------------------
-- MM peripeheral accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
-
p_mm_stimuli : PROCESS
BEGIN
-- Wait for DUT power up after reset
@@ -374,8 +376,9 @@ BEGIN
---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
- proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, tb_end);
+ proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, i_tb_end);
WAIT;
END PROCESS;
+ tb_end <= i_tb_end;
END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
index d5e25f46a925c27a5fd684ae70a471deda6bb66b..8b0daf1ad71c2e3f304eb59254ef14d156b03d44 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
@@ -25,6 +25,7 @@
-- Usage:
-- > as 3
-- > run -all
+-- . tb takes about 1h4m
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
index d60ed37ca75f2da0a2607b7f894c0b41f97e67f7..7402bfc69a97c4fd98dd526569744ad73546159e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
@@ -106,6 +106,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ring IS
-- Tb
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL i_tb_end : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
SIGNAL i_QSFP_0_TX : t_unb2c_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -142,10 +143,13 @@ BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
- pps_rst <= '0' AFTER c_ext_clk_period*2;
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ ext_clk <= NOT ext_clk OR i_tb_end AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk(0) <= NOT eth_clk(0) OR i_tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK OR i_tb_end AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+
+ pps_rst <= '0' AFTER c_ext_clk_period*2;
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -224,8 +228,6 @@ BEGIN
------------------------------------------------------------------------------
-- MM peripeheral accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
-
p_mm_stimuli : PROCESS
BEGIN
-- Wait for DUT power up after reset
@@ -366,8 +368,9 @@ BEGIN
---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
- proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, tb_end);
+ proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, i_tb_end);
WAIT;
END PROCESS;
+ tb_end <= i_tb_end;
END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
index 657aaf6e55d4dfbee633e5098e024bc3b280f271..989e7fdd30cecc03e18f20e4100256a369e8f7d8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
@@ -25,6 +25,7 @@
-- Usage:
-- > as 3
-- > run -all
+-- . tb takes about 1h4m
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;