From e3e65fb0f38a9086a052f320369d9e70939757ab Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Mon, 21 Aug 2023 11:21:39 +0200
Subject: [PATCH] RTSD-154: fix with vhdl_style_fix empty lines 2
---
.../libraries/sdp/src/vhdl/sdp_beamformer_local.vhd | 1 -
.../lofar2/libraries/sdp/src/vhdl/sdp_station.vhd | 1 -
.../sdp/src/vhdl/sdp_statistics_offload.vhd | 1 +
.../ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd | 1 -
.../ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd | 2 --
.../src/vhdl/node_unb1_bn_terminal_bg.vhd | 1 -
.../src/vhdl/node_unb1_fn_terminal_db.vhd | 1 -
.../tb/vhdl/tb_unb1_fn_terminal_db.vhd | 1 -
.../src/vhdl/node_unb1_terminal_bg_mesh_db.vhd | 4 ----
.../unb1_board/src/vhdl/ctrl_unb1_board.vhd | 1 -
.../src/vhdl/node_unb1_fn_terminal_db.vhd | 1 -
.../src/vhdl/unb1_board_terminals_back.vhd | 1 -
.../src/vhdl/unb1_board_terminals_mesh.vhd | 13 -------------
.../tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd | 6 ------
.../unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd | 1 -
.../designs/unb2_test/src/vhdl/unb2_test.vhd | 1 -
.../unb2_board/src/vhdl/ctrl_unb2_board.vhd | 1 -
.../unb2_board/src/vhdl/unb2_board_back_io.vhd | 1 -
.../unb2_board/src/vhdl/unb2_board_front_io.vhd | 1 -
.../unb2_board/src/vhdl/unb2_board_ring_io.vhd | 1 -
.../designs/unb2a_test/src/vhdl/unb2a_test.vhd | 1 -
.../unb2a_board/src/vhdl/unb2_board_back_io.vhd | 1 -
.../unb2a_board/src/vhdl/unb2_board_front_io.vhd | 1 -
.../unb2a_board/src/vhdl/unb2_board_ring_io.vhd | 1 -
.../designs/unb2b_test/src/vhdl/unb2b_test.vhd | 1 -
.../unb2b_board/src/vhdl/unb2b_board_back_io.vhd | 1 -
.../unb2b_board/src/vhdl/unb2b_board_front_io.vhd | 1 -
.../unb2b_board/src/vhdl/unb2b_board_ring_io.vhd | 1 -
.../designs/unb2c_test/src/vhdl/unb2c_test.vhd | 1 -
.../unb2c_board/src/vhdl/unb2c_board_back_io.vhd | 1 -
.../unb2c_board/src/vhdl/unb2c_board_front_io.vhd | 1 -
.../unb2c_board/src/vhdl/unb2c_board_ring_io.vhd | 1 -
.../common/src/vhdl/common_adder_tree_a_str.vhd | 1 -
.../base/common/src/vhdl/common_deinterleave.vhd | 1 -
.../base/common/src/vhdl/common_fanout_tree.vhd | 1 -
.../base/common/src/vhdl/common_operation_tree.vhd | 1 -
.../common/src/vhdl/common_paged_ram_crw_crw.vhd | 1 -
.../base/common/src/vhdl/common_reinterleave.vhd | 6 ------
.../base/common/src/vhdl/common_reorder_symbol.vhd | 1 -
libraries/base/common/src/vhdl/common_resize.vhd | 1 -
libraries/base/common/src/vhdl/common_round.vhd | 1 +
.../common/src/vhdl/common_transpose_symbol.vhd | 2 --
.../common/src/vhdl/common_wideband_data_scope.vhd | 1 -
libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd | 1 -
.../base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd | 1 -
.../base/diagnostics/src/vhdl/diagnostics_reg.vhd | 1 -
libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd | 1 -
libraries/base/dp/src/vhdl/dp_deinterleave.vhd | 3 ---
libraries/base/dp/src/vhdl/dp_distribute.vhd | 5 -----
libraries/base/dp/src/vhdl/dp_folder.vhd | 2 --
libraries/base/dp/src/vhdl/dp_mux.vhd | 1 -
libraries/base/dp/src/vhdl/dp_reinterleave.vhd | 4 ----
.../base/dp/src/vhdl/dp_strobe_total_count.vhd | 1 -
libraries/base/dp/src/vhdl/dp_unfolder.vhd | 2 --
.../base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd | 1 -
.../base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd | 1 -
libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd | 2 --
.../base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd | 1 -
libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd | 1 -
libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd | 2 --
.../tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd | 1 -
.../base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd | 1 -
libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd | 1 -
libraries/base/reorder/src/vhdl/reorder_row.vhd | 1 -
.../base/reorder/src/vhdl/reorder_row_select.vhd | 1 -
libraries/base/uth/src/vhdl/uth_terminal_rx.vhd | 2 --
libraries/base/uth/src/vhdl/uth_terminal_tx.vhd | 2 --
libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd | 2 --
libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd | 1 -
libraries/dsp/beamformer/src/vhdl/beamformer.vhd | 2 --
libraries/dsp/bf/src/vhdl/bf_unit.vhd | 1 -
.../dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd | 3 ---
.../dsp/correlator/src/vhdl/corr_permutator.vhd | 1 -
libraries/dsp/correlator/src/vhdl/corr_permutor.vhd | 1 -
libraries/dsp/fft/src/vhdl/fft_r2_par.vhd | 2 --
.../dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd | 1 -
libraries/dsp/iquv/src/vhdl/iquv_iab.vhd | 1 -
libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd | 5 -----
libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd | 7 -------
libraries/io/i2c/src/vhdl/i2c_byte.vhd | 1 +
libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd | 1 -
libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd | 1 -
.../technology/10gbase_r/tech_10gbase_r_arria10.vhd | 1 -
.../10gbase_r/tech_10gbase_r_arria10_e1sg.vhd | 1 -
.../10gbase_r/tech_10gbase_r_arria10_e2sg.vhd | 1 -
.../10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd | 1 -
libraries/technology/ddr/tech_ddr.vhd | 1 -
.../jesd204b/ip_arria10_e1sg_jesd204b.vhd | 1 -
.../jesd204b/ip_arria10_e2sg_jesd204b.vhd | 1 -
.../technology/transceiver/sim_transceiver_gx.vhd | 1 -
.../transceiver/tech_transceiver_gx_stratixiv.vhd | 1 -
91 files changed, 3 insertions(+), 145 deletions(-)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
index aaef9b709d..8281d80b1b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
@@ -97,7 +97,6 @@ begin
-- Use short index variables PB (= Polarization Beamlet), I (= Instance)
-- names, to ease recognizing them as loop indices.
gen_pol : for PB in 0 to c_sdp_N_pol_bf - 1 generate
-
gen_pfb : for I in 0 to c_sdp_P_pfb - 1 generate
sub_sosi_arr(PB * c_sdp_P_pfb + I) <= in_sosi_arr(I);
end generate;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 2dcd175b23..e4c4679001 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -1207,7 +1207,6 @@ begin
end generate;
gen_use_ring : if g_use_ring generate
-
gen_xst_ring : if g_use_xsub generate
u_ring_lane_xst : entity ring_lib.ring_lane
generic map (
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index f0a945c3c0..858a12ce9f 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -469,6 +469,7 @@ begin
fsub_type <= '0' when r.packet_count < c_sdp_S_pn else '1'; -- Set fsub_type = 0 for unshifted bands, '1' for shifted bands
data_id_rec.sst_signal_input_index <= r.packet_count + p.local_si_offset when r.packet_count < c_sdp_S_pn else r.packet_count - c_sdp_S_pn + p.local_si_offset;
end generate;
+
gen_no_os : if g_statistics_type /= "SST_OS" generate -- Set fsub_type to sdp_info.fsub_type when g_statistics_type is not SST_OS.
fsub_type <= sdp_info.fsub_type;
end generate;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index 52f72532c2..d13377d1b3 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -448,7 +448,6 @@ begin
RING_1_TX <= i_RING_TX(1);
gen_wire_bus : for i in 0 to c_nof_ring_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_ring_bus_w - 1 generate
i_RING_TX(i)(j) <= unb2b_board_ring_io_serial_tx_arr(i * c_ring_bus_w + j);
unb2b_board_ring_io_serial_rx_arr(i * c_ring_bus_w + j) <= i_RING_RX(i)(j);
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 49641543b1..931a44d841 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -184,7 +184,6 @@ begin
----------------------------------------------------------------------------
-- Reverse byte order
gen_reverse_rx_bytes : if g_reverse_bytes generate
-
gen_rx_bytes: for I in 0 to g_nof_bytes - 1 generate
kernel_src_out_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 - I)) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_byte_w * (I + 1) - 1 downto c_byte_w * I);
end generate;
@@ -222,7 +221,6 @@ begin
----------------------------------------------------------------------------
-- Reverse byte order to correct for endianess
gen_reverse_tx_bytes : if g_reverse_bytes generate
-
gen_tx_bytes: for I in 0 to g_nof_bytes - 1 generate
dp_latency_adapter_rx_snk_in_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 - I)) <= kernel_snk_in_arr(stream).data(c_byte_w * (I + 1) - 1 downto c_byte_w * I);
end generate;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
index 211541fc7d..f1ac60af9f 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
@@ -166,7 +166,6 @@ begin
-- Map the 16 BG streams into 4*4 streams; 4 streams for each UniBoard 3..0.
-----------------------------------------------------------------------------
gen_bg_unb : for i in 0 to c_unb1_board_nof_uniboard - 1 generate
-
gen_bg_st : for j in 0 to c_back_usr_nof_input - 1 generate
bg_siso_arr(i * c_back_usr_nof_input + j) <= bg_siso_2arr(i)(j);
bg_sosi_2arr(i)(j) <= bg_sosi_arr(i * c_back_usr_nof_input + j);
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
index 676ffca9df..f7ddc51006 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -328,7 +328,6 @@ begin
-- From 2d to 1d array
---------------------------------------------------------------------------------------
gen_i : for I in 0 to c_unb1_board_nof_bn - 1 generate
-
gen_j : for J in 0 to c_usr_nof_streams_per_bus - 1 generate
rx_rew_siso_2arr(I)(J) <= rx_usr_siso_arr(I * c_usr_nof_streams_per_bus + J);
rx_usr_sosi_arr(I * c_usr_nof_streams_per_bus + J) <= rx_rew_sosi_2arr(I)(J);
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index 77d224765c..25bd96f7d8 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -220,7 +220,6 @@ begin
-- DUTs and their MM buses
----------------------------------------------------------------------------
gen_unb : for UNB in 0 to g_unb_sys.nof_unb - 1 generate
-
gen_bn: for BN in 0 to g_unb_sys.nof_bn - 1 generate
----------------------------------------------------------------------------
-- bn_terminal_bg: MM <-> file I/O
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
index 18d22a499b..f70200f9e0 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
@@ -197,7 +197,6 @@ begin
-- From 2d to 1d array. Input port to input BG.
---------------------------------------------------------------------------------------
gen_i_a : for I in 0 to g_nof_bus - 1 generate
-
gen_j_a : for J in 0 to g_usr_nof_streams - 1 generate
bg_snk_in_arr(I * g_usr_nof_streams + J) <= tx_usr_sosi_2arr(I)(J);
tx_usr_siso_2arr(I)(J) <= bg_snk_out_arr(I * g_usr_nof_streams + J);
@@ -247,7 +246,6 @@ begin
-- From 1d to 2d array. Output BG to input Mesh
---------------------------------------------------------------------------------------
gen_i_b : for I in 0 to g_nof_bus - 1 generate
-
gen_j_b : for J in 0 to g_usr_nof_streams - 1 generate
bg_src_in_arr(I * g_usr_nof_streams + J) <= bg_out_siso_2arr(I)(J);
bg_out_sosi_2arr(I)(J) <= bg_src_out_arr(I * g_usr_nof_streams + J);
@@ -329,7 +327,6 @@ begin
-- From 2d to 1d array. Input port to input BG.
---------------------------------------------------------------------------------------
gen_i_c : for I in 0 to g_nof_bus - 1 generate
-
gen_j_c : for J in 0 to g_usr_nof_streams - 1 generate
bsn_align_snk_in_arr(I * g_usr_nof_streams + J) <= rx_usr_i_sosi_2arr(I)(J);
rx_usr_i_siso_2arr(I)(J) <= bsn_align_snk_out_arr(I * g_usr_nof_streams + J);
@@ -420,7 +417,6 @@ begin
-- From 1d to 2d array. Output BSN Aligner to port output
---------------------------------------------------------------------------------------
gen_i_d : for I in 0 to g_nof_bus - 1 generate
-
gen_j_d : for J in 0 to g_usr_nof_streams - 1 generate
bsn_align_src_in_arr(I * g_usr_nof_streams + J) <= rx_usr_siso_2arr(I)(J);
rx_usr_sosi_2arr(I)(J) <= bsn_align_src_out_arr(I * g_usr_nof_streams + J);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
index 96c632bf1f..a26175ea38 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
@@ -401,7 +401,6 @@ begin
-- for UNB1 designs with SOPC g_xo_clk_use_pll=FALSE and the the SOPC generates and outputs the mm_clk
-- for UNB1 designs with QSYS g_xo_clk_use_pll=TRUE and this ctrl_unb1_board generates and outputs the mm_clk
gen_clk25_pll: if g_xo_clk_use_pll = true generate
-
gen_sim : if g_sim = true generate
sim_mm_clk <= not sim_mm_clk after c_mmf_mm_clk_period / 2;
end generate;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
index 676ffca9df..f7ddc51006 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -328,7 +328,6 @@ begin
-- From 2d to 1d array
---------------------------------------------------------------------------------------
gen_i : for I in 0 to c_unb1_board_nof_bn - 1 generate
-
gen_j : for J in 0 to c_usr_nof_streams_per_bus - 1 generate
rx_rew_siso_2arr(I)(J) <= rx_usr_siso_arr(I * c_usr_nof_streams_per_bus + J);
rx_usr_sosi_arr(I * c_usr_nof_streams_per_bus + J) <= rx_rew_sosi_2arr(I)(J);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
index 368990aebf..d0e464d77e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
@@ -217,7 +217,6 @@ begin
-- Map 1-dim array on 2-dim array
gen_bus : for i in c_nof_bus_serial - 1 downto 0 generate
-
gen_lane : for j in g_phy_nof_serial - 1 downto 0 generate
-- SOSI
tx_phy_sosi_arr(i * g_phy_nof_serial + j) <= tx_phy_sosi_2arr(i)(j);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
index a66a8a5881..b65dc635d7 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -190,9 +190,7 @@ begin
------------------------------------------------------------------------------
mon_rx_mesh : if g_mon_select = 1 generate
-
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
-
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= rx_phy_sosi_2arr(I)(J);
end generate;
@@ -200,9 +198,7 @@ begin
end generate;
mon_rx_term_uth : if g_mon_select = 2 generate
-
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
-
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= rx_term_sosi_2arr(I)(J);
end generate;
@@ -210,9 +206,7 @@ begin
end generate;
mon_rx_term_pkt : if g_mon_select = 3 generate
-
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
-
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= mon_rx_term_pkt_sosi_2arr(I)(J);
end generate;
@@ -220,9 +214,7 @@ begin
end generate;
mon_rx_term_dist : if g_mon_select = 4 generate
-
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
-
gen_j : for J in 0 to g_usr_nof_streams - 1 generate
mon_sosi_arr(I * g_usr_nof_streams + J) <= mon_rx_term_dist_sosi_2arr(I)(J);
end generate;
@@ -230,9 +222,7 @@ begin
end generate;
mon_tx_mesh : if g_mon_select = 5 generate
-
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
-
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
end generate;
@@ -240,9 +230,7 @@ begin
end generate;
mon_tx_term_uth : if g_mon_select = 6 generate
-
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
-
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= tx_term_sosi_2arr(I)(J);
end generate;
@@ -367,7 +355,6 @@ begin
-- Map 1-dim array on 2-dim array
gen_bus : for I in g_nof_bus - 1 downto 0 generate
-
gen_lane : for J in g_phy_nof_serial - 1 downto 0 generate
-- SOSI
tx_phy_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
index 7f52cf85e4..1eaa6aa807 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -181,9 +181,7 @@ begin
------------------------------------------------------------------------------
gen_node : for I in 0 to c_nof_node-1 generate
-
gen_bus : for J in 0 to c_nof_bus - 1 generate
-
gen_lanes : for K in c_bus_w - 1 downto 0 generate
-- SOSI
-- . Transmit order
@@ -253,9 +251,7 @@ begin
-- Use tx_phy SOSI.valid stimuli for input to unb1_board_mesh_model_sl
gen_tx_serial : for I in 0 to c_nof_node-1 generate
-
gen_bus : for J in 0 to c_nof_bus - 1 generate
-
gen_lanes : for K in c_bus_w - 1 downto 0 generate
fn_tx_phy_sl_3arr(I)(J)(K) <= fn_tx_phy_sosi_3arr(I)(J)(K).valid;
bn_tx_phy_sl_3arr(I)(J)(K) <= bn_tx_phy_sosi_3arr(I)(J)(K).valid;
@@ -279,9 +275,7 @@ begin
-- Use rx_phy SOSI.valid as reference output to verify output of unb1_board_mesh_model_sl
mon_rx_serial : for I in 0 to c_nof_node-1 generate
-
gen_bus : for J in 0 to c_nof_bus - 1 generate
-
gen_lanes : for K in c_bus_w - 1 downto 0 generate
-- Monitor SOSI valids in SLV
bn_rx_phy_valid((I * c_nof_bus + J) * c_bus_w + K) <= bn_rx_phy_sosi_3arr(I)(J)(K).valid;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
index 0932726a6a..11019e63c4 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
@@ -54,7 +54,6 @@ begin
-- BN(i)(j) <= FN(j)(i)
-- FN(i)(j) <= BN(j)(i)
gen_i : for i in 0 to 3 generate
-
gen_j : for j in 0 to 3 generate
bn_rx_sl_3arr(i)(j) <= fn_tx_sl_3arr(j)(i);
fn_rx_sl_3arr(i)(j) <= bn_tx_sl_3arr(j)(i);
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 5691102521..a4e2c262f8 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -815,7 +815,6 @@ begin
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
-
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index cfc3d5a23c..8a4c6bd89a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -390,7 +390,6 @@ begin
end generate;
gen_dp_clk_hardware: if g_sim = false generate
-
gen_pll: if g_dp_clk_use_pll = true generate
u_unb2_board_clk200_pll : entity work.unb2_board_clk200_pll
generic map (
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
index b862d0f626..9210abec47 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
@@ -52,7 +52,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2_board_tr_back.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
index 612d26ad8c..1e8e9a974c 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -61,7 +61,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
index 91828b0380..b83c069659 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -47,7 +47,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2_board_tr_ring.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index 101d38d7b0..73f726f8a9 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -820,7 +820,6 @@ begin
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
-
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
index b862d0f626..9210abec47 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
@@ -52,7 +52,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2_board_tr_back.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
index 612d26ad8c..1e8e9a974c 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
@@ -61,7 +61,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
index 91828b0380..b83c069659 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
@@ -47,7 +47,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2_board_tr_ring.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index 5d37e055a1..5886a9aef1 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -814,7 +814,6 @@ begin
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
-
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
index b3a8a15564..4054420d21 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
@@ -52,7 +52,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2b_board_tr_back.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2b_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
index d02c042248..8eaa8e52bc 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
@@ -61,7 +61,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2b_board_tr_qsfp.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j);
serial_rx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
index 0e410c9e93..4d89b79a08 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
@@ -47,7 +47,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2b_board_tr_ring.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2b_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index d9d434a640..bed4ac8d3e 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -1157,7 +1157,6 @@ begin
end generate;
gen_back_wiring : if c_use_10GbE_back0 = true generate
-
gen_back0_wires: for i in 0 to c_nof_streams_back0 - 1 generate
serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
index f288657a77..f50eaf95d2 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
@@ -48,7 +48,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2c_board_tr_back.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2c_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
index ed72bac6c2..ca19220a75 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
@@ -59,7 +59,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2c_board_tr_qsfp.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j);
serial_rx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
index 088aa1bbe3..1ae3b3d7e6 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
@@ -47,7 +47,6 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
-
gen_wire_signals : for j in 0 to c_unb2c_board_tr_ring.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2c_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
index 3bac355787..579de011dc 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
@@ -89,7 +89,6 @@ begin
-- Adder tree
gen_stage : for j in 0 to c_nof_stages - 1 generate
-
gen_add : for i in 0 to (c_N + (2**j) - 1) / (2**(j + 1)) - 1 generate
u_addj : entity work.common_add_sub
generic map (
diff --git a/libraries/base/common/src/vhdl/common_deinterleave.vhd b/libraries/base/common/src/vhdl/common_deinterleave.vhd
index 8c3f4c44ed..50f2901035 100644
--- a/libraries/base/common/src/vhdl/common_deinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_deinterleave.vhd
@@ -129,7 +129,6 @@ begin
-- Align the output streams by adding pipeline stages
-----------------------------------------------------------------------------
gen_align_out: if g_align_out = true generate
-
gen_inter: for i in 0 to g_nof_out - 1 generate
u_shiftreg : entity work.common_shiftreg
generic map (
diff --git a/libraries/base/common/src/vhdl/common_fanout_tree.vhd b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
index b94ec116b6..d0dcc9ba25 100644
--- a/libraries/base/common/src/vhdl/common_fanout_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
@@ -120,7 +120,6 @@ begin
-- Fanout tree
gen_stage : for j in 0 to g_nof_stages - 1 generate
-
gen_cell : for i in 0 to g_nof_output_per_cell**j - 1 generate
-- output k =
u_fanout : entity work.common_fanout
diff --git a/libraries/base/common/src/vhdl/common_operation_tree.vhd b/libraries/base/common/src/vhdl/common_operation_tree.vhd
index 7199a5b7ff..0ad7a72e6a 100644
--- a/libraries/base/common/src/vhdl/common_operation_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_operation_tree.vhd
@@ -81,7 +81,6 @@ begin
-- Adder tree
gen_stage : for j in 0 to c_nof_stages - 1 generate
-
gen_oper : for i in 0 to (c_N + (2**j) - 1) / (2**(j + 1)) - 1 generate
u_operj : entity work.common_operation
generic map (
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index 0e5492a237..4bc889b7fe 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -220,7 +220,6 @@ begin
end process;
gen_mux : if g_str = "use_mux" generate
-
gen_pages : for I in 0 to g_nof_pages - 1 generate
u_ram : entity work.common_ram_crw_crw
generic map (
diff --git a/libraries/base/common/src/vhdl/common_reinterleave.vhd b/libraries/base/common/src/vhdl/common_reinterleave.vhd
index c9f708c09f..af7766e68e 100644
--- a/libraries/base/common/src/vhdl/common_reinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_reinterleave.vhd
@@ -164,9 +164,7 @@ begin
-- Use the entity outputs if no interleavers are instantiated.
-----------------------------------------------------------------------------
gen_wire_deint_out: if c_deinterleave_only = false generate
-
gen_wires_deint : for i in 0 to c_nof_deint - 1 generate
-
gen_deint_out : for j in 0 to c_nof_deint_out - 1 generate
deint_out_dat_2arr(i)(j) <= deint_out_concat_dat_arr(i)(j * g_dat_w + g_dat_w - 1 downto j * g_dat_w);
deint_out_val_2arr(i)(j) <= deint_out_concat_val_arr(i)(j);
@@ -183,9 +181,7 @@ begin
-- Deinterleavers -> Interleavers interconnections
-----------------------------------------------------------------------------
gen_interconnect: if c_deinterleave_only = false and c_interleave_only = false generate
-
gen_wires_deint : for i in 0 to c_nof_deint - 1 generate
-
gen_deint_out : for j in 0 to c_nof_deint_out - 1 generate
inter_in_dat_2arr(j)(i) <= deint_out_dat_2arr(i)(j);
inter_in_val_2arr(j)(i) <= deint_out_val_2arr(i)(j);
@@ -199,9 +195,7 @@ begin
-- Use the entity inputs if no deinterleavers are instantiated.
-----------------------------------------------------------------------------
gen_wire_inter_arr: if c_interleave_only = false generate
-
gen_nof_inter : for i in 0 to c_nof_inter - 1 generate
-
gen_inter_in : for j in 0 to c_nof_inter_in - 1 generate
inter_in_concat_dat_arr(i)(j * g_dat_w + g_dat_w - 1 downto j * g_dat_w) <= inter_in_dat_2arr(i)(j);
inter_in_concat_val_arr(i)(j) <= inter_in_val_2arr(i)(j);
diff --git a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
index e5ccafa394..a3bcf0c3c6 100644
--- a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
@@ -190,7 +190,6 @@ begin
-- stage I=1:c_N
gen_stage : for I in 1 to c_N generate
-
gen_row : for J in 0 to c_N generate
-- generate the 2-input reorder cells for each stage
gen_reorder2 : if func_common_reorder2_is_there(I, J) generate
diff --git a/libraries/base/common/src/vhdl/common_resize.vhd b/libraries/base/common/src/vhdl/common_resize.vhd
index 18c69a7689..04ae5e8e6d 100644
--- a/libraries/base/common/src/vhdl/common_resize.vhd
+++ b/libraries/base/common/src/vhdl/common_resize.vhd
@@ -98,7 +98,6 @@ begin
end generate;
gen_clip : if c_clip = true generate
-
gen_s_clip : if g_representation = "SIGNED" generate
clip <= '1' when signed(reg_dat) > c_smax or signed(reg_dat) < c_smin else '0';
sign <= reg_dat(reg_dat'high);
diff --git a/libraries/base/common/src/vhdl/common_round.vhd b/libraries/base/common/src/vhdl/common_round.vhd
index 9c0f229b79..6f7aae19d2 100644
--- a/libraries/base/common/src/vhdl/common_round.vhd
+++ b/libraries/base/common/src/vhdl/common_round.vhd
@@ -93,6 +93,7 @@ begin
gen_u : if c_remove_w > 0 and g_round = true and g_representation = "UNSIGNED" generate
res_dat <= u_round(reg_dat, c_remove_w, g_round_clip, g_round_even);
end generate;
+
-- . truncating
gen_t : if c_remove_w > 0 and g_round = false generate
res_dat <= truncate(reg_dat, c_remove_w);
diff --git a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
index faf6c8ceab..bd6fc252d0 100644
--- a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
@@ -83,9 +83,7 @@ begin
end generate;
gen_transpose : if g_nof_data > 1 generate
-
gen_data : for I in g_nof_data - 1 downto 0 generate
-
gen_symbols : for J in c_nof_symbols - 1 downto 0 generate
-- map input vector to 2arr
in_symbol_2arr(I)(J) <= in_data((J + 1) * c_symbol_w + I * g_data_w - 1 downto J * c_symbol_w + I * g_data_w);
diff --git a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
index 9c387e5d2e..4327b27652 100644
--- a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
+++ b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
@@ -67,7 +67,6 @@ architecture beh of common_wideband_data_scope is
signal scope_dat : std_logic_vector(g_dat_w - 1 downto 0);
begin
sim_only : if g_sim = true generate
-
use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
end generate;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index dbd4111aec..60095ffc8c 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -229,7 +229,6 @@ begin
);
gen_streams : for I in 0 to g_nof_streams - 1 generate
-
no_buffer_ram : if g_use_bg_buffer_ram = false generate
ram_bg_data_miso_arr(I) <= c_mem_miso_rst;
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
index 6205b58112..f18f50f775 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
@@ -238,7 +238,6 @@ begin
end generate;
gen_user_fifo : if c_use_user_fifo = true generate
-
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_user_fifo : entity dp_lib.dp_fifo_sc
generic map (
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
index c5edd26f91..6fd9e3ac98 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
@@ -102,7 +102,6 @@ begin
end generate;
gen_one_clk : if g_separate_clk = false generate
-
gen_nof_streams : for i in 0 to g_nof_streams - 1 generate
i_src_clk(i) <= st_clk;
i_src_rst(i) <= st_rst;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index b2b0a1640b..9042f050f7 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -431,7 +431,6 @@ begin
------------------------------------------------------------------------------
gen_streaming_output : if not g_use_mm_output generate
-
gen_mm_to_dp : for I in 0 to g_nof_streams - 1 generate
u_mm_to_dp: entity work.dp_block_from_mm
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
index 9a7ddc82f1..e652bad0f3 100644
--- a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
@@ -105,7 +105,6 @@ begin
-- Use complex fields if required
-----------------------------------------------------------------------------
gen_wires_out : for i in 0 to g_nof_out - 1 generate
-
gen_sosi_dat_out: if g_use_complex = false generate
common_deinterleave_src_out_arr(i).data(g_dat_w - 1 downto 0) <= common_deinterleave_out_dat( i * g_dat_w + g_dat_w - 1 downto i * g_dat_w);
end generate;
@@ -122,7 +121,6 @@ begin
-- Add SOP and EOP to the outputs
-----------------------------------------------------------------------------
gen_ctrl : if g_use_ctrl = true generate
-
gen_dp_block_gen : for i in 0 to g_nof_out - 1 generate
u_dp_block_gen : entity work.dp_block_gen
generic map (
@@ -149,7 +147,6 @@ begin
-- Re-add input sync + BSN to all output streams
-----------------------------------------------------------------------------
align_out : if g_use_sync_bsn = true generate
-
gen_dp_fifo_info: for i in 0 to g_nof_out - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_distribute.vhd b/libraries/base/dp/src/vhdl/dp_distribute.vhd
index dea7dc87d6..4165fd6370 100644
--- a/libraries/base/dp/src/vhdl/dp_distribute.vhd
+++ b/libraries/base/dp/src/vhdl/dp_distribute.vhd
@@ -155,7 +155,6 @@ begin
end generate;
gen_fifo : if g_use_fifo = true generate
-
gen_input : for I in 0 to g_nof_input - 1 generate
u_fifo : entity work.dp_fifo_fill
generic map (
@@ -194,7 +193,6 @@ begin
end generate;
gen_dec : if g_decode_channel_lo = true generate
-
gen_i : for I in 0 to g_nof_input - 1 generate
u_dec : entity work.dp_packet_dec_channel_lo
generic map (
@@ -220,7 +218,6 @@ begin
end generate;
gen_transpose : if g_nof_input /= g_nof_output or g_transpose = true generate
-
gen_demux : for I in 0 to g_nof_input - 1 generate
u_demux : entity work.dp_demux
generic map (
@@ -243,7 +240,6 @@ begin
-- Rewire to distribute
gen_in : for I in 0 to g_nof_input - 1 generate
-
gen_out : for J in 0 to g_nof_output - 1 generate
demux_siso_2arr(I)(J) <= mux_siso_2arr(J)(I);
mux_sosi_2arr(J)(I) <= demux_sosi_2arr(I)(J);
@@ -281,7 +277,6 @@ begin
end generate;
gen_enc : if g_encode_channel_lo = true generate
-
gen_j : for J in 0 to g_nof_output - 1 generate
u_enc : entity work.dp_packet_enc_channel_lo
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_folder.vhd b/libraries/base/dp/src/vhdl/dp_folder.vhd
index 87097cb1b4..7b49530966 100644
--- a/libraries/base/dp/src/vhdl/dp_folder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_folder.vhd
@@ -189,7 +189,6 @@ begin
-- Add SOP and EOP to the outputs
-----------------------------------------------------------------------------
gen_ctrl : if g_output_block_size > 0 generate
-
gen_dp_block_gen : for i in 0 to c_nof_muxes - 1 generate
u_dp_block_gen : entity work.dp_block_gen
generic map (
@@ -217,7 +216,6 @@ begin
-- Re-add input sync + BSN to all output streams
-----------------------------------------------------------------------------
gen_sync_bsn : if g_fwd_sync_bsn = true generate
-
gen_dp_fifo_info: for i in 0 to c_nof_muxes - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index 93ad6c17e8..9e15141bf0 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -209,7 +209,6 @@ begin
end process;
gen_input : for I in 0 to g_nof_input - 1 generate
-
gen_fifo : if g_use_fifo = true generate
u_fill : entity work.dp_fifo_fill
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
index 1c0b4204f0..d0f65d7299 100644
--- a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
@@ -89,7 +89,6 @@ begin
-- Map input sosi_arr to SLV
-----------------------------------------------------------------------------
gen_wires_in : for i in 0 to g_nof_in - 1 generate
-
gen_sosi_dat_in: if g_use_complex = false generate
-----------------------------------------------------------------------------
-- Forward SOSI data field
@@ -131,7 +130,6 @@ begin
-- Map output SLV to sosi_arr
-----------------------------------------------------------------------------
gen_wires_out : for i in 0 to g_nof_out - 1 generate
-
gen_sosi_dat_out: if g_use_complex = false generate
-----------------------------------------------------------------------------
-- Forward SOSI data field
@@ -154,7 +152,6 @@ begin
-- Add SOP and EOP to the outputs
-----------------------------------------------------------------------------
gen_ctrl : if g_use_ctrl = true generate
-
gen_dp_block_gen : for i in 0 to g_nof_out - 1 generate
u_dp_block_gen : entity work.dp_block_gen
generic map (
@@ -181,7 +178,6 @@ begin
-- Re-add input sync + BSN to all output streams
-----------------------------------------------------------------------------
align_out : if g_use_sync_bsn = true generate
-
gen_dp_fifo_info: for i in 0 to g_nof_out - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 76c0b90aa5..82eb03aa00 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -229,7 +229,6 @@ begin
-- Register mapping
gen_cnt : for I in 0 to g_nof_counts - 1 generate
-
gen_reg_32b : if g_count_w <= g_mm_w generate
rd_reg((2 * I + 1) * g_mm_w - 1 downto (2 * I + 0) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I), g_mm_w); -- low part
rd_reg((2 * I + 2) * g_mm_w - 1 downto (2 * I + 1) * g_mm_w) <= (others => '0'); -- high part (not used)
diff --git a/libraries/base/dp/src/vhdl/dp_unfolder.vhd b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
index d0811413ed..3df7cc4c18 100644
--- a/libraries/base/dp/src/vhdl/dp_unfolder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
@@ -201,7 +201,6 @@ begin
-- Add SOP and EOP to the outputs
-----------------------------------------------------------------------------
gen_ctrl : if g_output_block_size > 0 generate
-
gen_dp_block_gen : for i in 0 to c_nof_outputs - 1 generate
u_dp_block_gen : entity work.dp_block_gen
generic map (
@@ -229,7 +228,6 @@ begin
-- Re-add input sync + BSN to all output streams
-----------------------------------------------------------------------------
gen_sync_bsn : if g_fwd_sync_bsn = true generate
-
gen_dp_fifo_info: for i in 0 to c_nof_outputs - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
index e25f692777..a12132a9ea 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
@@ -83,7 +83,6 @@ architecture beh of dp_wideband_sp_arr_scope is
signal st_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
begin
sim_only : if g_sim = true generate
-
use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
end generate;
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
index 772f4a5ce0..fcedf58750 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
@@ -73,7 +73,6 @@ architecture beh of dp_wideband_wb_arr_scope is
signal st_sosi : t_dp_sosi;
begin
sim_only : if g_sim = true generate
-
use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
end generate;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
index 3c8d7025a9..f6915b5ef6 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
@@ -158,7 +158,6 @@ begin
);
gen_real_multiply : if c_real_multiply = true generate
-
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_common_mult : entity common_mult_lib.common_mult
generic map (
@@ -205,7 +204,6 @@ begin
end generate gen_real_multiply;
gen_complex_multiply : if c_real_multiply = false generate
-
gen_complex_gain : if g_complex_gain = true generate
u_common_reg_r_w_dc_im : entity common_lib.common_reg_r_w_dc
generic map (
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index 0131c10cf0..e81bb5a6d0 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -252,7 +252,6 @@ begin
end generate gen_real_multiply;
gen_complex_multiply : if c_real_multiply = false generate
-
gen_real_gain : if g_complex_gain = false generate
gains_re_arr(I) <= gains_rd_data_arr(I)(g_gain_w - 1 downto 0);
gains_im_arr(I) <= gains_rd_data_arr(I)(g_gain_w - 1 downto 0);
diff --git a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
index ddd9947f02..ac9ddc3c2c 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
@@ -83,7 +83,6 @@ begin
);
gen_reg : for i in 0 to c_nof_ctrl_streams - 1 generate
-
gen_no_timeout : if g_timeout_time = 0 generate
u_reg : entity work.dp_xonoff_reg
generic map(
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
index c4c0161f75..de5f5139e0 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
@@ -194,7 +194,6 @@ begin
-- Generate data path input data
gen_type : for I in 0 to c_nof_type-1 generate
-
gen_input : for J in 0 to c_nof_input - 1 generate
p_stimuli : process
constant cK : natural := I * c_nof_input + J;
@@ -228,7 +227,6 @@ begin
prev_count_eop <= count_eop when rising_edge(clk);
gen_verify : for I in 0 to c_nof_type-1 generate
-
gen_output : for J in 0 to c_nof_input - 1 generate
-- Verification logistics
verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
index 1be5bdf0b7..85bdf4243f 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -261,7 +261,6 @@ begin
-- Use FIFO to break flow control between one to N and N to one, so that stimuli see ready = '1'
use_fifo : if g_use_fifo = true generate
-
gen_fifos : for I in 0 to g_nof_streams - 1 generate
u_dp_fifo_sc : entity work.dp_fifo_sc
generic map (
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index f9c35e7c75..78ff110792 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -364,7 +364,6 @@ begin
-- Model misalignment latency between the input streams to have different
-- input BSN monitor latencies
no_lost_input : if g_lost_input = false generate
-
gen_in_sosi_arr : for I in c_nof_streams - 1 downto 0 generate
in_sosi_arr(I) <= transport ref_sosi_arr(I) after func_input_delay(I) * c_dp_clk_period;
end generate;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
index 2d03c4ac50..f61ac82582 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
@@ -69,7 +69,6 @@ begin
-------------------------------------------------------------------------
gen_bool_bypass : for K in 0 to 1 generate
-
gen_bool_bypass : for L in 0 to 1 generate
-- no repack, g_in_nof_words = g_out_nof_words = 1
u_16_1_16_1_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 16, 1, 16, 1, c_bool(K), c_bool(L), 1, 1, c_nof_repeat, 10, 0); -- g_pkt_len > g_in_nof_words
diff --git a/libraries/base/reorder/src/vhdl/reorder_row.vhd b/libraries/base/reorder/src/vhdl/reorder_row.vhd
index dc638d860b..b02b86889f 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row.vhd
@@ -119,7 +119,6 @@ begin
-- selection buffer.
---------------------------------------------------------------
gen_input : for I in g_nof_inputs - 1 downto 0 generate
-
use_complex : if g_use_complex generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
r.pipe_sosi_2arr(0)(I).im(g_dsp_data_w - 1 downto 0) &
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index b3a0873aaa..429639223a 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -83,7 +83,6 @@ begin
-- selection buffer.
---------------------------------------------------------------
gen_input : for I in g_nof_inputs - 1 downto 0 generate
-
use_complex : if g_use_complex generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
input_sosi_arr(I).im(g_dsp_data_w - 1 downto 0) &
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
index b579e31de4..e31b474623 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
@@ -121,7 +121,6 @@ begin
end generate;
gen_input_fifo : for I in g_nof_input - 1 downto 0 generate
-
gen_fifo : if g_input_use_fifo = true generate
-- Input FIFO passes DP/Uthernet packets, so the sosi control fields (sync, bsn, empty, channel and error) are encoded in the packet data
u_fifo_fill : entity dp_lib.dp_fifo_fill
@@ -215,7 +214,6 @@ begin
end generate;
gen_output_fifo : for I in g_nof_output - 1 downto 0 generate
-
gen_fifo : if g_output_use_fifo = true generate
-- Output FIFO passes DP packets, so the sosi control fields (sync, bsn, empty, channel and error) are encoded in the packet data.
-- However if g_use_uth_err=TRUE then the Uthernet CRC error status is passed on via the sosi error field using 1 bit.
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
index fd93ab5060..9b177da33e 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
@@ -132,7 +132,6 @@ begin
end generate;
gen_input_fifo : for I in g_nof_input - 1 downto 0 generate
-
gen_fifo : if g_input_use_fifo = true generate
u_fifo_fill : entity dp_lib.dp_fifo_fill
generic map (
@@ -247,7 +246,6 @@ begin
end generate;
gen_output_fifo : for I in g_nof_output - 1 downto 0 generate
-
gen_fifo : if g_output_use_fifo = true generate
-- Output FIFO passes DP/Uthernet packets, so the sosi control fields (sync, bsn, empty, channel and error) are encoded in the packet data
u_fifo_fill : entity dp_lib.dp_fifo_fill
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
index e939f36899..7ad85b075d 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
@@ -241,7 +241,6 @@ begin
-- Generate data path input data
gen_tlen : for I in 0 to c_nof_tlen - 1 generate
-
gen_input : for J in 0 to c_nof_input - 1 generate
p_stimuli : process
constant c_pkt_data_len : natural := c_len_arr(I) - c_pkt_overhead_len;
@@ -292,7 +291,6 @@ begin
prev_count_eop <= count_eop when rising_edge(clk);
gen_verify : for I in 0 to c_nof_tlen - 1 generate
-
gen_output : for J in 0 to c_nof_input - 1 generate
-- Verification logistics
verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
index 7bfc0b30a3..3c5cf552cd 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
@@ -316,7 +316,6 @@ begin
end generate;
gen_phy_fifo : if g_phy_fifo_size > 0 generate
-
gen_nof_serial : for I in 0 to g_nof_serial - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
diff --git a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
index 22571f10ce..25a30b681c 100644
--- a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
+++ b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
@@ -134,7 +134,6 @@ begin
-- Weights RAM
------------------------------------------------------------------------------
gen_weight_ram : if g_use_weight_ram = true generate
-
gen_common_ram_crw_crw : for i in 0 to g_nof_inputs - 1 generate
-- Read request on every incoming valid cycle
common_ram_crw_crw_rd_en_b_arr(i) <= snk_in_arr(i).valid;
@@ -181,7 +180,6 @@ begin
-- Weights register
------------------------------------------------------------------------------
gen_weight_reg : if g_use_weight_reg = true generate
-
gen_common_reg_r_w_dc : for i in 0 to g_nof_inputs - 1 generate
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
generic map (
diff --git a/libraries/dsp/bf/src/vhdl/bf_unit.vhd b/libraries/dsp/bf/src/vhdl/bf_unit.vhd
index 0cb5b01899..73d202ae11 100644
--- a/libraries/dsp/bf/src/vhdl/bf_unit.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf_unit.vhd
@@ -209,7 +209,6 @@ begin
-- A set of ss_wide units is used to distribute the incoming subbands to the data-inputs of the
-- beamformer multipliers.
gen_ss_wide : for I in 0 to g_bf.nof_input_streams - 1 generate
-
gen_copy_input : for J in 0 to c_nof_signal_paths_per_stream - 1 generate
ss_wide_in_sosi_arr(I * c_nof_signal_paths_per_stream + J) <= in_sosi_arr(I);
end generate;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd b/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
index 58a94fe3df..0c96de2937 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
@@ -89,7 +89,6 @@ begin
-- 3) [0][1][2][3] -> pipeline -> [0] [1] [2] [3]
-----------------------------------------------------------------------------
gen_dp_pipeline_src_out_2arr2 : for i in 0 to g_nof_inputs - 1 generate
-
gen_dp_pipeline : for j in 0 to 2 - 1 generate
u_dp_pipeline : entity dp_lib.dp_pipeline
generic map (
@@ -109,7 +108,6 @@ begin
-- Folder input: tranposed pipeline output
------------------------------------------------------------------------------
gen_input_i : for i in 0 to g_nof_inputs - 1 generate
-
gen_input_j : for j in 0 to 2 - 1 generate
corr_folder_snk_in_2arr(j)(i) <= dp_pipeline_src_out_2arr_2(i)(j);
end generate;
@@ -138,7 +136,6 @@ begin
-- Entity output: tranposed folder output
------------------------------------------------------------------------------
gen_output_i : for i in 0 to c_nof_outputs - 1 generate
-
gen_output_j : for j in 0 to 2 - 1 generate
src_out_2arr_2(i)(j) <= corr_folder_src_out_2arr(j)(i);
end generate;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
index 0505d66d44..376b3babdd 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
@@ -73,7 +73,6 @@ begin
-- . Wire via input buffer if we need to serialize the output permutations
-----------------------------------------------------------------------------
gen_input: for i in 0 to g_nof_inputs - 1 generate
-
gen_input: for j in 0 to g_nof_inputs - 1 generate
permu_in_2arr(i)(j) <= reg_snk_in_arr(i);
end generate;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
index 5bfd1fe3b6..9289aa4847 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
@@ -80,7 +80,6 @@ begin
-- cycles while the process p_permute puts the input data on the outputs.
-----------------------------------------------------------------------------
gen_common_paged_reg : if g_nof_cycles > 1 generate
-
gen_common_paged_reg_i : for i in 0 to g_nof_inputs - 1 generate
common_paged_reg_wr_re_arr(i) <= snk_in_arr(i).re(g_data_w - 1 downto 0);
common_paged_reg_wr_im_arr(i) <= snk_in_arr(i).im(g_data_w - 1 downto 0);
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
index d9bb965b62..622cd822b8 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
@@ -175,7 +175,6 @@ begin
-- parallel FFT stages
------------------------------------------------------------------------------
gen_fft_stages: for stage in c_nof_stages downto 1 generate
-
gen_fft_elements: for element in 0 to c_nof_bf_per_stage-1 generate
u_element : entity work.fft_r2_bf_par
generic map (
@@ -365,7 +364,6 @@ begin
end generate;
no_separate : if g_fft.use_separate = false generate
-
assign_outputs : for I in 0 to g_fft.nof_points - 1 generate
-- c_raw_dat_w = g_fft.stage_dat_w, because g_fft.use_separate=false
fft_re_arr(I) <= int_re_arr(I);
diff --git a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
index afd5aae347..36d0e53f0d 100644
--- a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
@@ -126,7 +126,6 @@ begin
adr_fft_shift <= fft_shift(adr_fft_flip); -- invert MSbit for fft_shift
gen_complex : if g_separate = false generate
-
no_bit_flip : if g_bit_flip = false generate
wr_adr <= adr_tot_cnt;
end generate;
diff --git a/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd b/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
index 3235efb662..5c60653c13 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
@@ -580,7 +580,6 @@ begin
-- Diagnostic to display the I signal flow in simulation
-------------------------------------------------------------------------------
gen_diag : if g_sim = true generate
-
gen_diag_inputs : for stream in 0 to g_nof_streams - 1 generate
diag_in_complex_arr(stream * 2) <= in_complex_arr(stream).re(g_in_data_w - 1 downto 0);
diag_in_complex_arr(stream * 2 + 1) <= in_complex_arr(stream).im(g_in_data_w - 1 downto 0);
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
index 5ace9a7615..c75f7f8c99 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
@@ -196,7 +196,6 @@ begin
-- | 15 1 3 IM | |
--
gen_prep_filter_wb_factor: for I in 0 to g_wpfb.wb_factor - 1 generate
-
gen_prep_filter_streams: for J in 0 to g_wpfb.nof_wb_streams - 1 generate
fil_in_arr(2 * J + I * g_wpfb.nof_wb_streams * c_nof_complex) <= RESIZE_SVEC(r.in_sosi_arr(I + J * g_wpfb.wb_factor).re(g_wpfb.fil_in_dat_w - 1 downto 0), fil_in_arr(0)'length);
fil_in_arr(2 * J + I * g_wpfb.nof_wb_streams * c_nof_complex + 1) <= RESIZE_SVEC(r.in_sosi_arr(I + J * g_wpfb.wb_factor).im(g_wpfb.fil_in_dat_w - 1 downto 0), fil_in_arr(0)'length);
@@ -244,7 +243,6 @@ begin
---------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
gen_prep_fft_streams: for I in 0 to g_wpfb.nof_wb_streams - 1 generate
-
gen_prep_fft_wb_factor: for J in 0 to g_wpfb.wb_factor - 1 generate
fft_in_re_arr(I * g_wpfb.wb_factor + J) <= fil_out_arr(J * c_nof_complex * g_wpfb.nof_wb_streams + I * c_nof_complex);
fft_in_im_arr(I * g_wpfb.wb_factor + J) <= fil_out_arr(J * c_nof_complex * g_wpfb.nof_wb_streams + I * c_nof_complex + 1);
@@ -365,9 +363,7 @@ begin
-- for multiplication, the incoming data cannot be wider
-- than 18 bit.
gen_stats : if g_stats_ena = true generate
-
gen_stats_streams: for I in 0 to g_wpfb.nof_wb_streams - 1 generate
-
gen_stats_wb_factor: for J in 0 to g_wpfb.wb_factor - 1 generate
u_subband_stats : entity st_lib.st_sst
generic map(
@@ -391,7 +387,6 @@ begin
-- Connect to the outside world
gen_output_streams: for I in 0 to g_wpfb.nof_wb_streams - 1 generate
-
gen_output_wb_factor : for J in 0 to g_wpfb.wb_factor - 1 generate
out_sosi_arr(I * g_wpfb.wb_factor + J) <= fft_out_sosi_arr(I * g_wpfb.wb_factor + J);
end generate;
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index dfacbd13ea..3385973b52 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -502,7 +502,6 @@ begin
-- Wire in_sosi_arr --> fil_in_arr
wire_fil_in_wideband: for P in 0 to g_wpfb.wb_factor - 1 generate
-
wire_fil_in_streams: for S in 0 to g_wpfb.nof_wb_streams - 1 generate
fil_in_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex) <= RESIZE_SVEC_32(r.in_sosi_arr(S * g_wpfb.wb_factor + P).re(g_wpfb.fil_in_dat_w - 1 downto 0));
fil_in_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex + 1) <= RESIZE_SVEC_32(r.in_sosi_arr(S * g_wpfb.wb_factor + P).im(g_wpfb.fil_in_dat_w - 1 downto 0));
@@ -512,7 +511,6 @@ begin
-- Wire fil_out_arr --> fil_sosi_arr
wire_fil_sosi_streams: for S in 0 to g_wpfb.nof_wb_streams - 1 generate
-
wire_fil_sosi_wideband: for P in 0 to g_wpfb.wb_factor - 1 generate
fil_sosi_arr(S * g_wpfb.wb_factor + P).valid <= fil_out_val;
fil_sosi_arr(S * g_wpfb.wb_factor + P).re <= RESIZE_DP_DSP_DATA(fil_out_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex ));
@@ -522,7 +520,6 @@ begin
-- Wire fil_out_arr --> fft_in_re_arr, fft_in_im_arr
wire_fft_in_streams: for S in 0 to g_wpfb.nof_wb_streams - 1 generate
-
wire_fft_in_wideband: for P in 0 to g_wpfb.wb_factor - 1 generate
fft_in_re_arr(S * g_wpfb.wb_factor + P) <= fil_out_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex);
fft_in_im_arr(S * g_wpfb.wb_factor + P) <= fil_out_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex + 1);
@@ -567,7 +564,6 @@ begin
-- THE WIDEBAND FFT
---------------------------------------------------------------
gen_wideband_fft: if g_wpfb.wb_factor > 1 generate
-
gen_fft_r2_wide_streams: for S in 0 to g_wpfb.nof_wb_streams - 1 generate
u_fft_r2_wide : entity fft_lib.fft_r2_wide
generic map(
@@ -592,7 +588,6 @@ begin
-- THE PIPELINED FFT
---------------------------------------------------------------
gen_pipeline_fft: if g_wpfb.wb_factor = 1 generate
-
gen_fft_r2_pipe_streams: for S in 0 to g_wpfb.nof_wb_streams - 1 generate
u_fft_r2_pipe : entity fft_lib.fft_r2_pipe
generic map(
@@ -702,9 +697,7 @@ begin
-- for multiplication, the incoming data cannot be wider
-- than 18 bit.
gen_stats : if g_stats_ena = true generate
-
gen_stats_streams: for S in 0 to g_wpfb.nof_wb_streams - 1 generate
-
gen_stats_wideband: for P in 0 to g_wpfb.wb_factor - 1 generate
u_subband_stats : entity st_lib.st_sst
generic map(
diff --git a/libraries/io/i2c/src/vhdl/i2c_byte.vhd b/libraries/io/i2c/src/vhdl/i2c_byte.vhd
index 81747d7fe1..1460a8c272 100644
--- a/libraries/io/i2c/src/vhdl/i2c_byte.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_byte.vhd
@@ -246,6 +246,7 @@ begin
sda_oen => sda_oen
);
end generate;
+
i2c_al <= al;
-- generate host-command-acknowledge
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index 608150105b..85c4d7da12 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -239,7 +239,6 @@ begin
-- TX FIFO for buffering last packet when xon = 0 to prevent corrupt frames.
---------------------------------------------------------------------------------------
gen_xon_backpressure : if g_xon_backpressure generate
-
gen_dp_fifo_sc_tx : for i in 0 to g_nof_macs - 1 generate
u_dp_fifo_sc_tx : entity dp_lib.dp_fifo_sc
generic map (
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
index c977a11acc..b93a840b06 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
@@ -158,7 +158,6 @@ begin
-- SOSI-XGMII user interface
-----------------------------------------------------------------------------
gen_sosi_io: if g_use_xgmii = false generate
-
gen_nof_user : for i in g_nof_xaui - 1 downto 0 generate
xgmii_tx_dc_in_arr(i) <= func_xgmii_dc(xgmii_tx_d_arr(i), xgmii_tx_c_arr(i));
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
index 80dd7a5a55..f106ec2d00 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
@@ -134,7 +134,6 @@ begin
end generate;
gen_phy_1 : if c_nof_channels_per_ip = 1 generate
-
gen_channels : for I in 0 to g_nof_channels - 1 generate
u_ip_arria10_phy_10gbase_r : ip_arria10_phy_10gbase_r
port map (
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index 01084675fc..b69ecf769b 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -142,7 +142,6 @@ begin
end generate;
gen_phy_1 : if c_nof_channels_per_ip = 1 generate
-
gen_channels : for I in 0 to g_nof_channels - 1 generate
u_ip_arria10_e1sg_phy_10gbase_r : ip_arria10_e1sg_phy_10gbase_r
port map (
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
index f7bea40244..2b3c08f784 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
@@ -142,7 +142,6 @@ begin
end generate;
gen_phy_1 : if c_nof_channels_per_ip = 1 generate
-
gen_channels : for I in 0 to g_nof_channels - 1 generate
u_ip_arria10_e2sg_phy_10gbase_r : ip_arria10_e2sg_phy_10gbase_r
port map (
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
index da96eed970..6881254db1 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
@@ -141,7 +141,6 @@ begin
end generate;
gen_phy_1 : if c_nof_channels_per_ip = 1 generate
-
gen_channels : for I in 0 to g_nof_channels - 1 generate
u_ip_arria10_e3sge3_phy_10gbase_r : ip_arria10_e3sge3_phy_10gbase_r
port map (
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index cceff80992..e15ba40ef6 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -74,7 +74,6 @@ begin
-- Technology IP cores
-----------------------------------------------------------------------------
gen_ip: if g_sim_model = false generate
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : entity work.tech_ddr_stratixiv
generic map (g_tech_ddr)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index e76d7099f0..554b93b247 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -248,7 +248,6 @@ begin
end generate;
gen_jesd204b_rx : if g_direction = "RX_ONLY" generate
-
gen_jesd204b_rx_channels : for I in 0 to g_nof_streams - 1 generate
-----------------------------------------------------------------------------
-- The JESD204 IP (rx only)
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 8ab7c7a8f5..87a34d3c9c 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -248,7 +248,6 @@ begin
end generate;
gen_jesd204b_rx : if g_direction = "RX_ONLY" generate
-
gen_jesd204b_rx_channels : for I in 0 to g_nof_streams - 1 generate
-----------------------------------------------------------------------------
-- The JESD204 IP (rx only)
diff --git a/libraries/technology/transceiver/sim_transceiver_gx.vhd b/libraries/technology/transceiver/sim_transceiver_gx.vhd
index 95b54cb675..3b3671516d 100644
--- a/libraries/technology/transceiver/sim_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_gx.vhd
@@ -179,7 +179,6 @@ begin
end process;
gen_sim: for i in 0 to g_nof_gx - 1 generate
-
gen_tx : if g_tx = true generate
tx_siso_arr(i).ready <= tx_ready;
tx_siso_arr(i).xon <= tx_ready;
diff --git a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
index 9c5dbca81c..4bf74473d8 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
@@ -283,7 +283,6 @@ begin
end generate;
gen_tx : if g_tx = true and g_rx = false generate
-
gen_32b : if g_data_w = 32 generate
u_tx: ip_stratixiv_hssi_tx_32b_generic
generic map (
--
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