diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index aa0f730882561b2ac714e6e7b8d061d00d6e8536..1046f9ee81e0e3d025399dbae6ebfce54a27f948 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -70,7 +70,6 @@ ENTITY ip_arria10_e1sg_jesd204b IS
);
END ip_arria10_e1sg_jesd204b;
-
ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
-- JESD IP constants
@@ -83,7 +82,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
-- JESD204 control status registers
SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
@@ -131,11 +130,9 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-
-- Component declarations for the IP blocks
-
- component ip_arria10_e1sg_jesd204b_rx_200MHz is
+ component ip_arria10_e1sg_jesd204b_rx_200MHz is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
@@ -233,8 +230,6 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
);
end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
-
-
BEGIN
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e1sg_jesd204b and causes a reset on the rx_rst output.
@@ -252,7 +247,6 @@ BEGIN
jesd204b_avs_clk <= mm_clk;
END GENERATE;
-
gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
@@ -260,10 +254,9 @@ BEGIN
-- The JESD204 IP (rx only)
-----------------------------------------------------------------------------
- gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
- u_ip_arria10_e1sg_jesd204b_rx_200MHz : ip_arria10_e1sg_jesd204b_rx_200MHz
- PORT MAP
- (
+ gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
+ u_ip_arria10_e1sg_jesd204b_rx_200MHz : ip_arria10_e1sg_jesd204b_rx_200MHz
+ PORT MAP (
alldev_lane_aligned => dev_lane_aligned_arr(i),
csr_cf => OPEN,
csr_cs => OPEN,
@@ -311,6 +304,9 @@ BEGIN
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
sysref => jesd204b_sysref_2
);
+
+ -- One cycle rd-rdval latency, waitrequest = '0' fixed
+ jesd204b_miso_arr(i).rdval <= jesd204b_mosi_arr(i).rd WHEN rising_edge(jesd204b_avs_clk);
END GENERATE;
-----------------------------------------------------------------------------
@@ -365,7 +361,6 @@ BEGIN
out_rst => rxframe_rst_arr(i)
);
-
rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
-- synchronize rx_xcvr_ready_in_arr to mm_clk
u_common_async_rx_xcvr_ready : ENTITY common_lib.common_async
@@ -384,7 +379,6 @@ BEGIN
rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
-
-----------------------------------------------------------------------------
-- Minimal deframer (transport layer)
-----------------------------------------------------------------------------
@@ -415,7 +409,7 @@ BEGIN
END IF;
END PROCESS;
- END GENERATE;
+ END GENERATE; -- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
-----------------------------------------------------------------------------
-- Reclock sysref and the sync_n output
@@ -459,7 +453,6 @@ BEGIN
END IF;
END PROCESS;
-
-- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
gen_jesd204b_rx_corepll_freqsel : IF g_jesd_freq = "200MHz" GENERATE
u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz : ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz
@@ -483,7 +476,6 @@ BEGIN
out_rst => mm_core_pll_locked_reg
);
-
-- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
-- Clock set to 100MHz (use rxlink_clk)
@@ -498,24 +490,23 @@ BEGIN
rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
);
- END GENERATE;
+ END GENERATE; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_enable_sync_n : FOR i IN 0 TO g_nof_streams-1 GENERATE
- -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
- -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
- -- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
- -- the sync_n_combined to become unavailable (see gen_group_sync_n).
-
+ -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
+ -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
+ -- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
+ -- the sync_n_combined to become unavailable (see gen_group_sync_n).
- -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
- jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
+ -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
+ jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
END GENERATE;
-----------------------------------------------------------------------------
-- Group the SYNC_N outputs
-----------------------------------------------------------------------------
gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
- jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
+ jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
END GENERATE;
-----------------------------------------------------------------------------
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index d655038811a4d4291b0852d51c039887235629f3..e49282da0874a9ad81d443ee0b3991ff8042f242 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -70,7 +70,6 @@ ENTITY ip_arria10_e2sg_jesd204b IS
);
END ip_arria10_e2sg_jesd204b;
-
ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
-- JESD IP constants
@@ -83,7 +82,7 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
-- JESD204 control status registers
SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
@@ -131,11 +130,9 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-
-- Component declarations for the IP blocks
-
- component ip_arria10_e2sg_jesd204b_rx_200MHz is
+ component ip_arria10_e2sg_jesd204b_rx_200MHz is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
@@ -233,8 +230,6 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
);
end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
-
-
BEGIN
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e2sg_jesd204b and causes a reset on the rx_rst output.
@@ -252,7 +247,6 @@ BEGIN
jesd204b_avs_clk <= mm_clk;
END GENERATE;
-
gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
@@ -260,10 +254,9 @@ BEGIN
-- The JESD204 IP (rx only)
-----------------------------------------------------------------------------
- gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
- u_ip_arria10_e2sg_jesd204b_rx_200MHz : ip_arria10_e2sg_jesd204b_rx_200MHz
- PORT MAP
- (
+ gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
+ u_ip_arria10_e2sg_jesd204b_rx_200MHz : ip_arria10_e2sg_jesd204b_rx_200MHz
+ PORT MAP (
alldev_lane_aligned => dev_lane_aligned_arr(i),
csr_cf => OPEN,
csr_cs => OPEN,
@@ -311,6 +304,9 @@ BEGIN
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
sysref => jesd204b_sysref_2
);
+
+ -- One cycle rd-rdval latency, waitrequest = '0' fixed
+ jesd204b_miso_arr(i).rdval <= jesd204b_mosi_arr(i).rd WHEN rising_edge(jesd204b_avs_clk);
END GENERATE;
-----------------------------------------------------------------------------
@@ -383,7 +379,6 @@ BEGIN
rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
-
-----------------------------------------------------------------------------
-- Minimal deframer (transport layer)
-----------------------------------------------------------------------------
@@ -414,7 +409,7 @@ BEGIN
END IF;
END PROCESS;
- END GENERATE;
+ END GENERATE; -- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
-----------------------------------------------------------------------------
-- Reclock sysref and the sync_n output
@@ -458,7 +453,6 @@ BEGIN
END IF;
END PROCESS;
-
-- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
gen_jesd204b_rx_corepll_freqsel : IF g_jesd_freq = "200MHz" GENERATE
u_ip_arria10_e2sg_jesd204b_rx_corepll_200MHz : ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz
@@ -482,7 +476,6 @@ BEGIN
out_rst => mm_core_pll_locked_reg
);
-
-- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
-- Clock set to 100MHz (use rxlink_clk)
@@ -497,24 +490,23 @@ BEGIN
rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
);
- END GENERATE;
+ END GENERATE; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_enable_sync_n : FOR i IN 0 TO g_nof_streams-1 GENERATE
- -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
- -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
- -- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
- -- the sync_n_combined to become unavailable (see gen_group_sync_n).
-
+ -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
+ -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
+ -- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
+ -- the sync_n_combined to become unavailable (see gen_group_sync_n).
- -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
- jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
+ -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
+ jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
END GENERATE;
-----------------------------------------------------------------------------
-- Group the SYNC_N outputs
-----------------------------------------------------------------------------
gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
- jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
+ jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
END GENERATE;
-----------------------------------------------------------------------------