diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index db4c1b60bc9856dd4fdd8e20b3991c3acc5c02a5..ed0f49f1635ec1b070c2e97d63205607b0a55af6 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -121,13 +121,18 @@ ARCHITECTURE str OF unb1_test IS
-- Select the according revision record based on the design name.
- CONSTANT c_revision_select : t_unb1_test_config := func_sel_revision_rec(g_design_name);
+ CONSTANT c_revision_select : t_unb1_test_config := func_unb1_test_sel_revision_rec(g_design_name);
-- ddr
CONSTANT c_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_revision_select.use_1GbE, 1, 0), c_revision_select.use_front, 0, c_revision_select.use_back, c_revision_select.use_ddr_MB_I, c_revision_select.use_ddr_MB_II, 0, 1);
-
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_revision_select.use_streaming_1GbE, 1, 0),
+ c_revision_select.use_front, 0,
+ c_revision_select.use_back,
+ c_revision_select.use_ddr_MB_I,
+ c_revision_select.use_ddr_MB_II,
+ 0,
+ 1);
CONSTANT c_nof_streams_10GbE : NATURAL := c_revision_select.use_nof_streams_10GbE;
CONSTANT c_nof_streams_1GbE : NATURAL := c_revision_select.use_nof_streams_1GbE;
@@ -316,9 +321,6 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL reg_diag_rx_seq_ddr_MB_II_mosi : t_mem_mosi;
SIGNAL reg_diag_rx_seq_ddr_MB_II_miso : t_mem_miso;
- SIGNAL block_gen_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL block_gen_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-
SIGNAL dp_offload_tx_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL dp_offload_tx_1GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL dp_offload_tx_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
@@ -334,12 +336,6 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL reg_io_ddr_MB_II_mosi : t_mem_mosi;
SIGNAL reg_io_ddr_MB_II_miso : t_mem_miso;
- -- Interface: 1GbE UDP streaming ports
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
-
-- DDR3 pass on termination control from master to slave controller
SIGNAL term_ctrl_out : t_tech_ddr3_phy_terminationcontrol;
SIGNAL term_ctrl_in : t_tech_ddr3_phy_terminationcontrol;
@@ -372,7 +368,7 @@ BEGIN
g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
g_use_phy => c_use_phy,
g_aux => c_unb1_board_aux,
- g_udp_offload => c_revision_select.use_1GbE,
+ g_udp_offload => c_revision_select.use_streaming_1GbE,
g_udp_offload_nof_streams => c_nof_streams_1GbE,
g_dp_clk_use_pll => TRUE,
g_xo_clk_use_pll => TRUE
@@ -457,10 +453,10 @@ BEGIN
eth1g_ram_miso => eth1g_ram_miso,
-- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+ udp_tx_sosi_arr => dp_offload_tx_1GbE_src_out_arr,
+ udp_tx_siso_arr => dp_offload_tx_1GbE_src_in_arr,
+ udp_rx_sosi_arr => dp_offload_rx_1GbE_snk_in_arr,
+ udp_rx_siso_arr => dp_offload_rx_1GbE_snk_out_arr,
-- FPGA pins
-- . General
@@ -491,7 +487,7 @@ BEGIN
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
- g_nof_streams_1GbE => 1,--c_nof_streams_1GbE,
+ g_nof_streams_1GbE => c_nof_streams_1GbE,
g_nof_streams_10GbE => 3,--c_nof_streams_10GbE,
g_nof_streams_ddr => 1,--c_nof_streams_ddr,
g_bg_block_size => c_bg_block_size
@@ -641,7 +637,7 @@ BEGIN
);
- gen_udp_stream_1GbE : IF c_revision_select.use_1GbE = TRUE GENERATE
+ gen_udp_stream_1GbE : IF c_revision_select.use_streaming_1GbE = TRUE GENERATE
u_udp_stream_1GbE : ENTITY work.udp_stream
GENERIC MAP (
g_sim => g_sim,
@@ -759,18 +755,6 @@ BEGIN
END GENERATE;
-
- -----------------------------------------------------------------------------
- -- Interface : 1GbE
- -----------------------------------------------------------------------------
- gen_wires_1GbE : IF c_revision_select.use_1GbE = TRUE GENERATE
- eth1g_udp_tx_sosi_arr(0) <= dp_offload_tx_1GbE_src_out_arr(0);
- dp_offload_tx_1GbE_src_in_arr(0) <= eth1g_udp_tx_siso_arr(0);
-
- dp_offload_rx_1GbE_snk_in_arr(0) <= eth1g_udp_rx_sosi_arr(0);
- eth1g_udp_rx_siso_arr(0) <= dp_offload_rx_1GbE_snk_out_arr(0);
- END GENERATE;
-
-----------------------------------------------------------------------------
-- tr_10GbE
-----------------------------------------------------------------------------