From e388306dadd19b39eabadce2cec73fcf53fd1f02 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Wed, 7 Apr 2021 15:16:51 +0200
Subject: [PATCH] Processed review comments
---
.../src/vhdl/lofar2_unb2b_beamformer.vhd | 111 +++++-----
.../src/vhdl/lofar2_unb2b_filterbank.vhd | 96 ++++----
.../lofar2_unb2b_sdp_station/hdllib.cfg | 2 +-
.../src/vhdl/lofar2_unb2b_sdp_station.vhd | 206 +++++++++---------
.../vhdl/node_sdp_adc_input_and_timing.vhd | 13 +-
.../libraries/sdp/src/vhdl/sdp_bf_weights.vhd | 28 +--
.../lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd | 2 +-
.../unb2b_board/src/vhdl/ctrl_unb2b_board.vhd | 2 +-
8 files changed, 241 insertions(+), 219 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 3a7c092e0d..fc365f01a7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -139,7 +139,8 @@ ARCHITECTURE str OF lofar2_unb2b_beamformer IS
-- Read only sdp_info values
CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
- SIGNAL gn_index : NATURAL := 0;
+ SIGNAL gn_id : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+ SIGNAL gn_index : NATURAL := 0;
-- System
@@ -371,12 +372,16 @@ ARCHITECTURE str OF lofar2_unb2b_beamformer IS
SIGNAL nw_10GbE_hdr_fields_in_arr : t_slv_1024_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL id_backplane : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
- SIGNAL id_eth : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ SIGNAL this_bck_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0);
+ SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0);
- SIGNAL eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- SIGNAL ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- SIGNAL udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL cep_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL cep_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL cep_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL stat_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL stat_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL sst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL bst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
@@ -430,6 +435,9 @@ BEGIN
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
-- Toggle WDI
pout_wdi => pout_wdi,
@@ -632,8 +640,45 @@ BEGIN
ram_scrap_mosi => ram_scrap_mosi,
ram_scrap_miso => ram_scrap_miso
);
+
+ -----------------------------------------------------------------------------
+ -- SDP Info register
+ -----------------------------------------------------------------------------
+ u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
+ PORT MAP(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
+
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
+
+ -- sdp info
+ sdp_info => sdp_info
+ );
+
+ -----------------------------------------------------------------------------
+ -- nof beamsets node_sdp_beamformers (BF)
+ -----------------------------------------------------------------------------
+ gn_id <= ID(c_sdp_W_gn_id-1 DOWNTO 0);
+ gn_index <= TO_UINT(gn_id);
+ -- derive MAC, IP and UDP Port
+ cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
+ stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
+ bst_udp_src_port <= c_sdp_bst_udp_src_port_15_8 & ID;
-
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
@@ -724,49 +769,13 @@ BEGIN
reg_selector_miso => reg_dp_selector_miso,
sdp_info => sdp_info,
- gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
);
-
- -----------------------------------------------------------------------------
- -- SDP Info register
- -----------------------------------------------------------------------------
- gn_index <= TO_UINT(ID(c_sdp_W_gn_id-1 DOWNTO 0));
-
- u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
- PORT MAP(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
-
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
-
- -- sdp info
- sdp_info => sdp_info
- );
-
- -----------------------------------------------------------------------------
- -- nof beamsets node_sdp_beamformers (BF)
- -----------------------------------------------------------------------------
- -- derive MAC, IP and UDP Port from ID
- id_backplane <= RESIZE_UVEC(ID(c_sdp_W_gn_id-1 DOWNTO 2), c_byte_w);
- id_eth <= RESIZE_UVEC(ID(1 DOWNTO 0) & TO_UVEC(0, 2), c_byte_w);
- eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & id_backplane & INCR_UVEC(id_eth, 0); -- Interface id = 0
- ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_eth, 1); -- Interface id = 0
- udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
-- Beamformers
gen_bf : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
@@ -802,11 +811,11 @@ BEGIN
ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
sdp_info => sdp_info,
- gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
+ gn_id => gn_id,
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
+ eth_src_mac => cep_eth_src_mac,
+ ip_src_addr => cep_ip_src_addr,
+ udp_src_port => cep_udp_src_port,
hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index d32ffe7f4d..eb53db17a7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -118,6 +118,7 @@ ARCHITECTURE str OF lofar2_unb2b_filterbank IS
-- Read only sdp_info values
CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
+ SIGNAL gn_id : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
SIGNAL gn_index : NATURAL := 0;
-- System
@@ -273,16 +274,16 @@ ARCHITECTURE str OF lofar2_unb2b_filterbank IS
SIGNAL reg_stat_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_stat_hdr_dat_miso : t_mem_miso;
- -- Statistics ??
- SIGNAL id_backplane : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
- SIGNAL id_chip : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
-
+ -- Statistics
SIGNAL udp_tx_sosi_arr : t_dp_sosi_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
SIGNAL udp_tx_siso_arr : t_dp_siso_arr(c_udp_offload_nof_streams-1 DOWNTO 0);
- SIGNAL eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- SIGNAL ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- SIGNAL udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL this_bck_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0);
+ SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0);
+
+ SIGNAL stat_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL stat_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL sst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
@@ -339,7 +340,10 @@ BEGIN
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
-
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
-- Toggle WDI
pout_wdi => pout_wdi,
@@ -541,7 +545,37 @@ BEGIN
reg_stat_hdr_dat_miso => reg_stat_hdr_dat_miso
);
-
+ -----------------------------------------------------------------------------
+ -- SDP Info register
+ -----------------------------------------------------------------------------
+ gn_id <= ID(c_sdp_W_gn_id-1 DOWNTO 0);
+ gn_index <= TO_UINT(gn_id);
+ -- derive MAC, IP and UDP Port
+ stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
+
+ u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
+ PORT MAP(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
+
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
+
+ -- sdp info
+ sdp_info => sdp_info
+ );
+
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
@@ -600,42 +634,10 @@ BEGIN
-- Streaming data output
out_sosi_arr => ait_sosi_arr
);
-
+
-----------------------------------------------------------------------------
- -- SDP Info register
+ -- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
- gn_index <= TO_UINT(ID(c_sdp_W_gn_id-1 DOWNTO 0));
-
- u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
- PORT MAP(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
-
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
-
- -- sdp info
- sdp_info => sdp_info
- );
-
- -- derive MAC, IP and UDP Port from ID
- id_backplane <= RESIZE_UVEC(ID(c_sdp_W_gn_id-1 DOWNTO 2), c_byte_w);
- id_chip <= RESIZE_UVEC(ID(1 DOWNTO 0), c_byte_w); -- Unb2 has 4 FPGA chips
-
- -- The eth_src_mac and ip_src_addr for SST offload are the same as for M&C, because they share the same 1GbE interface
- eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & id_backplane & id_chip;
- ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_chip, 1); -- +1, because IP address must be > 0
- udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
-
u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank
GENERIC MAP(
g_sim => g_sim,
@@ -673,11 +675,11 @@ BEGIN
reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
sdp_info => sdp_info,
- gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
+ gn_id => gn_id,
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
);
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
index eb210374c4..663aefa26a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
@@ -25,7 +25,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
src/data data
-#### Overwrite bf weights with sim data
+#### Overwrite bf weights with sim data ensuring all weights are 1.0 by default in simulation.
tb/data data
[quartus_project_file]
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index bf5f1e8b2f..75afb61dfa 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -86,7 +86,7 @@ ENTITY lofar2_unb2b_sdp_station IS
-- Transceiver clocks
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
- -- front transceivers
+ -- front transceivers QSFP1 for 10GbE output to CEP.
QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-- LEDs
@@ -112,7 +112,7 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
- CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ CONSTANT c_lofar2_sample_clk_freq : NATURAL := c_sdp_f_adc_MHz * 10**6; -- fixed 200 MHz for LOFAR2.0 stage 1
-- 10 GbE Interface
CONSTANT c_nof_streams_qsfp : NATURAL := 4;
@@ -132,13 +132,13 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
-
-- Read only sdp_info values
CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
+
+ SIGNAL gn_id : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
SIGNAL gn_index : NATURAL := 0;
-
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_ethclk : STD_LOGIC;
@@ -155,66 +155,66 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL pout_wdi : STD_LOGIC;
-- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi;
- SIGNAL reg_wdi_miso : t_mem_miso;
+ SIGNAL reg_wdi_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_wdi_miso : t_mem_miso := c_mem_miso_rst;
-- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi;
- SIGNAL reg_ppsh_miso : t_mem_miso;
+ SIGNAL reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
-- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
- SIGNAL rom_unb_system_info_miso : t_mem_miso;
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
-- UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
- SIGNAL reg_unb_sens_miso : t_mem_miso;
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_unb_sens_miso : t_mem_miso := c_mem_miso_rst;
-- pm bus
- SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
- SIGNAL reg_unb_pmbus_miso : t_mem_miso;
+ SIGNAL reg_unb_pmbus_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_unb_pmbus_miso : t_mem_miso := c_mem_miso_rst;
-- FPGA sensors
- SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
- SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
- SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
- SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
+ SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_fpga_temp_sens_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso := c_mem_miso_rst;
-- eth1g
SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso;
+ SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso := c_mem_miso_rst;
-- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_data_miso : t_mem_miso;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso := c_mem_miso_rst;
-- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_data_miso : t_mem_miso;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso := c_mem_miso_rst;
-- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi;
- SIGNAL reg_epcs_miso : t_mem_miso;
+ SIGNAL reg_epcs_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_epcs_miso : t_mem_miso := c_mem_miso_rst;
-- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi;
- SIGNAL reg_remu_miso : t_mem_miso;
+ SIGNAL reg_remu_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_remu_miso : t_mem_miso := c_mem_miso_rst;
-- Scrap ram
- SIGNAL ram_scrap_mosi : t_mem_mosi;
- SIGNAL ram_scrap_miso : t_mem_miso;
+ SIGNAL ram_scrap_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_scrap_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------
-- AIT
@@ -246,47 +246,47 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL ram_wg_miso : t_mem_miso := c_mem_miso_rst;
-- BSN MONITOR
- SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_input_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_bsn_monitor_input_miso : t_mem_miso := c_mem_miso_rst;
-- Data buffer bsn
- SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso;
+ SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
-- Aduh statistics monitor
- SIGNAL reg_aduh_monitor_mosi : t_mem_mosi;
- SIGNAL reg_aduh_monitor_miso : t_mem_miso;
+ SIGNAL reg_aduh_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------
-- FUSB
----------------------------------------------
-- Subband statistics
- SIGNAL ram_st_sst_mosi : t_mem_mosi;
- SIGNAL ram_st_sst_miso : t_mem_miso;
+ SIGNAL ram_st_sst_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_sst_miso : t_mem_miso := c_mem_miso_rst;
-- Spectral Inversion
- SIGNAL reg_si_mosi : t_mem_mosi;
- SIGNAL reg_si_miso : t_mem_miso;
+ SIGNAL reg_si_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_si_miso : t_mem_miso := c_mem_miso_rst;
-- Filter coefficients
- SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
- SIGNAL ram_fil_coefs_miso : t_mem_miso;
+ SIGNAL ram_fil_coefs_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_fil_coefs_miso : t_mem_miso := c_mem_miso_rst;
-- Equalizer gains
- SIGNAL ram_equalizer_gains_mosi : t_mem_mosi;
- SIGNAL ram_equalizer_gains_miso : t_mem_miso;
+ SIGNAL ram_equalizer_gains_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_equalizer_gains_miso : t_mem_miso := c_mem_miso_rst;
-- DP Selector
- SIGNAL reg_dp_selector_mosi : t_mem_mosi;
- SIGNAL reg_dp_selector_miso : t_mem_miso;
+ SIGNAL reg_dp_selector_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dp_selector_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------
-- SDP Info
----------------------------------------------
- SIGNAL reg_sdp_info_mosi : t_mem_mosi;
- SIGNAL reg_sdp_info_miso : t_mem_miso;
+ SIGNAL reg_sdp_info_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_sdp_info_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------
-- BF
@@ -294,47 +294,47 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Beamlet Subband Select
SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_ss_ss_wide_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL ram_ss_ss_wide_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_ss_ss_wide_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Local BF bf weights
SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_bf_weights_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_bf_weights_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL ram_bf_weights_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL ram_bf_weights_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_bf_weights_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- mms_dp_scale Scale Beamlets
SIGNAL reg_bf_scale_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_bf_scale_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_bf_scale_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL reg_bf_scale_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL reg_bf_scale_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_bf_scale_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Data Output header fields
SIGNAL reg_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_hdr_dat_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL reg_hdr_dat_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL reg_hdr_dat_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_hdr_dat_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Data Output xonoff
SIGNAL reg_dp_xonoff_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_xonoff_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_dp_xonoff_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL reg_dp_xonoff_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL reg_dp_xonoff_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_dp_xonoff_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Statistics (BST)
SIGNAL ram_st_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_st_bst_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
----------------------------------------------
-- 10 GbE
----------------------------------------------
- SIGNAL reg_nw_10GbE_mac_mosi : t_mem_mosi;
- SIGNAL reg_nw_10GbE_mac_miso : t_mem_miso;
+ SIGNAL reg_nw_10GbE_mac_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_nw_10GbE_mac_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi;
- SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso;
+ SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------
@@ -364,12 +364,17 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL nw_10GbE_hdr_fields_in_arr : t_slv_1024_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL id_backplane : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
- SIGNAL id_eth : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ SIGNAL this_bck_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0);
+ SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0);
- SIGNAL eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- SIGNAL ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- SIGNAL udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL cep_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL cep_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL cep_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL stat_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL stat_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL sst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL bst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL xst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
@@ -419,7 +424,10 @@ BEGIN
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
-
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
-- Toggle WDI
pout_wdi => pout_wdi,
@@ -622,13 +630,17 @@ BEGIN
-----------------------------------------------------------------------------
-- SDP Info register
-----------------------------------------------------------------------------
- gn_index <= TO_UINT(ID(c_sdp_W_gn_id-1 DOWNTO 0));
- -- derive MAC, IP and UDP Port from ID
- id_backplane <= RESIZE_UVEC(ID(c_sdp_W_gn_id-1 DOWNTO 2), c_byte_w);
- id_eth <= RESIZE_UVEC(ID(1 DOWNTO 0) & TO_UVEC(0, 2), c_byte_w);
- eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & id_backplane & INCR_UVEC(id_eth, 0); -- Interface id = 0
- ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_eth, 1); -- Interface id = 0
- udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
+ gn_id <= ID(c_sdp_W_gn_id-1 DOWNTO 0);
+ gn_index <= TO_UINT(gn_id);
+ -- derive MAC, IP and UDP Port
+ cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
+ stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
+ bst_udp_src_port <= c_sdp_bst_udp_src_port_15_8 & ID;
+ xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & ID;
u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
PORT MAP(
@@ -734,10 +746,10 @@ BEGIN
reg_selector_miso => reg_dp_selector_miso,
sdp_info => sdp_info,
- gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
);
END GENERATE;
@@ -779,11 +791,11 @@ BEGIN
ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
sdp_info => sdp_info,
- gn_id => ID(c_sdp_W_gn_id-1 DOWNTO 0),
+ gn_id => gn_id,
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
+ eth_src_mac => cep_eth_src_mac,
+ ip_src_addr => cep_ip_src_addr,
+ udp_src_port => cep_udp_src_port,
hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 424218a2bc..3a9ba31cad 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -111,16 +111,13 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
CONSTANT c_wg_buf_directory : STRING := "data/";
CONSTANT c_wg_buf_dat_w : NATURAL := 18; --default value of WG that fits 14 bits of ADC data
CONSTANT c_wg_buf_addr_w : NATURAL := 10; --default value of WG for 1024 samples;
- SIGNAL wg_out_ovr : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL wg_out_val : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL wg_out_data : STD_LOGIC_VECTOR(c_sdp_S_pn*c_wg_buf_dat_w-1 DOWNTO 0);
- SIGNAL wg_out_sync : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL trigger_wg : STD_LOGIC;
-- Frame parameters TBC
CONSTANT c_bs_bsn_w : NATURAL := 64; --51;
- CONSTANT c_bs_block_size : NATURAL := 1024;
- CONSTANT c_bs_nof_block_per_sync : NATURAL := 390625; -- generate a sync every 2s for testing
+ CONSTANT c_bs_block_size : NATURAL := c_sdp_N_fft; -- =1024;
+ CONSTANT c_bs_nof_clk_per_sync : NATURAL := 2 * c_sdp_f_adc_MHz * 10**6; -- = 400M, use a sync interval of 2s for testing
+ CONSTANT c_bs_nof_block_per_sync : NATURAL := c_bs_nof_clk_per_sync / c_sdp_N_fft; -- = 390625, to have integer number of blocks per sync interval for testing
CONSTANT c_dp_fifo_dc_size : NATURAL := 64;
-- JESD signals
@@ -392,9 +389,9 @@ BEGIN
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_nof_streams => c_sdp_S_pn,
- g_symbol_w => c_sdp_W_adc_jesd, --TBD 16?
+ g_symbol_w => c_sdp_W_adc_jesd,
g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => 200000512 -- = 195313 blocks * 1024 samples
+ g_nof_accumulations => c_bs_nof_clk_per_sync
)
PORT MAP (
-- Memory-mapped clock domain
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index 6498dab03f..229ca24f7e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -76,30 +76,32 @@ BEGIN
-- to be applied according the subband data order
-- [N_pol][S_pn/Q_fft]_[S_sub_bf][Q_fft]. Therefore this counter
-- has to account for this difference in order.
- p_cnt : PROCESS(dp_clk, dp_rst, in_sosi_arr)
+ p_cnt : PROCESS(dp_clk, dp_rst)
VARIABLE v_Q_fft, v_S_sub_bf : NATURAL;
BEGIN
IF dp_rst = '1' THEN
cnt <= 0;
v_Q_fft := 0;
v_S_sub_bf := 0;
- ELSIF rising_edge(dp_clk) AND in_sosi_arr(0).valid = '1' THEN
- IF in_sosi_arr(0).eop = '1' THEN
- v_Q_fft := 0;
- v_S_sub_bf := 0;
- ELSE
- IF v_Q_fft >= c_sdp_Q_fft-1 THEN
+ ELSIF rising_edge(dp_clk) THEN
+ IF in_sosi_arr(0).valid = '1' THEN
+ IF in_sosi_arr(0).eop = '1' THEN
v_Q_fft := 0;
- IF v_S_sub_bf >= c_sdp_S_sub_bf-1 THEN
- v_S_sub_bf := 0;
+ v_S_sub_bf := 0;
+ ELSE
+ IF v_Q_fft >= c_sdp_Q_fft-1 THEN
+ v_Q_fft := 0;
+ IF v_S_sub_bf >= c_sdp_S_sub_bf-1 THEN
+ v_S_sub_bf := 0;
+ ELSE
+ v_S_sub_bf := v_S_sub_bf + 1;
+ END IF;
ELSE
- v_S_sub_bf := v_S_sub_bf + 1;
+ v_Q_fft := v_Q_fft + 1;
END IF;
- ELSE
- v_Q_fft := v_Q_fft + 1;
END IF;
+ cnt <= v_Q_fft * c_sdp_S_sub_bf + v_S_sub_bf;
END IF;
- cnt <= v_Q_fft * c_sdp_S_sub_bf + v_S_sub_bf;
END IF;
END PROCESS;
gains_rd_address <= TO_UVEC(cnt, c_gain_addr_w);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index dee35dd346..e6130f2e68 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -69,6 +69,7 @@ PACKAGE sdp_pkg is
-------------------------------------------------
-- SDP specific parameters as defined in:
-- L3 SDP Decision: SDP Parameter definitions
+ CONSTANT c_sdp_f_adc_MHz : NATURAL := 200;
CONSTANT c_sdp_N_beamsets : NATURAL := 2;
CONSTANT c_sdp_N_fft : NATURAL := 1024;
CONSTANT c_sdp_N_pn_lb : NATURAL := 16;
@@ -94,7 +95,6 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_W_sub_magnitude : NATURAL := 2;
CONSTANT c_sdp_W_sub_weight : NATURAL := 16;
CONSTANT c_sdp_W_subband : NATURAL := 18;
- CONSTANT c_sdp_f_adc_MHz : NATURAL := 200;
-- Derived constants
CONSTANT c_sdp_P_pfb : NATURAL := c_sdp_S_pn / c_sdp_Q_fft;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index ead51ff2cb..0856f4403c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -143,7 +143,7 @@ ENTITY ctrl_unb2b_board IS
mb_II_ref_rst : OUT STD_LOGIC; -- reset in MB_II_REF_CLK domain released after mm_rst
this_chip_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0); -- [1:0], so range 0-3 for PN
- this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+ this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0); -- [5:0] used out of ID[7:2] to index UniBoard2 boards
app_led_red : IN STD_LOGIC := '0';
app_led_green : IN STD_LOGIC := '1';
--
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