diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
index 5d399780f5e3aaf91a03cf804266909247b51186..a1b2b4340e756e765cd54e34b6c2d511b03e9311 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -137,6 +137,7 @@ ARCHITECTURE str OF unb1_terminal_bg_mesh_db IS
   SIGNAL mm_locked                   : STD_LOGIC;
   SIGNAL mm_rst                      : STD_LOGIC;
   SIGNAL cal_clk                     : STD_LOGIC;
+  SIGNAL epcs_clk                    : STD_LOGIC; 
                                      
   SIGNAL dp_rst                      : STD_LOGIC;
   SIGNAL dp_clk                      : STD_LOGIC;
@@ -220,34 +221,44 @@ BEGIN
   -----------------------------------------------------------------------------
   u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
   GENERIC MAP (
-    g_sim           => g_sim,
-    g_design_name   => g_design_name,
-    g_design_note   => g_design_note,
-    g_stamp_date    => g_stamp_date,
-    g_stamp_time    => g_stamp_time, 
-    g_stamp_svn     => g_stamp_svn, 
-    g_fw_version    => c_fw_version,
-    g_mm_clk_freq   => c_unb1_board_mm_clk_freq_50M,
-    g_use_phy       => c_use_phy,
-    g_aux           => c_unb1_board_aux
+    g_sim            => g_sim,
+    g_design_name    => g_design_name,
+    g_design_note    => g_design_note,
+    g_stamp_date     => g_stamp_date,
+    g_stamp_time     => g_stamp_time, 
+    g_stamp_svn      => g_stamp_svn, 
+    g_fw_version     => c_fw_version,
+    g_mm_clk_freq    => c_unb1_board_mm_clk_freq_125M,
+    g_use_phy        => c_use_phy,
+    g_aux            => c_unb1_board_aux,
+    g_dp_clk_use_pll => TRUE,
+    g_xo_clk_use_pll => TRUE
+    
   )
   PORT MAP (
-    -- Clock an reset signals
+    -- Clock and reset signals
     cs_sim                   => cs_sim,
     xo_clk                   => xo_clk,
     xo_rst                   => xo_rst,
     xo_rst_n                 => xo_rst_n,
 
+    mm_clk_out               => mm_clk,
     mm_clk                   => mm_clk,
-    mm_locked                => mm_locked,
     mm_rst                   => mm_rst,
 
+    mm_locked                => mm_locked,
+    mm_locked_out            => mm_locked,
+
+    epcs_clk                 => epcs_clk,
+    epcs_clk_out             => epcs_clk,
+
     dp_rst                   => dp_rst,
     dp_clk                   => dp_clk,
     dp_pps                   => dp_pps,
     dp_rst_in                => dp_rst,
     dp_clk_in                => dp_clk,
-    
+
+    cal_rec_clk              => cal_clk,    
     -- Toggle WDI
     pout_wdi                 => pout_wdi,