diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 1c5bb853caf166cf6b5536e9b5b9ab0bf05b8f23..1bd4841de59ecc1519cb26f25013e0f0cbc3926d 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -32,24 +32,29 @@ USE work.diag_pkg.ALL;
-- > run -all
-- . default should run OK i.e. no mismatches reported
-- . force errors by briefly using different tx sequence at the end of the
---- stimuli process, these mismatches are reported
+-- stimuli process, these mismatches are reported
+-- Remarks:
+-- . The tb can verify rx_steps other than +1 by using g_tx_cnt_incr, it can
+-- only verify one of the c_diag_seq_rx_reg_nof_steps at a time.
+
ENTITY tb_diag_rx_seq IS
GENERIC (
- g_use_steps : BOOLEAN := TRUE;
- g_steps_arr : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0) := (OTHERS=>1);
+ g_tx_cnt_incr : INTEGER := -7;
+ g_rx_use_steps : BOOLEAN := TRUE;
+ g_rx_steps_arr : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0) := (1, 0, -7, 3);
g_seq_dat_w : NATURAL := 16 -- = 12b for Lofar RCU test data, 16b for Lofar TBBI test data
);
END tb_diag_rx_seq;
ARCHITECTURE tb OF tb_diag_rx_seq IS
- CONSTANT c_period : TIME := 100 ns;
- CONSTANT c_nof_cycles : NATURAL := 100;
- CONSTANT c_latency : NATURAL := 2;
+ CONSTANT c_period : TIME := 100 ns;
+ CONSTANT c_nof_cycles : NATURAL := 100;
+ CONSTANT c_latency : NATURAL := 2;
- CONSTANT c_nof_steps : NATURAL := c_diag_seq_rx_reg_nof_steps;
- CONSTANT c_diag_res_w : NATURAL := g_seq_dat_w + 1;
+ CONSTANT c_rx_nof_steps : NATURAL := c_diag_seq_rx_reg_nof_steps;
+ CONSTANT c_diag_res_w : NATURAL := g_seq_dat_w + 1;
CONSTANT c_diag_res_ok : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0) := '0' & TO_UVEC( 0, c_diag_res_w-1);
CONSTANT c_diag_res_wrong : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0) := '0' & TO_UVEC(2**g_seq_dat_w-1, c_diag_res_w-1);
@@ -68,7 +73,7 @@ ARCHITECTURE tb OF tb_diag_rx_seq IS
-- Rx test data
SIGNAL rx_diag_en : STD_LOGIC;
SIGNAL rx_diag_sel : STD_LOGIC;
- SIGNAL rx_diag_steps_arr : t_integer_arr(c_nof_steps-1 DOWNTO 0) := g_steps_arr;
+ SIGNAL rx_diag_steps_arr : t_integer_arr(c_rx_nof_steps-1 DOWNTO 0) := g_rx_steps_arr;
SIGNAL diag_res : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0);
SIGNAL diag_res_val : STD_LOGIC;
@@ -89,7 +94,7 @@ BEGIN
tx_diag_req <= '1';
-- COUNTER
- expected_res <= sel_a_b(g_use_steps, c_diag_res_ok, c_diag_res_ok);
+ expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_ok, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '1';
rx_diag_sel <= '1';
@@ -122,7 +127,7 @@ BEGIN
WAIT FOR c_latency*c_period;
-- PRSG
- expected_res <= sel_a_b(g_use_steps, c_diag_res_wrong, c_diag_res_ok);
+ expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_wrong, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '0';
rx_diag_sel <= '0';
@@ -136,7 +141,7 @@ BEGIN
-- COUNTER
WAIT FOR c_latency*c_period;
- expected_res <= sel_a_b(g_use_steps, c_diag_res_ok, c_diag_res_ok);
+ expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_ok, c_diag_res_ok);
tx_diag_en <= '0'; -- stop tx
WAIT FOR c_period;
tx_diag_sel <= '1';
@@ -154,7 +159,7 @@ BEGIN
WAIT FOR c_latency*c_period;
-- COUNTER
- expected_res <= sel_a_b(g_use_steps, c_diag_res_ok, c_diag_res_ok);
+ expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_ok, c_diag_res_ok);
tx_diag_en <= '0'; -- stop tx
tx_diag_req <= '0'; -- inactive tx request
WAIT FOR c_period;
@@ -185,7 +190,7 @@ BEGIN
WAIT FOR c_latency*c_period;
-- PRSG
- expected_res <= sel_a_b(g_use_steps, c_diag_res_wrong, c_diag_res_ok);
+ expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_wrong, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '0';
rx_diag_sel <= '0';
@@ -201,7 +206,7 @@ BEGIN
WAIT FOR c_latency*c_period;
-- PRSG
- expected_res <= sel_a_b(g_use_steps, c_diag_res_wrong, c_diag_res_ok);
+ expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_wrong, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '0';
rx_diag_sel <= '0';
@@ -227,7 +232,7 @@ BEGIN
WAIT FOR c_latency*c_period;
-- COUNTER
- expected_res <= sel_a_b(g_use_steps, c_diag_res_ok, c_diag_res_ok);
+ expected_res <= sel_a_b(g_rx_use_steps, c_diag_res_ok, c_diag_res_ok);
WAIT FOR c_period;
tx_diag_sel <= '1';
rx_diag_sel <= '1';
@@ -252,7 +257,8 @@ BEGIN
u_diag_tx_seq : ENTITY work.diag_tx_seq
GENERIC MAP (
- g_dat_w => g_seq_dat_w
+ g_cnt_incr => g_tx_cnt_incr,
+ g_dat_w => g_seq_dat_w
)
PORT MAP (
clk => clk,
@@ -266,8 +272,8 @@ BEGIN
u_diag_rx_seq : ENTITY work.diag_rx_seq
GENERIC MAP (
- g_use_steps => g_use_steps,
- g_nof_steps => c_nof_steps,
+ g_use_steps => g_rx_use_steps,
+ g_nof_steps => c_rx_nof_steps,
g_dat_w => g_seq_dat_w,
g_diag_res_w => c_diag_res_w
)
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
index cedd41b5269a990e9654d2152dbbd26dc895de32..f3f1c323f51f5ed2fe2363756a8cc82e8f8cc053 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
@@ -30,11 +30,13 @@ END tb_tb_diag_rx_seq;
ARCHITECTURE tb OF tb_tb_diag_rx_seq IS
BEGIN
- -- g_use_steps : BOOLEAN := TRUE;
- -- g_steps_arr : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0) := (OTHERS=>1);
- -- g_seq_dat_w : NATURAL := 16 -- = 12b for Lofar RCU test data, 16b for Lofar TBBI test data
+ -- g_tx_cnt_incr : INTEGER := 1;
+ -- g_rx_use_steps : BOOLEAN := TRUE;
+ -- g_rx_steps_arr : t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0) := (OTHERS=>1);
+ -- g_seq_dat_w : NATURAL := 16
- u_diag_sel : ENTITY work.tb_diag_rx_seq GENERIC MAP (FALSE, (1, 1, 1, 1), 16);
- u_diag_steps : ENTITY work.tb_diag_rx_seq GENERIC MAP ( TRUE, (1, 1, 1, 1), 16);
+ u_diag_sel : ENTITY work.tb_diag_rx_seq GENERIC MAP ( 1, FALSE, (1, 1, 1, 1), 8);
+ u_diag_steps_incr_1 : ENTITY work.tb_diag_rx_seq GENERIC MAP ( 1, TRUE, (1, 1, 1, 1), 8);
+ u_diag_steps_incr_neg_7 : ENTITY work.tb_diag_rx_seq GENERIC MAP (-7, TRUE, (1, -7, 1, 1), 8);
END tb;