From e1aa55a375815e6e9388011a8e8b6e4467b36eb7 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Wed, 3 Feb 2021 13:19:24 +0100
Subject: [PATCH] L2SDP-200, chanded comment and cleaned up.
---
libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index 00a1360623..10eba26202 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -59,7 +59,7 @@ END tb_dp_block_from_mm;
ARCHITECTURE tb OF tb_dp_block_from_mm IS
CONSTANT c_nof_blocks : NATURAL := g_step_size / g_data_size;
- CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks + g_data_size; -- Size is 1 address more than needed, to check for oversized blocks.
+ CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks + g_data_size; -- Size is g_data_size addresses more than needed, to check for oversized blocks.
CONSTANT c_ram_adr_w : NATURAL := ceil_log2(c_ram_data_size);
CONSTANT c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
@@ -116,7 +116,7 @@ BEGIN
ram_wr_en <= '0';
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 10);
- FOR i IN 0 TO c_ram_data_size - 1 LOOP -- Write 1 address more than needed.
+ FOR i IN 0 TO c_ram_data_size - 1 LOOP
ram_wr_adr <= TO_UVEC(i, c_ram.adr_w);
ram_wr_dat <= TO_UVEC(i, c_ram.dat_w);
ram_wr_en <= '1';
@@ -140,7 +140,6 @@ BEGIN
proc_common_wait_some_cycles(clk, 1);
start_pulse <= '0';
- --stop_address <= start_address + g_nof_data * g_step_size - g_data_size - 1;
stop_address <= start_address + (g_nof_data - 1) * g_step_size + g_data_size - 1;
proc_common_wait_until_high(clk, block_done);
END LOOP;
@@ -167,7 +166,7 @@ BEGIN
ram_rd_adr <= TO_UVEC(0 , c_ram.adr_w);
proc_common_wait_until_high(clk, transfer_done);
ram_rd_en <= '1';
- FOR i IN 0 TO c_ram_data_size - 1 LOOP -- Ask for 1 address more than needed.
+ FOR i IN 0 TO c_ram_data_size - 1 LOOP
ram_rd_adr <= TO_UVEC(i, c_ram.adr_w);
proc_common_wait_some_cycles(clk, 1);
END LOOP;
@@ -182,7 +181,6 @@ BEGIN
p_verify_read_ram_data: PROCESS
BEGIN
- --stop_address <= g_nof_data * g_step_size - 1;
rd_nxt_data <= 1;
proc_common_wait_until_high(clk, transfer_done);
WHILE tb_end = '0' LOOP
--
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