From e197d696df13fde17d899a22627753f0eedaf38a Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 1 Dec 2022 16:24:16 +0100
Subject: [PATCH] Correct range of samples_cnt for gapsize. Support BG disable
at sync.
---
.../base/diag/src/vhdl/diag_block_gen.vhd | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen.vhd b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
index 7e48ee30e5..55ed96f50c 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
@@ -107,7 +107,7 @@ architecture rtl of diag_block_gen is
sop : std_logic;
eop : std_logic;
rd_ena : std_logic;
- samples_cnt : natural range 0 to 2**c_diag_bg_samples_per_packet_w-1;
+ samples_cnt : natural range 0 to 2**c_diag_bg_gapsize_w-1;
blocks_cnt : natural range 0 to 2**c_diag_bg_blocks_per_sync_w-1;
bsn_cnt : std_logic_vector(c_diag_bg_bsn_init_w-1 downto 0); -- = c_dp_stream_bsn_w
mem_cnt : natural range 0 to 2**g_buf_addr_w-1;
@@ -146,14 +146,16 @@ begin
v.rd_ena := '0';
-- Control block generator enable
- if ctrl.enable='0' then
- v.blk_en := '0'; -- disable immediately
- elsif ctrl.enable_sync='0' then
- v.blk_en := '1'; -- enable immediately or keep enabled
- elsif en_sync='1' then
- v.blk_en := '1'; -- enable at input sync pulse or keep enabled
+ if ctrl.enable_sync='0' then
+ -- apply ctrl.enable immediately
+ v.blk_en := ctrl.enable;
+ else
+ -- keep blk_en and apply ctrl.enable at input sync pulse
+ if en_sync='1' then
+ v.blk_en := ctrl.enable;
+ end if;
end if;
-
+
-- The pulse sync is high at the sop of the first block, the block sync is high during the entire block until the eop
if r.eop='1' then
v.blk_sync := '0';
--
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