diff --git a/applications/unb1_correlator/quartus/qsys_unb1_correlator.qsys b/applications/unb1_correlator/quartus/qsys_unb1_correlator.qsys
index 7bc5f01a210f39750c48ccf7e8a83497d0e86480..150d3eab88168e03679c38080831ca95f7890d0c 100644
--- a/applications/unb1_correlator/quartus/qsys_unb1_correlator.qsys
+++ b/applications/unb1_correlator/quartus/qsys_unb1_correlator.qsys
@@ -6,9 +6,12 @@
version="1.0"
description=""
tags=""
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
+ element $${FILENAME}
+ {
+ }
element altpll_0
{
datum _sortIndex
@@ -21,7 +24,7 @@
{
datum baseAddress
{
- value = "368";
+ value = "304";
type = "long";
}
}
@@ -102,7 +105,7 @@
type = "String";
}
}
- element rom_system_info.mem
+ element pio_system_info.mem
{
datum _lockedAddress
{
@@ -111,23 +114,23 @@
}
datum baseAddress
{
- value = "4096";
+ value = "0";
type = "long";
}
}
- element reg_epcs.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "288";
+ value = "312";
type = "long";
}
}
- element pio_pps.mem
+ element ram_diag_data_buf.mem
{
datum baseAddress
{
- value = "376";
+ value = "524288";
type = "long";
}
}
@@ -144,23 +147,7 @@
type = "long";
}
}
- element reg_mmdp_ctrl.mem
- {
- datum baseAddress
- {
- value = "400";
- type = "long";
- }
- }
- element reg_unb_sens.mem
- {
- datum baseAddress
- {
- value = "224";
- type = "long";
- }
- }
- element pio_system_info.mem
+ element rom_system_info.mem
{
datum _lockedAddress
{
@@ -169,39 +156,23 @@
}
datum baseAddress
{
- value = "0";
- type = "long";
- }
- }
- element reg_remu.mem
- {
- datum baseAddress
- {
- value = "256";
- type = "long";
- }
- }
- element reg_dpmm_ctrl.mem
- {
- datum baseAddress
- {
- value = "384";
+ value = "4096";
type = "long";
}
}
- element reg_dpmm_data.mem
+ element reg_diag_data_buf.mem
{
datum baseAddress
{
- value = "392";
+ value = "20480";
type = "long";
}
}
- element reg_mmdp_data.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "408";
+ value = "224";
type = "long";
}
}
@@ -288,27 +259,19 @@
}
datum baseAddress
{
- value = "320";
+ value = "256";
type = "long";
}
}
- element reg_dpmm_ctrl
- {
- datum _sortIndex
- {
- value = "17";
- type = "int";
- }
- }
- element reg_dpmm_data
+ element ram_diag_data_buf
{
datum _sortIndex
{
- value = "18";
+ value = "15";
type = "int";
}
}
- element reg_epcs
+ element reg_diag_data_buf
{
datum _sortIndex
{
@@ -316,30 +279,6 @@
type = "int";
}
}
- element reg_mmdp_ctrl
- {
- datum _sortIndex
- {
- value = "19";
- type = "int";
- }
- }
- element reg_mmdp_data
- {
- datum _sortIndex
- {
- value = "20";
- type = "int";
- }
- }
- element reg_remu
- {
- datum _sortIndex
- {
- value = "15";
- type = "int";
- }
- }
element reg_unb_sens
{
datum _sortIndex
@@ -364,11 +303,19 @@
type = "int";
}
}
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "272";
+ type = "long";
+ }
+ }
element pio_wdi.s1
{
datum baseAddress
{
- value = "352";
+ value = "288";
type = "long";
}
}
@@ -385,14 +332,6 @@
type = "long";
}
}
- element pio_debug_wave.s1
- {
- datum baseAddress
- {
- value = "336";
- type = "long";
- }
- }
element timer_0.s1
{
datum baseAddress
@@ -421,10 +360,10 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName">unb1_minimal_sopc.qpf</parameter>
+ <parameter name="projectName" value="unb1_correlator.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1414142788570" />
+ <parameter name="timeStamp" value="1416325611226" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
@@ -445,15 +384,6 @@
name="coe_reg_read_export_from_the_avs_eth_0"
internal="coe_reg_read_export" />
</interface>
- <interface
- name="reg_mmdp_ctrl_readdata"
- internal="reg_mmdp_ctrl.readdata"
- type="conduit"
- dir="end">
- <port
- name="coe_readdata_export_to_the_reg_mmdp_ctrl"
- internal="coe_readdata_export" />
- </interface>
<interface name="c0_out_clk" internal="c0.out_clk" type="clock" dir="start">
<port name="mm_clk" internal="out_clk" />
</interface>
@@ -482,15 +412,6 @@
dir="end">
<port name="coe_reset_export_from_the_pio_pps" internal="coe_reset_export" />
</interface>
- <interface
- name="reg_epcs_readdata"
- internal="reg_epcs.readdata"
- type="conduit"
- dir="end">
- <port
- name="coe_readdata_export_to_the_reg_epcs"
- internal="coe_readdata_export" />
- </interface>
<interface
name="pio_pps_readdata"
internal="pio_pps.readdata"
@@ -534,33 +455,6 @@
dir="end">
<port name="coe_reset_export_from_the_reg_wdi" internal="coe_reset_export" />
</interface>
- <interface
- name="reg_dpmm_data_readdata"
- internal="reg_dpmm_data.readdata"
- type="conduit"
- dir="end">
- <port
- name="coe_readdata_export_to_the_reg_dpmm_data"
- internal="coe_readdata_export" />
- </interface>
- <interface
- name="reg_mmdp_ctrl_writedata"
- internal="reg_mmdp_ctrl.writedata"
- type="conduit"
- dir="end">
- <port
- name="coe_writedata_export_from_the_reg_mmdp_ctrl"
- internal="coe_writedata_export" />
- </interface>
- <interface
- name="reg_dpmm_ctrl_address"
- internal="reg_dpmm_ctrl.address"
- type="conduit"
- dir="end">
- <port
- name="coe_address_export_from_the_reg_dpmm_ctrl"
- internal="coe_address_export" />
- </interface>
<interface
name="rom_system_info_clk"
internal="rom_system_info.clk"
@@ -570,13 +464,6 @@
name="coe_clk_export_from_the_rom_system_info"
internal="coe_clk_export" />
</interface>
- <interface
- name="reg_remu_reset"
- internal="reg_remu.reset"
- type="conduit"
- dir="end">
- <port name="coe_reset_export_from_the_reg_remu" internal="coe_reset_export" />
- </interface>
<interface
name="reg_unb_sens_read"
internal="reg_unb_sens.read"
@@ -595,15 +482,6 @@
name="coe_write_export_from_the_reg_unb_sens"
internal="coe_write_export" />
</interface>
- <interface
- name="reg_dpmm_data_clk"
- internal="reg_dpmm_data.clk"
- type="conduit"
- dir="end">
- <port
- name="coe_clk_export_from_the_reg_dpmm_data"
- internal="coe_clk_export" />
- </interface>
<interface
name="reg_unb_sens_clk"
internal="reg_unb_sens.clk"
@@ -620,27 +498,9 @@
name="coe_reg_writedata_export_from_the_avs_eth_0"
internal="coe_reg_writedata_export" />
</interface>
- <interface
- name="reg_dpmm_ctrl_readdata"
- internal="reg_dpmm_ctrl.readdata"
- type="conduit"
- dir="end">
- <port
- name="coe_readdata_export_to_the_reg_dpmm_ctrl"
- internal="coe_readdata_export" />
- </interface>
<interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end">
<port name="coe_read_export_from_the_reg_wdi" internal="coe_read_export" />
</interface>
- <interface
- name="reg_mmdp_data_reset"
- internal="reg_mmdp_data.reset"
- type="conduit"
- dir="end">
- <port
- name="coe_reset_export_from_the_reg_mmdp_data"
- internal="coe_reset_export" />
- </interface>
<interface
name="avs_eth_0_reg_write"
internal="avs_eth_0.reg_write"
@@ -650,31 +510,6 @@
name="coe_reg_write_export_from_the_avs_eth_0"
internal="coe_reg_write_export" />
</interface>
- <interface
- name="reg_mmdp_data_writedata"
- internal="reg_mmdp_data.writedata"
- type="conduit"
- dir="end">
- <port
- name="coe_writedata_export_from_the_reg_mmdp_data"
- internal="coe_writedata_export" />
- </interface>
- <interface
- name="reg_epcs_read"
- internal="reg_epcs.read"
- type="conduit"
- dir="end">
- <port name="coe_read_export_from_the_reg_epcs" internal="coe_read_export" />
- </interface>
- <interface
- name="reg_remu_readdata"
- internal="reg_remu.readdata"
- type="conduit"
- dir="end">
- <port
- name="coe_readdata_export_to_the_reg_remu"
- internal="coe_readdata_export" />
- </interface>
<interface
name="reg_unb_sens_readdata"
internal="reg_unb_sens.readdata"
@@ -714,24 +549,6 @@
name="coe_writedata_export_from_the_rom_system_info"
internal="coe_writedata_export" />
</interface>
- <interface
- name="reg_dpmm_data_address"
- internal="reg_dpmm_data.address"
- type="conduit"
- dir="end">
- <port
- name="coe_address_export_from_the_reg_dpmm_data"
- internal="coe_address_export" />
- </interface>
- <interface
- name="reg_mmdp_ctrl_write"
- internal="reg_mmdp_ctrl.write"
- type="conduit"
- dir="end">
- <port
- name="coe_write_export_from_the_reg_mmdp_ctrl"
- internal="coe_write_export" />
- </interface>
<interface
name="reg_wdi_address"
internal="reg_wdi.address"
@@ -791,13 +608,6 @@
dir="end">
<port name="coe_irq_export_to_the_avs_eth_0" internal="coe_irq_export" />
</interface>
- <interface
- name="reg_epcs_reset"
- internal="reg_epcs.reset"
- type="conduit"
- dir="end">
- <port name="coe_reset_export_from_the_reg_epcs" internal="coe_reset_export" />
- </interface>
<interface
name="rom_system_info_read"
internal="rom_system_info.read"
@@ -830,15 +640,6 @@
name="coe_tse_writedata_export_from_the_avs_eth_0"
internal="coe_tse_writedata_export" />
</interface>
- <interface
- name="reg_mmdp_ctrl_clk"
- internal="reg_mmdp_ctrl.clk"
- type="conduit"
- dir="end">
- <port
- name="coe_clk_export_from_the_reg_mmdp_ctrl"
- internal="coe_clk_export" />
- </interface>
<interface
name="avs_eth_0_tse_readdata"
internal="avs_eth_0.tse_readdata"
@@ -860,33 +661,6 @@
<interface name="clk_0_clk_in" internal="clk_0.clk_in" type="clock" dir="end">
<port name="clk_0" internal="in_clk" />
</interface>
- <interface
- name="reg_dpmm_ctrl_read"
- internal="reg_dpmm_ctrl.read"
- type="conduit"
- dir="end">
- <port
- name="coe_read_export_from_the_reg_dpmm_ctrl"
- internal="coe_read_export" />
- </interface>
- <interface
- name="reg_remu_writedata"
- internal="reg_remu.writedata"
- type="conduit"
- dir="end">
- <port
- name="coe_writedata_export_from_the_reg_remu"
- internal="coe_writedata_export" />
- </interface>
- <interface
- name="reg_dpmm_data_write"
- internal="reg_dpmm_data.write"
- type="conduit"
- dir="end">
- <port
- name="coe_write_export_from_the_reg_dpmm_data"
- internal="coe_write_export" />
- </interface>
<interface
name="reg_unb_sens_writedata"
internal="reg_unb_sens.writedata"
@@ -911,15 +685,6 @@
name="coe_reg_readdata_export_to_the_avs_eth_0"
internal="coe_reg_readdata_export" />
</interface>
- <interface
- name="reg_dpmm_ctrl_reset"
- internal="reg_dpmm_ctrl.reset"
- type="conduit"
- dir="end">
- <port
- name="coe_reset_export_from_the_reg_dpmm_ctrl"
- internal="coe_reset_export" />
- </interface>
<interface
name="pio_debug_wave_external_connection"
internal="pio_debug_wave.external_connection"
@@ -936,15 +701,6 @@
name="coe_tse_read_export_from_the_avs_eth_0"
internal="coe_tse_read_export" />
</interface>
- <interface
- name="reg_dpmm_data_writedata"
- internal="reg_dpmm_data.writedata"
- type="conduit"
- dir="end">
- <port
- name="coe_writedata_export_from_the_reg_dpmm_data"
- internal="coe_writedata_export" />
- </interface>
<interface
name="reg_wdi_writedata"
internal="reg_wdi.writedata"
@@ -972,15 +728,6 @@
name="coe_read_export_from_the_pio_system_info"
internal="coe_read_export" />
</interface>
- <interface
- name="reg_mmdp_data_clk"
- internal="reg_mmdp_data.clk"
- type="conduit"
- dir="end">
- <port
- name="coe_clk_export_from_the_reg_mmdp_data"
- internal="coe_clk_export" />
- </interface>
<interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end">
<port name="coe_clk_export_from_the_reg_wdi" internal="coe_clk_export" />
</interface>
@@ -993,34 +740,6 @@
name="coe_ram_readdata_export_to_the_avs_eth_0"
internal="coe_ram_readdata_export" />
</interface>
- <interface
- name="reg_remu_write"
- internal="reg_remu.write"
- type="conduit"
- dir="end">
- <port name="coe_write_export_from_the_reg_remu" internal="coe_write_export" />
- </interface>
- <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end">
- <port name="coe_clk_export_from_the_reg_epcs" internal="coe_clk_export" />
- </interface>
- <interface
- name="reg_mmdp_data_read"
- internal="reg_mmdp_data.read"
- type="conduit"
- dir="end">
- <port
- name="coe_read_export_from_the_reg_mmdp_data"
- internal="coe_read_export" />
- </interface>
- <interface
- name="reg_epcs_writedata"
- internal="reg_epcs.writedata"
- type="conduit"
- dir="end">
- <port
- name="coe_writedata_export_from_the_reg_epcs"
- internal="coe_writedata_export" />
- </interface>
<interface
name="pio_wdi_external_connection"
internal="pio_wdi.external_connection"
@@ -1028,27 +747,6 @@
dir="end">
<port name="out_port_from_the_pio_wdi" internal="out_port" />
</interface>
- <interface
- name="reg_dpmm_data_reset"
- internal="reg_dpmm_data.reset"
- type="conduit"
- dir="end">
- <port
- name="coe_reset_export_from_the_reg_dpmm_data"
- internal="coe_reset_export" />
- </interface>
- <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end">
- <port name="coe_clk_export_from_the_reg_remu" internal="coe_clk_export" />
- </interface>
- <interface
- name="reg_mmdp_ctrl_read"
- internal="reg_mmdp_ctrl.read"
- type="conduit"
- dir="end">
- <port
- name="coe_read_export_from_the_reg_mmdp_ctrl"
- internal="coe_read_export" />
- </interface>
<interface
name="avs_eth_0_clk"
internal="avs_eth_0.clk"
@@ -1056,22 +754,6 @@
dir="end">
<port name="coe_clk_export_from_the_avs_eth_0" internal="coe_clk_export" />
</interface>
- <interface
- name="reg_mmdp_ctrl_address"
- internal="reg_mmdp_ctrl.address"
- type="conduit"
- dir="end">
- <port
- name="coe_address_export_from_the_reg_mmdp_ctrl"
- internal="coe_address_export" />
- </interface>
- <interface
- name="reg_epcs_write"
- internal="reg_epcs.write"
- type="conduit"
- dir="end">
- <port name="coe_write_export_from_the_reg_epcs" internal="coe_write_export" />
- </interface>
<interface
name="rom_system_info_readdata"
internal="rom_system_info.readdata"
@@ -1081,24 +763,6 @@
name="coe_readdata_export_to_the_rom_system_info"
internal="coe_readdata_export" />
</interface>
- <interface
- name="reg_mmdp_ctrl_reset"
- internal="reg_mmdp_ctrl.reset"
- type="conduit"
- dir="end">
- <port
- name="coe_reset_export_from_the_reg_mmdp_ctrl"
- internal="coe_reset_export" />
- </interface>
- <interface
- name="reg_mmdp_data_readdata"
- internal="reg_mmdp_data.readdata"
- type="conduit"
- dir="end">
- <port
- name="coe_readdata_export_to_the_reg_mmdp_data"
- internal="coe_readdata_export" />
- </interface>
<interface
name="reg_wdi_write"
internal="reg_wdi.write"
@@ -1136,24 +800,6 @@
name="coe_writedata_export_from_the_pio_pps"
internal="coe_writedata_export" />
</interface>
- <interface
- name="reg_epcs_address"
- internal="reg_epcs.address"
- type="conduit"
- dir="end">
- <port
- name="coe_address_export_from_the_reg_epcs"
- internal="coe_address_export" />
- </interface>
- <interface
- name="reg_dpmm_data_read"
- internal="reg_dpmm_data.read"
- type="conduit"
- dir="end">
- <port
- name="coe_read_export_from_the_reg_dpmm_data"
- internal="coe_read_export" />
- </interface>
<interface
name="rom_system_info_reset"
internal="rom_system_info.reset"
@@ -1172,24 +818,6 @@
name="coe_tse_waitrequest_export_to_the_avs_eth_0"
internal="coe_tse_waitrequest_export" />
</interface>
- <interface
- name="reg_dpmm_ctrl_writedata"
- internal="reg_dpmm_ctrl.writedata"
- type="conduit"
- dir="end">
- <port
- name="coe_writedata_export_from_the_reg_dpmm_ctrl"
- internal="coe_writedata_export" />
- </interface>
- <interface
- name="reg_mmdp_data_address"
- internal="reg_mmdp_data.address"
- type="conduit"
- dir="end">
- <port
- name="coe_address_export_from_the_reg_mmdp_data"
- internal="coe_address_export" />
- </interface>
<interface
name="reg_unb_sens_address"
internal="reg_unb_sens.address"
@@ -1199,15 +827,6 @@
name="coe_address_export_from_the_reg_unb_sens"
internal="coe_address_export" />
</interface>
- <interface
- name="reg_dpmm_ctrl_clk"
- internal="reg_dpmm_ctrl.clk"
- type="conduit"
- dir="end">
- <port
- name="coe_clk_export_from_the_reg_dpmm_ctrl"
- internal="coe_clk_export" />
- </interface>
<interface
name="avs_eth_0_reg_address"
internal="avs_eth_0.reg_address"
@@ -1226,24 +845,6 @@
name="coe_address_export_from_the_rom_system_info"
internal="coe_address_export" />
</interface>
- <interface
- name="reg_mmdp_data_write"
- internal="reg_mmdp_data.write"
- type="conduit"
- dir="end">
- <port
- name="coe_write_export_from_the_reg_mmdp_data"
- internal="coe_write_export" />
- </interface>
- <interface
- name="reg_remu_address"
- internal="reg_remu.address"
- type="conduit"
- dir="end">
- <port
- name="coe_address_export_from_the_reg_remu"
- internal="coe_address_export" />
- </interface>
<interface
name="altpll_0_areset_conduit"
internal="altpll_0.areset_conduit"
@@ -1258,15 +859,6 @@
dir="end">
<port name="locked_from_the_altpll_0" internal="locked" />
</interface>
- <interface
- name="reg_dpmm_ctrl_write"
- internal="reg_dpmm_ctrl.write"
- type="conduit"
- dir="end">
- <port
- name="coe_write_export_from_the_reg_dpmm_ctrl"
- internal="coe_write_export" />
- </interface>
<interface
name="avs_eth_0_ram_writedata"
internal="avs_eth_0.ram_writedata"
@@ -1284,12 +876,75 @@
<port name="c3_from_the_altpll_0" internal="c3" />
</interface>
<interface
- name="reg_remu_read"
- internal="reg_remu.read"
+ name="ram_diag_data_buf_readdata"
+ internal="ram_diag_data_buf.readdata"
type="conduit"
- dir="end">
- <port name="coe_read_export_from_the_reg_remu" internal="coe_read_export" />
- </interface>
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_read"
+ internal="ram_diag_data_buf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_writedata"
+ internal="ram_diag_data_buf.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_write"
+ internal="ram_diag_data_buf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_address"
+ internal="ram_diag_data_buf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_clk"
+ internal="ram_diag_data_buf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buf_reset"
+ internal="ram_diag_data_buf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_readdata"
+ internal="reg_diag_data_buf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_read"
+ internal="reg_diag_data_buf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_writedata"
+ internal="reg_diag_data_buf.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_write"
+ internal="reg_diag_data_buf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_address"
+ internal="reg_diag_data_buf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_clk"
+ internal="reg_diag_data_buf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buf_reset"
+ internal="reg_diag_data_buf.reset"
+ type="conduit"
+ dir="end" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
<parameter name="clockFrequencyKnown" value="true" />
@@ -1302,7 +957,7 @@
enabled="1"
name="onchip_memory2_0">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
- <parameter name="autoInitializationFileName">sopc_unb1_minimal_onchip_memory2_0</parameter>
+ <parameter name="autoInitializationFileName">qsys_unb1_correlator_onchip_memory2_0</parameter>
<parameter name="blockType" value="M144K" />
<parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Stratix IV" />
@@ -1578,36 +1233,6 @@ q]]></parameter>
<module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
<parameter name="AUTO_MM_CLOCK_RATE" value="50000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_remu">
- <parameter name="g_adr_w" value="3" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_epcs">
- <parameter name="g_adr_w" value="3" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_ctrl">
- <parameter name="g_adr_w" value="1" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_data">
- <parameter name="g_adr_w" value="1" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_ctrl">
- <parameter name="g_adr_w" value="1" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_data">
- <parameter name="g_adr_w" value="1" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
<module kind="altera_nios2_qsys" version="11.1" enabled="1" name="cpu_0">
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="setting_showInternalSettings" value="false" />
@@ -1687,7 +1312,7 @@ q]]></parameter>
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_lineSize" value="32" />
<parameter name="instAddrWidth" value="18" />
- <parameter name="dataAddrWidth" value="18" />
+ <parameter name="dataAddrWidth" value="20" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
@@ -1697,7 +1322,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_remu.mem' start='0x100' end='0x120' /><slave name='reg_epcs.mem' start='0x120' end='0x140' /><slave name='altpll_0.pll_slave' start='0x140' end='0x150' /><slave name='pio_debug_wave.s1' start='0x150' end='0x160' /><slave name='pio_wdi.s1' start='0x160' end='0x170' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x170' end='0x178' /><slave name='pio_pps.mem' start='0x178' end='0x180' /><slave name='reg_dpmm_ctrl.mem' start='0x180' end='0x188' /><slave name='reg_dpmm_data.mem' start='0x188' end='0x190' /><slave name='reg_mmdp_ctrl.mem' start='0x190' end='0x198' /><slave name='reg_mmdp_data.mem' start='0x198' end='0x1A0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='altpll_0.pll_slave' start='0x100' end='0x110' /><slave name='pio_debug_wave.s1' start='0x110' end='0x120' /><slave name='pio_wdi.s1' start='0x120' end='0x130' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x130' end='0x138' /><slave name='pio_pps.mem' start='0x138' end='0x140' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='reg_diag_data_buf.mem' start='0x5000' end='0x6000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buf.mem' start='0x80000' end='0x100000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="50000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -1717,6 +1342,24 @@ q]]></parameter>
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_data_buf">
+ <parameter name="g_adr_w" value="17" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_data_buf">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -1755,7 +1398,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0170" />
+ <parameter name="baseAddress" value="0x0130" />
</connection>
<connection
kind="interrupt"
@@ -1770,7 +1413,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="altpll_0.pll_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0140" />
+ <parameter name="baseAddress" value="0x0100" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
<connection
@@ -1795,7 +1438,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_debug_wave.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0150" />
+ <parameter name="baseAddress" value="0x0110" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
<connection
@@ -1804,7 +1447,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0160" />
+ <parameter name="baseAddress" value="0x0120" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
<connection
@@ -1864,7 +1507,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0178" />
+ <parameter name="baseAddress" value="0x0138" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
<connection
@@ -1907,76 +1550,6 @@ q]]></parameter>
end="avs_eth_0.interrupt">
<parameter name="irqNumber" value="2" />
</connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_remu.system" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_remu.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
- </connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_epcs.system" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_epcs.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0120" />
- </connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dpmm_ctrl.system" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_dpmm_ctrl.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0180" />
- </connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dpmm_data.system" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_dpmm_data.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0188" />
- </connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_mmdp_ctrl.system" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_mmdp_ctrl.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0190" />
- </connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_mmdp_data.system" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_mmdp_data.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0198" />
- </connection>
<connection
kind="reset"
version="11.1"
@@ -2101,71 +1674,47 @@ q]]></parameter>
kind="reset"
version="11.1"
start="clk_0.clk_reset"
- end="reg_remu.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_remu.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_0.clk_reset"
- end="reg_epcs.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_epcs.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_0.clk_reset"
- end="reg_dpmm_ctrl.system_reset" />
+ end="cpu_0.reset_n" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_dpmm_ctrl.system_reset" />
+ end="cpu_0.reset_n" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="c0.in_clk" />
<connection
- kind="reset"
+ kind="clock"
version="11.1"
- start="clk_0.clk_reset"
- end="reg_dpmm_data.system_reset" />
+ start="altpll_0.c0"
+ end="ram_diag_data_buf.system" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_dpmm_data.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_0.clk_reset"
- end="reg_mmdp_ctrl.system_reset" />
+ end="ram_diag_data_buf.system_reset" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_mmdp_ctrl.system_reset" />
+ end="reg_diag_data_buf.system_reset" />
<connection
- kind="reset"
- version="11.1"
- start="clk_0.clk_reset"
- end="reg_mmdp_data.system_reset" />
- <connection
- kind="reset"
+ kind="avalon"
version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_mmdp_data.system_reset" />
+ start="cpu_0.data_master"
+ end="ram_diag_data_buf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00080000" />
+ </connection>
<connection
- kind="reset"
+ kind="avalon"
version="11.1"
- start="clk_0.clk_reset"
- end="cpu_0.reset_n" />
+ start="cpu_0.data_master"
+ end="reg_diag_data_buf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5000" />
+ </connection>
<connection
- kind="reset"
+ kind="clock"
version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="cpu_0.reset_n" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="c0.in_clk" />
+ start="altpll_0.c0"
+ end="reg_diag_data_buf.system" />
</system>
diff --git a/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index 7ed1a7016ee250ec367250c2ba8c4fe092c3910e..fef5b02dd1a41687e50d32c364a5599ff0f965a0 100644
--- a/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -260,7 +260,8 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buf_write_export : out std_logic; -- export
reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export
- reg_diag_data_buf_clk_export : out std_logic -- export
+ reg_diag_data_buf_clk_export : out std_logic; -- export
+ reg_diag_data_buf_reset_export : out std_logic -- export
);
end component qsys_unb1_correlator;
BEGIN
@@ -389,7 +390,23 @@ BEGIN
coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ ram_diag_data_buf_readdata_export => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buf_read_export => ram_diag_data_buf_mosi.rd,
+ ram_diag_data_buf_writedata_export => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buf_write_export => ram_diag_data_buf_mosi.wr,
+ ram_diag_data_buf_address_export => ram_diag_data_buf_mosi.address,
+ ram_diag_data_buf_clk_export => OPEN,
+ ram_diag_data_buf_reset_export => OPEN,
+
+ reg_diag_data_buf_readdata_export => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buf_read_export => reg_diag_data_buf_mosi.rd,
+ reg_diag_data_buf_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buf_write_export => reg_diag_data_buf_mosi.wr,
+ reg_diag_data_buf_address_export => reg_diag_data_buf_mosi.address,
+ reg_diag_data_buf_clk_export => OPEN,
+ reg_diag_data_buf_reset_export => OPEN
);
END GENERATE;