From e052f7b3bcb2c99c2a1086699991588b29c95584 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 14 Nov 2014 11:58:17 +0000
Subject: [PATCH] Added PLL for 10G and reset controller for 1 tranceiver to be
used with phy_10gbase_r.
---
.../ip_arria10/transceiver_pll_10g/hdllib.cfg | 16 ++
.../transceiver_pll_10g/ip/compile_ip.tcl | 51 ++++++
.../transceiver_pll_10g/ip/generate_ip.sh | 44 +++++
.../transceiver_pll_10g/ip/hdllib.cfg | 17 ++
.../ip/ip_arria10_transceiver_pll_10g.qsys | 152 ++++++++++++++++
.../ip_arria10_transceiver_pll_10g_top.vhd | 57 ++++++
.../transceiver_reset_controller_1/hdllib.cfg | 16 ++
.../ip/compile_ip.tcl | 43 +++++
.../ip/generate_ip.sh | 44 +++++
.../ip/hdllib.cfg | 17 ++
...rria10_transceiver_reset_controller_1.qsys | 171 ++++++++++++++++++
...a10_transceiver_reset_controller_1_top.vhd | 75 ++++++++
12 files changed, 703 insertions(+)
create mode 100644 libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10/transceiver_pll_10g/ip/compile_ip.tcl
create mode 100755 libraries/technology/ip_arria10/transceiver_pll_10g/ip/generate_ip.sh
create mode 100644 libraries/technology/ip_arria10/transceiver_pll_10g/ip/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10/transceiver_pll_10g/ip/ip_arria10_transceiver_pll_10g.qsys
create mode 100644 libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd
create mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/compile_ip.tcl
create mode 100755 libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/generate_ip.sh
create mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/ip_arria10_transceiver_reset_controller_1.qsys
create mode 100644 libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1_top.vhd
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
new file mode 100644
index 0000000000..73b55bbfbb
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_transceiver_pll_10g
+hdl_library_clause_name = ip_arria10_transceiver_pll_10g_lib
+hdl_lib_uses = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ ip_arria10_transceiver_pll_10g_top.vhd
+
+test_bench_files =
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+ altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/ip/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/ip/compile_ip.tcl
new file mode 100644
index 0000000000..fa418c69c2
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/ip/compile_ip.tcl
@@ -0,0 +1,51 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_pll_10g/ip/generated/sim"
+
+vlib ./work/
+
+vmap ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 ./work/
+
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vcom "$IP_DIR/ip_arria10_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/ip/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_pll_10g/ip/generate_ip.sh
new file mode 100755
index 0000000000..d52cddda76
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/ip/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_transceiver_pll_10g.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/ip/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/ip/hdllib.cfg
new file mode 100644
index 0000000000..4cb86aa2c2
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/ip/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+hdl_library_clause_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+hdl_lib_uses =
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/ip/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+
+quartus_qip_files =
+ generated/ip_arria10_transceiver_pll_10g.qip
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/ip/ip_arria10_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10/transceiver_pll_10g/ip/ip_arria10_transceiver_pll_10g.qsys
new file mode 100644
index 0000000000..a6a3843d48
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/ip/ip_arria10_transceiver_pll_10g.qsys
@@ -0,0 +1,152 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element xcvr_atx_pll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_atx_pll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_atx_pll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <interface
+ name="tx_serial_clk"
+ internal="xcvr_atx_pll_a10_0.tx_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="tx_serial_clk" internal="tx_serial_clk" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_atx_pll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_atx_pll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <module
+ kind="altera_xcvr_atx_pll_a10"
+ version="14.0"
+ enabled="1"
+ name="xcvr_atx_pll_a10_0"
+ autoexport="1">
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="enable_pll_reconfig" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_param_vals1" value="" />
+ <parameter name="rcfg_param_vals2" value="" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="test_mode" value="0" />
+ <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+ <parameter name="enable_debug_ports_parameters" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="message_level" value="error" />
+ <parameter name="prot_mode" value="Basic" />
+ <parameter name="bw_sel" value="low" />
+ <parameter name="refclk_cnt" value="1" />
+ <parameter name="refclk_index" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+ <parameter name="enable_8G_path" value="1" />
+ <parameter name="enable_16G_path" value="0" />
+ <parameter name="enable_pcie_clk" value="0" />
+ <parameter name="enable_cascade_out" value="0" />
+ <parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="select_manual_config" value="0" />
+ <parameter name="set_output_clock_frequency" value="5156.25" />
+ <parameter name="enable_fractional" value="0" />
+ <parameter name="set_auto_reference_clock_frequency" value="644.53125" />
+ <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_fref_clock_frequency" value="100.0" />
+ <parameter name="set_m_counter" value="1" />
+ <parameter name="set_ref_clk_div" value="1" />
+ <parameter name="set_l_counter" value="2" />
+ <parameter name="set_k_counter" value="1" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="AUTO_PLL_REFCLK0_CLOCK_RATE" value="0" />
+ <parameter name="AUTO_PLL_REFCLK1_CLOCK_RATE" value="-1" />
+ <parameter name="AUTO_PLL_REFCLK2_CLOCK_RATE" value="-1" />
+ <parameter name="AUTO_PLL_REFCLK3_CLOCK_RATE" value="-1" />
+ <parameter name="AUTO_PLL_REFCLK4_CLOCK_RATE" value="-1" />
+ <parameter name="AUTO_RECONFIG_CLK0_CLOCK_RATE" value="-1" />
+ <parameter name="AUTO_RECONFIG_CLK1_CLOCK_RATE" value="-1" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd b/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd
new file mode 100644
index 0000000000..8b841c41ed
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd
@@ -0,0 +1,57 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Wrapper for generated ip_arria10_transceiver_pll_10g.vhd
+-- Description:
+-- This wrapper avoids the need to vmap the ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 library
+-- in the technology independent library that instantiate this IP.
+-- Remarks:
+-- . Manually created from generated ip_arria10_transceiver_pll_10g.vhd.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140;
+
+entity ip_arria10_transceiver_pll_10g_top is
+ port (
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
+ tx_serial_clk : out std_logic; -- tx_serial_clk.clk
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_cal_busy : out std_logic -- pll_cal_busy.pll_cal_busy
+ );
+end ip_arria10_transceiver_pll_10g_top;
+
+architecture str of ip_arria10_transceiver_pll_10g_top is
+begin
+
+ u_ip_arria10_transceiver_pll_10g : entity ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140.ip_arria10_transceiver_pll_10g
+ port map (
+ pll_powerdown => pll_powerdown, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => pll_refclk0 , -- pll_refclk0.clk
+ tx_serial_clk => tx_serial_clk, -- tx_serial_clk.clk
+ pll_locked => pll_locked , -- pll_locked.pll_locked
+ pll_cal_busy => pll_cal_busy -- pll_cal_busy.pll_cal_busy
+ );
+
+end str;
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
new file mode 100644
index 0000000000..72783508d7
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_transceiver_reset_controller_1
+hdl_library_clause_name = ip_arria10_transceiver_reset_controller_1_lib
+hdl_lib_uses = ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ ip_arria10_transceiver_reset_controller_1_top.vhd
+
+test_bench_files =
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+ altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/compile_ip.tcl
new file mode 100644
index 0000000000..3d22854126
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/compile_ip.tcl
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/generated/sim"
+
+vlib ./work/
+
+vmap ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 ./work/
+
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vcom "$IP_DIR/ip_arria10_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/generate_ip.sh b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/generate_ip.sh
new file mode 100755
index 0000000000..c6562df088
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_transceiver_reset_controller_1.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/hdllib.cfg
new file mode 100644
index 0000000000..c85aedf94c
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+hdl_library_clause_name = ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+hdl_lib_uses =
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+
+quartus_qip_files =
+ generated/ip_arria10_transceiver_reset_controller_1.qip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/ip_arria10_transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/ip_arria10_transceiver_reset_controller_1.qsys
new file mode 100644
index 0000000000..15e68b6e26
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip/ip_arria10_transceiver_reset_controller_1.qsys
@@ -0,0 +1,171 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element xcvr_reset_control_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="xcvr_reset_control_0.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="reset"
+ internal="xcvr_reset_control_0.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_reset_control_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_reset_control_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_reset_control_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="xcvr_reset_control_0.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_reset_control_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="xcvr_reset_control_0.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_reset_control_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_reset_control_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_reset_control_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="xcvr_reset_control_0.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_reset_control_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_reset_control_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <module
+ kind="altera_xcvr_reset_control"
+ version="14.0"
+ enabled="1"
+ name="xcvr_reset_control_0"
+ autoexport="1">
+ <parameter name="CHANNELS" value="1" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="200" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="gui_tx_auto_reset" value="1" />
+ <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="T_PLL_LOCK_HYST" value="0" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="T_RX_ANALOGRESET" value="40" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="AUTO_CLOCK_CLOCK_RATE" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1_top.vhd b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1_top.vhd
new file mode 100644
index 0000000000..f80430de41
--- /dev/null
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1_top.vhd
@@ -0,0 +1,75 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Wrapper for generated ip_arria10_transceiver_reset_controller_1.vhd
+-- Description:
+-- This wrapper avoids the need to vmap the ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 library
+-- in the technology independent library that instantiate this IP.
+-- Remarks:
+-- . Manually created from generated ip_arria10_transceiver_reset_controller_1.vhd.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140;
+
+entity ip_arria10_transceiver_reset_controller_1_top is
+ port (
+ clock : in std_logic := '0'; -- clock.clk
+ reset : in std_logic := '0'; -- reset.reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ tx_analogreset : out std_logic_vector(0 downto 0); -- tx_analogreset.tx_analogreset
+ tx_digitalreset : out std_logic_vector(0 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(0 downto 0); -- tx_ready.tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset.rx_analogreset
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_ready : out std_logic_vector(0 downto 0); -- rx_ready.rx_ready
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0') -- rx_cal_busy.rx_cal_busy
+ );
+end ip_arria10_transceiver_reset_controller_1_top;
+
+architecture str of ip_arria10_transceiver_reset_controller_1_top is
+begin
+
+ u_ip_arria10_transceiver_reset_controller_1 : entity ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140.ip_arria10_transceiver_reset_controller_1
+ port map (
+ clock => clock , -- clock.clk
+ reset => reset , -- reset.reset
+ pll_powerdown => pll_powerdown , -- pll_powerdown.pll_powerdown
+ tx_analogreset => tx_analogreset , -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset , -- tx_digitalreset.tx_digitalreset
+ tx_ready => tx_ready , -- tx_ready.tx_ready
+ pll_locked => pll_locked , -- pll_locked.pll_locked
+ pll_select => pll_select , -- pll_select.pll_select
+ tx_cal_busy => tx_cal_busy , -- tx_cal_busy.tx_cal_busy
+ rx_analogreset => rx_analogreset , -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset , -- rx_digitalreset.rx_digitalreset
+ rx_ready => rx_ready , -- rx_ready.rx_ready
+ rx_is_lockedtodata => rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_cal_busy => rx_cal_busy -- rx_cal_busy.rx_cal_busy
+ );
+
+end str;
--
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