From e016487147eda8266c5308afb681a56e9c26c263 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 12 Jun 2018 06:31:14 +0000
Subject: [PATCH] Made tb self stopping and added to regression test.
---
.../apertif_unb1_correlator_full/hdllib.cfg | 3 +
.../tb_apertif_unb1_correlator_full.vhd | 118 ++++++++++--------
2 files changed, 66 insertions(+), 55 deletions(-)
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg
index 7c6149f0de..ce6399b0c4 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg
@@ -22,6 +22,9 @@ synth_files =
test_bench_files =
tb_apertif_unb1_correlator_full.vhd
+regression_test_vhdl =
+ tb_apertif_unb1_correlator_full.vhd
+
[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL/libraries/dsp/filter/src/hex hex
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd
index 1a6259f7de..7fac3f0c0c 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd
@@ -25,11 +25,11 @@
-- Description:
-- Must use c_sim = TRUE, because then nof block per sync will be << 800000
-- which is necessary to avoid PC out-of-memory due to large DB when the tb
--- is laoded in the simulator.
+-- is loaded in the simulator.
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 10 # check that the hierarchy for g_design_name is complete
--- > run 1 us # check that design can simulate
+-- > run -a # check that design can simulate some us without error
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
@@ -55,12 +55,15 @@ ARCHITECTURE tb OF tb_apertif_unb1_correlator_full IS
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
CONSTANT c_sa_clk_period : TIME := 6.4 ns;
- CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
-
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+
-- DUT
- SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL sa_clk : STD_LOGIC := '1';
@@ -91,7 +94,7 @@ BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2;
@@ -104,59 +107,64 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_apertif_unb1_correlator_full : ENTITY work.apertif_unb1_correlator_full
- GENERIC MAP (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- PORT MAP (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
- SB_CLK => sa_clk,
-
- -- Serial I/O
- SI_FN_0_RX => si_fn_0_tx,
- SI_FN_1_RX => si_fn_0_tx,
- SI_FN_2_RX => si_fn_0_tx,
- SI_FN_3_RX => si_fn_0_tx,
-
- FN_BN_0_RX => fn_bn_0_tx,
- FN_BN_0_TX => fn_bn_0_tx,
-
- FN_BN_1_RX => fn_bn_1_tx,
- FN_BN_1_tX => fn_bn_1_tx,
-
- FN_BN_2_RX => fn_bn_2_tx,
- FN_BN_2_TX => fn_bn_2_tx,
-
- FN_BN_3_RX => fn_bn_3_tx,
- FN_BN_3_TX => fn_bn_3_tx
- );
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+ SB_CLK => sa_clk,
+
+ -- Serial I/O
+ SI_FN_0_RX => si_fn_0_tx,
+ SI_FN_1_RX => si_fn_0_tx,
+ SI_FN_2_RX => si_fn_0_tx,
+ SI_FN_3_RX => si_fn_0_tx,
+
+ FN_BN_0_RX => fn_bn_0_tx,
+ FN_BN_0_TX => fn_bn_0_tx,
+
+ FN_BN_1_RX => fn_bn_1_tx,
+ FN_BN_1_tX => fn_bn_1_tx,
+
+ FN_BN_2_RX => fn_bn_2_tx,
+ FN_BN_2_TX => fn_bn_2_tx,
+
+ FN_BN_3_RX => fn_bn_3_tx,
+ FN_BN_3_TX => fn_bn_3_tx
+ );
+
+ -- Check that design can simulate some us without error
+ sim_done <= '0', '1' AFTER 1 us;
+
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
END tb;
--
GitLab