From dfcbe20045e471cccc3e3950dd5472384eed0ac1 Mon Sep 17 00:00:00 2001
From: JobvanWee <wee@astron.nl>
Date: Wed, 4 May 2022 14:24:11 +0200
Subject: [PATCH] Save
---
.../src/vhdl/lofar2_unb2c_ddrctrl.vhd | 22 ++---
.../tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd | 96 ++++++++++++-------
.../libraries/ddrctrl/src/vhdl/ddrctrl.vhd | 2 +-
.../vhdl/ddrctrl_input_address_counter.vhd | 1 -
4 files changed, 69 insertions(+), 52 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
index c0cb52deb5..4348e204ab 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -94,7 +94,7 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
-- diag_data_buffer
CONSTANT c_data_type : t_diag_data_type_enum := e_data;
- CONSTANT c_buf_nof_words : NATURAL := 1024;
+ CONSTANT c_buf_nof_words : NATURAL := c_bs_block_size;
-- diag_bsn_buffer
CONSTANT c_bsn_type : t_diag_data_type_enum := e_real;
@@ -199,7 +199,7 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
-- ddrctrl
SIGNAL st_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL out_siso : t_dp_siso;
- SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL phy3_io : t_tech_ddr3_phy_io;
SIGNAL phy3_ou : t_tech_ddr3_phy_ou;
SIGNAL phy4_io : t_tech_ddr4_phy_io;
@@ -382,12 +382,11 @@ BEGIN
-- DB settings
g_data_type => c_data_type,
- g_data_w => c_data_w,
+ g_data_w => c_word_w,
g_buf_nof_data => c_buf_nof_words,
g_buf_use_sync => FALSE,
g_use_steps => FALSE,
- g_nof_steps => c_diag_seq_rx_reg_nof_steps,
- g_seq_dat_w => c_data_w
+ g_nof_steps => c_diag_seq_rx_reg_nof_steps
)
PORT MAP (
-- Memory-mapped clock domain
@@ -400,14 +399,11 @@ BEGIN
ram_data_buf_mosi => ram_data_buf_mosi,
ram_data_buf_miso => ram_data_buf_miso,
- reg_rx_seq_mosi => reg_rx_seq_data_mosi,
- reg_rx_seq_miso => reg_rx_seq_data_miso,
-
-- Streaming clock domain
dp_rst => st_rst,
dp_clk => st_clk,
- in_sync => PPS,
+ in_sync => st_pps,
in_sosi_arr => out_sosi_arr,
out_wr_done_arr => out_wr_data_done_arr
);
@@ -426,8 +422,7 @@ BEGIN
g_buf_nof_data => c_buf_nof_words,
g_buf_use_sync => FALSE,
g_use_steps => FALSE,
- g_nof_steps => c_diag_seq_rx_reg_nof_steps,
- g_seq_dat_w => c_data_w
+ g_nof_steps => c_diag_seq_rx_reg_nof_steps
)
PORT MAP (
-- Memory-mapped clock domain
@@ -440,14 +435,11 @@ BEGIN
ram_data_buf_mosi => ram_bsn_buf_mosi,
ram_data_buf_miso => ram_bsn_buf_miso,
- reg_rx_seq_mosi => reg_rx_seq_bsn_mosi,
- reg_rx_seq_miso => reg_rx_seq_bsn_miso,
-
-- Streaming clock domain
dp_rst => st_rst,
dp_clk => st_clk,
- in_sync => PPS,
+ in_sync => st_pps,
in_sosi_arr => out_sosi_arr,
out_wr_done_arr => out_wr_bsn_done_arr
);
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index ed00b17ac3..07cd68479c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -69,6 +69,7 @@ END tb_lofar2_unb2c_ddrctrl;
ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_rd_data_w : NATURAL := 32;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 3; -- Node 3
@@ -96,17 +97,18 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
CONSTANT c_mm_file_reg_rx_seq_bsn : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_RX_SEQ_BSN";
-- c_check_vector
- CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr4_sim_16k;
- CONSTANT c_ctrl_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr); -- 576
- CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w(c_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the address vector length
- CONSTANT c_block_size : NATURAL := 1024;
- CONSTANT c_nof_streams : NATURAL := 12;
- CONSTANT c_data_w : NATURAL := 14;
- CONSTANT c_bim : NATURAL := (c_max_adr*c_ctrl_data_w)/(c_block_size*c_nof_streams*c_data_w); -- the amount of whole blocks that fit in memory.
+ CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr4_sim_16k;
+ CONSTANT c_ctrl_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr); -- 576
+ CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w(c_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the address vector length
+ CONSTANT c_block_size : NATURAL := 1024;
+ CONSTANT c_nof_streams : NATURAL := 12;
+ CONSTANT c_data_w : NATURAL := 14;
+ CONSTANT c_bim : NATURAL := (c_max_adr*c_ctrl_data_w)/(c_block_size*c_nof_streams*c_data_w); -- the amount of whole blocks that fit in memory.
+ CONSTANT c_nof_st_in_mem : NATURAL := c_bim*c_block_size;
- CONSTANT c_check_vector : STD_LOGIC_VECTOR(c_ctrl_data_w*c_bim*c_block_size-1 DOWNTO 0) := (OTHERS => '0'); -- the sinewave of one stream for c_bim length
+ CONSTANT c_check_vector : STD_LOGIC_VECTOR(c_ctrl_data_w*c_bim*c_block_size-1 DOWNTO 0) := (OTHERS => '0'); -- the sinewave of one stream for c_bim length
-- BSN
CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
@@ -116,32 +118,35 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
-- WG
CONSTANT c_wg_phase : REAL := 0.0; -- WG phase in degrees
CONSTANT c_wg_freq : REAL := 160.0; -- WG freq
- CONSTANT c_wg_ampl : REAL := 20.0; -- WG amplitude
+ CONSTANT c_wg_ampl : NATURAL := NATURAL(0.125*REAL(c_sdp_FS_adc)); -- in number of lsb
CONSTANT c_bsn_start_wg : NATURAL := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
-
+
-- DUT
- SIGNAL st_clk : STD_LOGIC := '0';
- SIGNAL tb_clk : STD_LOGIC := '0';
- SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL pps : STD_LOGIC := '0';
- SIGNAL pps_rst : STD_LOGIC := '0';
- SIGNAL rd_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '0');
-
- SIGNAL WDI : STD_LOGIC;
- SIGNAL INTA : STD_LOGIC;
- SIGNAL INTB : STD_LOGIC;
-
- SIGNAL eth_clk : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL eth_txp : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL eth_rxp : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL st_clk : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_rd_data_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL sosi_out_data : STD_LOGIC_VECTOR(c_rd_data_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL sosi_out_bsn : STD_LOGIC_VECTOR(c_rd_data_w-1 DOWNTO 0) := (OTHERS => '0');
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(1 DOWNTO 0);
- SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0) := c_version;
- SIGNAL ID : STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0) := c_id;
- SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
- SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
BEGIN
@@ -200,6 +205,9 @@ BEGIN
);
+ -- WG
+
+
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
@@ -213,6 +221,7 @@ BEGIN
BEGIN
+ WAIT FOR 1 us;
----------------------------------------------------------------------------
-- Enable BSN
----------------------------------------------------------------------------
@@ -238,7 +247,7 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+1, INTEGER(c_wg_phase), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+2, INTEGER(c_wg_freq), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+3, INTEGER(c_wg_ampl), tb_clk); -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+3, INTEGER(REAL(c_wg_ampl)*c_sdp_wg_ampl_lsb), tb_clk); -- ampl
END LOOP;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
-- Read current BSN
@@ -253,12 +262,29 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
- WAIT FOR c_mm_clk_period*100000;
- mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1**32, tb_clk);
+ WAIT FOR c_mm_clk_period*26000;
+ mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
WAIT FOR c_mm_clk_period*16;
- mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
- WAIT FOR c_mm_clk_period*50000;
+ mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
+ WAIT FOR c_mm_clk_period*30000;
+
+
+ FOR I IN 0 TO c_bim-1 LOOP
+ -- mmf_mm_bus_rd(c_mm_file_reg_data_buf, 0, sosi_out_data(c_rd_data_w-1 DOWNTO 0), tb_clk);
+ -- mmf_mm_bus_rd( c_mm_file_reg_bsn_buf, 0, sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+ FOR J IN 0 TO c_nof_streams-1 LOOP
+ FOR K IN 0 TO c_block_size-1 LOOP
+ mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J*c_block_size)+K , sosi_out_data(c_rd_data_w-1 DOWNTO 0), tb_clk);
+ sosi_out_data(c_rd_data_w-1 DOWNTO c_data_w) <= (OTHERS => sosi_out_data(c_data_w-1));
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, (J*c_block_size)+(k*2) , sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+ -- mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, (J*c_block_size)+(k*2)+1, sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+ END LOOP;
+ END LOOP;
+ WAIT FOR c_st_clk_period*1024;
+ WAIT FOR c_st_clk_period*5;
+ END LOOP;
+ WAIT FOR c_mm_clk_period*3000;
tb_end <= '1';
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index a6ed9291ac..37a5457749 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -62,7 +62,7 @@ ENTITY ddrctrl IS
in_sosi_arr : IN t_dp_sosi_arr; -- input data
stop_in : IN STD_LOGIC := '0';
- out_sosi_arr : OUT t_dp_sosi_arr;
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
out_siso : IN t_dp_siso := c_dp_siso_rst;
term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index 1854d3fd14..cfc4dedf5a 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -133,7 +133,6 @@ BEGIN
IF in_sosi.sop = '1' THEN
v.bsn_passed := '1';
END IF;
- v.out_sosi.valid := '0';
END CASE;
--
GitLab