From dfad601e2232315eba8f02fbd6ba5569304b8016 Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Wed, 17 Jan 2024 15:42:42 +0100
Subject: [PATCH] RTSD-181: Added severity error for Agilex7, when two
different clocks are used.
---
libraries/technology/memory/tech_memory_ram_crw_crw.vhd | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index da074de765..2bcc8bcca8 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -1,6 +1,6 @@
-- -----------------------------------------------------------------------------
--
--- Copyright 2014-2023
+-- Copyright 2014-2024
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -58,7 +58,7 @@ entity tech_memory_ram_crw_crw is
address_a : in std_logic_vector(g_adr_w - 1 downto 0);
address_b : in std_logic_vector(g_adr_w - 1 downto 0);
clock_a : in std_logic := '1';
- clock_b : in std_logic;
+ clock_b : in std_logic := '1';
data_a : in std_logic_vector(g_dat_w - 1 downto 0);
data_b : in std_logic_vector(g_dat_w - 1 downto 0);
enable_a : in std_logic := '1';
@@ -110,6 +110,10 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
+ assert not(g_technology = c_tech_agi027_xxxx and clock_a /= clock_b)
+ report "tech_memory_ram_crw_crw, utilizing ip_agi027_xxxx_ram_rw_rw : only supports one clock domain (use clock_b)"
+ severity FAILURE;
+
gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
u0 : ip_agi027_xxxx_ram_rw_rw
generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
@@ -117,3 +121,4 @@ begin
end generate;
end architecture;
+
--
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