diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 09de03e44be8e4fe69f7e5946f481783806e8ebc..42c187ef08556cbf1d5e24583fc83a444bb140f4 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -18,7 +18,7 @@
 --
 -------------------------------------------------------------------------------
 -- Author: Job van Wee
--- Purpose: stopping the data stream into the SDRAM stick.
+-- Purpose: controller for ddrctrl, decides when to write when to read or when to stop writing or reading.
 --
 -- Description:
 --
@@ -63,7 +63,7 @@ END ddrctrl_controller;
 ARCHITECTURE rtl OF ddrctrl_controller IS
 
   CONSTANT  c_burstsize       : NATURAL                                     := 64;                                            -- max burstsize for max troughput
-  CONSTANT  c_bitshift_adr    : NATURAL                                     := ceil_log2(c_burstsize);
+  CONSTANT  c_bitshift_adr    : NATURAL                                     := ceil_log2(c_burstsize);                        -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
   CONSTANT  c_adr_w           : NATURAL                                     := func_tech_ddr_ctlr_address_w( g_tech_ddr );    -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
   CONSTANT  c_max_adr         : NATURAL                                     := 2**(c_adr_w)-1;                                -- the maximal address that is possible within the vector length of the address
   CONSTANT  c_pof_ma          : NATURAL                                     := (c_max_adr*(100-g_stop_percentage))/100;
@@ -101,7 +101,7 @@ BEGIN
   -- put the input data into c_v and fill the output vector from c_v
   p_state : PROCESS(q_reg, rst, out_of, out_sosi, out_adr)
 
-    VARIABLE v                : t_reg;
+    VARIABLE v                : t_reg         := c_t_reg_init;
 
   BEGIN
 
@@ -115,20 +115,20 @@ BEGIN
 
 
     WHEN WRITING =>
-      IF TO_UVEC(out_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN                        -- if adr mod 64 = 0
-        v.dvr_mosi.burstbegin := '1';
+      IF TO_UVEC(out_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN                        -- if adr mod c_burstsize = 0
+        v.dvr_mosi.burstbegin   := '1';
         IF out_adr = 0 THEN
           v.dvr_mosi.address    := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
         ELSE
           v.dvr_mosi.address    := TO_UVEC(out_adr-c_burstsize, dvr_mosi.address'length);
         END IF;
       ELSE
-        v.dvr_mosi.burstbegin := '0';
+        v.dvr_mosi.burstbegin   := '0';
       END IF;
-      v.dvr_mosi.burstsize  := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
-      v.dvr_mosi.wr         := '1';
-      v.dvr_mosi.rd         := '0';
-      v.wr_sosi             := out_sosi;
+      v.dvr_mosi.burstsize      := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
+      v.dvr_mosi.wr             := '1';
+      v.dvr_mosi.rd             := '0';
+      v.wr_sosi                 := out_sosi;