diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
index 955c7a71843cff1ce24a7f1bee58ebd539d888da..3d8876bef741062289b57fb0e393ff70e8bcb436 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
@@ -83,7 +83,8 @@ entity tb_reorder_col_select_all is
g_nof_data_per_block : natural := 3;
g_inter_valid_gap : natural := 0; -- nof clk gap in in_sosi.valid
g_inter_packet_gap : natural := 3; -- nof clk gap betweek in_sosi.eop and next in_sosi.sop
- g_use_complex : boolean := false;
+ g_use_complex : boolean := true;
+ g_use_identity : boolean := true; -- reorder identity or transpose
g_use_dynamic_selection : boolean := false
);
end tb_reorder_col_select_all;
@@ -115,9 +116,12 @@ architecture tb of tb_reorder_col_select_all is
signal clk : std_logic := '1';
signal tb_end : std_logic := '0';
- signal verify_en_sosi : t_dp_sosi_sl;
- signal verify_en_out_sosi : t_dp_sosi_sl;
- signal verify_en_out_sosi_long : t_dp_sosi_sl;
+ signal verify_en_sosi_sl : t_dp_sosi_sl;
+ signal verify_en_out_sosi_sl : t_dp_sosi_sl;
+ signal verify_en_out_sosi_sl_long : t_dp_sosi_sl;
+
+ signal expected_last_sosi : t_dp_sosi := c_dp_sosi_rst;
+ signal expected_last_sosi_evt : t_dp_sosi_sl := c_dp_sosi_sl_rst;
-- Data
signal in_en : std_logic := '1';
@@ -126,7 +130,7 @@ architecture tb of tb_reorder_col_select_all is
signal transposed_sosi : t_dp_sosi;
signal out_sosi : t_dp_sosi;
- -- Reorder control for transpose and undo transpose
+ -- Reorder control for first and second reorder_col_select
signal sel_long : boolean := false;
signal reorder_busy_transposed : std_logic;
signal reorder_busy_output : std_logic;
@@ -141,8 +145,15 @@ architecture tb of tb_reorder_col_select_all is
signal nof_data_per_block_transposed : natural;
signal nof_data_per_block_output : natural;
+ -- Connect reorder identity or reorder transpose, dependent on g_use_identity
+ signal select_copi : t_mem_copi;
+ signal undo_select_copi : t_mem_copi;
signal select_cipo : t_mem_cipo;
signal undo_select_cipo : t_mem_cipo;
+ signal r_identity : t_reorder_identity;
+ signal d_identity : t_reorder_identity;
+ signal r_redo_identity : t_reorder_identity;
+ signal d_redo_identity : t_reorder_identity;
signal r_transpose : t_reorder_transpose;
signal d_transpose : t_reorder_transpose;
signal r_undo_transpose : t_reorder_transpose;
@@ -173,7 +184,8 @@ begin
-- Run some sync intervals with counter data in the packets
-- proc_dp_gen_block_data(
-- constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- -- constant c_use_data : in boolean; -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
+ -- constant c_use_data : in boolean; -- when TRUE use data field, else use re, im fields,
+ -- and keep unused fields at 'X'
-- constant c_data_w : in natural; -- data width for the data, re and im fields
-- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
-- constant c_symbol_init : in natural; -- init counter for symbols in data field
@@ -246,6 +258,20 @@ begin
in_sosi <= c_dp_sosi_rst;
proc_common_wait_some_cycles(clk, c_nof_ch_long * 2);
proc_common_wait_some_cycles(clk, 10);
+
+ -- Pulse event for used sosi fields, to verify that stimuli have been applied
+ expected_last_sosi_evt <= c_dp_sosi_sl_ones;
+ if g_use_complex then
+ expected_last_sosi_evt.data <= '0';
+ else
+ expected_last_sosi_evt.re <= '0';
+ expected_last_sosi_evt.im <= '0';
+ end if;
+ proc_common_wait_some_cycles(clk, 1);
+ expected_last_sosi_evt <= c_dp_sosi_sl_rst;
+
+ -- End of test
+ proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
wait;
end process;
@@ -254,25 +280,42 @@ begin
-- Verification
------------------------------------------------------------------------------
- p_verify_en_sosi : process
+ -- During stimuli verify that values are incrementing
+ p_verify_en_sosi_sl : process
begin
- verify_en_sosi <= c_dp_sosi_sl_rst;
+ verify_en_sosi_sl <= c_dp_sosi_sl_rst;
proc_common_wait_until_low(clk, rst);
-- Verify all sosi fields, except for some
- verify_en_sosi <= c_dp_sosi_sl_ones;
+ verify_en_sosi_sl <= c_dp_sosi_sl_ones;
if g_use_complex then
- verify_en_sosi.data <= '0';
+ verify_en_sosi_sl.data <= '0';
else
- verify_en_sosi.re <= '0';
- verify_en_sosi.im <= '0';
+ verify_en_sosi_sl.re <= '0';
+ verify_en_sosi_sl.im <= '0';
end if;
- verify_en_sosi.empty <= '0';
+ verify_en_sosi_sl.empty <= '0';
wait;
end process;
- verify_en_out_sosi <= verify_en_sosi when sel_long = false else c_dp_sosi_sl_rst;
- verify_en_out_sosi_long <= verify_en_sosi when sel_long = true else c_dp_sosi_sl_rst;
+ verify_en_out_sosi_sl <= verify_en_sosi_sl when sel_long = false else c_dp_sosi_sl_rst;
+ verify_en_out_sosi_sl_long <= verify_en_sosi_sl when sel_long = true else c_dp_sosi_sl_rst;
+
+ -- After stimuli verify last valid values, to check that stimuli have been applied
+ p_expected_last_sosi : process(clk)
+ begin
+ if rising_edge(clk) then
+ if in_sosi.valid = '1' then
+ -- hold last valid sosi.info fields
+ expected_last_sosi <= in_sosi;
+ end if;
+ -- sosi.ctrl fields must have occured at least once
+ expected_last_sosi.valid <= '1';
+ expected_last_sosi.sync <= '1';
+ expected_last_sosi.sop <= '1';
+ expected_last_sosi.eop <= '1';
+ end if;
+ end process;
u_verify_out_sosi : entity dp_lib.dp_stream_verify
generic map (
@@ -289,11 +332,11 @@ begin
-- Verify data
snk_in => out_sosi,
-- During stimuli
- verify_snk_in_enable => verify_en_out_sosi,
+ verify_snk_in_enable => verify_en_out_sosi_sl,
-- End of stimuli
- expected_snk_in => c_dp_sosi_rst,
- verify_expected_snk_in_evt => c_dp_sosi_sl_rst
+ expected_snk_in => expected_last_sosi,
+ verify_expected_snk_in_evt => expected_last_sosi_evt
);
-- When g_use_dynamic_selection = true then c_nof_sync = 2 and second sync interval
@@ -316,28 +359,65 @@ begin
-- Verify data
snk_in => out_sosi,
-- During stimuli
- verify_snk_in_enable => verify_en_out_sosi_long,
+ verify_snk_in_enable => verify_en_out_sosi_sl_long,
-- End of stimuli
- expected_snk_in => c_dp_sosi_rst,
+ expected_snk_in => c_dp_sosi_rst, -- u_verify_out_sosi already does this
verify_expected_snk_in_evt => c_dp_sosi_sl_rst
);
------------------------------------------------------------------------------
- -- DUT
+ -- DUT reorder control for select_copi/select_cipo
------------------------------------------------------------------------------
- p_clk : process(rst, clk)
+ select_copi <= r_identity.select_copi when g_use_identity else r_transpose.select_copi;
+ undo_select_copi <= r_redo_identity.select_copi when g_use_identity else r_undo_transpose.select_copi;
+
+ -- Use synchronous reset in d signals
+ p_clk : process(clk)
begin
- if rst = '1' then
- r_transpose <= c_reorder_transpose_rst;
- r_undo_transpose <= c_reorder_transpose_rst;
- elsif rising_edge(clk) then
+ if rising_edge(clk) then
+ r_identity <= r_identity;
+ r_redo_identity <= d_redo_identity;
r_transpose <= d_transpose;
r_undo_transpose <= d_undo_transpose;
end if;
end process;
+ p_comb_identity : process(rst, select_cipo, nof_ch_input, r_identity)
+ variable v : t_reorder_identity;
+ begin
+ if select_cipo.waitrequest = '0' then
+ -- Read from reorder_col_select page
+ v := func_reorder_identity(nof_ch_input, r_identity);
+ else
+ -- No read, new reorder_col_select page not available yet
+ v := c_reorder_identity_rst;
+ end if;
+ -- Synchronous reset
+ if rst = '1' then
+ v := c_reorder_identity_rst;
+ end if;
+ d_identity <= v;
+ end process;
+
+ p_comb_redo_identity : process(rst, select_cipo, nof_ch_input, r_redo_identity)
+ variable v : t_reorder_identity;
+ begin
+ if select_cipo.waitrequest = '0' then
+ -- Read from reorder_col_select page
+ v := func_reorder_identity(nof_ch_input, r_redo_identity);
+ else
+ -- No read, new reorder_col_select page not available yet
+ v := c_reorder_identity_rst;
+ end if;
+ -- Synchronous reset
+ if rst = '1' then
+ v := c_reorder_identity_rst;
+ end if;
+ d_redo_identity <= v;
+ end process;
+
-- The p_comb_transpose and p_comb_undo_transpose can both use
-- func_reorder_transpose(), by swapping the transpose dimensions.
@@ -346,7 +426,8 @@ begin
nof_data_per_block_input <= g_nof_data_per_block when nof_ch_input = c_nof_ch else
g_nof_data_per_block * c_factor_dat;
- p_comb_transpose : process(rst, r_transpose, select_cipo)
+ p_comb_transpose : process(rst, select_cipo,
+ nof_data_per_block_input, nof_blocks_per_packet_input, r_transpose)
variable v : t_reorder_transpose;
begin
if select_cipo.waitrequest = '0' then
@@ -368,7 +449,8 @@ begin
nof_data_per_block_transposed <= g_nof_data_per_block when nof_ch_transposed = c_nof_ch else
g_nof_data_per_block * c_factor_dat;
- p_comb_undo_transpose : process(rst, r_undo_transpose, undo_select_cipo)
+ p_comb_undo_transpose : process(rst, undo_select_cipo,
+ nof_blocks_per_packet_transposed, nof_data_per_block_transposed, r_undo_transpose)
variable v : t_reorder_transpose;
begin
if undo_select_cipo.waitrequest = '0' then
@@ -390,6 +472,9 @@ begin
nof_data_per_block_output <= g_nof_data_per_block when nof_ch_output = c_nof_ch else
g_nof_data_per_block * c_factor_dat;
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
u_transpose : entity work.reorder_col_select
generic map (
g_dsp_data_w => g_dsp_data_w,
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
index bd66fd81f0cd9f3021c662a50fce8ed3cb750816..442bf28f0142a4398412c0ba0a7d78f03f351f05 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
@@ -45,16 +45,19 @@ begin
-- g_inter_valid_gap : natural := 5; -- nof clk gap in in_sosi.valid
-- g_inter_packet_gap : natural := 0; -- nof clk gap between in_sosi.eop and next in_sosi.sop
-- g_use_complex : boolean := false;
+-- g_use_identity : boolean := false; -- reorder identity or transpose
-- g_use_dynamic_selection : boolean := true
- u_complex_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 2, 5, 3, 0, 0, true, false);
- u_data_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3, 0, 0, false, false);
- u_data_5_1_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 4, 5, 1, 0, 0, false, false);
- u_data_1_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 5, 1, 3, 0, 0, false, false);
- u_data_3_5_pkt_gap_1 : entity work.tb_reorder_col_select_all generic map(16, 3, 6, 3, 5, 0, 1, false, false);
- u_data_3_5_valid_gap_1 : entity work.tb_reorder_col_select_all generic map(16, 3, 6, 3, 5, 1, 0, false, false);
+ u_data_5_3_no_gaps_identity : entity work.tb_reorder_col_select_all generic map(16, 3, 2, 5, 3, 0, 0, false, true, false);
- u_dynamic_data_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3, 0, 0, false, true);
- u_dynamic_data_5_3_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3,10,100, false, true);
+ u_complex_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 2, 5, 3, 0, 0, true, false, false);
+ u_data_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3, 0, 0, false, false, false);
+ u_data_5_1_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 4, 5, 1, 0, 0, false, false, false);
+ u_data_1_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 5, 1, 3, 0, 0, false, false, false);
+ u_data_3_5_pkt_gap_1 : entity work.tb_reorder_col_select_all generic map(16, 3, 6, 3, 5, 0, 1, false, false, false);
+ u_data_3_5_valid_gap_1 : entity work.tb_reorder_col_select_all generic map(16, 3, 6, 3, 5, 1, 0, false, false, false);
+
+ u_dynamic_data_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3, 0, 0, false, false, true);
+ u_dynamic_data_5_3_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3,10,100, false, false, true);
end tb;