From df3172be1bbcd9763ae64b545c058d9f7be5ebd1 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Fri, 25 Jun 2021 14:53:37 +0200
Subject: [PATCH] merged the two beamset IPs to 1 in qsys
---
.../qsys_lofar2_unb2b_sdp_station_cpu_0.ip | 4 +-
..._unb2b_sdp_station_reg_stat_enable_bst.ip} | 48 +-
...unb2b_sdp_station_reg_stat_enable_bst_1.ip | 1439 ----------
...unb2b_sdp_station_reg_stat_hdr_dat_bst.ip} | 26 +-
...nb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip | 1447 ----------
.../qsys_lofar2_unb2b_sdp_station.qsys | 2362 ++++-------------
.../lofar2_unb2b_sdp_station_adc/hdllib.cfg | 6 +-
.../lofar2_unb2b_sdp_station_bf/hdllib.cfg | 6 +-
.../lofar2_unb2b_sdp_station_fsub/hdllib.cfg | 6 +-
.../hdllib.cfg | 6 +-
10 files changed, 548 insertions(+), 4802 deletions(-)
rename applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/{qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip => qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip} (97%)
delete mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
rename applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/{qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip => qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip} (98%)
delete mode 100644 applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index 1954ada2da..bafd22679a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4060' end='0xB4068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xB4068' end='0xB4070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_wg.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x36C0' end='0x36E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x36E0' end='0x3700' datawidth='32' /><slave name='reg_epcs.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_remu.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3740' end='0x3750' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3750' end='0x3760' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3760' end='0x3770' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0x3770' end='0x3778' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x3778' end='0x3780' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3780' end='0x3788' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3788' end='0x3790' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3790' end='0x3798' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3798' end='0x37A0' datawidth='32' /><slave name='reg_si.mem' start='0x37A0' end='0x37A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37A8' end='0x37B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x37B0' end='0x37B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x37B8' end='0x37C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='pio_pps.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4060' end='0xB4068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xB4068' end='0xB4070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_wg.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x36C0' end='0x36E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x36E0' end='0x3700' datawidth='32' /><slave name='reg_epcs.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_remu.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3740' end='0x3750' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3750' end='0x3760' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3760' end='0x3770' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0x3770' end='0x3778' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x3778' end='0x3780' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3780' end='0x3788' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3788' end='0x3790' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3790' end='0x3798' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3798' end='0x37A0' datawidth='32' /><slave name='reg_si.mem' start='0x37A0' end='0x37A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37A8' end='0x37B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x37B0' end='0x37B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x37B8' end='0x37C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='pio_pps.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
index abb238885c..fb9f5c754e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,6 +605,10 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>1</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -697,6 +701,10 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>1</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -766,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -775,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -838,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -902,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -971,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1366,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1398,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
deleted file mode 100644
index e4500ca3d6..0000000000
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+++ /dev/null
@@ -1,1439 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>address</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_address_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_clk_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>mem</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>address</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_address</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>write</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_write</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>writedata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_writedata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>read</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_read</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>readdata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_readdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>addressAlignment</spirit:name>
- <spirit:displayName>Slave addressing</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressGroup</spirit:name>
- <spirit:displayName>Address group</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressSpan</spirit:name>
- <spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressUnits</spirit:name>
- <spirit:displayName>Address units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>alwaysBurstMaxBurst</spirit:name>
- <spirit:displayName>Always burst maximum burst</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>Associated reset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bitsPerSymbol</spirit:name>
- <spirit:displayName>Bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgedAddressOffset</spirit:name>
- <spirit:displayName>Bridged Address Offset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgesToMaster</spirit:name>
- <spirit:displayName>Bridges to master</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
- <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstcountUnits</spirit:name>
- <spirit:displayName>Burstcount units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>constantBurstBehavior</spirit:name>
- <spirit:displayName>Constant burst behavior</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>explicitAddressSpan</spirit:name>
- <spirit:displayName>Explicit address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>holdTime</spirit:name>
- <spirit:displayName>Hold</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>interleaveBursts</spirit:name>
- <spirit:displayName>Interleave bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isBigEndian</spirit:name>
- <spirit:displayName>Big endian</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isFlash</spirit:name>
- <spirit:displayName>Flash memory</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isMemoryDevice</spirit:name>
- <spirit:displayName>Memory device</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isNonVolatileStorage</spirit:name>
- <spirit:displayName>Non-volatile storage</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>linewrapBursts</spirit:name>
- <spirit:displayName>Linewrap bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingReadTransactions</spirit:name>
- <spirit:displayName>Maximum pending read transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingWriteTransactions</spirit:name>
- <spirit:displayName>Maximum pending write transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumReadLatency</spirit:name>
- <spirit:displayName>minimumReadLatency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumResponseLatency</spirit:name>
- <spirit:displayName>Minimum response latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumUninterruptedRunLength</spirit:name>
- <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>printableDevice</spirit:name>
- <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readLatency</spirit:name>
- <spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitStates</spirit:name>
- <spirit:displayName>Read wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitTime</spirit:name>
- <spirit:displayName>Read wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerIncomingSignals</spirit:name>
- <spirit:displayName>Register incoming signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerOutgoingSignals</spirit:name>
- <spirit:displayName>Register outgoing signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>setupTime</spirit:name>
- <spirit:displayName>Setup</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>timingUnits</spirit:name>
- <spirit:displayName>Timing units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>transparentBridge</spirit:name>
- <spirit:displayName>Transparent bridge</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>waitrequestAllowance</spirit:name>
- <spirit:displayName>Waitrequest allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>wellBehavedWaitrequest</spirit:name>
- <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeLatency</spirit:name>
- <spirit:displayName>Write latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitStates</spirit:name>
- <spirit:displayName>Write wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitTime</spirit:name>
- <spirit:displayName>Write wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>read</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_read_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>readdata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_readdata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_reset_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>write</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_write_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>writedata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_writedata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>csi_system_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>csi_system_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_write</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_writedata</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_read</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_readdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_reset_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_clk_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_address_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_write_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_writedata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_read_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_readdata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:library>
- <spirit:name>avs_common_mm</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>g_adr_w</spirit:name>
- <spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>g_dat_w</spirit:name>
- <spirit:displayName>g_dat_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
- <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>generationId</spirit:name>
- <spirit:displayName>Generation Id</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>3</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
index 3c0b3d0ae7..df0fabd51f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
deleted file mode 100644
index 1ae732e8c7..0000000000
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+++ /dev/null
@@ -1,1447 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>address</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_address_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_clk_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>mem</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>address</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_address</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>write</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_write</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>writedata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_writedata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>read</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_read</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>readdata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_readdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>addressAlignment</spirit:name>
- <spirit:displayName>Slave addressing</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressGroup</spirit:name>
- <spirit:displayName>Address group</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressSpan</spirit:name>
- <spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressUnits</spirit:name>
- <spirit:displayName>Address units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>alwaysBurstMaxBurst</spirit:name>
- <spirit:displayName>Always burst maximum burst</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>Associated reset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bitsPerSymbol</spirit:name>
- <spirit:displayName>Bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgedAddressOffset</spirit:name>
- <spirit:displayName>Bridged Address Offset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgesToMaster</spirit:name>
- <spirit:displayName>Bridges to master</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
- <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstcountUnits</spirit:name>
- <spirit:displayName>Burstcount units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>constantBurstBehavior</spirit:name>
- <spirit:displayName>Constant burst behavior</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>explicitAddressSpan</spirit:name>
- <spirit:displayName>Explicit address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>holdTime</spirit:name>
- <spirit:displayName>Hold</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>interleaveBursts</spirit:name>
- <spirit:displayName>Interleave bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isBigEndian</spirit:name>
- <spirit:displayName>Big endian</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isFlash</spirit:name>
- <spirit:displayName>Flash memory</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isMemoryDevice</spirit:name>
- <spirit:displayName>Memory device</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isNonVolatileStorage</spirit:name>
- <spirit:displayName>Non-volatile storage</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>linewrapBursts</spirit:name>
- <spirit:displayName>Linewrap bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingReadTransactions</spirit:name>
- <spirit:displayName>Maximum pending read transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingWriteTransactions</spirit:name>
- <spirit:displayName>Maximum pending write transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumReadLatency</spirit:name>
- <spirit:displayName>minimumReadLatency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumResponseLatency</spirit:name>
- <spirit:displayName>Minimum response latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumUninterruptedRunLength</spirit:name>
- <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>printableDevice</spirit:name>
- <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readLatency</spirit:name>
- <spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitStates</spirit:name>
- <spirit:displayName>Read wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitTime</spirit:name>
- <spirit:displayName>Read wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerIncomingSignals</spirit:name>
- <spirit:displayName>Register incoming signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerOutgoingSignals</spirit:name>
- <spirit:displayName>Register outgoing signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>setupTime</spirit:name>
- <spirit:displayName>Setup</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>timingUnits</spirit:name>
- <spirit:displayName>Timing units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>transparentBridge</spirit:name>
- <spirit:displayName>Transparent bridge</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>waitrequestAllowance</spirit:name>
- <spirit:displayName>Waitrequest allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>wellBehavedWaitrequest</spirit:name>
- <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeLatency</spirit:name>
- <spirit:displayName>Write latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitStates</spirit:name>
- <spirit:displayName>Write wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitTime</spirit:name>
- <spirit:displayName>Write wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>read</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_read_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>readdata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_readdata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_reset_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>write</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_write_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>writedata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_writedata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>csi_system_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>csi_system_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>5</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_write</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_writedata</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_read</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_readdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_reset_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_clk_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_address_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>5</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_write_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_writedata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_read_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_readdata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:library>
- <spirit:name>avs_common_mm</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>g_adr_w</spirit:name>
- <spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>g_dat_w</spirit:name>
- <spirit:displayName>g_dat_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
- <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>generationId</spirit:name>
- <spirit:displayName>Generation Id</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>6</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>6</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>256</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>8</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index be5dfd5d03..dc5e68ef49 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "737488";
+ value = "14288";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "737408";
+ value = "14208";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "737480";
+ value = "14280";
type = "String";
}
}
@@ -338,7 +338,7 @@
{
datum _sortIndex
{
- value = "56";
+ value = "54";
type = "int";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "13312";
+ value = "13056";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "737360";
+ value = "14176";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "737432";
+ value = "14232";
type = "String";
}
}
@@ -434,7 +434,7 @@
{
datum _sortIndex
{
- value = "55";
+ value = "53";
type = "int";
}
}
@@ -458,7 +458,7 @@
{
datum baseAddress
{
- value = "14272";
+ value = "14016";
type = "String";
}
}
@@ -466,7 +466,7 @@
{
datum _sortIndex
{
- value = "54";
+ value = "52";
type = "int";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "14080";
+ value = "13824";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "737424";
+ value = "14224";
type = "String";
}
}
@@ -530,7 +530,7 @@
{
datum _sortIndex
{
- value = "53";
+ value = "51";
type = "int";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "737376";
+ value = "14192";
type = "String";
}
}
@@ -554,7 +554,7 @@
{
datum baseAddress
{
- value = "737344";
+ value = "14160";
type = "String";
}
}
@@ -575,7 +575,7 @@
{
datum baseAddress
{
- value = "737472";
+ value = "14272";
type = "String";
}
}
@@ -596,7 +596,7 @@
{
datum baseAddress
{
- value = "737464";
+ value = "14264";
type = "String";
}
}
@@ -617,7 +617,7 @@
{
datum baseAddress
{
- value = "737280";
+ value = "14080";
type = "String";
}
}
@@ -633,7 +633,7 @@
{
datum baseAddress
{
- value = "14304";
+ value = "14048";
type = "String";
}
}
@@ -654,7 +654,7 @@
{
datum baseAddress
{
- value = "14208";
+ value = "13952";
type = "String";
}
}
@@ -691,7 +691,7 @@
{
datum baseAddress
{
- value = "737456";
+ value = "14256";
type = "String";
}
}
@@ -712,7 +712,7 @@
{
datum baseAddress
{
- value = "737448";
+ value = "14248";
type = "String";
}
}
@@ -728,7 +728,7 @@
{
datum baseAddress
{
- value = "737416";
+ value = "14216";
type = "String";
}
}
@@ -765,7 +765,7 @@
{
datum baseAddress
{
- value = "737312";
+ value = "14112";
type = "String";
}
}
@@ -781,7 +781,7 @@
{
datum baseAddress
{
- value = "14144";
+ value = "13888";
type = "String";
}
}
@@ -797,11 +797,11 @@
{
datum baseAddress
{
- value = "737440";
+ value = "14240";
type = "String";
}
}
- element reg_stat_enable_bst_0
+ element reg_stat_enable_bst
{
datum _sortIndex
{
@@ -809,27 +809,11 @@
type = "int";
}
}
- element reg_stat_enable_bst_0.mem
+ element reg_stat_enable_bst.mem
{
datum baseAddress
{
- value = "737392";
- type = "String";
- }
- }
- element reg_stat_enable_bst_1
- {
- datum _sortIndex
- {
- value = "51";
- type = "int";
- }
- }
- element reg_stat_enable_bst_1.mem
- {
- datum baseAddress
- {
- value = "737384";
+ value = "14144";
type = "String";
}
}
@@ -845,11 +829,11 @@
{
datum baseAddress
{
- value = "737400";
+ value = "14200";
type = "String";
}
}
- element reg_stat_hdr_dat_bst_0
+ element reg_stat_hdr_dat_bst
{
datum _sortIndex
{
@@ -857,7 +841,7 @@
type = "int";
}
}
- element reg_stat_hdr_dat_bst_0.mem
+ element reg_stat_hdr_dat_bst.mem
{
datum baseAddress
{
@@ -865,22 +849,6 @@
type = "String";
}
}
- element reg_stat_hdr_dat_bst_1
- {
- datum _sortIndex
- {
- value = "52";
- type = "int";
- }
- }
- element reg_stat_hdr_dat_bst_1.mem
- {
- datum baseAddress
- {
- value = "12544";
- type = "String";
- }
- }
element reg_stat_hdr_dat_sst
{
datum _sortIndex
@@ -893,7 +861,7 @@
{
datum baseAddress
{
- value = "12800";
+ value = "12544";
type = "String";
}
}
@@ -909,7 +877,7 @@
{
datum baseAddress
{
- value = "13568";
+ value = "13312";
type = "String";
}
}
@@ -925,7 +893,7 @@
{
datum baseAddress
{
- value = "13824";
+ value = "13568";
type = "String";
}
}
@@ -967,7 +935,7 @@
{
datum baseAddress
{
- value = "13056";
+ value = "12800";
type = "String";
}
}
@@ -2477,73 +2445,38 @@
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_0_address"
- internal="reg_stat_enable_bst_0.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_clk"
- internal="reg_stat_enable_bst_0.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_read"
- internal="reg_stat_enable_bst_0.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_readdata"
- internal="reg_stat_enable_bst_0.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_reset"
- internal="reg_stat_enable_bst_0.reset"
+ name="reg_stat_enable_bst_address"
+ internal="reg_stat_enable_bst.address"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_0_write"
- internal="reg_stat_enable_bst_0.write"
+ name="reg_stat_enable_bst_clk"
+ internal="reg_stat_enable_bst.clk"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_0_writedata"
- internal="reg_stat_enable_bst_0.writedata"
+ name="reg_stat_enable_bst_read"
+ internal="reg_stat_enable_bst.read"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_address"
- internal="reg_stat_enable_bst_1.address"
+ name="reg_stat_enable_bst_readdata"
+ internal="reg_stat_enable_bst.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_clk"
- internal="reg_stat_enable_bst_1.clk"
+ name="reg_stat_enable_bst_reset"
+ internal="reg_stat_enable_bst.reset"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_read"
- internal="reg_stat_enable_bst_1.read"
+ name="reg_stat_enable_bst_write"
+ internal="reg_stat_enable_bst.write"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_readdata"
- internal="reg_stat_enable_bst_1.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_1_reset"
- internal="reg_stat_enable_bst_1.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_1_write"
- internal="reg_stat_enable_bst_1.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_1_writedata"
- internal="reg_stat_enable_bst_1.writedata"
+ name="reg_stat_enable_bst_writedata"
+ internal="reg_stat_enable_bst.writedata"
type="conduit"
dir="end" />
<interface
@@ -2582,73 +2515,38 @@
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_0_address"
- internal="reg_stat_hdr_dat_bst_0.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_clk"
- internal="reg_stat_hdr_dat_bst_0.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_read"
- internal="reg_stat_hdr_dat_bst_0.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_readdata"
- internal="reg_stat_hdr_dat_bst_0.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_reset"
- internal="reg_stat_hdr_dat_bst_0.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_write"
- internal="reg_stat_hdr_dat_bst_0.write"
+ name="reg_stat_hdr_dat_bst_address"
+ internal="reg_stat_hdr_dat_bst.address"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_0_writedata"
- internal="reg_stat_hdr_dat_bst_0.writedata"
+ name="reg_stat_hdr_dat_bst_clk"
+ internal="reg_stat_hdr_dat_bst.clk"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_address"
- internal="reg_stat_hdr_dat_bst_1.address"
+ name="reg_stat_hdr_dat_bst_read"
+ internal="reg_stat_hdr_dat_bst.read"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_clk"
- internal="reg_stat_hdr_dat_bst_1.clk"
+ name="reg_stat_hdr_dat_bst_readdata"
+ internal="reg_stat_hdr_dat_bst.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_read"
- internal="reg_stat_hdr_dat_bst_1.read"
+ name="reg_stat_hdr_dat_bst_reset"
+ internal="reg_stat_hdr_dat_bst.reset"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_readdata"
- internal="reg_stat_hdr_dat_bst_1.readdata"
+ name="reg_stat_hdr_dat_bst_write"
+ internal="reg_stat_hdr_dat_bst.write"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_reset"
- internal="reg_stat_hdr_dat_bst_1.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_1_write"
- internal="reg_stat_hdr_dat_bst_1.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_1_writedata"
- internal="reg_stat_hdr_dat_bst_1.writedata"
+ name="reg_stat_hdr_dat_bst_writedata"
+ internal="reg_stat_hdr_dat_bst.writedata"
type="conduit"
dir="end" />
<interface
@@ -5805,7 +5703,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4060' end='0xB4068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xB4068' end='0xB4070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_wg.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x36C0' end='0x36E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x36E0' end='0x3700' datawidth='32' /><slave name='reg_epcs.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_remu.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3740' end='0x3750' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3750' end='0x3760' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3760' end='0x3770' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0x3770' end='0x3778' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x3778' end='0x3780' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3780' end='0x3788' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3788' end='0x3790' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3790' end='0x3798' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3798' end='0x37A0' datawidth='32' /><slave name='reg_si.mem' start='0x37A0' end='0x37A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37A8' end='0x37B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x37B0' end='0x37B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x37B8' end='0x37C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='pio_pps.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -15190,1269 +15088,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="ram_st_xsq"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>65536</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>16</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="ram_wg"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>14</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>65536</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>16</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="ram_st_xsq"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16468,7 +15134,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16532,7 +15198,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16601,7 +15267,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17007,11 +15673,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17038,37 +15704,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17084,7 +15750,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17148,7 +15814,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17217,7 +15883,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17623,11 +16289,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17654,37 +16320,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17700,7 +16366,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17764,7 +16430,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17833,7 +16499,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18239,11 +16905,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18270,37 +16936,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18316,7 +16982,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18380,7 +17046,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18449,7 +17115,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18855,11 +17521,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18886,37 +17552,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler_xsub"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18932,7 +17598,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18996,7 +17662,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19065,7 +17731,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19471,11 +18137,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19502,37 +18168,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source_v2"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19548,7 +18214,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19612,7 +18278,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19681,7 +18347,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20087,11 +18753,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20118,37 +18784,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_crosslets_info"
+ name="reg_bsn_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20164,7 +18830,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20228,7 +18894,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20297,7 +18963,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20703,11 +19369,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20734,37 +19400,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_bsn_source_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20780,7 +19446,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20844,7 +19510,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20913,7 +19579,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21319,11 +19985,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21350,37 +20016,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21396,7 +20062,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21460,7 +20126,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21529,7 +20195,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21935,11 +20601,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21966,37 +20632,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22582,37 +21248,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_sync_insert_v2"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23198,37 +21864,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_xonoff"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23244,7 +21910,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23308,7 +21974,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23377,7 +22043,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23783,11 +22449,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23814,37 +22480,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_dp_sync_insert_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24430,37 +23096,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_dp_xonoff"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24476,7 +23142,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24540,7 +23206,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24609,7 +23275,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25015,11 +23681,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25046,37 +23712,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25092,7 +23758,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25156,7 +23822,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25225,7 +23891,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25631,11 +24297,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25662,37 +24328,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25708,7 +24374,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25772,7 +24438,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25841,7 +24507,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26247,11 +24913,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26278,37 +24944,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26324,7 +24990,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26388,7 +25054,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26457,7 +25123,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26863,11 +25529,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26894,37 +25560,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_hdr_dat"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26940,7 +25606,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27004,7 +25670,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27073,7 +25739,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27479,11 +26145,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27510,37 +26176,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27556,7 +26222,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27620,7 +26286,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27689,7 +26355,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28095,11 +26761,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28126,37 +26792,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28172,7 +26838,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28236,7 +26902,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28305,7 +26971,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28711,11 +27377,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28742,37 +27408,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29358,37 +28024,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29404,7 +28070,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29468,7 +28134,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29537,7 +28203,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29943,11 +28609,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29974,37 +28640,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30020,7 +28686,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30084,7 +28750,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30153,7 +28819,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30559,11 +29225,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30590,37 +29256,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30636,7 +29302,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30700,7 +29366,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30769,7 +29435,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31175,11 +29841,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31206,37 +29872,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31252,7 +29918,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31316,7 +29982,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31385,7 +30051,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31791,11 +30457,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31822,37 +30488,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst_0"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31868,7 +30534,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31932,7 +30598,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32001,7 +30667,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32407,11 +31073,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32438,37 +31104,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst_1"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33054,37 +31720,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_sst"
+ name="reg_stat_enable_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33100,7 +31766,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33164,7 +31830,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33233,7 +31899,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33639,11 +32305,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33670,37 +32336,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst_0"
+ name="reg_stat_enable_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33716,7 +32382,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33780,7 +32446,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33849,7 +32515,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34255,11 +32921,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34286,37 +32952,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst_1"
+ name="reg_stat_hdr_dat_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34902,30 +33568,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -39356,7 +38022,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x000b40d0" />
+ <parameter name="baseAddress" value="0x37d0" />
</connection>
<connection
kind="avalon"
@@ -39370,7 +38036,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x3600" />
+ <parameter name="baseAddress" value="0x3500" />
</connection>
<connection
kind="avalon"
@@ -39391,7 +38057,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x000b40c8" />
+ <parameter name="baseAddress" value="0x37c8" />
</connection>
<connection
kind="avalon"
@@ -39405,63 +38071,63 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x000b4020" />
+ <parameter name="baseAddress" value="0x3720" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x000b4000" />
+ <parameter name="baseAddress" value="0x3700" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x000b40c0" />
+ <parameter name="baseAddress" value="0x37c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x000b40b8" />
+ <parameter name="baseAddress" value="0x37b8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x000b40b0" />
+ <parameter name="baseAddress" value="0x37b0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x000b40a8" />
+ <parameter name="baseAddress" value="0x37a8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x37e0" />
+ <parameter name="baseAddress" value="0x36e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="baseAddress" value="0x3500" />
+ <parameter name="baseAddress" value="0x3400" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x3780" />
+ <parameter name="baseAddress" value="0x3680" />
</connection>
<connection
kind="avalon"
@@ -39475,7 +38141,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x000b40a0" />
+ <parameter name="baseAddress" value="0x37a0" />
</connection>
<connection
kind="avalon"
@@ -39496,7 +38162,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x3300" />
</connection>
<connection
kind="avalon"
@@ -39517,21 +38183,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x000b4098" />
+ <parameter name="baseAddress" value="0x3798" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x37c0" />
+ <parameter name="baseAddress" value="0x36c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x3300" />
+ <parameter name="baseAddress" value="0x3200" />
</connection>
<connection
kind="avalon"
@@ -39552,7 +38218,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x000b4090" />
+ <parameter name="baseAddress" value="0x3790" />
</connection>
<connection
kind="avalon"
@@ -39580,7 +38246,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x000b4050" />
+ <parameter name="baseAddress" value="0x3760" />
</connection>
<connection
kind="avalon"
@@ -39594,7 +38260,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x000b4040" />
+ <parameter name="baseAddress" value="0x3750" />
</connection>
<connection
kind="avalon"
@@ -39608,14 +38274,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x3740" />
+ <parameter name="baseAddress" value="0x3640" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x000b4088" />
+ <parameter name="baseAddress" value="0x3788" />
</connection>
<connection
kind="avalon"
@@ -39643,48 +38309,34 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x000b4080" />
+ <parameter name="baseAddress" value="0x3780" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x000b4078" />
+ <parameter name="baseAddress" value="0x3778" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_hdr_dat_sst.mem">
- <parameter name="baseAddress" value="0x3200" />
- </connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_stat_enable_bst_0.mem">
- <parameter name="baseAddress" value="0x000b4070" />
- </connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_stat_enable_bst_1.mem">
- <parameter name="baseAddress" value="0x000b4068" />
+ <parameter name="baseAddress" value="0x3100" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_stat_hdr_dat_bst_1.mem">
- <parameter name="baseAddress" value="0x3100" />
+ end="reg_stat_enable_bst.mem">
+ <parameter name="baseAddress" value="0x3740" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_stat_hdr_dat_bst_0.mem">
+ end="reg_stat_hdr_dat_bst.mem">
<parameter name="baseAddress" value="0x0100" />
</connection>
<connection
@@ -39692,14 +38344,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_sync_insert_v2.mem">
- <parameter name="baseAddress" value="0x000b4060" />
+ <parameter name="baseAddress" value="0x3770" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x3700" />
+ <parameter name="baseAddress" value="0x3600" />
</connection>
<connection
kind="avalon"
@@ -39951,22 +38603,12 @@
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_enable_bst_0.system" />
+ end="reg_stat_enable_bst.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_enable_bst_1.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="reg_stat_hdr_dat_bst_1.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="reg_stat_hdr_dat_bst_0.system" />
+ end="reg_stat_hdr_dat_bst.system" />
<connection
kind="clock"
version="18.0"
@@ -40238,22 +38880,12 @@
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_enable_bst_0.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="reg_stat_enable_bst_1.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="reg_stat_hdr_dat_bst_1.system_reset" />
+ end="reg_stat_enable_bst.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_hdr_dat_bst_0.system_reset" />
+ end="reg_stat_hdr_dat_bst.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index a337fbca79..54408a457f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -87,11 +87,9 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 7fe9ef99dd..e709996fce 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -95,11 +95,9 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index 27cbd50c68..7f5f837821 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -94,11 +94,9 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index cac284c1d9..d91b50b605 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -92,11 +92,9 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
--
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