From df21a625b1d7cd30286fc163e0f2366762e5740b Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Wed, 8 Apr 2015 11:31:38 +0000
Subject: [PATCH] -Using the *full* (including MSbit) range of FIFO used words
to trigger FIFO readout. As the MSbit was missing, usedw would wrap from 127
to 0 (instead of indicating 128) which caused the FIFO to no longer be read
out and overflowing under cetain circumstances (gaps in the data = no valid
signal to trigger FIFO readout while the adder+fifo registers still output 4
valid words after fifo src_in.ready goining down).
---
.../dsp/correlator/src/vhdl/corr_accumulator.vhd | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index 4b8bbe55d4..1f254351ab 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -67,8 +67,12 @@ ARCHITECTURE str OF corr_accumulator IS
SIGNAL nxt_corr_adder_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs-1 DOWNTO 0); -- Array of pairs
SIGNAL corr_adder_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
- TYPE t_dp_fifo_sc_usedw_arr IS ARRAY(g_nof_inputs-1 DOWNTO 0) OF STD_LOGIC_VECTOR(ceil_log2(g_nof_accumulators)-1 DOWNTO 0);
+ TYPE t_dp_fifo_sc_usedw_arr IS ARRAY(g_nof_inputs-1 DOWNTO 0) OF STD_LOGIC_VECTOR(ceil_log2(g_nof_accumulators)-1 DOWNTO 0);
+ TYPE t_dp_fifo_sc_used_words_arr IS ARRAY(g_nof_inputs-1 DOWNTO 0) OF STD_LOGIC_VECTOR(ceil_log2(g_nof_accumulators) DOWNTO 0);
SIGNAL dp_fifo_sc_usedw_arr : t_dp_fifo_sc_usedw_arr;
+ SIGNAL dp_fifo_sc_used_words_arr : t_dp_fifo_sc_used_words_arr;
+ SIGNAL dp_fifo_sc_wr_ful_arr : STD_LOGIC_VECTOR(g_nof_inputs-1 DOWNTO 0);
+
SIGNAL dp_fifo_sc_src_in_arr : t_dp_siso_arr(g_nof_inputs-1 DOWNTO 0);
SIGNAL dp_fifo_sc_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
@@ -138,17 +142,21 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
-
+
+ wr_ful => dp_fifo_sc_wr_ful_arr(i),
usedw => dp_fifo_sc_usedw_arr(i),
snk_in => corr_adder_src_out_arr(i),
src_in => dp_fifo_sc_src_in_arr(i),
src_out => dp_fifo_sc_src_out_arr(i)
);
+
+ -- The FIFO does not output the MSbit in its usedw output; it is output as wr_ful. Restore the full number of words here.
+ dp_fifo_sc_used_words_arr(i) <= dp_fifo_sc_wr_ful_arr(i) & dp_fifo_sc_usedw_arr(i);
-- Shift out the first accumulated value when it aligns with the corresponding current value at the adder input
-- . this produces the dp_fifo_sc_src_out_arr data in sync with reg_snk_in_arr data
- dp_fifo_sc_src_in_arr(i).ready <= snk_in_arr(i).valid WHEN TO_UINT(dp_fifo_sc_usedw_arr(i))>=g_nof_accumulators-1-c_adder_latency-c_fifo_latency-1 ELSE '0';
+ dp_fifo_sc_src_in_arr(i).ready <= snk_in_arr(i).valid WHEN TO_UINT(dp_fifo_sc_used_words_arr(i))>=g_nof_accumulators-c_adder_latency-c_fifo_latency-1 ELSE '0';
END GENERATE;
--
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